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Emilio Lópeze874a662013-02-25 11:44:26 -03001/*
2 * Copyright 2013 Emilio López
3 *
4 * Emilio López <emilio@elopez.com.ar>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 */
16
17#include <linux/clk-provider.h>
18#include <linux/clkdev.h>
Emilio Lópeze874a662013-02-25 11:44:26 -030019#include <linux/of.h>
20#include <linux/of_address.h>
Hans de Goedecfb00862014-02-07 16:21:49 +010021#include <linux/reset-controller.h>
Maxime Ripard601da9d2014-07-04 22:24:52 +020022#include <linux/spinlock.h>
Chen-Yu Tsai7954dfa2014-11-26 15:16:52 +080023#include <linux/log2.h>
Emilio Lópeze874a662013-02-25 11:44:26 -030024
25#include "clk-factors.h"
26
27static DEFINE_SPINLOCK(clk_lock);
28
Chen-Yu Tsai7954dfa2014-11-26 15:16:52 +080029/**
30 * sun6i_a31_ahb1_clk_setup() - Setup function for a31 ahb1 composite clk
31 */
32
33#define SUN6I_AHB1_MAX_PARENTS 4
34#define SUN6I_AHB1_MUX_PARENT_PLL6 3
35#define SUN6I_AHB1_MUX_SHIFT 12
36/* un-shifted mask is what mux_clk expects */
37#define SUN6I_AHB1_MUX_MASK 0x3
38#define SUN6I_AHB1_MUX_GET_PARENT(reg) ((reg >> SUN6I_AHB1_MUX_SHIFT) & \
39 SUN6I_AHB1_MUX_MASK)
40
41#define SUN6I_AHB1_DIV_SHIFT 4
42#define SUN6I_AHB1_DIV_MASK (0x3 << SUN6I_AHB1_DIV_SHIFT)
43#define SUN6I_AHB1_DIV_GET(reg) ((reg & SUN6I_AHB1_DIV_MASK) >> \
44 SUN6I_AHB1_DIV_SHIFT)
45#define SUN6I_AHB1_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_DIV_MASK) | \
46 (div << SUN6I_AHB1_DIV_SHIFT))
47#define SUN6I_AHB1_PLL6_DIV_SHIFT 6
48#define SUN6I_AHB1_PLL6_DIV_MASK (0x3 << SUN6I_AHB1_PLL6_DIV_SHIFT)
49#define SUN6I_AHB1_PLL6_DIV_GET(reg) ((reg & SUN6I_AHB1_PLL6_DIV_MASK) >> \
50 SUN6I_AHB1_PLL6_DIV_SHIFT)
51#define SUN6I_AHB1_PLL6_DIV_SET(reg, div) ((reg & ~SUN6I_AHB1_PLL6_DIV_MASK) | \
52 (div << SUN6I_AHB1_PLL6_DIV_SHIFT))
53
54struct sun6i_ahb1_clk {
55 struct clk_hw hw;
56 void __iomem *reg;
57};
58
59#define to_sun6i_ahb1_clk(_hw) container_of(_hw, struct sun6i_ahb1_clk, hw)
60
61static unsigned long sun6i_ahb1_clk_recalc_rate(struct clk_hw *hw,
62 unsigned long parent_rate)
63{
64 struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
65 unsigned long rate;
66 u32 reg;
67
68 /* Fetch the register value */
69 reg = readl(ahb1->reg);
70
71 /* apply pre-divider first if parent is pll6 */
72 if (SUN6I_AHB1_MUX_GET_PARENT(reg) == SUN6I_AHB1_MUX_PARENT_PLL6)
73 parent_rate /= SUN6I_AHB1_PLL6_DIV_GET(reg) + 1;
74
75 /* clk divider */
76 rate = parent_rate >> SUN6I_AHB1_DIV_GET(reg);
77
78 return rate;
79}
80
81static long sun6i_ahb1_clk_round(unsigned long rate, u8 *divp, u8 *pre_divp,
82 u8 parent, unsigned long parent_rate)
83{
84 u8 div, calcp, calcm = 1;
85
86 /*
87 * clock can only divide, so we will never be able to achieve
88 * frequencies higher than the parent frequency
89 */
90 if (parent_rate && rate > parent_rate)
91 rate = parent_rate;
92
93 div = DIV_ROUND_UP(parent_rate, rate);
94
95 /* calculate pre-divider if parent is pll6 */
96 if (parent == SUN6I_AHB1_MUX_PARENT_PLL6) {
97 if (div < 4)
98 calcp = 0;
99 else if (div / 2 < 4)
100 calcp = 1;
101 else if (div / 4 < 4)
102 calcp = 2;
103 else
104 calcp = 3;
105
106 calcm = DIV_ROUND_UP(div, 1 << calcp);
107 } else {
108 calcp = __roundup_pow_of_two(div);
109 calcp = calcp > 3 ? 3 : calcp;
110 }
111
112 /* we were asked to pass back divider values */
113 if (divp) {
114 *divp = calcp;
115 *pre_divp = calcm - 1;
116 }
117
118 return (parent_rate / calcm) >> calcp;
119}
120
121static long sun6i_ahb1_clk_determine_rate(struct clk_hw *hw, unsigned long rate,
Tomeu Vizoso1c8e6002015-01-23 12:03:31 +0100122 unsigned long min_rate,
123 unsigned long max_rate,
Chen-Yu Tsai7954dfa2014-11-26 15:16:52 +0800124 unsigned long *best_parent_rate,
125 struct clk_hw **best_parent_clk)
126{
127 struct clk *clk = hw->clk, *parent, *best_parent = NULL;
128 int i, num_parents;
129 unsigned long parent_rate, best = 0, child_rate, best_child_rate = 0;
130
131 /* find the parent that can help provide the fastest rate <= rate */
132 num_parents = __clk_get_num_parents(clk);
133 for (i = 0; i < num_parents; i++) {
134 parent = clk_get_parent_by_index(clk, i);
135 if (!parent)
136 continue;
137 if (__clk_get_flags(clk) & CLK_SET_RATE_PARENT)
138 parent_rate = __clk_round_rate(parent, rate);
139 else
140 parent_rate = __clk_get_rate(parent);
141
142 child_rate = sun6i_ahb1_clk_round(rate, NULL, NULL, i,
143 parent_rate);
144
145 if (child_rate <= rate && child_rate > best_child_rate) {
146 best_parent = parent;
147 best = parent_rate;
148 best_child_rate = child_rate;
149 }
150 }
151
152 if (best_parent)
153 *best_parent_clk = __clk_get_hw(best_parent);
154 *best_parent_rate = best;
155
156 return best_child_rate;
157}
158
159static int sun6i_ahb1_clk_set_rate(struct clk_hw *hw, unsigned long rate,
160 unsigned long parent_rate)
161{
162 struct sun6i_ahb1_clk *ahb1 = to_sun6i_ahb1_clk(hw);
163 unsigned long flags;
164 u8 div, pre_div, parent;
165 u32 reg;
166
167 spin_lock_irqsave(&clk_lock, flags);
168
169 reg = readl(ahb1->reg);
170
171 /* need to know which parent is used to apply pre-divider */
172 parent = SUN6I_AHB1_MUX_GET_PARENT(reg);
173 sun6i_ahb1_clk_round(rate, &div, &pre_div, parent, parent_rate);
174
175 reg = SUN6I_AHB1_DIV_SET(reg, div);
176 reg = SUN6I_AHB1_PLL6_DIV_SET(reg, pre_div);
177 writel(reg, ahb1->reg);
178
179 spin_unlock_irqrestore(&clk_lock, flags);
180
181 return 0;
182}
183
184static const struct clk_ops sun6i_ahb1_clk_ops = {
185 .determine_rate = sun6i_ahb1_clk_determine_rate,
186 .recalc_rate = sun6i_ahb1_clk_recalc_rate,
187 .set_rate = sun6i_ahb1_clk_set_rate,
188};
189
190static void __init sun6i_ahb1_clk_setup(struct device_node *node)
191{
192 struct clk *clk;
193 struct sun6i_ahb1_clk *ahb1;
194 struct clk_mux *mux;
195 const char *clk_name = node->name;
196 const char *parents[SUN6I_AHB1_MAX_PARENTS];
197 void __iomem *reg;
198 int i = 0;
199
200 reg = of_io_request_and_map(node, 0, of_node_full_name(node));
201
202 /* we have a mux, we will have >1 parents */
203 while (i < SUN6I_AHB1_MAX_PARENTS &&
204 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
205 i++;
206
207 of_property_read_string(node, "clock-output-names", &clk_name);
208
209 ahb1 = kzalloc(sizeof(struct sun6i_ahb1_clk), GFP_KERNEL);
210 if (!ahb1)
211 return;
212
213 mux = kzalloc(sizeof(struct clk_mux), GFP_KERNEL);
214 if (!mux) {
215 kfree(ahb1);
216 return;
217 }
218
219 /* set up clock properties */
220 mux->reg = reg;
221 mux->shift = SUN6I_AHB1_MUX_SHIFT;
222 mux->mask = SUN6I_AHB1_MUX_MASK;
223 mux->lock = &clk_lock;
224 ahb1->reg = reg;
225
226 clk = clk_register_composite(NULL, clk_name, parents, i,
227 &mux->hw, &clk_mux_ops,
228 &ahb1->hw, &sun6i_ahb1_clk_ops,
229 NULL, NULL, 0);
230
231 if (!IS_ERR(clk)) {
232 of_clk_add_provider(node, of_clk_src_simple_get, clk);
233 clk_register_clkdev(clk, clk_name, NULL);
234 }
235}
236CLK_OF_DECLARE(sun6i_a31_ahb1, "allwinner,sun6i-a31-ahb1-clk", sun6i_ahb1_clk_setup);
237
Emilio López40a5dcb2013-12-23 00:32:32 -0300238/* Maximum number of parents our clocks have */
239#define SUNXI_MAX_PARENTS 5
240
Emilio Lópeze874a662013-02-25 11:44:26 -0300241/**
Maxime Ripard81ba6c52013-07-22 18:21:32 +0200242 * sun4i_get_pll1_factors() - calculates n, k, m, p factors for PLL1
Emilio Lópeze874a662013-02-25 11:44:26 -0300243 * PLL1 rate is calculated as follows
244 * rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
245 * parent_rate is always 24Mhz
246 */
247
Maxime Ripard81ba6c52013-07-22 18:21:32 +0200248static void sun4i_get_pll1_factors(u32 *freq, u32 parent_rate,
Emilio Lópeze874a662013-02-25 11:44:26 -0300249 u8 *n, u8 *k, u8 *m, u8 *p)
250{
251 u8 div;
252
253 /* Normalize value to a 6M multiple */
254 div = *freq / 6000000;
255 *freq = 6000000 * div;
256
257 /* we were called to round the frequency, we can now return */
258 if (n == NULL)
259 return;
260
261 /* m is always zero for pll1 */
262 *m = 0;
263
264 /* k is 1 only on these cases */
265 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
266 *k = 1;
267 else
268 *k = 0;
269
270 /* p will be 3 for divs under 10 */
271 if (div < 10)
272 *p = 3;
273
274 /* p will be 2 for divs between 10 - 20 and odd divs under 32 */
275 else if (div < 20 || (div < 32 && (div & 1)))
276 *p = 2;
277
278 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
279 * of divs between 40-62 */
280 else if (div < 40 || (div < 64 && (div & 2)))
281 *p = 1;
282
283 /* any other entries have p = 0 */
284 else
285 *p = 0;
286
287 /* calculate a suitable n based on k and p */
288 div <<= *p;
289 div /= (*k + 1);
290 *n = div / 4;
291}
292
Maxime Ripard6a721db2013-07-23 23:34:10 +0200293/**
294 * sun6i_a31_get_pll1_factors() - calculates n, k and m factors for PLL1
295 * PLL1 rate is calculated as follows
296 * rate = parent_rate * (n + 1) * (k + 1) / (m + 1);
297 * parent_rate should always be 24MHz
298 */
299static void sun6i_a31_get_pll1_factors(u32 *freq, u32 parent_rate,
300 u8 *n, u8 *k, u8 *m, u8 *p)
301{
302 /*
303 * We can operate only on MHz, this will make our life easier
304 * later.
305 */
306 u32 freq_mhz = *freq / 1000000;
307 u32 parent_freq_mhz = parent_rate / 1000000;
Emilio Lópeze874a662013-02-25 11:44:26 -0300308
Maxime Ripard6a721db2013-07-23 23:34:10 +0200309 /*
310 * Round down the frequency to the closest multiple of either
311 * 6 or 16
312 */
313 u32 round_freq_6 = round_down(freq_mhz, 6);
314 u32 round_freq_16 = round_down(freq_mhz, 16);
315
316 if (round_freq_6 > round_freq_16)
317 freq_mhz = round_freq_6;
318 else
319 freq_mhz = round_freq_16;
320
321 *freq = freq_mhz * 1000000;
322
323 /*
324 * If the factors pointer are null, we were just called to
325 * round down the frequency.
326 * Exit.
327 */
328 if (n == NULL)
329 return;
330
331 /* If the frequency is a multiple of 32 MHz, k is always 3 */
332 if (!(freq_mhz % 32))
333 *k = 3;
334 /* If the frequency is a multiple of 9 MHz, k is always 2 */
335 else if (!(freq_mhz % 9))
336 *k = 2;
337 /* If the frequency is a multiple of 8 MHz, k is always 1 */
338 else if (!(freq_mhz % 8))
339 *k = 1;
340 /* Otherwise, we don't use the k factor */
341 else
342 *k = 0;
343
344 /*
345 * If the frequency is a multiple of 2 but not a multiple of
346 * 3, m is 3. This is the first time we use 6 here, yet we
347 * will use it on several other places.
348 * We use this number because it's the lowest frequency we can
349 * generate (with n = 0, k = 0, m = 3), so every other frequency
350 * somehow relates to this frequency.
351 */
352 if ((freq_mhz % 6) == 2 || (freq_mhz % 6) == 4)
353 *m = 2;
354 /*
355 * If the frequency is a multiple of 6MHz, but the factor is
356 * odd, m will be 3
357 */
358 else if ((freq_mhz / 6) & 1)
359 *m = 3;
360 /* Otherwise, we end up with m = 1 */
361 else
362 *m = 1;
363
364 /* Calculate n thanks to the above factors we already got */
365 *n = freq_mhz * (*m + 1) / ((*k + 1) * parent_freq_mhz) - 1;
366
367 /*
368 * If n end up being outbound, and that we can still decrease
369 * m, do it.
370 */
371 if ((*n + 1) > 31 && (*m + 1) > 1) {
372 *n = (*n + 1) / 2 - 1;
373 *m = (*m + 1) / 2 - 1;
374 }
375}
Emilio Lópeze874a662013-02-25 11:44:26 -0300376
377/**
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +0800378 * sun8i_a23_get_pll1_factors() - calculates n, k, m, p factors for PLL1
379 * PLL1 rate is calculated as follows
380 * rate = (parent_rate * (n + 1) * (k + 1) >> p) / (m + 1);
381 * parent_rate is always 24Mhz
382 */
383
384static void sun8i_a23_get_pll1_factors(u32 *freq, u32 parent_rate,
385 u8 *n, u8 *k, u8 *m, u8 *p)
386{
387 u8 div;
388
389 /* Normalize value to a 6M multiple */
390 div = *freq / 6000000;
391 *freq = 6000000 * div;
392
393 /* we were called to round the frequency, we can now return */
394 if (n == NULL)
395 return;
396
397 /* m is always zero for pll1 */
398 *m = 0;
399
400 /* k is 1 only on these cases */
401 if (*freq >= 768000000 || *freq == 42000000 || *freq == 54000000)
402 *k = 1;
403 else
404 *k = 0;
405
406 /* p will be 2 for divs under 20 and odd divs under 32 */
407 if (div < 20 || (div < 32 && (div & 1)))
408 *p = 2;
409
410 /* p will be 1 for even divs under 32, divs under 40 and odd pairs
411 * of divs between 40-62 */
412 else if (div < 40 || (div < 64 && (div & 2)))
413 *p = 1;
414
415 /* any other entries have p = 0 */
416 else
417 *p = 0;
418
419 /* calculate a suitable n based on k and p */
420 div <<= *p;
421 div /= (*k + 1);
422 *n = div / 4 - 1;
423}
424
425/**
Emilio Lópezd584c132013-12-23 00:32:37 -0300426 * sun4i_get_pll5_factors() - calculates n, k factors for PLL5
427 * PLL5 rate is calculated as follows
428 * rate = parent_rate * n * (k + 1)
429 * parent_rate is always 24Mhz
430 */
431
432static void sun4i_get_pll5_factors(u32 *freq, u32 parent_rate,
433 u8 *n, u8 *k, u8 *m, u8 *p)
434{
435 u8 div;
436
437 /* Normalize value to a parent_rate multiple (24M) */
438 div = *freq / parent_rate;
439 *freq = parent_rate * div;
440
441 /* we were called to round the frequency, we can now return */
442 if (n == NULL)
443 return;
444
445 if (div < 31)
446 *k = 0;
447 else if (div / 2 < 31)
448 *k = 1;
449 else if (div / 3 < 31)
450 *k = 2;
451 else
452 *k = 3;
453
454 *n = DIV_ROUND_UP(div, (*k+1));
455}
456
Maxime Ripard92ef67c2014-02-05 14:05:03 +0100457/**
Chen-Yu Tsai95e94c12014-11-13 02:08:31 +0800458 * sun6i_a31_get_pll6_factors() - calculates n, k factors for A31 PLL6x2
459 * PLL6x2 rate is calculated as follows
460 * rate = parent_rate * (n + 1) * (k + 1)
Maxime Ripard92ef67c2014-02-05 14:05:03 +0100461 * parent_rate is always 24Mhz
462 */
Emilio Lópezd584c132013-12-23 00:32:37 -0300463
Maxime Ripard92ef67c2014-02-05 14:05:03 +0100464static void sun6i_a31_get_pll6_factors(u32 *freq, u32 parent_rate,
465 u8 *n, u8 *k, u8 *m, u8 *p)
466{
467 u8 div;
468
Chen-Yu Tsai95e94c12014-11-13 02:08:31 +0800469 /* Normalize value to a parent_rate multiple (24M) */
Maxime Ripard92ef67c2014-02-05 14:05:03 +0100470 div = *freq / parent_rate;
471 *freq = parent_rate * div;
472
473 /* we were called to round the frequency, we can now return */
474 if (n == NULL)
475 return;
476
477 *k = div / 32;
478 if (*k > 3)
479 *k = 3;
480
Chen-Yu Tsai95e94c12014-11-13 02:08:31 +0800481 *n = DIV_ROUND_UP(div, (*k+1)) - 1;
Maxime Ripard92ef67c2014-02-05 14:05:03 +0100482}
Emilio Lópezd584c132013-12-23 00:32:37 -0300483
484/**
Chen-Yu Tsai9f243092015-03-20 01:19:03 +0800485 * sun5i_a13_get_ahb_factors() - calculates m, p factors for AHB
486 * AHB rate is calculated as follows
487 * rate = parent_rate >> p
488 */
489
490static void sun5i_a13_get_ahb_factors(u32 *freq, u32 parent_rate,
491 u8 *n, u8 *k, u8 *m, u8 *p)
492{
493 u32 div;
494
495 /* divide only */
496 if (parent_rate < *freq)
497 *freq = parent_rate;
498
499 /*
500 * user manual says valid speed is 8k ~ 276M, but tests show it
501 * can work at speeds up to 300M, just after reparenting to pll6
502 */
503 if (*freq < 8000)
504 *freq = 8000;
505 if (*freq > 300000000)
506 *freq = 300000000;
507
508 div = order_base_2(DIV_ROUND_UP(parent_rate, *freq));
509
510 /* p = 0 ~ 3 */
511 if (div > 3)
512 div = 3;
513
514 *freq = parent_rate >> div;
515
516 /* we were called to round the frequency, we can now return */
517 if (p == NULL)
518 return;
519
520 *p = div;
521}
522
523/**
Maxime Ripard81ba6c52013-07-22 18:21:32 +0200524 * sun4i_get_apb1_factors() - calculates m, p factors for APB1
Emilio Lópeze874a662013-02-25 11:44:26 -0300525 * APB1 rate is calculated as follows
526 * rate = (parent_rate >> p) / (m + 1);
527 */
528
Maxime Ripard81ba6c52013-07-22 18:21:32 +0200529static void sun4i_get_apb1_factors(u32 *freq, u32 parent_rate,
Emilio Lópeze874a662013-02-25 11:44:26 -0300530 u8 *n, u8 *k, u8 *m, u8 *p)
531{
532 u8 calcm, calcp;
533
534 if (parent_rate < *freq)
535 *freq = parent_rate;
536
Emilio López22260132014-03-19 15:19:32 -0300537 parent_rate = DIV_ROUND_UP(parent_rate, *freq);
Emilio Lópeze874a662013-02-25 11:44:26 -0300538
539 /* Invalid rate! */
540 if (parent_rate > 32)
541 return;
542
543 if (parent_rate <= 4)
544 calcp = 0;
545 else if (parent_rate <= 8)
546 calcp = 1;
547 else if (parent_rate <= 16)
548 calcp = 2;
549 else
550 calcp = 3;
551
552 calcm = (parent_rate >> calcp) - 1;
553
554 *freq = (parent_rate >> calcp) / (calcm + 1);
555
556 /* we were called to round the frequency, we can now return */
557 if (n == NULL)
558 return;
559
560 *m = calcm;
561 *p = calcp;
562}
563
564
565
Emilio López75517692013-12-23 00:32:39 -0300566
567/**
Chen-Yu Tsai6f863412013-12-24 21:26:17 +0800568 * sun7i_a20_get_out_factors() - calculates m, p factors for CLK_OUT_A/B
569 * CLK_OUT rate is calculated as follows
570 * rate = (parent_rate >> p) / (m + 1);
571 */
572
573static void sun7i_a20_get_out_factors(u32 *freq, u32 parent_rate,
574 u8 *n, u8 *k, u8 *m, u8 *p)
575{
576 u8 div, calcm, calcp;
577
578 /* These clocks can only divide, so we will never be able to achieve
579 * frequencies higher than the parent frequency */
580 if (*freq > parent_rate)
581 *freq = parent_rate;
582
Emilio López22260132014-03-19 15:19:32 -0300583 div = DIV_ROUND_UP(parent_rate, *freq);
Chen-Yu Tsai6f863412013-12-24 21:26:17 +0800584
585 if (div < 32)
586 calcp = 0;
587 else if (div / 2 < 32)
588 calcp = 1;
589 else if (div / 4 < 32)
590 calcp = 2;
591 else
592 calcp = 3;
593
594 calcm = DIV_ROUND_UP(div, 1 << calcp);
595
596 *freq = (parent_rate >> calcp) / calcm;
597
598 /* we were called to round the frequency, we can now return */
599 if (n == NULL)
600 return;
601
602 *m = calcm - 1;
603 *p = calcp;
604}
605
Chen-Yu Tsaie4c6d6c2014-02-10 18:35:47 +0800606/**
Emilio Lópeze874a662013-02-25 11:44:26 -0300607 * sunxi_factors_clk_setup() - Setup function for factor clocks
608 */
609
Maxime Ripard81ba6c52013-07-22 18:21:32 +0200610static struct clk_factors_config sun4i_pll1_config = {
Emilio Lópeze874a662013-02-25 11:44:26 -0300611 .nshift = 8,
612 .nwidth = 5,
613 .kshift = 4,
614 .kwidth = 2,
615 .mshift = 0,
616 .mwidth = 2,
617 .pshift = 16,
618 .pwidth = 2,
619};
620
Maxime Ripard6a721db2013-07-23 23:34:10 +0200621static struct clk_factors_config sun6i_a31_pll1_config = {
622 .nshift = 8,
623 .nwidth = 5,
624 .kshift = 4,
625 .kwidth = 2,
626 .mshift = 0,
627 .mwidth = 2,
Hans de Goede76820fc2015-01-24 12:56:32 +0100628 .n_start = 1,
Maxime Ripard6a721db2013-07-23 23:34:10 +0200629};
630
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +0800631static struct clk_factors_config sun8i_a23_pll1_config = {
632 .nshift = 8,
633 .nwidth = 5,
634 .kshift = 4,
635 .kwidth = 2,
636 .mshift = 0,
637 .mwidth = 2,
638 .pshift = 16,
639 .pwidth = 2,
640 .n_start = 1,
641};
642
Emilio Lópezd584c132013-12-23 00:32:37 -0300643static struct clk_factors_config sun4i_pll5_config = {
644 .nshift = 8,
645 .nwidth = 5,
646 .kshift = 4,
647 .kwidth = 2,
648};
649
Maxime Ripard92ef67c2014-02-05 14:05:03 +0100650static struct clk_factors_config sun6i_a31_pll6_config = {
651 .nshift = 8,
652 .nwidth = 5,
653 .kshift = 4,
654 .kwidth = 2,
Chen-Yu Tsai95e94c12014-11-13 02:08:31 +0800655 .n_start = 1,
Maxime Ripard92ef67c2014-02-05 14:05:03 +0100656};
657
Chen-Yu Tsai9f243092015-03-20 01:19:03 +0800658static struct clk_factors_config sun5i_a13_ahb_config = {
659 .pshift = 4,
660 .pwidth = 2,
661};
662
Maxime Ripard81ba6c52013-07-22 18:21:32 +0200663static struct clk_factors_config sun4i_apb1_config = {
Emilio Lópeze874a662013-02-25 11:44:26 -0300664 .mshift = 0,
665 .mwidth = 5,
666 .pshift = 16,
667 .pwidth = 2,
668};
669
Emilio López75517692013-12-23 00:32:39 -0300670/* user manual says "n" but it's really "p" */
Chen-Yu Tsai6f863412013-12-24 21:26:17 +0800671static struct clk_factors_config sun7i_a20_out_config = {
672 .mshift = 8,
673 .mwidth = 5,
674 .pshift = 20,
675 .pwidth = 2,
676};
677
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530678static const struct factors_data sun4i_pll1_data __initconst = {
Emilio Lópezd838ff32013-12-23 00:32:34 -0300679 .enable = 31,
Maxime Ripard81ba6c52013-07-22 18:21:32 +0200680 .table = &sun4i_pll1_config,
681 .getter = sun4i_get_pll1_factors,
Emilio Lópeze874a662013-02-25 11:44:26 -0300682};
683
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530684static const struct factors_data sun6i_a31_pll1_data __initconst = {
Emilio Lópezd838ff32013-12-23 00:32:34 -0300685 .enable = 31,
Maxime Ripard6a721db2013-07-23 23:34:10 +0200686 .table = &sun6i_a31_pll1_config,
687 .getter = sun6i_a31_get_pll1_factors,
688};
689
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +0800690static const struct factors_data sun8i_a23_pll1_data __initconst = {
691 .enable = 31,
692 .table = &sun8i_a23_pll1_config,
693 .getter = sun8i_a23_get_pll1_factors,
694};
695
Emilio López5a8ddf22014-03-19 15:19:30 -0300696static const struct factors_data sun7i_a20_pll4_data __initconst = {
697 .enable = 31,
698 .table = &sun4i_pll5_config,
699 .getter = sun4i_get_pll5_factors,
700};
701
Emilio Lópezd584c132013-12-23 00:32:37 -0300702static const struct factors_data sun4i_pll5_data __initconst = {
703 .enable = 31,
704 .table = &sun4i_pll5_config,
705 .getter = sun4i_get_pll5_factors,
Chen-Yu Tsai667f5422014-02-03 09:51:39 +0800706 .name = "pll5",
707};
708
709static const struct factors_data sun4i_pll6_data __initconst = {
710 .enable = 31,
711 .table = &sun4i_pll5_config,
712 .getter = sun4i_get_pll5_factors,
713 .name = "pll6",
Emilio Lópezd584c132013-12-23 00:32:37 -0300714};
715
Maxime Ripard92ef67c2014-02-05 14:05:03 +0100716static const struct factors_data sun6i_a31_pll6_data __initconst = {
717 .enable = 31,
718 .table = &sun6i_a31_pll6_config,
719 .getter = sun6i_a31_get_pll6_factors,
Chen-Yu Tsai95e94c12014-11-13 02:08:31 +0800720 .name = "pll6x2",
Maxime Ripard92ef67c2014-02-05 14:05:03 +0100721};
722
Chen-Yu Tsai9f243092015-03-20 01:19:03 +0800723static const struct factors_data sun5i_a13_ahb_data __initconst = {
724 .mux = 6,
725 .muxmask = BIT(1) | BIT(0),
726 .table = &sun5i_a13_ahb_config,
727 .getter = sun5i_a13_get_ahb_factors,
728};
729
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530730static const struct factors_data sun4i_apb1_data __initconst = {
Emilio López93746e72014-11-06 11:40:29 +0800731 .mux = 24,
732 .muxmask = BIT(1) | BIT(0),
Maxime Ripard81ba6c52013-07-22 18:21:32 +0200733 .table = &sun4i_apb1_config,
734 .getter = sun4i_get_apb1_factors,
Emilio Lópeze874a662013-02-25 11:44:26 -0300735};
736
Chen-Yu Tsai6f863412013-12-24 21:26:17 +0800737static const struct factors_data sun7i_a20_out_data __initconst = {
738 .enable = 31,
739 .mux = 24,
Chen-Yu Tsaie94f8cb32014-10-20 22:10:26 +0800740 .muxmask = BIT(1) | BIT(0),
Chen-Yu Tsai6f863412013-12-24 21:26:17 +0800741 .table = &sun7i_a20_out_config,
742 .getter = sun7i_a20_get_out_factors,
743};
744
Emilio López5f4e0be2013-12-23 00:32:36 -0300745static struct clk * __init sunxi_factors_clk_setup(struct device_node *node,
Maxime Ripard601da9d2014-07-04 22:24:52 +0200746 const struct factors_data *data)
Emilio Lópeze874a662013-02-25 11:44:26 -0300747{
Hans de Goede7c74c222014-11-23 14:38:07 +0100748 void __iomem *reg;
749
750 reg = of_iomap(node, 0);
751 if (!reg) {
752 pr_err("Could not get registers for factors-clk: %s\n",
753 node->name);
754 return NULL;
755 }
756
757 return sunxi_factors_register(node, data, &clk_lock, reg);
Emilio Lópeze874a662013-02-25 11:44:26 -0300758}
759
760
761
762/**
763 * sunxi_mux_clk_setup() - Setup function for muxes
764 */
765
766#define SUNXI_MUX_GATE_WIDTH 2
767
768struct mux_data {
769 u8 shift;
770};
771
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530772static const struct mux_data sun4i_cpu_mux_data __initconst = {
Emilio Lópeze874a662013-02-25 11:44:26 -0300773 .shift = 16,
774};
775
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530776static const struct mux_data sun6i_a31_ahb1_mux_data __initconst = {
Maxime Ripard6a721db2013-07-23 23:34:10 +0200777 .shift = 12,
778};
779
Emilio Lópeze874a662013-02-25 11:44:26 -0300780static void __init sunxi_mux_clk_setup(struct device_node *node,
781 struct mux_data *data)
782{
783 struct clk *clk;
784 const char *clk_name = node->name;
Emilio Lópezedaf3fb2013-12-23 00:32:33 -0300785 const char *parents[SUNXI_MAX_PARENTS];
Emilio López89a94562014-07-28 00:49:42 -0300786 void __iomem *reg;
Emilio Lópeze874a662013-02-25 11:44:26 -0300787 int i = 0;
788
789 reg = of_iomap(node, 0);
790
Emilio Lópezedaf3fb2013-12-23 00:32:33 -0300791 while (i < SUNXI_MAX_PARENTS &&
792 (parents[i] = of_clk_get_parent_name(node, i)) != NULL)
Emilio Lópeze874a662013-02-25 11:44:26 -0300793 i++;
794
Chen-Yu Tsaif64111e2014-02-03 09:51:37 +0800795 of_property_read_string(node, "clock-output-names", &clk_name);
796
James Hogan819c1de2013-07-29 12:25:01 +0100797 clk = clk_register_mux(NULL, clk_name, parents, i,
Chen-Yu Tsai3ec72fa2015-01-06 10:35:12 +0800798 CLK_SET_RATE_PARENT, reg,
Emilio Lópeze874a662013-02-25 11:44:26 -0300799 data->shift, SUNXI_MUX_GATE_WIDTH,
800 0, &clk_lock);
801
802 if (clk) {
803 of_clk_add_provider(node, of_clk_src_simple_get, clk);
804 clk_register_clkdev(clk, clk_name, NULL);
805 }
806}
807
808
809
810/**
811 * sunxi_divider_clk_setup() - Setup function for simple divider clocks
812 */
813
Emilio Lópeze874a662013-02-25 11:44:26 -0300814struct div_data {
Maxime Ripard70855bb2013-07-23 09:25:56 +0200815 u8 shift;
816 u8 pow;
817 u8 width;
Chen-Yu Tsaiea5671b2014-06-26 23:55:42 +0800818 const struct clk_div_table *table;
Emilio Lópeze874a662013-02-25 11:44:26 -0300819};
820
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530821static const struct div_data sun4i_axi_data __initconst = {
Maxime Ripard70855bb2013-07-23 09:25:56 +0200822 .shift = 0,
823 .pow = 0,
824 .width = 2,
Emilio Lópeze874a662013-02-25 11:44:26 -0300825};
826
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +0800827static const struct clk_div_table sun8i_a23_axi_table[] __initconst = {
828 { .val = 0, .div = 1 },
829 { .val = 1, .div = 2 },
830 { .val = 2, .div = 3 },
831 { .val = 3, .div = 4 },
832 { .val = 4, .div = 4 },
833 { .val = 5, .div = 4 },
834 { .val = 6, .div = 4 },
835 { .val = 7, .div = 4 },
836 { } /* sentinel */
837};
838
839static const struct div_data sun8i_a23_axi_data __initconst = {
840 .width = 3,
841 .table = sun8i_a23_axi_table,
842};
843
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530844static const struct div_data sun4i_ahb_data __initconst = {
Maxime Ripard70855bb2013-07-23 09:25:56 +0200845 .shift = 4,
846 .pow = 1,
847 .width = 2,
Emilio Lópeze874a662013-02-25 11:44:26 -0300848};
849
Chen-Yu Tsaicfe4c932014-09-06 14:45:10 +0800850static const struct clk_div_table sun4i_apb0_table[] __initconst = {
851 { .val = 0, .div = 2 },
852 { .val = 1, .div = 2 },
853 { .val = 2, .div = 4 },
854 { .val = 3, .div = 8 },
855 { } /* sentinel */
856};
857
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530858static const struct div_data sun4i_apb0_data __initconst = {
Maxime Ripard70855bb2013-07-23 09:25:56 +0200859 .shift = 8,
860 .pow = 1,
861 .width = 2,
Chen-Yu Tsaicfe4c932014-09-06 14:45:10 +0800862 .table = sun4i_apb0_table,
Emilio Lópeze874a662013-02-25 11:44:26 -0300863};
864
865static void __init sunxi_divider_clk_setup(struct device_node *node,
866 struct div_data *data)
867{
868 struct clk *clk;
869 const char *clk_name = node->name;
870 const char *clk_parent;
Emilio López89a94562014-07-28 00:49:42 -0300871 void __iomem *reg;
Emilio Lópeze874a662013-02-25 11:44:26 -0300872
873 reg = of_iomap(node, 0);
874
875 clk_parent = of_clk_get_parent_name(node, 0);
876
Chen-Yu Tsaif64111e2014-02-03 09:51:37 +0800877 of_property_read_string(node, "clock-output-names", &clk_name);
878
Chen-Yu Tsaiea5671b2014-06-26 23:55:42 +0800879 clk = clk_register_divider_table(NULL, clk_name, clk_parent, 0,
880 reg, data->shift, data->width,
881 data->pow ? CLK_DIVIDER_POWER_OF_TWO : 0,
882 data->table, &clk_lock);
Emilio Lópeze874a662013-02-25 11:44:26 -0300883 if (clk) {
884 of_clk_add_provider(node, of_clk_src_simple_get, clk);
885 clk_register_clkdev(clk, clk_name, NULL);
886 }
887}
888
889
Emilio López13569a72013-03-27 18:20:37 -0300890
891/**
892 * sunxi_gates_clk_setup() - Setup function for leaf gates on clocks
893 */
894
895#define SUNXI_GATES_MAX_SIZE 64
896
897struct gates_data {
898 DECLARE_BITMAP(mask, SUNXI_GATES_MAX_SIZE);
899};
900
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530901static const struct gates_data sun4i_axi_gates_data __initconst = {
Emilio López13569a72013-03-27 18:20:37 -0300902 .mask = {1},
903};
904
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530905static const struct gates_data sun4i_ahb_gates_data __initconst = {
Emilio López13569a72013-03-27 18:20:37 -0300906 .mask = {0x7F77FFF, 0x14FB3F},
907};
908
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530909static const struct gates_data sun5i_a10s_ahb_gates_data __initconst = {
Maxime Ripard2371dd82013-07-16 11:21:59 +0200910 .mask = {0x147667e7, 0x185915},
911};
912
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530913static const struct gates_data sun5i_a13_ahb_gates_data __initconst = {
Maxime Ripard4f985b42013-04-30 11:56:22 +0200914 .mask = {0x107067e7, 0x185111},
915};
916
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530917static const struct gates_data sun6i_a31_ahb1_gates_data __initconst = {
Maxime Ripard6a721db2013-07-23 23:34:10 +0200918 .mask = {0xEDFE7F62, 0x794F931},
919};
920
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530921static const struct gates_data sun7i_a20_ahb_gates_data __initconst = {
Maxime Ripard1fb2e4a2013-07-25 21:06:56 +0200922 .mask = { 0x12f77fff, 0x16ff3f },
923};
924
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +0800925static const struct gates_data sun8i_a23_ahb1_gates_data __initconst = {
926 .mask = {0x25386742, 0x2505111},
927};
928
Chen-Yu Tsai0b0f0802014-10-20 22:10:28 +0800929static const struct gates_data sun9i_a80_ahb0_gates_data __initconst = {
930 .mask = {0xF5F12B},
931};
932
933static const struct gates_data sun9i_a80_ahb1_gates_data __initconst = {
934 .mask = {0x1E20003},
935};
936
937static const struct gates_data sun9i_a80_ahb2_gates_data __initconst = {
938 .mask = {0x9B7},
939};
940
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530941static const struct gates_data sun4i_apb0_gates_data __initconst = {
Emilio López13569a72013-03-27 18:20:37 -0300942 .mask = {0x4EF},
943};
944
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530945static const struct gates_data sun5i_a10s_apb0_gates_data __initconst = {
Maxime Ripard2371dd82013-07-16 11:21:59 +0200946 .mask = {0x469},
947};
948
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530949static const struct gates_data sun5i_a13_apb0_gates_data __initconst = {
Maxime Ripard4f985b42013-04-30 11:56:22 +0200950 .mask = {0x61},
951};
952
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530953static const struct gates_data sun7i_a20_apb0_gates_data __initconst = {
Maxime Ripard1fb2e4a2013-07-25 21:06:56 +0200954 .mask = { 0x4ff },
955};
956
Chen-Yu Tsai0b0f0802014-10-20 22:10:28 +0800957static const struct gates_data sun9i_a80_apb0_gates_data __initconst = {
958 .mask = {0xEB822},
959};
960
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530961static const struct gates_data sun4i_apb1_gates_data __initconst = {
Emilio López13569a72013-03-27 18:20:37 -0300962 .mask = {0xFF00F7},
963};
964
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530965static const struct gates_data sun5i_a10s_apb1_gates_data __initconst = {
Maxime Ripard2371dd82013-07-16 11:21:59 +0200966 .mask = {0xf0007},
967};
968
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530969static const struct gates_data sun5i_a13_apb1_gates_data __initconst = {
Maxime Ripard4f985b42013-04-30 11:56:22 +0200970 .mask = {0xa0007},
971};
972
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530973static const struct gates_data sun6i_a31_apb1_gates_data __initconst = {
Maxime Ripard6a721db2013-07-23 23:34:10 +0200974 .mask = {0x3031},
975};
976
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +0800977static const struct gates_data sun8i_a23_apb1_gates_data __initconst = {
978 .mask = {0x3021},
979};
980
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530981static const struct gates_data sun6i_a31_apb2_gates_data __initconst = {
Maxime Ripard6a721db2013-07-23 23:34:10 +0200982 .mask = {0x3F000F},
983};
984
Sachin Kamat52be7cc2013-08-12 14:44:06 +0530985static const struct gates_data sun7i_a20_apb1_gates_data __initconst = {
Maxime Ripard1fb2e4a2013-07-25 21:06:56 +0200986 .mask = { 0xff80ff },
987};
988
Chen-Yu Tsai0b0f0802014-10-20 22:10:28 +0800989static const struct gates_data sun9i_a80_apb1_gates_data __initconst = {
990 .mask = {0x3F001F},
991};
992
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +0800993static const struct gates_data sun8i_a23_apb2_gates_data __initconst = {
994 .mask = {0x1F0007},
995};
996
Emilio López13569a72013-03-27 18:20:37 -0300997static void __init sunxi_gates_clk_setup(struct device_node *node,
998 struct gates_data *data)
999{
1000 struct clk_onecell_data *clk_data;
1001 const char *clk_parent;
1002 const char *clk_name;
Emilio López89a94562014-07-28 00:49:42 -03001003 void __iomem *reg;
Emilio López13569a72013-03-27 18:20:37 -03001004 int qty;
1005 int i = 0;
1006 int j = 0;
Emilio López13569a72013-03-27 18:20:37 -03001007
1008 reg = of_iomap(node, 0);
1009
1010 clk_parent = of_clk_get_parent_name(node, 0);
1011
1012 /* Worst-case size approximation and memory allocation */
1013 qty = find_last_bit(data->mask, SUNXI_GATES_MAX_SIZE);
1014 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1015 if (!clk_data)
1016 return;
1017 clk_data->clks = kzalloc((qty+1) * sizeof(struct clk *), GFP_KERNEL);
1018 if (!clk_data->clks) {
1019 kfree(clk_data);
1020 return;
1021 }
1022
1023 for_each_set_bit(i, data->mask, SUNXI_GATES_MAX_SIZE) {
1024 of_property_read_string_index(node, "clock-output-names",
1025 j, &clk_name);
1026
Emilio López13569a72013-03-27 18:20:37 -03001027 clk_data->clks[i] = clk_register_gate(NULL, clk_name,
Chen-Yu Tsai70eab192014-06-26 23:55:40 +08001028 clk_parent, 0,
Emilio López13569a72013-03-27 18:20:37 -03001029 reg + 4 * (i/32), i % 32,
1030 0, &clk_lock);
1031 WARN_ON(IS_ERR(clk_data->clks[i]));
Chen-Yu Tsaid14e4702014-06-26 23:55:39 +08001032 clk_register_clkdev(clk_data->clks[i], clk_name, NULL);
Emilio López13569a72013-03-27 18:20:37 -03001033
1034 j++;
1035 }
1036
1037 /* Adjust to the real max */
1038 clk_data->clk_num = i;
1039
1040 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1041}
1042
Emilio Lópezd584c132013-12-23 00:32:37 -03001043
1044
1045/**
1046 * sunxi_divs_clk_setup() helper data
1047 */
1048
Chen-Yu Tsai934fe5f2015-03-25 01:22:07 +08001049#define SUNXI_DIVS_MAX_QTY 4
Emilio Lópezd584c132013-12-23 00:32:37 -03001050#define SUNXI_DIVISOR_WIDTH 2
1051
1052struct divs_data {
1053 const struct factors_data *factors; /* data for the factor clock */
Chen-Yu Tsai934fe5f2015-03-25 01:22:07 +08001054 int ndivs; /* number of outputs */
1055 /*
1056 * List of outputs. Refer to the diagram for sunxi_divs_clk_setup():
1057 * self or base factor clock refers to the output from the pll
1058 * itself. The remaining refer to fixed or configurable divider
1059 * outputs.
1060 */
Emilio Lópezd584c132013-12-23 00:32:37 -03001061 struct {
Chen-Yu Tsai934fe5f2015-03-25 01:22:07 +08001062 u8 self; /* is it the base factor clock? (only one) */
Emilio Lópezd584c132013-12-23 00:32:37 -03001063 u8 fixed; /* is it a fixed divisor? if not... */
1064 struct clk_div_table *table; /* is it a table based divisor? */
1065 u8 shift; /* otherwise it's a normal divisor with this shift */
1066 u8 pow; /* is it power-of-two based? */
1067 u8 gate; /* is it independently gateable? */
1068 } div[SUNXI_DIVS_MAX_QTY];
1069};
1070
1071static struct clk_div_table pll6_sata_tbl[] = {
1072 { .val = 0, .div = 6, },
1073 { .val = 1, .div = 12, },
1074 { .val = 2, .div = 18, },
1075 { .val = 3, .div = 24, },
1076 { } /* sentinel */
1077};
1078
1079static const struct divs_data pll5_divs_data __initconst = {
1080 .factors = &sun4i_pll5_data,
Chen-Yu Tsai13d52f62014-11-13 02:08:30 +08001081 .ndivs = 2,
Emilio Lópezd584c132013-12-23 00:32:37 -03001082 .div = {
1083 { .shift = 0, .pow = 0, }, /* M, DDR */
1084 { .shift = 16, .pow = 1, }, /* P, other */
Chen-Yu Tsai934fe5f2015-03-25 01:22:07 +08001085 /* No output for the base factor clock */
Emilio Lópezd584c132013-12-23 00:32:37 -03001086 }
1087};
1088
1089static const struct divs_data pll6_divs_data __initconst = {
Chen-Yu Tsai667f5422014-02-03 09:51:39 +08001090 .factors = &sun4i_pll6_data,
Chen-Yu Tsai934fe5f2015-03-25 01:22:07 +08001091 .ndivs = 3,
Emilio Lópezd584c132013-12-23 00:32:37 -03001092 .div = {
1093 { .shift = 0, .table = pll6_sata_tbl, .gate = 14 }, /* M, SATA */
1094 { .fixed = 2 }, /* P, other */
Chen-Yu Tsai934fe5f2015-03-25 01:22:07 +08001095 { .self = 1 }, /* base factor clock, 2x */
Emilio Lópezd584c132013-12-23 00:32:37 -03001096 }
1097};
1098
Chen-Yu Tsai95e94c12014-11-13 02:08:31 +08001099static const struct divs_data sun6i_a31_pll6_divs_data __initconst = {
1100 .factors = &sun6i_a31_pll6_data,
Chen-Yu Tsai934fe5f2015-03-25 01:22:07 +08001101 .ndivs = 2,
Chen-Yu Tsai95e94c12014-11-13 02:08:31 +08001102 .div = {
1103 { .fixed = 2 }, /* normal output */
Chen-Yu Tsai934fe5f2015-03-25 01:22:07 +08001104 { .self = 1 }, /* base factor clock, 2x */
Chen-Yu Tsai95e94c12014-11-13 02:08:31 +08001105 }
1106};
1107
Emilio Lópezd584c132013-12-23 00:32:37 -03001108/**
1109 * sunxi_divs_clk_setup() - Setup function for leaf divisors on clocks
1110 *
1111 * These clocks look something like this
1112 * ________________________
1113 * | ___divisor 1---|----> to consumer
1114 * parent >--| pll___/___divisor 2---|----> to consumer
1115 * | \_______________|____> to consumer
1116 * |________________________|
1117 */
1118
1119static void __init sunxi_divs_clk_setup(struct device_node *node,
1120 struct divs_data *data)
1121{
1122 struct clk_onecell_data *clk_data;
Chen-Yu Tsai97e36b32014-02-03 09:51:40 +08001123 const char *parent;
Emilio Lópezd584c132013-12-23 00:32:37 -03001124 const char *clk_name;
1125 struct clk **clks, *pclk;
1126 struct clk_hw *gate_hw, *rate_hw;
1127 const struct clk_ops *rate_ops;
1128 struct clk_gate *gate = NULL;
1129 struct clk_fixed_factor *fix_factor;
1130 struct clk_divider *divider;
Emilio López89a94562014-07-28 00:49:42 -03001131 void __iomem *reg;
Chen-Yu Tsai13d52f62014-11-13 02:08:30 +08001132 int ndivs = SUNXI_DIVS_MAX_QTY, i = 0;
Emilio Lópezd584c132013-12-23 00:32:37 -03001133 int flags, clkflags;
1134
Chen-Yu Tsai934fe5f2015-03-25 01:22:07 +08001135 /* if number of children known, use it */
1136 if (data->ndivs)
1137 ndivs = data->ndivs;
1138
Emilio Lópezd584c132013-12-23 00:32:37 -03001139 /* Set up factor clock that we will be dividing */
1140 pclk = sunxi_factors_clk_setup(node, data->factors);
Chen-Yu Tsai97e36b32014-02-03 09:51:40 +08001141 parent = __clk_get_name(pclk);
Emilio Lópezd584c132013-12-23 00:32:37 -03001142
1143 reg = of_iomap(node, 0);
1144
1145 clk_data = kmalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);
1146 if (!clk_data)
1147 return;
1148
Chen-Yu Tsai934fe5f2015-03-25 01:22:07 +08001149 clks = kcalloc(ndivs, sizeof(*clks), GFP_KERNEL);
Emilio Lópezd584c132013-12-23 00:32:37 -03001150 if (!clks)
1151 goto free_clkdata;
1152
1153 clk_data->clks = clks;
1154
1155 /* It's not a good idea to have automatic reparenting changing
1156 * our RAM clock! */
1157 clkflags = !strcmp("pll5", parent) ? 0 : CLK_SET_RATE_PARENT;
1158
Chen-Yu Tsai13d52f62014-11-13 02:08:30 +08001159 for (i = 0; i < ndivs; i++) {
Emilio Lópezd584c132013-12-23 00:32:37 -03001160 if (of_property_read_string_index(node, "clock-output-names",
1161 i, &clk_name) != 0)
1162 break;
1163
Chen-Yu Tsai934fe5f2015-03-25 01:22:07 +08001164 /* If this is the base factor clock, only update clks */
1165 if (data->div[i].self) {
1166 clk_data->clks[i] = pclk;
1167 continue;
1168 }
1169
Emilio Lópezd584c132013-12-23 00:32:37 -03001170 gate_hw = NULL;
1171 rate_hw = NULL;
1172 rate_ops = NULL;
1173
1174 /* If this leaf clock can be gated, create a gate */
1175 if (data->div[i].gate) {
1176 gate = kzalloc(sizeof(*gate), GFP_KERNEL);
1177 if (!gate)
1178 goto free_clks;
1179
1180 gate->reg = reg;
1181 gate->bit_idx = data->div[i].gate;
1182 gate->lock = &clk_lock;
1183
1184 gate_hw = &gate->hw;
1185 }
1186
1187 /* Leaves can be fixed or configurable divisors */
1188 if (data->div[i].fixed) {
1189 fix_factor = kzalloc(sizeof(*fix_factor), GFP_KERNEL);
1190 if (!fix_factor)
1191 goto free_gate;
1192
1193 fix_factor->mult = 1;
1194 fix_factor->div = data->div[i].fixed;
1195
1196 rate_hw = &fix_factor->hw;
1197 rate_ops = &clk_fixed_factor_ops;
1198 } else {
1199 divider = kzalloc(sizeof(*divider), GFP_KERNEL);
1200 if (!divider)
1201 goto free_gate;
1202
1203 flags = data->div[i].pow ? CLK_DIVIDER_POWER_OF_TWO : 0;
1204
1205 divider->reg = reg;
1206 divider->shift = data->div[i].shift;
1207 divider->width = SUNXI_DIVISOR_WIDTH;
1208 divider->flags = flags;
1209 divider->lock = &clk_lock;
1210 divider->table = data->div[i].table;
1211
1212 rate_hw = &divider->hw;
1213 rate_ops = &clk_divider_ops;
1214 }
1215
1216 /* Wrap the (potential) gate and the divisor on a composite
1217 * clock to unify them */
1218 clks[i] = clk_register_composite(NULL, clk_name, &parent, 1,
1219 NULL, NULL,
1220 rate_hw, rate_ops,
1221 gate_hw, &clk_gate_ops,
1222 clkflags);
1223
1224 WARN_ON(IS_ERR(clk_data->clks[i]));
1225 clk_register_clkdev(clks[i], clk_name, NULL);
1226 }
1227
Emilio Lópezd584c132013-12-23 00:32:37 -03001228 /* Adjust to the real max */
1229 clk_data->clk_num = i;
1230
1231 of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);
1232
1233 return;
1234
1235free_gate:
1236 kfree(gate);
1237free_clks:
1238 kfree(clks);
1239free_clkdata:
1240 kfree(clk_data);
1241}
1242
1243
1244
Emilio Lópeze874a662013-02-25 11:44:26 -03001245/* Matches for factors clocks */
Sachin Kamat52be7cc2013-08-12 14:44:06 +05301246static const struct of_device_id clk_factors_match[] __initconst = {
Maxime Ripardfd1b22f2014-02-06 09:55:57 +01001247 {.compatible = "allwinner,sun4i-a10-pll1-clk", .data = &sun4i_pll1_data,},
Maxime Ripard6a721db2013-07-23 23:34:10 +02001248 {.compatible = "allwinner,sun6i-a31-pll1-clk", .data = &sun6i_a31_pll1_data,},
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +08001249 {.compatible = "allwinner,sun8i-a23-pll1-clk", .data = &sun8i_a23_pll1_data,},
Emilio López5a8ddf22014-03-19 15:19:30 -03001250 {.compatible = "allwinner,sun7i-a20-pll4-clk", .data = &sun7i_a20_pll4_data,},
Chen-Yu Tsai9f243092015-03-20 01:19:03 +08001251 {.compatible = "allwinner,sun5i-a13-ahb-clk", .data = &sun5i_a13_ahb_data,},
Maxime Ripardfd1b22f2014-02-06 09:55:57 +01001252 {.compatible = "allwinner,sun4i-a10-apb1-clk", .data = &sun4i_apb1_data,},
Chen-Yu Tsai6f863412013-12-24 21:26:17 +08001253 {.compatible = "allwinner,sun7i-a20-out-clk", .data = &sun7i_a20_out_data,},
Emilio Lópeze874a662013-02-25 11:44:26 -03001254 {}
1255};
1256
1257/* Matches for divider clocks */
Sachin Kamat52be7cc2013-08-12 14:44:06 +05301258static const struct of_device_id clk_div_match[] __initconst = {
Maxime Ripardfd1b22f2014-02-06 09:55:57 +01001259 {.compatible = "allwinner,sun4i-a10-axi-clk", .data = &sun4i_axi_data,},
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +08001260 {.compatible = "allwinner,sun8i-a23-axi-clk", .data = &sun8i_a23_axi_data,},
Maxime Ripardfd1b22f2014-02-06 09:55:57 +01001261 {.compatible = "allwinner,sun4i-a10-ahb-clk", .data = &sun4i_ahb_data,},
1262 {.compatible = "allwinner,sun4i-a10-apb0-clk", .data = &sun4i_apb0_data,},
Emilio Lópeze874a662013-02-25 11:44:26 -03001263 {}
1264};
1265
Emilio Lópezd584c132013-12-23 00:32:37 -03001266/* Matches for divided outputs */
1267static const struct of_device_id clk_divs_match[] __initconst = {
Maxime Ripardfd1b22f2014-02-06 09:55:57 +01001268 {.compatible = "allwinner,sun4i-a10-pll5-clk", .data = &pll5_divs_data,},
1269 {.compatible = "allwinner,sun4i-a10-pll6-clk", .data = &pll6_divs_data,},
Chen-Yu Tsai95e94c12014-11-13 02:08:31 +08001270 {.compatible = "allwinner,sun6i-a31-pll6-clk", .data = &sun6i_a31_pll6_divs_data,},
Emilio Lópezd584c132013-12-23 00:32:37 -03001271 {}
1272};
1273
Emilio Lópeze874a662013-02-25 11:44:26 -03001274/* Matches for mux clocks */
Sachin Kamat52be7cc2013-08-12 14:44:06 +05301275static const struct of_device_id clk_mux_match[] __initconst = {
Maxime Ripardfd1b22f2014-02-06 09:55:57 +01001276 {.compatible = "allwinner,sun4i-a10-cpu-clk", .data = &sun4i_cpu_mux_data,},
Maxime Ripard6a721db2013-07-23 23:34:10 +02001277 {.compatible = "allwinner,sun6i-a31-ahb1-mux-clk", .data = &sun6i_a31_ahb1_mux_data,},
Emilio Lópeze874a662013-02-25 11:44:26 -03001278 {}
1279};
1280
Emilio López13569a72013-03-27 18:20:37 -03001281/* Matches for gate clocks */
Sachin Kamat52be7cc2013-08-12 14:44:06 +05301282static const struct of_device_id clk_gates_match[] __initconst = {
Maxime Ripardfd1b22f2014-02-06 09:55:57 +01001283 {.compatible = "allwinner,sun4i-a10-axi-gates-clk", .data = &sun4i_axi_gates_data,},
1284 {.compatible = "allwinner,sun4i-a10-ahb-gates-clk", .data = &sun4i_ahb_gates_data,},
Maxime Ripard2371dd82013-07-16 11:21:59 +02001285 {.compatible = "allwinner,sun5i-a10s-ahb-gates-clk", .data = &sun5i_a10s_ahb_gates_data,},
Maxime Ripard4f985b42013-04-30 11:56:22 +02001286 {.compatible = "allwinner,sun5i-a13-ahb-gates-clk", .data = &sun5i_a13_ahb_gates_data,},
Maxime Ripard6a721db2013-07-23 23:34:10 +02001287 {.compatible = "allwinner,sun6i-a31-ahb1-gates-clk", .data = &sun6i_a31_ahb1_gates_data,},
Maxime Ripard1fb2e4a2013-07-25 21:06:56 +02001288 {.compatible = "allwinner,sun7i-a20-ahb-gates-clk", .data = &sun7i_a20_ahb_gates_data,},
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +08001289 {.compatible = "allwinner,sun8i-a23-ahb1-gates-clk", .data = &sun8i_a23_ahb1_gates_data,},
Chen-Yu Tsai0b0f0802014-10-20 22:10:28 +08001290 {.compatible = "allwinner,sun9i-a80-ahb0-gates-clk", .data = &sun9i_a80_ahb0_gates_data,},
1291 {.compatible = "allwinner,sun9i-a80-ahb1-gates-clk", .data = &sun9i_a80_ahb1_gates_data,},
1292 {.compatible = "allwinner,sun9i-a80-ahb2-gates-clk", .data = &sun9i_a80_ahb2_gates_data,},
Maxime Ripardfd1b22f2014-02-06 09:55:57 +01001293 {.compatible = "allwinner,sun4i-a10-apb0-gates-clk", .data = &sun4i_apb0_gates_data,},
Maxime Ripard2371dd82013-07-16 11:21:59 +02001294 {.compatible = "allwinner,sun5i-a10s-apb0-gates-clk", .data = &sun5i_a10s_apb0_gates_data,},
Maxime Ripard4f985b42013-04-30 11:56:22 +02001295 {.compatible = "allwinner,sun5i-a13-apb0-gates-clk", .data = &sun5i_a13_apb0_gates_data,},
Maxime Ripard1fb2e4a2013-07-25 21:06:56 +02001296 {.compatible = "allwinner,sun7i-a20-apb0-gates-clk", .data = &sun7i_a20_apb0_gates_data,},
Chen-Yu Tsai0b0f0802014-10-20 22:10:28 +08001297 {.compatible = "allwinner,sun9i-a80-apb0-gates-clk", .data = &sun9i_a80_apb0_gates_data,},
Maxime Ripardfd1b22f2014-02-06 09:55:57 +01001298 {.compatible = "allwinner,sun4i-a10-apb1-gates-clk", .data = &sun4i_apb1_gates_data,},
Maxime Ripard2371dd82013-07-16 11:21:59 +02001299 {.compatible = "allwinner,sun5i-a10s-apb1-gates-clk", .data = &sun5i_a10s_apb1_gates_data,},
Maxime Ripard4f985b42013-04-30 11:56:22 +02001300 {.compatible = "allwinner,sun5i-a13-apb1-gates-clk", .data = &sun5i_a13_apb1_gates_data,},
Maxime Ripard6a721db2013-07-23 23:34:10 +02001301 {.compatible = "allwinner,sun6i-a31-apb1-gates-clk", .data = &sun6i_a31_apb1_gates_data,},
Maxime Ripard1fb2e4a2013-07-25 21:06:56 +02001302 {.compatible = "allwinner,sun7i-a20-apb1-gates-clk", .data = &sun7i_a20_apb1_gates_data,},
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +08001303 {.compatible = "allwinner,sun8i-a23-apb1-gates-clk", .data = &sun8i_a23_apb1_gates_data,},
Chen-Yu Tsai0b0f0802014-10-20 22:10:28 +08001304 {.compatible = "allwinner,sun9i-a80-apb1-gates-clk", .data = &sun9i_a80_apb1_gates_data,},
Maxime Ripard6a721db2013-07-23 23:34:10 +02001305 {.compatible = "allwinner,sun6i-a31-apb2-gates-clk", .data = &sun6i_a31_apb2_gates_data,},
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +08001306 {.compatible = "allwinner,sun8i-a23-apb2-gates-clk", .data = &sun8i_a23_apb2_gates_data,},
Emilio López13569a72013-03-27 18:20:37 -03001307 {}
1308};
1309
Emilio Lópeze874a662013-02-25 11:44:26 -03001310static void __init of_sunxi_table_clock_setup(const struct of_device_id *clk_match,
1311 void *function)
1312{
1313 struct device_node *np;
1314 const struct div_data *data;
1315 const struct of_device_id *match;
1316 void (*setup_function)(struct device_node *, const void *) = function;
1317
Rob Herringcb7d5f42014-05-12 11:24:31 -05001318 for_each_matching_node_and_match(np, clk_match, &match) {
Emilio Lópeze874a662013-02-25 11:44:26 -03001319 data = match->data;
1320 setup_function(np, data);
1321 }
1322}
1323
Maxime Ripard134a6692014-05-09 22:33:39 -05001324static void __init sunxi_init_clocks(const char *clocks[], int nclocks)
Emilio López8e6a4c42013-09-20 22:03:12 -03001325{
Maxime Ripard134a6692014-05-09 22:33:39 -05001326 unsigned int i;
Emilio López8e6a4c42013-09-20 22:03:12 -03001327
Chen-Yu Tsaib712a622015-03-20 01:19:05 +08001328 /* Register divided output clocks */
1329 of_sunxi_table_clock_setup(clk_divs_match, sunxi_divs_clk_setup);
1330
Emilio Lópeze874a662013-02-25 11:44:26 -03001331 /* Register factor clocks */
1332 of_sunxi_table_clock_setup(clk_factors_match, sunxi_factors_clk_setup);
1333
1334 /* Register divider clocks */
1335 of_sunxi_table_clock_setup(clk_div_match, sunxi_divider_clk_setup);
1336
1337 /* Register mux clocks */
1338 of_sunxi_table_clock_setup(clk_mux_match, sunxi_mux_clk_setup);
Emilio López13569a72013-03-27 18:20:37 -03001339
1340 /* Register gate clocks */
1341 of_sunxi_table_clock_setup(clk_gates_match, sunxi_gates_clk_setup);
Emilio López8e6a4c42013-09-20 22:03:12 -03001342
Maxime Ripard134a6692014-05-09 22:33:39 -05001343 /* Protect the clocks that needs to stay on */
1344 for (i = 0; i < nclocks; i++) {
1345 struct clk *clk = clk_get(NULL, clocks[i]);
1346
1347 if (!IS_ERR(clk))
1348 clk_prepare_enable(clk);
1349 }
Emilio Lópeze874a662013-02-25 11:44:26 -03001350}
Maxime Ripard134a6692014-05-09 22:33:39 -05001351
1352static const char *sun4i_a10_critical_clocks[] __initdata = {
1353 "pll5_ddr",
Chen-Yu Tsai70eab192014-06-26 23:55:40 +08001354 "ahb_sdram",
Maxime Ripard134a6692014-05-09 22:33:39 -05001355};
1356
1357static void __init sun4i_a10_init_clocks(struct device_node *node)
1358{
1359 sunxi_init_clocks(sun4i_a10_critical_clocks,
1360 ARRAY_SIZE(sun4i_a10_critical_clocks));
1361}
1362CLK_OF_DECLARE(sun4i_a10_clk_init, "allwinner,sun4i-a10", sun4i_a10_init_clocks);
1363
1364static const char *sun5i_critical_clocks[] __initdata = {
Chen-Yu Tsai946fd402015-03-20 01:19:04 +08001365 "cpu",
Maxime Ripard134a6692014-05-09 22:33:39 -05001366 "pll5_ddr",
Chen-Yu Tsai70eab192014-06-26 23:55:40 +08001367 "ahb_sdram",
Maxime Ripard134a6692014-05-09 22:33:39 -05001368};
1369
1370static void __init sun5i_init_clocks(struct device_node *node)
1371{
1372 sunxi_init_clocks(sun5i_critical_clocks,
1373 ARRAY_SIZE(sun5i_critical_clocks));
1374}
1375CLK_OF_DECLARE(sun5i_a10s_clk_init, "allwinner,sun5i-a10s", sun5i_init_clocks);
1376CLK_OF_DECLARE(sun5i_a13_clk_init, "allwinner,sun5i-a13", sun5i_init_clocks);
1377CLK_OF_DECLARE(sun7i_a20_clk_init, "allwinner,sun7i-a20", sun5i_init_clocks);
1378
1379static const char *sun6i_critical_clocks[] __initdata = {
Maxime Ripard2df73f42014-05-09 22:33:40 -05001380 "cpu",
Maxime Ripard134a6692014-05-09 22:33:39 -05001381};
1382
1383static void __init sun6i_init_clocks(struct device_node *node)
1384{
1385 sunxi_init_clocks(sun6i_critical_clocks,
1386 ARRAY_SIZE(sun6i_critical_clocks));
1387}
1388CLK_OF_DECLARE(sun6i_a31_clk_init, "allwinner,sun6i-a31", sun6i_init_clocks);
Hans de Goedeb0f2faa2014-12-17 18:18:14 +01001389CLK_OF_DECLARE(sun6i_a31s_clk_init, "allwinner,sun6i-a31s", sun6i_init_clocks);
Chen-Yu Tsai515c1a42014-06-26 23:55:43 +08001390CLK_OF_DECLARE(sun8i_a23_clk_init, "allwinner,sun8i-a23", sun6i_init_clocks);
Chen-Yu Tsai0b0f0802014-10-20 22:10:28 +08001391
1392static void __init sun9i_init_clocks(struct device_node *node)
1393{
1394 sunxi_init_clocks(NULL, 0);
1395}
1396CLK_OF_DECLARE(sun9i_a80_clk_init, "allwinner,sun9i-a80", sun9i_init_clocks);