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gerrit-public.fairphone.software / kernel / msm-4.9 / fb72bb21486269f71775a24d6dacf2576ea3edcc / . / arch / arm / boot / dts / imx6qdl.dtsi
blob: 98ab31ce71fd13aa96affff22b7e631323b26ca4 [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]14
15/ {
16 aliases {
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]17 gpio0 = &gpio1;
18 gpio1 = &gpio2;
19 gpio2 = &gpio3;
20 gpio3 = &gpio4;
21 gpio4 = &gpio5;
22 gpio5 = &gpio6;
23 gpio6 = &gpio7;
Sascha Hauer80fa0582013-06-25 15:51:57 +0200[diff] [blame]24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 serial0 = &uart1;
28 serial1 = &uart2;
29 serial2 = &uart3;
30 serial3 = &uart4;
31 serial4 = &uart5;
32 spi0 = &ecspi1;
33 spi1 = &ecspi2;
34 spi2 = &ecspi3;
35 spi3 = &ecspi4;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]36 };
37
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]38 intc: interrupt-controller@00a01000 {
39 compatible = "arm,cortex-a9-gic";
40 #interrupt-cells = <3>;
41 #address-cells = <1>;
42 #size-cells = <1>;
43 interrupt-controller;
44 reg = <0x00a01000 0x1000>,
45 <0x00a00100 0x100>;
46 };
47
48 clocks {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 ckil {
53 compatible = "fsl,imx-ckil", "fixed-clock";
54 clock-frequency = <32768>;
55 };
56
57 ckih1 {
58 compatible = "fsl,imx-ckih1", "fixed-clock";
59 clock-frequency = <0>;
60 };
61
62 osc {
63 compatible = "fsl,imx-osc", "fixed-clock";
64 clock-frequency = <24000000>;
65 };
66 };
67
68 soc {
69 #address-cells = <1>;
70 #size-cells = <1>;
71 compatible = "simple-bus";
72 interrupt-parent = <&intc>;
73 ranges;
74
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]75 dma_apbh: dma-apbh@00110000 {
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]76 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
77 reg = <0x00110000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]78 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
79 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
80 #dma-cells = <1>;
81 dma-channels = <4>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]82 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]83 };
84
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]85 gpmi: gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]86 compatible = "fsl,imx6q-gpmi-nand";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
90 reg-names = "gpmi-nand", "bch";
91 interrupts = <0 13 0x04>, <0 15 0x04>;
92 interrupt-names = "gpmi-dma", "bch";
93 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
94 <&clks 150>, <&clks 149>;
95 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
96 "gpmi_bch_apb", "per1_bch";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]97 dmas = <&dma_apbh 0>;
98 dma-names = "rx-tx";
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]99 fsl,gpmi-dma-channel = <0>;
100 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]101 };
102
Philipp Zabel481fbe12013-07-01 11:06:09 +0200[diff] [blame]103 ocram: sram@00900000 {
104 compatible = "mmio-sram";
105 reg = <0x00900000 0x3f000>;
106 clocks = <&clks 142>;
107 };
108
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]109 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]110 compatible = "arm,cortex-a9-twd-timer";
111 reg = <0x00a00600 0x20>;
112 interrupts = <1 13 0xf01>;
Shawn Guo2bb4b702013-04-03 23:50:09 +0800[diff] [blame]113 clocks = <&clks 15>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]114 };
115
116 L2: l2-cache@00a02000 {
117 compatible = "arm,pl310-cache";
118 reg = <0x00a02000 0x1000>;
119 interrupts = <0 92 0x04>;
120 cache-unified;
121 cache-level = <2>;
Dirk Behme5a5ca562013-04-26 10:13:55 +0200[diff] [blame]122 arm,tag-latency = <4 2 3>;
123 arm,data-latency = <4 2 3>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]124 };
125
Dirk Behme218abe62013-02-15 15:10:01 +0100[diff] [blame]126 pmu {
127 compatible = "arm,cortex-a9-pmu";
128 interrupts = <0 94 0x04>;
129 };
130
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]131 aips-bus@02000000 { /* AIPS1 */
132 compatible = "fsl,aips-bus", "simple-bus";
133 #address-cells = <1>;
134 #size-cells = <1>;
135 reg = <0x02000000 0x100000>;
136 ranges;
137
138 spba-bus@02000000 {
139 compatible = "fsl,spba-bus", "simple-bus";
140 #address-cells = <1>;
141 #size-cells = <1>;
142 reg = <0x02000000 0x40000>;
143 ranges;
144
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]145 spdif: spdif@02004000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]146 reg = <0x02004000 0x4000>;
147 interrupts = <0 52 0x04>;
148 };
149
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]150 ecspi1: ecspi@02008000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]151 #address-cells = <1>;
152 #size-cells = <0>;
153 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
154 reg = <0x02008000 0x4000>;
155 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]156 clocks = <&clks 112>, <&clks 112>;
157 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]158 status = "disabled";
159 };
160
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]161 ecspi2: ecspi@0200c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]162 #address-cells = <1>;
163 #size-cells = <0>;
164 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
165 reg = <0x0200c000 0x4000>;
166 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]167 clocks = <&clks 113>, <&clks 113>;
168 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]169 status = "disabled";
170 };
171
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]172 ecspi3: ecspi@02010000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]173 #address-cells = <1>;
174 #size-cells = <0>;
175 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
176 reg = <0x02010000 0x4000>;
177 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]178 clocks = <&clks 114>, <&clks 114>;
179 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]180 status = "disabled";
181 };
182
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]183 ecspi4: ecspi@02014000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]184 #address-cells = <1>;
185 #size-cells = <0>;
186 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
187 reg = <0x02014000 0x4000>;
188 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]189 clocks = <&clks 115>, <&clks 115>;
190 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]191 status = "disabled";
192 };
193
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]194 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]195 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
196 reg = <0x02020000 0x4000>;
197 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]198 clocks = <&clks 160>, <&clks 161>;
199 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]200 status = "disabled";
201 };
202
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]203 esai: esai@02024000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]204 reg = <0x02024000 0x4000>;
205 interrupts = <0 51 0x04>;
206 };
207
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]208 ssi1: ssi@02028000 {
209 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]210 reg = <0x02028000 0x4000>;
211 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]212 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]213 fsl,fifo-depth = <15>;
214 fsl,ssi-dma-events = <38 37>;
215 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]216 };
217
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]218 ssi2: ssi@0202c000 {
219 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]220 reg = <0x0202c000 0x4000>;
221 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]222 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]223 fsl,fifo-depth = <15>;
224 fsl,ssi-dma-events = <42 41>;
225 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]226 };
227
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]228 ssi3: ssi@02030000 {
229 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]230 reg = <0x02030000 0x4000>;
231 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]232 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]233 fsl,fifo-depth = <15>;
234 fsl,ssi-dma-events = <46 45>;
235 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]236 };
237
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]238 asrc: asrc@02034000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]239 reg = <0x02034000 0x4000>;
240 interrupts = <0 50 0x04>;
241 };
242
243 spba@0203c000 {
244 reg = <0x0203c000 0x4000>;
245 };
246 };
247
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]248 vpu: vpu@02040000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]249 reg = <0x02040000 0x3c000>;
250 interrupts = <0 3 0x04 0 12 0x04>;
251 };
252
253 aipstz@0207c000 { /* AIPSTZ1 */
254 reg = <0x0207c000 0x4000>;
255 };
256
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]257 pwm1: pwm@02080000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]258 #pwm-cells = <2>;
259 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]260 reg = <0x02080000 0x4000>;
261 interrupts = <0 83 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]262 clocks = <&clks 62>, <&clks 145>;
263 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]264 };
265
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]266 pwm2: pwm@02084000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]267 #pwm-cells = <2>;
268 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]269 reg = <0x02084000 0x4000>;
270 interrupts = <0 84 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]271 clocks = <&clks 62>, <&clks 146>;
272 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]273 };
274
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]275 pwm3: pwm@02088000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]276 #pwm-cells = <2>;
277 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]278 reg = <0x02088000 0x4000>;
279 interrupts = <0 85 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]280 clocks = <&clks 62>, <&clks 147>;
281 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]282 };
283
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]284 pwm4: pwm@0208c000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]285 #pwm-cells = <2>;
286 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]287 reg = <0x0208c000 0x4000>;
288 interrupts = <0 86 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]289 clocks = <&clks 62>, <&clks 148>;
290 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]291 };
292
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]293 can1: flexcan@02090000 {
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]294 compatible = "fsl,imx6q-flexcan";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]295 reg = <0x02090000 0x4000>;
296 interrupts = <0 110 0x04>;
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]297 clocks = <&clks 108>, <&clks 109>;
298 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]299 };
300
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]301 can2: flexcan@02094000 {
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]302 compatible = "fsl,imx6q-flexcan";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]303 reg = <0x02094000 0x4000>;
304 interrupts = <0 111 0x04>;
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]305 clocks = <&clks 110>, <&clks 111>;
306 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]307 };
308
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]309 gpt: gpt@02098000 {
Sascha Hauer97b108f2013-06-25 15:51:47 +0200[diff] [blame]310 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]311 reg = <0x02098000 0x4000>;
312 interrupts = <0 55 0x04>;
Sascha Hauer4efccad2013-03-14 13:09:01 +0100[diff] [blame]313 clocks = <&clks 119>, <&clks 120>;
314 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]315 };
316
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]317 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]318 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]319 reg = <0x0209c000 0x4000>;
320 interrupts = <0 66 0x04 0 67 0x04>;
321 gpio-controller;
322 #gpio-cells = <2>;
323 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]324 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]325 };
326
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]327 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]328 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]329 reg = <0x020a0000 0x4000>;
330 interrupts = <0 68 0x04 0 69 0x04>;
331 gpio-controller;
332 #gpio-cells = <2>;
333 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]334 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]335 };
336
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]337 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]338 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]339 reg = <0x020a4000 0x4000>;
340 interrupts = <0 70 0x04 0 71 0x04>;
341 gpio-controller;
342 #gpio-cells = <2>;
343 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]344 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]345 };
346
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]347 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]348 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]349 reg = <0x020a8000 0x4000>;
350 interrupts = <0 72 0x04 0 73 0x04>;
351 gpio-controller;
352 #gpio-cells = <2>;
353 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]354 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]355 };
356
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]357 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]358 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]359 reg = <0x020ac000 0x4000>;
360 interrupts = <0 74 0x04 0 75 0x04>;
361 gpio-controller;
362 #gpio-cells = <2>;
363 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]364 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]365 };
366
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]367 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]368 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]369 reg = <0x020b0000 0x4000>;
370 interrupts = <0 76 0x04 0 77 0x04>;
371 gpio-controller;
372 #gpio-cells = <2>;
373 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]374 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]375 };
376
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]377 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]378 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]379 reg = <0x020b4000 0x4000>;
380 interrupts = <0 78 0x04 0 79 0x04>;
381 gpio-controller;
382 #gpio-cells = <2>;
383 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]384 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]385 };
386
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]387 kpp: kpp@020b8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]388 reg = <0x020b8000 0x4000>;
389 interrupts = <0 82 0x04>;
390 };
391
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]392 wdog1: wdog@020bc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]393 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
394 reg = <0x020bc000 0x4000>;
395 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]396 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]397 };
398
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]399 wdog2: wdog@020c0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]400 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
401 reg = <0x020c0000 0x4000>;
402 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]403 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]404 status = "disabled";
405 };
406
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]407 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]408 compatible = "fsl,imx6q-ccm";
409 reg = <0x020c4000 0x4000>;
410 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]411 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]412 };
413
Dong Aishengbaa64152012-09-05 10:57:15 +0800[diff] [blame]414 anatop: anatop@020c8000 {
415 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]416 reg = <0x020c8000 0x1000>;
417 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]418
419 regulator-1p1@110 {
420 compatible = "fsl,anatop-regulator";
421 regulator-name = "vdd1p1";
422 regulator-min-microvolt = <800000>;
423 regulator-max-microvolt = <1375000>;
424 regulator-always-on;
425 anatop-reg-offset = <0x110>;
426 anatop-vol-bit-shift = <8>;
427 anatop-vol-bit-width = <5>;
428 anatop-min-bit-val = <4>;
429 anatop-min-voltage = <800000>;
430 anatop-max-voltage = <1375000>;
431 };
432
433 regulator-3p0@120 {
434 compatible = "fsl,anatop-regulator";
435 regulator-name = "vdd3p0";
436 regulator-min-microvolt = <2800000>;
437 regulator-max-microvolt = <3150000>;
438 regulator-always-on;
439 anatop-reg-offset = <0x120>;
440 anatop-vol-bit-shift = <8>;
441 anatop-vol-bit-width = <5>;
442 anatop-min-bit-val = <0>;
443 anatop-min-voltage = <2625000>;
444 anatop-max-voltage = <3400000>;
445 };
446
447 regulator-2p5@130 {
448 compatible = "fsl,anatop-regulator";
449 regulator-name = "vdd2p5";
450 regulator-min-microvolt = <2000000>;
451 regulator-max-microvolt = <2750000>;
452 regulator-always-on;
453 anatop-reg-offset = <0x130>;
454 anatop-vol-bit-shift = <8>;
455 anatop-vol-bit-width = <5>;
456 anatop-min-bit-val = <0>;
457 anatop-min-voltage = <2000000>;
458 anatop-max-voltage = <2750000>;
459 };
460
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]461 reg_arm: regulator-vddcore@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]462 compatible = "fsl,anatop-regulator";
463 regulator-name = "cpu";
464 regulator-min-microvolt = <725000>;
465 regulator-max-microvolt = <1450000>;
466 regulator-always-on;
467 anatop-reg-offset = <0x140>;
468 anatop-vol-bit-shift = <0>;
469 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]470 anatop-delay-reg-offset = <0x170>;
471 anatop-delay-bit-shift = <24>;
472 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]473 anatop-min-bit-val = <1>;
474 anatop-min-voltage = <725000>;
475 anatop-max-voltage = <1450000>;
476 };
477
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]478 reg_pu: regulator-vddpu@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]479 compatible = "fsl,anatop-regulator";
480 regulator-name = "vddpu";
481 regulator-min-microvolt = <725000>;
482 regulator-max-microvolt = <1450000>;
483 regulator-always-on;
484 anatop-reg-offset = <0x140>;
485 anatop-vol-bit-shift = <9>;
486 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]487 anatop-delay-reg-offset = <0x170>;
488 anatop-delay-bit-shift = <26>;
489 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]490 anatop-min-bit-val = <1>;
491 anatop-min-voltage = <725000>;
492 anatop-max-voltage = <1450000>;
493 };
494
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]495 reg_soc: regulator-vddsoc@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]496 compatible = "fsl,anatop-regulator";
497 regulator-name = "vddsoc";
498 regulator-min-microvolt = <725000>;
499 regulator-max-microvolt = <1450000>;
500 regulator-always-on;
501 anatop-reg-offset = <0x140>;
502 anatop-vol-bit-shift = <18>;
503 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]504 anatop-delay-reg-offset = <0x170>;
505 anatop-delay-bit-shift = <28>;
506 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]507 anatop-min-bit-val = <1>;
508 anatop-min-voltage = <725000>;
509 anatop-max-voltage = <1450000>;
510 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]511 };
512
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]513 usbphy1: usbphy@020c9000 {
514 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]515 reg = <0x020c9000 0x1000>;
516 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]517 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]518 };
519
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]520 usbphy2: usbphy@020ca000 {
521 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]522 reg = <0x020ca000 0x1000>;
523 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]524 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]525 };
526
527 snvs@020cc000 {
Shawn Guoc9250382012-07-02 20:13:03 +0800[diff] [blame]528 compatible = "fsl,sec-v4.0-mon", "simple-bus";
529 #address-cells = <1>;
530 #size-cells = <1>;
531 ranges = <0 0x020cc000 0x4000>;
532
533 snvs-rtc-lp@34 {
534 compatible = "fsl,sec-v4.0-mon-rtc-lp";
535 reg = <0x34 0x58>;
536 interrupts = <0 19 0x04 0 20 0x04>;
537 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]538 };
539
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]540 epit1: epit@020d0000 { /* EPIT1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]541 reg = <0x020d0000 0x4000>;
542 interrupts = <0 56 0x04>;
543 };
544
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]545 epit2: epit@020d4000 { /* EPIT2 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]546 reg = <0x020d4000 0x4000>;
547 interrupts = <0 57 0x04>;
548 };
549
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]550 src: src@020d8000 {
Philipp Zabelbd3d9242013-03-28 17:35:22 +0100[diff] [blame]551 compatible = "fsl,imx6q-src", "fsl,imx51-src";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]552 reg = <0x020d8000 0x4000>;
553 interrupts = <0 91 0x04 0 96 0x04>;
Philipp Zabel09ebf362013-03-28 17:35:20 +0100[diff] [blame]554 #reset-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]555 };
556
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]557 gpc: gpc@020dc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]558 compatible = "fsl,imx6q-gpc";
559 reg = <0x020dc000 0x4000>;
560 interrupts = <0 89 0x04 0 90 0x04>;
561 };
562
Dong Aishengdf37e0c2012-09-05 10:57:14 +0800[diff] [blame]563 gpr: iomuxc-gpr@020e0000 {
564 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
565 reg = <0x020e0000 0x38>;
566 };
567
Steffen Trumtrar41c04342013-03-28 16:23:35 +0100[diff] [blame]568 ldb: ldb@020e0008 {
569 #address-cells = <1>;
570 #size-cells = <0>;
571 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
572 gpr = <&gpr>;
573 status = "disabled";
574
575 lvds-channel@0 {
576 reg = <0>;
Steffen Trumtrar41c04342013-03-28 16:23:35 +0100[diff] [blame]577 status = "disabled";
578 };
579
580 lvds-channel@1 {
581 reg = <1>;
Steffen Trumtrar41c04342013-03-28 16:23:35 +0100[diff] [blame]582 status = "disabled";
583 };
584 };
585
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]586 dcic1: dcic@020e4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]587 reg = <0x020e4000 0x4000>;
588 interrupts = <0 124 0x04>;
589 };
590
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]591 dcic2: dcic@020e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]592 reg = <0x020e8000 0x4000>;
593 interrupts = <0 125 0x04>;
594 };
595
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]596 sdma: sdma@020ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]597 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
598 reg = <0x020ec000 0x4000>;
599 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]600 clocks = <&clks 155>, <&clks 155>;
601 clock-names = "ipg", "ahb";
Huang Shijiefb72bb22013-07-02 10:15:29 +0800[diff] [blame^]602 #dma-cells = <3>;
Fabio Estevamd6b9c592013-01-17 12:13:25 -0200[diff] [blame]603 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]604 };
605 };
606
607 aips-bus@02100000 { /* AIPS2 */
608 compatible = "fsl,aips-bus", "simple-bus";
609 #address-cells = <1>;
610 #size-cells = <1>;
611 reg = <0x02100000 0x100000>;
612 ranges;
613
614 caam@02100000 {
615 reg = <0x02100000 0x40000>;
616 interrupts = <0 105 0x04 0 106 0x04>;
617 };
618
619 aipstz@0217c000 { /* AIPSTZ2 */
620 reg = <0x0217c000 0x4000>;
621 };
622
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]623 usbotg: usb@02184000 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]624 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
625 reg = <0x02184000 0x200>;
626 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]627 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]628 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]629 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]630 status = "disabled";
631 };
632
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]633 usbh1: usb@02184200 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]634 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
635 reg = <0x02184200 0x200>;
636 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]637 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]638 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]639 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]640 status = "disabled";
641 };
642
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]643 usbh2: usb@02184400 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]644 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
645 reg = <0x02184400 0x200>;
646 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]647 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]648 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]649 status = "disabled";
650 };
651
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]652 usbh3: usb@02184600 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]653 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
654 reg = <0x02184600 0x200>;
655 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]656 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]657 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]658 status = "disabled";
659 };
660
Shawn Guo60984bd2013-04-28 09:59:54 +0800[diff] [blame]661 usbmisc: usbmisc@02184800 {
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]662 #index-cells = <1>;
663 compatible = "fsl,imx6q-usbmisc";
664 reg = <0x02184800 0x200>;
665 clocks = <&clks 162>;
666 };
667
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]668 fec: ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]669 compatible = "fsl,imx6q-fec";
670 reg = <0x02188000 0x4000>;
671 interrupts = <0 118 0x04 0 119 0x04>;
Frank Li8dd5c662013-02-05 14:21:06 +0800[diff] [blame]672 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
Frank Li76298382012-10-30 18:24:57 +0000[diff] [blame]673 clock-names = "ipg", "ahb", "ptp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]674 status = "disabled";
675 };
676
677 mlb@0218c000 {
678 reg = <0x0218c000 0x4000>;
679 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
680 };
681
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]682 usdhc1: usdhc@02190000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]683 compatible = "fsl,imx6q-usdhc";
684 reg = <0x02190000 0x4000>;
685 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]686 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
687 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]688 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]689 status = "disabled";
690 };
691
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]692 usdhc2: usdhc@02194000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]693 compatible = "fsl,imx6q-usdhc";
694 reg = <0x02194000 0x4000>;
695 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]696 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
697 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]698 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]699 status = "disabled";
700 };
701
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]702 usdhc3: usdhc@02198000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]703 compatible = "fsl,imx6q-usdhc";
704 reg = <0x02198000 0x4000>;
705 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]706 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
707 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]708 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]709 status = "disabled";
710 };
711
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]712 usdhc4: usdhc@0219c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]713 compatible = "fsl,imx6q-usdhc";
714 reg = <0x0219c000 0x4000>;
715 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]716 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
717 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]718 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]719 status = "disabled";
720 };
721
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]722 i2c1: i2c@021a0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]723 #address-cells = <1>;
724 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]725 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]726 reg = <0x021a0000 0x4000>;
727 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]728 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]729 status = "disabled";
730 };
731
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]732 i2c2: i2c@021a4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]733 #address-cells = <1>;
734 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]735 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]736 reg = <0x021a4000 0x4000>;
737 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]738 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]739 status = "disabled";
740 };
741
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]742 i2c3: i2c@021a8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]743 #address-cells = <1>;
744 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]745 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]746 reg = <0x021a8000 0x4000>;
747 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]748 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]749 status = "disabled";
750 };
751
752 romcp@021ac000 {
753 reg = <0x021ac000 0x4000>;
754 };
755
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]756 mmdc0: mmdc@021b0000 { /* MMDC0 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]757 compatible = "fsl,imx6q-mmdc";
758 reg = <0x021b0000 0x4000>;
759 };
760
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]761 mmdc1: mmdc@021b4000 { /* MMDC1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]762 reg = <0x021b4000 0x4000>;
763 };
764
Huang Shijie05e3f8e2013-05-28 14:20:09 +0800[diff] [blame]765 weim: weim@021b8000 {
766 compatible = "fsl,imx6q-weim";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]767 reg = <0x021b8000 0x4000>;
768 interrupts = <0 14 0x04>;
Huang Shijie05e3f8e2013-05-28 14:20:09 +0800[diff] [blame]769 clocks = <&clks 196>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]770 };
771
772 ocotp@021bc000 {
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]773 compatible = "fsl,imx6q-ocotp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]774 reg = <0x021bc000 0x4000>;
775 };
776
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]777 tzasc@021d0000 { /* TZASC1 */
778 reg = <0x021d0000 0x4000>;
779 interrupts = <0 108 0x04>;
780 };
781
782 tzasc@021d4000 { /* TZASC2 */
783 reg = <0x021d4000 0x4000>;
784 interrupts = <0 109 0x04>;
785 };
786
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]787 audmux: audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]788 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]789 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]790 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]791 };
792
793 mipi@021dc000 { /* MIPI-CSI */
794 reg = <0x021dc000 0x4000>;
795 };
796
797 mipi@021e0000 { /* MIPI-DSI */
798 reg = <0x021e0000 0x4000>;
799 };
800
801 vdoa@021e4000 {
802 reg = <0x021e4000 0x4000>;
803 interrupts = <0 18 0x04>;
804 };
805
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]806 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]807 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
808 reg = <0x021e8000 0x4000>;
809 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]810 clocks = <&clks 160>, <&clks 161>;
811 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]812 status = "disabled";
813 };
814
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]815 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]816 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
817 reg = <0x021ec000 0x4000>;
818 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]819 clocks = <&clks 160>, <&clks 161>;
820 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]821 status = "disabled";
822 };
823
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]824 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]825 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
826 reg = <0x021f0000 0x4000>;
827 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]828 clocks = <&clks 160>, <&clks 161>;
829 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]830 status = "disabled";
831 };
832
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]833 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]834 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
835 reg = <0x021f4000 0x4000>;
836 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]837 clocks = <&clks 160>, <&clks 161>;
838 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]839 status = "disabled";
840 };
841 };
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]842
843 ipu1: ipu@02400000 {
844 #crtc-cells = <1>;
845 compatible = "fsl,imx6q-ipu";
846 reg = <0x02400000 0x400000>;
847 interrupts = <0 6 0x4 0 5 0x4>;
848 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
849 clock-names = "bus", "di0", "di1";
Philipp Zabel09ebf362013-03-28 17:35:20 +0100[diff] [blame]850 resets = <&src 2>;
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]851 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]852 };
853};