Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1 | /* |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 2 | * Set up the interrupt priorities |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 3 | * |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 4 | * Copyright 2004-2009 Analog Devices Inc. |
| 5 | * 2003 Bas Vermeulen <bas@buyways.nl> |
| 6 | * 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca> |
| 7 | * 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca> |
| 8 | * 1999 D. Jeff Dionne <jeff@uclinux.org> |
| 9 | * 1996 Roman Zippel |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 10 | * |
Robin Getz | 96f1050 | 2009-09-24 14:11:24 +0000 | [diff] [blame] | 11 | * Licensed under the GPL-2 |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 12 | */ |
| 13 | |
| 14 | #include <linux/module.h> |
| 15 | #include <linux/kernel_stat.h> |
| 16 | #include <linux/seq_file.h> |
| 17 | #include <linux/irq.h> |
Philippe Gerum | 5b5da4c | 2011-03-17 02:12:48 -0400 | [diff] [blame] | 18 | #include <linux/sched.h> |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 19 | #include <linux/syscore_ops.h> |
| 20 | #include <asm/delay.h> |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 21 | #ifdef CONFIG_IPIPE |
| 22 | #include <linux/ipipe.h> |
| 23 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 24 | #include <asm/traps.h> |
| 25 | #include <asm/blackfin.h> |
| 26 | #include <asm/gpio.h> |
| 27 | #include <asm/irq_handler.h> |
Mike Frysinger | 761ec44 | 2009-10-15 17:12:05 +0000 | [diff] [blame] | 28 | #include <asm/dpmc.h> |
Sonic Zhang | 06051fd | 2012-07-04 19:22:55 +0800 | [diff] [blame] | 29 | #include <asm/traps.h> |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 30 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 31 | #ifndef SEC_GCTL |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 32 | # define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1)) |
| 33 | #else |
| 34 | # define SIC_SYSIRQ(irq) ((irq) - IVG15) |
| 35 | #endif |
Mike Frysinger | 7beb743 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 36 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 37 | /* |
| 38 | * NOTES: |
| 39 | * - we have separated the physical Hardware interrupt from the |
| 40 | * levels that the LINUX kernel sees (see the description in irq.h) |
| 41 | * - |
| 42 | */ |
| 43 | |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 44 | #ifndef CONFIG_SMP |
Mike Frysinger | a99bbcc | 2007-10-22 00:19:31 +0800 | [diff] [blame] | 45 | /* Initialize this to an actual value to force it into the .data |
| 46 | * section so that we know it is properly initialized at entry into |
| 47 | * the kernel but before bss is initialized to zero (which is where |
| 48 | * it would live otherwise). The 0x1f magic represents the IRQs we |
| 49 | * cannot actually mask out in hardware. |
| 50 | */ |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 51 | unsigned long bfin_irq_flags = 0x1f; |
| 52 | EXPORT_SYMBOL(bfin_irq_flags); |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 53 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 54 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 55 | #ifdef CONFIG_PM |
| 56 | unsigned long bfin_sic_iwr[3]; /* Up to 3 SIC_IWRx registers */ |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 57 | unsigned vr_wakeup; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 58 | #endif |
| 59 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 60 | #ifndef SEC_GCTL |
Mike Frysinger | e9e334c | 2011-03-30 00:43:52 -0400 | [diff] [blame] | 61 | static struct ivgx { |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 62 | /* irq number for request_irq, available in mach-bf5xx/irq.h */ |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 63 | unsigned int irqno; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 64 | /* corresponding bit in the SIC_ISR register */ |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 65 | unsigned int isrflag; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 66 | } ivg_table[NR_PERI_INTS]; |
| 67 | |
Mike Frysinger | e9e334c | 2011-03-30 00:43:52 -0400 | [diff] [blame] | 68 | static struct ivg_slice { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 69 | /* position of first irq in ivg_table for given ivg */ |
| 70 | struct ivgx *ifirst; |
| 71 | struct ivgx *istop; |
| 72 | } ivg7_13[IVG13 - IVG7 + 1]; |
| 73 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 74 | |
| 75 | /* |
| 76 | * Search SIC_IAR and fill tables with the irqvalues |
| 77 | * and their positions in the SIC_ISR register. |
| 78 | */ |
| 79 | static void __init search_IAR(void) |
| 80 | { |
| 81 | unsigned ivg, irq_pos = 0; |
| 82 | for (ivg = 0; ivg <= IVG13 - IVG7; ivg++) { |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 83 | int irqN; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 84 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 85 | ivg7_13[ivg].istop = ivg7_13[ivg].ifirst = &ivg_table[irq_pos]; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 86 | |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 87 | for (irqN = 0; irqN < NR_PERI_INTS; irqN += 4) { |
| 88 | int irqn; |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 89 | u32 iar = |
| 90 | bfin_read32((unsigned long *)SIC_IAR0 + |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 91 | #if defined(CONFIG_BF51x) || defined(CONFIG_BF52x) || \ |
| 92 | defined(CONFIG_BF538) || defined(CONFIG_BF539) |
| 93 | ((irqN % 32) >> 3) + ((irqN / 32) * ((SIC_IAR4 - SIC_IAR0) / 4)) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 94 | #else |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 95 | (irqN >> 3) |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 96 | #endif |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 97 | ); |
Mike Frysinger | 80fcdb9 | 2010-04-22 21:15:00 +0000 | [diff] [blame] | 98 | for (irqn = irqN; irqn < irqN + 4; ++irqn) { |
| 99 | int iar_shift = (irqn & 7) * 4; |
| 100 | if (ivg == (0xf & (iar >> iar_shift))) { |
| 101 | ivg_table[irq_pos].irqno = IVG7 + irqn; |
| 102 | ivg_table[irq_pos].isrflag = 1 << (irqn % 32); |
| 103 | ivg7_13[ivg].istop++; |
| 104 | irq_pos++; |
| 105 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 106 | } |
| 107 | } |
| 108 | } |
| 109 | } |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 110 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 111 | |
| 112 | /* |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 113 | * This is for core internal IRQs |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 114 | */ |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 115 | void bfin_ack_noop(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 116 | { |
| 117 | /* Dummy function. */ |
| 118 | } |
| 119 | |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame] | 120 | static void bfin_core_mask_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 121 | { |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame] | 122 | bfin_irq_flags &= ~(1 << d->irq); |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 123 | if (!hard_irqs_disabled()) |
| 124 | hard_local_irq_enable(); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 125 | } |
| 126 | |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame] | 127 | static void bfin_core_unmask_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 128 | { |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame] | 129 | bfin_irq_flags |= 1 << d->irq; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 130 | /* |
| 131 | * If interrupts are enabled, IMASK must contain the same value |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 132 | * as bfin_irq_flags. Make sure that invariant holds. If interrupts |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 133 | * are currently disabled we need not do anything; one of the |
| 134 | * callers will take care of setting IMASK to the proper value |
| 135 | * when reenabling interrupts. |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 136 | * local_irq_enable just does "STI bfin_irq_flags", so it's exactly |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 137 | * what we need. |
| 138 | */ |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 139 | if (!hard_irqs_disabled()) |
| 140 | hard_local_irq_enable(); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 141 | return; |
| 142 | } |
| 143 | |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 144 | void bfin_internal_mask_irq(unsigned int irq) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 145 | { |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 146 | unsigned long flags = hard_local_irq_save(); |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 147 | #ifndef SEC_GCTL |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 148 | #ifdef SIC_IMASK0 |
| 149 | unsigned mask_bank = SIC_SYSIRQ(irq) / 32; |
| 150 | unsigned mask_bit = SIC_SYSIRQ(irq) % 32; |
Bryan Wu | c04d66b | 2007-07-12 17:26:31 +0800 | [diff] [blame] | 151 | bfin_write_SIC_IMASK(mask_bank, bfin_read_SIC_IMASK(mask_bank) & |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 152 | ~(1 << mask_bit)); |
| 153 | # if defined(CONFIG_SMP) || defined(CONFIG_ICC) |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 154 | bfin_write_SICB_IMASK(mask_bank, bfin_read_SICB_IMASK(mask_bank) & |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 155 | ~(1 << mask_bit)); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 156 | # endif |
| 157 | #else |
| 158 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() & |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 159 | ~(1 << SIC_SYSIRQ(irq))); |
| 160 | #endif /* end of SIC_IMASK0 */ |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 161 | #endif |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 162 | hard_local_irq_restore(flags); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 163 | } |
| 164 | |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 165 | static void bfin_internal_mask_irq_chip(struct irq_data *d) |
| 166 | { |
| 167 | bfin_internal_mask_irq(d->irq); |
| 168 | } |
| 169 | |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 170 | #ifdef CONFIG_SMP |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 171 | void bfin_internal_unmask_irq_affinity(unsigned int irq, |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 172 | const struct cpumask *affinity) |
| 173 | #else |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 174 | void bfin_internal_unmask_irq(unsigned int irq) |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 175 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 176 | { |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 177 | unsigned long flags = hard_local_irq_save(); |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 178 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 179 | #ifndef SEC_GCTL |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 180 | #ifdef SIC_IMASK0 |
| 181 | unsigned mask_bank = SIC_SYSIRQ(irq) / 32; |
| 182 | unsigned mask_bit = SIC_SYSIRQ(irq) % 32; |
| 183 | # ifdef CONFIG_SMP |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 184 | if (cpumask_test_cpu(0, affinity)) |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 185 | # endif |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 186 | bfin_write_SIC_IMASK(mask_bank, |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 187 | bfin_read_SIC_IMASK(mask_bank) | |
| 188 | (1 << mask_bit)); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 189 | # ifdef CONFIG_SMP |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 190 | if (cpumask_test_cpu(1, affinity)) |
| 191 | bfin_write_SICB_IMASK(mask_bank, |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 192 | bfin_read_SICB_IMASK(mask_bank) | |
| 193 | (1 << mask_bit)); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 194 | # endif |
| 195 | #else |
| 196 | bfin_write_SIC_IMASK(bfin_read_SIC_IMASK() | |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 197 | (1 << SIC_SYSIRQ(irq))); |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 198 | #endif |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 199 | #endif |
| 200 | hard_local_irq_restore(flags); |
| 201 | } |
| 202 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 203 | #ifdef SEC_GCTL |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 204 | static void bfin_sec_preflow_handler(struct irq_data *d) |
| 205 | { |
| 206 | unsigned long flags = hard_local_irq_save(); |
| 207 | unsigned int sid = SIC_SYSIRQ(d->irq); |
| 208 | |
| 209 | bfin_write_SEC_SCI(0, SEC_CSID, sid); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 210 | |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 211 | hard_local_irq_restore(flags); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 212 | } |
| 213 | |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 214 | static void bfin_sec_mask_ack_irq(struct irq_data *d) |
| 215 | { |
| 216 | unsigned long flags = hard_local_irq_save(); |
| 217 | unsigned int sid = SIC_SYSIRQ(d->irq); |
| 218 | |
| 219 | bfin_write_SEC_SCI(0, SEC_CSID, sid); |
| 220 | |
| 221 | hard_local_irq_restore(flags); |
| 222 | } |
| 223 | |
| 224 | static void bfin_sec_unmask_irq(struct irq_data *d) |
| 225 | { |
| 226 | unsigned long flags = hard_local_irq_save(); |
| 227 | unsigned int sid = SIC_SYSIRQ(d->irq); |
| 228 | |
| 229 | bfin_write32(SEC_END, sid); |
| 230 | |
| 231 | hard_local_irq_restore(flags); |
| 232 | } |
| 233 | |
| 234 | static void bfin_sec_enable_ssi(unsigned int sid) |
| 235 | { |
| 236 | unsigned long flags = hard_local_irq_save(); |
| 237 | uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); |
| 238 | |
| 239 | reg_sctl |= SEC_SCTL_SRC_EN; |
| 240 | bfin_write_SEC_SCTL(sid, reg_sctl); |
| 241 | |
| 242 | hard_local_irq_restore(flags); |
| 243 | } |
| 244 | |
| 245 | static void bfin_sec_disable_ssi(unsigned int sid) |
| 246 | { |
| 247 | unsigned long flags = hard_local_irq_save(); |
| 248 | uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); |
| 249 | |
| 250 | reg_sctl &= ((uint32_t)~SEC_SCTL_SRC_EN); |
| 251 | bfin_write_SEC_SCTL(sid, reg_sctl); |
| 252 | |
| 253 | hard_local_irq_restore(flags); |
| 254 | } |
| 255 | |
| 256 | static void bfin_sec_set_ssi_coreid(unsigned int sid, unsigned int coreid) |
| 257 | { |
| 258 | unsigned long flags = hard_local_irq_save(); |
| 259 | uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); |
| 260 | |
| 261 | reg_sctl &= ((uint32_t)~SEC_SCTL_CTG); |
| 262 | bfin_write_SEC_SCTL(sid, reg_sctl | ((coreid << 20) & SEC_SCTL_CTG)); |
| 263 | |
| 264 | hard_local_irq_restore(flags); |
| 265 | } |
| 266 | |
| 267 | static void bfin_sec_enable_sci(unsigned int sid) |
| 268 | { |
| 269 | unsigned long flags = hard_local_irq_save(); |
| 270 | uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); |
| 271 | |
| 272 | if (sid == SIC_SYSIRQ(IRQ_WATCH0)) |
| 273 | reg_sctl |= SEC_SCTL_FAULT_EN; |
| 274 | else |
| 275 | reg_sctl |= SEC_SCTL_INT_EN; |
| 276 | bfin_write_SEC_SCTL(sid, reg_sctl); |
| 277 | |
| 278 | hard_local_irq_restore(flags); |
| 279 | } |
| 280 | |
| 281 | static void bfin_sec_disable_sci(unsigned int sid) |
| 282 | { |
| 283 | unsigned long flags = hard_local_irq_save(); |
| 284 | uint32_t reg_sctl = bfin_read_SEC_SCTL(sid); |
| 285 | |
| 286 | reg_sctl &= ((uint32_t)~SEC_SCTL_INT_EN); |
| 287 | bfin_write_SEC_SCTL(sid, reg_sctl); |
| 288 | |
| 289 | hard_local_irq_restore(flags); |
| 290 | } |
| 291 | |
| 292 | static void bfin_sec_enable(struct irq_data *d) |
| 293 | { |
| 294 | unsigned long flags = hard_local_irq_save(); |
| 295 | unsigned int sid = SIC_SYSIRQ(d->irq); |
| 296 | |
| 297 | bfin_sec_enable_sci(sid); |
| 298 | bfin_sec_enable_ssi(sid); |
| 299 | |
| 300 | hard_local_irq_restore(flags); |
| 301 | } |
| 302 | |
| 303 | static void bfin_sec_disable(struct irq_data *d) |
| 304 | { |
| 305 | unsigned long flags = hard_local_irq_save(); |
| 306 | unsigned int sid = SIC_SYSIRQ(d->irq); |
| 307 | |
| 308 | bfin_sec_disable_sci(sid); |
| 309 | bfin_sec_disable_ssi(sid); |
| 310 | |
| 311 | hard_local_irq_restore(flags); |
| 312 | } |
| 313 | |
Sonic Zhang | e0a5931 | 2012-06-29 18:19:29 +0800 | [diff] [blame] | 314 | static void bfin_sec_set_priority(unsigned int sec_int_levels, u8 *sec_int_priority) |
| 315 | { |
| 316 | unsigned long flags = hard_local_irq_save(); |
| 317 | uint32_t reg_sctl; |
| 318 | int i; |
| 319 | |
| 320 | bfin_write_SEC_SCI(0, SEC_CPLVL, sec_int_levels); |
| 321 | |
| 322 | for (i = 0; i < SYS_IRQS - BFIN_IRQ(0); i++) { |
| 323 | reg_sctl = bfin_read_SEC_SCTL(i) & ~SEC_SCTL_PRIO; |
| 324 | reg_sctl |= sec_int_priority[i] << SEC_SCTL_PRIO_OFFSET; |
| 325 | bfin_write_SEC_SCTL(i, reg_sctl); |
| 326 | } |
| 327 | |
| 328 | hard_local_irq_restore(flags); |
| 329 | } |
| 330 | |
Bob Liu | 719154c | 2012-07-23 14:59:36 +0800 | [diff] [blame] | 331 | void bfin_sec_raise_irq(unsigned int sid) |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 332 | { |
| 333 | unsigned long flags = hard_local_irq_save(); |
| 334 | |
| 335 | bfin_write32(SEC_RAISE, sid); |
| 336 | |
| 337 | hard_local_irq_restore(flags); |
| 338 | } |
| 339 | |
| 340 | static void init_software_driven_irq(void) |
| 341 | { |
| 342 | bfin_sec_set_ssi_coreid(34, 0); |
| 343 | bfin_sec_set_ssi_coreid(35, 1); |
| 344 | bfin_sec_set_ssi_coreid(36, 0); |
| 345 | bfin_sec_set_ssi_coreid(37, 1); |
| 346 | } |
| 347 | |
| 348 | void bfin_sec_resume(void) |
| 349 | { |
| 350 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); |
| 351 | udelay(100); |
| 352 | bfin_write_SEC_GCTL(SEC_GCTL_EN); |
| 353 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); |
| 354 | } |
| 355 | |
| 356 | void handle_sec_sfi_fault(uint32_t gstat) |
| 357 | { |
| 358 | |
| 359 | } |
| 360 | |
| 361 | void handle_sec_sci_fault(uint32_t gstat) |
| 362 | { |
| 363 | uint32_t core_id; |
| 364 | uint32_t cstat; |
| 365 | |
| 366 | core_id = gstat & SEC_GSTAT_SCI; |
| 367 | cstat = bfin_read_SEC_SCI(core_id, SEC_CSTAT); |
| 368 | if (cstat & SEC_CSTAT_ERR) { |
| 369 | switch (cstat & SEC_CSTAT_ERRC) { |
| 370 | case SEC_CSTAT_ACKERR: |
| 371 | printk(KERN_DEBUG "sec ack err\n"); |
| 372 | break; |
| 373 | default: |
| 374 | printk(KERN_DEBUG "sec sci unknow err\n"); |
| 375 | } |
| 376 | } |
| 377 | |
| 378 | } |
| 379 | |
| 380 | void handle_sec_ssi_fault(uint32_t gstat) |
| 381 | { |
| 382 | uint32_t sid; |
| 383 | uint32_t sstat; |
| 384 | |
| 385 | sid = gstat & SEC_GSTAT_SID; |
| 386 | sstat = bfin_read_SEC_SSTAT(sid); |
| 387 | |
| 388 | } |
| 389 | |
| 390 | void handle_sec_fault(unsigned int irq, struct irq_desc *desc) |
| 391 | { |
| 392 | uint32_t sec_gstat; |
| 393 | |
| 394 | raw_spin_lock(&desc->lock); |
| 395 | |
| 396 | sec_gstat = bfin_read32(SEC_GSTAT); |
| 397 | if (sec_gstat & SEC_GSTAT_ERR) { |
| 398 | |
| 399 | switch (sec_gstat & SEC_GSTAT_ERRC) { |
| 400 | case 0: |
| 401 | handle_sec_sfi_fault(sec_gstat); |
| 402 | break; |
| 403 | case SEC_GSTAT_SCIERR: |
| 404 | handle_sec_sci_fault(sec_gstat); |
| 405 | break; |
| 406 | case SEC_GSTAT_SSIERR: |
| 407 | handle_sec_ssi_fault(sec_gstat); |
| 408 | break; |
| 409 | } |
| 410 | |
| 411 | |
| 412 | } |
| 413 | |
| 414 | raw_spin_unlock(&desc->lock); |
| 415 | } |
| 416 | |
Sonic Zhang | 06051fd | 2012-07-04 19:22:55 +0800 | [diff] [blame] | 417 | void handle_core_fault(unsigned int irq, struct irq_desc *desc) |
| 418 | { |
| 419 | struct pt_regs *fp = get_irq_regs(); |
| 420 | |
| 421 | raw_spin_lock(&desc->lock); |
| 422 | |
| 423 | switch (irq) { |
| 424 | case IRQ_C0_DBL_FAULT: |
| 425 | double_fault_c(fp); |
| 426 | break; |
| 427 | case IRQ_C0_HW_ERR: |
| 428 | dump_bfin_process(fp); |
| 429 | dump_bfin_mem(fp); |
| 430 | show_regs(fp); |
| 431 | printk(KERN_NOTICE "Kernel Stack\n"); |
| 432 | show_stack(current, NULL); |
| 433 | print_modules(); |
| 434 | panic("Kernel core hardware error"); |
| 435 | break; |
| 436 | case IRQ_C0_NMI_L1_PARITY_ERR: |
Bob Liu | 719154c | 2012-07-23 14:59:36 +0800 | [diff] [blame] | 437 | panic("NMI occurs unexpectedly"); |
Sonic Zhang | 06051fd | 2012-07-04 19:22:55 +0800 | [diff] [blame] | 438 | break; |
| 439 | default: |
Bob Liu | 719154c | 2012-07-23 14:59:36 +0800 | [diff] [blame] | 440 | panic("Core 1 fault occurs unexpectedly"); |
Sonic Zhang | 06051fd | 2012-07-04 19:22:55 +0800 | [diff] [blame] | 441 | } |
| 442 | |
| 443 | raw_spin_unlock(&desc->lock); |
| 444 | } |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 445 | #endif |
| 446 | |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 447 | #ifdef CONFIG_SMP |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 448 | static void bfin_internal_unmask_irq_chip(struct irq_data *d) |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 449 | { |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 450 | bfin_internal_unmask_irq_affinity(d->irq, d->affinity); |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 451 | } |
| 452 | |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 453 | static int bfin_internal_set_affinity(struct irq_data *d, |
| 454 | const struct cpumask *mask, bool force) |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 455 | { |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 456 | bfin_internal_mask_irq(d->irq); |
| 457 | bfin_internal_unmask_irq_affinity(d->irq, mask); |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 458 | |
| 459 | return 0; |
| 460 | } |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 461 | #else |
| 462 | static void bfin_internal_unmask_irq_chip(struct irq_data *d) |
| 463 | { |
| 464 | bfin_internal_unmask_irq(d->irq); |
| 465 | } |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 466 | #endif |
| 467 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 468 | #if defined(CONFIG_PM) && !defined(SEC_GCTL) |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 469 | int bfin_internal_set_wake(unsigned int irq, unsigned int state) |
| 470 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 471 | u32 bank, bit, wakeup = 0; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 472 | unsigned long flags; |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 473 | bank = SIC_SYSIRQ(irq) / 32; |
| 474 | bit = SIC_SYSIRQ(irq) % 32; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 475 | |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 476 | switch (irq) { |
| 477 | #ifdef IRQ_RTC |
| 478 | case IRQ_RTC: |
| 479 | wakeup |= WAKE; |
| 480 | break; |
| 481 | #endif |
| 482 | #ifdef IRQ_CAN0_RX |
| 483 | case IRQ_CAN0_RX: |
| 484 | wakeup |= CANWE; |
| 485 | break; |
| 486 | #endif |
| 487 | #ifdef IRQ_CAN1_RX |
| 488 | case IRQ_CAN1_RX: |
| 489 | wakeup |= CANWE; |
| 490 | break; |
| 491 | #endif |
| 492 | #ifdef IRQ_USB_INT0 |
| 493 | case IRQ_USB_INT0: |
| 494 | wakeup |= USBWE; |
| 495 | break; |
| 496 | #endif |
Michael Hennerich | d310fb4 | 2008-08-28 17:32:01 +0800 | [diff] [blame] | 497 | #ifdef CONFIG_BF54x |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 498 | case IRQ_CNT: |
| 499 | wakeup |= ROTWE; |
| 500 | break; |
| 501 | #endif |
| 502 | default: |
| 503 | break; |
| 504 | } |
| 505 | |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 506 | flags = hard_local_irq_save(); |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 507 | |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 508 | if (state) { |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 509 | bfin_sic_iwr[bank] |= (1 << bit); |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 510 | vr_wakeup |= wakeup; |
| 511 | |
| 512 | } else { |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 513 | bfin_sic_iwr[bank] &= ~(1 << bit); |
Michael Hennerich | 4a88d0c | 2008-08-05 17:38:41 +0800 | [diff] [blame] | 514 | vr_wakeup &= ~wakeup; |
| 515 | } |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 516 | |
David Howells | 3b139cd | 2010-10-07 14:08:52 +0100 | [diff] [blame] | 517 | hard_local_irq_restore(flags); |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 518 | |
| 519 | return 0; |
| 520 | } |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 521 | |
| 522 | static int bfin_internal_set_wake_chip(struct irq_data *d, unsigned int state) |
| 523 | { |
| 524 | return bfin_internal_set_wake(d->irq, state); |
| 525 | } |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 526 | #else |
Bob Liu | 357351b | 2012-06-01 14:04:02 +0800 | [diff] [blame] | 527 | inline int bfin_internal_set_wake(unsigned int irq, unsigned int state) |
| 528 | { |
| 529 | return 0; |
| 530 | } |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 531 | # define bfin_internal_set_wake_chip NULL |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 532 | #endif |
| 533 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 534 | static struct irq_chip bfin_core_irqchip = { |
Graf Yang | 763e63c | 2008-10-08 17:08:15 +0800 | [diff] [blame] | 535 | .name = "CORE", |
Thomas Gleixner | 4f19ea4 | 2011-02-06 18:23:27 +0000 | [diff] [blame] | 536 | .irq_mask = bfin_core_mask_irq, |
| 537 | .irq_unmask = bfin_core_unmask_irq, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 538 | }; |
| 539 | |
| 540 | static struct irq_chip bfin_internal_irqchip = { |
Graf Yang | 763e63c | 2008-10-08 17:08:15 +0800 | [diff] [blame] | 541 | .name = "INTN", |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 542 | .irq_mask = bfin_internal_mask_irq_chip, |
| 543 | .irq_unmask = bfin_internal_unmask_irq_chip, |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 544 | .irq_disable = bfin_internal_mask_irq_chip, |
| 545 | .irq_enable = bfin_internal_unmask_irq_chip, |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 546 | #ifdef CONFIG_SMP |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 547 | .irq_set_affinity = bfin_internal_set_affinity, |
Sonic Zhang | 0325f25 | 2009-12-28 07:29:57 +0000 | [diff] [blame] | 548 | #endif |
Thomas Gleixner | ff43a67 | 2011-02-06 18:23:29 +0000 | [diff] [blame] | 549 | .irq_set_wake = bfin_internal_set_wake_chip, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 550 | }; |
| 551 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 552 | #ifdef SEC_GCTL |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 553 | static struct irq_chip bfin_sec_irqchip = { |
| 554 | .name = "SEC", |
| 555 | .irq_mask_ack = bfin_sec_mask_ack_irq, |
| 556 | .irq_mask = bfin_sec_mask_ack_irq, |
| 557 | .irq_unmask = bfin_sec_unmask_irq, |
| 558 | .irq_eoi = bfin_sec_unmask_irq, |
| 559 | .irq_disable = bfin_sec_disable, |
| 560 | .irq_enable = bfin_sec_enable, |
| 561 | }; |
| 562 | #endif |
| 563 | |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 564 | void bfin_handle_irq(unsigned irq) |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 565 | { |
| 566 | #ifdef CONFIG_IPIPE |
| 567 | struct pt_regs regs; /* Contents not used. */ |
| 568 | ipipe_trace_irq_entry(irq); |
| 569 | __ipipe_handle_irq(irq, ®s); |
| 570 | ipipe_trace_irq_exit(irq); |
| 571 | #else /* !CONFIG_IPIPE */ |
Thomas Gleixner | b10bbbb | 2011-02-06 18:23:25 +0000 | [diff] [blame] | 572 | generic_handle_irq(irq); |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 573 | #endif /* !CONFIG_IPIPE */ |
| 574 | } |
| 575 | |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 576 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
| 577 | static int mac_stat_int_mask; |
| 578 | |
| 579 | static void bfin_mac_status_ack_irq(unsigned int irq) |
| 580 | { |
| 581 | switch (irq) { |
| 582 | case IRQ_MAC_MMCINT: |
| 583 | bfin_write_EMAC_MMC_TIRQS( |
| 584 | bfin_read_EMAC_MMC_TIRQE() & |
| 585 | bfin_read_EMAC_MMC_TIRQS()); |
| 586 | bfin_write_EMAC_MMC_RIRQS( |
| 587 | bfin_read_EMAC_MMC_RIRQE() & |
| 588 | bfin_read_EMAC_MMC_RIRQS()); |
| 589 | break; |
| 590 | case IRQ_MAC_RXFSINT: |
| 591 | bfin_write_EMAC_RX_STKY( |
| 592 | bfin_read_EMAC_RX_IRQE() & |
| 593 | bfin_read_EMAC_RX_STKY()); |
| 594 | break; |
| 595 | case IRQ_MAC_TXFSINT: |
| 596 | bfin_write_EMAC_TX_STKY( |
| 597 | bfin_read_EMAC_TX_IRQE() & |
| 598 | bfin_read_EMAC_TX_STKY()); |
| 599 | break; |
| 600 | case IRQ_MAC_WAKEDET: |
| 601 | bfin_write_EMAC_WKUP_CTL( |
| 602 | bfin_read_EMAC_WKUP_CTL() | MPKS | RWKS); |
| 603 | break; |
| 604 | default: |
| 605 | /* These bits are W1C */ |
| 606 | bfin_write_EMAC_SYSTAT(1L << (irq - IRQ_MAC_PHYINT)); |
| 607 | break; |
| 608 | } |
| 609 | } |
| 610 | |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 611 | static void bfin_mac_status_mask_irq(struct irq_data *d) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 612 | { |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 613 | unsigned int irq = d->irq; |
| 614 | |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 615 | mac_stat_int_mask &= ~(1L << (irq - IRQ_MAC_PHYINT)); |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 616 | #ifdef BF537_FAMILY |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 617 | switch (irq) { |
| 618 | case IRQ_MAC_PHYINT: |
| 619 | bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() & ~PHYIE); |
| 620 | break; |
| 621 | default: |
| 622 | break; |
| 623 | } |
| 624 | #else |
| 625 | if (!mac_stat_int_mask) |
| 626 | bfin_internal_mask_irq(IRQ_MAC_ERROR); |
| 627 | #endif |
| 628 | bfin_mac_status_ack_irq(irq); |
| 629 | } |
| 630 | |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 631 | static void bfin_mac_status_unmask_irq(struct irq_data *d) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 632 | { |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 633 | unsigned int irq = d->irq; |
| 634 | |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 635 | #ifdef BF537_FAMILY |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 636 | switch (irq) { |
| 637 | case IRQ_MAC_PHYINT: |
| 638 | bfin_write_EMAC_SYSCTL(bfin_read_EMAC_SYSCTL() | PHYIE); |
| 639 | break; |
| 640 | default: |
| 641 | break; |
| 642 | } |
| 643 | #else |
| 644 | if (!mac_stat_int_mask) |
| 645 | bfin_internal_unmask_irq(IRQ_MAC_ERROR); |
| 646 | #endif |
| 647 | mac_stat_int_mask |= 1L << (irq - IRQ_MAC_PHYINT); |
| 648 | } |
| 649 | |
| 650 | #ifdef CONFIG_PM |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 651 | int bfin_mac_status_set_wake(struct irq_data *d, unsigned int state) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 652 | { |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 653 | #ifdef BF537_FAMILY |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 654 | return bfin_internal_set_wake(IRQ_GENERIC_ERROR, state); |
| 655 | #else |
| 656 | return bfin_internal_set_wake(IRQ_MAC_ERROR, state); |
| 657 | #endif |
| 658 | } |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 659 | #else |
| 660 | # define bfin_mac_status_set_wake NULL |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 661 | #endif |
| 662 | |
| 663 | static struct irq_chip bfin_mac_status_irqchip = { |
| 664 | .name = "MACST", |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 665 | .irq_mask = bfin_mac_status_mask_irq, |
| 666 | .irq_unmask = bfin_mac_status_unmask_irq, |
Thomas Gleixner | 172d2d1 | 2011-02-06 18:23:34 +0000 | [diff] [blame] | 667 | .irq_set_wake = bfin_mac_status_set_wake, |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 668 | }; |
| 669 | |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 670 | void bfin_demux_mac_status_irq(unsigned int int_err_irq, |
| 671 | struct irq_desc *inta_desc) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 672 | { |
| 673 | int i, irq = 0; |
| 674 | u32 status = bfin_read_EMAC_SYSTAT(); |
| 675 | |
Michael Hennerich | bedeea6 | 2010-08-20 11:59:27 +0000 | [diff] [blame] | 676 | for (i = 0; i <= (IRQ_MAC_STMDONE - IRQ_MAC_PHYINT); i++) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 677 | if (status & (1L << i)) { |
| 678 | irq = IRQ_MAC_PHYINT + i; |
| 679 | break; |
| 680 | } |
| 681 | |
| 682 | if (irq) { |
| 683 | if (mac_stat_int_mask & (1L << (irq - IRQ_MAC_PHYINT))) { |
| 684 | bfin_handle_irq(irq); |
| 685 | } else { |
| 686 | bfin_mac_status_ack_irq(irq); |
| 687 | pr_debug("IRQ %d:" |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 688 | " MASKED MAC ERROR INTERRUPT ASSERTED\n", |
| 689 | irq); |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 690 | } |
| 691 | } else |
| 692 | printk(KERN_ERR |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 693 | "%s : %s : LINE %d :\nIRQ ?: MAC ERROR" |
| 694 | " INTERRUPT ASSERTED BUT NO SOURCE FOUND" |
| 695 | "(EMAC_SYSTAT=0x%X)\n", |
| 696 | __func__, __FILE__, __LINE__, status); |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 697 | } |
| 698 | #endif |
| 699 | |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 700 | static inline void bfin_set_irq_handler(unsigned irq, irq_flow_handler_t handle) |
| 701 | { |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 702 | #ifdef CONFIG_IPIPE |
Philippe Gerum | 5b5da4c | 2011-03-17 02:12:48 -0400 | [diff] [blame] | 703 | handle = handle_level_irq; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 704 | #endif |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 705 | __irq_set_handler_locked(irq, handle); |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 706 | } |
| 707 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 708 | static DECLARE_BITMAP(gpio_enabled, MAX_BLACKFIN_GPIOS); |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 709 | extern void bfin_gpio_irq_prepare(unsigned gpio); |
Michael Hennerich | 6fce6a8 | 2007-12-24 16:56:12 +0800 | [diff] [blame] | 710 | |
Mike Frysinger | 01f8e34 | 2011-06-26 13:56:23 -0400 | [diff] [blame] | 711 | #if !BFIN_GPIO_PINT |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 712 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 713 | static void bfin_gpio_ack_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 714 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 715 | /* AFAIK ack_irq in case mask_ack is provided |
| 716 | * get's only called for edge sense irqs |
| 717 | */ |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 718 | set_gpio_data(irq_to_gpio(d->irq), 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 719 | } |
| 720 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 721 | static void bfin_gpio_mask_ack_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 722 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 723 | unsigned int irq = d->irq; |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 724 | u32 gpionr = irq_to_gpio(irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 725 | |
Thomas Gleixner | 1907d8b | 2011-03-24 17:21:01 +0100 | [diff] [blame] | 726 | if (!irqd_is_level_type(d)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 727 | set_gpio_data(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 728 | |
| 729 | set_gpio_maska(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 730 | } |
| 731 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 732 | static void bfin_gpio_mask_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 733 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 734 | set_gpio_maska(irq_to_gpio(d->irq), 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 735 | } |
| 736 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 737 | static void bfin_gpio_unmask_irq(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 738 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 739 | set_gpio_maska(irq_to_gpio(d->irq), 1); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 740 | } |
| 741 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 742 | static unsigned int bfin_gpio_irq_startup(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 743 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 744 | u32 gpionr = irq_to_gpio(d->irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 745 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 746 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 747 | bfin_gpio_irq_prepare(gpionr); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 748 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 749 | bfin_gpio_unmask_irq(d); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 750 | |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 751 | return 0; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 752 | } |
| 753 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 754 | static void bfin_gpio_irq_shutdown(struct irq_data *d) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 755 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 756 | u32 gpionr = irq_to_gpio(d->irq); |
Graf Yang | 30af6d4 | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 757 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 758 | bfin_gpio_mask_irq(d); |
Graf Yang | 30af6d4 | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 759 | __clear_bit(gpionr, gpio_enabled); |
Graf Yang | 9570ff4 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 760 | bfin_gpio_irq_free(gpionr); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 761 | } |
| 762 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 763 | static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 764 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 765 | unsigned int irq = d->irq; |
Graf Yang | 8eb3e3b | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 766 | int ret; |
| 767 | char buf[16]; |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 768 | u32 gpionr = irq_to_gpio(irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 769 | |
| 770 | if (type == IRQ_TYPE_PROBE) { |
| 771 | /* only probe unenabled GPIO interrupt lines */ |
Mike Frysinger | c369534 | 2009-06-13 10:32:29 -0400 | [diff] [blame] | 772 | if (test_bit(gpionr, gpio_enabled)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 773 | return 0; |
| 774 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 775 | } |
| 776 | |
| 777 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 778 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 779 | |
Graf Yang | 9570ff4 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 780 | snprintf(buf, 16, "gpio-irq%d", irq); |
| 781 | ret = bfin_gpio_irq_request(gpionr, buf); |
| 782 | if (ret) |
| 783 | return ret; |
| 784 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 785 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 786 | bfin_gpio_irq_prepare(gpionr); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 787 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 788 | } else { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 789 | __clear_bit(gpionr, gpio_enabled); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 790 | return 0; |
| 791 | } |
| 792 | |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 793 | set_gpio_inen(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 794 | set_gpio_dir(gpionr, 0); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 795 | |
| 796 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 797 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 798 | set_gpio_both(gpionr, 1); |
| 799 | else |
| 800 | set_gpio_both(gpionr, 0); |
| 801 | |
| 802 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) |
| 803 | set_gpio_polar(gpionr, 1); /* low or falling edge denoted by one */ |
| 804 | else |
| 805 | set_gpio_polar(gpionr, 0); /* high or rising edge denoted by zero */ |
| 806 | |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 807 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 808 | set_gpio_edge(gpionr, 1); |
| 809 | set_gpio_inen(gpionr, 1); |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 810 | set_gpio_data(gpionr, 0); |
| 811 | |
| 812 | } else { |
| 813 | set_gpio_edge(gpionr, 0); |
Michael Hennerich | f1bceb4 | 2008-02-02 16:17:52 +0800 | [diff] [blame] | 814 | set_gpio_inen(gpionr, 1); |
| 815 | } |
| 816 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 817 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 818 | bfin_set_irq_handler(irq, handle_edge_irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 819 | else |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 820 | bfin_set_irq_handler(irq, handle_level_irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 821 | |
| 822 | return 0; |
| 823 | } |
| 824 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 825 | #ifdef CONFIG_PM |
Mike Frysinger | dd8cb37 | 2011-04-15 03:19:22 -0400 | [diff] [blame] | 826 | static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 827 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 828 | return gpio_pm_wakeup_ctrl(irq_to_gpio(d->irq), state); |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 829 | } |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 830 | #else |
| 831 | # define bfin_gpio_set_wake NULL |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 832 | #endif |
| 833 | |
Mike Frysinger | e2a8092 | 2011-04-15 12:51:33 -0400 | [diff] [blame] | 834 | static void bfin_demux_gpio_block(unsigned int irq) |
| 835 | { |
| 836 | unsigned int gpio, mask; |
| 837 | |
| 838 | gpio = irq_to_gpio(irq); |
| 839 | mask = get_gpiop_data(gpio) & get_gpiop_maska(gpio); |
| 840 | |
| 841 | while (mask) { |
| 842 | if (mask & 1) |
| 843 | bfin_handle_irq(irq); |
| 844 | irq++; |
| 845 | mask >>= 1; |
| 846 | } |
| 847 | } |
| 848 | |
Mike Frysinger | 8c05410 | 2011-04-15 13:04:59 -0400 | [diff] [blame] | 849 | void bfin_demux_gpio_irq(unsigned int inta_irq, |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 850 | struct irq_desc *desc) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 851 | { |
Mike Frysinger | e2a8092 | 2011-04-15 12:51:33 -0400 | [diff] [blame] | 852 | unsigned int irq; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 853 | |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 854 | switch (inta_irq) { |
Mike Frysinger | e2a8092 | 2011-04-15 12:51:33 -0400 | [diff] [blame] | 855 | #if defined(BF537_FAMILY) |
Mike Frysinger | 8c05410 | 2011-04-15 13:04:59 -0400 | [diff] [blame] | 856 | case IRQ_PF_INTA_PG_INTA: |
Mike Frysinger | e2a8092 | 2011-04-15 12:51:33 -0400 | [diff] [blame] | 857 | bfin_demux_gpio_block(IRQ_PF0); |
| 858 | irq = IRQ_PG0; |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 859 | break; |
Mike Frysinger | 8c05410 | 2011-04-15 13:04:59 -0400 | [diff] [blame] | 860 | case IRQ_PH_INTA_MAC_RX: |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 861 | irq = IRQ_PH0; |
| 862 | break; |
Mike Frysinger | e2a8092 | 2011-04-15 12:51:33 -0400 | [diff] [blame] | 863 | #elif defined(BF533_FAMILY) |
| 864 | case IRQ_PROG_INTA: |
| 865 | irq = IRQ_PF0; |
| 866 | break; |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 867 | #elif defined(BF538_FAMILY) |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 868 | case IRQ_PORTF_INTA: |
| 869 | irq = IRQ_PF0; |
| 870 | break; |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 871 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 872 | case IRQ_PORTF_INTA: |
| 873 | irq = IRQ_PF0; |
| 874 | break; |
| 875 | case IRQ_PORTG_INTA: |
| 876 | irq = IRQ_PG0; |
| 877 | break; |
| 878 | case IRQ_PORTH_INTA: |
| 879 | irq = IRQ_PH0; |
| 880 | break; |
| 881 | #elif defined(CONFIG_BF561) |
| 882 | case IRQ_PROG0_INTA: |
| 883 | irq = IRQ_PF0; |
| 884 | break; |
| 885 | case IRQ_PROG1_INTA: |
| 886 | irq = IRQ_PF16; |
| 887 | break; |
| 888 | case IRQ_PROG2_INTA: |
| 889 | irq = IRQ_PF32; |
| 890 | break; |
| 891 | #endif |
| 892 | default: |
| 893 | BUG(); |
| 894 | return; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 895 | } |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 896 | |
Mike Frysinger | e2a8092 | 2011-04-15 12:51:33 -0400 | [diff] [blame] | 897 | bfin_demux_gpio_block(irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 898 | } |
| 899 | |
Mike Frysinger | 01f8e34 | 2011-06-26 13:56:23 -0400 | [diff] [blame] | 900 | #else |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 901 | |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 902 | #define NR_PINT_BITS 32 |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 903 | #define IRQ_NOT_AVAIL 0xFF |
| 904 | |
| 905 | #define PINT_2_BANK(x) ((x) >> 5) |
| 906 | #define PINT_2_BIT(x) ((x) & 0x1F) |
| 907 | #define PINT_BIT(x) (1 << (PINT_2_BIT(x))) |
| 908 | |
| 909 | static unsigned char irq2pint_lut[NR_PINTS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 910 | static unsigned char pint2irq_lut[NR_PINT_SYS_IRQS * NR_PINT_BITS]; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 911 | |
Mike Frysinger | 82ed5f7 | 2011-06-26 13:22:05 -0400 | [diff] [blame] | 912 | static struct bfin_pint_regs * const pint[NR_PINT_SYS_IRQS] = { |
| 913 | (struct bfin_pint_regs *)PINT0_MASK_SET, |
| 914 | (struct bfin_pint_regs *)PINT1_MASK_SET, |
| 915 | (struct bfin_pint_regs *)PINT2_MASK_SET, |
| 916 | (struct bfin_pint_regs *)PINT3_MASK_SET, |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 917 | #ifdef CONFIG_BF60x |
| 918 | (struct bfin_pint_regs *)PINT4_MASK_SET, |
| 919 | (struct bfin_pint_regs *)PINT5_MASK_SET, |
| 920 | #endif |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 921 | }; |
| 922 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 923 | inline unsigned int get_irq_base(u32 bank, u8 bmap) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 924 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 925 | unsigned int irq_base; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 926 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 927 | #ifndef CONFIG_BF60x |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 928 | if (bank < 2) { /*PA-PB */ |
| 929 | irq_base = IRQ_PA0 + bmap * 16; |
| 930 | } else { /*PC-PJ */ |
| 931 | irq_base = IRQ_PC0 + bmap * 16; |
| 932 | } |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 933 | #else |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 934 | irq_base = IRQ_PA0 + bank * 16 + bmap * 16; |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 935 | #endif |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 936 | return irq_base; |
| 937 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 938 | |
| 939 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| 940 | void init_pint_lut(void) |
| 941 | { |
| 942 | u16 bank, bit, irq_base, bit_pos; |
| 943 | u32 pint_assign; |
| 944 | u8 bmap; |
| 945 | |
| 946 | memset(irq2pint_lut, IRQ_NOT_AVAIL, sizeof(irq2pint_lut)); |
| 947 | |
| 948 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { |
| 949 | |
| 950 | pint_assign = pint[bank]->assign; |
| 951 | |
| 952 | for (bit = 0; bit < NR_PINT_BITS; bit++) { |
| 953 | |
| 954 | bmap = (pint_assign >> ((bit / 8) * 8)) & 0xFF; |
| 955 | |
| 956 | irq_base = get_irq_base(bank, bmap); |
| 957 | |
| 958 | irq_base += (bit % 8) + ((bit / 8) & 1 ? 8 : 0); |
| 959 | bit_pos = bit + bank * NR_PINT_BITS; |
| 960 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 961 | pint2irq_lut[bit_pos] = irq_base - SYS_IRQS; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 962 | irq2pint_lut[irq_base - SYS_IRQS] = bit_pos; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 963 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 964 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 965 | } |
| 966 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 967 | static void bfin_gpio_ack_irq(struct irq_data *d) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 968 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 969 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 970 | u32 pintbit = PINT_BIT(pint_val); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 971 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 972 | |
Thomas Gleixner | 1907d8b | 2011-03-24 17:21:01 +0100 | [diff] [blame] | 973 | if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 974 | if (pint[bank]->invert_set & pintbit) |
| 975 | pint[bank]->invert_clear = pintbit; |
| 976 | else |
| 977 | pint[bank]->invert_set = pintbit; |
| 978 | } |
| 979 | pint[bank]->request = pintbit; |
| 980 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 981 | } |
| 982 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 983 | static void bfin_gpio_mask_ack_irq(struct irq_data *d) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 984 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 985 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 986 | u32 pintbit = PINT_BIT(pint_val); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 987 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 988 | |
Thomas Gleixner | 1907d8b | 2011-03-24 17:21:01 +0100 | [diff] [blame] | 989 | if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) { |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 990 | if (pint[bank]->invert_set & pintbit) |
| 991 | pint[bank]->invert_clear = pintbit; |
| 992 | else |
| 993 | pint[bank]->invert_set = pintbit; |
| 994 | } |
| 995 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 996 | pint[bank]->request = pintbit; |
| 997 | pint[bank]->mask_clear = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 998 | } |
| 999 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1000 | static void bfin_gpio_mask_irq(struct irq_data *d) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1001 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1002 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1003 | |
| 1004 | pint[PINT_2_BANK(pint_val)]->mask_clear = PINT_BIT(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1005 | } |
| 1006 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1007 | static void bfin_gpio_unmask_irq(struct irq_data *d) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1008 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1009 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1010 | u32 pintbit = PINT_BIT(pint_val); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1011 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1012 | |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1013 | pint[bank]->mask_set = pintbit; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1014 | } |
| 1015 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1016 | static unsigned int bfin_gpio_irq_startup(struct irq_data *d) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1017 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1018 | unsigned int irq = d->irq; |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1019 | u32 gpionr = irq_to_gpio(irq); |
| 1020 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1021 | |
Michael Hennerich | 50e163c | 2007-07-24 16:17:28 +0800 | [diff] [blame] | 1022 | if (pint_val == IRQ_NOT_AVAIL) { |
| 1023 | printk(KERN_ERR |
| 1024 | "GPIO IRQ %d :Not in PINT Assign table " |
| 1025 | "Reconfigure Interrupt to Port Assignemt\n", irq); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1026 | return -ENODEV; |
Michael Hennerich | 50e163c | 2007-07-24 16:17:28 +0800 | [diff] [blame] | 1027 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1028 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1029 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 1030 | bfin_gpio_irq_prepare(gpionr); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1031 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1032 | bfin_gpio_unmask_irq(d); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1033 | |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 1034 | return 0; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1035 | } |
| 1036 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1037 | static void bfin_gpio_irq_shutdown(struct irq_data *d) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1038 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1039 | u32 gpionr = irq_to_gpio(d->irq); |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1040 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1041 | bfin_gpio_mask_irq(d); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1042 | __clear_bit(gpionr, gpio_enabled); |
Graf Yang | 9570ff4 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 1043 | bfin_gpio_irq_free(gpionr); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1044 | } |
| 1045 | |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1046 | static int bfin_gpio_irq_type(struct irq_data *d, unsigned int type) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1047 | { |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1048 | unsigned int irq = d->irq; |
Graf Yang | 8eb3e3b | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1049 | int ret; |
| 1050 | char buf[16]; |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1051 | u32 gpionr = irq_to_gpio(irq); |
| 1052 | u32 pint_val = irq2pint_lut[irq - SYS_IRQS]; |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1053 | u32 pintbit = PINT_BIT(pint_val); |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1054 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1055 | |
| 1056 | if (pint_val == IRQ_NOT_AVAIL) |
| 1057 | return -ENODEV; |
| 1058 | |
| 1059 | if (type == IRQ_TYPE_PROBE) { |
| 1060 | /* only probe unenabled GPIO interrupt lines */ |
Mike Frysinger | c369534 | 2009-06-13 10:32:29 -0400 | [diff] [blame] | 1061 | if (test_bit(gpionr, gpio_enabled)) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1062 | return 0; |
| 1063 | type = IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING; |
| 1064 | } |
| 1065 | |
| 1066 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING | |
| 1067 | IRQ_TYPE_LEVEL_HIGH | IRQ_TYPE_LEVEL_LOW)) { |
Graf Yang | 9570ff4 | 2009-01-07 23:14:38 +0800 | [diff] [blame] | 1068 | |
| 1069 | snprintf(buf, 16, "gpio-irq%d", irq); |
| 1070 | ret = bfin_gpio_irq_request(gpionr, buf); |
| 1071 | if (ret) |
| 1072 | return ret; |
| 1073 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1074 | if (__test_and_set_bit(gpionr, gpio_enabled)) |
Michael Hennerich | affee2b | 2008-04-24 08:10:10 +0800 | [diff] [blame] | 1075 | bfin_gpio_irq_prepare(gpionr); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1076 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1077 | } else { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1078 | __clear_bit(gpionr, gpio_enabled); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1079 | return 0; |
| 1080 | } |
| 1081 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1082 | if ((type & (IRQ_TYPE_EDGE_FALLING | IRQ_TYPE_LEVEL_LOW))) |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1083 | pint[bank]->invert_set = pintbit; /* low or falling edge denoted by one */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1084 | else |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1085 | pint[bank]->invert_clear = pintbit; /* high or rising edge denoted by zero */ |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1086 | |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1087 | if ((type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) |
| 1088 | == (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1089 | if (gpio_get_value(gpionr)) |
| 1090 | pint[bank]->invert_set = pintbit; |
| 1091 | else |
| 1092 | pint[bank]->invert_clear = pintbit; |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1093 | } |
| 1094 | |
| 1095 | if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) { |
| 1096 | pint[bank]->edge_set = pintbit; |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 1097 | bfin_set_irq_handler(irq, handle_edge_irq); |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1098 | } else { |
| 1099 | pint[bank]->edge_clear = pintbit; |
Graf Yang | bfd1511 | 2008-10-08 18:02:44 +0800 | [diff] [blame] | 1100 | bfin_set_irq_handler(irq, handle_level_irq); |
Michael Hennerich | 8baf560 | 2007-12-24 18:51:34 +0800 | [diff] [blame] | 1101 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1102 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1103 | return 0; |
| 1104 | } |
| 1105 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1106 | #ifdef CONFIG_PM |
Steven Miao | d49cdf840 | 2012-06-14 18:04:01 +0800 | [diff] [blame] | 1107 | static struct bfin_pm_pint_save save_pint_reg[NR_PINT_SYS_IRQS]; |
| 1108 | static u32 save_pint_sec_ctl[NR_PINT_SYS_IRQS]; |
| 1109 | |
Mike Frysinger | dd8cb37 | 2011-04-15 03:19:22 -0400 | [diff] [blame] | 1110 | static int bfin_gpio_set_wake(struct irq_data *d, unsigned int state) |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1111 | { |
| 1112 | u32 pint_irq; |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1113 | u32 pint_val = irq2pint_lut[d->irq - SYS_IRQS]; |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1114 | u32 bank = PINT_2_BANK(pint_val); |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1115 | |
| 1116 | switch (bank) { |
| 1117 | case 0: |
| 1118 | pint_irq = IRQ_PINT0; |
| 1119 | break; |
| 1120 | case 2: |
| 1121 | pint_irq = IRQ_PINT2; |
| 1122 | break; |
| 1123 | case 3: |
| 1124 | pint_irq = IRQ_PINT3; |
| 1125 | break; |
| 1126 | case 1: |
| 1127 | pint_irq = IRQ_PINT1; |
| 1128 | break; |
Bob Liu | 494b794 | 2012-04-27 14:13:01 +0800 | [diff] [blame] | 1129 | #ifdef CONFIG_BF60x |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1130 | case 4: |
| 1131 | pint_irq = IRQ_PINT4; |
| 1132 | break; |
| 1133 | case 5: |
| 1134 | pint_irq = IRQ_PINT5; |
| 1135 | break; |
Bob Liu | 494b794 | 2012-04-27 14:13:01 +0800 | [diff] [blame] | 1136 | #endif |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1137 | default: |
| 1138 | return -EINVAL; |
| 1139 | } |
| 1140 | |
| 1141 | bfin_internal_set_wake(pint_irq, state); |
| 1142 | |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1143 | return 0; |
| 1144 | } |
Steven Miao | d49cdf840 | 2012-06-14 18:04:01 +0800 | [diff] [blame] | 1145 | |
| 1146 | void bfin_pint_suspend(void) |
| 1147 | { |
| 1148 | u32 bank; |
| 1149 | |
| 1150 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { |
| 1151 | save_pint_reg[bank].mask_set = pint[bank]->mask_set; |
| 1152 | save_pint_reg[bank].assign = pint[bank]->assign; |
| 1153 | save_pint_reg[bank].edge_set = pint[bank]->edge_set; |
| 1154 | save_pint_reg[bank].invert_set = pint[bank]->invert_set; |
| 1155 | } |
| 1156 | } |
| 1157 | |
| 1158 | void bfin_pint_resume(void) |
| 1159 | { |
| 1160 | u32 bank; |
| 1161 | |
| 1162 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) { |
| 1163 | pint[bank]->mask_set = save_pint_reg[bank].mask_set; |
| 1164 | pint[bank]->assign = save_pint_reg[bank].assign; |
| 1165 | pint[bank]->edge_set = save_pint_reg[bank].edge_set; |
| 1166 | pint[bank]->invert_set = save_pint_reg[bank].invert_set; |
| 1167 | } |
| 1168 | } |
| 1169 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1170 | #ifdef SEC_GCTL |
Steven Miao | d49cdf840 | 2012-06-14 18:04:01 +0800 | [diff] [blame] | 1171 | static int sec_suspend(void) |
| 1172 | { |
| 1173 | u32 bank; |
| 1174 | |
| 1175 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) |
| 1176 | save_pint_sec_ctl[bank] = bfin_read_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0)); |
| 1177 | return 0; |
| 1178 | } |
| 1179 | |
| 1180 | static void sec_resume(void) |
| 1181 | { |
| 1182 | u32 bank; |
| 1183 | |
| 1184 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); |
| 1185 | udelay(100); |
| 1186 | bfin_write_SEC_GCTL(SEC_GCTL_EN); |
| 1187 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); |
| 1188 | |
| 1189 | for (bank = 0; bank < NR_PINT_SYS_IRQS; bank++) |
| 1190 | bfin_write_SEC_SCTL(bank + SIC_SYSIRQ(IRQ_PINT0), save_pint_sec_ctl[bank]); |
| 1191 | } |
| 1192 | |
| 1193 | static struct syscore_ops sec_pm_syscore_ops = { |
| 1194 | .suspend = sec_suspend, |
| 1195 | .resume = sec_resume, |
| 1196 | }; |
Steven Miao | 3375a43 | 2012-06-15 12:59:19 +0800 | [diff] [blame] | 1197 | #endif |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1198 | #else |
| 1199 | # define bfin_gpio_set_wake NULL |
Michael Hennerich | cfefe3c | 2008-02-09 04:12:37 +0800 | [diff] [blame] | 1200 | #endif |
| 1201 | |
Mike Frysinger | 8c05410 | 2011-04-15 13:04:59 -0400 | [diff] [blame] | 1202 | void bfin_demux_gpio_irq(unsigned int inta_irq, |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1203 | struct irq_desc *desc) |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1204 | { |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1205 | u32 bank, pint_val; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1206 | u32 request, irq; |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1207 | u32 level_mask; |
| 1208 | int umask = 0; |
| 1209 | struct irq_chip *chip = irq_desc_get_chip(desc); |
| 1210 | |
| 1211 | if (chip->irq_mask_ack) { |
| 1212 | chip->irq_mask_ack(&desc->irq_data); |
| 1213 | } else { |
| 1214 | chip->irq_mask(&desc->irq_data); |
| 1215 | if (chip->irq_ack) |
| 1216 | chip->irq_ack(&desc->irq_data); |
| 1217 | } |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1218 | |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 1219 | switch (inta_irq) { |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1220 | case IRQ_PINT0: |
| 1221 | bank = 0; |
| 1222 | break; |
| 1223 | case IRQ_PINT2: |
| 1224 | bank = 2; |
| 1225 | break; |
| 1226 | case IRQ_PINT3: |
| 1227 | bank = 3; |
| 1228 | break; |
| 1229 | case IRQ_PINT1: |
| 1230 | bank = 1; |
| 1231 | break; |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1232 | #ifdef CONFIG_BF60x |
| 1233 | case IRQ_PINT4: |
| 1234 | bank = 4; |
| 1235 | break; |
| 1236 | case IRQ_PINT5: |
| 1237 | bank = 5; |
| 1238 | break; |
| 1239 | #endif |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1240 | default: |
| 1241 | return; |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1242 | } |
| 1243 | |
| 1244 | pint_val = bank * NR_PINT_BITS; |
| 1245 | |
| 1246 | request = pint[bank]->request; |
| 1247 | |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1248 | level_mask = pint[bank]->edge_set & request; |
| 1249 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1250 | while (request) { |
| 1251 | if (request & 1) { |
Michael Hennerich | e3f2300 | 2007-07-12 16:39:29 +0800 | [diff] [blame] | 1252 | irq = pint2irq_lut[pint_val] + SYS_IRQS; |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1253 | if (level_mask & PINT_BIT(pint_val)) { |
| 1254 | umask = 1; |
| 1255 | chip->irq_unmask(&desc->irq_data); |
| 1256 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1257 | bfin_handle_irq(irq); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1258 | } |
| 1259 | pint_val++; |
| 1260 | request >>= 1; |
| 1261 | } |
| 1262 | |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1263 | if (!umask) |
| 1264 | chip->irq_unmask(&desc->irq_data); |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1265 | } |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1266 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1267 | |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1268 | static struct irq_chip bfin_gpio_irqchip = { |
| 1269 | .name = "GPIO", |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1270 | .irq_ack = bfin_gpio_ack_irq, |
| 1271 | .irq_mask = bfin_gpio_mask_irq, |
| 1272 | .irq_mask_ack = bfin_gpio_mask_ack_irq, |
| 1273 | .irq_unmask = bfin_gpio_unmask_irq, |
| 1274 | .irq_disable = bfin_gpio_mask_irq, |
| 1275 | .irq_enable = bfin_gpio_unmask_irq, |
| 1276 | .irq_set_type = bfin_gpio_irq_type, |
| 1277 | .irq_startup = bfin_gpio_irq_startup, |
| 1278 | .irq_shutdown = bfin_gpio_irq_shutdown, |
Thomas Gleixner | e950285 | 2011-02-06 18:23:36 +0000 | [diff] [blame] | 1279 | .irq_set_wake = bfin_gpio_set_wake, |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1280 | }; |
| 1281 | |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1282 | void __cpuinit init_exception_vectors(void) |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 1283 | { |
Mike Frysinger | f0b5d12 | 2007-08-05 17:03:59 +0800 | [diff] [blame] | 1284 | /* cannot program in software: |
| 1285 | * evt0 - emulation (jtag) |
| 1286 | * evt1 - reset |
| 1287 | */ |
| 1288 | bfin_write_EVT2(evt_nmi); |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 1289 | bfin_write_EVT3(trap); |
| 1290 | bfin_write_EVT5(evt_ivhw); |
| 1291 | bfin_write_EVT6(evt_timer); |
| 1292 | bfin_write_EVT7(evt_evt7); |
| 1293 | bfin_write_EVT8(evt_evt8); |
| 1294 | bfin_write_EVT9(evt_evt9); |
| 1295 | bfin_write_EVT10(evt_evt10); |
| 1296 | bfin_write_EVT11(evt_evt11); |
| 1297 | bfin_write_EVT12(evt_evt12); |
| 1298 | bfin_write_EVT13(evt_evt13); |
Philippe Gerum | 9703a73 | 2009-06-22 18:23:48 +0200 | [diff] [blame] | 1299 | bfin_write_EVT14(evt_evt14); |
Bernd Schmidt | 8be80ed | 2007-07-25 14:44:49 +0800 | [diff] [blame] | 1300 | bfin_write_EVT15(evt_system_call); |
| 1301 | CSYNC(); |
| 1302 | } |
| 1303 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1304 | #ifndef SEC_GCTL |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1305 | /* |
| 1306 | * This function should be called during kernel startup to initialize |
| 1307 | * the BFin IRQ handling routines. |
| 1308 | */ |
Michael Hennerich | 8d02237 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1309 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1310 | int __init init_arch_irq(void) |
| 1311 | { |
| 1312 | int irq; |
| 1313 | unsigned long ilat = 0; |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1314 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1315 | /* Disable all the peripheral intrs - page 4-29 HW Ref manual */ |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1316 | #ifdef SIC_IMASK0 |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1317 | bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); |
| 1318 | bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1319 | # ifdef SIC_IMASK2 |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1320 | bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1321 | # endif |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1322 | # if defined(CONFIG_SMP) || defined(CONFIG_ICC) |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1323 | bfin_write_SICB_IMASK0(SIC_UNMASK_ALL); |
| 1324 | bfin_write_SICB_IMASK1(SIC_UNMASK_ALL); |
| 1325 | # endif |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1326 | #else |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1327 | bfin_write_SIC_IMASK(SIC_UNMASK_ALL); |
Roy Huang | 24a07a1 | 2007-07-12 22:41:45 +0800 | [diff] [blame] | 1328 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1329 | |
| 1330 | local_irq_disable(); |
| 1331 | |
Mike Frysinger | 01f8e34 | 2011-06-26 13:56:23 -0400 | [diff] [blame] | 1332 | #if BFIN_GPIO_PINT |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1333 | # ifdef CONFIG_PINTx_REASSIGN |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1334 | pint[0]->assign = CONFIG_PINT0_ASSIGN; |
| 1335 | pint[1]->assign = CONFIG_PINT1_ASSIGN; |
| 1336 | pint[2]->assign = CONFIG_PINT2_ASSIGN; |
| 1337 | pint[3]->assign = CONFIG_PINT3_ASSIGN; |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1338 | # endif |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1339 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| 1340 | init_pint_lut(); |
| 1341 | #endif |
| 1342 | |
| 1343 | for (irq = 0; irq <= SYS_IRQS; irq++) { |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1344 | if (irq <= IRQ_CORETMR) |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1345 | irq_set_chip(irq, &bfin_core_irqchip); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1346 | else |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1347 | irq_set_chip(irq, &bfin_internal_irqchip); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1348 | |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1349 | switch (irq) { |
Mike Frysinger | 01f8e34 | 2011-06-26 13:56:23 -0400 | [diff] [blame] | 1350 | #if BFIN_GPIO_PINT |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1351 | case IRQ_PINT0: |
| 1352 | case IRQ_PINT1: |
| 1353 | case IRQ_PINT2: |
| 1354 | case IRQ_PINT3: |
Mike Frysinger | 01f8e34 | 2011-06-26 13:56:23 -0400 | [diff] [blame] | 1355 | #elif defined(BF537_FAMILY) |
| 1356 | case IRQ_PH_INTA_MAC_RX: |
| 1357 | case IRQ_PF_INTA_PG_INTA: |
| 1358 | #elif defined(BF533_FAMILY) |
| 1359 | case IRQ_PROG_INTA: |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 1360 | #elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1361 | case IRQ_PORTF_INTA: |
| 1362 | case IRQ_PORTG_INTA: |
| 1363 | case IRQ_PORTH_INTA: |
Michael Hennerich | 2c4f829 | 2008-02-09 04:11:14 +0800 | [diff] [blame] | 1364 | #elif defined(CONFIG_BF561) |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1365 | case IRQ_PROG0_INTA: |
| 1366 | case IRQ_PROG1_INTA: |
| 1367 | case IRQ_PROG2_INTA: |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1368 | #elif defined(BF538_FAMILY) |
Michael Hennerich | dc26aec | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1369 | case IRQ_PORTF_INTA: |
Michael Hennerich | 5900314 | 2007-10-21 16:54:27 +0800 | [diff] [blame] | 1370 | #endif |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1371 | irq_set_chained_handler(irq, bfin_demux_gpio_irq); |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1372 | break; |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1373 | #if defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE) |
| 1374 | case IRQ_MAC_ERROR: |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1375 | irq_set_chained_handler(irq, |
| 1376 | bfin_demux_mac_status_irq); |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1377 | break; |
| 1378 | #endif |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1379 | #if defined(CONFIG_SMP) || defined(CONFIG_ICC) |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1380 | case IRQ_SUPPLE_0: |
| 1381 | case IRQ_SUPPLE_1: |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1382 | irq_set_handler(irq, handle_percpu_irq); |
Graf Yang | 6b3087c | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1383 | break; |
| 1384 | #endif |
Graf Yang | 17941314 | 2009-08-18 04:29:33 +0000 | [diff] [blame] | 1385 | |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1386 | #ifdef CONFIG_TICKSOURCE_CORETMR |
| 1387 | case IRQ_CORETMR: |
| 1388 | # ifdef CONFIG_SMP |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1389 | irq_set_handler(irq, handle_percpu_irq); |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1390 | # else |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1391 | irq_set_handler(irq, handle_simple_irq); |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1392 | # endif |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1393 | break; |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1394 | #endif |
| 1395 | |
| 1396 | #ifdef CONFIG_TICKSOURCE_GPTMR0 |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1397 | case IRQ_TIMER0: |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1398 | irq_set_handler(irq, handle_simple_irq); |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1399 | break; |
Graf Yang | 17941314 | 2009-08-18 04:29:33 +0000 | [diff] [blame] | 1400 | #endif |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1401 | |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1402 | default: |
Yi Li | cb19171 | 2009-12-30 07:12:50 +0000 | [diff] [blame] | 1403 | #ifdef CONFIG_IPIPE |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1404 | irq_set_handler(irq, handle_level_irq); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1405 | #else |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1406 | irq_set_handler(irq, handle_simple_irq); |
Mike Frysinger | fc6bd7b | 2011-04-15 01:35:53 -0400 | [diff] [blame] | 1407 | #endif |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1408 | break; |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1409 | } |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1410 | } |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1411 | |
Mike Frysinger | f58c327 | 2011-04-15 03:08:20 -0400 | [diff] [blame] | 1412 | init_mach_irq(); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1413 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1414 | #if (defined(CONFIG_BFIN_MAC) || defined(CONFIG_BFIN_MAC_MODULE)) |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1415 | for (irq = IRQ_MAC_PHYINT; irq <= IRQ_MAC_STMDONE; irq++) |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1416 | irq_set_chip_and_handler(irq, &bfin_mac_status_irqchip, |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1417 | handle_level_irq); |
| 1418 | #endif |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1419 | /* if configured as edge, then will be changed to do_edge_IRQ */ |
Michael Hennerich | aec59c9 | 2010-02-19 15:09:10 +0000 | [diff] [blame] | 1420 | for (irq = GPIO_IRQ_BASE; |
| 1421 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) |
Thomas Gleixner | 43f2f11 | 2011-03-24 17:22:30 +0100 | [diff] [blame] | 1422 | irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, |
Michael Hennerich | 464abc5 | 2008-02-25 13:50:20 +0800 | [diff] [blame] | 1423 | handle_level_irq); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1424 | bfin_write_IMASK(0); |
| 1425 | CSYNC(); |
| 1426 | ilat = bfin_read_ILAT(); |
| 1427 | CSYNC(); |
| 1428 | bfin_write_ILAT(ilat); |
| 1429 | CSYNC(); |
| 1430 | |
Michael Hennerich | 34e0fc8 | 2007-07-12 16:17:18 +0800 | [diff] [blame] | 1431 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1432 | /* IMASK=xxx is equivalent to STI xx or bfin_irq_flags=xx, |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1433 | * local_irq_enable() |
| 1434 | */ |
| 1435 | program_IAR(); |
| 1436 | /* Therefore it's better to setup IARs before interrupts enabled */ |
| 1437 | search_IAR(); |
| 1438 | |
| 1439 | /* Enable interrupts IVG7-15 */ |
Mike Frysinger | 4005978 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1440 | bfin_irq_flags |= IMASK_IVG15 | |
Steven Miao | 4f6b600 | 2012-05-16 17:56:51 +0800 | [diff] [blame] | 1441 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
| 1442 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
| 1443 | |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1444 | |
Michael Hennerich | 349ebbc | 2009-04-15 08:48:08 +0000 | [diff] [blame] | 1445 | /* This implicitly covers ANOMALY_05000171 |
| 1446 | * Boot-ROM code modifies SICA_IWRx wakeup registers |
| 1447 | */ |
Mike Frysinger | be1d854 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 1448 | #ifdef SIC_IWR0 |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1449 | bfin_write_SIC_IWR0(IWR_DISABLE_ALL); |
Mike Frysinger | be1d854 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 1450 | # ifdef SIC_IWR1 |
Bryan Wu | 2f6f4bc | 2008-11-18 17:48:21 +0800 | [diff] [blame] | 1451 | /* BF52x/BF51x system reset does not properly reset SIC_IWR1 which |
Michael Hennerich | 55546ac | 2008-08-13 17:41:13 +0800 | [diff] [blame] | 1452 | * will screw up the bootrom as it relies on MDMA0/1 waking it |
| 1453 | * up from IDLE instructions. See this report for more info: |
| 1454 | * http://blackfin.uclinux.org/gf/tracker/4323 |
| 1455 | */ |
Mike Frysinger | b7e1129 | 2008-11-18 17:48:22 +0800 | [diff] [blame] | 1456 | if (ANOMALY_05000435) |
| 1457 | bfin_write_SIC_IWR1(IWR_ENABLE(10) | IWR_ENABLE(11)); |
| 1458 | else |
| 1459 | bfin_write_SIC_IWR1(IWR_DISABLE_ALL); |
Mike Frysinger | be1d854 | 2009-02-04 16:49:45 +0800 | [diff] [blame] | 1460 | # endif |
| 1461 | # ifdef SIC_IWR2 |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1462 | bfin_write_SIC_IWR2(IWR_DISABLE_ALL); |
Michael Hennerich | fe9ec9b | 2008-02-25 12:04:57 +0800 | [diff] [blame] | 1463 | # endif |
| 1464 | #else |
Michael Hennerich | 56f5f59 | 2008-08-06 17:55:32 +0800 | [diff] [blame] | 1465 | bfin_write_SIC_IWR(IWR_DISABLE_ALL); |
Michael Hennerich | fe9ec9b | 2008-02-25 12:04:57 +0800 | [diff] [blame] | 1466 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1467 | return 0; |
| 1468 | } |
| 1469 | |
| 1470 | #ifdef CONFIG_DO_IRQ_L1 |
Mike Frysinger | a055b2b | 2007-11-15 21:12:32 +0800 | [diff] [blame] | 1471 | __attribute__((l1_text)) |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1472 | #endif |
Mike Frysinger | 6b10804 | 2011-03-30 01:35:41 -0400 | [diff] [blame] | 1473 | static int vec_to_irq(int vec) |
| 1474 | { |
| 1475 | struct ivgx *ivg = ivg7_13[vec - IVG7].ifirst; |
| 1476 | struct ivgx *ivg_stop = ivg7_13[vec - IVG7].istop; |
| 1477 | unsigned long sic_status[3]; |
Mike Frysinger | 6b10804 | 2011-03-30 01:35:41 -0400 | [diff] [blame] | 1478 | if (likely(vec == EVT_IVTMR_P)) |
| 1479 | return IRQ_CORETMR; |
Mike Frysinger | 6b10804 | 2011-03-30 01:35:41 -0400 | [diff] [blame] | 1480 | #ifdef SIC_ISR |
| 1481 | sic_status[0] = bfin_read_SIC_IMASK() & bfin_read_SIC_ISR(); |
| 1482 | #else |
| 1483 | if (smp_processor_id()) { |
| 1484 | # ifdef SICB_ISR0 |
| 1485 | /* This will be optimized out in UP mode. */ |
| 1486 | sic_status[0] = bfin_read_SICB_ISR0() & bfin_read_SICB_IMASK0(); |
| 1487 | sic_status[1] = bfin_read_SICB_ISR1() & bfin_read_SICB_IMASK1(); |
| 1488 | # endif |
| 1489 | } else { |
| 1490 | sic_status[0] = bfin_read_SIC_ISR0() & bfin_read_SIC_IMASK0(); |
| 1491 | sic_status[1] = bfin_read_SIC_ISR1() & bfin_read_SIC_IMASK1(); |
| 1492 | } |
| 1493 | #endif |
| 1494 | #ifdef SIC_ISR2 |
| 1495 | sic_status[2] = bfin_read_SIC_ISR2() & bfin_read_SIC_IMASK2(); |
| 1496 | #endif |
| 1497 | |
| 1498 | for (;; ivg++) { |
| 1499 | if (ivg >= ivg_stop) |
| 1500 | return -1; |
| 1501 | #ifdef SIC_ISR |
| 1502 | if (sic_status[0] & ivg->isrflag) |
| 1503 | #else |
| 1504 | if (sic_status[(ivg->irqno - IVG7) / 32] & ivg->isrflag) |
| 1505 | #endif |
| 1506 | return ivg->irqno; |
| 1507 | } |
| 1508 | } |
| 1509 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1510 | #else /* SEC_GCTL */ |
| 1511 | |
| 1512 | /* |
| 1513 | * This function should be called during kernel startup to initialize |
| 1514 | * the BFin IRQ handling routines. |
| 1515 | */ |
| 1516 | |
| 1517 | int __init init_arch_irq(void) |
| 1518 | { |
| 1519 | int irq; |
| 1520 | unsigned long ilat = 0; |
| 1521 | |
| 1522 | bfin_write_SEC_GCTL(SEC_GCTL_RESET); |
| 1523 | |
| 1524 | local_irq_disable(); |
| 1525 | |
| 1526 | #if BFIN_GPIO_PINT |
| 1527 | # ifdef CONFIG_PINTx_REASSIGN |
| 1528 | pint[0]->assign = CONFIG_PINT0_ASSIGN; |
| 1529 | pint[1]->assign = CONFIG_PINT1_ASSIGN; |
| 1530 | pint[2]->assign = CONFIG_PINT2_ASSIGN; |
| 1531 | pint[3]->assign = CONFIG_PINT3_ASSIGN; |
| 1532 | pint[4]->assign = CONFIG_PINT4_ASSIGN; |
| 1533 | pint[5]->assign = CONFIG_PINT5_ASSIGN; |
| 1534 | # endif |
| 1535 | /* Whenever PINTx_ASSIGN is altered init_pint_lut() must be executed! */ |
| 1536 | init_pint_lut(); |
| 1537 | #endif |
| 1538 | |
| 1539 | for (irq = 0; irq <= SYS_IRQS; irq++) { |
| 1540 | if (irq <= IRQ_CORETMR) { |
| 1541 | irq_set_chip(irq, &bfin_core_irqchip); |
| 1542 | #ifdef CONFIG_TICKSOURCE_CORETMR |
| 1543 | if (irq == IRQ_CORETMR) |
| 1544 | # ifdef CONFIG_SMP |
| 1545 | irq_set_handler(irq, handle_percpu_irq); |
| 1546 | # else |
| 1547 | irq_set_handler(irq, handle_simple_irq); |
| 1548 | # endif |
| 1549 | #endif |
| 1550 | } else if (irq < BFIN_IRQ(0)) { |
| 1551 | irq_set_chip_and_handler(irq, &bfin_internal_irqchip, |
| 1552 | handle_simple_irq); |
Sonic Zhang | 06051fd | 2012-07-04 19:22:55 +0800 | [diff] [blame] | 1553 | } else if (irq == IRQ_SEC_ERR) { |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1554 | irq_set_chip_and_handler(irq, &bfin_sec_irqchip, |
| 1555 | handle_sec_fault); |
Sonic Zhang | 06051fd | 2012-07-04 19:22:55 +0800 | [diff] [blame] | 1556 | } else if (irq < CORE_IRQS && irq >= IRQ_C0_DBL_FAULT) { |
| 1557 | irq_set_chip_and_handler(irq, &bfin_sec_irqchip, |
| 1558 | handle_core_fault); |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1559 | } else if (irq >= BFIN_IRQ(21) && irq <= BFIN_IRQ(26)) { |
| 1560 | irq_set_chip(irq, &bfin_sec_irqchip); |
| 1561 | irq_set_chained_handler(irq, bfin_demux_gpio_irq); |
| 1562 | } else if (irq >= BFIN_IRQ(34) && irq <= BFIN_IRQ(37)) { |
| 1563 | irq_set_chip(irq, &bfin_sec_irqchip); |
| 1564 | irq_set_handler(irq, handle_percpu_irq); |
| 1565 | } else { |
| 1566 | irq_set_chip_and_handler(irq, &bfin_sec_irqchip, |
| 1567 | handle_fasteoi_irq); |
| 1568 | __irq_set_preflow_handler(irq, bfin_sec_preflow_handler); |
| 1569 | } |
| 1570 | } |
| 1571 | for (irq = GPIO_IRQ_BASE; |
| 1572 | irq < (GPIO_IRQ_BASE + MAX_BLACKFIN_GPIOS); irq++) |
| 1573 | irq_set_chip_and_handler(irq, &bfin_gpio_irqchip, |
| 1574 | handle_level_irq); |
| 1575 | |
| 1576 | bfin_write_IMASK(0); |
| 1577 | CSYNC(); |
| 1578 | ilat = bfin_read_ILAT(); |
| 1579 | CSYNC(); |
| 1580 | bfin_write_ILAT(ilat); |
| 1581 | CSYNC(); |
| 1582 | |
| 1583 | printk(KERN_INFO "Configuring Blackfin Priority Driven Interrupts\n"); |
| 1584 | |
Sonic Zhang | e0a5931 | 2012-06-29 18:19:29 +0800 | [diff] [blame] | 1585 | bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority); |
| 1586 | |
| 1587 | bfin_sec_set_priority(CONFIG_SEC_IRQ_PRIORITY_LEVELS, sec_int_priority); |
| 1588 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1589 | /* Enable interrupts IVG7-15 */ |
| 1590 | bfin_irq_flags |= IMASK_IVG15 | |
| 1591 | IMASK_IVG14 | IMASK_IVG13 | IMASK_IVG12 | IMASK_IVG11 | |
| 1592 | IMASK_IVG10 | IMASK_IVG9 | IMASK_IVG8 | IMASK_IVG7 | IMASK_IVGHW; |
| 1593 | |
| 1594 | |
| 1595 | bfin_write_SEC_FCTL(SEC_FCTL_EN | SEC_FCTL_SYSRST_EN | SEC_FCTL_FLTIN_EN); |
| 1596 | bfin_sec_enable_sci(SIC_SYSIRQ(IRQ_WATCH0)); |
| 1597 | bfin_sec_enable_ssi(SIC_SYSIRQ(IRQ_WATCH0)); |
| 1598 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_RESET); |
| 1599 | udelay(100); |
| 1600 | bfin_write_SEC_GCTL(SEC_GCTL_EN); |
| 1601 | bfin_write_SEC_SCI(0, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); |
| 1602 | bfin_write_SEC_SCI(1, SEC_CCTL, SEC_CCTL_EN | SEC_CCTL_NMI_EN); |
| 1603 | |
| 1604 | init_software_driven_irq(); |
| 1605 | register_syscore_ops(&sec_pm_syscore_ops); |
| 1606 | |
| 1607 | return 0; |
| 1608 | } |
| 1609 | |
| 1610 | #ifdef CONFIG_DO_IRQ_L1 |
| 1611 | __attribute__((l1_text)) |
| 1612 | #endif |
| 1613 | static int vec_to_irq(int vec) |
| 1614 | { |
| 1615 | if (likely(vec == EVT_IVTMR_P)) |
| 1616 | return IRQ_CORETMR; |
| 1617 | |
| 1618 | return BFIN_IRQ(bfin_read_SEC_SCI(0, SEC_CSID)); |
| 1619 | } |
| 1620 | #endif /* SEC_GCTL */ |
| 1621 | |
Mike Frysinger | 6b10804 | 2011-03-30 01:35:41 -0400 | [diff] [blame] | 1622 | #ifdef CONFIG_DO_IRQ_L1 |
| 1623 | __attribute__((l1_text)) |
| 1624 | #endif |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1625 | void do_irq(int vec, struct pt_regs *fp) |
| 1626 | { |
Mike Frysinger | 6b10804 | 2011-03-30 01:35:41 -0400 | [diff] [blame] | 1627 | int irq = vec_to_irq(vec); |
| 1628 | if (irq == -1) |
| 1629 | return; |
| 1630 | asm_do_IRQ(irq, fp); |
Bryan Wu | 1394f03 | 2007-05-06 14:50:22 -0700 | [diff] [blame] | 1631 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1632 | |
| 1633 | #ifdef CONFIG_IPIPE |
| 1634 | |
| 1635 | int __ipipe_get_irq_priority(unsigned irq) |
| 1636 | { |
| 1637 | int ient, prio; |
| 1638 | |
| 1639 | if (irq <= IRQ_CORETMR) |
| 1640 | return irq; |
| 1641 | |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1642 | #ifdef SEC_GCTL |
| 1643 | if (irq >= BFIN_IRQ(0)) |
| 1644 | return IVG11; |
| 1645 | #else |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1646 | for (ient = 0; ient < NR_PERI_INTS; ient++) { |
| 1647 | struct ivgx *ivg = ivg_table + ient; |
| 1648 | if (ivg->irqno == irq) { |
| 1649 | for (prio = 0; prio <= IVG13-IVG7; prio++) { |
| 1650 | if (ivg7_13[prio].ifirst <= ivg && |
| 1651 | ivg7_13[prio].istop > ivg) |
| 1652 | return IVG7 + prio; |
| 1653 | } |
| 1654 | } |
| 1655 | } |
Sonic Zhang | 11b27cb | 2012-06-28 19:16:48 +0800 | [diff] [blame] | 1656 | #endif |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1657 | |
| 1658 | return IVG15; |
| 1659 | } |
| 1660 | |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1661 | /* Hw interrupts are disabled on entry (check SAVE_CONTEXT). */ |
| 1662 | #ifdef CONFIG_DO_IRQ_L1 |
| 1663 | __attribute__((l1_text)) |
| 1664 | #endif |
| 1665 | asmlinkage int __ipipe_grab_irq(int vec, struct pt_regs *regs) |
| 1666 | { |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1667 | struct ipipe_percpu_domain_data *p = ipipe_root_cpudom_ptr(); |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1668 | struct ipipe_domain *this_domain = __ipipe_current_domain; |
Philippe Gerum | 5b5da4c | 2011-03-17 02:12:48 -0400 | [diff] [blame] | 1669 | int irq, s = 0; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1670 | |
Mike Frysinger | 6b10804 | 2011-03-30 01:35:41 -0400 | [diff] [blame] | 1671 | irq = vec_to_irq(vec); |
| 1672 | if (irq == -1) |
| 1673 | return 0; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1674 | |
| 1675 | if (irq == IRQ_SYSTMR) { |
Philippe Gerum | a40494a | 2009-06-16 05:25:42 +0200 | [diff] [blame] | 1676 | #if !defined(CONFIG_GENERIC_CLOCKEVENTS) || defined(CONFIG_TICKSOURCE_GPTMR0) |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1677 | bfin_write_TIMER_STATUS(1); /* Latch TIMIL0 */ |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1678 | #endif |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1679 | /* This is basically what we need from the register frame. */ |
| 1680 | __raw_get_cpu_var(__ipipe_tick_regs).ipend = regs->ipend; |
| 1681 | __raw_get_cpu_var(__ipipe_tick_regs).pc = regs->pc; |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1682 | if (this_domain != ipipe_root_domain) |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1683 | __raw_get_cpu_var(__ipipe_tick_regs).ipend &= ~0x10; |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1684 | else |
| 1685 | __raw_get_cpu_var(__ipipe_tick_regs).ipend |= 0x10; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1686 | } |
| 1687 | |
Philippe Gerum | 5b5da4c | 2011-03-17 02:12:48 -0400 | [diff] [blame] | 1688 | /* |
| 1689 | * We don't want Linux interrupt handlers to run at the |
| 1690 | * current core priority level (i.e. < EVT15), since this |
| 1691 | * might delay other interrupts handled by a high priority |
| 1692 | * domain. Here is what we do instead: |
| 1693 | * |
| 1694 | * - we raise the SYNCDEFER bit to prevent |
| 1695 | * __ipipe_handle_irq() to sync the pipeline for the root |
| 1696 | * stage for the incoming interrupt. Upon return, that IRQ is |
| 1697 | * pending in the interrupt log. |
| 1698 | * |
| 1699 | * - we raise the TIF_IRQ_SYNC bit for the current thread, so |
| 1700 | * that _schedule_and_signal_from_int will eventually sync the |
| 1701 | * pipeline from EVT15. |
| 1702 | */ |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1703 | if (this_domain == ipipe_root_domain) { |
| 1704 | s = __test_and_set_bit(IPIPE_SYNCDEFER_FLAG, &p->status); |
| 1705 | barrier(); |
| 1706 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1707 | |
| 1708 | ipipe_trace_irq_entry(irq); |
| 1709 | __ipipe_handle_irq(irq, regs); |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1710 | ipipe_trace_irq_exit(irq); |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1711 | |
Philippe Gerum | 5b5da4c | 2011-03-17 02:12:48 -0400 | [diff] [blame] | 1712 | if (user_mode(regs) && |
| 1713 | !ipipe_test_foreign_stack() && |
| 1714 | (current->ipipe_flags & PF_EVTRET) != 0) { |
| 1715 | /* |
| 1716 | * Testing for user_regs() does NOT fully eliminate |
| 1717 | * foreign stack contexts, because of the forged |
| 1718 | * interrupt returns we do through |
| 1719 | * __ipipe_call_irqtail. In that case, we might have |
| 1720 | * preempted a foreign stack context in a high |
| 1721 | * priority domain, with a single interrupt level now |
| 1722 | * pending after the irqtail unwinding is done. In |
| 1723 | * which case user_mode() is now true, and the event |
| 1724 | * gets dispatched spuriously. |
| 1725 | */ |
| 1726 | current->ipipe_flags &= ~PF_EVTRET; |
| 1727 | __ipipe_dispatch_event(IPIPE_EVENT_RETURN, regs); |
| 1728 | } |
| 1729 | |
Philippe Gerum | 9bd50df | 2009-03-04 16:52:38 +0800 | [diff] [blame] | 1730 | if (this_domain == ipipe_root_domain) { |
| 1731 | set_thread_flag(TIF_IRQ_SYNC); |
| 1732 | if (!s) { |
| 1733 | __clear_bit(IPIPE_SYNCDEFER_FLAG, &p->status); |
| 1734 | return !test_bit(IPIPE_STALL_FLAG, &p->status); |
| 1735 | } |
| 1736 | } |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1737 | |
Graf Yang | 1fa9be7 | 2009-05-15 11:01:59 +0000 | [diff] [blame] | 1738 | return 0; |
Yi Li | 6a01f23 | 2009-01-07 23:14:39 +0800 | [diff] [blame] | 1739 | } |
| 1740 | |
| 1741 | #endif /* CONFIG_IPIPE */ |