blob: 5804fcc124c5ba6e883796eedb9667b68db117ed [file] [log] [blame]
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001/*
2 * Copyright © 2009 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21 * DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Zhenyu Wang <zhenyu.z.wang@intel.com>
25 * Wu Fengguang <fengguang.wu@intel.com>
26 *
27 */
28
Wu Fengguang020abdb2010-04-19 13:13:06 +080029#define _GNU_SOURCE
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080030#include <unistd.h>
Wu Fengguang020abdb2010-04-19 13:13:06 +080031#include <stdlib.h>
32#include <stdio.h>
33#include <string.h>
34#include <err.h>
Wu Fengguang9e9c9f22009-11-06 11:06:22 +080035#include <arpa/inet.h>
36#include "intel_gpu_tools.h"
37
Wu Fengguang020abdb2010-04-19 13:13:06 +080038static uint32_t devid;
39
40
41#define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1)
42#define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low))
43#define BITS(reg, high, low) (((reg) & (BITMASK(high, low))) >> (low))
44#define BIT(reg, n) BITS(reg, n, n)
45
46#define min_t(type, x, y) ({ \
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -040047 type __min1 = (x); \
48 type __min2 = (y); \
49 __min1 < __min2 ? __min1 : __min2; })
Wu Fengguang020abdb2010-04-19 13:13:06 +080050
51#define OPNAME(names, index) \
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -040052 names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)]
Wu Fengguang020abdb2010-04-19 13:13:06 +080053
54#define dump_reg(reg, desc) \
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -040055 do { \
56 dword = INREG(reg); \
57 printf("%-21s 0x%08x %s\n", # reg, dword, desc); \
58 } while (0)
Wu Fengguang020abdb2010-04-19 13:13:06 +080059
60
Daniel Vetter03ab1322012-01-09 23:09:37 +010061static const char *pixel_clock[] = {
Wu Fengguang020abdb2010-04-19 13:13:06 +080062 [0] = "25.2 / 1.001 MHz",
63 [1] = "25.2 MHz",
64 [2] = "27 MHz",
65 [3] = "27 * 1.001 MHz",
66 [4] = "54 MHz",
67 [5] = "54 * 1.001 MHz",
68 [6] = "74.25 / 1.001 MHz",
69 [7] = "74.25 MHz",
70 [8] = "148.5 / 1.001 MHz",
71 [9] = "148.5 MHz",
72 [10] = "Reserved",
73};
74
Daniel Vetter03ab1322012-01-09 23:09:37 +010075static const char *power_state[] = {
Wu Fengguang020abdb2010-04-19 13:13:06 +080076 [0] = "D0",
77 [1] = "D1",
78 [2] = "D2",
79 [3] = "D3",
80};
81
Daniel Vetter03ab1322012-01-09 23:09:37 +010082static const char *stream_type[] = {
Wu Fengguang020abdb2010-04-19 13:13:06 +080083 [0] = "default samples",
84 [1] = "one bit stream",
85 [2] = "DST stream",
86 [3] = "MLP stream",
87 [4] = "Reserved",
88};
89
Daniel Vetter03ab1322012-01-09 23:09:37 +010090static const char *dip_port[] = {
Wu Fengguang020abdb2010-04-19 13:13:06 +080091 [0] = "Reserved",
92 [1] = "Digital Port B",
93 [2] = "Digital Port C",
94 [3] = "Digital Port D",
95};
96
Wang Xingchaoc4077222012-08-15 16:13:38 +080097static const char *dip_type[] = {
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -040098 [0] = "Audio DIP Disabled",
99 [1] = "Audio DIP Enabled",
Wang Xingchaoc4077222012-08-15 16:13:38 +0800100};
101
Daniel Vetter03ab1322012-01-09 23:09:37 +0100102static const char *dip_index[] = {
Wu Fengguang020abdb2010-04-19 13:13:06 +0800103 [0] = "Audio DIP",
104 [1] = "ACP DIP",
105 [2] = "ISRC1 DIP",
106 [3] = "ISRC2 DIP",
107 [4] = "Reserved",
108};
109
Daniel Vetter03ab1322012-01-09 23:09:37 +0100110static const char *dip_trans[] = {
Wu Fengguang020abdb2010-04-19 13:13:06 +0800111 [0] = "disabled",
112 [1] = "reserved",
113 [2] = "send once",
114 [3] = "best effort",
115};
116
Daniel Vetter03ab1322012-01-09 23:09:37 +0100117static const char *video_dip_index[] = {
Wu Fengguang020abdb2010-04-19 13:13:06 +0800118 [0] = "AVI DIP",
119 [1] = "Vendor-specific DIP",
Wu Fengguangf3f84bb2011-11-12 11:12:55 +0800120 [2] = "Gamut Metadata DIP",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800121 [3] = "Source Product Description DIP",
122};
123
Daniel Vetter03ab1322012-01-09 23:09:37 +0100124static const char *video_dip_trans[] = {
Wu Fengguang020abdb2010-04-19 13:13:06 +0800125 [0] = "send once",
126 [1] = "send every vsync",
127 [2] = "send at least every other vsync",
128 [3] = "reserved",
129};
130
Daniel Vetter03ab1322012-01-09 23:09:37 +0100131static const char *trans_to_port_sel[] = {
Wu Fengguang020abdb2010-04-19 13:13:06 +0800132 [0] = "no port",
133 [1] = "Digital Port B",
Wang Xingchaof9a24812012-08-15 16:13:37 +0800134 [2] = "Digital Port C",
135 [3] = "Digital Port D",
136 [4] = "reserved",
Alan Coopersmithc4610062012-01-06 14:37:19 -0800137 [5] = "reserved",
138 [6] = "reserved",
139 [7] = "reserved",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800140};
141
Wang Xingchaoc4077222012-08-15 16:13:38 +0800142static const char *ddi_mode[] = {
143 [0] = "HDMI mode",
144 [1] = "DVI mode",
145 [2] = "DP SST mode",
146 [3] = "DP MST mode",
147 [4] = "DP FDI mode",
148 [5] = "reserved",
149 [6] = "reserved",
150 [7] = "reserved",
151};
152
Daniel Vetter03ab1322012-01-09 23:09:37 +0100153static const char *transcoder_select[] = {
Wu Fengguang020abdb2010-04-19 13:13:06 +0800154 [0] = "Transcoder A",
155 [1] = "Transcoder B",
156 [2] = "Transcoder C",
157 [3] = "reserved",
158};
159
Daniel Vetter03ab1322012-01-09 23:09:37 +0100160static const char *dp_port_width[] = {
Wu Fengguang020abdb2010-04-19 13:13:06 +0800161 [0] = "x1 mode",
162 [1] = "x2 mode",
Wu Fengguangcf4c12f2011-11-12 11:12:46 +0800163 [2] = "reserved",
164 [3] = "x4 mode",
Alan Coopersmithc4610062012-01-06 14:37:19 -0800165 [4] = "reserved",
166 [5] = "reserved",
167 [6] = "reserved",
168 [7] = "reserved",
Wu Fengguang020abdb2010-04-19 13:13:06 +0800169};
170
Daniel Vetter03ab1322012-01-09 23:09:37 +0100171static const char *bits_per_sample[] = {
Wu Fengguang12861a92011-11-12 11:12:47 +0800172 [0] = "reserved",
173 [1] = "16 bits",
174 [2] = "24 bits",
175 [3] = "32 bits",
176 [4] = "20 bits",
177 [5] = "reserved",
178};
179
Daniel Vetter03ab1322012-01-09 23:09:37 +0100180static const char *sdvo_hdmi_encoding[] = {
Wu Fengguangee949582011-11-12 11:12:53 +0800181 [0] = "SDVO",
182 [1] = "reserved",
183 [2] = "TMDS",
184 [3] = "reserved",
185};
Wu Fengguang12861a92011-11-12 11:12:47 +0800186
Wu Fengguange64abe52012-01-17 07:19:24 +0800187static const char *n_index_value[] = {
188 [0] = "HDMI",
189 [1] = "DisplayPort",
190};
191
Wu Fengguang020abdb2010-04-19 13:13:06 +0800192static void do_self_tests(void)
193{
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400194 if (BIT(1, 0) != 1)
195 exit(1);
196 if (BIT(0x80000000, 31) != 1)
197 exit(2);
198 if (BITS(0xc0000000, 31, 30) != 3)
199 exit(3);
Wu Fengguang020abdb2010-04-19 13:13:06 +0800200}
201
202/*
203 * EagleLake registers
204 */
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800205#define AUD_CONFIG 0x62000
206#define AUD_DEBUG 0x62010
207#define AUD_VID_DID 0x62020
208#define AUD_RID 0x62024
209#define AUD_SUBN_CNT 0x62028
210#define AUD_FUNC_GRP 0x62040
211#define AUD_SUBN_CNT2 0x62044
212#define AUD_GRP_CAP 0x62048
213#define AUD_PWRST 0x6204c
214#define AUD_SUPPWR 0x62050
215#define AUD_SID 0x62054
216#define AUD_OUT_CWCAP 0x62070
217#define AUD_OUT_PCMSIZE 0x62074
218#define AUD_OUT_STR 0x62078
219#define AUD_OUT_DIG_CNVT 0x6207c
220#define AUD_OUT_CH_STR 0x62080
221#define AUD_OUT_STR_DESC 0x62084
222#define AUD_PINW_CAP 0x620a0
223#define AUD_PIN_CAP 0x620a4
224#define AUD_PINW_CONNLNG 0x620a8
225#define AUD_PINW_CONNLST 0x620ac
226#define AUD_PINW_CNTR 0x620b0
227#define AUD_PINW_UNSOLRESP 0x620b8
228#define AUD_CNTL_ST 0x620b4
229#define AUD_PINW_CONFIG 0x620bc
230#define AUD_HDMIW_STATUS 0x620d4
231#define AUD_HDMIW_HDMIEDID 0x6210c
232#define AUD_HDMIW_INFOFR 0x62118
233#define AUD_CONV_CHCNT 0x62120
234#define AUD_CTS_ENABLE 0x62128
235
236#define VIDEO_DIP_CTL 0x61170
237#define VIDEO_DIP_ENABLE (1<<31)
238#define VIDEO_DIP_ENABLE_AVI (1<<21)
239#define VIDEO_DIP_ENABLE_VENDOR (1<<22)
240#define VIDEO_DIP_ENABLE_SPD (1<<24)
241#define VIDEO_DIP_BUF_AVI (0<<19)
242#define VIDEO_DIP_BUF_VENDOR (1<<19)
243#define VIDEO_DIP_BUF_SPD (3<<19)
244#define VIDEO_DIP_TRANS_ONCE (0<<16)
245#define VIDEO_DIP_TRANS_1 (1<<16)
246#define VIDEO_DIP_TRANS_2 (2<<16)
247
248#define AUDIO_HOTPLUG_EN (1<<24)
249
250
Wu Fengguang020abdb2010-04-19 13:13:06 +0800251static void dump_eaglelake(void)
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800252{
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400253 uint32_t dword;
254 int i;
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800255
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400256 /* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800257
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400258 dump_reg(VIDEO_DIP_CTL, "Video DIP Control");
259 dump_reg(SDVOB, "Digital Display Port B Control Register");
260 dump_reg(SDVOC, "Digital Display Port C Control Register");
261 dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable");
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800262
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400263 dump_reg(AUD_CONFIG, "Audio Configuration");
264 dump_reg(AUD_DEBUG, "Audio Debug");
265 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
266 dump_reg(AUD_RID, "Audio Revision ID");
267 dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count");
268 dump_reg(AUD_FUNC_GRP, "Audio Function Group Type");
269 dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count");
270 dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities");
271 dump_reg(AUD_PWRST, "Audio Power State");
272 dump_reg(AUD_SUPPWR, "Audio Supported Power States");
273 dump_reg(AUD_SID, "Audio Root Node Subsystem ID");
274 dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities");
275 dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates");
276 dump_reg(AUD_OUT_STR, "Audio Stream Formats");
277 dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter");
278 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
279 dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format");
280 dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities");
281 dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities");
282 dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length");
283 dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry");
284 dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control");
285 dump_reg(AUD_PINW_UNSOLRESP, "Audio Unsolicited Response Enable");
286 dump_reg(AUD_CNTL_ST, "Audio Control State Register");
287 dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default");
288 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
289 dump_reg(AUD_HDMIW_HDMIEDID, "Audio HDMI Data EDID Block");
290 dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet");
291 dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count");
292 dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable");
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800293
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400294 printf("\nDetails:\n\n");
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800295
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400296 dword = INREG(AUD_VID_DID);
297 printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16);
298 printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff);
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800299
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400300 dword = INREG(AUD_RID);
301 printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20));
302 printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16));
303 printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8));
304 printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800305
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400306 dword = INREG(SDVOB);
307 printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
308 printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
309 printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
310 printf("SDVOB null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
311 printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800312
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400313 dword = INREG(SDVOC);
314 printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
315 printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI));
316 printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO));
317 printf("SDVOC null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
318 printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800319
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400320 dword = INREG(PORT_HOTPLUG_EN);
321 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)),
322 printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)),
323 printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)),
324 printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)),
325 printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)),
326 printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)),
327 printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)),
328 printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)),
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800329
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400330 dword = INREG(VIDEO_DIP_CTL);
331 printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)),
332 printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n",
333 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
334 printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28));
335 printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21));
336 printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22));
337 printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24));
338 printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n",
339 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
340 printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n",
341 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
342 printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8));
343 printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800344
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400345 dword = INREG(AUD_CONFIG);
346 printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
347 OPNAME(pixel_clock, BITS(dword, 19, 16)));
348 printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2));
349 printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1));
350 printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800351
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400352 dword = INREG(AUD_DEBUG);
353 printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800354
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400355 dword = INREG(AUD_SUBN_CNT);
356 printf("AUD_SUBN_CNT starting node number\t0x%lx\n", BITS(dword, 23, 16));
357 printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800358
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400359 dword = INREG(AUD_SUBN_CNT2);
360 printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n", BITS(dword, 24, 16));
361 printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", BITS(dword, 7, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800362
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400363 dword = INREG(AUD_FUNC_GRP);
364 printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8));
365 printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800366
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400367 dword = INREG(AUD_GRP_CAP);
368 printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16));
369 printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8));
370 printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800371
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400372 dword = INREG(AUD_PWRST);
373 printf("AUD_PWRST device power state\t\t%s\n",
374 power_state[BITS(dword, 5, 4)]);
375 printf("AUD_PWRST device power state setting\t%s\n",
376 power_state[BITS(dword, 1, 0)]);
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800377
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400378 dword = INREG(AUD_SUPPWR);
379 printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0));
380 printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1));
381 printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2));
382 printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800383
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400384 dword = INREG(AUD_OUT_CWCAP);
385 printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
386 printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
387 printf("AUD_OUT_CWCAP channel count\t\t%lu\n",
388 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
389 printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
390 printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10));
391 printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9));
392 printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8));
393 printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7));
394 printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5));
395 printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4));
396 printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3));
397 printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2));
398 printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800399
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400400 dword = INREG(AUD_OUT_DIG_CNVT);
401 printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", BITS(dword, 14, 8));
402 printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7));
403 printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6));
404 printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5));
405 printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4));
406 printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3));
407 printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2));
408 printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1));
409 printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800410
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400411 dword = INREG(AUD_OUT_CH_STR);
412 printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4));
413 printf("AUD_OUT_CH_STR lowest channel\t\t%lu\n", BITS(dword, 3, 0));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800414
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400415 dword = INREG(AUD_OUT_STR_DESC);
416 printf("AUD_OUT_STR_DESC stream channels\t%lu\n", BITS(dword, 3, 0) + 1);
417 printf("AUD_OUT_STR_DESC Bits per Sample\t[%#lx] %s\n",
418 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800419
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400420 dword = INREG(AUD_PINW_CAP);
421 printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20));
422 printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16));
423 printf("AUD_PINW_CAP channel count\t\t%lu\n",
424 BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1);
425 printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12));
426 printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11));
427 printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10));
428 printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9));
429 printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8));
430 printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7));
431 printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5));
432 printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4));
433 printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3));
434 printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2));
435 printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800436
437
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400438 dword = INREG(AUD_PIN_CAP);
439 printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16));
440 printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7));
441 printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4));
442 printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800443
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400444 dword = INREG(AUD_PINW_CNTR);
445 printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8));
446 printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6));
447 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
448 printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8));
449 printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n",
450 BITS(dword, 2, 0),
451 OPNAME(stream_type, BITS(dword, 2, 0)));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800452
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400453 dword = INREG(AUD_PINW_UNSOLRESP);
454 printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800455
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400456 dword = INREG(AUD_CNTL_ST);
457 printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21));
458 printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22));
459 printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23));
460 printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n",
461 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
462 printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n",
463 BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18)));
464 printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n",
465 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
466 printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0));
467 printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15));
468 printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14));
469 printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4));
470 printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9));
471 printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800472
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400473 dword = INREG(AUD_HDMIW_STATUS);
474 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31));
475 printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30));
476 printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29));
477 printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28));
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800478
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400479 dword = INREG(AUD_CONV_CHCNT);
480 printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14));
481 printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", BITS(dword, 11, 8) + 1);
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800482
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400483 printf("AUD_CONV_CHCNT HDMI channel mapping:\n");
484 for (i = 0; i < 8; i++) {
485 OUTREG(AUD_CONV_CHCNT, i);
486 dword = INREG(AUD_CONV_CHCNT);
487 printf("\t\t\t\t\t[0x%x] %u => %lu\n", dword, i, BITS(dword, 7, 4));
488 }
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800489
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400490 printf("AUD_HDMIW_HDMIEDID HDMI ELD:\n\t");
491 dword = INREG(AUD_CNTL_ST);
492 dword &= ~BITMASK(8, 5);
493 OUTREG(AUD_CNTL_ST, dword);
494 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
495 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID)));
496 printf("\n");
Wu Fengguangf32aecb2011-11-12 11:12:50 +0800497
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400498 printf("AUD_HDMIW_INFOFR HDMI audio Infoframe:\n\t");
499 dword = INREG(AUD_CNTL_ST);
500 dword &= ~BITMASK(20, 18);
501 dword &= ~BITMASK(3, 0);
502 OUTREG(AUD_CNTL_ST, dword);
503 for (i = 0; i < 8; i++)
504 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR)));
505 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800506}
Wu Fengguang9e9c9f22009-11-06 11:06:22 +0800507
Wu Fengguang020abdb2010-04-19 13:13:06 +0800508#undef AUD_RID
509#undef AUD_VID_DID
510#undef AUD_PWRST
511#undef AUD_OUT_CH_STR
512#undef AUD_HDMIW_STATUS
513
514/*
515 * IronLake registers
516 */
517#define AUD_CONFIG_A 0xE2000
518#define AUD_CONFIG_B 0xE2100
519#define AUD_CTS_ENABLE_A 0xE2028
520#define AUD_CTS_ENABLE_B 0xE2128
521#define AUD_MISC_CTRL_A 0xE2010
522#define AUD_MISC_CTRL_B 0xE2110
523#define AUD_VID_DID 0xE2020
524#define AUD_RID 0xE2024
525#define AUD_PWRST 0xE204C
526#define AUD_PORT_EN_HD_CFG 0xE207C
527#define AUD_OUT_DIG_CNVT_A 0xE2080
528#define AUD_OUT_DIG_CNVT_B 0xE2180
529#define AUD_OUT_CH_STR 0xE2088
530#define AUD_OUT_STR_DESC_A 0xE2084
531#define AUD_OUT_STR_DESC_B 0xE2184
532#define AUD_PINW_CONNLNG_LIST 0xE20A8
533#define AUD_PINW_CONNLNG_SEL 0xE20AC
534#define AUD_CNTL_ST_A 0xE20B4
535#define AUD_CNTL_ST_B 0xE21B4
536#define AUD_CNTL_ST2 0xE20C0
537#define AUD_HDMIW_STATUS 0xE20D4
538#define AUD_HDMIW_HDMIEDID_A 0xE2050
539#define AUD_HDMIW_HDMIEDID_B 0xE2150
540#define AUD_HDMIW_INFOFR_A 0xE2054
541#define AUD_HDMIW_INFOFR_B 0xE2154
542
543static void dump_ironlake(void)
544{
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400545 uint32_t dword;
546 int i;
Wu Fengguang020abdb2010-04-19 13:13:06 +0800547
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400548 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
549 dump_reg(HDMIC, "HDMI Port C Control");
550 dump_reg(HDMID, "HDMI Port D Control");
551 dump_reg(PCH_DP_B, "DisplayPort B Control Register");
552 dump_reg(PCH_DP_C, "DisplayPort C Control Register");
553 dump_reg(PCH_DP_D, "DisplayPort D Control Register");
554 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
555 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
556 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
557 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
558 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
559 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
560 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
561 dump_reg(AUD_RID, "Audio Revision ID");
562 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
563 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
564 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
565 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
566 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
567 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
568 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
569 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
570 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
571 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
572 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
573 dump_reg(AUD_CNTL_ST2, "Audio Control State 2");
574 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
575 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
576 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
577 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
578 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800579
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400580 printf("\nDetails:\n\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800581
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400582 dword = INREG(AUD_VID_DID);
583 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
584 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
Wu Fengguang020abdb2010-04-19 13:13:06 +0800585
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400586 dword = INREG(AUD_RID);
587 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
588 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
589 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
590 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800591
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400592 dword = INREG(HDMIB);
593 printf("HDMIB HDMIB_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
594 printf("HDMIB Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
595 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
596 printf("HDMIB SDVOB Hot Plug Interrupt Detect Enable\t\t%lu\n", BIT(dword, 23));
597 printf("HDMIB Digital_Port_B_Detected\t\t\t\t%lu\n", BIT(dword, 2));
598 printf("HDMIB Encoding\t\t\t\t\t\t[0x%lx] %s\n",
599 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
600 printf("HDMIB Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
601 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800602
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400603 dword = INREG(HDMIC);
604 printf("HDMIC HDMIC_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
605 printf("HDMIC Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
606 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
607 printf("HDMIC Digital_Port_C_Detected\t\t\t\t%lu\n", BIT(dword, 2));
608 printf("HDMIC Encoding\t\t\t\t\t\t[0x%lx] %s\n",
609 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
610 printf("HDMIC Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
611 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800612
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400613 dword = INREG(HDMID);
614 printf("HDMID HDMID_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
615 printf("HDMID Transcoder_Select\t\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
616 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
617 printf("HDMID Digital_Port_D_Detected\t\t\t\t%lu\n", BIT(dword, 2));
618 printf("HDMID Encoding\t\t\t\t\t\t[0x%lx] %s\n",
619 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
620 printf("HDMID Null_packets_enabled_during_Vsync\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC));
621 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800622
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400623 dword = INREG(PCH_DP_B);
624 printf("PCH_DP_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
625 printf("PCH_DP_B Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
626 printf("PCH_DP_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
627 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
628 printf("PCH_DP_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
629 printf("PCH_DP_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
630 printf("PCH_DP_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguangb5ca6b42011-11-12 11:12:48 +0800631
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400632 dword = INREG(PCH_DP_C);
633 printf("PCH_DP_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
634 printf("PCH_DP_C Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
635 printf("PCH_DP_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
636 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
637 printf("PCH_DP_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
638 printf("PCH_DP_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
639 printf("PCH_DP_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguangb5ca6b42011-11-12 11:12:48 +0800640
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400641 dword = INREG(PCH_DP_D);
642 printf("PCH_DP_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
643 printf("PCH_DP_D Transcoder_Select\t\t\t\t%s\n", BIT(dword, 30) ? "Transcoder B" : "Transcoder A");
644 printf("PCH_DP_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
645 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
646 printf("PCH_DP_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
647 printf("PCH_DP_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
648 printf("PCH_DP_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguangb5ca6b42011-11-12 11:12:48 +0800649
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400650 dword = INREG(AUD_CONFIG_A);
651 printf("AUD_CONFIG_A N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
652 n_index_value[BIT(dword, 29)]);
653 printf("AUD_CONFIG_A N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
654 printf("AUD_CONFIG_A Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
655 printf("AUD_CONFIG_A Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
656 printf("AUD_CONFIG_A Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
657 OPNAME(pixel_clock, BITS(dword, 19, 16)));
658 printf("AUD_CONFIG_A Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
659 dword = INREG(AUD_CONFIG_B);
660 printf("AUD_CONFIG_B N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
661 n_index_value[BIT(dword, 29)]);
662 printf("AUD_CONFIG_B N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
663 printf("AUD_CONFIG_B Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
664 printf("AUD_CONFIG_B Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
665 printf("AUD_CONFIG_B Pixel_Clock\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
666 OPNAME(pixel_clock, BITS(dword, 19, 16)));
667 printf("AUD_CONFIG_B Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800668
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400669 dword = INREG(AUD_CTS_ENABLE_A);
670 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
671 printf("AUD_CTS_ENABLE_A CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
672 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
673 dword = INREG(AUD_CTS_ENABLE_B);
674 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
675 printf("AUD_CTS_ENABLE_B CTS/M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
676 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800677
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400678 dword = INREG(AUD_MISC_CTRL_A);
679 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
680 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
681 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
682 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
683 dword = INREG(AUD_MISC_CTRL_B);
684 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
685 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
686 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
687 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800688
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400689 dword = INREG(AUD_PWRST);
690 printf("AUD_PWRST Function_Group_Device_Power_State_Current\t%s\n", power_state[BITS(dword, 23, 22)]);
691 printf("AUD_PWRST Function_Group_Device_Power_State_Set \t%s\n", power_state[BITS(dword, 21, 20)]);
692 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
693 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
694 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
695 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
696 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
697 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
698 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
699 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
700 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
701 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +0800702
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400703 dword = INREG(AUD_PORT_EN_HD_CFG);
704 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
705 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
706 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
707 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
708 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 12));
709 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 13));
710 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 14));
711 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 16));
712 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 17));
713 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 18));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800714
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400715 dword = INREG(AUD_OUT_DIG_CNVT_A);
716 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
717 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
718 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
719 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
720 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
721 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
722 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
723 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
724 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n", BITS(dword, 19, 16));
725 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800726
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400727 dword = INREG(AUD_OUT_DIG_CNVT_B);
728 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
729 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
730 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
731 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
732 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
733 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
734 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
735 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
736 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n", BITS(dword, 19, 16));
737 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800738
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400739 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
740 for (i = 0; i < 8; i++) {
741 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
742 dword = INREG(AUD_OUT_CH_STR);
743 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
744 1 + BITS(dword, 3, 0),
745 1 + BITS(dword, 7, 4),
746 1 + BITS(dword, 15, 12),
747 1 + BITS(dword, 23, 20));
748 }
Wu Fengguang020abdb2010-04-19 13:13:06 +0800749
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400750 dword = INREG(AUD_OUT_STR_DESC_A);
751 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
752 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
753 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
754 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
755 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800756
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400757 dword = INREG(AUD_OUT_STR_DESC_B);
758 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
759 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
760 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
761 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
762 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800763
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400764 dword = INREG(AUD_PINW_CONNLNG_SEL);
765 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%lu\n", BITS(dword, 7, 0));
766 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%lu\n", BITS(dword, 15, 8));
767 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%lu\n", BITS(dword, 23, 16));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800768
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400769 dword = INREG(AUD_CNTL_ST_A);
770 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
771 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
772 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
773 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
774 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
775 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
776 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
777 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
778 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
779 printf("AUD_CNTL_ST_A ELD_access_address\t\t\t%lu\n", BITS(dword, 9, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800780
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400781 dword = INREG(AUD_CNTL_ST_B);
782 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
783 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
784 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
785 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
786 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
787 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
788 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
789 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
790 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
791 printf("AUD_CNTL_ST_B ELD_access_address\t\t\t%lu\n", BITS(dword, 9, 5));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800792
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400793 dword = INREG(AUD_CNTL_ST2);
794 printf("AUD_CNTL_ST2 CP_ReadyB\t\t\t\t\t%lu\n", BIT(dword, 1));
795 printf("AUD_CNTL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
796 printf("AUD_CNTL_ST2 CP_ReadyC\t\t\t\t\t%lu\n", BIT(dword, 5));
797 printf("AUD_CNTL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
798 printf("AUD_CNTL_ST2 CP_ReadyD\t\t\t\t\t%lu\n", BIT(dword, 9));
799 printf("AUD_CNTL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800800
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400801 dword = INREG(AUD_HDMIW_STATUS);
802 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
803 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
804 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
805 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
806 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
807 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 29));
Wu Fengguang020abdb2010-04-19 13:13:06 +0800808
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400809 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
810 dword = INREG(AUD_CNTL_ST_A);
811 dword &= ~BITMASK(9, 5);
812 OUTREG(AUD_CNTL_ST_A, dword);
813 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
814 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
815 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800816
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400817 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
818 dword = INREG(AUD_CNTL_ST_B);
819 dword &= ~BITMASK(9, 5);
820 OUTREG(AUD_CNTL_ST_B, dword);
821 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
822 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
823 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800824
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400825 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
826 dword = INREG(AUD_CNTL_ST_A);
827 dword &= ~BITMASK(20, 18);
828 dword &= ~BITMASK(3, 0);
829 OUTREG(AUD_CNTL_ST_A, dword);
830 for (i = 0; i < 8; i++)
831 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
832 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800833
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400834 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
835 dword = INREG(AUD_CNTL_ST_B);
836 dword &= ~BITMASK(20, 18);
837 dword &= ~BITMASK(3, 0);
838 OUTREG(AUD_CNTL_ST_B, dword);
839 for (i = 0; i < 8; i++)
840 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
841 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800842
843}
844
845
846#undef AUD_CONFIG_A
847#undef AUD_MISC_CTRL_A
848#undef AUD_VID_DID
849#undef AUD_RID
850#undef AUD_CTS_ENABLE_A
851#undef AUD_PWRST
852#undef AUD_HDMIW_HDMIEDID_A
853#undef AUD_HDMIW_INFOFR_A
854#undef AUD_PORT_EN_HD_CFG
855#undef AUD_OUT_DIG_CNVT_A
856#undef AUD_OUT_STR_DESC_A
857#undef AUD_OUT_CH_STR
858#undef AUD_PINW_CONNLNG_LIST
859#undef AUD_CNTL_ST_A
860#undef AUD_HDMIW_STATUS
861#undef AUD_CONFIG_B
862#undef AUD_MISC_CTRL_B
863#undef AUD_CTS_ENABLE_B
864#undef AUD_HDMIW_HDMIEDID_B
865#undef AUD_HDMIW_INFOFR_B
866#undef AUD_OUT_DIG_CNVT_B
867#undef AUD_OUT_STR_DESC_B
868#undef AUD_CNTL_ST_B
869
870/*
871 * CougarPoint registers
872 */
Wu Fengguang97d20312011-11-12 11:12:45 +0800873#define DP_CTL_B 0xE4100
Wu Fengguang020abdb2010-04-19 13:13:06 +0800874#define DP_CTL_C 0xE4200
875#define DP_AUX_CTL_C 0xE4210
876#define DP_AUX_TST_C 0xE4228
877#define SPORT_DDI_CRC_C 0xE4250
878#define SPORT_DDI_CRC_R 0xE4264
879#define DP_CTL_D 0xE4300
880#define DP_AUX_CTL_D 0xE4310
881#define DP_AUX_TST_D 0xE4328
882#define SPORT_DDI_CRC_CTL_D 0xE4350
883#define AUD_CONFIG_A 0xE5000
884#define AUD_MISC_CTRL_A 0xE5010
885#define AUD_VID_DID 0xE5020
886#define AUD_RID 0xE5024
887#define AUD_CTS_ENABLE_A 0xE5028
888#define AUD_PWRST 0xE504C
889#define AUD_HDMIW_HDMIEDID_A 0xE5050
890#define AUD_HDMIW_INFOFR_A 0xE5054
891#define AUD_PORT_EN_HD_CFG 0xE507C
892#define AUD_OUT_DIG_CNVT_A 0xE5080
893#define AUD_OUT_STR_DESC_A 0xE5084
894#define AUD_OUT_CH_STR 0xE5088
895#define AUD_PINW_CONNLNG_LIST 0xE50A8
896#define AUD_PINW_CONNLNG_SELA 0xE50AC
897#define AUD_CNTL_ST_A 0xE50B4
898#define AUD_CNTRL_ST2 0xE50C0
899#define AUD_CNTRL_ST3 0xE50C4
900#define AUD_HDMIW_STATUS 0xE50D4
901#define AUD_CONFIG_B 0xE5100
902#define AUD_MISC_CTRL_B 0xE5110
903#define AUD_CTS_ENABLE_B 0xE5128
904#define AUD_HDMIW_HDMIEDID_B 0xE5150
905#define AUD_HDMIW_INFOFR_B 0xE5154
906#define AUD_OUT_DIG_CNVT_B 0xE5180
907#define AUD_OUT_STR_DESC_B 0xE5184
908#define AUD_CNTL_ST_B 0xE51B4
909#define AUD_CONFIG_C 0xE5200
910#define AUD_MISC_CTRL_C 0xE5210
911#define AUD_CTS_ENABLE_C 0xE5228
912#define AUD_HDMIW_HDMIEDID_C 0xE5250
913#define AUD_HDMIW_INFOFR_C 0xE5254
914#define AUD_OUT_DIG_CNVT_C 0xE5280
915#define AUD_OUT_STR_DESC_C 0xE5284
916#define AUD_CNTL_ST_C 0xE52B4
917#define AUD_CONFIG_D 0xE5300
918#define AUD_MISC_CTRL_D 0xE5310
919#define AUD_CTS_ENABLE_D 0xE5328
920#define AUD_HDMIW_HDMIEDID_D 0xE5350
921#define AUD_HDMIW_INFOFR_D 0xE5354
922#define AUD_OUT_DIG_CNVT_D 0xE5380
923#define AUD_OUT_STR_DESC_D 0xE5384
924#define AUD_CNTL_ST_D 0xE53B4
925
Wu Fengguange321f132011-11-12 11:12:52 +0800926#define VIDEO_DIP_CTL_A 0xE0200
927#define VIDEO_DIP_CTL_B 0xE1200
928#define VIDEO_DIP_CTL_C 0xE2200
929#define VIDEO_DIP_CTL_D 0xE3200
930
Wu Fengguang020abdb2010-04-19 13:13:06 +0800931
932static void dump_cpt(void)
933{
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400934 uint32_t dword;
935 int i;
Wu Fengguang020abdb2010-04-19 13:13:06 +0800936
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400937 dump_reg(HDMIB, "sDVO/HDMI Port B Control");
938 dump_reg(HDMIC, "HDMI Port C Control");
939 dump_reg(HDMID, "HDMI Port D Control");
940 dump_reg(DP_CTL_B, "DisplayPort B Control");
941 dump_reg(DP_CTL_C, "DisplayPort C Control");
942 dump_reg(DP_CTL_D, "DisplayPort D Control");
943 dump_reg(TRANS_DP_CTL_A, "Transcoder A DisplayPort Control");
944 dump_reg(TRANS_DP_CTL_B, "Transcoder B DisplayPort Control");
945 dump_reg(TRANS_DP_CTL_C, "Transcoder C DisplayPort Control");
946 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
947 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
948 dump_reg(AUD_CONFIG_C, "Audio Configuration - Transcoder C");
949 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
950 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
951 dump_reg(AUD_CTS_ENABLE_C, "Audio CTS Programming Enable - Transcoder C");
952 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
953 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
954 dump_reg(AUD_MISC_CTRL_C, "Audio MISC Control for Transcoder C");
955 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
956 dump_reg(AUD_RID, "Audio Revision ID");
957 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
958 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config");
959 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
960 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
961 dump_reg(AUD_OUT_DIG_CNVT_C, "Audio Digital Converter - Conv C");
962 dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID");
963 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
964 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
965 dump_reg(AUD_OUT_STR_DESC_C, "Audio Stream Descriptor Format - Conv C");
966 dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List");
967 dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select");
968 dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A");
969 dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B");
970 dump_reg(AUD_CNTL_ST_C, "Audio Control State Register - Transcoder C");
971 dump_reg(AUD_CNTRL_ST2, "Audio Control State 2");
972 dump_reg(AUD_CNTRL_ST3, "Audio Control State 3");
973 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status");
974 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
975 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
976 dump_reg(AUD_HDMIW_HDMIEDID_C, "HDMI Data EDID Block - Transcoder C");
977 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
978 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
979 dump_reg(AUD_HDMIW_INFOFR_C, "Audio Widget Data Island Packet - Transcoder C");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800980
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400981 printf("\nDetails:\n\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +0800982
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400983 dword = INREG(VIDEO_DIP_CTL_A);
984 printf("VIDEO_DIP_CTL_A Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)),
985 printf("VIDEO_DIP_CTL_A GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)),
986 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21));
987 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22));
988 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23));
989 printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24));
990 printf("VIDEO_DIP_CTL_A Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
991 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
992 printf("VIDEO_DIP_CTL_A Video_DIP_frequency\t\t\t[0x%lx] %s\n",
993 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
994 printf("VIDEO_DIP_CTL_A Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8));
995 printf("VIDEO_DIP_CTL_A Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0));
Wu Fengguange321f132011-11-12 11:12:52 +0800996
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -0400997 dword = INREG(VIDEO_DIP_CTL_B);
998 printf("VIDEO_DIP_CTL_B Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)),
999 printf("VIDEO_DIP_CTL_B GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)),
1000 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21));
1001 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22));
1002 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23));
1003 printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24));
1004 printf("VIDEO_DIP_CTL_B Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
1005 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
1006 printf("VIDEO_DIP_CTL_B Video_DIP_frequency\t\t\t[0x%lx] %s\n",
1007 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
1008 printf("VIDEO_DIP_CTL_B Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8));
1009 printf("VIDEO_DIP_CTL_B Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0));
Wu Fengguange321f132011-11-12 11:12:52 +08001010
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001011 dword = INREG(VIDEO_DIP_CTL_C);
1012 printf("VIDEO_DIP_CTL_C Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)),
1013 printf("VIDEO_DIP_CTL_C GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)),
1014 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21));
1015 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22));
1016 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23));
1017 printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24));
1018 printf("VIDEO_DIP_CTL_C Video_DIP_buffer_index\t\t\t[0x%lx] %s\n",
1019 BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]);
1020 printf("VIDEO_DIP_CTL_C Video_DIP_frequency\t\t\t[0x%lx] %s\n",
1021 BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]);
1022 printf("VIDEO_DIP_CTL_C Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8));
1023 printf("VIDEO_DIP_CTL_C Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0));
Wu Fengguange321f132011-11-12 11:12:52 +08001024
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001025 dword = INREG(AUD_VID_DID);
1026 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
1027 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
Wu Fengguang020abdb2010-04-19 13:13:06 +08001028
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001029 dword = INREG(AUD_RID);
1030 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
1031 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
1032 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
1033 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001034
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001035 dword = INREG(HDMIB);
1036 printf("HDMIB Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
1037 printf("HDMIB Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
1038 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
1039 printf("HDMIB sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
1040 printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
1041 printf("HDMIB SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", BIT(dword, 23));
1042 printf("HDMIB Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1043 printf("HDMIB Encoding\t\t\t\t\t\t[0x%lx] %s\n",
1044 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
1045 printf("HDMIB HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
1046 printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001047
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001048 dword = INREG(HDMIC);
1049 printf("HDMIC Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
1050 printf("HDMIC Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
1051 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
1052 printf("HDMIC sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
1053 printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
1054 printf("HDMIC SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", BIT(dword, 23));
1055 printf("HDMIC Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1056 printf("HDMIC Encoding\t\t\t\t\t\t[0x%lx] %s\n",
1057 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
1058 printf("HDMIC HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
1059 printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001060
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001061 dword = INREG(HDMID);
1062 printf("HDMID Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE));
1063 printf("HDMID Transcoder_Select\t\t\t\t\t[0x%lx] %s\n",
1064 BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]);
1065 printf("HDMID sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7));
1066 printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5));
1067 printf("HDMID SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", BIT(dword, 23));
1068 printf("HDMID Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1069 printf("HDMID Encoding\t\t\t\t\t\t[0x%lx] %s\n",
1070 BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]);
1071 printf("HDMID HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI");
1072 printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001073
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001074 dword = INREG(DP_CTL_B);
1075 printf("DP_CTL_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
1076 printf("DP_CTL_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
1077 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
1078 printf("DP_CTL_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1079 printf("DP_CTL_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
1080 printf("DP_CTL_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001081
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001082 dword = INREG(DP_CTL_C);
1083 printf("DP_CTL_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
1084 printf("DP_CTL_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
1085 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
1086 printf("DP_CTL_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1087 printf("DP_CTL_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
1088 printf("DP_CTL_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001089
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001090 dword = INREG(DP_CTL_D);
1091 printf("DP_CTL_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31));
1092 printf("DP_CTL_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n",
1093 BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]);
1094 printf("DP_CTL_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2));
1095 printf("DP_CTL_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5));
1096 printf("DP_CTL_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001097
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001098 dword = INREG(AUD_CONFIG_A);
1099 printf("AUD_CONFIG_A N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
1100 n_index_value[BIT(dword, 29)]);
1101 printf("AUD_CONFIG_A N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
1102 printf("AUD_CONFIG_A Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
1103 printf("AUD_CONFIG_A Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
1104 printf("AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1105 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1106 printf("AUD_CONFIG_A Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
1107 dword = INREG(AUD_CONFIG_B);
1108 printf("AUD_CONFIG_B N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
1109 n_index_value[BIT(dword, 29)]);
1110 printf("AUD_CONFIG_B N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
1111 printf("AUD_CONFIG_B Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
1112 printf("AUD_CONFIG_B Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
1113 printf("AUD_CONFIG_B Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1114 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1115 printf("AUD_CONFIG_B Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
1116 dword = INREG(AUD_CONFIG_C);
1117 printf("AUD_CONFIG_C N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
1118 n_index_value[BIT(dword, 29)]);
1119 printf("AUD_CONFIG_C N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
1120 printf("AUD_CONFIG_C Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
1121 printf("AUD_CONFIG_C Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
1122 printf("AUD_CONFIG_C Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1123 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1124 printf("AUD_CONFIG_C Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001125
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001126 dword = INREG(AUD_CTS_ENABLE_A);
1127 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1128 printf("AUD_CTS_ENABLE_A CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1129 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1130 dword = INREG(AUD_CTS_ENABLE_B);
1131 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1132 printf("AUD_CTS_ENABLE_B CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1133 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1134 dword = INREG(AUD_CTS_ENABLE_C);
1135 printf("AUD_CTS_ENABLE_C Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1136 printf("AUD_CTS_ENABLE_C CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1137 printf("AUD_CTS_ENABLE_C CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001138
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001139 dword = INREG(AUD_MISC_CTRL_A);
1140 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1141 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1142 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1143 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1144 dword = INREG(AUD_MISC_CTRL_B);
1145 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1146 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1147 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1148 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1149 dword = INREG(AUD_MISC_CTRL_C);
1150 printf("AUD_MISC_CTRL_C Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1151 printf("AUD_MISC_CTRL_C Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1152 printf("AUD_MISC_CTRL_C Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1153 printf("AUD_MISC_CTRL_C Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001154
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001155 dword = INREG(AUD_PWRST);
1156 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 27, 26)]);
1157 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 25, 24)]);
1158 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
1159 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
1160 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
1161 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
1162 printf("AUD_PWRST ConvC_Widget_PwrSt_Curr \t%s\n", power_state[BITS(dword, 23, 22)]);
1163 printf("AUD_PWRST ConvC_Widget_PwrSt_Req \t%s\n", power_state[BITS(dword, 21, 20)]);
1164 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
1165 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
1166 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
1167 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
1168 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
1169 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +08001170
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001171 dword = INREG(AUD_PORT_EN_HD_CFG);
1172 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
1173 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
1174 printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", BIT(dword, 2));
1175 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
1176 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
1177 printf("AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID\t\t%lu\n", BITS(dword, 15, 12));
1178 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16));
1179 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17));
1180 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18));
1181 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20));
1182 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21));
1183 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001184
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001185 dword = INREG(AUD_OUT_DIG_CNVT_A);
1186 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
1187 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1188 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1189 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
1190 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
1191 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1192 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
1193 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1194 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n", BITS(dword, 19, 16));
1195 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001196
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001197 dword = INREG(AUD_OUT_DIG_CNVT_B);
1198 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
1199 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1200 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1201 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
1202 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
1203 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1204 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
1205 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1206 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n", BITS(dword, 19, 16));
1207 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001208
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001209 dword = INREG(AUD_OUT_DIG_CNVT_C);
1210 printf("AUD_OUT_DIG_CNVT_C V\t\t\t\t\t%lu\n", BIT(dword, 1));
1211 printf("AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1212 printf("AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1213 printf("AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n", BIT(dword, 4));
1214 printf("AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
1215 printf("AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1216 printf("AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n", BIT(dword, 7));
1217 printf("AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1218 printf("AUD_OUT_DIG_CNVT_C Lowest_Channel_Number\t\t%lu\n", BITS(dword, 19, 16));
1219 printf("AUD_OUT_DIG_CNVT_C Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001220
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001221 printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n");
1222 for (i = 0; i < 8; i++) {
1223 OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16));
1224 dword = INREG(AUD_OUT_CH_STR);
1225 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
1226 1 + BITS(dword, 3, 0),
1227 1 + BITS(dword, 7, 4),
1228 1 + BITS(dword, 15, 12),
1229 1 + BITS(dword, 23, 20));
1230 }
Wu Fengguang020abdb2010-04-19 13:13:06 +08001231
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001232 dword = INREG(AUD_OUT_STR_DESC_A);
1233 printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
1234 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
1235 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
1236 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
1237 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001238
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001239 dword = INREG(AUD_OUT_STR_DESC_B);
1240 printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
1241 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
1242 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
1243 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
1244 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001245
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001246 dword = INREG(AUD_OUT_STR_DESC_C);
1247 printf("AUD_OUT_STR_DESC_C HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27));
1248 printf("AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
1249 printf("AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t[%#lx] %s\n",
1250 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
1251 printf("AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001252
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001253 dword = INREG(AUD_PINW_CONNLNG_SEL);
1254 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%#lx\n", BITS(dword, 7, 0));
1255 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%#lx\n", BITS(dword, 15, 8));
1256 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%#lx\n", BITS(dword, 23, 16));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001257
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001258 dword = INREG(AUD_CNTL_ST_A);
1259 printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1260 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
1261 printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
1262 printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
1263 printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1264 printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n",
1265 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1266 printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1267 printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001268
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001269 dword = INREG(AUD_CNTL_ST_B);
1270 printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1271 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
1272 printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
1273 printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
1274 printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1275 printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n",
1276 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1277 printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1278 printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001279
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001280 dword = INREG(AUD_CNTL_ST_C);
1281 printf("AUD_CNTL_ST_C DIP_Port_Select\t\t\t\t[%#lx] %s\n",
1282 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
1283 printf("AUD_CNTL_ST_C DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21));
1284 printf("AUD_CNTL_ST_C DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22));
1285 printf("AUD_CNTL_ST_C DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23));
1286 printf("AUD_CNTL_ST_C DIP_transmission_frequency\t\t[0x%lx] %s\n",
1287 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1288 printf("AUD_CNTL_ST_C ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4));
1289 printf("AUD_CNTL_ST_C ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001290
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001291 dword = INREG(AUD_CNTRL_ST2);
1292 printf("AUD_CNTRL_ST2 CP_ReadyB\t\t\t\t%lu\n", BIT(dword, 1));
1293 printf("AUD_CNTRL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
1294 printf("AUD_CNTRL_ST2 CP_ReadyC\t\t\t\t%lu\n", BIT(dword, 5));
1295 printf("AUD_CNTRL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
1296 printf("AUD_CNTRL_ST2 CP_ReadyD\t\t\t\t%lu\n", BIT(dword, 9));
1297 printf("AUD_CNTRL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001298
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001299 dword = INREG(AUD_CNTRL_ST3);
1300 printf("AUD_CNTRL_ST3 TransA_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 3));
1301 printf("AUD_CNTRL_ST3 TransA_to_Port_Sel\t\t\t[%#lx] %s\n",
1302 BITS(dword, 2, 0), trans_to_port_sel[BITS(dword, 2, 0)]);
1303 printf("AUD_CNTRL_ST3 TransB_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 7));
1304 printf("AUD_CNTRL_ST3 TransB_to_Port_Sel\t\t\t[%#lx] %s\n",
1305 BITS(dword, 6, 4), trans_to_port_sel[BITS(dword, 6, 4)]);
1306 printf("AUD_CNTRL_ST3 TransC_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 11));
1307 printf("AUD_CNTRL_ST3 TransC_to_Port_Sel\t\t\t[%#lx] %s\n",
1308 BITS(dword, 10, 8), trans_to_port_sel[BITS(dword, 10, 8)]);
Wu Fengguang020abdb2010-04-19 13:13:06 +08001309
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001310 dword = INREG(AUD_HDMIW_STATUS);
1311 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27));
1312 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 26));
1313 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
1314 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
1315 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
1316 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
1317 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
1318 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24));
Wu Fengguang020abdb2010-04-19 13:13:06 +08001319
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001320 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
1321 dword = INREG(AUD_CNTL_ST_A);
1322 dword &= ~BITMASK(9, 5);
1323 OUTREG(AUD_CNTL_ST_A, dword);
1324 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1325 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
1326 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001327
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001328 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
1329 dword = INREG(AUD_CNTL_ST_B);
1330 dword &= ~BITMASK(9, 5);
1331 OUTREG(AUD_CNTL_ST_B, dword);
1332 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1333 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
1334 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001335
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001336 printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t");
1337 dword = INREG(AUD_CNTL_ST_C);
1338 dword &= ~BITMASK(9, 5);
1339 OUTREG(AUD_CNTL_ST_C, dword);
1340 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1341 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C)));
1342 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001343
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001344 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
1345 dword = INREG(AUD_CNTL_ST_A);
1346 dword &= ~BITMASK(20, 18);
1347 dword &= ~BITMASK(3, 0);
1348 OUTREG(AUD_CNTL_ST_A, dword);
1349 for (i = 0; i < 8; i++)
1350 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
1351 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001352
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001353 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
1354 dword = INREG(AUD_CNTL_ST_B);
1355 dword &= ~BITMASK(20, 18);
1356 dword &= ~BITMASK(3, 0);
1357 OUTREG(AUD_CNTL_ST_B, dword);
1358 for (i = 0; i < 8; i++)
1359 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
1360 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001361
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001362 printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t");
1363 dword = INREG(AUD_CNTL_ST_C);
1364 dword &= ~BITMASK(20, 18);
1365 dword &= ~BITMASK(3, 0);
1366 OUTREG(AUD_CNTL_ST_C, dword);
1367 for (i = 0; i < 8; i++)
1368 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C)));
1369 printf("\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001370
1371}
1372
Wang Xingchaoc4077222012-08-15 16:13:38 +08001373#undef AUD_CONFIG_A
1374#undef AUD_MISC_CTRL_A
1375#undef AUD_VID_DID
1376#undef AUD_RID
1377#undef AUD_CTS_ENABLE_A
1378#undef AUD_PWRST
1379#undef AUD_HDMIW_HDMIEDID_A
1380#undef AUD_HDMIW_INFOFR_A
1381#undef AUD_PORT_EN_HD_CFG
1382#undef AUD_OUT_DIG_CNVT_A
1383#undef AUD_OUT_STR_DESC_A
1384#undef AUD_OUT_CH_STR
1385#undef AUD_PINW_CONNLNG_LIST
1386#undef AUD_CNTL_ST_A
1387#undef AUD_HDMIW_STATUS
1388#undef AUD_CONFIG_B
1389#undef AUD_MISC_CTRL_B
1390#undef AUD_CTS_ENABLE_B
1391#undef AUD_HDMIW_HDMIEDID_B
1392#undef AUD_HDMIW_INFOFR_B
1393#undef AUD_OUT_DIG_CNVT_B
1394#undef AUD_OUT_STR_DESC_B
1395#undef AUD_CNTL_ST_B
1396#undef AUD_CONFIG_C
1397#undef AUD_MISC_CTRL_C
1398#undef AUD_CTS_ENABLE_C
1399#undef AUD_HDMIW_HDMIEDID_C
1400#undef AUD_HDMIW_INFOFR_C
1401#undef AUD_OUT_DIG_CNVT_C
1402#undef AUD_OUT_STR_DESC_C
1403
1404#undef VIDEO_DIP_CTL_A
1405#undef VIDEO_DIP_CTL_B
1406#undef VIDEO_DIP_CTL_C
1407#undef VIDEO_DIP_CTL_D
1408#undef VIDEO_DIP_DATA
1409
1410/*
1411 * Haswell registers
1412 */
1413
1414/* DisplayPort Transport Control */
1415#define DP_TP_CTL_A 0x64040
1416#define DP_TP_CTL_B 0x64140
1417#define DP_TP_CTL_C 0x64240
1418#define DP_TP_CTL_D 0x64340
1419#define DP_TP_CTL_E 0x64440
1420
1421/* DisplayPort Transport Status */
1422#define DP_TP_ST_A 0x64044
1423#define DP_TP_ST_B 0x64144
1424#define DP_TP_ST_C 0x64244
1425#define DP_TP_ST_D 0x64344
1426#define DP_TP_ST_E 0x64444
1427
Wang Xingchaoc4077222012-08-15 16:13:38 +08001428/* DDI Buffer Control */
1429#define DDI_BUF_CTL_A 0x64000
1430#define DDI_BUF_CTL_B 0x64100
1431#define DDI_BUF_CTL_C 0x64200
1432#define DDI_BUF_CTL_D 0x64300
1433#define DDI_BUF_CTL_E 0x64400
1434
1435/* DDI Buffer Translation */
1436#define DDI_BUF_TRANS_A 0x64e00
1437#define DDI_BUF_TRANS_B 0x64e60
1438#define DDI_BUF_TRANS_C 0x64ec0
1439#define DDI_BUF_TRANS_D 0x64f20
1440#define DDI_BUF_TRANS_E 0x64f80
1441
1442/* DDI Aux Channel */
1443#define DDI_AUX_CHANNEL_CTRL 0x64010
1444#define DDI_AUX_DATA 0x64014
1445#define DDI_AUX_TST 0x64028
1446
1447/* DDI CRC Control */
1448#define DDI_CRC_CTL_A 0x64050
1449#define DDI_CRC_CTL_B 0x64150
1450#define DDI_CRC_CTL_C 0x64250
1451#define DDI_CRC_CTL_D 0x64350
1452#define DDI_CRC_CTL_E 0x64450
1453
1454/* Pipe DDI Function Control */
1455#define PIPE_DDI_FUNC_CTL_A 0x60400
1456#define PIPE_DDI_FUNC_CTL_B 0x61400
1457#define PIPE_DDI_FUNC_CTL_C 0x62400
1458#define PIPE_DDI_FUNC_CTL_EDP 0x6F400
1459
1460/* Pipe Configuration */
1461#define PIPE_CONF_A 0x70008
1462#define PIPE_CONF_B 0x71008
1463#define PIPE_CONF_C 0x72008
1464#define PIPE_CONF_EDP 0x7F008
1465
1466/* Audio registers */
1467#define AUD_CONFIG_A 0x65000
1468#define AUD_MISC_CTRL_A 0x65010
1469#define AUD_VID_DID 0x65020
1470#define AUD_RID 0x65024
1471#define AUD_CTS_ENABLE_A 0x65028
1472#define AUD_PWRST 0x6504C
1473#define AUD_HDMIW_HDMIEDID_A 0x65050
1474#define AUD_HDMIW_INFOFR_A 0x65054
1475#define AUD_PORT_EN_HD_CFG 0x6507C
1476#define AUD_OUT_DIG_CNVT_A 0x65080
1477#define AUD_OUT_STR_DESC_A 0x65084
1478#define AUD_OUT_CHAN_MAP 0x65088
1479#define AUD_PINW_CONNLNG_LIST_A 0x650A8
1480#define AUD_PINW_CONNLNG_LIST_B 0x651A8
1481#define AUD_PINW_CONNLNG_LIST_C 0x652A8
1482#define AUD_PIPE_CONN_SEL_CTRL 0x650AC
1483#define AUD_PIN_ELD_CP_VLD 0x650C0
1484#define AUD_HDMIW_STATUS 0x650D4
1485#define AUD_CONFIG_B 0x65100
1486#define AUD_MISC_CTRL_B 0x65110
1487#define AUD_CTS_ENABLE_B 0x65128
1488#define AUD_HDMIW_HDMIEDID_B 0x65150
1489#define AUD_HDMIW_INFOFR_B 0x65154
1490#define AUD_OUT_DIG_CNVT_B 0x65180
1491#define AUD_OUT_STR_DESC_B 0x65184
1492#define AUD_CONFIG_C 0x65200
1493#define AUD_MISC_CTRL_C 0x65210
1494#define AUD_CTS_ENABLE_C 0x65228
1495#define AUD_HDMIW_HDMIEDID_C 0x65250
1496#define AUD_HDMIW_INFOFR_C 0x65254
1497#define AUD_OUT_DIG_CNVT_C 0x65280
1498#define AUD_OUT_STR_DESC_C 0x65284
1499#define AUD_DIP_ELD_CTRL_ST_A 0x650b4
1500#define AUD_DIP_ELD_CTRL_ST_B 0x651b4
1501#define AUD_DIP_ELD_CTRL_ST_C 0x652b4
1502
1503/* Video DIP Control */
1504#define VIDEO_DIP_CTL_A 0x60200
1505#define VIDEO_DIP_CTL_B 0x61200
1506#define VIDEO_DIP_CTL_C 0x62200
1507#define VIDEO_DIP_CTL_D 0x63200
1508
1509#define VIDEO_DIP_DATA 0x60220
1510#define VIDEO_DIP_ECC 0x60240
1511
1512#define AUD_DP_DIP_STATUS 0x65f20
1513
1514
1515static void dump_hsw(void)
1516{
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001517 uint32_t dword;
1518 int i;
Wang Xingchaoc4077222012-08-15 16:13:38 +08001519
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001520 /* HSW DDI Buffer */
1521 dump_reg(DDI_BUF_CTL_A, "DDI Buffer Controler A");
1522 dump_reg(DDI_BUF_CTL_B, "DDI Buffer Controler B");
1523 dump_reg(DDI_BUF_CTL_C, "DDI Buffer Controler C");
1524 dump_reg(DDI_BUF_CTL_D, "DDI Buffer Controler D");
1525 dump_reg(DDI_BUF_CTL_E, "DDI Buffer Controler E");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001526
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001527 /* HSW Pipe Function */
1528 dump_reg(PIPE_CONF_A, "PIPE Configuration A");
1529 dump_reg(PIPE_CONF_B, "PIPE Configuration B");
1530 dump_reg(PIPE_CONF_C, "PIPE Configuration C");
1531 dump_reg(PIPE_CONF_EDP, "PIPE Configuration EDP");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001532
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001533 dump_reg(PIPE_DDI_FUNC_CTL_A, "PIPE DDI Function Control A");
1534 dump_reg(PIPE_DDI_FUNC_CTL_B, "PIPE DDI Function Control B");
1535 dump_reg(PIPE_DDI_FUNC_CTL_C, "PIPE DDI Function Control C");
1536 dump_reg(PIPE_DDI_FUNC_CTL_EDP, "PIPE DDI Function Control EDP");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001537
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001538 /* HSW Display port */
1539 dump_reg(DP_TP_CTL_A, "DisplayPort Transport A Control");
1540 dump_reg(DP_TP_CTL_B, "DisplayPort Transport B Control");
1541 dump_reg(DP_TP_CTL_C, "DisplayPort Transport C Control");
1542 dump_reg(DP_TP_CTL_D, "DisplayPort Transport D Control");
1543 dump_reg(DP_TP_CTL_E, "DisplayPort Transport E Control");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001544
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001545 dump_reg(DP_TP_ST_A, "DisplayPort Transport A Status");
1546 dump_reg(DP_TP_ST_B, "DisplayPort Transport B Status");
1547 dump_reg(DP_TP_ST_C, "DisplayPort Transport C Status");
1548 dump_reg(DP_TP_ST_D, "DisplayPort Transport D Status");
1549 dump_reg(DP_TP_ST_E, "DisplayPort Transport E Status");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001550
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001551 /* HSW North Display Audio */
1552 dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A");
1553 dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B");
1554 dump_reg(AUD_CONFIG_C, "Audio Configuration - Transcoder C");
1555 dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A");
1556 dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B");
1557 dump_reg(AUD_MISC_CTRL_C, "Audio MISC Control for Transcoder C");
1558 dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID");
1559 dump_reg(AUD_RID, "Audio Revision ID");
1560 dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A");
1561 dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B");
1562 dump_reg(AUD_CTS_ENABLE_C, "Audio CTS Programming Enable - Transcoder C");
1563 dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)");
1564 dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A");
1565 dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B");
1566 dump_reg(AUD_HDMIW_HDMIEDID_C, "HDMI Data EDID Block - Transcoder C");
1567 dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A");
1568 dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B");
1569 dump_reg(AUD_HDMIW_INFOFR_C, "Audio Widget Data Island Packet - Transcoder C");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001570
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001571 dump_reg(AUD_PORT_EN_HD_CFG, "Audio Pipe and Convert Configs");
1572 dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A");
1573 dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B");
1574 dump_reg(AUD_OUT_DIG_CNVT_C, "Audio Digital Converter - Conv C");
1575 dump_reg(AUD_OUT_CHAN_MAP, "Audio Output Channel Mapping");
1576 dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A");
1577 dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B");
1578 dump_reg(AUD_OUT_STR_DESC_C, "Audio Stream Descriptor Format - Conv C");
1579 dump_reg(AUD_PINW_CONNLNG_LIST_A, "Audio Connection List entry and Length - Transcoder A");
1580 dump_reg(AUD_PINW_CONNLNG_LIST_B, "Audio Connection List entry and Length - Transcoder B");
1581 dump_reg(AUD_PINW_CONNLNG_LIST_C, "Audio Connection List entry and Length - Transcoder C");
1582 dump_reg(AUD_PIPE_CONN_SEL_CTRL, "Audio Pipe Connection Select Control");
1583 dump_reg(AUD_DIP_ELD_CTRL_ST_A, "Audio DIP and ELD control state - Transcoder A");
1584 dump_reg(AUD_DIP_ELD_CTRL_ST_B, "Audio DIP and ELD control state - Transcoder B");
1585 dump_reg(AUD_DIP_ELD_CTRL_ST_C, "Audio DIP and ELD control state - Transcoder C");
1586 dump_reg(AUD_PIN_ELD_CP_VLD, "audio pin eld valid status");
1587 dump_reg(AUD_HDMIW_STATUS, "Audio HDMI FIFO Status");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001588
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001589 printf("\nDetails:\n\n");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001590
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001591 dword = INREG(AUD_VID_DID);
1592 printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16);
1593 printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff);
Wang Xingchaoc4077222012-08-15 16:13:38 +08001594
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001595 dword = INREG(AUD_RID);
1596 printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20));
1597 printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16));
1598 printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8));
1599 printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001600
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001601 dword = INREG(AUD_DIP_ELD_CTRL_ST_A);
1602 printf("Audio DIP and ELD control state for TranscoderA\n");
1603 printf("Audio DIP port select\t\t\t\t\t[0x%lx] %s\n",
1604 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
1605
1606 printf("Audio DIP type enable status\t\t\t\t[0x%lx] %s\n",
1607 BITS(dword, 24, 21), dip_type[BIT(dword, 21)]);
1608
1609 printf("DIP Buffer Index \t\t\t\t\t[0x%lx] %s\n",
Wang Xingchaoc4077222012-08-15 16:13:38 +08001610 BITS(dword, 20, 18), dip_index[BITS(dword, 20, 18)]);
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001611 printf("DIP_transmission_frequency\t\t\t\t[0x%lx] %s\n",
1612 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1613 printf("ELD_ACK\t\t\t\t\t\t\t%lu\n", BIT(dword, 4));
1614 printf("ELD_buffer_size\t\t\t\t\t\t%lu\n", BITS(dword, 14, 10));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001615
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001616 dword = INREG(AUD_DIP_ELD_CTRL_ST_B);
1617 printf("Audio DIP and ELD control state for TranscoderB\n");
1618 printf("Audio DIP port select\t\t\t\t\t[0x%lx] %s\n",
1619 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wang Xingchaoc4077222012-08-15 16:13:38 +08001620
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001621 printf("Audio DIP type enable status\t\t\t\t[0x%lx] %s\n",
1622 BITS(dword, 24, 21), dip_type[BIT(dword, 21)]);
Wang Xingchaoc4077222012-08-15 16:13:38 +08001623
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001624 printf("DIP Buffer Index \t\t\t\t\t[0x%lx] %s\n",
Wang Xingchaoc4077222012-08-15 16:13:38 +08001625 BITS(dword, 20, 18), dip_index[BITS(dword, 20, 18)]);
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001626 printf("DIP_transmission_frequency\t\t\t\t[0x%lx] %s\n",
1627 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1628 printf("ELD_ACK\t\t\t\t\t\t\t%lu\n", BIT(dword, 4));
1629 printf("ELD_buffer_size\t\t\t\t\t\t%lu\n", BITS(dword, 14, 10));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001630
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001631 dword = INREG(AUD_DIP_ELD_CTRL_ST_C);
1632 printf("Audio DIP and ELD control state for TranscoderC\n");
1633 printf("Audio DIP port select\t\t\t\t\t[0x%lx] %s\n",
1634 BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]);
Wang Xingchaoc4077222012-08-15 16:13:38 +08001635
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001636 printf("Audio DIP type enable status\t\t\t\t[0x%lx] %s\n",
1637 BITS(dword, 24, 21), dip_type[BIT(dword, 21)]);
Wang Xingchaoc4077222012-08-15 16:13:38 +08001638
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001639 printf("DIP Buffer Index \t\t\t\t\t[0x%lx] %s\n",
Wang Xingchaoc4077222012-08-15 16:13:38 +08001640 BITS(dword, 20, 18), dip_index[BITS(dword, 20, 18)]);
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001641 printf("DIP_transmission_frequency\t\t\t\t[0x%lx] %s\n",
1642 BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]);
1643 printf("ELD_ACK\t\t\t\t\t\t\t%lu\n", BIT(dword, 4));
1644 printf("ELD_buffer_size\t\t\t\t\t\t%lu\n", BITS(dword, 14, 10));
1645
1646 dword = INREG(DDI_BUF_CTL_A);
1647 printf("DDI A Buffer control\n");
1648 printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
1649 printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
Wang Xingchaoc4077222012-08-15 16:13:38 +08001650 BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001651 dword = INREG(DDI_BUF_CTL_B);
1652 printf("DDI B Buffer control\n");
1653 printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
1654 printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
Wang Xingchaoc4077222012-08-15 16:13:38 +08001655 BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001656 dword = INREG(DDI_BUF_CTL_C);
1657 printf("DDI C Buffer control\n");
1658 printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
1659 printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
Wang Xingchaoc4077222012-08-15 16:13:38 +08001660 BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001661 dword = INREG(DDI_BUF_CTL_D);
1662 printf("DDI D Buffer control\n");
1663 printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
1664 printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
1665 BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
1666 dword = INREG(DDI_BUF_CTL_E);
1667 printf("DDI E Buffer control\n");
1668 printf("DDI Buffer Enable\t\t\t\t\t%ld\n", BIT(dword, 31));
1669 printf("DP port width\t\t\t\t\t\t[0x%lx] %s\n",
Wang Xingchaoc4077222012-08-15 16:13:38 +08001670 BITS(dword, 3, 1), dp_port_width[BITS(dword, 3, 1)]);
1671
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001672 dword = INREG(PIPE_DDI_FUNC_CTL_A);
1673 printf("Pipe A DDI Function Control\n");
1674 printf("PIPE DDI Function Enable\t\t\t\t[0x%lx]\n", BIT(dword, 31));
1675 printf("PIPE DDI selection\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 30, 28),
1676 trans_to_port_sel[BITS(dword, 30, 28)]);
1677 printf("PIPE DDI Mode\t\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 26, 24), ddi_mode[BITS(dword, 26, 24)]);
1678 printf("BITS per color\t\t\t\t\t\t[0x%lx]\n", BITS(dword, 22, 20));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001679
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001680 dword = INREG(PIPE_DDI_FUNC_CTL_B);
1681 printf("Pipe B DDI Function Control\n");
1682 printf("PIPE DDI Function Enable\t\t\t\t[0x%lx]\n", BIT(dword, 31));
1683 printf("PIPE DDI selection\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 30, 28),
1684 trans_to_port_sel[BITS(dword, 30, 28)]);
1685 printf("PIPE DDI Mode \t\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 26, 24), ddi_mode[BITS(dword, 26, 24)]);
1686 printf("BITS per color\t\t\t\t\t\t[0x%lx]\n", BITS(dword, 22, 20));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001687
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001688 dword = INREG(PIPE_DDI_FUNC_CTL_C);
1689 printf("Pipe C DDI Function Control\n");
1690 printf("PIPE DDI Function Enable\t\t\t\t[0x%lx]\n", BIT(dword, 31));
1691 printf("PIPE DDI selection\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 30, 28),
1692 trans_to_port_sel[BITS(dword, 30, 28)]);
1693 printf("PIPE DDI Mode \t\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 26, 24), ddi_mode[BITS(dword, 26, 24)]);
1694 printf("BITS per color\t\t\t\t\t\t[0x%lx]\n", BITS(dword, 22, 20));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001695
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001696 dword = INREG(AUD_CONFIG_A);
1697 printf("AUD_CONFIG_A N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
1698 n_index_value[BIT(dword, 29)]);
1699 printf("AUD_CONFIG_A N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
1700 printf("AUD_CONFIG_A Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
1701 printf("AUD_CONFIG_A Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
1702 printf("AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1703 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1704 printf("AUD_CONFIG_A Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
1705 dword = INREG(AUD_CONFIG_B);
1706 printf("AUD_CONFIG_B N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
1707 n_index_value[BIT(dword, 29)]);
1708 printf("AUD_CONFIG_B N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
1709 printf("AUD_CONFIG_B Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
1710 printf("AUD_CONFIG_B Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
1711 printf("AUD_CONFIG_B Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1712 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1713 printf("AUD_CONFIG_B Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
1714 dword = INREG(AUD_CONFIG_C);
1715 printf("AUD_CONFIG_C N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29),
1716 n_index_value[BIT(dword, 29)]);
1717 printf("AUD_CONFIG_C N_programming_enable\t\t\t%lu\n", BIT(dword, 28));
1718 printf("AUD_CONFIG_C Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20));
1719 printf("AUD_CONFIG_C Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4));
1720 printf("AUD_CONFIG_C Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16),
1721 OPNAME(pixel_clock, BITS(dword, 19, 16)));
1722 printf("AUD_CONFIG_C Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001723
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001724 dword = INREG(AUD_CTS_ENABLE_A);
1725 printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1726 printf("AUD_CTS_ENABLE_A CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1727 printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1728 dword = INREG(AUD_CTS_ENABLE_B);
1729 printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1730 printf("AUD_CTS_ENABLE_B CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1731 printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
1732 dword = INREG(AUD_CTS_ENABLE_C);
1733 printf("AUD_CTS_ENABLE_C Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20));
1734 printf("AUD_CTS_ENABLE_C CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M");
1735 printf("AUD_CTS_ENABLE_C CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001736
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001737 dword = INREG(AUD_MISC_CTRL_A);
1738 printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1739 printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1740 printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1741 printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1742 dword = INREG(AUD_MISC_CTRL_B);
1743 printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1744 printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1745 printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1746 printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
1747 dword = INREG(AUD_MISC_CTRL_C);
1748 printf("AUD_MISC_CTRL_C Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2));
1749 printf("AUD_MISC_CTRL_C Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8));
1750 printf("AUD_MISC_CTRL_C Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4));
1751 printf("AUD_MISC_CTRL_C Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001752
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001753 dword = INREG(AUD_PWRST);
1754 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 27, 26)]);
1755 printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 25, 24)]);
1756 printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]);
1757 printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]);
1758 printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]);
1759 printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]);
1760 printf("AUD_PWRST ConvC_Widget_PwrSt_Curr \t%s\n", power_state[BITS(dword, 23, 22)]);
1761 printf("AUD_PWRST ConvC_Widget_PwrSt_Req \t%s\n", power_state[BITS(dword, 21, 20)]);
1762 printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]);
1763 printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]);
1764 printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]);
1765 printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]);
1766 printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]);
1767 printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]);
Wang Xingchaoc4077222012-08-15 16:13:38 +08001768
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001769 dword = INREG(AUD_PORT_EN_HD_CFG);
1770 printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0));
1771 printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1));
1772 printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", BIT(dword, 2));
1773 printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4));
1774 printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8));
1775 printf("AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID\t\t%lu\n", BITS(dword, 15, 12));
1776 printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16));
1777 printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17));
1778 printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18));
1779 printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20));
1780 printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21));
1781 printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001782
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001783 dword = INREG(AUD_OUT_DIG_CNVT_A);
1784 printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1));
1785 printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1786 printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1787 printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4));
1788 printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
1789 printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1790 printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7));
1791 printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1792 printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n", BITS(dword, 19, 16));
1793 printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001794
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001795 dword = INREG(AUD_OUT_DIG_CNVT_B);
1796 printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1));
1797 printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1798 printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1799 printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4));
1800 printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
1801 printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1802 printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7));
1803 printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1804 printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n", BITS(dword, 19, 16));
1805 printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001806
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001807 dword = INREG(AUD_OUT_DIG_CNVT_C);
1808 printf("AUD_OUT_DIG_CNVT_C V\t\t\t\t\t%lu\n", BIT(dword, 1));
1809 printf("AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n", BIT(dword, 2));
1810 printf("AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n", BIT(dword, 3));
1811 printf("AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n", BIT(dword, 4));
1812 printf("AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t%lu\n", BIT(dword, 5));
1813 printf("AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n", BIT(dword, 6));
1814 printf("AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n", BIT(dword, 7));
1815 printf("AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n", BITS(dword, 14, 8));
1816 printf("AUD_OUT_DIG_CNVT_C Lowest_Channel_Number\t\t%lu\n", BITS(dword, 19, 16));
1817 printf("AUD_OUT_DIG_CNVT_C Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001818
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001819 printf("AUD_OUT_CHAN_MAP Converter_Channel_MAP PORTB PORTC PORTD\n");
1820 for (i = 0; i < 8; i++) {
1821 OUTREG(AUD_OUT_CHAN_MAP, i | (i << 8) | (i << 16));
1822 dword = INREG(AUD_OUT_CHAN_MAP);
1823 printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n",
1824 1 + BITS(dword, 3, 0),
1825 1 + BITS(dword, 7, 4),
1826 1 + BITS(dword, 15, 12),
1827 1 + BITS(dword, 23, 20));
1828 }
Wang Xingchaoc4077222012-08-15 16:13:38 +08001829
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001830 dword = INREG(AUD_OUT_STR_DESC_A);
1831 printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
1832 printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n",
1833 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
1834 printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001835
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001836 dword = INREG(AUD_OUT_STR_DESC_B);
1837 printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
1838 printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n",
1839 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
1840 printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001841
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001842 dword = INREG(AUD_OUT_STR_DESC_C);
1843 printf("AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1);
1844 printf("AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t[%#lx] %s\n",
1845 BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4)));
1846 printf("AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001847
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001848 dword = INREG(AUD_PINW_CONNLNG_SEL);
1849 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%#lx\n", BITS(dword, 7, 0));
1850 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%#lx\n", BITS(dword, 15, 8));
1851 printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%#lx\n", BITS(dword, 23, 16));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001852
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001853 dword = INREG(AUD_PIN_ELD_CP_VLD);
1854 printf("AUD_CNTRL_ST2 CP_ReadyB\t\t\t\t%lu\n", BIT(dword, 1));
1855 printf("AUD_CNTRL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0));
1856 printf("AUD_CNTRL_ST2 OUT_enableB\t\t\t\t%lu\n", BIT(dword, 2));
1857 printf("AUD_CNTRL_ST2 CP_ReadyC\t\t\t\t%lu\n", BIT(dword, 5));
1858 printf("AUD_CNTRL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4));
1859 printf("AUD_CNTRL_ST2 OUT_enableC\t\t\t\t%lu\n", BIT(dword, 6));
1860 printf("AUD_CNTRL_ST2 CP_ReadyD\t\t\t\t%lu\n", BIT(dword, 9));
1861 printf("AUD_CNTRL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8));
1862 printf("AUD_CNTRL_ST2 OUT_enableD\t\t\t\t%lu\n", BIT(dword, 10));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001863
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001864 dword = INREG(AUD_HDMIW_STATUS);
1865 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27));
1866 printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 26));
1867 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29));
1868 printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28));
1869 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31));
1870 printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30));
1871 printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25));
1872 printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24));
Wang Xingchaoc4077222012-08-15 16:13:38 +08001873
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001874 printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t");
1875 dword = INREG(AUD_DIP_ELD_CTRL_ST_A);
1876 dword &= ~BITMASK(9, 5);
1877 OUTREG(AUD_DIP_ELD_CTRL_ST_A, dword);
1878 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1879 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A)));
1880 printf("\n");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001881
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001882 printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t");
1883 dword = INREG(AUD_DIP_ELD_CTRL_ST_B);
1884 dword &= ~BITMASK(9, 5);
1885 OUTREG(AUD_DIP_ELD_CTRL_ST_B, dword);
1886 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1887 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B)));
1888 printf("\n");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001889
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001890 printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t");
1891 dword = INREG(AUD_DIP_ELD_CTRL_ST_C);
1892 dword &= ~BITMASK(9, 5);
1893 OUTREG(AUD_DIP_ELD_CTRL_ST_C, dword);
1894 for (i = 0; i < BITS(dword, 14, 10) / 4; i++)
1895 printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C)));
1896 printf("\n");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001897
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001898 printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t");
1899 dword = INREG(AUD_DIP_ELD_CTRL_ST_A);
1900 dword &= ~BITMASK(20, 18);
1901 dword &= ~BITMASK(3, 0);
1902 OUTREG(AUD_DIP_ELD_CTRL_ST_A, dword);
1903 for (i = 0; i < 8; i++)
1904 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A)));
1905 printf("\n");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001906
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001907 printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t");
1908 dword = INREG(AUD_DIP_ELD_CTRL_ST_B);
1909 dword &= ~BITMASK(20, 18);
1910 dword &= ~BITMASK(3, 0);
1911 OUTREG(AUD_DIP_ELD_CTRL_ST_B, dword);
1912 for (i = 0; i < 8; i++)
1913 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B)));
1914 printf("\n");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001915
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001916 printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t");
1917 dword = INREG(AUD_DIP_ELD_CTRL_ST_C);
1918 dword &= ~BITMASK(20, 18);
1919 dword &= ~BITMASK(3, 0);
1920 OUTREG(AUD_DIP_ELD_CTRL_ST_C, dword);
1921 for (i = 0; i < 8; i++)
1922 printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C)));
1923 printf("\n");
Wang Xingchaoc4077222012-08-15 16:13:38 +08001924}
1925
Wu Fengguang020abdb2010-04-19 13:13:06 +08001926int main(int argc, char **argv)
1927{
1928 struct pci_device *pci_dev;
1929
1930 pci_dev = intel_get_pci_device();
1931 devid = pci_dev->device_id; /* XXX not true when mapping! */
1932
1933 do_self_tests();
1934
1935 if (argc == 2)
1936 intel_map_file(argv[1]);
1937 else
1938 intel_get_mmio(pci_dev);
1939
Wu Fengguang63e3c372011-11-12 11:12:44 +08001940 if (IS_GEN6(devid) || IS_GEN7(devid) || getenv("HAS_PCH_SPLIT")) {
Wang Xingchaoc4077222012-08-15 16:13:38 +08001941 if (IS_HASWELL(devid)) {
1942 printf("Haswell audio registers:\n\n");
1943 dump_hsw();
1944 return 0;
1945 }
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001946 printf("%s audio registers:\n\n",
Mengdong Lin3c7dc5c2013-09-09 15:38:32 -04001947 IS_GEN6(devid) ? "SandyBridge" : "IvyBridge");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001948 intel_check_pch();
1949 dump_cpt();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001950 } else if (IS_GEN5(devid)) {
1951 printf("Ironlake audio registers:\n\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001952 dump_ironlake();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001953 } else if (IS_G4X(devid)) {
1954 printf("G45 audio registers:\n\n");
Wu Fengguang020abdb2010-04-19 13:13:06 +08001955 dump_eaglelake();
Wu Fengguang6fcb5cd2011-11-12 11:12:49 +08001956 }
Wu Fengguang020abdb2010-04-19 13:13:06 +08001957
1958 return 0;
Wu Fengguang9e9c9f22009-11-06 11:06:22 +08001959}