blob: 27ff209339273143b8a791e5ff48a9986ca57bc0 [file] [log] [blame]
Stéphane Marchesin25a26062014-09-12 16:18:59 -07001/*
Daniele Castagna7a755de2016-12-16 17:32:30 -05002 * Copyright 2014 The Chromium OS Authors. All rights reserved.
Stéphane Marchesin25a26062014-09-12 16:18:59 -07003 * Use of this source code is governed by a BSD-style license that can be
4 * found in the LICENSE file.
5 */
6
Gurchetan Singh46faf6b2016-08-05 14:40:07 -07007#ifdef DRV_I915
Stéphane Marchesin25a26062014-09-12 16:18:59 -07008
Kristian H. Kristensene8778f02018-04-04 14:21:41 -07009#include <assert.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070010#include <errno.h>
Gurchetan Singh82a8eed2017-01-03 13:01:37 -080011#include <i915_drm.h>
Kristian H. Kristensen9c3fb322018-04-11 15:55:13 -070012#include <stdbool.h>
Gurchetan Singhcc015e82017-01-17 16:15:25 -080013#include <stdio.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070014#include <string.h>
Gurchetan Singhef920532016-08-12 16:38:25 -070015#include <sys/mman.h>
Gurchetan Singhcc35e692019-02-28 15:44:54 -080016#include <unistd.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070017#include <xf86drm.h>
Stéphane Marchesin25a26062014-09-12 16:18:59 -070018
Gurchetan Singh46faf6b2016-08-05 14:40:07 -070019#include "drv_priv.h"
Stéphane Marchesin25a26062014-09-12 16:18:59 -070020#include "helpers.h"
21#include "util.h"
22
Gurchetan Singh68af9c22017-01-18 13:48:11 -080023#define I915_CACHELINE_SIZE 64
24#define I915_CACHELINE_MASK (I915_CACHELINE_SIZE - 1)
25
Nataraj Deshpande586e2d62019-08-21 15:19:46 -070026static const uint32_t render_target_formats[] = { DRM_FORMAT_ABGR16161616F, DRM_FORMAT_ABGR2101010,
Junichi Uekawad441f4e2020-01-29 15:45:16 +090027 DRM_FORMAT_ABGR8888, DRM_FORMAT_ARGB2101010,
28 DRM_FORMAT_ARGB8888, DRM_FORMAT_RGB565,
Gurchetan Singh9d20b9e2019-12-19 09:48:21 -080029 DRM_FORMAT_XBGR2101010, DRM_FORMAT_XBGR8888,
Nataraj Deshpande586e2d62019-08-21 15:19:46 -070030 DRM_FORMAT_XRGB2101010, DRM_FORMAT_XRGB8888 };
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080031
Gurchetan Singh9d20b9e2019-12-19 09:48:21 -080032static const uint32_t texture_source_formats[] = { DRM_FORMAT_R8, DRM_FORMAT_NV12, DRM_FORMAT_P010,
33 DRM_FORMAT_YVU420, DRM_FORMAT_YVU420_ANDROID };
Gurchetan Singh179687e2016-10-28 10:07:35 -070034
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080035struct i915_device {
Gurchetan Singh68af9c22017-01-18 13:48:11 -080036 uint32_t gen;
37 int32_t has_llc;
Stéphane Marchesin25a26062014-09-12 16:18:59 -070038};
39
Gurchetan Singh68af9c22017-01-18 13:48:11 -080040static uint32_t i915_get_gen(int device_id)
Stéphane Marchesin25a26062014-09-12 16:18:59 -070041{
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080042 const uint16_t gen3_ids[] = { 0x2582, 0x2592, 0x2772, 0x27A2, 0x27AE,
43 0x29C2, 0x29B2, 0x29D2, 0xA001, 0xA011 };
Stéphane Marchesina39dfde2014-09-15 15:38:25 -070044 unsigned i;
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -080045 for (i = 0; i < ARRAY_SIZE(gen3_ids); i++)
Stéphane Marchesin25a26062014-09-12 16:18:59 -070046 if (gen3_ids[i] == device_id)
47 return 3;
48
49 return 4;
50}
51
Kristian H. Kristensen9c3fb322018-04-11 15:55:13 -070052/*
53 * We allow allocation of ARGB formats for SCANOUT if the corresponding XRGB
54 * formats supports it. It's up to the caller (chrome ozone) to ultimately not
55 * scan out ARGB if the display controller only supports XRGB, but we'll allow
56 * the allocation of the bo here.
57 */
58static bool format_compatible(const struct combination *combo, uint32_t format)
59{
60 if (combo->format == format)
61 return true;
62
63 switch (format) {
64 case DRM_FORMAT_XRGB8888:
65 return combo->format == DRM_FORMAT_ARGB8888;
66 case DRM_FORMAT_XBGR8888:
67 return combo->format == DRM_FORMAT_ABGR8888;
68 case DRM_FORMAT_RGBX8888:
69 return combo->format == DRM_FORMAT_RGBA8888;
70 case DRM_FORMAT_BGRX8888:
71 return combo->format == DRM_FORMAT_BGRA8888;
Miguel Casas55485402019-11-19 16:10:17 -050072 case DRM_FORMAT_XRGB2101010:
73 return combo->format == DRM_FORMAT_ARGB2101010;
74 case DRM_FORMAT_XBGR2101010:
75 return combo->format == DRM_FORMAT_ABGR2101010;
Kristian H. Kristensen9c3fb322018-04-11 15:55:13 -070076 default:
77 return false;
78 }
79}
80
Gurchetan Singh6b41fb52017-03-01 20:14:39 -080081static int i915_add_kms_item(struct driver *drv, const struct kms_item *item)
82{
83 uint32_t i;
84 struct combination *combo;
85
86 /*
87 * Older hardware can't scanout Y-tiled formats. Newer devices can, and
88 * report this functionality via format modifiers.
89 */
Gurchetan Singhbc9a87d2017-11-03 17:17:35 -070090 for (i = 0; i < drv_array_size(drv->combos); i++) {
91 combo = (struct combination *)drv_array_at_idx(drv->combos, i);
Kristian H. Kristensen9c3fb322018-04-11 15:55:13 -070092 if (!format_compatible(combo, item->format))
Tomasz Figae821cc22017-07-08 15:53:11 +090093 continue;
94
Gurchetan Singhd118a0e2018-01-12 23:31:50 +000095 if (item->modifier == DRM_FORMAT_MOD_LINEAR &&
Tomasz Figae821cc22017-07-08 15:53:11 +090096 combo->metadata.tiling == I915_TILING_X) {
97 /*
98 * FIXME: drv_query_kms() does not report the available modifiers
99 * yet, but we know that all hardware can scanout from X-tiled
100 * buffers, so let's add this to our combinations, except for
101 * cursor, which must not be tiled.
102 */
Gurchetan Singha1892b22017-09-28 16:40:52 -0700103 combo->use_flags |= item->use_flags & ~BO_USE_CURSOR;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800104 }
Tomasz Figae821cc22017-07-08 15:53:11 +0900105
Kristian H. Kristensen3cb5bba2018-04-04 16:10:42 -0700106 /* If we can scanout NV12, we support all tiling modes. */
107 if (item->format == DRM_FORMAT_NV12)
108 combo->use_flags |= item->use_flags;
109
Tomasz Figae821cc22017-07-08 15:53:11 +0900110 if (combo->metadata.modifier == item->modifier)
Gurchetan Singha1892b22017-09-28 16:40:52 -0700111 combo->use_flags |= item->use_flags;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800112 }
113
114 return 0;
115}
116
117static int i915_add_combinations(struct driver *drv)
118{
119 int ret;
Gurchetan Singhbc9a87d2017-11-03 17:17:35 -0700120 uint32_t i;
121 struct drv_array *kms_items;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800122 struct format_metadata metadata;
Gurchetan Singha1892b22017-09-28 16:40:52 -0700123 uint64_t render_use_flags, texture_use_flags;
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700124
Gurchetan Singha1892b22017-09-28 16:40:52 -0700125 render_use_flags = BO_USE_RENDER_MASK;
126 texture_use_flags = BO_USE_TEXTURE_MASK;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800127
128 metadata.tiling = I915_TILING_NONE;
129 metadata.priority = 1;
Kristian H. Kristensenbc8c5932017-10-24 18:36:32 -0700130 metadata.modifier = DRM_FORMAT_MOD_LINEAR;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800131
Gurchetan Singhd3001452017-11-03 17:18:36 -0700132 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
133 &metadata, render_use_flags);
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800134
Gurchetan Singhd3001452017-11-03 17:18:36 -0700135 drv_add_combinations(drv, texture_source_formats, ARRAY_SIZE(texture_source_formats),
136 &metadata, texture_use_flags);
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700137
Hirokazu Honda3b8d4d02019-07-31 16:35:52 +0900138 /*
139 * Chrome uses DMA-buf mmap to write to YV12 buffers, which are then accessed by the
140 * Video Encoder Accelerator (VEA). It could also support NV12 potentially in the future.
141 */
142 drv_modify_combination(drv, DRM_FORMAT_YVU420, &metadata, BO_USE_HW_VIDEO_ENCODER);
David Stevens6116b312019-09-03 10:49:50 +0900143 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
144 BO_USE_HW_VIDEO_ENCODER | BO_USE_HW_VIDEO_DECODER);
Hirokazu Honda3b8d4d02019-07-31 16:35:52 +0900145
Gurchetan Singh71bc6652018-09-17 17:42:05 -0700146 /* Android CTS tests require this. */
147 drv_add_combination(drv, DRM_FORMAT_BGR888, &metadata, BO_USE_SW_MASK);
148
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800149 drv_modify_combination(drv, DRM_FORMAT_XRGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
150 drv_modify_combination(drv, DRM_FORMAT_ARGB8888, &metadata, BO_USE_CURSOR | BO_USE_SCANOUT);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800151
Tomasz Figad30c0a52017-07-05 17:50:18 +0900152 /* IPU3 camera ISP supports only NV12 output. */
153 drv_modify_combination(drv, DRM_FORMAT_NV12, &metadata,
Tomasz Figafd0b0162017-07-11 18:28:02 +0900154 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
Tomasz Figad30c0a52017-07-05 17:50:18 +0900155 /*
156 * R8 format is used for Android's HAL_PIXEL_FORMAT_BLOB and is used for JPEG snapshots
157 * from camera.
158 */
159 drv_modify_combination(drv, DRM_FORMAT_R8, &metadata,
Tomasz Figafd0b0162017-07-11 18:28:02 +0900160 BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE);
Tomasz Figad30c0a52017-07-05 17:50:18 +0900161
Gurchetan Singha1892b22017-09-28 16:40:52 -0700162 render_use_flags &= ~BO_USE_RENDERSCRIPT;
163 render_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
164 render_use_flags &= ~BO_USE_SW_READ_OFTEN;
165 render_use_flags &= ~BO_USE_LINEAR;
Gurchetan Singh2b1d6892018-09-17 16:58:16 -0700166 render_use_flags &= ~BO_USE_PROTECTED;
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700167
Gurchetan Singha1892b22017-09-28 16:40:52 -0700168 texture_use_flags &= ~BO_USE_RENDERSCRIPT;
169 texture_use_flags &= ~BO_USE_SW_WRITE_OFTEN;
170 texture_use_flags &= ~BO_USE_SW_READ_OFTEN;
171 texture_use_flags &= ~BO_USE_LINEAR;
Gurchetan Singh2b1d6892018-09-17 16:58:16 -0700172 texture_use_flags &= ~BO_USE_PROTECTED;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800173
174 metadata.tiling = I915_TILING_X;
175 metadata.priority = 2;
Tomasz Figae821cc22017-07-08 15:53:11 +0900176 metadata.modifier = I915_FORMAT_MOD_X_TILED;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800177
Gurchetan Singhd3001452017-11-03 17:18:36 -0700178 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
179 &metadata, render_use_flags);
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700180
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800181 metadata.tiling = I915_TILING_Y;
182 metadata.priority = 3;
Tomasz Figae821cc22017-07-08 15:53:11 +0900183 metadata.modifier = I915_FORMAT_MOD_Y_TILED;
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800184
Gurchetan Singhd3001452017-11-03 17:18:36 -0700185 drv_add_combinations(drv, render_target_formats, ARRAY_SIZE(render_target_formats),
186 &metadata, render_use_flags);
Gurchetan Singh8ac0c9a2017-05-15 09:34:22 -0700187
Miguel Casascdb25542019-07-18 13:07:30 -0400188 /* Support y-tiled NV12 and P010 for libva */
Gurchetan Singh86ddfdc2018-09-17 17:13:45 -0700189 drv_add_combination(drv, DRM_FORMAT_NV12, &metadata,
190 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
Miguel Casascdb25542019-07-18 13:07:30 -0400191 drv_add_combination(drv, DRM_FORMAT_P010, &metadata,
192 BO_USE_TEXTURE | BO_USE_HW_VIDEO_DECODER);
Kristian H. Kristensen3cb5bba2018-04-04 16:10:42 -0700193
Gurchetan Singhbc9a87d2017-11-03 17:17:35 -0700194 kms_items = drv_query_kms(drv);
195 if (!kms_items)
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800196 return 0;
197
Gurchetan Singhbc9a87d2017-11-03 17:17:35 -0700198 for (i = 0; i < drv_array_size(kms_items); i++) {
199 ret = i915_add_kms_item(drv, (struct kms_item *)drv_array_at_idx(kms_items, i));
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800200 if (ret) {
Gurchetan Singhbc9a87d2017-11-03 17:17:35 -0700201 drv_array_destroy(kms_items);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800202 return ret;
203 }
204 }
205
Gurchetan Singhbc9a87d2017-11-03 17:17:35 -0700206 drv_array_destroy(kms_items);
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800207 return 0;
208}
209
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800210static int i915_align_dimensions(struct bo *bo, uint32_t tiling, uint32_t *stride,
211 uint32_t *aligned_height)
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700212{
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700213 struct i915_device *i915 = bo->drv->priv;
Kristian H. Kristensene8778f02018-04-04 14:21:41 -0700214 uint32_t horizontal_alignment;
215 uint32_t vertical_alignment;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700216
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700217 switch (tiling) {
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700218 default:
219 case I915_TILING_NONE:
Kristian H. Kristensene8778f02018-04-04 14:21:41 -0700220 /*
221 * The Intel GPU doesn't need any alignment in linear mode,
222 * but libva requires the allocation stride to be aligned to
223 * 16 bytes and height to 4 rows. Further, we round up the
224 * horizontal alignment so that row start on a cache line (64
225 * bytes).
226 */
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700227 horizontal_alignment = 64;
Kristian H. Kristensene8778f02018-04-04 14:21:41 -0700228 vertical_alignment = 4;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700229 break;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800230
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700231 case I915_TILING_X:
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700232 horizontal_alignment = 512;
233 vertical_alignment = 8;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700234 break;
235
236 case I915_TILING_Y:
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700237 if (i915->gen == 3) {
238 horizontal_alignment = 512;
239 vertical_alignment = 8;
Gurchetan Singh1b1d56a2017-03-10 16:25:23 -0800240 } else {
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700241 horizontal_alignment = 128;
242 vertical_alignment = 32;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700243 }
244 break;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700245 }
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800246
David Stevens793675a2019-09-25 11:17:48 +0900247 *aligned_height = ALIGN(*aligned_height, vertical_alignment);
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700248 if (i915->gen > 3) {
249 *stride = ALIGN(*stride, horizontal_alignment);
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800250 } else {
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700251 while (*stride > horizontal_alignment)
252 horizontal_alignment <<= 1;
253
254 *stride = horizontal_alignment;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800255 }
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800256
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700257 if (i915->gen <= 3 && *stride > 8192)
258 return -EINVAL;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800259
Gurchetan Singh6423ecb2017-03-29 08:23:40 -0700260 return 0;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700261}
262
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800263static void i915_clflush(void *start, size_t size)
264{
265 void *p = (void *)(((uintptr_t)start) & ~I915_CACHELINE_MASK);
266 void *end = (void *)((uintptr_t)start + size);
267
268 __builtin_ia32_mfence();
269 while (p < end) {
270 __builtin_ia32_clflush(p);
271 p = (void *)((uintptr_t)p + I915_CACHELINE_SIZE);
272 }
273}
274
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800275static int i915_init(struct driver *drv)
276{
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800277 int ret;
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800278 int device_id;
279 struct i915_device *i915;
280 drm_i915_getparam_t get_param;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800281
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800282 i915 = calloc(1, sizeof(*i915));
283 if (!i915)
284 return -ENOMEM;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800285
286 memset(&get_param, 0, sizeof(get_param));
287 get_param.param = I915_PARAM_CHIPSET_ID;
288 get_param.value = &device_id;
289 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
290 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700291 drv_log("Failed to get I915_PARAM_CHIPSET_ID\n");
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800292 free(i915);
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800293 return -EINVAL;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800294 }
295
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800296 i915->gen = i915_get_gen(device_id);
297
298 memset(&get_param, 0, sizeof(get_param));
299 get_param.param = I915_PARAM_HAS_LLC;
300 get_param.value = &i915->has_llc;
301 ret = drmIoctl(drv->fd, DRM_IOCTL_I915_GETPARAM, &get_param);
302 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700303 drv_log("Failed to get I915_PARAM_HAS_LLC\n");
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800304 free(i915);
305 return -EINVAL;
306 }
307
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800308 drv->priv = i915;
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800309
Gurchetan Singh6b41fb52017-03-01 20:14:39 -0800310 return i915_add_combinations(drv);
Gurchetan Singh3eb8d8f2017-01-03 13:36:13 -0800311}
312
Kristian H. Kristensene8778f02018-04-04 14:21:41 -0700313static int i915_bo_from_format(struct bo *bo, uint32_t width, uint32_t height, uint32_t format)
314{
315 uint32_t offset;
316 size_t plane;
Gurchetan Singhcc35e692019-02-28 15:44:54 -0800317 int ret, pagesize;
Kristian H. Kristensene8778f02018-04-04 14:21:41 -0700318
319 offset = 0;
Gurchetan Singhcc35e692019-02-28 15:44:54 -0800320 pagesize = getpagesize();
Kristian H. Kristensene8778f02018-04-04 14:21:41 -0700321 for (plane = 0; plane < drv_num_planes_from_format(format); plane++) {
322 uint32_t stride = drv_stride_from_format(format, width, plane);
323 uint32_t plane_height = drv_height_from_format(format, height, plane);
324
Gurchetan Singh298b7572019-09-19 09:55:18 -0700325 if (bo->meta.tiling != I915_TILING_NONE)
Gurchetan Singhcc35e692019-02-28 15:44:54 -0800326 assert(IS_ALIGNED(offset, pagesize));
Kristian H. Kristensene8778f02018-04-04 14:21:41 -0700327
Gurchetan Singh298b7572019-09-19 09:55:18 -0700328 ret = i915_align_dimensions(bo, bo->meta.tiling, &stride, &plane_height);
Kristian H. Kristensene8778f02018-04-04 14:21:41 -0700329 if (ret)
330 return ret;
331
Gurchetan Singh298b7572019-09-19 09:55:18 -0700332 bo->meta.strides[plane] = stride;
333 bo->meta.sizes[plane] = stride * plane_height;
334 bo->meta.offsets[plane] = offset;
335 offset += bo->meta.sizes[plane];
Kristian H. Kristensene8778f02018-04-04 14:21:41 -0700336 }
337
Gurchetan Singh298b7572019-09-19 09:55:18 -0700338 bo->meta.total_size = ALIGN(offset, pagesize);
Kristian H. Kristensene8778f02018-04-04 14:21:41 -0700339
340 return 0;
341}
342
Kristian H. Kristensen6061eab2017-10-03 13:53:19 -0700343static int i915_bo_create_for_modifier(struct bo *bo, uint32_t width, uint32_t height,
344 uint32_t format, uint64_t modifier)
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700345{
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700346 int ret;
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800347 size_t plane;
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800348 struct drm_i915_gem_create gem_create;
349 struct drm_i915_gem_set_tiling gem_set_tiling;
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700350
Kristian H. Kristensen6061eab2017-10-03 13:53:19 -0700351 switch (modifier) {
352 case DRM_FORMAT_MOD_LINEAR:
Gurchetan Singh298b7572019-09-19 09:55:18 -0700353 bo->meta.tiling = I915_TILING_NONE;
Kristian H. Kristensen6061eab2017-10-03 13:53:19 -0700354 break;
355 case I915_FORMAT_MOD_X_TILED:
Gurchetan Singh298b7572019-09-19 09:55:18 -0700356 bo->meta.tiling = I915_TILING_X;
Kristian H. Kristensen6061eab2017-10-03 13:53:19 -0700357 break;
358 case I915_FORMAT_MOD_Y_TILED:
Mark Yacoubc9565642020-02-07 11:02:22 -0500359 case I915_FORMAT_MOD_Y_TILED_CCS:
Gurchetan Singh298b7572019-09-19 09:55:18 -0700360 bo->meta.tiling = I915_TILING_Y;
Kristian H. Kristensen6061eab2017-10-03 13:53:19 -0700361 break;
362 }
Owen Linbbb69fd2017-06-05 14:33:08 +0800363
Gurchetan Singh298b7572019-09-19 09:55:18 -0700364 bo->meta.format_modifiers[0] = modifier;
Kristian H. Kristensen2b8f89e2018-02-07 16:10:06 -0800365
Kristian H. Kristensene8778f02018-04-04 14:21:41 -0700366 if (format == DRM_FORMAT_YVU420_ANDROID) {
367 /*
368 * We only need to be able to use this as a linear texture,
369 * which doesn't put any HW restrictions on how we lay it
370 * out. The Android format does require the stride to be a
371 * multiple of 16 and expects the Cr and Cb stride to be
372 * ALIGN(Y_stride / 2, 16), which we can make happen by
373 * aligning to 32 bytes here.
374 */
375 uint32_t stride = ALIGN(width, 32);
376 drv_bo_from_format(bo, stride, height, format);
Mark Yacoubc9565642020-02-07 11:02:22 -0500377 } else if (modifier == I915_FORMAT_MOD_Y_TILED_CCS) {
378 /*
379 * For compressed surfaces, we need a color control surface
380 * (CCS). Color compression is only supported for Y tiled
381 * surfaces, and for each 32x16 tiles in the main surface we
382 * need a tile in the control surface. Y tiles are 128 bytes
383 * wide and 32 lines tall and we use that to first compute the
384 * width and height in tiles of the main surface. stride and
385 * height are already multiples of 128 and 32, respectively:
386 */
387 uint32_t stride = drv_stride_from_format(format, width, 0);
388 uint32_t width_in_tiles = DIV_ROUND_UP(stride, 128);
389 uint32_t height_in_tiles = DIV_ROUND_UP(height, 32);
390 uint32_t size = width_in_tiles * height_in_tiles * 4096;
391 uint32_t offset = 0;
392
393 bo->meta.strides[0] = width_in_tiles * 128;
394 bo->meta.sizes[0] = size;
395 bo->meta.offsets[0] = offset;
396 offset += size;
397
398 /*
399 * Now, compute the width and height in tiles of the control
400 * surface by dividing and rounding up.
401 */
402 uint32_t ccs_width_in_tiles = DIV_ROUND_UP(width_in_tiles, 32);
403 uint32_t ccs_height_in_tiles = DIV_ROUND_UP(height_in_tiles, 16);
404 uint32_t ccs_size = ccs_width_in_tiles * ccs_height_in_tiles * 4096;
405
406 /*
407 * With stride and height aligned to y tiles, offset is
408 * already a multiple of 4096, which is the required alignment
409 * of the CCS.
410 */
411 bo->meta.strides[1] = ccs_width_in_tiles * 128;
412 bo->meta.sizes[1] = ccs_size;
413 bo->meta.offsets[1] = offset;
414 offset += ccs_size;
415
416 bo->meta.num_planes = 2;
417 bo->meta.total_size = offset;
Kristian H. Kristensene8778f02018-04-04 14:21:41 -0700418 } else {
419 i915_bo_from_format(bo, width, height, format);
420 }
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800421
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800422 memset(&gem_create, 0, sizeof(gem_create));
Gurchetan Singh298b7572019-09-19 09:55:18 -0700423 gem_create.size = bo->meta.total_size;
Stéphane Marchesin5d867a42014-11-24 17:09:49 -0800424
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800425 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_CREATE, &gem_create);
426 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700427 drv_log("DRM_IOCTL_I915_GEM_CREATE failed (size=%llu)\n", gem_create.size);
Stéphane Marchesin6ac299f2019-03-21 12:23:29 -0700428 return -errno;
Ilja H. Friedelf9d2ab72015-04-09 14:08:36 -0700429 }
Gurchetan Singh83dc4fb2016-07-19 15:52:33 -0700430
Gurchetan Singh298b7572019-09-19 09:55:18 -0700431 for (plane = 0; plane < bo->meta.num_planes; plane++)
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800432 bo->handles[plane].u32 = gem_create.handle;
Daniel Nicoara1de26dc2014-09-25 18:53:19 -0400433
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800434 memset(&gem_set_tiling, 0, sizeof(gem_set_tiling));
435 gem_set_tiling.handle = bo->handles[0].u32;
Gurchetan Singh298b7572019-09-19 09:55:18 -0700436 gem_set_tiling.tiling_mode = bo->meta.tiling;
437 gem_set_tiling.stride = bo->meta.strides[0];
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700438
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800439 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_TILING, &gem_set_tiling);
440 if (ret) {
441 struct drm_gem_close gem_close;
442 memset(&gem_close, 0, sizeof(gem_close));
443 gem_close.handle = bo->handles[0].u32;
444 drmIoctl(bo->drv->fd, DRM_IOCTL_GEM_CLOSE, &gem_close);
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800445
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700446 drv_log("DRM_IOCTL_I915_GEM_SET_TILING failed with %d\n", errno);
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700447 return -errno;
448 }
449
450 return 0;
451}
452
Kristian H. Kristensen6061eab2017-10-03 13:53:19 -0700453static int i915_bo_create(struct bo *bo, uint32_t width, uint32_t height, uint32_t format,
454 uint64_t use_flags)
455{
456 struct combination *combo;
457
458 combo = drv_get_combination(bo->drv, format, use_flags);
459 if (!combo)
460 return -EINVAL;
461
462 return i915_bo_create_for_modifier(bo, width, height, format, combo->metadata.modifier);
463}
464
465static int i915_bo_create_with_modifiers(struct bo *bo, uint32_t width, uint32_t height,
466 uint32_t format, const uint64_t *modifiers, uint32_t count)
467{
468 static const uint64_t modifier_order[] = {
Mark Yacoubc9565642020-02-07 11:02:22 -0500469 I915_FORMAT_MOD_Y_TILED_CCS,
Gurchetan Singh2b1d6892018-09-17 16:58:16 -0700470 I915_FORMAT_MOD_Y_TILED,
471 I915_FORMAT_MOD_X_TILED,
472 DRM_FORMAT_MOD_LINEAR,
Kristian H. Kristensen6061eab2017-10-03 13:53:19 -0700473 };
474 uint64_t modifier;
475
476 modifier = drv_pick_modifier(modifiers, count, modifier_order, ARRAY_SIZE(modifier_order));
477
Kristian H. Kristensen6061eab2017-10-03 13:53:19 -0700478 return i915_bo_create_for_modifier(bo, width, height, format, modifier);
479}
480
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800481static void i915_close(struct driver *drv)
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800482{
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800483 free(drv->priv);
484 drv->priv = NULL;
Gurchetan Singh82a8eed2017-01-03 13:01:37 -0800485}
486
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800487static int i915_bo_import(struct bo *bo, struct drv_import_fd_data *data)
488{
489 int ret;
490 struct drm_i915_gem_get_tiling gem_get_tiling;
491
492 ret = drv_prime_bo_import(bo, data);
493 if (ret)
494 return ret;
495
496 /* TODO(gsingh): export modifiers and get rid of backdoor tiling. */
497 memset(&gem_get_tiling, 0, sizeof(gem_get_tiling));
498 gem_get_tiling.handle = bo->handles[0].u32;
499
500 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_GET_TILING, &gem_get_tiling);
501 if (ret) {
Joe Kniss9e5d12a2017-06-29 11:54:22 -0700502 drv_gem_bo_destroy(bo);
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700503 drv_log("DRM_IOCTL_I915_GEM_GET_TILING failed.\n");
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800504 return ret;
505 }
506
Gurchetan Singh298b7572019-09-19 09:55:18 -0700507 bo->meta.tiling = gem_get_tiling.tiling_mode;
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800508 return 0;
509}
510
Gurchetan Singhee43c302017-11-14 18:20:27 -0800511static void *i915_bo_map(struct bo *bo, struct vma *vma, size_t plane, uint32_t map_flags)
Gurchetan Singhef920532016-08-12 16:38:25 -0700512{
513 int ret;
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800514 void *addr;
Gurchetan Singhef920532016-08-12 16:38:25 -0700515
Mark Yacoubc9565642020-02-07 11:02:22 -0500516 if (bo->meta.format_modifiers[0] == I915_FORMAT_MOD_Y_TILED_CCS)
517 return MAP_FAILED;
518
Gurchetan Singh298b7572019-09-19 09:55:18 -0700519 if (bo->meta.tiling == I915_TILING_NONE) {
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800520 struct drm_i915_gem_mmap gem_map;
521 memset(&gem_map, 0, sizeof(gem_map));
Gurchetan Singhef920532016-08-12 16:38:25 -0700522
Tomasz Figa39eb9512018-11-01 00:45:31 +0900523 /* TODO(b/118799155): We don't seem to have a good way to
524 * detect the use cases for which WC mapping is really needed.
525 * The current heuristic seems overly coarse and may be slowing
526 * down some other use cases unnecessarily.
527 *
528 * For now, care must be taken not to use WC mappings for
529 * Renderscript and camera use cases, as they're
530 * performance-sensitive. */
Gurchetan Singh298b7572019-09-19 09:55:18 -0700531 if ((bo->meta.use_flags & BO_USE_SCANOUT) &&
532 !(bo->meta.use_flags &
Tomasz Figa39eb9512018-11-01 00:45:31 +0900533 (BO_USE_RENDERSCRIPT | BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE)))
Gurchetan Singh5af20232017-09-19 15:10:58 -0700534 gem_map.flags = I915_MMAP_WC;
535
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800536 gem_map.handle = bo->handles[0].u32;
537 gem_map.offset = 0;
Gurchetan Singh298b7572019-09-19 09:55:18 -0700538 gem_map.size = bo->meta.total_size;
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800539
540 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP, &gem_map);
541 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700542 drv_log("DRM_IOCTL_I915_GEM_MMAP failed\n");
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800543 return MAP_FAILED;
544 }
545
546 addr = (void *)(uintptr_t)gem_map.addr_ptr;
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800547 } else {
548 struct drm_i915_gem_mmap_gtt gem_map;
549 memset(&gem_map, 0, sizeof(gem_map));
550
551 gem_map.handle = bo->handles[0].u32;
552
553 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_MMAP_GTT, &gem_map);
554 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700555 drv_log("DRM_IOCTL_I915_GEM_MMAP_GTT failed\n");
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800556 return MAP_FAILED;
557 }
558
Gurchetan Singh298b7572019-09-19 09:55:18 -0700559 addr = mmap(0, bo->meta.total_size, drv_get_prot(map_flags), MAP_SHARED,
560 bo->drv->fd, gem_map.offset);
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800561 }
562
563 if (addr == MAP_FAILED) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700564 drv_log("i915 GEM mmap failed\n");
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800565 return addr;
566 }
567
Gurchetan Singh298b7572019-09-19 09:55:18 -0700568 vma->length = bo->meta.total_size;
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800569 return addr;
570}
Gurchetan Singh1a31e602016-10-06 10:58:00 -0700571
Gurchetan Singh47e629b2017-11-02 14:07:18 -0700572static int i915_bo_invalidate(struct bo *bo, struct mapping *mapping)
Gurchetan Singh2d1877f2017-10-10 14:12:46 -0700573{
574 int ret;
575 struct drm_i915_gem_set_domain set_domain;
576
577 memset(&set_domain, 0, sizeof(set_domain));
578 set_domain.handle = bo->handles[0].u32;
Gurchetan Singh298b7572019-09-19 09:55:18 -0700579 if (bo->meta.tiling == I915_TILING_NONE) {
Gurchetan Singh2d1877f2017-10-10 14:12:46 -0700580 set_domain.read_domains = I915_GEM_DOMAIN_CPU;
Gurchetan Singh47e629b2017-11-02 14:07:18 -0700581 if (mapping->vma->map_flags & BO_MAP_WRITE)
Gurchetan Singh2d1877f2017-10-10 14:12:46 -0700582 set_domain.write_domain = I915_GEM_DOMAIN_CPU;
583 } else {
584 set_domain.read_domains = I915_GEM_DOMAIN_GTT;
Gurchetan Singh47e629b2017-11-02 14:07:18 -0700585 if (mapping->vma->map_flags & BO_MAP_WRITE)
Gurchetan Singh2d1877f2017-10-10 14:12:46 -0700586 set_domain.write_domain = I915_GEM_DOMAIN_GTT;
587 }
588
589 ret = drmIoctl(bo->drv->fd, DRM_IOCTL_I915_GEM_SET_DOMAIN, &set_domain);
590 if (ret) {
Alistair Strachan0cfaaa52018-03-19 14:03:23 -0700591 drv_log("DRM_IOCTL_I915_GEM_SET_DOMAIN with %d\n", ret);
Gurchetan Singh2d1877f2017-10-10 14:12:46 -0700592 return ret;
593 }
594
595 return 0;
596}
597
Gurchetan Singh47e629b2017-11-02 14:07:18 -0700598static int i915_bo_flush(struct bo *bo, struct mapping *mapping)
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800599{
Gurchetan Singh68af9c22017-01-18 13:48:11 -0800600 struct i915_device *i915 = bo->drv->priv;
Gurchetan Singh298b7572019-09-19 09:55:18 -0700601 if (!i915->has_llc && bo->meta.tiling == I915_TILING_NONE)
Gurchetan Singh47e629b2017-11-02 14:07:18 -0700602 i915_clflush(mapping->vma->addr, mapping->vma->length);
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800603
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700604 return 0;
Gurchetan Singhef920532016-08-12 16:38:25 -0700605}
606
Gurchetan Singh0d44d482019-06-04 19:39:51 -0700607static uint32_t i915_resolve_format(struct driver *drv, uint32_t format, uint64_t use_flags)
Gurchetan Singhbfba8c22016-08-16 17:57:10 -0700608{
609 switch (format) {
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800610 case DRM_FORMAT_FLEX_IMPLEMENTATION_DEFINED:
Tomasz Figad30c0a52017-07-05 17:50:18 +0900611 /* KBL camera subsystem requires NV12. */
Gurchetan Singha1892b22017-09-28 16:40:52 -0700612 if (use_flags & (BO_USE_CAMERA_READ | BO_USE_CAMERA_WRITE))
Tomasz Figad30c0a52017-07-05 17:50:18 +0900613 return DRM_FORMAT_NV12;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700614 /*HACK: See b/28671744 */
Gurchetan Singhf3b22da2016-11-21 10:46:38 -0800615 return DRM_FORMAT_XBGR8888;
616 case DRM_FORMAT_FLEX_YCbCr_420_888:
Tomasz Figab92e4f82017-06-22 16:52:43 +0900617 /*
618 * KBL camera subsystem requires NV12. Our other use cases
619 * don't care:
620 * - Hardware video supports NV12,
621 * - USB Camera HALv3 supports NV12,
622 * - USB Camera HALv1 doesn't use this format.
623 * Moreover, NV12 is preferred for video, due to overlay
624 * support on SKL+.
625 */
626 return DRM_FORMAT_NV12;
Gurchetan Singhd6fb5772016-08-29 19:13:51 -0700627 default:
628 return format;
Gurchetan Singhbfba8c22016-08-16 17:57:10 -0700629 }
630}
631
Gurchetan Singh3e9d3832017-10-31 10:36:25 -0700632const struct backend backend_i915 = {
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700633 .name = "i915",
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700634 .init = i915_init,
635 .close = i915_close,
636 .bo_create = i915_bo_create,
Kristian H. Kristensen6061eab2017-10-03 13:53:19 -0700637 .bo_create_with_modifiers = i915_bo_create_with_modifiers,
Gurchetan Singhcc015e82017-01-17 16:15:25 -0800638 .bo_destroy = drv_gem_bo_destroy,
Gurchetan Singhfcad5ad2017-01-05 20:39:31 -0800639 .bo_import = i915_bo_import,
Gurchetan Singhd7c84fd2016-08-16 18:18:24 -0700640 .bo_map = i915_bo_map,
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700641 .bo_unmap = drv_bo_munmap,
Gurchetan Singh2d1877f2017-10-10 14:12:46 -0700642 .bo_invalidate = i915_bo_invalidate,
Gurchetan Singh8e02e052017-09-14 14:18:43 -0700643 .bo_flush = i915_bo_flush,
Gurchetan Singhbfba8c22016-08-16 17:57:10 -0700644 .resolve_format = i915_resolve_format,
Stéphane Marchesin25a26062014-09-12 16:18:59 -0700645};
646
647#endif