sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
| 3 | /*--- ---*/ |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 4 | /*--- This file (main/vex_main.c) is ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 5 | /*--- Copyright (c) 2004 OpenWorks LLP. All rights reserved. ---*/ |
| 6 | /*--- ---*/ |
| 7 | /*---------------------------------------------------------------*/ |
| 8 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | /* |
| 10 | This file is part of LibVEX, a library for dynamic binary |
| 11 | instrumentation and translation. |
| 12 | |
| 13 | Copyright (C) 2004 OpenWorks, LLP. |
| 14 | |
| 15 | This program is free software; you can redistribute it and/or modify |
| 16 | it under the terms of the GNU General Public License as published by |
| 17 | the Free Software Foundation; Version 2 dated June 1991 of the |
| 18 | license. |
| 19 | |
| 20 | This program is distributed in the hope that it will be useful, |
| 21 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 22 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE, or liability |
| 23 | for damages. See the GNU General Public License for more details. |
| 24 | |
| 25 | Neither the names of the U.S. Department of Energy nor the |
| 26 | University of California nor the names of its contributors may be |
| 27 | used to endorse or promote products derived from this software |
| 28 | without prior written permission. |
| 29 | |
| 30 | You should have received a copy of the GNU General Public License |
| 31 | along with this program; if not, write to the Free Software |
| 32 | Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 |
| 33 | USA. |
| 34 | */ |
| 35 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 36 | #include "libvex.h" |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 37 | #include "libvex_emwarn.h" |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 38 | #include "libvex_guest_x86.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 39 | #include "libvex_guest_amd64.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 40 | #include "libvex_guest_arm.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame^] | 41 | #include "libvex_guest_ppc32.h" |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 42 | |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 43 | #include "main/vex_globals.h" |
| 44 | #include "main/vex_util.h" |
| 45 | #include "host-generic/h_generic_regs.h" |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 46 | #include "ir/iropt.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 47 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 48 | #include "host-x86/hdefs.h" |
| 49 | |
| 50 | #include "guest-x86/gdefs.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 51 | #include "guest-amd64/gdefs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 52 | #include "guest-arm/gdefs.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame^] | 53 | #include "guest-ppc32/gdefs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 54 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 55 | |
| 56 | /* This file contains the top level interface to the library. */ |
| 57 | |
| 58 | /* --------- Initialise the library. --------- */ |
| 59 | |
| 60 | /* Exported to library client. */ |
| 61 | |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 62 | const HChar* LibVEX_Version ( void ) |
sewardj | 80f5fce | 2004-12-20 04:37:50 +0000 | [diff] [blame] | 63 | { |
| 64 | return |
| 65 | #include "main/vex_svnversion.h" |
| 66 | ; |
| 67 | } |
| 68 | |
| 69 | |
| 70 | /* Exported to library client. */ |
| 71 | |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 72 | void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) |
| 73 | { |
| 74 | vcon->iropt_verbosity = 0; |
| 75 | vcon->iropt_level = 2; |
| 76 | vcon->iropt_precise_memory_exns = False; |
| 77 | vcon->iropt_unroll_thresh = 120; |
| 78 | vcon->guest_max_insns = 50; |
| 79 | vcon->guest_chase_thresh = 10; |
| 80 | } |
| 81 | |
| 82 | |
| 83 | /* Exported to library client. */ |
| 84 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 85 | void LibVEX_Init ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 86 | /* failure exit function */ |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 87 | __attribute__ ((noreturn)) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 88 | void (*failure_exit) ( void ), |
| 89 | /* logging output function */ |
| 90 | void (*log_bytes) ( Char*, Int nbytes ), |
| 91 | /* debug paranoia level */ |
| 92 | Int debuglevel, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 93 | /* Are we supporting valgrind checking? */ |
| 94 | Bool valgrind_support, |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 95 | /* Control ... */ |
| 96 | /*READONLY*/VexControl* vcon |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 97 | ) |
| 98 | { |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 99 | /* First off, do enough minimal setup so that the following |
| 100 | assertions can fail in a sane fashion, if need be. */ |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 101 | vex_failure_exit = failure_exit; |
| 102 | vex_log_bytes = log_bytes; |
| 103 | |
| 104 | /* Now it's safe to check parameters for sanity. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 105 | vassert(!vex_initdone); |
| 106 | vassert(failure_exit); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 107 | vassert(log_bytes); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 108 | vassert(debuglevel >= 0); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 109 | |
| 110 | vassert(vcon->iropt_verbosity >= 0); |
| 111 | vassert(vcon->iropt_level >= 0); |
| 112 | vassert(vcon->iropt_level <= 2); |
| 113 | vassert(vcon->iropt_unroll_thresh >= 0); |
| 114 | vassert(vcon->iropt_unroll_thresh <= 400); |
| 115 | vassert(vcon->guest_max_insns >= 1); |
| 116 | vassert(vcon->guest_max_insns <= 100); |
| 117 | vassert(vcon->guest_chase_thresh >= 0); |
| 118 | vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 119 | |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 120 | /* All the guest state structs must have an 8-aligned size. */ |
| 121 | vassert(0 == sizeof(VexGuestX86State) % 8); |
| 122 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 123 | /* Check that Vex has been built with sizes of basic types as |
| 124 | stated in priv/libvex_basictypes.h. Failure of any of these is |
| 125 | a serious configuration error and should be corrected |
| 126 | immediately. If any of these assertions fail you can fully |
| 127 | expect Vex not to work properly, if at all. */ |
| 128 | |
| 129 | vassert(1 == sizeof(UChar)); |
| 130 | vassert(1 == sizeof(Char)); |
| 131 | vassert(2 == sizeof(UShort)); |
| 132 | vassert(2 == sizeof(Short)); |
| 133 | vassert(4 == sizeof(UInt)); |
| 134 | vassert(4 == sizeof(Int)); |
| 135 | vassert(8 == sizeof(ULong)); |
| 136 | vassert(8 == sizeof(Long)); |
| 137 | vassert(4 == sizeof(Float)); |
| 138 | vassert(8 == sizeof(Double)); |
| 139 | vassert(1 == sizeof(Bool)); |
| 140 | vassert(4 == sizeof(Addr32)); |
| 141 | vassert(8 == sizeof(Addr64)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 142 | vassert(16 == sizeof(U128)); |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 143 | |
| 144 | vassert(sizeof(void*) == 4 || sizeof(void*) == 8); |
| 145 | vassert(sizeof(void*) == sizeof(int*)); |
| 146 | vassert(sizeof(void*) == sizeof(HWord)); |
| 147 | |
| 148 | /* Really start up .. */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 149 | vex_debuglevel = debuglevel; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 150 | vex_valgrind_support = valgrind_support; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 151 | vex_control = *vcon; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 152 | vex_initdone = True; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 153 | vexSetAllocMode ( VexAllocModeTEMP ); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 154 | } |
| 155 | |
| 156 | |
| 157 | /* --------- Make a translation. --------- */ |
| 158 | |
| 159 | /* Exported to library client. */ |
| 160 | |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 161 | VexTranslateResult LibVEX_Translate ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 162 | /* The instruction sets we are translating from and to. */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 163 | VexArch arch_guest, |
| 164 | VexSubArch subarch_guest, |
| 165 | VexArch arch_host, |
| 166 | VexSubArch subarch_host, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 167 | /* IN: the block to translate, and its guest address. */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 168 | UChar* guest_bytes, |
| 169 | Addr64 guest_bytes_addr, |
| 170 | Bool (*chase_into_ok) ( Addr64 ), |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 171 | /* OUT: which bits of guest code actually got translated */ |
| 172 | VexGuestExtents* guest_extents, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 173 | /* IN: a place to put the resulting code, and its size */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 174 | UChar* host_bytes, |
| 175 | Int host_bytes_size, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 176 | /* OUT: how much of the output area is used. */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 177 | Int* host_bytes_used, |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 178 | /* IN: optionally, two instrumentation functions. */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 179 | IRBB* (*instrument1) ( IRBB*, VexGuestLayout*, IRType hWordTy ), |
| 180 | IRBB* (*instrument2) ( IRBB*, VexGuestLayout*, IRType hWordTy ), |
| 181 | Bool cleanup_after_instrumentation, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 182 | /* IN: optionally, an access check function for guest code. */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 183 | Bool (*byte_accessible) ( Addr64 ), |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 184 | /* IN: debug: trace vex activity at various points */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 185 | Int traceflags |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 186 | ) |
| 187 | { |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 188 | /* This the bundle of functions we need to do the back-end stuff |
| 189 | (insn selection, reg-alloc, assembly) whilst being insulated |
| 190 | from the target instruction set. */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 191 | HReg* available_real_regs; |
| 192 | Int n_available_real_regs; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 193 | Bool (*isMove) (HInstr*, HReg*, HReg*); |
| 194 | void (*getRegUsage) (HRegUsage*, HInstr*); |
| 195 | void (*mapRegs) (HRegRemap*, HInstr*); |
| 196 | HInstr* (*genSpill) ( HReg, Int ); |
| 197 | HInstr* (*genReload) ( HReg, Int ); |
| 198 | void (*ppInstr) ( HInstr* ); |
| 199 | void (*ppReg) ( HReg ); |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 200 | HInstrArray* (*iselBB) ( IRBB*, VexSubArch ); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 201 | IRBB* (*bbToIR) ( UChar*, Addr64, |
| 202 | VexGuestExtents*, |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 203 | Bool(*)(Addr64), |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 204 | Bool(*)(Addr64), |
| 205 | Bool, VexSubArch ); |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 206 | Int (*emit) ( UChar*, Int, HInstr* ); |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 207 | IRExpr* (*specHelper) ( Char*, IRExpr** ); |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 208 | Bool (*preciseMemExnsFn) ( Int, Int ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 209 | |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 210 | VexGuestLayout* guest_layout; |
| 211 | Bool host_is_bigendian = False; |
| 212 | IRBB* irbb; |
| 213 | HInstrArray* vcode; |
| 214 | HInstrArray* rcode; |
| 215 | Int i, j, k, out_used, guest_sizeB; |
| 216 | UChar insn_bytes[32]; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 217 | IRType guest_word_type; |
| 218 | IRType host_word_type; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 219 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 220 | guest_layout = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 221 | available_real_regs = NULL; |
| 222 | n_available_real_regs = 0; |
| 223 | isMove = NULL; |
| 224 | getRegUsage = NULL; |
| 225 | mapRegs = NULL; |
| 226 | genSpill = NULL; |
| 227 | genReload = NULL; |
| 228 | ppInstr = NULL; |
| 229 | ppReg = NULL; |
| 230 | iselBB = NULL; |
| 231 | bbToIR = NULL; |
| 232 | emit = NULL; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 233 | specHelper = NULL; |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 234 | preciseMemExnsFn = NULL; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 235 | guest_word_type = Ity_INVALID; |
| 236 | host_word_type = Ity_INVALID; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 237 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 238 | vex_traceflags = traceflags; |
sewardj | 58800ff | 2004-07-28 01:51:10 +0000 | [diff] [blame] | 239 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 240 | vassert(vex_initdone); |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 241 | vexClearTEMP(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 242 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 243 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 244 | /* First off, check that the guest and host insn sets |
| 245 | are supported. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 246 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 247 | switch (arch_host) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 248 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 249 | case VexArchX86: |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 250 | getAllocableRegs_X86 ( &n_available_real_regs, |
| 251 | &available_real_regs ); |
| 252 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr; |
| 253 | getRegUsage = (void(*)(HRegUsage*,HInstr*)) getRegUsage_X86Instr; |
| 254 | mapRegs = (void(*)(HRegRemap*,HInstr*)) mapRegs_X86Instr; |
| 255 | genSpill = (HInstr*(*)(HReg,Int)) genSpill_X86; |
| 256 | genReload = (HInstr*(*)(HReg,Int)) genReload_X86; |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 257 | ppInstr = (void(*)(HInstr*)) ppX86Instr; |
| 258 | ppReg = (void(*)(HReg)) ppHRegX86; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 259 | iselBB = iselBB_X86; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 260 | emit = (Int(*)(UChar*,Int,HInstr*)) emit_X86Instr; |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 261 | host_is_bigendian = False; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 262 | host_word_type = Ity_I32; |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 263 | vassert(subarch_host == VexSubArchX86_sse0 |
| 264 | || subarch_host == VexSubArchX86_sse1 |
| 265 | || subarch_host == VexSubArchX86_sse2); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 266 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 267 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 268 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 269 | vpanic("LibVEX_Translate: unsupported target insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 270 | } |
| 271 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 272 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 273 | switch (arch_guest) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 274 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 275 | case VexArchX86: |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 276 | preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 277 | bbToIR = bbToIR_X86; |
| 278 | specHelper = guest_x86_spechelper; |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 279 | guest_sizeB = sizeof(VexGuestX86State); |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 280 | guest_word_type = Ity_I32; |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 281 | guest_layout = &x86guest_layout; |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 282 | vassert(subarch_guest == VexSubArchX86_sse0 |
| 283 | || subarch_guest == VexSubArchX86_sse1 |
| 284 | || subarch_guest == VexSubArchX86_sse2); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 285 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 286 | |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 287 | case VexArchAMD64: |
| 288 | preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns; |
| 289 | bbToIR = bbToIR_AMD64; |
| 290 | specHelper = guest_amd64_spechelper; |
| 291 | guest_sizeB = sizeof(VexGuestAMD64State); |
| 292 | guest_word_type = Ity_I64; |
| 293 | guest_layout = &amd64guest_layout; |
| 294 | vassert(subarch_guest == VexSubArch_NONE); |
| 295 | break; |
| 296 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 297 | case VexArchARM: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 298 | preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; |
sewardj | c2c8716 | 2004-11-25 13:07:02 +0000 | [diff] [blame] | 299 | bbToIR = bbToIR_ARM; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 300 | specHelper = guest_arm_spechelper; |
| 301 | guest_sizeB = sizeof(VexGuestARMState); |
| 302 | guest_word_type = Ity_I32; |
| 303 | guest_layout = &armGuest_layout; |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 304 | vassert(subarch_guest == VexSubArchARM_v4); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 305 | break; |
| 306 | |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame^] | 307 | case VexArchPPC32: |
| 308 | preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns; |
| 309 | bbToIR = bbToIR_PPC32; |
| 310 | specHelper = guest_ppc32_spechelper; |
| 311 | guest_sizeB = sizeof(VexGuestPPC32State); |
| 312 | guest_word_type = Ity_I32; |
| 313 | guest_layout = &ppc32Guest_layout; |
| 314 | vassert(subarch_guest == VexSubArchPPC32); |
| 315 | break; |
| 316 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 317 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 318 | vpanic("LibVEX_Translate: unsupported guest insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 319 | } |
| 320 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 321 | /* yet more sanity checks ... */ |
| 322 | if (arch_guest == VexArchX86 && arch_host == VexArchX86) { |
| 323 | /* doesn't necessarily have to be true, but if it isn't it means |
| 324 | we are simulating one flavour of x86 on a different one, which |
| 325 | is pretty strange. */ |
| 326 | vassert(subarch_guest == subarch_host); |
| 327 | } |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 328 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 329 | if (vex_traceflags & VEX_TRACE_FE) |
| 330 | vex_printf("\n------------------------" |
| 331 | " Front end " |
| 332 | "------------------------\n\n"); |
| 333 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 334 | irbb = bbToIR ( guest_bytes, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 335 | guest_bytes_addr, |
| 336 | guest_extents, |
| 337 | byte_accessible, |
sewardj | 5bd4d16 | 2004-11-10 13:02:48 +0000 | [diff] [blame] | 338 | chase_into_ok, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 339 | host_is_bigendian, |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 340 | subarch_guest ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 341 | |
| 342 | if (irbb == NULL) { |
| 343 | /* Access failure. */ |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 344 | vexClearTEMP(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 345 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 346 | return VexTransAccessFail; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 347 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 348 | |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 349 | vassert(guest_extents->n_used >= 1 && guest_extents->n_used <= 3); |
| 350 | vassert(guest_extents->base[0] == guest_bytes_addr); |
| 351 | for (i = 0; i < guest_extents->n_used; i++) { |
| 352 | vassert(guest_extents->len[i] < 10000); /* sanity */ |
| 353 | } |
| 354 | |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 355 | /* If debugging, show the raw guest bytes for this bb. */ |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 356 | if (0 || (vex_traceflags & VEX_TRACE_FE)) { |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 357 | if (guest_extents->n_used > 1) { |
| 358 | vex_printf("can't show code due to extents > 1\n"); |
| 359 | } else { |
| 360 | /* HACK */ |
| 361 | UChar* p = (UChar*)guest_bytes; |
| 362 | UInt guest_bytes_read = (UInt)guest_extents->len[0]; |
| 363 | vex_printf(". 0 %llx %d\n.", guest_bytes_addr, guest_bytes_read ); |
| 364 | for (i = 0; i < guest_bytes_read; i++) |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 365 | vex_printf(" %02x", (Int)p[i] ); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 366 | vex_printf("\n\n"); |
| 367 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 368 | } |
| 369 | |
| 370 | /* Sanity check the initial IR. */ |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 371 | sanityCheckIRBB( irbb, "initial IR", |
| 372 | False/*can be non-flat*/, guest_word_type ); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 373 | |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 374 | /* Clean it up, hopefully a lot. */ |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 375 | irbb = do_iropt_BB ( irbb, specHelper, preciseMemExnsFn, |
| 376 | guest_bytes_addr ); |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 377 | sanityCheckIRBB( irbb, "after initial iropt", |
| 378 | True/*must be flat*/, guest_word_type ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 379 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 380 | if (vex_traceflags & VEX_TRACE_OPT1) { |
| 381 | vex_printf("\n------------------------" |
| 382 | " After pre-instr IR optimisation " |
| 383 | "------------------------\n\n"); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 384 | ppIRBB ( irbb ); |
| 385 | vex_printf("\n"); |
| 386 | } |
| 387 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 388 | /* Get the thing instrumented. */ |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 389 | if (instrument1) |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 390 | irbb = (*instrument1)(irbb, guest_layout, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 391 | if (instrument2) |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 392 | irbb = (*instrument2)(irbb, guest_layout, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 393 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 394 | if (vex_traceflags & VEX_TRACE_INST) { |
| 395 | vex_printf("\n------------------------" |
| 396 | " After instrumentation " |
| 397 | "------------------------\n\n"); |
| 398 | ppIRBB ( irbb ); |
| 399 | vex_printf("\n"); |
| 400 | } |
| 401 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 402 | if (instrument1 || instrument2) |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 403 | sanityCheckIRBB( irbb, "after instrumentation", |
| 404 | True/*must be flat*/, guest_word_type ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 405 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 406 | /* Do a post-instrumentation cleanup pass. */ |
| 407 | if (cleanup_after_instrumentation) { |
| 408 | do_deadcode_BB( irbb ); |
| 409 | irbb = cprop_BB( irbb ); |
| 410 | do_deadcode_BB( irbb ); |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 411 | sanityCheckIRBB( irbb, "after post-instrumentation cleanup", |
| 412 | True/*must be flat*/, guest_word_type ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 413 | } |
| 414 | |
| 415 | if (vex_traceflags & VEX_TRACE_OPT2) { |
| 416 | vex_printf("\n------------------------" |
| 417 | " After post-instr IR optimisation " |
| 418 | "------------------------\n\n"); |
| 419 | ppIRBB ( irbb ); |
| 420 | vex_printf("\n"); |
| 421 | } |
| 422 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 423 | /* Turn it into virtual-registerised code. */ |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 424 | do_deadcode_BB( irbb ); |
| 425 | do_treebuild_BB( irbb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 426 | |
| 427 | if (vex_traceflags & VEX_TRACE_TREES) { |
| 428 | vex_printf("\n------------------------" |
| 429 | " After tree-building " |
| 430 | "------------------------\n\n"); |
| 431 | ppIRBB ( irbb ); |
| 432 | vex_printf("\n"); |
| 433 | } |
| 434 | |
| 435 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 436 | vex_printf("\n------------------------" |
| 437 | " Instruction selection " |
| 438 | "------------------------\n"); |
| 439 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 440 | vcode = iselBB ( irbb, subarch_host ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 441 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 442 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 443 | vex_printf("\n"); |
| 444 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 445 | if (vex_traceflags & VEX_TRACE_VCODE) { |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 446 | for (i = 0; i < vcode->arr_used; i++) { |
| 447 | vex_printf("%3d ", i); |
| 448 | ppInstr(vcode->arr[i]); |
| 449 | vex_printf("\n"); |
| 450 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 451 | vex_printf("\n"); |
| 452 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 453 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 454 | /* Register allocate. */ |
| 455 | rcode = doRegisterAllocation ( vcode, available_real_regs, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 456 | n_available_real_regs, |
| 457 | isMove, getRegUsage, mapRegs, |
| 458 | genSpill, genReload, guest_sizeB, |
| 459 | ppInstr, ppReg ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 460 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 461 | if (vex_traceflags & VEX_TRACE_RCODE) { |
| 462 | vex_printf("\n------------------------" |
| 463 | " Register-allocated code " |
| 464 | "------------------------\n\n"); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 465 | for (i = 0; i < rcode->arr_used; i++) { |
| 466 | vex_printf("%3d ", i); |
| 467 | ppInstr(rcode->arr[i]); |
| 468 | vex_printf("\n"); |
| 469 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 470 | vex_printf("\n"); |
| 471 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 472 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 473 | /* Assemble */ |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 474 | if (vex_traceflags & VEX_TRACE_ASM) { |
| 475 | vex_printf("\n------------------------" |
| 476 | " Assembly " |
| 477 | "------------------------\n\n"); |
| 478 | } |
| 479 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 480 | out_used = 0; /* tracks along the host_bytes array */ |
| 481 | for (i = 0; i < rcode->arr_used; i++) { |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 482 | if (vex_traceflags & VEX_TRACE_ASM) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 483 | ppInstr(rcode->arr[i]); |
| 484 | vex_printf("\n"); |
| 485 | } |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 486 | j = (*emit)( insn_bytes, 32, rcode->arr[i] ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 487 | if (vex_traceflags & VEX_TRACE_ASM) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 488 | for (k = 0; k < j; k++) |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 489 | if (insn_bytes[k] < 16) |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 490 | vex_printf("0%x ", (UInt)insn_bytes[k]); |
| 491 | else |
| 492 | vex_printf("%x ", (UInt)insn_bytes[k]); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 493 | vex_printf("\n\n"); |
| 494 | } |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 495 | if (out_used + j > host_bytes_size) { |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 496 | vexClearTEMP(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 497 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 498 | return VexTransOutputFull; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 499 | } |
| 500 | for (k = 0; k < j; k++) { |
| 501 | host_bytes[out_used] = insn_bytes[k]; |
| 502 | out_used++; |
| 503 | } |
| 504 | vassert(out_used <= host_bytes_size); |
| 505 | } |
| 506 | *host_bytes_used = out_used; |
| 507 | |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 508 | vexClearTEMP(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 509 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 510 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 511 | return VexTransOK; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 512 | } |
| 513 | |
| 514 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 515 | /* --------- Emulation warnings. --------- */ |
| 516 | |
| 517 | HChar* LibVEX_EmWarn_string ( VexEmWarn ew ) |
| 518 | { |
| 519 | switch (ew) { |
| 520 | case EmWarn_NONE: |
| 521 | return "none"; |
| 522 | case EmWarn_X86_x87exns: |
| 523 | return "Unmasking x87 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 524 | case EmWarn_X86_x87precision: |
| 525 | return "Selection of non-80-bit x87 FP precision"; |
| 526 | case EmWarn_X86_sseExns: |
sewardj | 5edfc26 | 2004-12-15 12:13:52 +0000 | [diff] [blame] | 527 | return "Unmasking SSE FP exceptions"; |
| 528 | case EmWarn_X86_fz: |
| 529 | return "Setting %mxcsr.fz (SSE flush-underflows-to-zero mode)"; |
| 530 | case EmWarn_X86_daz: |
| 531 | return "Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 532 | default: |
| 533 | vpanic("LibVEX_EmWarn_string: unknown warning"); |
| 534 | } |
| 535 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 536 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 537 | /* --------- Arch/Subarch names. --------- */ |
| 538 | |
| 539 | const HChar* LibVEX_ppVexArch ( VexArch arch ) |
| 540 | { |
| 541 | switch (arch) { |
| 542 | case VexArch_INVALID: return "INVALID"; |
| 543 | case VexArchX86: return "X86"; |
| 544 | case VexArchAMD64: return "AMD64"; |
| 545 | case VexArchARM: return "ARM"; |
| 546 | default: return "VexArch???"; |
| 547 | } |
| 548 | } |
| 549 | |
| 550 | const HChar* LibVEX_ppVexSubArch ( VexSubArch subarch ) |
| 551 | { |
| 552 | switch (subarch) { |
| 553 | case VexSubArch_INVALID: return "INVALID"; |
| 554 | case VexSubArch_NONE: return "NONE"; |
| 555 | case VexSubArchX86_sse0: return "x86-sse0"; |
| 556 | case VexSubArchX86_sse1: return "x86-sse1"; |
| 557 | case VexSubArchX86_sse2: return "x86-sse2"; |
| 558 | case VexSubArchARM_v4: return "arm-v4"; |
| 559 | default: return "VexSubArch???"; |
| 560 | } |
| 561 | } |
| 562 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 563 | /*---------------------------------------------------------------*/ |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 564 | /*--- end main/vex_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 565 | /*---------------------------------------------------------------*/ |