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Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "genhw/genhw.h"
30#include "kmd/winsys.h"
31#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080032#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080033#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080034#include "cmd_priv.h"
Chia-I Wu09142132014-08-11 15:42:55 +080035
Chia-I Wue24c3292014-08-21 14:05:23 +080036static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
37 struct intel_cmd_writer *writer,
38 XGL_UINT size)
Chia-I Wu730e5362014-08-19 12:15:09 +080039{
40 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wue24c3292014-08-21 14:05:23 +080041 const XGL_GPU_SIZE bo_size = sizeof(uint32_t) * size;
Chia-I Wu730e5362014-08-19 12:15:09 +080042 struct intel_bo *bo;
43 void *ptr;
44
45 bo = intel_winsys_alloc_buffer(winsys,
Chia-I Wu32a22462014-08-26 14:13:46 +080046 "batch buffer", bo_size, true);
Chia-I Wu730e5362014-08-19 12:15:09 +080047 if (!bo)
48 return XGL_ERROR_OUT_OF_GPU_MEMORY;
49
50 ptr = intel_bo_map(bo, true);
51 if (!bo) {
52 intel_bo_unreference(bo);
53 return XGL_ERROR_MEMORY_MAP_FAILED;
54 }
55
Chia-I Wue24c3292014-08-21 14:05:23 +080056 writer->bo = bo;
57 writer->ptr_opaque = ptr;
58 writer->size = size;
59 writer->used = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +080060
61 return XGL_SUCCESS;
62}
63
Chia-I Wu5e25c272014-08-21 20:19:12 +080064static void cmd_writer_copy(struct intel_cmd *cmd,
65 struct intel_cmd_writer *writer,
66 const uint32_t *vals, XGL_UINT len)
67{
68 assert(writer->used + len <= writer->size);
69 memcpy((uint32_t *) writer->ptr_opaque + writer->used,
70 vals, sizeof(uint32_t) * len);
71 writer->used += len;
72}
73
74static void cmd_writer_patch(struct intel_cmd *cmd,
75 struct intel_cmd_writer *writer,
76 XGL_UINT pos, uint32_t val)
77{
78 assert(pos < writer->used);
79 ((uint32_t *) writer->ptr_opaque)[pos] = val;
80}
81
Chia-I Wue24c3292014-08-21 14:05:23 +080082void cmd_writer_grow(struct intel_cmd *cmd,
83 struct intel_cmd_writer *writer)
Chia-I Wu730e5362014-08-19 12:15:09 +080084{
Chia-I Wue24c3292014-08-21 14:05:23 +080085 const XGL_UINT size = writer->size << 1;
86 const XGL_UINT old_used = writer->used;
87 struct intel_bo *old_bo = writer->bo;
88 void *old_ptr = writer->ptr_opaque;
89
90 if (size >= writer->size &&
91 cmd_writer_alloc_and_map(cmd, writer, size) == XGL_SUCCESS) {
92 cmd_writer_copy(cmd, writer, (const uint32_t *) old_ptr, old_used);
93
94 intel_bo_unmap(old_bo);
95 intel_bo_unreference(old_bo);
96 } else {
97 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
98 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
99 "failed to grow command buffer of size %u", writer->size);
100
101 /* wrap it and fail silently */
102 writer->used = 0;
103 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
104 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800105}
106
Chia-I Wue24c3292014-08-21 14:05:23 +0800107static void cmd_writer_unmap(struct intel_cmd *cmd,
108 struct intel_cmd_writer *writer)
Chia-I Wu730e5362014-08-19 12:15:09 +0800109{
Chia-I Wue24c3292014-08-21 14:05:23 +0800110 intel_bo_unmap(writer->bo);
111 writer->ptr_opaque = NULL;
112}
113
114static void cmd_writer_free(struct intel_cmd *cmd,
115 struct intel_cmd_writer *writer)
116{
117 intel_bo_unreference(writer->bo);
118 writer->bo = NULL;
119}
120
121static void cmd_writer_reset(struct intel_cmd *cmd,
122 struct intel_cmd_writer *writer)
123{
124 /* do not reset writer->size as we want to know how big it has grown to */
125 writer->used = 0;
126
127 if (writer->ptr_opaque)
128 cmd_writer_unmap(cmd, writer);
129 if (writer->bo)
130 cmd_writer_free(cmd, writer);
131}
132
133static void cmd_unmap(struct intel_cmd *cmd)
134{
135 cmd_writer_unmap(cmd, &cmd->batch);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800136 cmd_writer_unmap(cmd, &cmd->state);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800137 cmd_writer_unmap(cmd, &cmd->kernel);
Chia-I Wu730e5362014-08-19 12:15:09 +0800138}
139
140static void cmd_reset(struct intel_cmd *cmd)
141{
Chia-I Wue24c3292014-08-21 14:05:23 +0800142 cmd_writer_reset(cmd, &cmd->batch);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800143 cmd_writer_reset(cmd, &cmd->state);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800144 cmd_writer_reset(cmd, &cmd->kernel);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800145
Chia-I Wu338fe642014-08-28 10:43:04 +0800146 if (cmd->bind.shaderCache.shaderArray)
147 icd_free(cmd->bind.shaderCache.shaderArray);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800148 memset(&cmd->bind, 0, sizeof(cmd->bind));
149
Chia-I Wu343b1372014-08-20 16:39:20 +0800150 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800151 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800152}
153
154static void cmd_destroy(struct intel_obj *obj)
155{
156 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
157
158 intel_cmd_destroy(cmd);
159}
160
161XGL_RESULT intel_cmd_create(struct intel_dev *dev,
162 const XGL_CMD_BUFFER_CREATE_INFO *info,
163 struct intel_cmd **cmd_ret)
164{
Chia-I Wu63883292014-08-25 13:50:26 +0800165 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800166 struct intel_cmd *cmd;
167
Chia-I Wu63883292014-08-25 13:50:26 +0800168 switch (info->queueType) {
169 case XGL_QUEUE_TYPE_GRAPHICS:
170 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
171 break;
172 case XGL_QUEUE_TYPE_COMPUTE:
173 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
174 break;
175 case XGL_QUEUE_TYPE_DMA:
176 pipeline_select = -1;
177 break;
178 default:
179 return XGL_ERROR_INVALID_VALUE;
180 break;
181 }
182
Chia-I Wu730e5362014-08-19 12:15:09 +0800183 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
184 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
185 if (!cmd)
186 return XGL_ERROR_OUT_OF_MEMORY;
187
188 cmd->obj.destroy = cmd_destroy;
189
190 cmd->dev = dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800191 cmd->scratch_bo = dev->cmd_scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800192 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800193
Chia-I Wue0cdd832014-08-25 12:38:56 +0800194 /*
195 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
196 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
197 * and end offsets, for each referenced memories.
198 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800199 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
200 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
201 4096, XGL_SYSTEM_ALLOC_INTERNAL);
202 if (!cmd->relocs) {
203 intel_cmd_destroy(cmd);
204 return XGL_ERROR_OUT_OF_MEMORY;
205 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800206
207 *cmd_ret = cmd;
208
209 return XGL_SUCCESS;
210}
211
212void intel_cmd_destroy(struct intel_cmd *cmd)
213{
214 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800215
216 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800217 intel_base_destroy(&cmd->obj.base);
218}
219
220XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags)
221{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800222 XGL_RESULT ret;
Chia-I Wu730e5362014-08-19 12:15:09 +0800223
224 cmd_reset(cmd);
225
Chia-I Wu24565ee2014-08-21 20:24:31 +0800226 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800227 cmd->flags = flags;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800228 cmd->batch.size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800229 }
230
Chia-I Wu24565ee2014-08-21 20:24:31 +0800231 if (!cmd->batch.size) {
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800232 const XGL_UINT size =
233 cmd->dev->gpu->max_batch_buffer_size / sizeof(uint32_t) / 2;
234 XGL_UINT divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800235
236 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
237 divider *= 4;
238
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800239 cmd->batch.size = size / divider;
240 cmd->state.size = size / divider;
241 cmd->kernel.size = 16384 / sizeof(uint32_t) / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800242 }
243
244 ret = cmd_writer_alloc_and_map(cmd, &cmd->batch, cmd->batch.size);
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800245 if (ret == XGL_SUCCESS)
246 ret = cmd_writer_alloc_and_map(cmd, &cmd->state, cmd->state.size);
247 if (ret == XGL_SUCCESS)
248 ret = cmd_writer_alloc_and_map(cmd, &cmd->kernel, cmd->kernel.size);
249 if (ret != XGL_SUCCESS) {
250 cmd_reset(cmd);
Chia-I Wu24565ee2014-08-21 20:24:31 +0800251 return ret;
252 }
253
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800254 cmd_batch_begin(cmd);
255
Chia-I Wu24565ee2014-08-21 20:24:31 +0800256 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800257}
258
259XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
260{
261 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wu343b1372014-08-20 16:39:20 +0800262 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800263
Chia-I Wue24c3292014-08-21 14:05:23 +0800264 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800265
Chia-I Wu343b1372014-08-20 16:39:20 +0800266 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800267 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800268 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
269 uint64_t presumed_offset;
270 int err;
271
Chia-I Wue24c3292014-08-21 14:05:23 +0800272 err = intel_bo_add_reloc(reloc->writer->bo,
Chia-I Wu9ee38722014-08-25 12:11:36 +0800273 sizeof(uint32_t) * reloc->pos, reloc->bo, reloc->val,
Chia-I Wu32a22462014-08-26 14:13:46 +0800274 reloc->flags, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800275 if (err) {
276 cmd->result = XGL_ERROR_UNKNOWN;
277 break;
278 }
279
280 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wue24c3292014-08-21 14:05:23 +0800281 cmd_writer_patch(cmd, reloc->writer, reloc->pos,
282 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800283 }
284
Chia-I Wu730e5362014-08-19 12:15:09 +0800285 cmd_unmap(cmd);
286
Chia-I Wu04966702014-08-20 15:05:03 +0800287 if (cmd->result != XGL_SUCCESS)
288 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800289
290 if (intel_winsys_can_submit_bo(winsys, &cmd->batch.bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800291 return XGL_SUCCESS;
292 else
293 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
294}
295
Chia-I Wu09142132014-08-11 15:42:55 +0800296XGL_RESULT XGLAPI intelCreateCommandBuffer(
297 XGL_DEVICE device,
298 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
299 XGL_CMD_BUFFER* pCmdBuffer)
300{
Chia-I Wu730e5362014-08-19 12:15:09 +0800301 struct intel_dev *dev = intel_dev(device);
302
303 return intel_cmd_create(dev, pCreateInfo,
304 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800305}
306
307XGL_RESULT XGLAPI intelBeginCommandBuffer(
308 XGL_CMD_BUFFER cmdBuffer,
309 XGL_FLAGS flags)
310{
Chia-I Wu730e5362014-08-19 12:15:09 +0800311 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
312
313 return intel_cmd_begin(cmd, flags);
Chia-I Wu09142132014-08-11 15:42:55 +0800314}
315
316XGL_RESULT XGLAPI intelEndCommandBuffer(
317 XGL_CMD_BUFFER cmdBuffer)
318{
Chia-I Wu730e5362014-08-19 12:15:09 +0800319 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
320
321 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800322}
323
324XGL_RESULT XGLAPI intelResetCommandBuffer(
325 XGL_CMD_BUFFER cmdBuffer)
326{
Chia-I Wu730e5362014-08-19 12:15:09 +0800327 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
328
329 cmd_reset(cmd);
330
331 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800332}
333
Chia-I Wu09142132014-08-11 15:42:55 +0800334XGL_VOID XGLAPI intelCmdCopyMemory(
335 XGL_CMD_BUFFER cmdBuffer,
336 XGL_GPU_MEMORY srcMem,
337 XGL_GPU_MEMORY destMem,
338 XGL_UINT regionCount,
339 const XGL_MEMORY_COPY* pRegions)
340{
341}
342
343XGL_VOID XGLAPI intelCmdCopyImage(
344 XGL_CMD_BUFFER cmdBuffer,
345 XGL_IMAGE srcImage,
346 XGL_IMAGE destImage,
347 XGL_UINT regionCount,
348 const XGL_IMAGE_COPY* pRegions)
349{
350}
351
352XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
353 XGL_CMD_BUFFER cmdBuffer,
354 XGL_GPU_MEMORY srcMem,
355 XGL_IMAGE destImage,
356 XGL_UINT regionCount,
357 const XGL_MEMORY_IMAGE_COPY* pRegions)
358{
359}
360
361XGL_VOID XGLAPI intelCmdCopyImageToMemory(
362 XGL_CMD_BUFFER cmdBuffer,
363 XGL_IMAGE srcImage,
364 XGL_GPU_MEMORY destMem,
365 XGL_UINT regionCount,
366 const XGL_MEMORY_IMAGE_COPY* pRegions)
367{
368}
369
370XGL_VOID XGLAPI intelCmdCloneImageData(
371 XGL_CMD_BUFFER cmdBuffer,
372 XGL_IMAGE srcImage,
373 XGL_IMAGE_STATE srcImageState,
374 XGL_IMAGE destImage,
375 XGL_IMAGE_STATE destImageState)
376{
377}
378
379XGL_VOID XGLAPI intelCmdUpdateMemory(
380 XGL_CMD_BUFFER cmdBuffer,
381 XGL_GPU_MEMORY destMem,
382 XGL_GPU_SIZE destOffset,
383 XGL_GPU_SIZE dataSize,
384 const XGL_UINT32* pData)
385{
386}
387
388XGL_VOID XGLAPI intelCmdFillMemory(
389 XGL_CMD_BUFFER cmdBuffer,
390 XGL_GPU_MEMORY destMem,
391 XGL_GPU_SIZE destOffset,
392 XGL_GPU_SIZE fillSize,
393 XGL_UINT32 data)
394{
395}
396
397XGL_VOID XGLAPI intelCmdClearColorImage(
398 XGL_CMD_BUFFER cmdBuffer,
399 XGL_IMAGE image,
400 const XGL_FLOAT color[4],
401 XGL_UINT rangeCount,
402 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
403{
404}
405
406XGL_VOID XGLAPI intelCmdClearColorImageRaw(
407 XGL_CMD_BUFFER cmdBuffer,
408 XGL_IMAGE image,
409 const XGL_UINT32 color[4],
410 XGL_UINT rangeCount,
411 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
412{
413}
414
415XGL_VOID XGLAPI intelCmdClearDepthStencil(
416 XGL_CMD_BUFFER cmdBuffer,
417 XGL_IMAGE image,
418 XGL_FLOAT depth,
419 XGL_UINT32 stencil,
420 XGL_UINT rangeCount,
421 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
422{
423}
424
425XGL_VOID XGLAPI intelCmdResolveImage(
426 XGL_CMD_BUFFER cmdBuffer,
427 XGL_IMAGE srcImage,
428 XGL_IMAGE destImage,
429 XGL_UINT rectCount,
430 const XGL_IMAGE_RESOLVE* pRects)
431{
432}
433
Chia-I Wu09142132014-08-11 15:42:55 +0800434XGL_VOID XGLAPI intelCmdMemoryAtomic(
435 XGL_CMD_BUFFER cmdBuffer,
436 XGL_GPU_MEMORY destMem,
437 XGL_GPU_SIZE destOffset,
438 XGL_UINT64 srcData,
439 XGL_ATOMIC_OP atomicOp)
440{
441}
442
Chia-I Wu09142132014-08-11 15:42:55 +0800443XGL_VOID XGLAPI intelCmdInitAtomicCounters(
444 XGL_CMD_BUFFER cmdBuffer,
445 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
446 XGL_UINT startCounter,
447 XGL_UINT counterCount,
448 const XGL_UINT32* pData)
449{
450}
451
452XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
453 XGL_CMD_BUFFER cmdBuffer,
454 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
455 XGL_UINT startCounter,
456 XGL_UINT counterCount,
457 XGL_GPU_MEMORY srcMem,
458 XGL_GPU_SIZE srcOffset)
459{
460}
461
462XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
463 XGL_CMD_BUFFER cmdBuffer,
464 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
465 XGL_UINT startCounter,
466 XGL_UINT counterCount,
467 XGL_GPU_MEMORY destMem,
468 XGL_GPU_SIZE destOffset)
469{
470}
471
472XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
473 XGL_CMD_BUFFER cmdBuffer,
474 const XGL_CHAR* pMarker)
475{
476}
477
478XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
479 XGL_CMD_BUFFER cmdBuffer)
480{
481}