blob: 76385af80614cf4f6b42e796977614ac9c6bc041 [file] [log] [blame]
Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "genhw/genhw.h"
30#include "kmd/winsys.h"
31#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080032#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080033#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080034#include "cmd_priv.h"
Chia-I Wu09142132014-08-11 15:42:55 +080035
Chia-I Wue24c3292014-08-21 14:05:23 +080036static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +080037 enum intel_cmd_writer_type which,
Chia-I Wue24c3292014-08-21 14:05:23 +080038 XGL_UINT size)
Chia-I Wu730e5362014-08-19 12:15:09 +080039{
Chia-I Wu68f319d2014-09-09 09:43:21 +080040 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wu730e5362014-08-19 12:15:09 +080041 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wue24c3292014-08-21 14:05:23 +080042 const XGL_GPU_SIZE bo_size = sizeof(uint32_t) * size;
Chia-I Wu730e5362014-08-19 12:15:09 +080043 struct intel_bo *bo;
44 void *ptr;
45
46 bo = intel_winsys_alloc_buffer(winsys,
Chia-I Wu32a22462014-08-26 14:13:46 +080047 "batch buffer", bo_size, true);
Chia-I Wu730e5362014-08-19 12:15:09 +080048 if (!bo)
49 return XGL_ERROR_OUT_OF_GPU_MEMORY;
50
51 ptr = intel_bo_map(bo, true);
52 if (!bo) {
53 intel_bo_unreference(bo);
54 return XGL_ERROR_MEMORY_MAP_FAILED;
55 }
56
Chia-I Wue24c3292014-08-21 14:05:23 +080057 writer->bo = bo;
58 writer->ptr_opaque = ptr;
59 writer->size = size;
60 writer->used = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +080061
62 return XGL_SUCCESS;
63}
64
Chia-I Wu5e25c272014-08-21 20:19:12 +080065static void cmd_writer_copy(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +080066 enum intel_cmd_writer_type which,
Chia-I Wu5e25c272014-08-21 20:19:12 +080067 const uint32_t *vals, XGL_UINT len)
68{
Chia-I Wu68f319d2014-09-09 09:43:21 +080069 struct intel_cmd_writer *writer = &cmd->writers[which];
70
Chia-I Wu5e25c272014-08-21 20:19:12 +080071 assert(writer->used + len <= writer->size);
72 memcpy((uint32_t *) writer->ptr_opaque + writer->used,
73 vals, sizeof(uint32_t) * len);
74 writer->used += len;
75}
76
77static void cmd_writer_patch(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +080078 enum intel_cmd_writer_type which,
Chia-I Wu5e25c272014-08-21 20:19:12 +080079 XGL_UINT pos, uint32_t val)
80{
Chia-I Wu68f319d2014-09-09 09:43:21 +080081 struct intel_cmd_writer *writer = &cmd->writers[which];
82
Chia-I Wu5e25c272014-08-21 20:19:12 +080083 assert(pos < writer->used);
84 ((uint32_t *) writer->ptr_opaque)[pos] = val;
85}
86
Chia-I Wue24c3292014-08-21 14:05:23 +080087void cmd_writer_grow(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +080088 enum intel_cmd_writer_type which)
Chia-I Wu730e5362014-08-19 12:15:09 +080089{
Chia-I Wu68f319d2014-09-09 09:43:21 +080090 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wue24c3292014-08-21 14:05:23 +080091 const XGL_UINT size = writer->size << 1;
92 const XGL_UINT old_used = writer->used;
93 struct intel_bo *old_bo = writer->bo;
94 void *old_ptr = writer->ptr_opaque;
95
96 if (size >= writer->size &&
Chia-I Wu68f319d2014-09-09 09:43:21 +080097 cmd_writer_alloc_and_map(cmd, which, size) == XGL_SUCCESS) {
98 cmd_writer_copy(cmd, which, (const uint32_t *) old_ptr, old_used);
Chia-I Wue24c3292014-08-21 14:05:23 +080099
100 intel_bo_unmap(old_bo);
101 intel_bo_unreference(old_bo);
102 } else {
103 intel_dev_log(cmd->dev, XGL_DBG_MSG_ERROR,
104 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
105 "failed to grow command buffer of size %u", writer->size);
106
107 /* wrap it and fail silently */
108 writer->used = 0;
109 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
110 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800111}
112
Chia-I Wue24c3292014-08-21 14:05:23 +0800113static void cmd_writer_unmap(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +0800114 enum intel_cmd_writer_type which)
Chia-I Wu730e5362014-08-19 12:15:09 +0800115{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800116 struct intel_cmd_writer *writer = &cmd->writers[which];
117
Chia-I Wue24c3292014-08-21 14:05:23 +0800118 intel_bo_unmap(writer->bo);
119 writer->ptr_opaque = NULL;
120}
121
122static void cmd_writer_free(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +0800123 enum intel_cmd_writer_type which)
Chia-I Wue24c3292014-08-21 14:05:23 +0800124{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800125 struct intel_cmd_writer *writer = &cmd->writers[which];
126
Chia-I Wue24c3292014-08-21 14:05:23 +0800127 intel_bo_unreference(writer->bo);
128 writer->bo = NULL;
129}
130
131static void cmd_writer_reset(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +0800132 enum intel_cmd_writer_type which)
Chia-I Wue24c3292014-08-21 14:05:23 +0800133{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800134 struct intel_cmd_writer *writer = &cmd->writers[which];
135
Chia-I Wue24c3292014-08-21 14:05:23 +0800136 /* do not reset writer->size as we want to know how big it has grown to */
137 writer->used = 0;
138
139 if (writer->ptr_opaque)
Chia-I Wu68f319d2014-09-09 09:43:21 +0800140 cmd_writer_unmap(cmd, which);
Chia-I Wue24c3292014-08-21 14:05:23 +0800141 if (writer->bo)
Chia-I Wu68f319d2014-09-09 09:43:21 +0800142 cmd_writer_free(cmd, which);
Chia-I Wue24c3292014-08-21 14:05:23 +0800143}
144
145static void cmd_unmap(struct intel_cmd *cmd)
146{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800147 XGL_UINT i;
148
149 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
150 cmd_writer_unmap(cmd, i);
Chia-I Wu730e5362014-08-19 12:15:09 +0800151}
152
153static void cmd_reset(struct intel_cmd *cmd)
154{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800155 XGL_UINT i;
156
157 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
158 cmd_writer_reset(cmd, i);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800159
Chia-I Wu338fe642014-08-28 10:43:04 +0800160 if (cmd->bind.shaderCache.shaderArray)
161 icd_free(cmd->bind.shaderCache.shaderArray);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800162 memset(&cmd->bind, 0, sizeof(cmd->bind));
163
Chia-I Wu343b1372014-08-20 16:39:20 +0800164 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800165 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800166}
167
168static void cmd_destroy(struct intel_obj *obj)
169{
170 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
171
172 intel_cmd_destroy(cmd);
173}
174
175XGL_RESULT intel_cmd_create(struct intel_dev *dev,
176 const XGL_CMD_BUFFER_CREATE_INFO *info,
177 struct intel_cmd **cmd_ret)
178{
Chia-I Wu63883292014-08-25 13:50:26 +0800179 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800180 struct intel_cmd *cmd;
181
Chia-I Wu63883292014-08-25 13:50:26 +0800182 switch (info->queueType) {
183 case XGL_QUEUE_TYPE_GRAPHICS:
184 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
185 break;
186 case XGL_QUEUE_TYPE_COMPUTE:
187 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
188 break;
189 case XGL_QUEUE_TYPE_DMA:
190 pipeline_select = -1;
191 break;
192 default:
193 return XGL_ERROR_INVALID_VALUE;
194 break;
195 }
196
Chia-I Wu730e5362014-08-19 12:15:09 +0800197 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
198 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
199 if (!cmd)
200 return XGL_ERROR_OUT_OF_MEMORY;
201
202 cmd->obj.destroy = cmd_destroy;
203
204 cmd->dev = dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800205 cmd->scratch_bo = dev->cmd_scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800206 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800207
Chia-I Wue0cdd832014-08-25 12:38:56 +0800208 /*
209 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
210 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
211 * and end offsets, for each referenced memories.
212 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800213 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
214 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
215 4096, XGL_SYSTEM_ALLOC_INTERNAL);
216 if (!cmd->relocs) {
217 intel_cmd_destroy(cmd);
218 return XGL_ERROR_OUT_OF_MEMORY;
219 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800220
221 *cmd_ret = cmd;
222
223 return XGL_SUCCESS;
224}
225
226void intel_cmd_destroy(struct intel_cmd *cmd)
227{
228 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800229
230 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800231 intel_base_destroy(&cmd->obj.base);
232}
233
234XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags)
235{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800236 XGL_RESULT ret;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800237 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800238
239 cmd_reset(cmd);
240
Chia-I Wu24565ee2014-08-21 20:24:31 +0800241 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800242 cmd->flags = flags;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800243 cmd->writers[INTEL_CMD_WRITER_BATCH].size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800244 }
245
Chia-I Wu68f319d2014-09-09 09:43:21 +0800246 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].size) {
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800247 const XGL_UINT size =
248 cmd->dev->gpu->max_batch_buffer_size / sizeof(uint32_t) / 2;
249 XGL_UINT divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800250
251 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
252 divider *= 4;
253
Chia-I Wu68f319d2014-09-09 09:43:21 +0800254 cmd->writers[INTEL_CMD_WRITER_BATCH].size = size / divider;
255 cmd->writers[INTEL_CMD_WRITER_STATE].size = size / divider;
256 cmd->writers[INTEL_CMD_WRITER_INSTRUCTION].size =
257 16384 / sizeof(uint32_t) / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800258 }
259
Chia-I Wu68f319d2014-09-09 09:43:21 +0800260 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++) {
261 ret = cmd_writer_alloc_and_map(cmd, i, cmd->writers[i].size);
262 if (ret != XGL_SUCCESS) {
263 cmd_reset(cmd);
264 return ret;
265 }
Chia-I Wu24565ee2014-08-21 20:24:31 +0800266 }
267
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800268 cmd_batch_begin(cmd);
269
Chia-I Wu24565ee2014-08-21 20:24:31 +0800270 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800271}
272
273XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
274{
275 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wu343b1372014-08-20 16:39:20 +0800276 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800277
Chia-I Wue24c3292014-08-21 14:05:23 +0800278 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800279
Chia-I Wu343b1372014-08-20 16:39:20 +0800280 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800281 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800282 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
Chia-I Wu68f319d2014-09-09 09:43:21 +0800283 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
Chia-I Wu343b1372014-08-20 16:39:20 +0800284 uint64_t presumed_offset;
285 int err;
286
Chia-I Wu68f319d2014-09-09 09:43:21 +0800287 err = intel_bo_add_reloc(writer->bo,
Chia-I Wu9ee38722014-08-25 12:11:36 +0800288 sizeof(uint32_t) * reloc->pos, reloc->bo, reloc->val,
Chia-I Wu32a22462014-08-26 14:13:46 +0800289 reloc->flags, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800290 if (err) {
291 cmd->result = XGL_ERROR_UNKNOWN;
292 break;
293 }
294
295 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wu68f319d2014-09-09 09:43:21 +0800296 cmd_writer_patch(cmd, reloc->which, reloc->pos,
Chia-I Wue24c3292014-08-21 14:05:23 +0800297 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800298 }
299
Chia-I Wu730e5362014-08-19 12:15:09 +0800300 cmd_unmap(cmd);
301
Chia-I Wu04966702014-08-20 15:05:03 +0800302 if (cmd->result != XGL_SUCCESS)
303 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800304
Chia-I Wu68f319d2014-09-09 09:43:21 +0800305 if (intel_winsys_can_submit_bo(winsys,
306 &cmd->writers[INTEL_CMD_WRITER_BATCH].bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800307 return XGL_SUCCESS;
308 else
309 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
310}
311
Chia-I Wu09142132014-08-11 15:42:55 +0800312XGL_RESULT XGLAPI intelCreateCommandBuffer(
313 XGL_DEVICE device,
314 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
315 XGL_CMD_BUFFER* pCmdBuffer)
316{
Chia-I Wu730e5362014-08-19 12:15:09 +0800317 struct intel_dev *dev = intel_dev(device);
318
319 return intel_cmd_create(dev, pCreateInfo,
320 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800321}
322
323XGL_RESULT XGLAPI intelBeginCommandBuffer(
324 XGL_CMD_BUFFER cmdBuffer,
325 XGL_FLAGS flags)
326{
Chia-I Wu730e5362014-08-19 12:15:09 +0800327 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
328
329 return intel_cmd_begin(cmd, flags);
Chia-I Wu09142132014-08-11 15:42:55 +0800330}
331
332XGL_RESULT XGLAPI intelEndCommandBuffer(
333 XGL_CMD_BUFFER cmdBuffer)
334{
Chia-I Wu730e5362014-08-19 12:15:09 +0800335 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
336
337 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800338}
339
340XGL_RESULT XGLAPI intelResetCommandBuffer(
341 XGL_CMD_BUFFER cmdBuffer)
342{
Chia-I Wu730e5362014-08-19 12:15:09 +0800343 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
344
345 cmd_reset(cmd);
346
347 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800348}
349
Chia-I Wu09142132014-08-11 15:42:55 +0800350XGL_VOID XGLAPI intelCmdCopyMemory(
351 XGL_CMD_BUFFER cmdBuffer,
352 XGL_GPU_MEMORY srcMem,
353 XGL_GPU_MEMORY destMem,
354 XGL_UINT regionCount,
355 const XGL_MEMORY_COPY* pRegions)
356{
357}
358
359XGL_VOID XGLAPI intelCmdCopyImage(
360 XGL_CMD_BUFFER cmdBuffer,
361 XGL_IMAGE srcImage,
362 XGL_IMAGE destImage,
363 XGL_UINT regionCount,
364 const XGL_IMAGE_COPY* pRegions)
365{
366}
367
368XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
369 XGL_CMD_BUFFER cmdBuffer,
370 XGL_GPU_MEMORY srcMem,
371 XGL_IMAGE destImage,
372 XGL_UINT regionCount,
373 const XGL_MEMORY_IMAGE_COPY* pRegions)
374{
375}
376
377XGL_VOID XGLAPI intelCmdCopyImageToMemory(
378 XGL_CMD_BUFFER cmdBuffer,
379 XGL_IMAGE srcImage,
380 XGL_GPU_MEMORY destMem,
381 XGL_UINT regionCount,
382 const XGL_MEMORY_IMAGE_COPY* pRegions)
383{
384}
385
386XGL_VOID XGLAPI intelCmdCloneImageData(
387 XGL_CMD_BUFFER cmdBuffer,
388 XGL_IMAGE srcImage,
389 XGL_IMAGE_STATE srcImageState,
390 XGL_IMAGE destImage,
391 XGL_IMAGE_STATE destImageState)
392{
393}
394
395XGL_VOID XGLAPI intelCmdUpdateMemory(
396 XGL_CMD_BUFFER cmdBuffer,
397 XGL_GPU_MEMORY destMem,
398 XGL_GPU_SIZE destOffset,
399 XGL_GPU_SIZE dataSize,
400 const XGL_UINT32* pData)
401{
402}
403
404XGL_VOID XGLAPI intelCmdFillMemory(
405 XGL_CMD_BUFFER cmdBuffer,
406 XGL_GPU_MEMORY destMem,
407 XGL_GPU_SIZE destOffset,
408 XGL_GPU_SIZE fillSize,
409 XGL_UINT32 data)
410{
411}
412
413XGL_VOID XGLAPI intelCmdClearColorImage(
414 XGL_CMD_BUFFER cmdBuffer,
415 XGL_IMAGE image,
416 const XGL_FLOAT color[4],
417 XGL_UINT rangeCount,
418 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
419{
420}
421
422XGL_VOID XGLAPI intelCmdClearColorImageRaw(
423 XGL_CMD_BUFFER cmdBuffer,
424 XGL_IMAGE image,
425 const XGL_UINT32 color[4],
426 XGL_UINT rangeCount,
427 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
428{
429}
430
431XGL_VOID XGLAPI intelCmdClearDepthStencil(
432 XGL_CMD_BUFFER cmdBuffer,
433 XGL_IMAGE image,
434 XGL_FLOAT depth,
435 XGL_UINT32 stencil,
436 XGL_UINT rangeCount,
437 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
438{
439}
440
441XGL_VOID XGLAPI intelCmdResolveImage(
442 XGL_CMD_BUFFER cmdBuffer,
443 XGL_IMAGE srcImage,
444 XGL_IMAGE destImage,
445 XGL_UINT rectCount,
446 const XGL_IMAGE_RESOLVE* pRects)
447{
448}
449
Chia-I Wu09142132014-08-11 15:42:55 +0800450XGL_VOID XGLAPI intelCmdMemoryAtomic(
451 XGL_CMD_BUFFER cmdBuffer,
452 XGL_GPU_MEMORY destMem,
453 XGL_GPU_SIZE destOffset,
454 XGL_UINT64 srcData,
455 XGL_ATOMIC_OP atomicOp)
456{
457}
458
Chia-I Wu09142132014-08-11 15:42:55 +0800459XGL_VOID XGLAPI intelCmdInitAtomicCounters(
460 XGL_CMD_BUFFER cmdBuffer,
461 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
462 XGL_UINT startCounter,
463 XGL_UINT counterCount,
464 const XGL_UINT32* pData)
465{
466}
467
468XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
469 XGL_CMD_BUFFER cmdBuffer,
470 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
471 XGL_UINT startCounter,
472 XGL_UINT counterCount,
473 XGL_GPU_MEMORY srcMem,
474 XGL_GPU_SIZE srcOffset)
475{
476}
477
478XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
479 XGL_CMD_BUFFER cmdBuffer,
480 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
481 XGL_UINT startCounter,
482 XGL_UINT counterCount,
483 XGL_GPU_MEMORY destMem,
484 XGL_GPU_SIZE destOffset)
485{
486}
487
488XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
489 XGL_CMD_BUFFER cmdBuffer,
490 const XGL_CHAR* pMarker)
491{
492}
493
494XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
495 XGL_CMD_BUFFER cmdBuffer)
496{
497}