blob: eb502e7e52be86c65968f5c1b15357234244b7bd [file] [log] [blame]
Chia-I Wu82f50aa2014-08-05 10:43:03 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
Chia-I Wu82f50aa2014-08-05 10:43:03 +080026 */
27
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -060028#include "dev.h"
Chia-I Wu9e61c0d2014-09-15 15:12:06 +080029#include "gpu.h"
30#include "mem.h"
Chia-I Wu82f50aa2014-08-05 10:43:03 +080031#include "obj.h"
32
Chia-I Wu4c120782015-01-18 11:32:18 +080033static const uint32_t intel_base_magic = 0x494e544c;
Chia-I Wu778a80c2015-01-03 22:45:10 +080034
Chia-I Wu82f50aa2014-08-05 10:43:03 +080035/**
36 * Return true if an (not so) arbitrary pointer casted to intel_base points to
Chia-I Wu778a80c2015-01-03 22:45:10 +080037 * a valid intel_base. This assumes at least the first
38 * sizeof(void*)+sizeof(uint32_t) bytes of the address are accessible, and
39 * they does not happen to be our magic values.
Chia-I Wu82f50aa2014-08-05 10:43:03 +080040 */
Chia-I Wu778a80c2015-01-03 22:45:10 +080041bool intel_base_is_valid(const struct intel_base *base,
42 XGL_DBG_OBJECT_TYPE type)
Chia-I Wu82f50aa2014-08-05 10:43:03 +080043{
Chia-I Wu778a80c2015-01-03 22:45:10 +080044 return (base->magic == intel_base_magic + type);
Chia-I Wu82f50aa2014-08-05 10:43:03 +080045}
46
Chia-I Wu26f0bd02014-08-07 10:38:40 +080047XGL_RESULT intel_base_get_info(struct intel_base *base, int type,
48 XGL_SIZE *size, XGL_VOID *data)
49{
50 XGL_RESULT ret = XGL_SUCCESS;
51 XGL_SIZE s;
Jon Ashburna9ae3832015-01-16 09:37:43 -070052 XGL_UINT *count;
Chia-I Wu26f0bd02014-08-07 10:38:40 +080053
54 switch (type) {
55 case XGL_INFO_TYPE_MEMORY_REQUIREMENTS:
56 s = sizeof(XGL_MEMORY_REQUIREMENTS);
Chia-I Wu26f0bd02014-08-07 10:38:40 +080057 *size = s;
Jon Ashburn408daec2014-12-05 09:23:52 -070058 if (data == NULL)
59 return ret;
60 memset(data, 0, s);
61
Chia-I Wu26f0bd02014-08-07 10:38:40 +080062 break;
Jon Ashburna9ae3832015-01-16 09:37:43 -070063 case XGL_INFO_TYPE_MEMORY_ALLOCATION_COUNT:
64 *size = sizeof(XGL_UINT);
65 if (data == NULL)
66 return ret;
67 count = (XGL_UINT *) data;
68 *count = 1;
69 break;
Chia-I Wu26f0bd02014-08-07 10:38:40 +080070 default:
71 ret = XGL_ERROR_INVALID_VALUE;
72 break;
73 }
74
75 return ret;
76}
77
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080078static bool base_dbg_copy_create_info(struct intel_base_dbg *dbg,
79 const void *create_info)
80{
81 const union {
82 const void *ptr;
83 const struct {
84 XGL_STRUCTURE_TYPE struct_type;
85 XGL_VOID *next;
86 } *header;
87 } info = { .ptr = create_info };
88 XGL_SIZE shallow_copy = 0;
89
90 if (!create_info)
91 return true;
92
Chia-I Wub1076d72014-08-18 16:10:20 +080093 switch (dbg->type) {
94 case XGL_DBG_OBJECT_DEVICE:
95 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DEVICE_CREATE_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080096 break;
Chia-I Wub1076d72014-08-18 16:10:20 +080097 case XGL_DBG_OBJECT_GPU_MEMORY:
98 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_MEMORY_ALLOC_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +080099 shallow_copy = sizeof(XGL_MEMORY_ALLOC_INFO);
100 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800101 case XGL_DBG_OBJECT_EVENT:
102 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_EVENT_CREATE_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800103 shallow_copy = sizeof(XGL_EVENT_CREATE_INFO);
104 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800105 case XGL_DBG_OBJECT_FENCE:
106 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_FENCE_CREATE_INFO);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800107 shallow_copy = sizeof(XGL_FENCE_CREATE_INFO);
108 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800109 case XGL_DBG_OBJECT_QUERY_POOL:
110 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_QUERY_POOL_CREATE_INFO);
Courtney Goeltzenleuchter850d12c2014-08-07 18:13:10 -0600111 shallow_copy = sizeof(XGL_QUERY_POOL_CREATE_INFO);
112 break;
Chia-I Wu714df452015-01-01 07:55:04 +0800113 case XGL_DBG_OBJECT_BUFFER:
114 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
115 shallow_copy = sizeof(XGL_BUFFER_CREATE_INFO);
116 break;
117 case XGL_DBG_OBJECT_BUFFER_VIEW:
118 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_BUFFER_VIEW_CREATE_INFO);
119 shallow_copy = sizeof(XGL_BUFFER_VIEW_CREATE_INFO);
120 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800121 case XGL_DBG_OBJECT_IMAGE:
122 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
Chia-I Wufeb441f2014-08-08 21:27:38 +0800123 shallow_copy = sizeof(XGL_IMAGE_CREATE_INFO);
124 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800125 case XGL_DBG_OBJECT_IMAGE_VIEW:
126 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO);
Chia-I Wu5a323262014-08-11 10:31:53 +0800127 shallow_copy = sizeof(XGL_IMAGE_VIEW_CREATE_INFO);
128 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800129 case XGL_DBG_OBJECT_COLOR_TARGET_VIEW:
130 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_COLOR_ATTACHMENT_VIEW_CREATE_INFO);
Chia-I Wu5a323262014-08-11 10:31:53 +0800131 shallow_copy = sizeof(XGL_COLOR_ATTACHMENT_VIEW_CREATE_INFO);
132 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800133 case XGL_DBG_OBJECT_DEPTH_STENCIL_VIEW:
134 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DEPTH_STENCIL_VIEW_CREATE_INFO);
Chia-I Wu5a323262014-08-11 10:31:53 +0800135 shallow_copy = sizeof(XGL_DEPTH_STENCIL_VIEW_CREATE_INFO);
136 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800137 case XGL_DBG_OBJECT_SAMPLER:
138 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
Chia-I Wu28b89962014-08-18 14:40:49 +0800139 shallow_copy = sizeof(XGL_SAMPLER_CREATE_INFO);
140 break;
Chia-I Wub1076d72014-08-18 16:10:20 +0800141 case XGL_DBG_OBJECT_DESCRIPTOR_SET:
Chia-I Wuf8385062015-01-04 16:27:24 +0800142 /* no create info */
Chia-I Wub8d04c82014-08-18 15:51:10 +0800143 break;
Chia-I Wua5714e82014-08-11 15:33:42 +0800144 case XGL_DBG_OBJECT_VIEWPORT_STATE:
Tony Barbourfa6cac72015-01-16 14:27:35 -0700145 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DYNAMIC_VP_STATE_CREATE_INFO);
146 shallow_copy = sizeof(XGL_DYNAMIC_VP_STATE_CREATE_INFO);
Chia-I Wua5714e82014-08-11 15:33:42 +0800147 break;
148 case XGL_DBG_OBJECT_RASTER_STATE:
Tony Barbourfa6cac72015-01-16 14:27:35 -0700149 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DYNAMIC_RS_STATE_CREATE_INFO);
150 shallow_copy = sizeof(XGL_DYNAMIC_RS_STATE_CREATE_INFO);
Chia-I Wua5714e82014-08-11 15:33:42 +0800151 break;
152 case XGL_DBG_OBJECT_COLOR_BLEND_STATE:
Tony Barbourfa6cac72015-01-16 14:27:35 -0700153 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DYNAMIC_CB_STATE_CREATE_INFO);
154 shallow_copy = sizeof(XGL_DYNAMIC_CB_STATE_CREATE_INFO);
Chia-I Wua5714e82014-08-11 15:33:42 +0800155 break;
156 case XGL_DBG_OBJECT_DEPTH_STENCIL_STATE:
Tony Barbourfa6cac72015-01-16 14:27:35 -0700157 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DYNAMIC_DS_STATE_CREATE_INFO);
158 shallow_copy = sizeof(XGL_DYNAMIC_DS_STATE_CREATE_INFO);
Chia-I Wua5714e82014-08-11 15:33:42 +0800159 break;
Chia-I Wu730e5362014-08-19 12:15:09 +0800160 case XGL_DBG_OBJECT_CMD_BUFFER:
161 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_CMD_BUFFER_CREATE_INFO);
162 shallow_copy = sizeof(XGL_CMD_BUFFER_CREATE_INFO);
163 break;
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600164 case XGL_DBG_OBJECT_GRAPHICS_PIPELINE:
165 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO);
166 break;
Courtney Goeltzenleuchter52ec3362014-08-19 11:52:02 -0600167 case XGL_DBG_OBJECT_SHADER:
Courtney Goeltzenleuchteref5b1162014-10-10 16:29:46 -0600168 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_SHADER_CREATE_INFO);
Courtney Goeltzenleuchter52ec3362014-08-19 11:52:02 -0600169 shallow_copy = sizeof(XGL_SHADER_CREATE_INFO);
170 break;
Jon Ashburnc6f4a412014-12-24 12:38:36 -0700171 case XGL_DBG_OBJECT_FRAMEBUFFER:
172 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
173 shallow_copy = sizeof(XGL_FRAMEBUFFER_CREATE_INFO);
174 break;
175 case XGL_DBG_OBJECT_RENDER_PASS:
176 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO);
177 shallow_copy = sizeof(XGL_RENDER_PASS_CREATE_INFO);
178 break;
Chia-I Wuf8385062015-01-04 16:27:24 +0800179 case XGL_DBG_OBJECT_DESCRIPTOR_SET_LAYOUT:
180 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO);
181 /* TODO */
182 shallow_copy = sizeof(XGL_DESCRIPTOR_SET_LAYOUT_CREATE_INFO) * 0;
183 break;
184 case XGL_DBG_OBJECT_DESCRIPTOR_REGION:
185 assert(info.header->struct_type == XGL_STRUCTURE_TYPE_DESCRIPTOR_REGION_CREATE_INFO);
186 shallow_copy = sizeof(XGL_DESCRIPTOR_REGION_CREATE_INFO);
187 break;
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800188 default:
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600189 // log debug message regarding invalid struct_type?
190 intel_dev_log(dbg->dev, XGL_DBG_MSG_ERROR,
191 XGL_VALIDATION_LEVEL_0, XGL_NULL_HANDLE, 0, 0,
192 "Invalid Create Info type: 0x%x", info.header->struct_type);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800193 return false;
194 break;
195 }
196
197 if (shallow_copy) {
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800198 dbg->create_info = icd_alloc(shallow_copy, 0, XGL_SYSTEM_ALLOC_DEBUG);
199 if (!dbg->create_info)
200 return false;
201
202 memcpy(dbg->create_info, create_info, shallow_copy);
Chia-I Wue2934f92014-08-16 13:17:22 +0800203 dbg->create_info_size = shallow_copy;
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800204 } else if (info.header->struct_type ==
205 XGL_STRUCTURE_TYPE_DEVICE_CREATE_INFO) {
206 const XGL_DEVICE_CREATE_INFO *src = info.ptr;
207 XGL_DEVICE_CREATE_INFO *dst;
208 uint8_t *d;
209 XGL_SIZE size;
210 XGL_UINT i;
211
212 size = sizeof(*src);
Chia-I Wue2934f92014-08-16 13:17:22 +0800213 dbg->create_info_size = size;
214
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800215 size += sizeof(src->pRequestedQueues[0]) * src->queueRecordCount;
216 size += sizeof(src->ppEnabledExtensionNames[0]) * src->extensionCount;
217 for (i = 0; i < src->extensionCount; i++) {
Chia-I Wu7461fcf2014-12-27 15:16:07 +0800218 size += 1 + strlen(src->ppEnabledExtensionNames[i]);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800219 }
220
Chia-I Wu98dcfab2014-08-07 12:07:52 +0800221 dst = icd_alloc(size, 0, XGL_SYSTEM_ALLOC_DEBUG);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800222 if (!dst)
223 return false;
224
225 memcpy(dst, src, sizeof(*src));
226
227 d = (uint8_t *) dst;
228 d += sizeof(*src);
229
230 size = sizeof(src->pRequestedQueues[0]) * src->queueRecordCount;
231 memcpy(d, src->pRequestedQueues, size);
232 dst->pRequestedQueues = (const XGL_DEVICE_QUEUE_CREATE_INFO *) d;
233 d += size;
234
235 size = sizeof(src->ppEnabledExtensionNames[0]) * src->extensionCount;
236 dst->ppEnabledExtensionNames = (const XGL_CHAR * const *) d;
237
238 for (i = 0; i < src->extensionCount; i++) {
Chia-I Wu7461fcf2014-12-27 15:16:07 +0800239 const XGL_SIZE len = strlen(src->ppEnabledExtensionNames[i]);
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800240
241 memcpy(d + size, src->ppEnabledExtensionNames[i], len + 1);
242 ((const XGL_CHAR **) d)[i] = (const XGL_CHAR *) (d + size);
243
244 size += len + 1;
245 }
Courtney Goeltzenleuchter191b06c2014-10-17 16:21:35 -0600246 dbg->create_info = dst;
Courtney Goeltzenleuchter05a60542014-08-15 14:54:34 -0600247 } else if (info.header->struct_type == XGL_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO) {
248 // TODO: What do we want to copy here?
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800249 }
250
251 return true;
252}
253
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800254/**
Chia-I Wubbf2c932014-08-07 12:20:08 +0800255 * Create an intel_base_dbg. When dbg_size is non-zero, a buffer of that
Chia-I Wu660caf82014-08-07 10:54:26 +0800256 * size is allocated and zeroed.
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800257 */
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600258struct intel_base_dbg *intel_base_dbg_create(struct intel_dev *dev,
259 XGL_DBG_OBJECT_TYPE type,
Chia-I Wu660caf82014-08-07 10:54:26 +0800260 const void *create_info,
Chia-I Wubbf2c932014-08-07 12:20:08 +0800261 XGL_SIZE dbg_size)
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800262{
Chia-I Wu660caf82014-08-07 10:54:26 +0800263 struct intel_base_dbg *dbg;
264
Chia-I Wubbf2c932014-08-07 12:20:08 +0800265 if (!dbg_size)
266 dbg_size = sizeof(*dbg);
Chia-I Wu660caf82014-08-07 10:54:26 +0800267
Chia-I Wubbf2c932014-08-07 12:20:08 +0800268 assert(dbg_size >= sizeof(*dbg));
Chia-I Wu660caf82014-08-07 10:54:26 +0800269
Chia-I Wubbf2c932014-08-07 12:20:08 +0800270 dbg = icd_alloc(dbg_size, 0, XGL_SYSTEM_ALLOC_DEBUG);
Chia-I Wu660caf82014-08-07 10:54:26 +0800271 if (!dbg)
272 return NULL;
273
Chia-I Wubbf2c932014-08-07 12:20:08 +0800274 memset(dbg, 0, dbg_size);
Chia-I Wu660caf82014-08-07 10:54:26 +0800275
Chia-I Wu900364b2015-01-03 13:55:22 +0800276 dbg->alloc_id = icd_allocator_get_id();
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800277 dbg->type = type;
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600278 dbg->dev = dev;
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800279
Chia-I Wu1f8fc7c2014-08-07 11:09:11 +0800280 if (!base_dbg_copy_create_info(dbg, create_info)) {
281 icd_free(dbg);
282 return NULL;
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800283 }
284
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800285 return dbg;
286}
287
288void intel_base_dbg_destroy(struct intel_base_dbg *dbg)
289{
Chia-I Wu660caf82014-08-07 10:54:26 +0800290 if (dbg->tag)
291 icd_free(dbg->tag);
292
293 if (dbg->create_info)
294 icd_free(dbg->create_info);
295
Chia-I Wu82f50aa2014-08-05 10:43:03 +0800296 icd_free(dbg);
297}
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800298
Chia-I Wubbf2c932014-08-07 12:20:08 +0800299/**
300 * Create an intel_base. obj_size and dbg_size specify the real sizes of the
301 * object and the debug metadata. Memories are zeroed.
302 */
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600303struct intel_base *intel_base_create(struct intel_dev *dev,
304 XGL_SIZE obj_size, bool debug,
Chia-I Wubbf2c932014-08-07 12:20:08 +0800305 XGL_DBG_OBJECT_TYPE type,
306 const void *create_info,
307 XGL_SIZE dbg_size)
308{
309 struct intel_base *base;
310
311 if (!obj_size)
312 obj_size = sizeof(*base);
313
314 assert(obj_size >= sizeof(*base));
315
316 base = icd_alloc(obj_size, 0, XGL_SYSTEM_ALLOC_API_OBJECT);
317 if (!base)
318 return NULL;
319
Chia-I Wu778a80c2015-01-03 22:45:10 +0800320 memset(base, 0, obj_size);
321 base->magic = intel_base_magic + type;
322
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600323 if (dev == NULL) {
324 /*
325 * dev is NULL when we are creating the base device object
326 * Set dev now so that debug setup happens correctly
327 */
328 dev = (struct intel_dev *) base;
329 }
330
Chia-I Wubbf2c932014-08-07 12:20:08 +0800331 if (debug) {
Courtney Goeltzenleuchterfb4fb532014-08-14 09:35:21 -0600332 base->dbg = intel_base_dbg_create(dev, type, create_info, dbg_size);
Chia-I Wubbf2c932014-08-07 12:20:08 +0800333 if (!base->dbg) {
334 icd_free(base);
335 return NULL;
336 }
337 }
Chia-I Wu6a42c2a2014-08-19 14:36:47 +0800338
Chia-I Wubbf2c932014-08-07 12:20:08 +0800339 base->get_info = intel_base_get_info;
340
341 return base;
342}
343
344void intel_base_destroy(struct intel_base *base)
345{
346 if (base->dbg)
347 intel_base_dbg_destroy(base->dbg);
348 icd_free(base);
349}
350
Chia-I Wu96177272015-01-03 15:27:41 +0800351ICD_EXPORT XGL_RESULT XGLAPI xglDestroyObject(
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800352 XGL_OBJECT object)
353{
354 struct intel_obj *obj = intel_obj(object);
355
356 obj->destroy(obj);
357
358 return XGL_SUCCESS;
359}
360
Chia-I Wu96177272015-01-03 15:27:41 +0800361ICD_EXPORT XGL_RESULT XGLAPI xglGetObjectInfo(
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800362 XGL_BASE_OBJECT object,
363 XGL_OBJECT_INFO_TYPE infoType,
364 XGL_SIZE* pDataSize,
365 XGL_VOID* pData)
366{
367 struct intel_base *base = intel_base(object);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800368
Chia-I Wu26f0bd02014-08-07 10:38:40 +0800369 return base->get_info(base, infoType, pDataSize, pData);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800370}
371
Chia-I Wu96177272015-01-03 15:27:41 +0800372ICD_EXPORT XGL_RESULT XGLAPI xglBindObjectMemory(
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800373 XGL_OBJECT object,
Jon Ashburned62b412015-01-15 10:39:19 -0700374 XGL_UINT allocationIdx,
Chia-I Wu9e61c0d2014-09-15 15:12:06 +0800375 XGL_GPU_MEMORY mem_,
Chia-I Wu714df452015-01-01 07:55:04 +0800376 XGL_GPU_SIZE memOffset)
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800377{
378 struct intel_obj *obj = intel_obj(object);
Chia-I Wu9e61c0d2014-09-15 15:12:06 +0800379 struct intel_mem *mem = intel_mem(mem_);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800380
Chia-I Wu714df452015-01-01 07:55:04 +0800381 intel_obj_bind_mem(obj, mem, memOffset);
Chia-I Wu53fc6aa2014-08-06 14:22:51 +0800382
383 return XGL_SUCCESS;
384}
Chia-I Wu7ec9f342014-08-19 10:47:53 +0800385
Chia-I Wu714df452015-01-01 07:55:04 +0800386ICD_EXPORT XGL_RESULT XGLAPI xglBindObjectMemoryRange(
387 XGL_OBJECT object,
Jon Ashburned62b412015-01-15 10:39:19 -0700388 XGL_UINT allocationIdx,
Chia-I Wu714df452015-01-01 07:55:04 +0800389 XGL_GPU_SIZE rangeOffset,
390 XGL_GPU_SIZE rangeSize,
391 XGL_GPU_MEMORY mem,
392 XGL_GPU_SIZE memOffset)
393{
394 return XGL_ERROR_UNKNOWN;
395}
396
397ICD_EXPORT XGL_RESULT XGLAPI xglBindImageMemoryRange(
398 XGL_IMAGE image,
Jon Ashburned62b412015-01-15 10:39:19 -0700399 XGL_UINT allocationIdx,
Chia-I Wu714df452015-01-01 07:55:04 +0800400 const XGL_IMAGE_MEMORY_BIND_INFO* bindInfo,
401 XGL_GPU_MEMORY mem,
402 XGL_GPU_SIZE memOffset)
403{
404 return XGL_ERROR_UNKNOWN;
405}
406
Chia-I Wu96177272015-01-03 15:27:41 +0800407ICD_EXPORT XGL_RESULT XGLAPI xglDbgSetObjectTag(
Chia-I Wu7ec9f342014-08-19 10:47:53 +0800408 XGL_BASE_OBJECT object,
409 XGL_SIZE tagSize,
410 const XGL_VOID* pTag)
411{
412 struct intel_base *base = intel_base(object);
413 struct intel_base_dbg *dbg = base->dbg;
414 void *tag;
415
416 if (!dbg)
417 return XGL_SUCCESS;
418
419 tag = icd_alloc(tagSize, 0, XGL_SYSTEM_ALLOC_DEBUG);
420 if (!tag)
421 return XGL_ERROR_OUT_OF_MEMORY;
422
423 memcpy(tag, pTag, tagSize);
424
425 if (dbg->tag)
426 icd_free(dbg->tag);
427
428 dbg->tag = tag;
429 dbg->tag_size = tagSize;
430
431 return XGL_SUCCESS;
432}