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Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef CMD_H
26#define CMD_H
27
28#include "intel.h"
29#include "obj.h"
Chia-I Wub2755562014-08-20 13:38:52 +080030#include "view.h"
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -060031#include "shader.h"
Chia-I Wub2755562014-08-20 13:38:52 +080032
33struct intel_pipeline;
34struct intel_pipeline_delta;
35struct intel_viewport_state;
36struct intel_raster_state;
37struct intel_msaa_state;
38struct intel_blend_state;
39struct intel_ds_state;
40struct intel_dset;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -060041struct intel_pipe_shader;
Chia-I Wub2755562014-08-20 13:38:52 +080042
Chia-I Wu958d1b72014-08-21 11:28:11 +080043struct intel_cmd_reloc;
44
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -060045struct intel_cmd_shader {
46 struct intel_pipe_shader *shader;
47 XGL_UINT kernel_pos;
48};
49
Chia-I Wub2755562014-08-20 13:38:52 +080050/*
51 * States bounded to the command buffer. We want to write states directly to
52 * the command buffer when possible, and reduce this struct.
53 */
54struct intel_cmd_bind {
55 struct {
56 const struct intel_pipeline *graphics;
57 const struct intel_pipeline *compute;
58 const struct intel_pipeline_delta *graphics_delta;
59 const struct intel_pipeline_delta *compute_delta;
60 } pipeline;
61
62 struct {
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -060063 uint32_t size;
64 uint32_t used;
65 struct intel_cmd_shader *shaderList;
66 } shaderCache;
67
68 struct {
Chia-I Wub2755562014-08-20 13:38:52 +080069 const struct intel_viewport_state *viewport;
70 const struct intel_raster_state *raster;
71 const struct intel_msaa_state *msaa;
72 const struct intel_blend_state *blend;
73 const struct intel_ds_state *ds;
74 } state;
75
76 struct {
77 const struct intel_dset *graphics;
78 XGL_UINT graphics_offset;
79 const struct intel_dset *compute;
80 XGL_UINT compute_offset;
81 } dset;
82
83 struct {
84 struct intel_mem_view graphics;
85 struct intel_mem_view compute;
Chia-I Wu9f1722c2014-08-25 10:17:58 +080086 } dyn_view;
Chia-I Wub2755562014-08-20 13:38:52 +080087
88 struct {
89 const struct intel_mem *mem;
90 XGL_GPU_SIZE offset;
91 XGL_INDEX_TYPE type;
92 } index;
93
94 struct {
95 const struct intel_rt_view *rt[XGL_MAX_COLOR_ATTACHMENTS];
96 XGL_UINT rt_count;
97
98 const struct intel_ds_view *ds;
99 } att;
Chia-I Wu48c283d2014-08-25 23:13:46 +0800100
Chia-I Wu707a29e2014-08-27 12:51:47 +0800101 XGL_UINT draw_count;
Chia-I Wu48c283d2014-08-25 23:13:46 +0800102 uint32_t wa_flags;
Chia-I Wub2755562014-08-20 13:38:52 +0800103};
Chia-I Wu09142132014-08-11 15:42:55 +0800104
Chia-I Wue24c3292014-08-21 14:05:23 +0800105struct intel_cmd_writer {
106 struct intel_bo *bo;
107 void *ptr_opaque;
108
109 /* in DWords */
110 XGL_UINT size;
111 XGL_UINT used;
112};
113
Chia-I Wu730e5362014-08-19 12:15:09 +0800114struct intel_cmd {
115 struct intel_obj obj;
116
117 struct intel_dev *dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800118 struct intel_bo *scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800119 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800120
Chia-I Wu343b1372014-08-20 16:39:20 +0800121 struct intel_cmd_reloc *relocs;
122 XGL_UINT reloc_count;
123
Chia-I Wu730e5362014-08-19 12:15:09 +0800124 XGL_FLAGS flags;
125
Chia-I Wue24c3292014-08-21 14:05:23 +0800126 struct intel_cmd_writer batch;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800127 struct intel_cmd_writer state;
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800128 struct intel_cmd_writer kernel;
Chia-I Wu730e5362014-08-19 12:15:09 +0800129
Chia-I Wu343b1372014-08-20 16:39:20 +0800130 XGL_UINT reloc_used;
Chia-I Wu04966702014-08-20 15:05:03 +0800131 XGL_RESULT result;
Chia-I Wub2755562014-08-20 13:38:52 +0800132
133 struct intel_cmd_bind bind;
Chia-I Wu730e5362014-08-19 12:15:09 +0800134};
135
136static inline struct intel_cmd *intel_cmd(XGL_CMD_BUFFER cmd)
137{
138 return (struct intel_cmd *) cmd;
139}
140
141static inline struct intel_cmd *intel_cmd_from_obj(struct intel_obj *obj)
142{
143 return (struct intel_cmd *) obj;
144}
145
146XGL_RESULT intel_cmd_create(struct intel_dev *dev,
147 const XGL_CMD_BUFFER_CREATE_INFO *info,
148 struct intel_cmd **cmd_ret);
149void intel_cmd_destroy(struct intel_cmd *cmd);
150
151XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags);
152XGL_RESULT intel_cmd_end(struct intel_cmd *cmd);
153
Chia-I Wue24c3292014-08-21 14:05:23 +0800154static inline struct intel_bo *intel_cmd_get_batch(const struct intel_cmd *cmd,
155 XGL_GPU_SIZE *used)
156{
157 const struct intel_cmd_writer *writer = &cmd->batch;
158
159 if (used)
160 *used = sizeof(uint32_t) * writer->used;
161
162 return writer->bo;
163}
164
Chia-I Wu09142132014-08-11 15:42:55 +0800165XGL_RESULT XGLAPI intelCreateCommandBuffer(
166 XGL_DEVICE device,
167 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
168 XGL_CMD_BUFFER* pCmdBuffer);
169
170XGL_RESULT XGLAPI intelBeginCommandBuffer(
171 XGL_CMD_BUFFER cmdBuffer,
172 XGL_FLAGS flags);
173
174XGL_RESULT XGLAPI intelEndCommandBuffer(
175 XGL_CMD_BUFFER cmdBuffer);
176
177XGL_RESULT XGLAPI intelResetCommandBuffer(
178 XGL_CMD_BUFFER cmdBuffer);
179
180XGL_VOID XGLAPI intelCmdBindPipeline(
181 XGL_CMD_BUFFER cmdBuffer,
182 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
183 XGL_PIPELINE pipeline);
184
185XGL_VOID XGLAPI intelCmdBindPipelineDelta(
186 XGL_CMD_BUFFER cmdBuffer,
187 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
188 XGL_PIPELINE_DELTA delta);
189
190XGL_VOID XGLAPI intelCmdBindStateObject(
191 XGL_CMD_BUFFER cmdBuffer,
192 XGL_STATE_BIND_POINT stateBindPoint,
193 XGL_STATE_OBJECT state);
194
195XGL_VOID XGLAPI intelCmdBindDescriptorSet(
196 XGL_CMD_BUFFER cmdBuffer,
197 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
198 XGL_UINT index,
199 XGL_DESCRIPTOR_SET descriptorSet,
200 XGL_UINT slotOffset);
201
202XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
203 XGL_CMD_BUFFER cmdBuffer,
204 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
205 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView);
206
207XGL_VOID XGLAPI intelCmdBindIndexData(
208 XGL_CMD_BUFFER cmdBuffer,
209 XGL_GPU_MEMORY mem,
210 XGL_GPU_SIZE offset,
211 XGL_INDEX_TYPE indexType);
212
213XGL_VOID XGLAPI intelCmdBindAttachments(
214 XGL_CMD_BUFFER cmdBuffer,
215 XGL_UINT colorAttachmentCount,
216 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
217 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment);
218
219XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
220 XGL_CMD_BUFFER cmdBuffer,
221 XGL_UINT transitionCount,
222 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions);
223
224XGL_VOID XGLAPI intelCmdPrepareImages(
225 XGL_CMD_BUFFER cmdBuffer,
226 XGL_UINT transitionCount,
227 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions);
228
229XGL_VOID XGLAPI intelCmdDraw(
230 XGL_CMD_BUFFER cmdBuffer,
231 XGL_UINT firstVertex,
232 XGL_UINT vertexCount,
233 XGL_UINT firstInstance,
234 XGL_UINT instanceCount);
235
236XGL_VOID XGLAPI intelCmdDrawIndexed(
237 XGL_CMD_BUFFER cmdBuffer,
238 XGL_UINT firstIndex,
239 XGL_UINT indexCount,
240 XGL_INT vertexOffset,
241 XGL_UINT firstInstance,
242 XGL_UINT instanceCount);
243
244XGL_VOID XGLAPI intelCmdDrawIndirect(
245 XGL_CMD_BUFFER cmdBuffer,
246 XGL_GPU_MEMORY mem,
247 XGL_GPU_SIZE offset,
248 XGL_UINT32 count,
249 XGL_UINT32 stride);
250
251XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
252 XGL_CMD_BUFFER cmdBuffer,
253 XGL_GPU_MEMORY mem,
254 XGL_GPU_SIZE offset,
255 XGL_UINT32 count,
256 XGL_UINT32 stride);
257
258XGL_VOID XGLAPI intelCmdDispatch(
259 XGL_CMD_BUFFER cmdBuffer,
260 XGL_UINT x,
261 XGL_UINT y,
262 XGL_UINT z);
263
264XGL_VOID XGLAPI intelCmdDispatchIndirect(
265 XGL_CMD_BUFFER cmdBuffer,
266 XGL_GPU_MEMORY mem,
267 XGL_GPU_SIZE offset);
268
269XGL_VOID XGLAPI intelCmdCopyMemory(
270 XGL_CMD_BUFFER cmdBuffer,
271 XGL_GPU_MEMORY srcMem,
272 XGL_GPU_MEMORY destMem,
273 XGL_UINT regionCount,
274 const XGL_MEMORY_COPY* pRegions);
275
276XGL_VOID XGLAPI intelCmdCopyImage(
277 XGL_CMD_BUFFER cmdBuffer,
278 XGL_IMAGE srcImage,
279 XGL_IMAGE destImage,
280 XGL_UINT regionCount,
281 const XGL_IMAGE_COPY* pRegions);
282
283XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
284 XGL_CMD_BUFFER cmdBuffer,
285 XGL_GPU_MEMORY srcMem,
286 XGL_IMAGE destImage,
287 XGL_UINT regionCount,
288 const XGL_MEMORY_IMAGE_COPY* pRegions);
289
290XGL_VOID XGLAPI intelCmdCopyImageToMemory(
291 XGL_CMD_BUFFER cmdBuffer,
292 XGL_IMAGE srcImage,
293 XGL_GPU_MEMORY destMem,
294 XGL_UINT regionCount,
295 const XGL_MEMORY_IMAGE_COPY* pRegions);
296
297XGL_VOID XGLAPI intelCmdCloneImageData(
298 XGL_CMD_BUFFER cmdBuffer,
299 XGL_IMAGE srcImage,
300 XGL_IMAGE_STATE srcImageState,
301 XGL_IMAGE destImage,
302 XGL_IMAGE_STATE destImageState);
303
304XGL_VOID XGLAPI intelCmdUpdateMemory(
305 XGL_CMD_BUFFER cmdBuffer,
306 XGL_GPU_MEMORY destMem,
307 XGL_GPU_SIZE destOffset,
308 XGL_GPU_SIZE dataSize,
309 const XGL_UINT32* pData);
310
311XGL_VOID XGLAPI intelCmdFillMemory(
312 XGL_CMD_BUFFER cmdBuffer,
313 XGL_GPU_MEMORY destMem,
314 XGL_GPU_SIZE destOffset,
315 XGL_GPU_SIZE fillSize,
316 XGL_UINT32 data);
317
318XGL_VOID XGLAPI intelCmdClearColorImage(
319 XGL_CMD_BUFFER cmdBuffer,
320 XGL_IMAGE image,
321 const XGL_FLOAT color[4],
322 XGL_UINT rangeCount,
323 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
324
325XGL_VOID XGLAPI intelCmdClearColorImageRaw(
326 XGL_CMD_BUFFER cmdBuffer,
327 XGL_IMAGE image,
328 const XGL_UINT32 color[4],
329 XGL_UINT rangeCount,
330 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
331
332XGL_VOID XGLAPI intelCmdClearDepthStencil(
333 XGL_CMD_BUFFER cmdBuffer,
334 XGL_IMAGE image,
335 XGL_FLOAT depth,
336 XGL_UINT32 stencil,
337 XGL_UINT rangeCount,
338 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
339
340XGL_VOID XGLAPI intelCmdResolveImage(
341 XGL_CMD_BUFFER cmdBuffer,
342 XGL_IMAGE srcImage,
343 XGL_IMAGE destImage,
344 XGL_UINT rectCount,
345 const XGL_IMAGE_RESOLVE* pRects);
346
347XGL_VOID XGLAPI intelCmdSetEvent(
348 XGL_CMD_BUFFER cmdBuffer,
349 XGL_EVENT event);
350
351XGL_VOID XGLAPI intelCmdResetEvent(
352 XGL_CMD_BUFFER cmdBuffer,
353 XGL_EVENT event);
354
355XGL_VOID XGLAPI intelCmdMemoryAtomic(
356 XGL_CMD_BUFFER cmdBuffer,
357 XGL_GPU_MEMORY destMem,
358 XGL_GPU_SIZE destOffset,
359 XGL_UINT64 srcData,
360 XGL_ATOMIC_OP atomicOp);
361
362XGL_VOID XGLAPI intelCmdBeginQuery(
363 XGL_CMD_BUFFER cmdBuffer,
364 XGL_QUERY_POOL queryPool,
365 XGL_UINT slot,
366 XGL_FLAGS flags);
367
368XGL_VOID XGLAPI intelCmdEndQuery(
369 XGL_CMD_BUFFER cmdBuffer,
370 XGL_QUERY_POOL queryPool,
371 XGL_UINT slot);
372
373XGL_VOID XGLAPI intelCmdResetQueryPool(
374 XGL_CMD_BUFFER cmdBuffer,
375 XGL_QUERY_POOL queryPool,
376 XGL_UINT startQuery,
377 XGL_UINT queryCount);
378
379XGL_VOID XGLAPI intelCmdWriteTimestamp(
380 XGL_CMD_BUFFER cmdBuffer,
381 XGL_TIMESTAMP_TYPE timestampType,
382 XGL_GPU_MEMORY destMem,
383 XGL_GPU_SIZE destOffset);
384
385XGL_VOID XGLAPI intelCmdInitAtomicCounters(
386 XGL_CMD_BUFFER cmdBuffer,
387 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
388 XGL_UINT startCounter,
389 XGL_UINT counterCount,
390 const XGL_UINT32* pData);
391
392XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
393 XGL_CMD_BUFFER cmdBuffer,
394 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
395 XGL_UINT startCounter,
396 XGL_UINT counterCount,
397 XGL_GPU_MEMORY srcMem,
398 XGL_GPU_SIZE srcOffset);
399
400XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
401 XGL_CMD_BUFFER cmdBuffer,
402 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
403 XGL_UINT startCounter,
404 XGL_UINT counterCount,
405 XGL_GPU_MEMORY destMem,
406 XGL_GPU_SIZE destOffset);
407
408XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
409 XGL_CMD_BUFFER cmdBuffer,
410 const XGL_CHAR* pMarker);
411
412XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
413 XGL_CMD_BUFFER cmdBuffer);
414
415#endif /* CMD_H */