Meng Wang | 43bbb87 | 2018-12-10 12:32:05 +0800 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0-only |
Sudheer Papothi | f415500 | 2019-12-05 01:36:13 +0530 | [diff] [blame] | 2 | /* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3 | */ |
| 4 | |
| 5 | #include <linux/module.h> |
| 6 | #include <linux/init.h> |
| 7 | #include <linux/clk.h> |
| 8 | #include <linux/io.h> |
| 9 | #include <linux/platform_device.h> |
| 10 | #include <linux/regmap.h> |
Sudheer Papothi | 7601cc6 | 2019-03-30 03:00:52 +0530 | [diff] [blame] | 11 | #include <linux/pm_runtime.h> |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 12 | #include <sound/soc.h> |
| 13 | #include <sound/soc-dapm.h> |
| 14 | #include <sound/tlv.h> |
Sudheer Papothi | a3e969d | 2018-10-27 06:22:10 +0530 | [diff] [blame] | 15 | #include <soc/swr-common.h> |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 16 | #include <soc/swr-wcd.h> |
Meng Wang | 11a25cf | 2018-10-31 14:11:26 +0800 | [diff] [blame] | 17 | #include <asoc/msm-cdc-pinctrl.h> |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 18 | #include "bolero-cdc.h" |
| 19 | #include "bolero-cdc-registers.h" |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame] | 20 | #include "bolero-clk-rsc.h" |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 21 | |
Sudheer Papothi | 7601cc6 | 2019-03-30 03:00:52 +0530 | [diff] [blame] | 22 | #define AUTO_SUSPEND_DELAY 50 /* delay in msec */ |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 23 | #define TX_MACRO_MAX_OFFSET 0x1000 |
| 24 | |
| 25 | #define NUM_DECIMATORS 8 |
| 26 | |
| 27 | #define TX_MACRO_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ |
| 28 | SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000 |\ |
| 29 | SNDRV_PCM_RATE_96000 | SNDRV_PCM_RATE_192000) |
| 30 | #define TX_MACRO_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
| 31 | SNDRV_PCM_FMTBIT_S24_LE |\ |
| 32 | SNDRV_PCM_FMTBIT_S24_3LE) |
| 33 | |
| 34 | #define TX_HPF_CUT_OFF_FREQ_MASK 0x60 |
| 35 | #define CF_MIN_3DB_4HZ 0x0 |
| 36 | #define CF_MIN_3DB_75HZ 0x1 |
| 37 | #define CF_MIN_3DB_150HZ 0x2 |
| 38 | |
| 39 | #define TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED 0 |
| 40 | #define TX_MACRO_MCLK_FREQ 9600000 |
| 41 | #define TX_MACRO_TX_PATH_OFFSET 0x80 |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 42 | #define TX_MACRO_SWR_MIC_MUX_SEL_MASK 0xF |
Sudheer Papothi | 339c411 | 2019-12-13 00:49:16 +0530 | [diff] [blame] | 43 | #define TX_MACRO_ADC_MUX_CFG_OFFSET 0x8 |
Karthikeyan Mani | 1dcd5a3 | 2019-08-22 14:37:13 -0700 | [diff] [blame] | 44 | #define TX_MACRO_ADC_MODE_CFG0_SHIFT 1 |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 45 | |
Sudheer Papothi | 339c411 | 2019-12-13 00:49:16 +0530 | [diff] [blame] | 46 | #define TX_MACRO_DMIC_UNMUTE_DELAY_MS 40 |
| 47 | #define TX_MACRO_AMIC_UNMUTE_DELAY_MS 100 |
| 48 | #define TX_MACRO_DMIC_HPF_DELAY_MS 300 |
| 49 | #define TX_MACRO_AMIC_HPF_DELAY_MS 300 |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 50 | |
Sudheer Papothi | 339c411 | 2019-12-13 00:49:16 +0530 | [diff] [blame] | 51 | static int tx_unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 52 | module_param(tx_unmute_delay, int, 0664); |
| 53 | MODULE_PARM_DESC(tx_unmute_delay, "delay to unmute the tx path"); |
| 54 | |
| 55 | static const DECLARE_TLV_DB_SCALE(digital_gain, 0, 1, 0); |
| 56 | |
| 57 | static int tx_macro_hw_params(struct snd_pcm_substream *substream, |
| 58 | struct snd_pcm_hw_params *params, |
| 59 | struct snd_soc_dai *dai); |
| 60 | static int tx_macro_get_channel_map(struct snd_soc_dai *dai, |
| 61 | unsigned int *tx_num, unsigned int *tx_slot, |
| 62 | unsigned int *rx_num, unsigned int *rx_slot); |
| 63 | |
| 64 | #define TX_MACRO_SWR_STRING_LEN 80 |
| 65 | #define TX_MACRO_CHILD_DEVICES_MAX 3 |
| 66 | |
| 67 | /* Hold instance to soundwire platform device */ |
| 68 | struct tx_macro_swr_ctrl_data { |
| 69 | struct platform_device *tx_swr_pdev; |
| 70 | }; |
| 71 | |
| 72 | struct tx_macro_swr_ctrl_platform_data { |
| 73 | void *handle; /* holds codec private data */ |
| 74 | int (*read)(void *handle, int reg); |
| 75 | int (*write)(void *handle, int reg, int val); |
| 76 | int (*bulk_write)(void *handle, u32 *reg, u32 *val, size_t len); |
| 77 | int (*clk)(void *handle, bool enable); |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 78 | int (*core_vote)(void *handle, bool enable); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 79 | int (*handle_irq)(void *handle, |
| 80 | irqreturn_t (*swrm_irq_handler)(int irq, |
| 81 | void *data), |
| 82 | void *swrm_handle, |
| 83 | int action); |
| 84 | }; |
| 85 | |
| 86 | enum { |
Laxminath Kasam | 59c7a1d | 2018-08-09 16:11:17 +0530 | [diff] [blame] | 87 | TX_MACRO_AIF_INVALID = 0, |
| 88 | TX_MACRO_AIF1_CAP, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 89 | TX_MACRO_AIF2_CAP, |
Karthikeyan Mani | f3bb818 | 2019-07-11 14:38:54 -0700 | [diff] [blame] | 90 | TX_MACRO_AIF3_CAP, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 91 | TX_MACRO_MAX_DAIS |
| 92 | }; |
| 93 | |
| 94 | enum { |
| 95 | TX_MACRO_DEC0, |
| 96 | TX_MACRO_DEC1, |
| 97 | TX_MACRO_DEC2, |
| 98 | TX_MACRO_DEC3, |
| 99 | TX_MACRO_DEC4, |
| 100 | TX_MACRO_DEC5, |
| 101 | TX_MACRO_DEC6, |
| 102 | TX_MACRO_DEC7, |
| 103 | TX_MACRO_DEC_MAX, |
| 104 | }; |
| 105 | |
| 106 | enum { |
| 107 | TX_MACRO_CLK_DIV_2, |
| 108 | TX_MACRO_CLK_DIV_3, |
| 109 | TX_MACRO_CLK_DIV_4, |
| 110 | TX_MACRO_CLK_DIV_6, |
| 111 | TX_MACRO_CLK_DIV_8, |
| 112 | TX_MACRO_CLK_DIV_16, |
| 113 | }; |
| 114 | |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 115 | enum { |
| 116 | MSM_DMIC, |
| 117 | SWR_MIC, |
| 118 | ANC_FB_TUNE1 |
| 119 | }; |
| 120 | |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 121 | enum { |
| 122 | TX_MCLK, |
| 123 | VA_MCLK, |
| 124 | }; |
| 125 | |
Sudheer Papothi | 72fef48 | 2019-08-30 11:00:20 +0530 | [diff] [blame] | 126 | struct tx_macro_reg_mask_val { |
| 127 | u16 reg; |
| 128 | u8 mask; |
| 129 | u8 val; |
| 130 | }; |
| 131 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 132 | struct tx_mute_work { |
| 133 | struct tx_macro_priv *tx_priv; |
| 134 | u32 decimator; |
| 135 | struct delayed_work dwork; |
| 136 | }; |
| 137 | |
| 138 | struct hpf_work { |
| 139 | struct tx_macro_priv *tx_priv; |
| 140 | u8 decimator; |
| 141 | u8 hpf_cut_off_freq; |
| 142 | struct delayed_work dwork; |
| 143 | }; |
| 144 | |
| 145 | struct tx_macro_priv { |
| 146 | struct device *dev; |
| 147 | bool dec_active[NUM_DECIMATORS]; |
| 148 | int tx_mclk_users; |
| 149 | int swr_clk_users; |
Ramprasad Katkam | 452772a | 2019-01-07 17:30:36 +0530 | [diff] [blame] | 150 | bool dapm_mclk_enable; |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame] | 151 | bool reset_swr; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 152 | struct mutex mclk_lock; |
| 153 | struct mutex swr_clk_lock; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 154 | struct snd_soc_component *component; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 155 | struct device_node *tx_swr_gpio_p; |
| 156 | struct tx_macro_swr_ctrl_data *swr_ctrl_data; |
| 157 | struct tx_macro_swr_ctrl_platform_data swr_plat_data; |
| 158 | struct work_struct tx_macro_add_child_devices_work; |
| 159 | struct hpf_work tx_hpf_work[NUM_DECIMATORS]; |
| 160 | struct tx_mute_work tx_mute_dwork[NUM_DECIMATORS]; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 161 | u16 dmic_clk_div; |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 162 | u32 version; |
Laxminath Kasam | 2e13d64 | 2019-10-12 01:36:30 +0530 | [diff] [blame] | 163 | u32 is_used_tx_swr_gpio; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 164 | unsigned long active_ch_mask[TX_MACRO_MAX_DAIS]; |
| 165 | unsigned long active_ch_cnt[TX_MACRO_MAX_DAIS]; |
| 166 | char __iomem *tx_io_base; |
| 167 | struct platform_device *pdev_child_devices |
| 168 | [TX_MACRO_CHILD_DEVICES_MAX]; |
| 169 | int child_count; |
Sudheer Papothi | e456c2c | 2019-03-05 07:08:45 +0530 | [diff] [blame] | 170 | int tx_swr_clk_cnt; |
| 171 | int va_swr_clk_cnt; |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 172 | int va_clk_status; |
| 173 | int tx_clk_status; |
Karthikeyan Mani | 765eaab | 2019-07-18 16:27:01 -0700 | [diff] [blame] | 174 | bool bcs_enable; |
Karthikeyan Mani | 1dcd5a3 | 2019-08-22 14:37:13 -0700 | [diff] [blame] | 175 | int dec_mode[NUM_DECIMATORS]; |
Vatsal Bucha | d06525f | 2019-10-14 23:14:12 +0530 | [diff] [blame] | 176 | bool bcs_clk_en; |
| 177 | bool hs_slow_insert_complete; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 178 | }; |
| 179 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 180 | static bool tx_macro_get_data(struct snd_soc_component *component, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 181 | struct device **tx_dev, |
| 182 | struct tx_macro_priv **tx_priv, |
| 183 | const char *func_name) |
| 184 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 185 | *tx_dev = bolero_get_device_ptr(component->dev, TX_MACRO); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 186 | if (!(*tx_dev)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 187 | dev_err(component->dev, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 188 | "%s: null device for macro!\n", func_name); |
| 189 | return false; |
| 190 | } |
| 191 | |
| 192 | *tx_priv = dev_get_drvdata((*tx_dev)); |
| 193 | if (!(*tx_priv)) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 194 | dev_err(component->dev, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 195 | "%s: priv is null for macro!\n", func_name); |
| 196 | return false; |
| 197 | } |
| 198 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 199 | if (!(*tx_priv)->component) { |
| 200 | dev_err(component->dev, |
| 201 | "%s: tx_priv->component not initialized!\n", func_name); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 202 | return false; |
| 203 | } |
| 204 | |
| 205 | return true; |
| 206 | } |
| 207 | |
| 208 | static int tx_macro_mclk_enable(struct tx_macro_priv *tx_priv, |
| 209 | bool mclk_enable) |
| 210 | { |
| 211 | struct regmap *regmap = dev_get_regmap(tx_priv->dev->parent, NULL); |
| 212 | int ret = 0; |
| 213 | |
Tanya Dixit | 8530fb9 | 2018-09-14 16:01:25 +0530 | [diff] [blame] | 214 | if (regmap == NULL) { |
| 215 | dev_err(tx_priv->dev, "%s: regmap is NULL\n", __func__); |
| 216 | return -EINVAL; |
| 217 | } |
| 218 | |
Laxminath Kasam | b7f823c | 2018-08-02 13:23:11 +0530 | [diff] [blame] | 219 | dev_dbg(tx_priv->dev, "%s: mclk_enable = %u,clk_users= %d\n", |
| 220 | __func__, mclk_enable, tx_priv->tx_mclk_users); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 221 | |
| 222 | mutex_lock(&tx_priv->mclk_lock); |
| 223 | if (mclk_enable) { |
Meng Wang | 52a8fb1 | 2019-12-12 20:36:05 +0800 | [diff] [blame] | 224 | ret = bolero_clk_rsc_request_clock(tx_priv->dev, |
| 225 | TX_CORE_CLK, |
| 226 | TX_CORE_CLK, |
| 227 | true); |
| 228 | if (ret < 0) { |
| 229 | dev_err_ratelimited(tx_priv->dev, |
| 230 | "%s: request clock enable failed\n", |
| 231 | __func__); |
| 232 | goto exit; |
| 233 | } |
| 234 | bolero_clk_rsc_fs_gen_request(tx_priv->dev, |
| 235 | true); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 236 | if (tx_priv->tx_mclk_users == 0) { |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 237 | regcache_mark_dirty(regmap); |
| 238 | regcache_sync_region(regmap, |
| 239 | TX_START_OFFSET, |
| 240 | TX_MAX_OFFSET); |
| 241 | /* 9.6MHz MCLK, set value 0x00 if other frequency */ |
| 242 | regmap_update_bits(regmap, |
| 243 | BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK, 0x01, 0x01); |
| 244 | regmap_update_bits(regmap, |
| 245 | BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, |
| 246 | 0x01, 0x01); |
| 247 | regmap_update_bits(regmap, |
| 248 | BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, |
| 249 | 0x01, 0x01); |
| 250 | } |
| 251 | tx_priv->tx_mclk_users++; |
| 252 | } else { |
| 253 | if (tx_priv->tx_mclk_users <= 0) { |
| 254 | dev_err(tx_priv->dev, "%s: clock already disabled\n", |
| 255 | __func__); |
| 256 | tx_priv->tx_mclk_users = 0; |
| 257 | goto exit; |
| 258 | } |
| 259 | tx_priv->tx_mclk_users--; |
| 260 | if (tx_priv->tx_mclk_users == 0) { |
| 261 | regmap_update_bits(regmap, |
| 262 | BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, |
| 263 | 0x01, 0x00); |
| 264 | regmap_update_bits(regmap, |
| 265 | BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, |
| 266 | 0x01, 0x00); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 267 | } |
Meng Wang | 52a8fb1 | 2019-12-12 20:36:05 +0800 | [diff] [blame] | 268 | |
| 269 | bolero_clk_rsc_fs_gen_request(tx_priv->dev, |
| 270 | false); |
| 271 | bolero_clk_rsc_request_clock(tx_priv->dev, |
| 272 | TX_CORE_CLK, |
| 273 | TX_CORE_CLK, |
| 274 | false); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 275 | } |
| 276 | exit: |
| 277 | mutex_unlock(&tx_priv->mclk_lock); |
| 278 | return ret; |
| 279 | } |
| 280 | |
Sudheer Papothi | fc3adb0 | 2019-11-24 10:14:21 +0530 | [diff] [blame] | 281 | static int __tx_macro_mclk_enable(struct snd_soc_component *component, |
| 282 | bool enable) |
| 283 | { |
| 284 | struct device *tx_dev = NULL; |
| 285 | struct tx_macro_priv *tx_priv = NULL; |
| 286 | |
| 287 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
| 288 | return -EINVAL; |
| 289 | |
| 290 | return tx_macro_mclk_enable(tx_priv, enable); |
| 291 | } |
| 292 | |
Sudheer Papothi | e456c2c | 2019-03-05 07:08:45 +0530 | [diff] [blame] | 293 | static int tx_macro_va_swr_clk_event(struct snd_soc_dapm_widget *w, |
| 294 | struct snd_kcontrol *kcontrol, int event) |
| 295 | { |
| 296 | struct device *tx_dev = NULL; |
| 297 | struct tx_macro_priv *tx_priv = NULL; |
| 298 | struct snd_soc_component *component = |
| 299 | snd_soc_dapm_to_component(w->dapm); |
| 300 | |
| 301 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
| 302 | return -EINVAL; |
| 303 | |
| 304 | if (SND_SOC_DAPM_EVENT_ON(event)) |
| 305 | ++tx_priv->va_swr_clk_cnt; |
| 306 | if (SND_SOC_DAPM_EVENT_OFF(event)) |
| 307 | --tx_priv->va_swr_clk_cnt; |
| 308 | |
| 309 | return 0; |
| 310 | } |
| 311 | |
| 312 | static int tx_macro_tx_swr_clk_event(struct snd_soc_dapm_widget *w, |
| 313 | struct snd_kcontrol *kcontrol, int event) |
| 314 | { |
| 315 | struct device *tx_dev = NULL; |
| 316 | struct tx_macro_priv *tx_priv = NULL; |
| 317 | struct snd_soc_component *component = |
| 318 | snd_soc_dapm_to_component(w->dapm); |
| 319 | |
| 320 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
| 321 | return -EINVAL; |
| 322 | |
| 323 | if (SND_SOC_DAPM_EVENT_ON(event)) |
| 324 | ++tx_priv->tx_swr_clk_cnt; |
| 325 | if (SND_SOC_DAPM_EVENT_OFF(event)) |
| 326 | --tx_priv->tx_swr_clk_cnt; |
| 327 | |
| 328 | return 0; |
| 329 | } |
| 330 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 331 | static int tx_macro_mclk_event(struct snd_soc_dapm_widget *w, |
| 332 | struct snd_kcontrol *kcontrol, int event) |
| 333 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 334 | struct snd_soc_component *component = |
| 335 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 336 | int ret = 0; |
| 337 | struct device *tx_dev = NULL; |
| 338 | struct tx_macro_priv *tx_priv = NULL; |
| 339 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 340 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 341 | return -EINVAL; |
| 342 | |
| 343 | dev_dbg(tx_dev, "%s: event = %d\n", __func__, event); |
| 344 | switch (event) { |
| 345 | case SND_SOC_DAPM_PRE_PMU: |
| 346 | ret = tx_macro_mclk_enable(tx_priv, 1); |
Ramprasad Katkam | 452772a | 2019-01-07 17:30:36 +0530 | [diff] [blame] | 347 | if (ret) |
| 348 | tx_priv->dapm_mclk_enable = false; |
| 349 | else |
| 350 | tx_priv->dapm_mclk_enable = true; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 351 | break; |
| 352 | case SND_SOC_DAPM_POST_PMD: |
Ramprasad Katkam | 452772a | 2019-01-07 17:30:36 +0530 | [diff] [blame] | 353 | if (tx_priv->dapm_mclk_enable) |
| 354 | ret = tx_macro_mclk_enable(tx_priv, 0); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 355 | break; |
| 356 | default: |
| 357 | dev_err(tx_priv->dev, |
| 358 | "%s: invalid DAPM event %d\n", __func__, event); |
| 359 | ret = -EINVAL; |
| 360 | } |
| 361 | return ret; |
| 362 | } |
| 363 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 364 | static int tx_macro_event_handler(struct snd_soc_component *component, |
| 365 | u16 event, u32 data) |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 366 | { |
| 367 | struct device *tx_dev = NULL; |
| 368 | struct tx_macro_priv *tx_priv = NULL; |
Aditya Bavanari | 50ef13e | 2019-08-09 15:14:43 +0530 | [diff] [blame] | 369 | int ret = 0; |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 370 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 371 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 372 | return -EINVAL; |
| 373 | |
| 374 | switch (event) { |
| 375 | case BOLERO_MACRO_EVT_SSR_DOWN: |
Karthikeyan Mani | 3bd80a5 | 2019-06-04 23:40:16 -0700 | [diff] [blame] | 376 | if (tx_priv->swr_ctrl_data) { |
| 377 | swrm_wcd_notify( |
| 378 | tx_priv->swr_ctrl_data[0].tx_swr_pdev, |
| 379 | SWR_DEVICE_DOWN, NULL); |
| 380 | swrm_wcd_notify( |
| 381 | tx_priv->swr_ctrl_data[0].tx_swr_pdev, |
| 382 | SWR_DEVICE_SSR_DOWN, NULL); |
| 383 | } |
Aditya Bavanari | 50ef13e | 2019-08-09 15:14:43 +0530 | [diff] [blame] | 384 | if ((!pm_runtime_enabled(tx_dev) || |
| 385 | !pm_runtime_suspended(tx_dev))) { |
| 386 | ret = bolero_runtime_suspend(tx_dev); |
| 387 | if (!ret) { |
| 388 | pm_runtime_disable(tx_dev); |
| 389 | pm_runtime_set_suspended(tx_dev); |
| 390 | pm_runtime_enable(tx_dev); |
| 391 | } |
| 392 | } |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 393 | break; |
| 394 | case BOLERO_MACRO_EVT_SSR_UP: |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame] | 395 | /* reset swr after ssr/pdr */ |
| 396 | tx_priv->reset_swr = true; |
Karthikeyan Mani | 3bd80a5 | 2019-06-04 23:40:16 -0700 | [diff] [blame] | 397 | if (tx_priv->swr_ctrl_data) |
| 398 | swrm_wcd_notify( |
| 399 | tx_priv->swr_ctrl_data[0].tx_swr_pdev, |
| 400 | SWR_DEVICE_SSR_UP, NULL); |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 401 | break; |
Meng Wang | 8ef0cc2 | 2019-05-08 15:12:56 +0800 | [diff] [blame] | 402 | case BOLERO_MACRO_EVT_CLK_RESET: |
| 403 | bolero_rsc_clk_reset(tx_dev, TX_CORE_CLK); |
| 404 | break; |
Vatsal Bucha | d06525f | 2019-10-14 23:14:12 +0530 | [diff] [blame] | 405 | case BOLERO_MACRO_EVT_BCS_CLK_OFF: |
| 406 | if (tx_priv->bcs_clk_en) |
| 407 | snd_soc_component_update_bits(component, |
| 408 | BOLERO_CDC_TX0_TX_PATH_SEC7, 0x40, data << 6); |
| 409 | if (data) |
| 410 | tx_priv->hs_slow_insert_complete = true; |
| 411 | else |
| 412 | tx_priv->hs_slow_insert_complete = false; |
| 413 | break; |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 414 | } |
| 415 | return 0; |
| 416 | } |
| 417 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 418 | static int tx_macro_reg_wake_irq(struct snd_soc_component *component, |
Aditya Bavanari | c4e9612 | 2018-11-14 14:46:38 +0530 | [diff] [blame] | 419 | u32 data) |
| 420 | { |
| 421 | struct device *tx_dev = NULL; |
| 422 | struct tx_macro_priv *tx_priv = NULL; |
| 423 | u32 ipc_wakeup = data; |
| 424 | int ret = 0; |
| 425 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 426 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Aditya Bavanari | c4e9612 | 2018-11-14 14:46:38 +0530 | [diff] [blame] | 427 | return -EINVAL; |
| 428 | |
Karthikeyan Mani | 3bd80a5 | 2019-06-04 23:40:16 -0700 | [diff] [blame] | 429 | if (tx_priv->swr_ctrl_data) |
| 430 | ret = swrm_wcd_notify( |
| 431 | tx_priv->swr_ctrl_data[0].tx_swr_pdev, |
| 432 | SWR_REGISTER_WAKE_IRQ, &ipc_wakeup); |
Aditya Bavanari | c4e9612 | 2018-11-14 14:46:38 +0530 | [diff] [blame] | 433 | |
| 434 | return ret; |
| 435 | } |
| 436 | |
Sudheer Papothi | 339c411 | 2019-12-13 00:49:16 +0530 | [diff] [blame] | 437 | static int is_amic_enabled(struct snd_soc_component *component, int decimator) |
| 438 | { |
| 439 | u16 adc_mux_reg = 0, adc_reg = 0; |
| 440 | u16 adc_n = BOLERO_ADC_MAX; |
| 441 | |
| 442 | adc_mux_reg = BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG1 + |
| 443 | TX_MACRO_ADC_MUX_CFG_OFFSET * decimator; |
| 444 | if (snd_soc_component_read32(component, adc_mux_reg) & SWR_MIC) { |
| 445 | adc_reg = BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0 + |
| 446 | TX_MACRO_ADC_MUX_CFG_OFFSET * decimator; |
| 447 | adc_n = snd_soc_component_read32(component, adc_reg) & |
| 448 | TX_MACRO_SWR_MIC_MUX_SEL_MASK; |
| 449 | if (adc_n >= BOLERO_ADC_MAX) |
| 450 | adc_n = BOLERO_ADC_MAX; |
| 451 | } |
| 452 | |
| 453 | return adc_n; |
| 454 | } |
| 455 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 456 | static void tx_macro_tx_hpf_corner_freq_callback(struct work_struct *work) |
| 457 | { |
| 458 | struct delayed_work *hpf_delayed_work = NULL; |
| 459 | struct hpf_work *hpf_work = NULL; |
| 460 | struct tx_macro_priv *tx_priv = NULL; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 461 | struct snd_soc_component *component = NULL; |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 462 | u16 dec_cfg_reg = 0, hpf_gate_reg = 0; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 463 | u8 hpf_cut_off_freq = 0; |
Sudheer Papothi | 339c411 | 2019-12-13 00:49:16 +0530 | [diff] [blame] | 464 | u16 adc_n = 0; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 465 | |
| 466 | hpf_delayed_work = to_delayed_work(work); |
| 467 | hpf_work = container_of(hpf_delayed_work, struct hpf_work, dwork); |
| 468 | tx_priv = hpf_work->tx_priv; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 469 | component = tx_priv->component; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 470 | hpf_cut_off_freq = hpf_work->hpf_cut_off_freq; |
| 471 | |
| 472 | dec_cfg_reg = BOLERO_CDC_TX0_TX_PATH_CFG0 + |
| 473 | TX_MACRO_TX_PATH_OFFSET * hpf_work->decimator; |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 474 | hpf_gate_reg = BOLERO_CDC_TX0_TX_PATH_SEC2 + |
| 475 | TX_MACRO_TX_PATH_OFFSET * hpf_work->decimator; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 476 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 477 | dev_dbg(component->dev, "%s: decimator %u hpf_cut_of_freq 0x%x\n", |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 478 | __func__, hpf_work->decimator, hpf_cut_off_freq); |
| 479 | |
Sudheer Papothi | 339c411 | 2019-12-13 00:49:16 +0530 | [diff] [blame] | 480 | adc_n = is_amic_enabled(component, hpf_work->decimator); |
| 481 | if (adc_n < BOLERO_ADC_MAX) { |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 482 | /* analog mic clear TX hold */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 483 | bolero_clear_amic_tx_hold(component->dev, adc_n); |
Sudheer Papothi | 339c411 | 2019-12-13 00:49:16 +0530 | [diff] [blame] | 484 | snd_soc_component_update_bits(component, |
| 485 | dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK, |
| 486 | hpf_cut_off_freq << 5); |
| 487 | snd_soc_component_update_bits(component, hpf_gate_reg, |
| 488 | 0x03, 0x02); |
| 489 | /* Minimum 1 clk cycle delay is required as per HW spec */ |
| 490 | usleep_range(1000, 1010); |
| 491 | snd_soc_component_update_bits(component, hpf_gate_reg, |
| 492 | 0x03, 0x01); |
| 493 | } else { |
| 494 | snd_soc_component_update_bits(component, |
| 495 | dec_cfg_reg, TX_HPF_CUT_OFF_FREQ_MASK, |
| 496 | hpf_cut_off_freq << 5); |
| 497 | snd_soc_component_update_bits(component, hpf_gate_reg, |
| 498 | 0x02, 0x02); |
| 499 | /* Minimum 1 clk cycle delay is required as per HW spec */ |
| 500 | usleep_range(1000, 1010); |
| 501 | snd_soc_component_update_bits(component, hpf_gate_reg, |
| 502 | 0x02, 0x00); |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 503 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 504 | } |
| 505 | |
| 506 | static void tx_macro_mute_update_callback(struct work_struct *work) |
| 507 | { |
| 508 | struct tx_mute_work *tx_mute_dwork = NULL; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 509 | struct snd_soc_component *component = NULL; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 510 | struct tx_macro_priv *tx_priv = NULL; |
| 511 | struct delayed_work *delayed_work = NULL; |
Xiaojun Sang | d155fdc | 2018-10-11 15:11:59 +0800 | [diff] [blame] | 512 | u16 tx_vol_ctl_reg = 0; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 513 | u8 decimator = 0; |
| 514 | |
| 515 | delayed_work = to_delayed_work(work); |
| 516 | tx_mute_dwork = container_of(delayed_work, struct tx_mute_work, dwork); |
| 517 | tx_priv = tx_mute_dwork->tx_priv; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 518 | component = tx_priv->component; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 519 | decimator = tx_mute_dwork->decimator; |
| 520 | |
| 521 | tx_vol_ctl_reg = |
| 522 | BOLERO_CDC_TX0_TX_PATH_CTL + |
| 523 | TX_MACRO_TX_PATH_OFFSET * decimator; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 524 | snd_soc_component_update_bits(component, tx_vol_ctl_reg, 0x10, 0x00); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 525 | dev_dbg(tx_priv->dev, "%s: decimator %u unmute\n", |
| 526 | __func__, decimator); |
| 527 | } |
| 528 | |
| 529 | static int tx_macro_put_dec_enum(struct snd_kcontrol *kcontrol, |
| 530 | struct snd_ctl_elem_value *ucontrol) |
| 531 | { |
| 532 | struct snd_soc_dapm_widget *widget = |
| 533 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 534 | struct snd_soc_component *component = |
| 535 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 536 | struct soc_enum *e = (struct soc_enum *)kcontrol->private_value; |
| 537 | unsigned int val = 0; |
| 538 | u16 mic_sel_reg = 0; |
Laxminath Kasam | 549d11d | 2019-07-18 13:44:17 +0530 | [diff] [blame] | 539 | u16 dmic_clk_reg = 0; |
| 540 | struct device *tx_dev = NULL; |
| 541 | struct tx_macro_priv *tx_priv = NULL; |
| 542 | |
| 543 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
| 544 | return -EINVAL; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 545 | |
| 546 | val = ucontrol->value.enumerated.item[0]; |
| 547 | if (val > e->items - 1) |
| 548 | return -EINVAL; |
| 549 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 550 | dev_dbg(component->dev, "%s: wname: %s, val: 0x%x\n", __func__, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 551 | widget->name, val); |
| 552 | |
| 553 | switch (e->reg) { |
| 554 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0: |
| 555 | mic_sel_reg = BOLERO_CDC_TX0_TX_PATH_CFG0; |
| 556 | break; |
| 557 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0: |
| 558 | mic_sel_reg = BOLERO_CDC_TX1_TX_PATH_CFG0; |
| 559 | break; |
| 560 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0: |
| 561 | mic_sel_reg = BOLERO_CDC_TX2_TX_PATH_CFG0; |
| 562 | break; |
| 563 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0: |
| 564 | mic_sel_reg = BOLERO_CDC_TX3_TX_PATH_CFG0; |
| 565 | break; |
| 566 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0: |
| 567 | mic_sel_reg = BOLERO_CDC_TX4_TX_PATH_CFG0; |
| 568 | break; |
| 569 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0: |
| 570 | mic_sel_reg = BOLERO_CDC_TX5_TX_PATH_CFG0; |
| 571 | break; |
| 572 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0: |
| 573 | mic_sel_reg = BOLERO_CDC_TX6_TX_PATH_CFG0; |
| 574 | break; |
| 575 | case BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0: |
| 576 | mic_sel_reg = BOLERO_CDC_TX7_TX_PATH_CFG0; |
| 577 | break; |
| 578 | default: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 579 | dev_err(component->dev, "%s: e->reg: 0x%x not expected\n", |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 580 | __func__, e->reg); |
| 581 | return -EINVAL; |
| 582 | } |
Laxminath Kasam | 497a651 | 2018-09-17 16:11:52 +0530 | [diff] [blame] | 583 | if (strnstr(widget->name, "SMIC", strlen(widget->name))) { |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 584 | if (val != 0) { |
Laxminath Kasam | 549d11d | 2019-07-18 13:44:17 +0530 | [diff] [blame] | 585 | if (val < 5) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 586 | snd_soc_component_update_bits(component, |
| 587 | mic_sel_reg, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 588 | 1 << 7, 0x0 << 7); |
Laxminath Kasam | 549d11d | 2019-07-18 13:44:17 +0530 | [diff] [blame] | 589 | } else { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 590 | snd_soc_component_update_bits(component, |
| 591 | mic_sel_reg, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 592 | 1 << 7, 0x1 << 7); |
Laxminath Kasam | 549d11d | 2019-07-18 13:44:17 +0530 | [diff] [blame] | 593 | snd_soc_component_update_bits(component, |
| 594 | BOLERO_CDC_VA_TOP_CSR_DMIC_CFG, |
| 595 | 0x80, 0x00); |
| 596 | dmic_clk_reg = |
| 597 | BOLERO_CDC_TX_TOP_CSR_SWR_DMIC0_CTL + |
| 598 | ((val - 5)/2) * 4; |
| 599 | snd_soc_component_update_bits(component, |
| 600 | dmic_clk_reg, |
| 601 | 0x0E, tx_priv->dmic_clk_div << 0x1); |
| 602 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 603 | } |
| 604 | } else { |
| 605 | /* DMIC selected */ |
| 606 | if (val != 0) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 607 | snd_soc_component_update_bits(component, mic_sel_reg, |
| 608 | 1 << 7, 1 << 7); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 609 | } |
| 610 | |
| 611 | return snd_soc_dapm_put_enum_double(kcontrol, ucontrol); |
| 612 | } |
| 613 | |
| 614 | static int tx_macro_tx_mixer_get(struct snd_kcontrol *kcontrol, |
| 615 | struct snd_ctl_elem_value *ucontrol) |
| 616 | { |
| 617 | struct snd_soc_dapm_widget *widget = |
| 618 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 619 | struct snd_soc_component *component = |
| 620 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 621 | struct soc_multi_mixer_control *mixer = |
| 622 | ((struct soc_multi_mixer_control *)kcontrol->private_value); |
| 623 | u32 dai_id = widget->shift; |
| 624 | u32 dec_id = mixer->shift; |
| 625 | struct device *tx_dev = NULL; |
| 626 | struct tx_macro_priv *tx_priv = NULL; |
| 627 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 628 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 629 | return -EINVAL; |
| 630 | |
| 631 | if (test_bit(dec_id, &tx_priv->active_ch_mask[dai_id])) |
| 632 | ucontrol->value.integer.value[0] = 1; |
| 633 | else |
| 634 | ucontrol->value.integer.value[0] = 0; |
| 635 | return 0; |
| 636 | } |
| 637 | |
| 638 | static int tx_macro_tx_mixer_put(struct snd_kcontrol *kcontrol, |
| 639 | struct snd_ctl_elem_value *ucontrol) |
| 640 | { |
| 641 | struct snd_soc_dapm_widget *widget = |
| 642 | snd_soc_dapm_kcontrol_widget(kcontrol); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 643 | struct snd_soc_component *component = |
| 644 | snd_soc_dapm_to_component(widget->dapm); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 645 | struct snd_soc_dapm_update *update = NULL; |
| 646 | struct soc_multi_mixer_control *mixer = |
| 647 | ((struct soc_multi_mixer_control *)kcontrol->private_value); |
| 648 | u32 dai_id = widget->shift; |
| 649 | u32 dec_id = mixer->shift; |
| 650 | u32 enable = ucontrol->value.integer.value[0]; |
| 651 | struct device *tx_dev = NULL; |
| 652 | struct tx_macro_priv *tx_priv = NULL; |
| 653 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 654 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 655 | return -EINVAL; |
| 656 | |
| 657 | if (enable) { |
| 658 | set_bit(dec_id, &tx_priv->active_ch_mask[dai_id]); |
| 659 | tx_priv->active_ch_cnt[dai_id]++; |
| 660 | } else { |
| 661 | tx_priv->active_ch_cnt[dai_id]--; |
| 662 | clear_bit(dec_id, &tx_priv->active_ch_mask[dai_id]); |
| 663 | } |
| 664 | snd_soc_dapm_mixer_update_power(widget->dapm, kcontrol, enable, update); |
| 665 | |
| 666 | return 0; |
| 667 | } |
Karthikeyan Mani | 1dcd5a3 | 2019-08-22 14:37:13 -0700 | [diff] [blame] | 668 | |
| 669 | static inline int tx_macro_path_get(const char *wname, |
| 670 | unsigned int *path_num) |
| 671 | { |
| 672 | int ret = 0; |
| 673 | char *widget_name = NULL; |
| 674 | char *w_name = NULL; |
| 675 | char *path_num_char = NULL; |
| 676 | char *path_name = NULL; |
| 677 | |
| 678 | widget_name = kstrndup(wname, 10, GFP_KERNEL); |
| 679 | if (!widget_name) |
| 680 | return -EINVAL; |
| 681 | |
| 682 | w_name = widget_name; |
| 683 | |
| 684 | path_name = strsep(&widget_name, " "); |
| 685 | if (!path_name) { |
| 686 | pr_err("%s: Invalid widget name = %s\n", |
| 687 | __func__, widget_name); |
| 688 | ret = -EINVAL; |
| 689 | goto err; |
| 690 | } |
| 691 | path_num_char = strpbrk(path_name, "01234567"); |
| 692 | if (!path_num_char) { |
| 693 | pr_err("%s: tx path index not found\n", |
| 694 | __func__); |
| 695 | ret = -EINVAL; |
| 696 | goto err; |
| 697 | } |
| 698 | ret = kstrtouint(path_num_char, 10, path_num); |
| 699 | if (ret < 0) |
| 700 | pr_err("%s: Invalid tx path = %s\n", |
| 701 | __func__, w_name); |
| 702 | |
| 703 | err: |
| 704 | kfree(w_name); |
| 705 | return ret; |
| 706 | } |
| 707 | |
| 708 | static int tx_macro_dec_mode_get(struct snd_kcontrol *kcontrol, |
| 709 | struct snd_ctl_elem_value *ucontrol) |
| 710 | { |
| 711 | struct snd_soc_component *component = |
| 712 | snd_soc_kcontrol_component(kcontrol); |
| 713 | struct tx_macro_priv *tx_priv = NULL; |
| 714 | struct device *tx_dev = NULL; |
| 715 | int ret = 0; |
| 716 | int path = 0; |
| 717 | |
| 718 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
| 719 | return -EINVAL; |
| 720 | |
| 721 | ret = tx_macro_path_get(kcontrol->id.name, &path); |
| 722 | if (ret) |
| 723 | return ret; |
| 724 | |
| 725 | ucontrol->value.integer.value[0] = tx_priv->dec_mode[path]; |
| 726 | |
| 727 | return 0; |
| 728 | } |
| 729 | |
| 730 | static int tx_macro_dec_mode_put(struct snd_kcontrol *kcontrol, |
| 731 | struct snd_ctl_elem_value *ucontrol) |
| 732 | { |
| 733 | struct snd_soc_component *component = |
| 734 | snd_soc_kcontrol_component(kcontrol); |
| 735 | struct tx_macro_priv *tx_priv = NULL; |
| 736 | struct device *tx_dev = NULL; |
| 737 | int value = ucontrol->value.integer.value[0]; |
| 738 | int ret = 0; |
| 739 | int path = 0; |
| 740 | |
| 741 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
| 742 | return -EINVAL; |
| 743 | |
| 744 | ret = tx_macro_path_get(kcontrol->id.name, &path); |
| 745 | if (ret) |
| 746 | return ret; |
| 747 | |
| 748 | tx_priv->dec_mode[path] = value; |
| 749 | |
| 750 | return 0; |
| 751 | } |
| 752 | |
Karthikeyan Mani | 765eaab | 2019-07-18 16:27:01 -0700 | [diff] [blame] | 753 | static int tx_macro_get_bcs(struct snd_kcontrol *kcontrol, |
| 754 | struct snd_ctl_elem_value *ucontrol) |
| 755 | { |
| 756 | struct snd_soc_component *component = |
| 757 | snd_soc_kcontrol_component(kcontrol); |
| 758 | struct tx_macro_priv *tx_priv = NULL; |
| 759 | struct device *tx_dev = NULL; |
| 760 | |
| 761 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
| 762 | return -EINVAL; |
| 763 | |
| 764 | ucontrol->value.integer.value[0] = tx_priv->bcs_enable; |
| 765 | |
| 766 | return 0; |
| 767 | } |
| 768 | |
| 769 | static int tx_macro_set_bcs(struct snd_kcontrol *kcontrol, |
| 770 | struct snd_ctl_elem_value *ucontrol) |
| 771 | { |
| 772 | struct snd_soc_component *component = |
| 773 | snd_soc_kcontrol_component(kcontrol); |
| 774 | struct tx_macro_priv *tx_priv = NULL; |
| 775 | struct device *tx_dev = NULL; |
| 776 | int value = ucontrol->value.integer.value[0]; |
| 777 | |
| 778 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
| 779 | return -EINVAL; |
| 780 | |
| 781 | tx_priv->bcs_enable = value; |
| 782 | |
| 783 | return 0; |
| 784 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 785 | |
| 786 | static int tx_macro_enable_dmic(struct snd_soc_dapm_widget *w, |
| 787 | struct snd_kcontrol *kcontrol, int event) |
| 788 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 789 | struct snd_soc_component *component = |
| 790 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 791 | unsigned int dmic = 0; |
| 792 | int ret = 0; |
| 793 | char *wname = NULL; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 794 | |
| 795 | wname = strpbrk(w->name, "01234567"); |
| 796 | if (!wname) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 797 | dev_err(component->dev, "%s: widget not found\n", __func__); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 798 | return -EINVAL; |
| 799 | } |
| 800 | |
| 801 | ret = kstrtouint(wname, 10, &dmic); |
| 802 | if (ret < 0) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 803 | dev_err(component->dev, "%s: Invalid DMIC line on the codec\n", |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 804 | __func__); |
| 805 | return -EINVAL; |
| 806 | } |
| 807 | |
Sudheer Papothi | d50a581 | 2019-11-21 07:24:42 +0530 | [diff] [blame] | 808 | dev_dbg(component->dev, "%s: event %d DMIC%d\n", |
| 809 | __func__, event, dmic); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 810 | |
| 811 | switch (event) { |
| 812 | case SND_SOC_DAPM_PRE_PMU: |
Sudheer Papothi | d50a581 | 2019-11-21 07:24:42 +0530 | [diff] [blame] | 813 | bolero_dmic_clk_enable(component, dmic, DMIC_TX, true); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 814 | break; |
| 815 | case SND_SOC_DAPM_POST_PMD: |
Sudheer Papothi | d50a581 | 2019-11-21 07:24:42 +0530 | [diff] [blame] | 816 | bolero_dmic_clk_enable(component, dmic, DMIC_TX, false); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 817 | break; |
| 818 | } |
| 819 | |
| 820 | return 0; |
| 821 | } |
| 822 | |
| 823 | static int tx_macro_enable_dec(struct snd_soc_dapm_widget *w, |
| 824 | struct snd_kcontrol *kcontrol, int event) |
| 825 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 826 | struct snd_soc_component *component = |
| 827 | snd_soc_dapm_to_component(w->dapm); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 828 | unsigned int decimator = 0; |
| 829 | u16 tx_vol_ctl_reg = 0; |
| 830 | u16 dec_cfg_reg = 0; |
| 831 | u16 hpf_gate_reg = 0; |
| 832 | u16 tx_gain_ctl_reg = 0; |
| 833 | u8 hpf_cut_off_freq = 0; |
Sudheer Papothi | 339c411 | 2019-12-13 00:49:16 +0530 | [diff] [blame] | 834 | int hpf_delay = TX_MACRO_DMIC_HPF_DELAY_MS; |
| 835 | int unmute_delay = TX_MACRO_DMIC_UNMUTE_DELAY_MS; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 836 | struct device *tx_dev = NULL; |
| 837 | struct tx_macro_priv *tx_priv = NULL; |
| 838 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 839 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 840 | return -EINVAL; |
| 841 | |
| 842 | decimator = w->shift; |
| 843 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 844 | dev_dbg(component->dev, "%s(): widget = %s decimator = %u\n", __func__, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 845 | w->name, decimator); |
| 846 | |
| 847 | tx_vol_ctl_reg = BOLERO_CDC_TX0_TX_PATH_CTL + |
| 848 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 849 | hpf_gate_reg = BOLERO_CDC_TX0_TX_PATH_SEC2 + |
| 850 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 851 | dec_cfg_reg = BOLERO_CDC_TX0_TX_PATH_CFG0 + |
| 852 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 853 | tx_gain_ctl_reg = BOLERO_CDC_TX0_TX_VOL_CTL + |
| 854 | TX_MACRO_TX_PATH_OFFSET * decimator; |
| 855 | |
| 856 | switch (event) { |
| 857 | case SND_SOC_DAPM_PRE_PMU: |
Karthikeyan Mani | 1dcd5a3 | 2019-08-22 14:37:13 -0700 | [diff] [blame] | 858 | snd_soc_component_update_bits(component, |
| 859 | dec_cfg_reg, 0x06, tx_priv->dec_mode[decimator] << |
| 860 | TX_MACRO_ADC_MODE_CFG0_SHIFT); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 861 | /* Enable TX PGA Mute */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 862 | snd_soc_component_update_bits(component, |
| 863 | tx_vol_ctl_reg, 0x10, 0x10); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 864 | break; |
| 865 | case SND_SOC_DAPM_POST_PMU: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 866 | snd_soc_component_update_bits(component, |
| 867 | tx_vol_ctl_reg, 0x20, 0x20); |
| 868 | snd_soc_component_update_bits(component, |
| 869 | hpf_gate_reg, 0x01, 0x00); |
Karthikeyan Mani | 144659b | 2019-10-02 17:29:57 -0700 | [diff] [blame] | 870 | /* |
| 871 | * Minimum 1 clk cycle delay is required as per HW spec |
| 872 | */ |
| 873 | usleep_range(1000, 1010); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 874 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 875 | hpf_cut_off_freq = ( |
| 876 | snd_soc_component_read32(component, dec_cfg_reg) & |
| 877 | TX_HPF_CUT_OFF_FREQ_MASK) >> 5; |
| 878 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 879 | tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq = |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 880 | hpf_cut_off_freq; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 881 | |
| 882 | if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 883 | snd_soc_component_update_bits(component, dec_cfg_reg, |
| 884 | TX_HPF_CUT_OFF_FREQ_MASK, |
| 885 | CF_MIN_3DB_150HZ << 5); |
| 886 | |
Sudheer Papothi | 339c411 | 2019-12-13 00:49:16 +0530 | [diff] [blame] | 887 | if (is_amic_enabled(component, decimator) < BOLERO_ADC_MAX) { |
| 888 | hpf_delay = TX_MACRO_AMIC_HPF_DELAY_MS; |
| 889 | unmute_delay = TX_MACRO_AMIC_UNMUTE_DELAY_MS; |
| 890 | } |
| 891 | if (tx_unmute_delay < unmute_delay) |
| 892 | tx_unmute_delay = unmute_delay; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 893 | /* schedule work queue to Remove Mute */ |
| 894 | schedule_delayed_work(&tx_priv->tx_mute_dwork[decimator].dwork, |
| 895 | msecs_to_jiffies(tx_unmute_delay)); |
| 896 | if (tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq != |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 897 | CF_MIN_3DB_150HZ) { |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 898 | schedule_delayed_work( |
Sudheer Papothi | 339c411 | 2019-12-13 00:49:16 +0530 | [diff] [blame] | 899 | &tx_priv->tx_hpf_work[decimator].dwork, |
| 900 | msecs_to_jiffies(hpf_delay)); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 901 | snd_soc_component_update_bits(component, |
Karthikeyan Mani | 144659b | 2019-10-02 17:29:57 -0700 | [diff] [blame] | 902 | hpf_gate_reg, 0x03, 0x03); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 903 | /* |
| 904 | * Minimum 1 clk cycle delay is required as per HW spec |
| 905 | */ |
| 906 | usleep_range(1000, 1010); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 907 | snd_soc_component_update_bits(component, |
| 908 | hpf_gate_reg, 0x02, 0x00); |
Karthikeyan Mani | 9366ce6 | 2019-11-06 11:43:36 -0800 | [diff] [blame] | 909 | snd_soc_component_update_bits(component, |
| 910 | hpf_gate_reg, 0x01, 0x01); |
| 911 | /* |
| 912 | * 6ms delay is required as per HW spec |
| 913 | */ |
| 914 | usleep_range(6000, 6010); |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 915 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 916 | /* apply gain after decimator is enabled */ |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 917 | snd_soc_component_write(component, tx_gain_ctl_reg, |
| 918 | snd_soc_component_read32(component, |
| 919 | tx_gain_ctl_reg)); |
Karthikeyan Mani | 765eaab | 2019-07-18 16:27:01 -0700 | [diff] [blame] | 920 | if (tx_priv->bcs_enable) { |
| 921 | snd_soc_component_update_bits(component, dec_cfg_reg, |
| 922 | 0x01, 0x01); |
Vatsal Bucha | d06525f | 2019-10-14 23:14:12 +0530 | [diff] [blame] | 923 | tx_priv->bcs_clk_en = true; |
| 924 | if (tx_priv->hs_slow_insert_complete) |
| 925 | snd_soc_component_update_bits(component, |
| 926 | BOLERO_CDC_TX0_TX_PATH_SEC7, 0x40, |
| 927 | 0x40); |
Karthikeyan Mani | 765eaab | 2019-07-18 16:27:01 -0700 | [diff] [blame] | 928 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 929 | break; |
| 930 | case SND_SOC_DAPM_PRE_PMD: |
| 931 | hpf_cut_off_freq = |
| 932 | tx_priv->tx_hpf_work[decimator].hpf_cut_off_freq; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 933 | snd_soc_component_update_bits(component, |
| 934 | tx_vol_ctl_reg, 0x10, 0x10); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 935 | if (cancel_delayed_work_sync( |
| 936 | &tx_priv->tx_hpf_work[decimator].dwork)) { |
| 937 | if (hpf_cut_off_freq != CF_MIN_3DB_150HZ) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 938 | snd_soc_component_update_bits( |
| 939 | component, dec_cfg_reg, |
| 940 | TX_HPF_CUT_OFF_FREQ_MASK, |
| 941 | hpf_cut_off_freq << 5); |
| 942 | snd_soc_component_update_bits(component, |
| 943 | hpf_gate_reg, |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 944 | 0x02, 0x02); |
| 945 | /* |
| 946 | * Minimum 1 clk cycle delay is required |
| 947 | * as per HW spec |
| 948 | */ |
| 949 | usleep_range(1000, 1010); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 950 | snd_soc_component_update_bits(component, |
| 951 | hpf_gate_reg, |
Laxminath Kasam | 9eb8022 | 2018-08-29 21:53:14 +0530 | [diff] [blame] | 952 | 0x02, 0x00); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 953 | } |
| 954 | } |
| 955 | cancel_delayed_work_sync( |
| 956 | &tx_priv->tx_mute_dwork[decimator].dwork); |
| 957 | break; |
| 958 | case SND_SOC_DAPM_POST_PMD: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 959 | snd_soc_component_update_bits(component, tx_vol_ctl_reg, |
| 960 | 0x20, 0x00); |
Karthikeyan Mani | 1dcd5a3 | 2019-08-22 14:37:13 -0700 | [diff] [blame] | 961 | snd_soc_component_update_bits(component, |
| 962 | dec_cfg_reg, 0x06, 0x00); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 963 | snd_soc_component_update_bits(component, tx_vol_ctl_reg, |
| 964 | 0x10, 0x00); |
Karthikeyan Mani | 765eaab | 2019-07-18 16:27:01 -0700 | [diff] [blame] | 965 | if (tx_priv->bcs_enable) { |
| 966 | snd_soc_component_update_bits(component, dec_cfg_reg, |
| 967 | 0x01, 0x00); |
| 968 | snd_soc_component_update_bits(component, |
| 969 | BOLERO_CDC_TX0_TX_PATH_SEC7, 0x40, 0x00); |
Vatsal Bucha | d06525f | 2019-10-14 23:14:12 +0530 | [diff] [blame] | 970 | tx_priv->bcs_clk_en = false; |
Karthikeyan Mani | 765eaab | 2019-07-18 16:27:01 -0700 | [diff] [blame] | 971 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 972 | break; |
| 973 | } |
| 974 | return 0; |
| 975 | } |
| 976 | |
| 977 | static int tx_macro_enable_micbias(struct snd_soc_dapm_widget *w, |
| 978 | struct snd_kcontrol *kcontrol, int event) |
| 979 | { |
| 980 | return 0; |
| 981 | } |
| 982 | |
| 983 | static int tx_macro_hw_params(struct snd_pcm_substream *substream, |
| 984 | struct snd_pcm_hw_params *params, |
| 985 | struct snd_soc_dai *dai) |
| 986 | { |
| 987 | int tx_fs_rate = -EINVAL; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 988 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 989 | u32 decimator = 0; |
Laxminath Kasam | b7f823c | 2018-08-02 13:23:11 +0530 | [diff] [blame] | 990 | u32 sample_rate = 0; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 991 | u16 tx_fs_reg = 0; |
| 992 | struct device *tx_dev = NULL; |
| 993 | struct tx_macro_priv *tx_priv = NULL; |
| 994 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 995 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 996 | return -EINVAL; |
| 997 | |
| 998 | pr_debug("%s: dai_name = %s DAI-ID %x rate %d num_ch %d\n", __func__, |
| 999 | dai->name, dai->id, params_rate(params), |
| 1000 | params_channels(params)); |
| 1001 | |
| 1002 | sample_rate = params_rate(params); |
| 1003 | switch (sample_rate) { |
| 1004 | case 8000: |
| 1005 | tx_fs_rate = 0; |
| 1006 | break; |
| 1007 | case 16000: |
| 1008 | tx_fs_rate = 1; |
| 1009 | break; |
| 1010 | case 32000: |
| 1011 | tx_fs_rate = 3; |
| 1012 | break; |
| 1013 | case 48000: |
| 1014 | tx_fs_rate = 4; |
| 1015 | break; |
| 1016 | case 96000: |
| 1017 | tx_fs_rate = 5; |
| 1018 | break; |
| 1019 | case 192000: |
| 1020 | tx_fs_rate = 6; |
| 1021 | break; |
| 1022 | case 384000: |
| 1023 | tx_fs_rate = 7; |
| 1024 | break; |
| 1025 | default: |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1026 | dev_err(component->dev, "%s: Invalid TX sample rate: %d\n", |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1027 | __func__, params_rate(params)); |
| 1028 | return -EINVAL; |
| 1029 | } |
| 1030 | for_each_set_bit(decimator, &tx_priv->active_ch_mask[dai->id], |
| 1031 | TX_MACRO_DEC_MAX) { |
| 1032 | if (decimator >= 0) { |
| 1033 | tx_fs_reg = BOLERO_CDC_TX0_TX_PATH_CTL + |
| 1034 | TX_MACRO_TX_PATH_OFFSET * decimator; |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1035 | dev_dbg(component->dev, "%s: set DEC%u rate to %u\n", |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1036 | __func__, decimator, sample_rate); |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1037 | snd_soc_component_update_bits(component, tx_fs_reg, |
| 1038 | 0x0F, tx_fs_rate); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1039 | } else { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1040 | dev_err(component->dev, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1041 | "%s: ERROR: Invalid decimator: %d\n", |
| 1042 | __func__, decimator); |
| 1043 | return -EINVAL; |
| 1044 | } |
| 1045 | } |
| 1046 | return 0; |
| 1047 | } |
| 1048 | |
| 1049 | static int tx_macro_get_channel_map(struct snd_soc_dai *dai, |
| 1050 | unsigned int *tx_num, unsigned int *tx_slot, |
| 1051 | unsigned int *rx_num, unsigned int *rx_slot) |
| 1052 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1053 | struct snd_soc_component *component = dai->component; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1054 | struct device *tx_dev = NULL; |
| 1055 | struct tx_macro_priv *tx_priv = NULL; |
| 1056 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 1057 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1058 | return -EINVAL; |
| 1059 | |
| 1060 | switch (dai->id) { |
| 1061 | case TX_MACRO_AIF1_CAP: |
| 1062 | case TX_MACRO_AIF2_CAP: |
Karthikeyan Mani | f3bb818 | 2019-07-11 14:38:54 -0700 | [diff] [blame] | 1063 | case TX_MACRO_AIF3_CAP: |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1064 | *tx_slot = tx_priv->active_ch_mask[dai->id]; |
| 1065 | *tx_num = tx_priv->active_ch_cnt[dai->id]; |
| 1066 | break; |
| 1067 | default: |
| 1068 | dev_err(tx_dev, "%s: Invalid AIF\n", __func__); |
| 1069 | break; |
| 1070 | } |
| 1071 | return 0; |
| 1072 | } |
| 1073 | |
| 1074 | static struct snd_soc_dai_ops tx_macro_dai_ops = { |
| 1075 | .hw_params = tx_macro_hw_params, |
| 1076 | .get_channel_map = tx_macro_get_channel_map, |
| 1077 | }; |
| 1078 | |
| 1079 | static struct snd_soc_dai_driver tx_macro_dai[] = { |
| 1080 | { |
| 1081 | .name = "tx_macro_tx1", |
| 1082 | .id = TX_MACRO_AIF1_CAP, |
| 1083 | .capture = { |
| 1084 | .stream_name = "TX_AIF1 Capture", |
| 1085 | .rates = TX_MACRO_RATES, |
| 1086 | .formats = TX_MACRO_FORMATS, |
| 1087 | .rate_max = 192000, |
| 1088 | .rate_min = 8000, |
| 1089 | .channels_min = 1, |
| 1090 | .channels_max = 8, |
| 1091 | }, |
| 1092 | .ops = &tx_macro_dai_ops, |
| 1093 | }, |
| 1094 | { |
| 1095 | .name = "tx_macro_tx2", |
| 1096 | .id = TX_MACRO_AIF2_CAP, |
| 1097 | .capture = { |
| 1098 | .stream_name = "TX_AIF2 Capture", |
| 1099 | .rates = TX_MACRO_RATES, |
| 1100 | .formats = TX_MACRO_FORMATS, |
| 1101 | .rate_max = 192000, |
| 1102 | .rate_min = 8000, |
| 1103 | .channels_min = 1, |
| 1104 | .channels_max = 8, |
| 1105 | }, |
| 1106 | .ops = &tx_macro_dai_ops, |
| 1107 | }, |
Karthikeyan Mani | f3bb818 | 2019-07-11 14:38:54 -0700 | [diff] [blame] | 1108 | { |
| 1109 | .name = "tx_macro_tx3", |
| 1110 | .id = TX_MACRO_AIF3_CAP, |
| 1111 | .capture = { |
| 1112 | .stream_name = "TX_AIF3 Capture", |
| 1113 | .rates = TX_MACRO_RATES, |
| 1114 | .formats = TX_MACRO_FORMATS, |
| 1115 | .rate_max = 192000, |
| 1116 | .rate_min = 8000, |
| 1117 | .channels_min = 1, |
| 1118 | .channels_max = 8, |
| 1119 | }, |
| 1120 | .ops = &tx_macro_dai_ops, |
| 1121 | }, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1122 | }; |
| 1123 | |
| 1124 | #define STRING(name) #name |
| 1125 | #define TX_MACRO_DAPM_ENUM(name, reg, offset, text) \ |
| 1126 | static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \ |
| 1127 | static const struct snd_kcontrol_new name##_mux = \ |
| 1128 | SOC_DAPM_ENUM(STRING(name), name##_enum) |
| 1129 | |
| 1130 | #define TX_MACRO_DAPM_ENUM_EXT(name, reg, offset, text, getname, putname) \ |
| 1131 | static SOC_ENUM_SINGLE_DECL(name##_enum, reg, offset, text); \ |
| 1132 | static const struct snd_kcontrol_new name##_mux = \ |
| 1133 | SOC_DAPM_ENUM_EXT(STRING(name), name##_enum, getname, putname) |
| 1134 | |
| 1135 | #define TX_MACRO_DAPM_MUX(name, shift, kctl) \ |
| 1136 | SND_SOC_DAPM_MUX(name, SND_SOC_NOPM, shift, 0, &kctl##_mux) |
| 1137 | |
| 1138 | static const char * const adc_mux_text[] = { |
| 1139 | "MSM_DMIC", "SWR_MIC", "ANC_FB_TUNE1" |
| 1140 | }; |
| 1141 | |
| 1142 | TX_MACRO_DAPM_ENUM(tx_dec0, BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG1, |
| 1143 | 0, adc_mux_text); |
| 1144 | TX_MACRO_DAPM_ENUM(tx_dec1, BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG1, |
| 1145 | 0, adc_mux_text); |
| 1146 | TX_MACRO_DAPM_ENUM(tx_dec2, BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG1, |
| 1147 | 0, adc_mux_text); |
| 1148 | TX_MACRO_DAPM_ENUM(tx_dec3, BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG1, |
| 1149 | 0, adc_mux_text); |
| 1150 | TX_MACRO_DAPM_ENUM(tx_dec4, BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG1, |
| 1151 | 0, adc_mux_text); |
| 1152 | TX_MACRO_DAPM_ENUM(tx_dec5, BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG1, |
| 1153 | 0, adc_mux_text); |
| 1154 | TX_MACRO_DAPM_ENUM(tx_dec6, BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG1, |
| 1155 | 0, adc_mux_text); |
| 1156 | TX_MACRO_DAPM_ENUM(tx_dec7, BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG1, |
| 1157 | 0, adc_mux_text); |
| 1158 | |
| 1159 | |
| 1160 | static const char * const dmic_mux_text[] = { |
| 1161 | "ZERO", "DMIC0", "DMIC1", "DMIC2", "DMIC3", |
| 1162 | "DMIC4", "DMIC5", "DMIC6", "DMIC7" |
| 1163 | }; |
| 1164 | |
| 1165 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic0, BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0, |
| 1166 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 1167 | tx_macro_put_dec_enum); |
| 1168 | |
| 1169 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic1, BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0, |
| 1170 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 1171 | tx_macro_put_dec_enum); |
| 1172 | |
| 1173 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic2, BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0, |
| 1174 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 1175 | tx_macro_put_dec_enum); |
| 1176 | |
| 1177 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic3, BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0, |
| 1178 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 1179 | tx_macro_put_dec_enum); |
| 1180 | |
| 1181 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic4, BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0, |
| 1182 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 1183 | tx_macro_put_dec_enum); |
| 1184 | |
| 1185 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic5, BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0, |
| 1186 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 1187 | tx_macro_put_dec_enum); |
| 1188 | |
| 1189 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic6, BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0, |
| 1190 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 1191 | tx_macro_put_dec_enum); |
| 1192 | |
| 1193 | TX_MACRO_DAPM_ENUM_EXT(tx_dmic7, BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0, |
| 1194 | 4, dmic_mux_text, snd_soc_dapm_get_enum_double, |
| 1195 | tx_macro_put_dec_enum); |
| 1196 | |
| 1197 | static const char * const smic_mux_text[] = { |
Sudheer Papothi | 324b495 | 2019-06-11 04:14:51 +0530 | [diff] [blame] | 1198 | "ZERO", "ADC0", "ADC1", "ADC2", "ADC3", "SWR_DMIC0", |
| 1199 | "SWR_DMIC1", "SWR_DMIC2", "SWR_DMIC3", "SWR_DMIC4", |
| 1200 | "SWR_DMIC5", "SWR_DMIC6", "SWR_DMIC7" |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1201 | }; |
| 1202 | |
| 1203 | TX_MACRO_DAPM_ENUM_EXT(tx_smic0, BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0, |
| 1204 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 1205 | tx_macro_put_dec_enum); |
| 1206 | |
| 1207 | TX_MACRO_DAPM_ENUM_EXT(tx_smic1, BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0, |
| 1208 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 1209 | tx_macro_put_dec_enum); |
| 1210 | |
| 1211 | TX_MACRO_DAPM_ENUM_EXT(tx_smic2, BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0, |
| 1212 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 1213 | tx_macro_put_dec_enum); |
| 1214 | |
| 1215 | TX_MACRO_DAPM_ENUM_EXT(tx_smic3, BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0, |
| 1216 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 1217 | tx_macro_put_dec_enum); |
| 1218 | |
| 1219 | TX_MACRO_DAPM_ENUM_EXT(tx_smic4, BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0, |
| 1220 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 1221 | tx_macro_put_dec_enum); |
| 1222 | |
| 1223 | TX_MACRO_DAPM_ENUM_EXT(tx_smic5, BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0, |
| 1224 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 1225 | tx_macro_put_dec_enum); |
| 1226 | |
| 1227 | TX_MACRO_DAPM_ENUM_EXT(tx_smic6, BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0, |
| 1228 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 1229 | tx_macro_put_dec_enum); |
| 1230 | |
| 1231 | TX_MACRO_DAPM_ENUM_EXT(tx_smic7, BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0, |
| 1232 | 0, smic_mux_text, snd_soc_dapm_get_enum_double, |
| 1233 | tx_macro_put_dec_enum); |
| 1234 | |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 1235 | static const char * const smic_mux_text_v2[] = { |
| 1236 | "ZERO", "SWR_MIC0", "SWR_MIC1", "SWR_MIC2", "SWR_MIC3", |
| 1237 | "SWR_MIC4", "SWR_MIC5", "SWR_MIC6", "SWR_MIC7", |
| 1238 | "SWR_MIC8", "SWR_MIC9", "SWR_MIC10", "SWR_MIC11" |
| 1239 | }; |
| 1240 | |
| 1241 | TX_MACRO_DAPM_ENUM_EXT(tx_smic0_v2, BOLERO_CDC_TX_INP_MUX_ADC_MUX0_CFG0, |
| 1242 | 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, |
| 1243 | tx_macro_put_dec_enum); |
| 1244 | |
| 1245 | TX_MACRO_DAPM_ENUM_EXT(tx_smic1_v2, BOLERO_CDC_TX_INP_MUX_ADC_MUX1_CFG0, |
| 1246 | 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, |
| 1247 | tx_macro_put_dec_enum); |
| 1248 | |
| 1249 | TX_MACRO_DAPM_ENUM_EXT(tx_smic2_v2, BOLERO_CDC_TX_INP_MUX_ADC_MUX2_CFG0, |
| 1250 | 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, |
| 1251 | tx_macro_put_dec_enum); |
| 1252 | |
| 1253 | TX_MACRO_DAPM_ENUM_EXT(tx_smic3_v2, BOLERO_CDC_TX_INP_MUX_ADC_MUX3_CFG0, |
| 1254 | 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, |
| 1255 | tx_macro_put_dec_enum); |
| 1256 | |
| 1257 | TX_MACRO_DAPM_ENUM_EXT(tx_smic4_v3, BOLERO_CDC_TX_INP_MUX_ADC_MUX4_CFG0, |
| 1258 | 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, |
| 1259 | tx_macro_put_dec_enum); |
| 1260 | |
| 1261 | TX_MACRO_DAPM_ENUM_EXT(tx_smic5_v3, BOLERO_CDC_TX_INP_MUX_ADC_MUX5_CFG0, |
| 1262 | 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, |
| 1263 | tx_macro_put_dec_enum); |
| 1264 | |
| 1265 | TX_MACRO_DAPM_ENUM_EXT(tx_smic6_v3, BOLERO_CDC_TX_INP_MUX_ADC_MUX6_CFG0, |
| 1266 | 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, |
| 1267 | tx_macro_put_dec_enum); |
| 1268 | |
| 1269 | TX_MACRO_DAPM_ENUM_EXT(tx_smic7_v3, BOLERO_CDC_TX_INP_MUX_ADC_MUX7_CFG0, |
| 1270 | 0, smic_mux_text_v2, snd_soc_dapm_get_enum_double, |
| 1271 | tx_macro_put_dec_enum); |
| 1272 | |
Karthikeyan Mani | 1dcd5a3 | 2019-08-22 14:37:13 -0700 | [diff] [blame] | 1273 | static const char * const dec_mode_mux_text[] = { |
| 1274 | "ADC_DEFAULT", "ADC_LOW_PWR", "ADC_HIGH_PERF", |
| 1275 | }; |
| 1276 | |
| 1277 | static const struct soc_enum dec_mode_mux_enum = |
| 1278 | SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(dec_mode_mux_text), |
| 1279 | dec_mode_mux_text); |
| 1280 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1281 | static const struct snd_kcontrol_new tx_aif1_cap_mixer[] = { |
| 1282 | SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, |
| 1283 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1284 | SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, |
| 1285 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1286 | SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, |
| 1287 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1288 | SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, |
| 1289 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1290 | SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, |
| 1291 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1292 | SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, |
| 1293 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1294 | SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, |
| 1295 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1296 | SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, |
| 1297 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1298 | }; |
| 1299 | |
| 1300 | static const struct snd_kcontrol_new tx_aif2_cap_mixer[] = { |
| 1301 | SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, |
| 1302 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1303 | SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, |
| 1304 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1305 | SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, |
| 1306 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1307 | SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, |
| 1308 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1309 | SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, |
| 1310 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1311 | SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, |
| 1312 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1313 | SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, |
| 1314 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1315 | SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, |
| 1316 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1317 | }; |
| 1318 | |
Karthikeyan Mani | f3bb818 | 2019-07-11 14:38:54 -0700 | [diff] [blame] | 1319 | static const struct snd_kcontrol_new tx_aif3_cap_mixer[] = { |
| 1320 | SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, |
| 1321 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1322 | SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, |
| 1323 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1324 | SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, |
| 1325 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1326 | SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, |
| 1327 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1328 | SOC_SINGLE_EXT("DEC4", SND_SOC_NOPM, TX_MACRO_DEC4, 1, 0, |
| 1329 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1330 | SOC_SINGLE_EXT("DEC5", SND_SOC_NOPM, TX_MACRO_DEC5, 1, 0, |
| 1331 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1332 | SOC_SINGLE_EXT("DEC6", SND_SOC_NOPM, TX_MACRO_DEC6, 1, 0, |
| 1333 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1334 | SOC_SINGLE_EXT("DEC7", SND_SOC_NOPM, TX_MACRO_DEC7, 1, 0, |
| 1335 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1336 | }; |
| 1337 | |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 1338 | static const struct snd_kcontrol_new tx_aif1_cap_mixer_v2[] = { |
| 1339 | SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, |
| 1340 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1341 | SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, |
| 1342 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1343 | SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, |
| 1344 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1345 | SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, |
| 1346 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1347 | }; |
| 1348 | |
| 1349 | static const struct snd_kcontrol_new tx_aif2_cap_mixer_v2[] = { |
| 1350 | SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, |
| 1351 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1352 | SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, |
| 1353 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1354 | SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, |
| 1355 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1356 | SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, |
| 1357 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1358 | }; |
| 1359 | |
| 1360 | static const struct snd_kcontrol_new tx_aif3_cap_mixer_v2[] = { |
| 1361 | SOC_SINGLE_EXT("DEC0", SND_SOC_NOPM, TX_MACRO_DEC0, 1, 0, |
| 1362 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1363 | SOC_SINGLE_EXT("DEC1", SND_SOC_NOPM, TX_MACRO_DEC1, 1, 0, |
| 1364 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1365 | SOC_SINGLE_EXT("DEC2", SND_SOC_NOPM, TX_MACRO_DEC2, 1, 0, |
| 1366 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1367 | SOC_SINGLE_EXT("DEC3", SND_SOC_NOPM, TX_MACRO_DEC3, 1, 0, |
| 1368 | tx_macro_tx_mixer_get, tx_macro_tx_mixer_put), |
| 1369 | }; |
| 1370 | |
| 1371 | static const struct snd_soc_dapm_widget tx_macro_dapm_widgets_common[] = { |
| 1372 | SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0, |
| 1373 | SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0), |
| 1374 | |
| 1375 | SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0, |
| 1376 | SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0), |
| 1377 | |
| 1378 | SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0, |
| 1379 | SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0), |
| 1380 | |
| 1381 | TX_MACRO_DAPM_MUX("TX DMIC MUX0", 0, tx_dmic0), |
| 1382 | TX_MACRO_DAPM_MUX("TX DMIC MUX1", 0, tx_dmic1), |
| 1383 | TX_MACRO_DAPM_MUX("TX DMIC MUX2", 0, tx_dmic2), |
| 1384 | TX_MACRO_DAPM_MUX("TX DMIC MUX3", 0, tx_dmic3), |
| 1385 | |
| 1386 | TX_MACRO_DAPM_MUX("TX SMIC MUX0", 0, tx_smic0_v2), |
| 1387 | TX_MACRO_DAPM_MUX("TX SMIC MUX1", 0, tx_smic1_v2), |
| 1388 | TX_MACRO_DAPM_MUX("TX SMIC MUX2", 0, tx_smic2_v2), |
| 1389 | TX_MACRO_DAPM_MUX("TX SMIC MUX3", 0, tx_smic3_v2), |
| 1390 | |
| 1391 | SND_SOC_DAPM_MICBIAS_E("TX MIC BIAS1", SND_SOC_NOPM, 0, 0, |
| 1392 | tx_macro_enable_micbias, |
| 1393 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 1394 | SND_SOC_DAPM_ADC_E("TX DMIC0", NULL, SND_SOC_NOPM, 0, 0, |
| 1395 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1396 | SND_SOC_DAPM_POST_PMD), |
| 1397 | |
| 1398 | SND_SOC_DAPM_ADC_E("TX DMIC1", NULL, SND_SOC_NOPM, 0, 0, |
| 1399 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1400 | SND_SOC_DAPM_POST_PMD), |
| 1401 | |
| 1402 | SND_SOC_DAPM_ADC_E("TX DMIC2", NULL, SND_SOC_NOPM, 0, 0, |
| 1403 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1404 | SND_SOC_DAPM_POST_PMD), |
| 1405 | |
| 1406 | SND_SOC_DAPM_ADC_E("TX DMIC3", NULL, SND_SOC_NOPM, 0, 0, |
| 1407 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1408 | SND_SOC_DAPM_POST_PMD), |
| 1409 | |
| 1410 | SND_SOC_DAPM_ADC_E("TX DMIC4", NULL, SND_SOC_NOPM, 0, 0, |
| 1411 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1412 | SND_SOC_DAPM_POST_PMD), |
| 1413 | |
| 1414 | SND_SOC_DAPM_ADC_E("TX DMIC5", NULL, SND_SOC_NOPM, 0, 0, |
| 1415 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1416 | SND_SOC_DAPM_POST_PMD), |
| 1417 | |
| 1418 | SND_SOC_DAPM_ADC_E("TX DMIC6", NULL, SND_SOC_NOPM, 0, 0, |
| 1419 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1420 | SND_SOC_DAPM_POST_PMD), |
| 1421 | |
| 1422 | SND_SOC_DAPM_ADC_E("TX DMIC7", NULL, SND_SOC_NOPM, 0, 0, |
| 1423 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1424 | SND_SOC_DAPM_POST_PMD), |
| 1425 | |
| 1426 | SND_SOC_DAPM_INPUT("TX SWR_MIC0"), |
| 1427 | SND_SOC_DAPM_INPUT("TX SWR_MIC1"), |
| 1428 | SND_SOC_DAPM_INPUT("TX SWR_MIC2"), |
| 1429 | SND_SOC_DAPM_INPUT("TX SWR_MIC3"), |
| 1430 | SND_SOC_DAPM_INPUT("TX SWR_MIC4"), |
| 1431 | SND_SOC_DAPM_INPUT("TX SWR_MIC5"), |
| 1432 | SND_SOC_DAPM_INPUT("TX SWR_MIC6"), |
| 1433 | SND_SOC_DAPM_INPUT("TX SWR_MIC7"), |
| 1434 | SND_SOC_DAPM_INPUT("TX SWR_MIC8"), |
| 1435 | SND_SOC_DAPM_INPUT("TX SWR_MIC9"), |
| 1436 | SND_SOC_DAPM_INPUT("TX SWR_MIC10"), |
| 1437 | SND_SOC_DAPM_INPUT("TX SWR_MIC11"), |
| 1438 | |
| 1439 | SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM, |
| 1440 | TX_MACRO_DEC0, 0, |
| 1441 | &tx_dec0_mux, tx_macro_enable_dec, |
| 1442 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1443 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1444 | |
| 1445 | SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM, |
| 1446 | TX_MACRO_DEC1, 0, |
| 1447 | &tx_dec1_mux, tx_macro_enable_dec, |
| 1448 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1449 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1450 | |
| 1451 | SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM, |
| 1452 | TX_MACRO_DEC2, 0, |
| 1453 | &tx_dec2_mux, tx_macro_enable_dec, |
| 1454 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1455 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1456 | |
| 1457 | SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM, |
| 1458 | TX_MACRO_DEC3, 0, |
| 1459 | &tx_dec3_mux, tx_macro_enable_dec, |
| 1460 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1461 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1462 | |
| 1463 | SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0, |
| 1464 | tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 1465 | }; |
| 1466 | |
| 1467 | static const struct snd_soc_dapm_widget tx_macro_dapm_widgets_v2[] = { |
| 1468 | SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, |
| 1469 | TX_MACRO_AIF1_CAP, 0, |
| 1470 | tx_aif1_cap_mixer_v2, ARRAY_SIZE(tx_aif1_cap_mixer_v2)), |
| 1471 | |
| 1472 | SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, |
| 1473 | TX_MACRO_AIF2_CAP, 0, |
| 1474 | tx_aif2_cap_mixer_v2, ARRAY_SIZE(tx_aif2_cap_mixer_v2)), |
| 1475 | |
| 1476 | SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, |
| 1477 | TX_MACRO_AIF3_CAP, 0, |
| 1478 | tx_aif3_cap_mixer_v2, ARRAY_SIZE(tx_aif3_cap_mixer_v2)), |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 1479 | }; |
| 1480 | |
| 1481 | static const struct snd_soc_dapm_widget tx_macro_dapm_widgets_v3[] = { |
| 1482 | SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, |
| 1483 | TX_MACRO_AIF1_CAP, 0, |
| 1484 | tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)), |
| 1485 | |
| 1486 | SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, |
| 1487 | TX_MACRO_AIF2_CAP, 0, |
| 1488 | tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)), |
| 1489 | |
| 1490 | SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, |
| 1491 | TX_MACRO_AIF3_CAP, 0, |
| 1492 | tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)), |
| 1493 | |
| 1494 | TX_MACRO_DAPM_MUX("TX DMIC MUX4", 0, tx_dmic4), |
| 1495 | TX_MACRO_DAPM_MUX("TX DMIC MUX5", 0, tx_dmic5), |
| 1496 | TX_MACRO_DAPM_MUX("TX DMIC MUX6", 0, tx_dmic6), |
| 1497 | TX_MACRO_DAPM_MUX("TX DMIC MUX7", 0, tx_dmic7), |
| 1498 | |
| 1499 | TX_MACRO_DAPM_MUX("TX SMIC MUX4", 0, tx_smic4_v3), |
| 1500 | TX_MACRO_DAPM_MUX("TX SMIC MUX5", 0, tx_smic5_v3), |
| 1501 | TX_MACRO_DAPM_MUX("TX SMIC MUX6", 0, tx_smic6_v3), |
| 1502 | TX_MACRO_DAPM_MUX("TX SMIC MUX7", 0, tx_smic7_v3), |
| 1503 | |
| 1504 | SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM, |
| 1505 | TX_MACRO_DEC4, 0, |
| 1506 | &tx_dec4_mux, tx_macro_enable_dec, |
| 1507 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1508 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1509 | |
| 1510 | SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM, |
| 1511 | TX_MACRO_DEC5, 0, |
| 1512 | &tx_dec5_mux, tx_macro_enable_dec, |
| 1513 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1514 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1515 | |
| 1516 | SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM, |
| 1517 | TX_MACRO_DEC6, 0, |
| 1518 | &tx_dec6_mux, tx_macro_enable_dec, |
| 1519 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1520 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1521 | |
| 1522 | SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM, |
| 1523 | TX_MACRO_DEC7, 0, |
| 1524 | &tx_dec7_mux, tx_macro_enable_dec, |
| 1525 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1526 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1527 | |
Laxminath Kasam | b03e82d | 2019-11-05 13:35:01 +0530 | [diff] [blame] | 1528 | SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, |
| 1529 | tx_macro_tx_swr_clk_event, |
| 1530 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 1531 | |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 1532 | SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, |
| 1533 | tx_macro_va_swr_clk_event, |
| 1534 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 1535 | }; |
| 1536 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1537 | static const struct snd_soc_dapm_widget tx_macro_dapm_widgets[] = { |
| 1538 | SND_SOC_DAPM_AIF_OUT("TX_AIF1 CAP", "TX_AIF1 Capture", 0, |
| 1539 | SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0), |
| 1540 | |
| 1541 | SND_SOC_DAPM_AIF_OUT("TX_AIF2 CAP", "TX_AIF2 Capture", 0, |
| 1542 | SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0), |
| 1543 | |
Karthikeyan Mani | f3bb818 | 2019-07-11 14:38:54 -0700 | [diff] [blame] | 1544 | SND_SOC_DAPM_AIF_OUT("TX_AIF3 CAP", "TX_AIF3 Capture", 0, |
| 1545 | SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0), |
| 1546 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1547 | SND_SOC_DAPM_MIXER("TX_AIF1_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF1_CAP, 0, |
| 1548 | tx_aif1_cap_mixer, ARRAY_SIZE(tx_aif1_cap_mixer)), |
| 1549 | |
| 1550 | SND_SOC_DAPM_MIXER("TX_AIF2_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF2_CAP, 0, |
| 1551 | tx_aif2_cap_mixer, ARRAY_SIZE(tx_aif2_cap_mixer)), |
| 1552 | |
Karthikeyan Mani | f3bb818 | 2019-07-11 14:38:54 -0700 | [diff] [blame] | 1553 | SND_SOC_DAPM_MIXER("TX_AIF3_CAP Mixer", SND_SOC_NOPM, TX_MACRO_AIF3_CAP, 0, |
| 1554 | tx_aif3_cap_mixer, ARRAY_SIZE(tx_aif3_cap_mixer)), |
| 1555 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1556 | |
| 1557 | TX_MACRO_DAPM_MUX("TX DMIC MUX0", 0, tx_dmic0), |
| 1558 | TX_MACRO_DAPM_MUX("TX DMIC MUX1", 0, tx_dmic1), |
| 1559 | TX_MACRO_DAPM_MUX("TX DMIC MUX2", 0, tx_dmic2), |
| 1560 | TX_MACRO_DAPM_MUX("TX DMIC MUX3", 0, tx_dmic3), |
| 1561 | TX_MACRO_DAPM_MUX("TX DMIC MUX4", 0, tx_dmic4), |
| 1562 | TX_MACRO_DAPM_MUX("TX DMIC MUX5", 0, tx_dmic5), |
| 1563 | TX_MACRO_DAPM_MUX("TX DMIC MUX6", 0, tx_dmic6), |
| 1564 | TX_MACRO_DAPM_MUX("TX DMIC MUX7", 0, tx_dmic7), |
| 1565 | |
| 1566 | TX_MACRO_DAPM_MUX("TX SMIC MUX0", 0, tx_smic0), |
| 1567 | TX_MACRO_DAPM_MUX("TX SMIC MUX1", 0, tx_smic1), |
| 1568 | TX_MACRO_DAPM_MUX("TX SMIC MUX2", 0, tx_smic2), |
| 1569 | TX_MACRO_DAPM_MUX("TX SMIC MUX3", 0, tx_smic3), |
| 1570 | TX_MACRO_DAPM_MUX("TX SMIC MUX4", 0, tx_smic4), |
| 1571 | TX_MACRO_DAPM_MUX("TX SMIC MUX5", 0, tx_smic5), |
| 1572 | TX_MACRO_DAPM_MUX("TX SMIC MUX6", 0, tx_smic6), |
| 1573 | TX_MACRO_DAPM_MUX("TX SMIC MUX7", 0, tx_smic7), |
| 1574 | |
| 1575 | SND_SOC_DAPM_MICBIAS_E("TX MIC BIAS1", SND_SOC_NOPM, 0, 0, |
| 1576 | tx_macro_enable_micbias, |
| 1577 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 1578 | SND_SOC_DAPM_ADC_E("TX DMIC0", NULL, SND_SOC_NOPM, 0, 0, |
| 1579 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1580 | SND_SOC_DAPM_POST_PMD), |
| 1581 | |
| 1582 | SND_SOC_DAPM_ADC_E("TX DMIC1", NULL, SND_SOC_NOPM, 0, 0, |
| 1583 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1584 | SND_SOC_DAPM_POST_PMD), |
| 1585 | |
| 1586 | SND_SOC_DAPM_ADC_E("TX DMIC2", NULL, SND_SOC_NOPM, 0, 0, |
| 1587 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1588 | SND_SOC_DAPM_POST_PMD), |
| 1589 | |
| 1590 | SND_SOC_DAPM_ADC_E("TX DMIC3", NULL, SND_SOC_NOPM, 0, 0, |
| 1591 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1592 | SND_SOC_DAPM_POST_PMD), |
| 1593 | |
| 1594 | SND_SOC_DAPM_ADC_E("TX DMIC4", NULL, SND_SOC_NOPM, 0, 0, |
| 1595 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1596 | SND_SOC_DAPM_POST_PMD), |
| 1597 | |
| 1598 | SND_SOC_DAPM_ADC_E("TX DMIC5", NULL, SND_SOC_NOPM, 0, 0, |
| 1599 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1600 | SND_SOC_DAPM_POST_PMD), |
| 1601 | |
| 1602 | SND_SOC_DAPM_ADC_E("TX DMIC6", NULL, SND_SOC_NOPM, 0, 0, |
| 1603 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1604 | SND_SOC_DAPM_POST_PMD), |
| 1605 | |
| 1606 | SND_SOC_DAPM_ADC_E("TX DMIC7", NULL, SND_SOC_NOPM, 0, 0, |
| 1607 | tx_macro_enable_dmic, SND_SOC_DAPM_PRE_PMU | |
| 1608 | SND_SOC_DAPM_POST_PMD), |
| 1609 | |
| 1610 | SND_SOC_DAPM_INPUT("TX SWR_ADC0"), |
| 1611 | SND_SOC_DAPM_INPUT("TX SWR_ADC1"), |
| 1612 | SND_SOC_DAPM_INPUT("TX SWR_ADC2"), |
| 1613 | SND_SOC_DAPM_INPUT("TX SWR_ADC3"), |
| 1614 | SND_SOC_DAPM_INPUT("TX SWR_DMIC0"), |
| 1615 | SND_SOC_DAPM_INPUT("TX SWR_DMIC1"), |
| 1616 | SND_SOC_DAPM_INPUT("TX SWR_DMIC2"), |
| 1617 | SND_SOC_DAPM_INPUT("TX SWR_DMIC3"), |
| 1618 | SND_SOC_DAPM_INPUT("TX SWR_DMIC4"), |
| 1619 | SND_SOC_DAPM_INPUT("TX SWR_DMIC5"), |
| 1620 | SND_SOC_DAPM_INPUT("TX SWR_DMIC6"), |
| 1621 | SND_SOC_DAPM_INPUT("TX SWR_DMIC7"), |
| 1622 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1623 | SND_SOC_DAPM_MUX_E("TX DEC0 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1624 | TX_MACRO_DEC0, 0, |
| 1625 | &tx_dec0_mux, tx_macro_enable_dec, |
| 1626 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1627 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1628 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1629 | SND_SOC_DAPM_MUX_E("TX DEC1 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1630 | TX_MACRO_DEC1, 0, |
| 1631 | &tx_dec1_mux, tx_macro_enable_dec, |
| 1632 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1633 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1634 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1635 | SND_SOC_DAPM_MUX_E("TX DEC2 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1636 | TX_MACRO_DEC2, 0, |
| 1637 | &tx_dec2_mux, tx_macro_enable_dec, |
| 1638 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1639 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1640 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1641 | SND_SOC_DAPM_MUX_E("TX DEC3 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1642 | TX_MACRO_DEC3, 0, |
| 1643 | &tx_dec3_mux, tx_macro_enable_dec, |
| 1644 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1645 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1646 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1647 | SND_SOC_DAPM_MUX_E("TX DEC4 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1648 | TX_MACRO_DEC4, 0, |
| 1649 | &tx_dec4_mux, tx_macro_enable_dec, |
| 1650 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1651 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1652 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1653 | SND_SOC_DAPM_MUX_E("TX DEC5 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1654 | TX_MACRO_DEC5, 0, |
| 1655 | &tx_dec5_mux, tx_macro_enable_dec, |
| 1656 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1657 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1658 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1659 | SND_SOC_DAPM_MUX_E("TX DEC6 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1660 | TX_MACRO_DEC6, 0, |
| 1661 | &tx_dec6_mux, tx_macro_enable_dec, |
| 1662 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1663 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1664 | |
Ramprasad Katkam | f83acfb | 2018-08-11 23:28:57 +0530 | [diff] [blame] | 1665 | SND_SOC_DAPM_MUX_E("TX DEC7 MUX", SND_SOC_NOPM, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1666 | TX_MACRO_DEC7, 0, |
| 1667 | &tx_dec7_mux, tx_macro_enable_dec, |
| 1668 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
| 1669 | SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
| 1670 | |
| 1671 | SND_SOC_DAPM_SUPPLY_S("TX_MCLK", 0, SND_SOC_NOPM, 0, 0, |
| 1672 | tx_macro_mclk_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
Sudheer Papothi | e456c2c | 2019-03-05 07:08:45 +0530 | [diff] [blame] | 1673 | |
| 1674 | SND_SOC_DAPM_SUPPLY_S("TX_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, |
| 1675 | tx_macro_tx_swr_clk_event, |
| 1676 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
| 1677 | |
| 1678 | SND_SOC_DAPM_SUPPLY_S("VA_SWR_CLK", 0, SND_SOC_NOPM, 0, 0, |
| 1679 | tx_macro_va_swr_clk_event, |
| 1680 | SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1681 | }; |
| 1682 | |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 1683 | static const struct snd_soc_dapm_route tx_audio_map_common[] = { |
| 1684 | {"TX_AIF1 CAP", NULL, "TX_MCLK"}, |
| 1685 | {"TX_AIF2 CAP", NULL, "TX_MCLK"}, |
| 1686 | {"TX_AIF3 CAP", NULL, "TX_MCLK"}, |
| 1687 | |
| 1688 | {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"}, |
| 1689 | {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"}, |
| 1690 | {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"}, |
| 1691 | |
| 1692 | {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"}, |
| 1693 | {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"}, |
| 1694 | {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"}, |
| 1695 | {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"}, |
| 1696 | |
| 1697 | {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"}, |
| 1698 | {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"}, |
| 1699 | {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"}, |
| 1700 | {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"}, |
| 1701 | |
| 1702 | {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"}, |
| 1703 | {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"}, |
| 1704 | {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"}, |
| 1705 | {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"}, |
| 1706 | |
| 1707 | {"TX DEC0 MUX", NULL, "TX_MCLK"}, |
| 1708 | {"TX DEC1 MUX", NULL, "TX_MCLK"}, |
| 1709 | {"TX DEC2 MUX", NULL, "TX_MCLK"}, |
| 1710 | {"TX DEC3 MUX", NULL, "TX_MCLK"}, |
| 1711 | |
| 1712 | {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"}, |
| 1713 | {"TX DMIC MUX0", "DMIC0", "TX DMIC0"}, |
| 1714 | {"TX DMIC MUX0", "DMIC1", "TX DMIC1"}, |
| 1715 | {"TX DMIC MUX0", "DMIC2", "TX DMIC2"}, |
| 1716 | {"TX DMIC MUX0", "DMIC3", "TX DMIC3"}, |
| 1717 | {"TX DMIC MUX0", "DMIC4", "TX DMIC4"}, |
| 1718 | {"TX DMIC MUX0", "DMIC5", "TX DMIC5"}, |
| 1719 | {"TX DMIC MUX0", "DMIC6", "TX DMIC6"}, |
| 1720 | {"TX DMIC MUX0", "DMIC7", "TX DMIC7"}, |
| 1721 | |
| 1722 | {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, |
| 1723 | {"TX SMIC MUX0", "SWR_MIC0", "TX SWR_MIC0"}, |
| 1724 | {"TX SMIC MUX0", "SWR_MIC1", "TX SWR_MIC1"}, |
| 1725 | {"TX SMIC MUX0", "SWR_MIC2", "TX SWR_MIC2"}, |
| 1726 | {"TX SMIC MUX0", "SWR_MIC3", "TX SWR_MIC3"}, |
| 1727 | {"TX SMIC MUX0", "SWR_MIC4", "TX SWR_MIC4"}, |
| 1728 | {"TX SMIC MUX0", "SWR_MIC5", "TX SWR_MIC5"}, |
| 1729 | {"TX SMIC MUX0", "SWR_MIC6", "TX SWR_MIC6"}, |
| 1730 | {"TX SMIC MUX0", "SWR_MIC7", "TX SWR_MIC7"}, |
| 1731 | {"TX SMIC MUX0", "SWR_MIC8", "TX SWR_MIC8"}, |
| 1732 | {"TX SMIC MUX0", "SWR_MIC9", "TX SWR_MIC9"}, |
| 1733 | {"TX SMIC MUX0", "SWR_MIC10", "TX SWR_MIC10"}, |
| 1734 | {"TX SMIC MUX0", "SWR_MIC11", "TX SWR_MIC11"}, |
| 1735 | |
| 1736 | {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"}, |
| 1737 | {"TX DMIC MUX1", "DMIC0", "TX DMIC0"}, |
| 1738 | {"TX DMIC MUX1", "DMIC1", "TX DMIC1"}, |
| 1739 | {"TX DMIC MUX1", "DMIC2", "TX DMIC2"}, |
| 1740 | {"TX DMIC MUX1", "DMIC3", "TX DMIC3"}, |
| 1741 | {"TX DMIC MUX1", "DMIC4", "TX DMIC4"}, |
| 1742 | {"TX DMIC MUX1", "DMIC5", "TX DMIC5"}, |
| 1743 | {"TX DMIC MUX1", "DMIC6", "TX DMIC6"}, |
| 1744 | {"TX DMIC MUX1", "DMIC7", "TX DMIC7"}, |
| 1745 | |
| 1746 | {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, |
| 1747 | {"TX SMIC MUX1", "SWR_MIC0", "TX SWR_MIC0"}, |
| 1748 | {"TX SMIC MUX1", "SWR_MIC1", "TX SWR_MIC1"}, |
| 1749 | {"TX SMIC MUX1", "SWR_MIC2", "TX SWR_MIC2"}, |
| 1750 | {"TX SMIC MUX1", "SWR_MIC3", "TX SWR_MIC3"}, |
| 1751 | {"TX SMIC MUX1", "SWR_MIC4", "TX SWR_MIC4"}, |
| 1752 | {"TX SMIC MUX1", "SWR_MIC5", "TX SWR_MIC5"}, |
| 1753 | {"TX SMIC MUX1", "SWR_MIC6", "TX SWR_MIC6"}, |
| 1754 | {"TX SMIC MUX1", "SWR_MIC7", "TX SWR_MIC7"}, |
| 1755 | {"TX SMIC MUX1", "SWR_MIC8", "TX SWR_MIC8"}, |
| 1756 | {"TX SMIC MUX1", "SWR_MIC9", "TX SWR_MIC9"}, |
| 1757 | {"TX SMIC MUX1", "SWR_MIC10", "TX SWR_MIC10"}, |
| 1758 | {"TX SMIC MUX1", "SWR_MIC11", "TX SWR_MIC11"}, |
| 1759 | |
| 1760 | {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"}, |
| 1761 | {"TX DMIC MUX2", "DMIC0", "TX DMIC0"}, |
| 1762 | {"TX DMIC MUX2", "DMIC1", "TX DMIC1"}, |
| 1763 | {"TX DMIC MUX2", "DMIC2", "TX DMIC2"}, |
| 1764 | {"TX DMIC MUX2", "DMIC3", "TX DMIC3"}, |
| 1765 | {"TX DMIC MUX2", "DMIC4", "TX DMIC4"}, |
| 1766 | {"TX DMIC MUX2", "DMIC5", "TX DMIC5"}, |
| 1767 | {"TX DMIC MUX2", "DMIC6", "TX DMIC6"}, |
| 1768 | {"TX DMIC MUX2", "DMIC7", "TX DMIC7"}, |
| 1769 | |
| 1770 | {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, |
| 1771 | {"TX SMIC MUX2", "SWR_MIC0", "TX SWR_MIC0"}, |
| 1772 | {"TX SMIC MUX2", "SWR_MIC1", "TX SWR_MIC1"}, |
| 1773 | {"TX SMIC MUX2", "SWR_MIC2", "TX SWR_MIC2"}, |
| 1774 | {"TX SMIC MUX2", "SWR_MIC3", "TX SWR_MIC3"}, |
| 1775 | {"TX SMIC MUX2", "SWR_MIC4", "TX SWR_MIC4"}, |
| 1776 | {"TX SMIC MUX2", "SWR_MIC5", "TX SWR_MIC5"}, |
| 1777 | {"TX SMIC MUX2", "SWR_MIC6", "TX SWR_MIC6"}, |
| 1778 | {"TX SMIC MUX2", "SWR_MIC7", "TX SWR_MIC7"}, |
| 1779 | {"TX SMIC MUX2", "SWR_MIC8", "TX SWR_MIC8"}, |
| 1780 | {"TX SMIC MUX2", "SWR_MIC9", "TX SWR_MIC9"}, |
| 1781 | {"TX SMIC MUX2", "SWR_MIC10", "TX SWR_MIC10"}, |
| 1782 | {"TX SMIC MUX2", "SWR_MIC11", "TX SWR_MIC11"}, |
| 1783 | |
| 1784 | {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"}, |
| 1785 | {"TX DMIC MUX3", "DMIC0", "TX DMIC0"}, |
| 1786 | {"TX DMIC MUX3", "DMIC1", "TX DMIC1"}, |
| 1787 | {"TX DMIC MUX3", "DMIC2", "TX DMIC2"}, |
| 1788 | {"TX DMIC MUX3", "DMIC3", "TX DMIC3"}, |
| 1789 | {"TX DMIC MUX3", "DMIC4", "TX DMIC4"}, |
| 1790 | {"TX DMIC MUX3", "DMIC5", "TX DMIC5"}, |
| 1791 | {"TX DMIC MUX3", "DMIC6", "TX DMIC6"}, |
| 1792 | {"TX DMIC MUX3", "DMIC7", "TX DMIC7"}, |
| 1793 | |
| 1794 | {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, |
| 1795 | {"TX SMIC MUX3", "SWR_MIC0", "TX SWR_MIC0"}, |
| 1796 | {"TX SMIC MUX3", "SWR_MIC1", "TX SWR_MIC1"}, |
| 1797 | {"TX SMIC MUX3", "SWR_MIC2", "TX SWR_MIC2"}, |
| 1798 | {"TX SMIC MUX3", "SWR_MIC3", "TX SWR_MIC3"}, |
| 1799 | {"TX SMIC MUX3", "SWR_MIC4", "TX SWR_MIC4"}, |
| 1800 | {"TX SMIC MUX3", "SWR_MIC5", "TX SWR_MIC5"}, |
| 1801 | {"TX SMIC MUX3", "SWR_MIC6", "TX SWR_MIC6"}, |
| 1802 | {"TX SMIC MUX3", "SWR_MIC7", "TX SWR_MIC7"}, |
| 1803 | {"TX SMIC MUX3", "SWR_MIC8", "TX SWR_MIC8"}, |
| 1804 | {"TX SMIC MUX3", "SWR_MIC9", "TX SWR_MIC9"}, |
| 1805 | {"TX SMIC MUX3", "SWR_MIC10", "TX SWR_MIC10"}, |
| 1806 | {"TX SMIC MUX3", "SWR_MIC11", "TX SWR_MIC11"}, |
| 1807 | }; |
| 1808 | |
| 1809 | static const struct snd_soc_dapm_route tx_audio_map_v3[] = { |
| 1810 | {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"}, |
| 1811 | {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"}, |
| 1812 | {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"}, |
| 1813 | {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"}, |
| 1814 | |
| 1815 | {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"}, |
| 1816 | {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"}, |
| 1817 | {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"}, |
| 1818 | {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"}, |
| 1819 | |
| 1820 | {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"}, |
| 1821 | {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"}, |
| 1822 | {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"}, |
| 1823 | {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"}, |
| 1824 | |
| 1825 | {"TX DEC4 MUX", NULL, "TX_MCLK"}, |
| 1826 | {"TX DEC5 MUX", NULL, "TX_MCLK"}, |
| 1827 | {"TX DEC6 MUX", NULL, "TX_MCLK"}, |
| 1828 | {"TX DEC7 MUX", NULL, "TX_MCLK"}, |
| 1829 | |
| 1830 | {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"}, |
| 1831 | {"TX DMIC MUX4", "DMIC0", "TX DMIC0"}, |
| 1832 | {"TX DMIC MUX4", "DMIC1", "TX DMIC1"}, |
| 1833 | {"TX DMIC MUX4", "DMIC2", "TX DMIC2"}, |
| 1834 | {"TX DMIC MUX4", "DMIC3", "TX DMIC3"}, |
| 1835 | {"TX DMIC MUX4", "DMIC4", "TX DMIC4"}, |
| 1836 | {"TX DMIC MUX4", "DMIC5", "TX DMIC5"}, |
| 1837 | {"TX DMIC MUX4", "DMIC6", "TX DMIC6"}, |
| 1838 | {"TX DMIC MUX4", "DMIC7", "TX DMIC7"}, |
| 1839 | |
| 1840 | {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, |
| 1841 | {"TX SMIC MUX4", "SWR_MIC0", "TX SWR_MIC0"}, |
| 1842 | {"TX SMIC MUX4", "SWR_MIC1", "TX SWR_MIC1"}, |
| 1843 | {"TX SMIC MUX4", "SWR_MIC2", "TX SWR_MIC2"}, |
| 1844 | {"TX SMIC MUX4", "SWR_MIC3", "TX SWR_MIC3"}, |
| 1845 | {"TX SMIC MUX4", "SWR_MIC4", "TX SWR_MIC4"}, |
| 1846 | {"TX SMIC MUX4", "SWR_MIC5", "TX SWR_MIC5"}, |
| 1847 | {"TX SMIC MUX4", "SWR_MIC6", "TX SWR_MIC6"}, |
| 1848 | {"TX SMIC MUX4", "SWR_MIC7", "TX SWR_MIC7"}, |
| 1849 | {"TX SMIC MUX4", "SWR_MIC8", "TX SWR_MIC8"}, |
| 1850 | {"TX SMIC MUX4", "SWR_MIC9", "TX SWR_MIC9"}, |
| 1851 | {"TX SMIC MUX4", "SWR_MIC10", "TX SWR_MIC10"}, |
| 1852 | {"TX SMIC MUX4", "SWR_MIC11", "TX SWR_MIC11"}, |
| 1853 | |
| 1854 | {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"}, |
| 1855 | {"TX DMIC MUX5", "DMIC0", "TX DMIC0"}, |
| 1856 | {"TX DMIC MUX5", "DMIC1", "TX DMIC1"}, |
| 1857 | {"TX DMIC MUX5", "DMIC2", "TX DMIC2"}, |
| 1858 | {"TX DMIC MUX5", "DMIC3", "TX DMIC3"}, |
| 1859 | {"TX DMIC MUX5", "DMIC4", "TX DMIC4"}, |
| 1860 | {"TX DMIC MUX5", "DMIC5", "TX DMIC5"}, |
| 1861 | {"TX DMIC MUX5", "DMIC6", "TX DMIC6"}, |
| 1862 | {"TX DMIC MUX5", "DMIC7", "TX DMIC7"}, |
| 1863 | |
| 1864 | {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, |
| 1865 | {"TX SMIC MUX5", "SWR_MIC0", "TX SWR_MIC0"}, |
| 1866 | {"TX SMIC MUX5", "SWR_MIC1", "TX SWR_MIC1"}, |
| 1867 | {"TX SMIC MUX5", "SWR_MIC2", "TX SWR_MIC2"}, |
| 1868 | {"TX SMIC MUX5", "SWR_MIC3", "TX SWR_MIC3"}, |
| 1869 | {"TX SMIC MUX5", "SWR_MIC4", "TX SWR_MIC4"}, |
| 1870 | {"TX SMIC MUX5", "SWR_MIC5", "TX SWR_MIC5"}, |
| 1871 | {"TX SMIC MUX5", "SWR_MIC6", "TX SWR_MIC6"}, |
| 1872 | {"TX SMIC MUX5", "SWR_MIC7", "TX SWR_MIC7"}, |
| 1873 | {"TX SMIC MUX5", "SWR_MIC8", "TX SWR_MIC8"}, |
| 1874 | {"TX SMIC MUX5", "SWR_MIC9", "TX SWR_MIC9"}, |
| 1875 | {"TX SMIC MUX5", "SWR_MIC10", "TX SWR_MIC10"}, |
| 1876 | {"TX SMIC MUX5", "SWR_MIC11", "TX SWR_MIC11"}, |
| 1877 | |
| 1878 | {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"}, |
| 1879 | {"TX DMIC MUX6", "DMIC0", "TX DMIC0"}, |
| 1880 | {"TX DMIC MUX6", "DMIC1", "TX DMIC1"}, |
| 1881 | {"TX DMIC MUX6", "DMIC2", "TX DMIC2"}, |
| 1882 | {"TX DMIC MUX6", "DMIC3", "TX DMIC3"}, |
| 1883 | {"TX DMIC MUX6", "DMIC4", "TX DMIC4"}, |
| 1884 | {"TX DMIC MUX6", "DMIC5", "TX DMIC5"}, |
| 1885 | {"TX DMIC MUX6", "DMIC6", "TX DMIC6"}, |
| 1886 | {"TX DMIC MUX6", "DMIC7", "TX DMIC7"}, |
| 1887 | |
| 1888 | {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, |
| 1889 | {"TX SMIC MUX6", "SWR_MIC0", "TX SWR_MIC0"}, |
| 1890 | {"TX SMIC MUX6", "SWR_MIC1", "TX SWR_MIC1"}, |
| 1891 | {"TX SMIC MUX6", "SWR_MIC2", "TX SWR_MIC2"}, |
| 1892 | {"TX SMIC MUX6", "SWR_MIC3", "TX SWR_MIC3"}, |
| 1893 | {"TX SMIC MUX6", "SWR_MIC4", "TX SWR_MIC4"}, |
| 1894 | {"TX SMIC MUX6", "SWR_MIC5", "TX SWR_MIC5"}, |
| 1895 | {"TX SMIC MUX6", "SWR_MIC6", "TX SWR_MIC6"}, |
| 1896 | {"TX SMIC MUX6", "SWR_MIC7", "TX SWR_MIC7"}, |
| 1897 | {"TX SMIC MUX6", "SWR_MIC8", "TX SWR_MIC8"}, |
| 1898 | {"TX SMIC MUX6", "SWR_MIC9", "TX SWR_MIC9"}, |
| 1899 | {"TX SMIC MUX6", "SWR_MIC10", "TX SWR_MIC10"}, |
| 1900 | {"TX SMIC MUX6", "SWR_MIC11", "TX SWR_MIC11"}, |
| 1901 | |
| 1902 | {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"}, |
| 1903 | {"TX DMIC MUX7", "DMIC0", "TX DMIC0"}, |
| 1904 | {"TX DMIC MUX7", "DMIC1", "TX DMIC1"}, |
| 1905 | {"TX DMIC MUX7", "DMIC2", "TX DMIC2"}, |
| 1906 | {"TX DMIC MUX7", "DMIC3", "TX DMIC3"}, |
| 1907 | {"TX DMIC MUX7", "DMIC4", "TX DMIC4"}, |
| 1908 | {"TX DMIC MUX7", "DMIC5", "TX DMIC5"}, |
| 1909 | {"TX DMIC MUX7", "DMIC6", "TX DMIC6"}, |
| 1910 | {"TX DMIC MUX7", "DMIC7", "TX DMIC7"}, |
| 1911 | |
| 1912 | {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, |
| 1913 | {"TX SMIC MUX7", "SWR_MIC0", "TX SWR_MIC0"}, |
| 1914 | {"TX SMIC MUX7", "SWR_MIC1", "TX SWR_MIC1"}, |
| 1915 | {"TX SMIC MUX7", "SWR_MIC2", "TX SWR_MIC2"}, |
| 1916 | {"TX SMIC MUX7", "SWR_MIC3", "TX SWR_MIC3"}, |
| 1917 | {"TX SMIC MUX7", "SWR_MIC4", "TX SWR_MIC4"}, |
| 1918 | {"TX SMIC MUX7", "SWR_MIC5", "TX SWR_MIC5"}, |
| 1919 | {"TX SMIC MUX7", "SWR_MIC6", "TX SWR_MIC6"}, |
| 1920 | {"TX SMIC MUX7", "SWR_MIC7", "TX SWR_MIC7"}, |
| 1921 | {"TX SMIC MUX7", "SWR_MIC8", "TX SWR_MIC8"}, |
| 1922 | {"TX SMIC MUX7", "SWR_MIC9", "TX SWR_MIC9"}, |
| 1923 | {"TX SMIC MUX7", "SWR_MIC10", "TX SWR_MIC10"}, |
| 1924 | {"TX SMIC MUX7", "SWR_MIC11", "TX SWR_MIC11"}, |
Laxminath Kasam | b03e82d | 2019-11-05 13:35:01 +0530 | [diff] [blame] | 1925 | |
| 1926 | {"TX SMIC MUX0", NULL, "TX_SWR_CLK"}, |
| 1927 | {"TX SMIC MUX1", NULL, "TX_SWR_CLK"}, |
| 1928 | {"TX SMIC MUX2", NULL, "TX_SWR_CLK"}, |
| 1929 | {"TX SMIC MUX3", NULL, "TX_SWR_CLK"}, |
| 1930 | {"TX SMIC MUX4", NULL, "TX_SWR_CLK"}, |
| 1931 | {"TX SMIC MUX5", NULL, "TX_SWR_CLK"}, |
| 1932 | {"TX SMIC MUX6", NULL, "TX_SWR_CLK"}, |
| 1933 | {"TX SMIC MUX7", NULL, "TX_SWR_CLK"}, |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 1934 | }; |
| 1935 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1936 | static const struct snd_soc_dapm_route tx_audio_map[] = { |
| 1937 | {"TX_AIF1 CAP", NULL, "TX_MCLK"}, |
| 1938 | {"TX_AIF2 CAP", NULL, "TX_MCLK"}, |
Karthikeyan Mani | f3bb818 | 2019-07-11 14:38:54 -0700 | [diff] [blame] | 1939 | {"TX_AIF3 CAP", NULL, "TX_MCLK"}, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1940 | |
| 1941 | {"TX_AIF1 CAP", NULL, "TX_AIF1_CAP Mixer"}, |
| 1942 | {"TX_AIF2 CAP", NULL, "TX_AIF2_CAP Mixer"}, |
Karthikeyan Mani | f3bb818 | 2019-07-11 14:38:54 -0700 | [diff] [blame] | 1943 | {"TX_AIF3 CAP", NULL, "TX_AIF3_CAP Mixer"}, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1944 | |
| 1945 | {"TX_AIF1_CAP Mixer", "DEC0", "TX DEC0 MUX"}, |
| 1946 | {"TX_AIF1_CAP Mixer", "DEC1", "TX DEC1 MUX"}, |
| 1947 | {"TX_AIF1_CAP Mixer", "DEC2", "TX DEC2 MUX"}, |
| 1948 | {"TX_AIF1_CAP Mixer", "DEC3", "TX DEC3 MUX"}, |
| 1949 | {"TX_AIF1_CAP Mixer", "DEC4", "TX DEC4 MUX"}, |
| 1950 | {"TX_AIF1_CAP Mixer", "DEC5", "TX DEC5 MUX"}, |
| 1951 | {"TX_AIF1_CAP Mixer", "DEC6", "TX DEC6 MUX"}, |
| 1952 | {"TX_AIF1_CAP Mixer", "DEC7", "TX DEC7 MUX"}, |
| 1953 | |
| 1954 | {"TX_AIF2_CAP Mixer", "DEC0", "TX DEC0 MUX"}, |
| 1955 | {"TX_AIF2_CAP Mixer", "DEC1", "TX DEC1 MUX"}, |
| 1956 | {"TX_AIF2_CAP Mixer", "DEC2", "TX DEC2 MUX"}, |
| 1957 | {"TX_AIF2_CAP Mixer", "DEC3", "TX DEC3 MUX"}, |
| 1958 | {"TX_AIF2_CAP Mixer", "DEC4", "TX DEC4 MUX"}, |
| 1959 | {"TX_AIF2_CAP Mixer", "DEC5", "TX DEC5 MUX"}, |
| 1960 | {"TX_AIF2_CAP Mixer", "DEC6", "TX DEC6 MUX"}, |
| 1961 | {"TX_AIF2_CAP Mixer", "DEC7", "TX DEC7 MUX"}, |
| 1962 | |
Karthikeyan Mani | f3bb818 | 2019-07-11 14:38:54 -0700 | [diff] [blame] | 1963 | {"TX_AIF3_CAP Mixer", "DEC0", "TX DEC0 MUX"}, |
| 1964 | {"TX_AIF3_CAP Mixer", "DEC1", "TX DEC1 MUX"}, |
| 1965 | {"TX_AIF3_CAP Mixer", "DEC2", "TX DEC2 MUX"}, |
| 1966 | {"TX_AIF3_CAP Mixer", "DEC3", "TX DEC3 MUX"}, |
| 1967 | {"TX_AIF3_CAP Mixer", "DEC4", "TX DEC4 MUX"}, |
| 1968 | {"TX_AIF3_CAP Mixer", "DEC5", "TX DEC5 MUX"}, |
| 1969 | {"TX_AIF3_CAP Mixer", "DEC6", "TX DEC6 MUX"}, |
| 1970 | {"TX_AIF3_CAP Mixer", "DEC7", "TX DEC7 MUX"}, |
| 1971 | |
Laxminath Kasam | fc281ad | 2018-08-06 20:19:40 +0530 | [diff] [blame] | 1972 | {"TX DEC0 MUX", NULL, "TX_MCLK"}, |
| 1973 | {"TX DEC1 MUX", NULL, "TX_MCLK"}, |
| 1974 | {"TX DEC2 MUX", NULL, "TX_MCLK"}, |
| 1975 | {"TX DEC3 MUX", NULL, "TX_MCLK"}, |
| 1976 | {"TX DEC4 MUX", NULL, "TX_MCLK"}, |
| 1977 | {"TX DEC5 MUX", NULL, "TX_MCLK"}, |
| 1978 | {"TX DEC6 MUX", NULL, "TX_MCLK"}, |
| 1979 | {"TX DEC7 MUX", NULL, "TX_MCLK"}, |
| 1980 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1981 | {"TX DEC0 MUX", "MSM_DMIC", "TX DMIC MUX0"}, |
| 1982 | {"TX DMIC MUX0", "DMIC0", "TX DMIC0"}, |
| 1983 | {"TX DMIC MUX0", "DMIC1", "TX DMIC1"}, |
| 1984 | {"TX DMIC MUX0", "DMIC2", "TX DMIC2"}, |
| 1985 | {"TX DMIC MUX0", "DMIC3", "TX DMIC3"}, |
| 1986 | {"TX DMIC MUX0", "DMIC4", "TX DMIC4"}, |
| 1987 | {"TX DMIC MUX0", "DMIC5", "TX DMIC5"}, |
| 1988 | {"TX DMIC MUX0", "DMIC6", "TX DMIC6"}, |
| 1989 | {"TX DMIC MUX0", "DMIC7", "TX DMIC7"}, |
| 1990 | |
| 1991 | {"TX DEC0 MUX", "SWR_MIC", "TX SMIC MUX0"}, |
Sudheer Papothi | e456c2c | 2019-03-05 07:08:45 +0530 | [diff] [blame] | 1992 | {"TX SMIC MUX0", NULL, "TX_SWR_CLK"}, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 1993 | {"TX SMIC MUX0", "ADC0", "TX SWR_ADC0"}, |
| 1994 | {"TX SMIC MUX0", "ADC1", "TX SWR_ADC1"}, |
| 1995 | {"TX SMIC MUX0", "ADC2", "TX SWR_ADC2"}, |
| 1996 | {"TX SMIC MUX0", "ADC3", "TX SWR_ADC3"}, |
| 1997 | {"TX SMIC MUX0", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 1998 | {"TX SMIC MUX0", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 1999 | {"TX SMIC MUX0", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 2000 | {"TX SMIC MUX0", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 2001 | {"TX SMIC MUX0", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 2002 | {"TX SMIC MUX0", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 2003 | {"TX SMIC MUX0", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 2004 | {"TX SMIC MUX0", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 2005 | |
| 2006 | {"TX DEC1 MUX", "MSM_DMIC", "TX DMIC MUX1"}, |
| 2007 | {"TX DMIC MUX1", "DMIC0", "TX DMIC0"}, |
| 2008 | {"TX DMIC MUX1", "DMIC1", "TX DMIC1"}, |
| 2009 | {"TX DMIC MUX1", "DMIC2", "TX DMIC2"}, |
| 2010 | {"TX DMIC MUX1", "DMIC3", "TX DMIC3"}, |
| 2011 | {"TX DMIC MUX1", "DMIC4", "TX DMIC4"}, |
| 2012 | {"TX DMIC MUX1", "DMIC5", "TX DMIC5"}, |
| 2013 | {"TX DMIC MUX1", "DMIC6", "TX DMIC6"}, |
| 2014 | {"TX DMIC MUX1", "DMIC7", "TX DMIC7"}, |
| 2015 | |
| 2016 | {"TX DEC1 MUX", "SWR_MIC", "TX SMIC MUX1"}, |
Sudheer Papothi | e456c2c | 2019-03-05 07:08:45 +0530 | [diff] [blame] | 2017 | {"TX SMIC MUX1", NULL, "TX_SWR_CLK"}, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2018 | {"TX SMIC MUX1", "ADC0", "TX SWR_ADC0"}, |
| 2019 | {"TX SMIC MUX1", "ADC1", "TX SWR_ADC1"}, |
| 2020 | {"TX SMIC MUX1", "ADC2", "TX SWR_ADC2"}, |
| 2021 | {"TX SMIC MUX1", "ADC3", "TX SWR_ADC3"}, |
| 2022 | {"TX SMIC MUX1", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 2023 | {"TX SMIC MUX1", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 2024 | {"TX SMIC MUX1", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 2025 | {"TX SMIC MUX1", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 2026 | {"TX SMIC MUX1", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 2027 | {"TX SMIC MUX1", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 2028 | {"TX SMIC MUX1", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 2029 | {"TX SMIC MUX1", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 2030 | |
| 2031 | {"TX DEC2 MUX", "MSM_DMIC", "TX DMIC MUX2"}, |
| 2032 | {"TX DMIC MUX2", "DMIC0", "TX DMIC0"}, |
| 2033 | {"TX DMIC MUX2", "DMIC1", "TX DMIC1"}, |
| 2034 | {"TX DMIC MUX2", "DMIC2", "TX DMIC2"}, |
| 2035 | {"TX DMIC MUX2", "DMIC3", "TX DMIC3"}, |
| 2036 | {"TX DMIC MUX2", "DMIC4", "TX DMIC4"}, |
| 2037 | {"TX DMIC MUX2", "DMIC5", "TX DMIC5"}, |
| 2038 | {"TX DMIC MUX2", "DMIC6", "TX DMIC6"}, |
| 2039 | {"TX DMIC MUX2", "DMIC7", "TX DMIC7"}, |
| 2040 | |
| 2041 | {"TX DEC2 MUX", "SWR_MIC", "TX SMIC MUX2"}, |
Sudheer Papothi | e456c2c | 2019-03-05 07:08:45 +0530 | [diff] [blame] | 2042 | {"TX SMIC MUX2", NULL, "TX_SWR_CLK"}, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2043 | {"TX SMIC MUX2", "ADC0", "TX SWR_ADC0"}, |
| 2044 | {"TX SMIC MUX2", "ADC1", "TX SWR_ADC1"}, |
| 2045 | {"TX SMIC MUX2", "ADC2", "TX SWR_ADC2"}, |
| 2046 | {"TX SMIC MUX2", "ADC3", "TX SWR_ADC3"}, |
| 2047 | {"TX SMIC MUX2", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 2048 | {"TX SMIC MUX2", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 2049 | {"TX SMIC MUX2", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 2050 | {"TX SMIC MUX2", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 2051 | {"TX SMIC MUX2", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 2052 | {"TX SMIC MUX2", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 2053 | {"TX SMIC MUX2", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 2054 | {"TX SMIC MUX2", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 2055 | |
| 2056 | {"TX DEC3 MUX", "MSM_DMIC", "TX DMIC MUX3"}, |
| 2057 | {"TX DMIC MUX3", "DMIC0", "TX DMIC0"}, |
| 2058 | {"TX DMIC MUX3", "DMIC1", "TX DMIC1"}, |
| 2059 | {"TX DMIC MUX3", "DMIC2", "TX DMIC2"}, |
| 2060 | {"TX DMIC MUX3", "DMIC3", "TX DMIC3"}, |
| 2061 | {"TX DMIC MUX3", "DMIC4", "TX DMIC4"}, |
| 2062 | {"TX DMIC MUX3", "DMIC5", "TX DMIC5"}, |
| 2063 | {"TX DMIC MUX3", "DMIC6", "TX DMIC6"}, |
| 2064 | {"TX DMIC MUX3", "DMIC7", "TX DMIC7"}, |
| 2065 | |
| 2066 | {"TX DEC3 MUX", "SWR_MIC", "TX SMIC MUX3"}, |
Sudheer Papothi | e456c2c | 2019-03-05 07:08:45 +0530 | [diff] [blame] | 2067 | {"TX SMIC MUX3", NULL, "TX_SWR_CLK"}, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2068 | {"TX SMIC MUX3", "ADC0", "TX SWR_ADC0"}, |
| 2069 | {"TX SMIC MUX3", "ADC1", "TX SWR_ADC1"}, |
| 2070 | {"TX SMIC MUX3", "ADC2", "TX SWR_ADC2"}, |
| 2071 | {"TX SMIC MUX3", "ADC3", "TX SWR_ADC3"}, |
| 2072 | {"TX SMIC MUX3", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 2073 | {"TX SMIC MUX3", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 2074 | {"TX SMIC MUX3", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 2075 | {"TX SMIC MUX3", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 2076 | {"TX SMIC MUX3", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 2077 | {"TX SMIC MUX3", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 2078 | {"TX SMIC MUX3", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 2079 | {"TX SMIC MUX3", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 2080 | |
| 2081 | {"TX DEC4 MUX", "MSM_DMIC", "TX DMIC MUX4"}, |
| 2082 | {"TX DMIC MUX4", "DMIC0", "TX DMIC0"}, |
| 2083 | {"TX DMIC MUX4", "DMIC1", "TX DMIC1"}, |
| 2084 | {"TX DMIC MUX4", "DMIC2", "TX DMIC2"}, |
| 2085 | {"TX DMIC MUX4", "DMIC3", "TX DMIC3"}, |
| 2086 | {"TX DMIC MUX4", "DMIC4", "TX DMIC4"}, |
| 2087 | {"TX DMIC MUX4", "DMIC5", "TX DMIC5"}, |
| 2088 | {"TX DMIC MUX4", "DMIC6", "TX DMIC6"}, |
| 2089 | {"TX DMIC MUX4", "DMIC7", "TX DMIC7"}, |
| 2090 | |
| 2091 | {"TX DEC4 MUX", "SWR_MIC", "TX SMIC MUX4"}, |
Sudheer Papothi | e456c2c | 2019-03-05 07:08:45 +0530 | [diff] [blame] | 2092 | {"TX SMIC MUX4", NULL, "TX_SWR_CLK"}, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2093 | {"TX SMIC MUX4", "ADC0", "TX SWR_ADC0"}, |
| 2094 | {"TX SMIC MUX4", "ADC1", "TX SWR_ADC1"}, |
| 2095 | {"TX SMIC MUX4", "ADC2", "TX SWR_ADC2"}, |
| 2096 | {"TX SMIC MUX4", "ADC3", "TX SWR_ADC3"}, |
| 2097 | {"TX SMIC MUX4", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 2098 | {"TX SMIC MUX4", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 2099 | {"TX SMIC MUX4", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 2100 | {"TX SMIC MUX4", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 2101 | {"TX SMIC MUX4", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 2102 | {"TX SMIC MUX4", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 2103 | {"TX SMIC MUX4", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 2104 | {"TX SMIC MUX4", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 2105 | |
| 2106 | {"TX DEC5 MUX", "MSM_DMIC", "TX DMIC MUX5"}, |
| 2107 | {"TX DMIC MUX5", "DMIC0", "TX DMIC0"}, |
| 2108 | {"TX DMIC MUX5", "DMIC1", "TX DMIC1"}, |
| 2109 | {"TX DMIC MUX5", "DMIC2", "TX DMIC2"}, |
| 2110 | {"TX DMIC MUX5", "DMIC3", "TX DMIC3"}, |
| 2111 | {"TX DMIC MUX5", "DMIC4", "TX DMIC4"}, |
| 2112 | {"TX DMIC MUX5", "DMIC5", "TX DMIC5"}, |
| 2113 | {"TX DMIC MUX5", "DMIC6", "TX DMIC6"}, |
| 2114 | {"TX DMIC MUX5", "DMIC7", "TX DMIC7"}, |
| 2115 | |
| 2116 | {"TX DEC5 MUX", "SWR_MIC", "TX SMIC MUX5"}, |
Sudheer Papothi | e456c2c | 2019-03-05 07:08:45 +0530 | [diff] [blame] | 2117 | {"TX SMIC MUX5", NULL, "TX_SWR_CLK"}, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2118 | {"TX SMIC MUX5", "ADC0", "TX SWR_ADC0"}, |
| 2119 | {"TX SMIC MUX5", "ADC1", "TX SWR_ADC1"}, |
| 2120 | {"TX SMIC MUX5", "ADC2", "TX SWR_ADC2"}, |
| 2121 | {"TX SMIC MUX5", "ADC3", "TX SWR_ADC3"}, |
| 2122 | {"TX SMIC MUX5", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 2123 | {"TX SMIC MUX5", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 2124 | {"TX SMIC MUX5", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 2125 | {"TX SMIC MUX5", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 2126 | {"TX SMIC MUX5", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 2127 | {"TX SMIC MUX5", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 2128 | {"TX SMIC MUX5", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 2129 | {"TX SMIC MUX5", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 2130 | |
| 2131 | {"TX DEC6 MUX", "MSM_DMIC", "TX DMIC MUX6"}, |
| 2132 | {"TX DMIC MUX6", "DMIC0", "TX DMIC0"}, |
| 2133 | {"TX DMIC MUX6", "DMIC1", "TX DMIC1"}, |
| 2134 | {"TX DMIC MUX6", "DMIC2", "TX DMIC2"}, |
| 2135 | {"TX DMIC MUX6", "DMIC3", "TX DMIC3"}, |
| 2136 | {"TX DMIC MUX6", "DMIC4", "TX DMIC4"}, |
| 2137 | {"TX DMIC MUX6", "DMIC5", "TX DMIC5"}, |
| 2138 | {"TX DMIC MUX6", "DMIC6", "TX DMIC6"}, |
| 2139 | {"TX DMIC MUX6", "DMIC7", "TX DMIC7"}, |
| 2140 | |
| 2141 | {"TX DEC6 MUX", "SWR_MIC", "TX SMIC MUX6"}, |
Sudheer Papothi | e456c2c | 2019-03-05 07:08:45 +0530 | [diff] [blame] | 2142 | {"TX SMIC MUX6", NULL, "TX_SWR_CLK"}, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2143 | {"TX SMIC MUX6", "ADC0", "TX SWR_ADC0"}, |
| 2144 | {"TX SMIC MUX6", "ADC1", "TX SWR_ADC1"}, |
| 2145 | {"TX SMIC MUX6", "ADC2", "TX SWR_ADC2"}, |
| 2146 | {"TX SMIC MUX6", "ADC3", "TX SWR_ADC3"}, |
| 2147 | {"TX SMIC MUX6", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 2148 | {"TX SMIC MUX6", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 2149 | {"TX SMIC MUX6", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 2150 | {"TX SMIC MUX6", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 2151 | {"TX SMIC MUX6", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 2152 | {"TX SMIC MUX6", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 2153 | {"TX SMIC MUX6", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 2154 | {"TX SMIC MUX6", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 2155 | |
| 2156 | {"TX DEC7 MUX", "MSM_DMIC", "TX DMIC MUX7"}, |
| 2157 | {"TX DMIC MUX7", "DMIC0", "TX DMIC0"}, |
| 2158 | {"TX DMIC MUX7", "DMIC1", "TX DMIC1"}, |
| 2159 | {"TX DMIC MUX7", "DMIC2", "TX DMIC2"}, |
| 2160 | {"TX DMIC MUX7", "DMIC3", "TX DMIC3"}, |
| 2161 | {"TX DMIC MUX7", "DMIC4", "TX DMIC4"}, |
| 2162 | {"TX DMIC MUX7", "DMIC5", "TX DMIC5"}, |
| 2163 | {"TX DMIC MUX7", "DMIC6", "TX DMIC6"}, |
| 2164 | {"TX DMIC MUX7", "DMIC7", "TX DMIC7"}, |
| 2165 | |
| 2166 | {"TX DEC7 MUX", "SWR_MIC", "TX SMIC MUX7"}, |
Sudheer Papothi | e456c2c | 2019-03-05 07:08:45 +0530 | [diff] [blame] | 2167 | {"TX SMIC MUX7", NULL, "TX_SWR_CLK"}, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2168 | {"TX SMIC MUX7", "ADC0", "TX SWR_ADC0"}, |
| 2169 | {"TX SMIC MUX7", "ADC1", "TX SWR_ADC1"}, |
| 2170 | {"TX SMIC MUX7", "ADC2", "TX SWR_ADC2"}, |
| 2171 | {"TX SMIC MUX7", "ADC3", "TX SWR_ADC3"}, |
| 2172 | {"TX SMIC MUX7", "SWR_DMIC0", "TX SWR_DMIC0"}, |
| 2173 | {"TX SMIC MUX7", "SWR_DMIC1", "TX SWR_DMIC1"}, |
| 2174 | {"TX SMIC MUX7", "SWR_DMIC2", "TX SWR_DMIC2"}, |
| 2175 | {"TX SMIC MUX7", "SWR_DMIC3", "TX SWR_DMIC3"}, |
| 2176 | {"TX SMIC MUX7", "SWR_DMIC4", "TX SWR_DMIC4"}, |
| 2177 | {"TX SMIC MUX7", "SWR_DMIC5", "TX SWR_DMIC5"}, |
| 2178 | {"TX SMIC MUX7", "SWR_DMIC6", "TX SWR_DMIC6"}, |
| 2179 | {"TX SMIC MUX7", "SWR_DMIC7", "TX SWR_DMIC7"}, |
| 2180 | }; |
| 2181 | |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 2182 | static const struct snd_kcontrol_new tx_macro_snd_controls_common[] = { |
| 2183 | SOC_SINGLE_SX_TLV("TX_DEC0 Volume", |
| 2184 | BOLERO_CDC_TX0_TX_VOL_CTL, |
| 2185 | 0, -84, 40, digital_gain), |
| 2186 | SOC_SINGLE_SX_TLV("TX_DEC1 Volume", |
| 2187 | BOLERO_CDC_TX1_TX_VOL_CTL, |
| 2188 | 0, -84, 40, digital_gain), |
| 2189 | SOC_SINGLE_SX_TLV("TX_DEC2 Volume", |
| 2190 | BOLERO_CDC_TX2_TX_VOL_CTL, |
| 2191 | 0, -84, 40, digital_gain), |
| 2192 | SOC_SINGLE_SX_TLV("TX_DEC3 Volume", |
| 2193 | BOLERO_CDC_TX3_TX_VOL_CTL, |
| 2194 | 0, -84, 40, digital_gain), |
| 2195 | |
| 2196 | SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum, |
| 2197 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2198 | |
| 2199 | SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum, |
| 2200 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2201 | |
| 2202 | SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum, |
| 2203 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2204 | |
| 2205 | SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum, |
| 2206 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2207 | |
| 2208 | SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0, |
| 2209 | tx_macro_get_bcs, tx_macro_set_bcs), |
| 2210 | }; |
| 2211 | |
| 2212 | static const struct snd_kcontrol_new tx_macro_snd_controls_v3[] = { |
| 2213 | SOC_SINGLE_SX_TLV("TX_DEC4 Volume", |
| 2214 | BOLERO_CDC_TX4_TX_VOL_CTL, |
| 2215 | 0, -84, 40, digital_gain), |
| 2216 | SOC_SINGLE_SX_TLV("TX_DEC5 Volume", |
| 2217 | BOLERO_CDC_TX5_TX_VOL_CTL, |
| 2218 | 0, -84, 40, digital_gain), |
| 2219 | SOC_SINGLE_SX_TLV("TX_DEC6 Volume", |
| 2220 | BOLERO_CDC_TX6_TX_VOL_CTL, |
| 2221 | 0, -84, 40, digital_gain), |
| 2222 | SOC_SINGLE_SX_TLV("TX_DEC7 Volume", |
| 2223 | BOLERO_CDC_TX7_TX_VOL_CTL, |
| 2224 | 0, -84, 40, digital_gain), |
| 2225 | |
| 2226 | SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum, |
| 2227 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2228 | |
| 2229 | SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum, |
| 2230 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2231 | |
| 2232 | SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum, |
| 2233 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2234 | |
| 2235 | SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum, |
| 2236 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2237 | }; |
| 2238 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2239 | static const struct snd_kcontrol_new tx_macro_snd_controls[] = { |
| 2240 | SOC_SINGLE_SX_TLV("TX_DEC0 Volume", |
| 2241 | BOLERO_CDC_TX0_TX_VOL_CTL, |
| 2242 | 0, -84, 40, digital_gain), |
| 2243 | SOC_SINGLE_SX_TLV("TX_DEC1 Volume", |
| 2244 | BOLERO_CDC_TX1_TX_VOL_CTL, |
| 2245 | 0, -84, 40, digital_gain), |
| 2246 | SOC_SINGLE_SX_TLV("TX_DEC2 Volume", |
| 2247 | BOLERO_CDC_TX2_TX_VOL_CTL, |
| 2248 | 0, -84, 40, digital_gain), |
| 2249 | SOC_SINGLE_SX_TLV("TX_DEC3 Volume", |
| 2250 | BOLERO_CDC_TX3_TX_VOL_CTL, |
| 2251 | 0, -84, 40, digital_gain), |
| 2252 | SOC_SINGLE_SX_TLV("TX_DEC4 Volume", |
| 2253 | BOLERO_CDC_TX4_TX_VOL_CTL, |
| 2254 | 0, -84, 40, digital_gain), |
| 2255 | SOC_SINGLE_SX_TLV("TX_DEC5 Volume", |
| 2256 | BOLERO_CDC_TX5_TX_VOL_CTL, |
| 2257 | 0, -84, 40, digital_gain), |
| 2258 | SOC_SINGLE_SX_TLV("TX_DEC6 Volume", |
| 2259 | BOLERO_CDC_TX6_TX_VOL_CTL, |
| 2260 | 0, -84, 40, digital_gain), |
| 2261 | SOC_SINGLE_SX_TLV("TX_DEC7 Volume", |
| 2262 | BOLERO_CDC_TX7_TX_VOL_CTL, |
| 2263 | 0, -84, 40, digital_gain), |
Karthikeyan Mani | 765eaab | 2019-07-18 16:27:01 -0700 | [diff] [blame] | 2264 | |
Karthikeyan Mani | 1dcd5a3 | 2019-08-22 14:37:13 -0700 | [diff] [blame] | 2265 | SOC_ENUM_EXT("DEC0 MODE", dec_mode_mux_enum, |
| 2266 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2267 | |
| 2268 | SOC_ENUM_EXT("DEC1 MODE", dec_mode_mux_enum, |
| 2269 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2270 | |
| 2271 | SOC_ENUM_EXT("DEC2 MODE", dec_mode_mux_enum, |
| 2272 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2273 | |
| 2274 | SOC_ENUM_EXT("DEC3 MODE", dec_mode_mux_enum, |
| 2275 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2276 | |
| 2277 | SOC_ENUM_EXT("DEC4 MODE", dec_mode_mux_enum, |
| 2278 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2279 | |
| 2280 | SOC_ENUM_EXT("DEC5 MODE", dec_mode_mux_enum, |
| 2281 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2282 | |
| 2283 | SOC_ENUM_EXT("DEC6 MODE", dec_mode_mux_enum, |
| 2284 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2285 | |
| 2286 | SOC_ENUM_EXT("DEC7 MODE", dec_mode_mux_enum, |
| 2287 | tx_macro_dec_mode_get, tx_macro_dec_mode_put), |
| 2288 | |
Karthikeyan Mani | 765eaab | 2019-07-18 16:27:01 -0700 | [diff] [blame] | 2289 | SOC_SINGLE_EXT("DEC0_BCS Switch", SND_SOC_NOPM, 0, 1, 0, |
| 2290 | tx_macro_get_bcs, tx_macro_set_bcs), |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2291 | }; |
| 2292 | |
Sudheer Papothi | 06a4c64 | 2019-08-08 05:17:46 +0530 | [diff] [blame] | 2293 | static int tx_macro_register_event_listener(struct snd_soc_component *component, |
| 2294 | bool enable) |
| 2295 | { |
| 2296 | struct device *tx_dev = NULL; |
| 2297 | struct tx_macro_priv *tx_priv = NULL; |
| 2298 | int ret = 0; |
| 2299 | |
| 2300 | if (!component) |
| 2301 | return -EINVAL; |
| 2302 | |
| 2303 | tx_dev = bolero_get_device_ptr(component->dev, TX_MACRO); |
| 2304 | if (!tx_dev) { |
| 2305 | dev_err(component->dev, |
| 2306 | "%s: null device for macro!\n", __func__); |
| 2307 | return -EINVAL; |
| 2308 | } |
| 2309 | tx_priv = dev_get_drvdata(tx_dev); |
| 2310 | if (!tx_priv) { |
| 2311 | dev_err(component->dev, |
| 2312 | "%s: priv is null for macro!\n", __func__); |
| 2313 | return -EINVAL; |
| 2314 | } |
Sudheer Papothi | fc3adb0 | 2019-11-24 10:14:21 +0530 | [diff] [blame] | 2315 | if (tx_priv->swr_ctrl_data && !tx_priv->tx_swr_clk_cnt) { |
Sudheer Papothi | bc3f1e5 | 2019-09-17 04:03:10 +0530 | [diff] [blame] | 2316 | if (enable) { |
Sudheer Papothi | 06a4c64 | 2019-08-08 05:17:46 +0530 | [diff] [blame] | 2317 | ret = swrm_wcd_notify( |
| 2318 | tx_priv->swr_ctrl_data[0].tx_swr_pdev, |
| 2319 | SWR_REGISTER_WAKEUP, NULL); |
Sudheer Papothi | bc3f1e5 | 2019-09-17 04:03:10 +0530 | [diff] [blame] | 2320 | msm_cdc_pinctrl_set_wakeup_capable( |
| 2321 | tx_priv->tx_swr_gpio_p, false); |
| 2322 | } else { |
| 2323 | msm_cdc_pinctrl_set_wakeup_capable( |
| 2324 | tx_priv->tx_swr_gpio_p, true); |
Sudheer Papothi | 06a4c64 | 2019-08-08 05:17:46 +0530 | [diff] [blame] | 2325 | ret = swrm_wcd_notify( |
| 2326 | tx_priv->swr_ctrl_data[0].tx_swr_pdev, |
| 2327 | SWR_DEREGISTER_WAKEUP, NULL); |
Sudheer Papothi | bc3f1e5 | 2019-09-17 04:03:10 +0530 | [diff] [blame] | 2328 | } |
Sudheer Papothi | 06a4c64 | 2019-08-08 05:17:46 +0530 | [diff] [blame] | 2329 | } |
| 2330 | |
| 2331 | return ret; |
| 2332 | } |
| 2333 | |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2334 | static int tx_macro_tx_va_mclk_enable(struct tx_macro_priv *tx_priv, |
| 2335 | struct regmap *regmap, int clk_type, |
| 2336 | bool enable) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2337 | { |
Meng Wang | 69b55c8 | 2019-05-29 11:04:29 +0800 | [diff] [blame] | 2338 | int ret = 0, clk_tx_ret = 0; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2339 | |
Sudheer Papothi | 7601cc6 | 2019-03-30 03:00:52 +0530 | [diff] [blame] | 2340 | dev_dbg(tx_priv->dev, |
| 2341 | "%s: clock type %s, enable: %s tx_mclk_users: %d\n", |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2342 | __func__, (clk_type ? "VA_MCLK" : "TX_MCLK"), |
Sudheer Papothi | 7601cc6 | 2019-03-30 03:00:52 +0530 | [diff] [blame] | 2343 | (enable ? "enable" : "disable"), tx_priv->tx_mclk_users); |
Tanya Dixit | 8530fb9 | 2018-09-14 16:01:25 +0530 | [diff] [blame] | 2344 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2345 | if (enable) { |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 2346 | if (tx_priv->swr_clk_users == 0) { |
| 2347 | ret = msm_cdc_pinctrl_select_active_state( |
Karthikeyan Mani | 01f1ba4 | 2019-02-26 18:48:15 -0800 | [diff] [blame] | 2348 | tx_priv->tx_swr_gpio_p); |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 2349 | if (ret < 0) { |
| 2350 | dev_err_ratelimited(tx_priv->dev, |
| 2351 | "%s: tx swr pinctrl enable failed\n", |
| 2352 | __func__); |
| 2353 | goto exit; |
| 2354 | } |
| 2355 | } |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2356 | |
Meng Wang | 69b55c8 | 2019-05-29 11:04:29 +0800 | [diff] [blame] | 2357 | clk_tx_ret = bolero_clk_rsc_request_clock(tx_priv->dev, |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2358 | TX_CORE_CLK, |
| 2359 | TX_CORE_CLK, |
| 2360 | true); |
| 2361 | if (clk_type == TX_MCLK) { |
| 2362 | ret = tx_macro_mclk_enable(tx_priv, 1); |
| 2363 | if (ret < 0) { |
| 2364 | if (tx_priv->swr_clk_users == 0) |
| 2365 | msm_cdc_pinctrl_select_sleep_state( |
| 2366 | tx_priv->tx_swr_gpio_p); |
| 2367 | dev_err_ratelimited(tx_priv->dev, |
| 2368 | "%s: request clock enable failed\n", |
| 2369 | __func__); |
| 2370 | goto done; |
| 2371 | } |
| 2372 | } |
| 2373 | if (clk_type == VA_MCLK) { |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2374 | ret = bolero_clk_rsc_request_clock(tx_priv->dev, |
| 2375 | TX_CORE_CLK, |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2376 | VA_CORE_CLK, |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2377 | true); |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2378 | if (ret < 0) { |
| 2379 | if (tx_priv->swr_clk_users == 0) |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2380 | msm_cdc_pinctrl_select_sleep_state( |
| 2381 | tx_priv->tx_swr_gpio_p); |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2382 | dev_err_ratelimited(tx_priv->dev, |
| 2383 | "%s: swr request clk failed\n", |
| 2384 | __func__); |
| 2385 | goto done; |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2386 | } |
Sudheer Papothi | 296867b | 2019-06-20 09:24:09 +0530 | [diff] [blame] | 2387 | bolero_clk_rsc_fs_gen_request(tx_priv->dev, |
| 2388 | true); |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2389 | if (tx_priv->tx_mclk_users == 0) { |
| 2390 | regmap_update_bits(regmap, |
| 2391 | BOLERO_CDC_TX_TOP_CSR_FREQ_MCLK, |
| 2392 | 0x01, 0x01); |
| 2393 | regmap_update_bits(regmap, |
Meng Wang | 52a8fb1 | 2019-12-12 20:36:05 +0800 | [diff] [blame] | 2394 | BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2395 | 0x01, 0x01); |
| 2396 | regmap_update_bits(regmap, |
Meng Wang | 52a8fb1 | 2019-12-12 20:36:05 +0800 | [diff] [blame] | 2397 | BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2398 | 0x01, 0x01); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2399 | } |
Meng Wang | 52a8fb1 | 2019-12-12 20:36:05 +0800 | [diff] [blame] | 2400 | tx_priv->tx_mclk_users++; |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2401 | } |
| 2402 | if (tx_priv->swr_clk_users == 0) { |
Sudheer Papothi | 7601cc6 | 2019-03-30 03:00:52 +0530 | [diff] [blame] | 2403 | dev_dbg(tx_priv->dev, "%s: reset_swr: %d\n", |
| 2404 | __func__, tx_priv->reset_swr); |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame] | 2405 | if (tx_priv->reset_swr) |
| 2406 | regmap_update_bits(regmap, |
| 2407 | BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, |
| 2408 | 0x02, 0x02); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2409 | regmap_update_bits(regmap, |
| 2410 | BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, |
| 2411 | 0x01, 0x01); |
Ramprasad Katkam | a4c747b | 2018-12-11 19:15:53 +0530 | [diff] [blame] | 2412 | if (tx_priv->reset_swr) |
| 2413 | regmap_update_bits(regmap, |
| 2414 | BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, |
| 2415 | 0x02, 0x00); |
| 2416 | tx_priv->reset_swr = false; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2417 | } |
Meng Wang | 69b55c8 | 2019-05-29 11:04:29 +0800 | [diff] [blame] | 2418 | if (!clk_tx_ret) |
| 2419 | ret = bolero_clk_rsc_request_clock(tx_priv->dev, |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2420 | TX_CORE_CLK, |
| 2421 | TX_CORE_CLK, |
| 2422 | false); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2423 | tx_priv->swr_clk_users++; |
| 2424 | } else { |
| 2425 | if (tx_priv->swr_clk_users <= 0) { |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2426 | dev_err_ratelimited(tx_priv->dev, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2427 | "tx swrm clock users already 0\n"); |
| 2428 | tx_priv->swr_clk_users = 0; |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2429 | return 0; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2430 | } |
Meng Wang | 69b55c8 | 2019-05-29 11:04:29 +0800 | [diff] [blame] | 2431 | clk_tx_ret = bolero_clk_rsc_request_clock(tx_priv->dev, |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2432 | TX_CORE_CLK, |
| 2433 | TX_CORE_CLK, |
| 2434 | true); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2435 | tx_priv->swr_clk_users--; |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2436 | if (tx_priv->swr_clk_users == 0) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2437 | regmap_update_bits(regmap, |
| 2438 | BOLERO_CDC_TX_CLK_RST_CTRL_SWR_CONTROL, |
| 2439 | 0x01, 0x00); |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2440 | if (clk_type == TX_MCLK) |
| 2441 | tx_macro_mclk_enable(tx_priv, 0); |
| 2442 | if (clk_type == VA_MCLK) { |
Meng Wang | 52a8fb1 | 2019-12-12 20:36:05 +0800 | [diff] [blame] | 2443 | if (tx_priv->tx_mclk_users <= 0) { |
| 2444 | dev_err(tx_priv->dev, "%s: clock already disabled\n", |
| 2445 | __func__); |
| 2446 | tx_priv->tx_mclk_users = 0; |
| 2447 | goto tx_clk; |
| 2448 | } |
| 2449 | tx_priv->tx_mclk_users--; |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2450 | if (tx_priv->tx_mclk_users == 0) { |
| 2451 | regmap_update_bits(regmap, |
Meng Wang | 52a8fb1 | 2019-12-12 20:36:05 +0800 | [diff] [blame] | 2452 | BOLERO_CDC_TX_CLK_RST_CTRL_FS_CNT_CONTROL, |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2453 | 0x01, 0x00); |
| 2454 | regmap_update_bits(regmap, |
Meng Wang | 52a8fb1 | 2019-12-12 20:36:05 +0800 | [diff] [blame] | 2455 | BOLERO_CDC_TX_CLK_RST_CTRL_MCLK_CONTROL, |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2456 | 0x01, 0x00); |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2457 | } |
Meng Wang | 52a8fb1 | 2019-12-12 20:36:05 +0800 | [diff] [blame] | 2458 | |
Sudheer Papothi | 296867b | 2019-06-20 09:24:09 +0530 | [diff] [blame] | 2459 | bolero_clk_rsc_fs_gen_request(tx_priv->dev, |
Meng Wang | 52a8fb1 | 2019-12-12 20:36:05 +0800 | [diff] [blame] | 2460 | false); |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2461 | ret = bolero_clk_rsc_request_clock(tx_priv->dev, |
| 2462 | TX_CORE_CLK, |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2463 | VA_CORE_CLK, |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2464 | false); |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2465 | if (ret < 0) { |
| 2466 | dev_err_ratelimited(tx_priv->dev, |
| 2467 | "%s: swr request clk failed\n", |
| 2468 | __func__); |
| 2469 | goto done; |
| 2470 | } |
| 2471 | } |
Meng Wang | 52a8fb1 | 2019-12-12 20:36:05 +0800 | [diff] [blame] | 2472 | tx_clk: |
Meng Wang | 69b55c8 | 2019-05-29 11:04:29 +0800 | [diff] [blame] | 2473 | if (!clk_tx_ret) |
| 2474 | ret = bolero_clk_rsc_request_clock(tx_priv->dev, |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2475 | TX_CORE_CLK, |
| 2476 | TX_CORE_CLK, |
| 2477 | false); |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 2478 | if (tx_priv->swr_clk_users == 0) { |
| 2479 | ret = msm_cdc_pinctrl_select_sleep_state( |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2480 | tx_priv->tx_swr_gpio_p); |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 2481 | if (ret < 0) { |
| 2482 | dev_err_ratelimited(tx_priv->dev, |
| 2483 | "%s: tx swr pinctrl disable failed\n", |
| 2484 | __func__); |
| 2485 | goto exit; |
| 2486 | } |
| 2487 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2488 | } |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2489 | return 0; |
| 2490 | |
| 2491 | done: |
Meng Wang | 69b55c8 | 2019-05-29 11:04:29 +0800 | [diff] [blame] | 2492 | if (!clk_tx_ret) |
| 2493 | bolero_clk_rsc_request_clock(tx_priv->dev, |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2494 | TX_CORE_CLK, |
| 2495 | TX_CORE_CLK, |
| 2496 | false); |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 2497 | exit: |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2498 | return ret; |
| 2499 | } |
| 2500 | |
Sudheer Papothi | d50a581 | 2019-11-21 07:24:42 +0530 | [diff] [blame] | 2501 | static int tx_macro_clk_div_get(struct snd_soc_component *component) |
| 2502 | { |
| 2503 | struct device *tx_dev = NULL; |
| 2504 | struct tx_macro_priv *tx_priv = NULL; |
| 2505 | |
| 2506 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
| 2507 | return -EINVAL; |
| 2508 | |
| 2509 | return tx_priv->dmic_clk_div; |
| 2510 | } |
| 2511 | |
Sudheer Papothi | f415500 | 2019-12-05 01:36:13 +0530 | [diff] [blame] | 2512 | static int tx_macro_clk_switch(struct snd_soc_component *component, int clk_src) |
Sudheer Papothi | 6cc7f52 | 2019-06-28 11:04:03 +0530 | [diff] [blame] | 2513 | { |
| 2514 | struct device *tx_dev = NULL; |
| 2515 | struct tx_macro_priv *tx_priv = NULL; |
| 2516 | int ret = 0; |
| 2517 | |
| 2518 | if (!component) |
| 2519 | return -EINVAL; |
| 2520 | |
| 2521 | tx_dev = bolero_get_device_ptr(component->dev, TX_MACRO); |
| 2522 | if (!tx_dev) { |
| 2523 | dev_err(component->dev, |
| 2524 | "%s: null device for macro!\n", __func__); |
| 2525 | return -EINVAL; |
| 2526 | } |
| 2527 | tx_priv = dev_get_drvdata(tx_dev); |
| 2528 | if (!tx_priv) { |
| 2529 | dev_err(component->dev, |
| 2530 | "%s: priv is null for macro!\n", __func__); |
| 2531 | return -EINVAL; |
| 2532 | } |
| 2533 | if (tx_priv->swr_ctrl_data) { |
| 2534 | ret = swrm_wcd_notify( |
| 2535 | tx_priv->swr_ctrl_data[0].tx_swr_pdev, |
Sudheer Papothi | f415500 | 2019-12-05 01:36:13 +0530 | [diff] [blame] | 2536 | SWR_REQ_CLK_SWITCH, &clk_src); |
Sudheer Papothi | 6cc7f52 | 2019-06-28 11:04:03 +0530 | [diff] [blame] | 2537 | } |
| 2538 | |
| 2539 | return ret; |
| 2540 | } |
| 2541 | |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 2542 | static int tx_macro_core_vote(void *handle, bool enable) |
| 2543 | { |
| 2544 | struct tx_macro_priv *tx_priv = (struct tx_macro_priv *) handle; |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 2545 | |
| 2546 | if (tx_priv == NULL) { |
| 2547 | pr_err("%s: tx priv data is NULL\n", __func__); |
| 2548 | return -EINVAL; |
| 2549 | } |
| 2550 | if (enable) { |
| 2551 | pm_runtime_get_sync(tx_priv->dev); |
| 2552 | pm_runtime_put_autosuspend(tx_priv->dev); |
| 2553 | pm_runtime_mark_last_busy(tx_priv->dev); |
| 2554 | } |
| 2555 | |
Aditya Bavanari | d577af9 | 2019-10-03 21:09:19 +0530 | [diff] [blame] | 2556 | if (bolero_check_core_votes(tx_priv->dev)) |
| 2557 | return 0; |
| 2558 | else |
| 2559 | return -EINVAL; |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 2560 | } |
| 2561 | |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2562 | static int tx_macro_swrm_clock(void *handle, bool enable) |
| 2563 | { |
| 2564 | struct tx_macro_priv *tx_priv = (struct tx_macro_priv *) handle; |
| 2565 | struct regmap *regmap = dev_get_regmap(tx_priv->dev->parent, NULL); |
| 2566 | int ret = 0; |
| 2567 | |
| 2568 | if (regmap == NULL) { |
| 2569 | dev_err(tx_priv->dev, "%s: regmap is NULL\n", __func__); |
| 2570 | return -EINVAL; |
| 2571 | } |
| 2572 | |
| 2573 | mutex_lock(&tx_priv->swr_clk_lock); |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2574 | dev_dbg(tx_priv->dev, |
| 2575 | "%s: swrm clock %s tx_swr_clk_cnt: %d va_swr_clk_cnt: %d\n", |
| 2576 | __func__, (enable ? "enable" : "disable"), |
| 2577 | tx_priv->tx_swr_clk_cnt, tx_priv->va_swr_clk_cnt); |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2578 | |
| 2579 | if (enable) { |
Sudheer Papothi | 7601cc6 | 2019-03-30 03:00:52 +0530 | [diff] [blame] | 2580 | pm_runtime_get_sync(tx_priv->dev); |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2581 | if (tx_priv->va_swr_clk_cnt && !tx_priv->tx_swr_clk_cnt) { |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2582 | ret = tx_macro_tx_va_mclk_enable(tx_priv, regmap, |
| 2583 | VA_MCLK, enable); |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 2584 | if (ret) { |
| 2585 | pm_runtime_mark_last_busy(tx_priv->dev); |
| 2586 | pm_runtime_put_autosuspend(tx_priv->dev); |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2587 | goto done; |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 2588 | } |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2589 | tx_priv->va_clk_status++; |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2590 | } else { |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2591 | ret = tx_macro_tx_va_mclk_enable(tx_priv, regmap, |
| 2592 | TX_MCLK, enable); |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 2593 | if (ret) { |
| 2594 | pm_runtime_mark_last_busy(tx_priv->dev); |
| 2595 | pm_runtime_put_autosuspend(tx_priv->dev); |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2596 | goto done; |
Karthikeyan Mani | 8d40a06 | 2019-09-05 16:44:49 -0700 | [diff] [blame] | 2597 | } |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2598 | tx_priv->tx_clk_status++; |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2599 | } |
Sudheer Papothi | 7601cc6 | 2019-03-30 03:00:52 +0530 | [diff] [blame] | 2600 | pm_runtime_mark_last_busy(tx_priv->dev); |
| 2601 | pm_runtime_put_autosuspend(tx_priv->dev); |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2602 | } else { |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2603 | if (tx_priv->va_clk_status && !tx_priv->tx_clk_status) { |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2604 | ret = tx_macro_tx_va_mclk_enable(tx_priv, regmap, |
| 2605 | VA_MCLK, enable); |
| 2606 | if (ret) |
| 2607 | goto done; |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2608 | --tx_priv->va_clk_status; |
| 2609 | } else if (!tx_priv->va_clk_status && tx_priv->tx_clk_status) { |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2610 | ret = tx_macro_tx_va_mclk_enable(tx_priv, regmap, |
| 2611 | TX_MCLK, enable); |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2612 | if (ret) |
| 2613 | goto done; |
| 2614 | --tx_priv->tx_clk_status; |
| 2615 | } else if (tx_priv->va_clk_status && tx_priv->tx_clk_status) { |
| 2616 | if (!tx_priv->va_swr_clk_cnt && tx_priv->tx_swr_clk_cnt) { |
| 2617 | ret = tx_macro_tx_va_mclk_enable(tx_priv, regmap, |
| 2618 | VA_MCLK, enable); |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2619 | if (ret) |
| 2620 | goto done; |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2621 | --tx_priv->va_clk_status; |
| 2622 | } else { |
| 2623 | ret = tx_macro_tx_va_mclk_enable(tx_priv, regmap, |
| 2624 | TX_MCLK, enable); |
| 2625 | if (ret) |
| 2626 | goto done; |
| 2627 | --tx_priv->tx_clk_status; |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2628 | } |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2629 | |
| 2630 | } else { |
| 2631 | dev_dbg(tx_priv->dev, |
| 2632 | "%s: Both clocks are disabled\n", __func__); |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2633 | } |
| 2634 | } |
Sudheer Papothi | cf3b406 | 2019-05-10 10:48:43 +0530 | [diff] [blame] | 2635 | |
| 2636 | dev_dbg(tx_priv->dev, |
| 2637 | "%s: swrm clock users %d tx_clk_sts_cnt: %d va_clk_sts_cnt: %d\n", |
| 2638 | __func__, tx_priv->swr_clk_users, tx_priv->tx_clk_status, |
| 2639 | tx_priv->va_clk_status); |
Sudheer Papothi | a739794 | 2019-03-19 03:14:23 +0530 | [diff] [blame] | 2640 | done: |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2641 | mutex_unlock(&tx_priv->swr_clk_lock); |
| 2642 | return ret; |
| 2643 | } |
| 2644 | |
| 2645 | static int tx_macro_validate_dmic_sample_rate(u32 dmic_sample_rate, |
| 2646 | struct tx_macro_priv *tx_priv) |
| 2647 | { |
| 2648 | u32 div_factor = TX_MACRO_CLK_DIV_2; |
| 2649 | u32 mclk_rate = TX_MACRO_MCLK_FREQ; |
| 2650 | |
| 2651 | if (dmic_sample_rate == TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED || |
| 2652 | mclk_rate % dmic_sample_rate != 0) |
| 2653 | goto undefined_rate; |
| 2654 | |
| 2655 | div_factor = mclk_rate / dmic_sample_rate; |
| 2656 | |
| 2657 | switch (div_factor) { |
| 2658 | case 2: |
| 2659 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_2; |
| 2660 | break; |
| 2661 | case 3: |
| 2662 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_3; |
| 2663 | break; |
| 2664 | case 4: |
| 2665 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_4; |
| 2666 | break; |
| 2667 | case 6: |
| 2668 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_6; |
| 2669 | break; |
| 2670 | case 8: |
| 2671 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_8; |
| 2672 | break; |
| 2673 | case 16: |
| 2674 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_16; |
| 2675 | break; |
| 2676 | default: |
| 2677 | /* Any other DIV factor is invalid */ |
| 2678 | goto undefined_rate; |
| 2679 | } |
| 2680 | |
| 2681 | /* Valid dmic DIV factors */ |
| 2682 | dev_dbg(tx_priv->dev, "%s: DMIC_DIV = %u, mclk_rate = %u\n", |
| 2683 | __func__, div_factor, mclk_rate); |
| 2684 | |
| 2685 | return dmic_sample_rate; |
| 2686 | |
| 2687 | undefined_rate: |
| 2688 | dev_dbg(tx_priv->dev, "%s: Invalid rate %d, for mclk %d\n", |
| 2689 | __func__, dmic_sample_rate, mclk_rate); |
| 2690 | dmic_sample_rate = TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED; |
| 2691 | |
| 2692 | return dmic_sample_rate; |
| 2693 | } |
| 2694 | |
Sudheer Papothi | 72fef48 | 2019-08-30 11:00:20 +0530 | [diff] [blame] | 2695 | static const struct tx_macro_reg_mask_val tx_macro_reg_init[] = { |
Vatsal Bucha | 116ac37 | 2020-01-14 12:55:18 +0530 | [diff] [blame^] | 2696 | {BOLERO_CDC_TX0_TX_PATH_SEC7, 0x3F, 0x0A}, |
Sudheer Papothi | 72fef48 | 2019-08-30 11:00:20 +0530 | [diff] [blame] | 2697 | }; |
| 2698 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2699 | static int tx_macro_init(struct snd_soc_component *component) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2700 | { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2701 | struct snd_soc_dapm_context *dapm = |
| 2702 | snd_soc_component_get_dapm(component); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2703 | int ret = 0, i = 0; |
| 2704 | struct device *tx_dev = NULL; |
| 2705 | struct tx_macro_priv *tx_priv = NULL; |
| 2706 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2707 | tx_dev = bolero_get_device_ptr(component->dev, TX_MACRO); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2708 | if (!tx_dev) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2709 | dev_err(component->dev, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2710 | "%s: null device for macro!\n", __func__); |
| 2711 | return -EINVAL; |
| 2712 | } |
| 2713 | tx_priv = dev_get_drvdata(tx_dev); |
| 2714 | if (!tx_priv) { |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2715 | dev_err(component->dev, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2716 | "%s: priv is null for macro!\n", __func__); |
| 2717 | return -EINVAL; |
| 2718 | } |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 2719 | tx_priv->version = bolero_get_version(tx_dev); |
| 2720 | if (tx_priv->version >= BOLERO_VERSION_2_0) { |
| 2721 | ret = snd_soc_dapm_new_controls(dapm, |
| 2722 | tx_macro_dapm_widgets_common, |
| 2723 | ARRAY_SIZE(tx_macro_dapm_widgets_common)); |
| 2724 | if (ret < 0) { |
| 2725 | dev_err(tx_dev, "%s: Failed to add controls\n", |
| 2726 | __func__); |
| 2727 | return ret; |
| 2728 | } |
| 2729 | if (tx_priv->version == BOLERO_VERSION_2_1) |
| 2730 | ret = snd_soc_dapm_new_controls(dapm, |
| 2731 | tx_macro_dapm_widgets_v2, |
| 2732 | ARRAY_SIZE(tx_macro_dapm_widgets_v2)); |
| 2733 | else if (tx_priv->version == BOLERO_VERSION_2_0) |
| 2734 | ret = snd_soc_dapm_new_controls(dapm, |
| 2735 | tx_macro_dapm_widgets_v3, |
| 2736 | ARRAY_SIZE(tx_macro_dapm_widgets_v3)); |
| 2737 | if (ret < 0) { |
| 2738 | dev_err(tx_dev, "%s: Failed to add controls\n", |
| 2739 | __func__); |
| 2740 | return ret; |
| 2741 | } |
| 2742 | } else { |
| 2743 | ret = snd_soc_dapm_new_controls(dapm, tx_macro_dapm_widgets, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2744 | ARRAY_SIZE(tx_macro_dapm_widgets)); |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 2745 | if (ret < 0) { |
| 2746 | dev_err(tx_dev, "%s: Failed to add controls\n", |
| 2747 | __func__); |
| 2748 | return ret; |
| 2749 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2750 | } |
| 2751 | |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 2752 | if (tx_priv->version >= BOLERO_VERSION_2_0) { |
| 2753 | ret = snd_soc_dapm_add_routes(dapm, |
| 2754 | tx_audio_map_common, |
| 2755 | ARRAY_SIZE(tx_audio_map_common)); |
| 2756 | if (ret < 0) { |
| 2757 | dev_err(tx_dev, "%s: Failed to add routes\n", |
| 2758 | __func__); |
| 2759 | return ret; |
| 2760 | } |
| 2761 | if (tx_priv->version == BOLERO_VERSION_2_0) |
| 2762 | ret = snd_soc_dapm_add_routes(dapm, |
| 2763 | tx_audio_map_v3, |
| 2764 | ARRAY_SIZE(tx_audio_map_v3)); |
| 2765 | if (ret < 0) { |
| 2766 | dev_err(tx_dev, "%s: Failed to add routes\n", |
| 2767 | __func__); |
| 2768 | return ret; |
| 2769 | } |
| 2770 | } else { |
| 2771 | ret = snd_soc_dapm_add_routes(dapm, tx_audio_map, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2772 | ARRAY_SIZE(tx_audio_map)); |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 2773 | if (ret < 0) { |
| 2774 | dev_err(tx_dev, "%s: Failed to add routes\n", |
| 2775 | __func__); |
| 2776 | return ret; |
| 2777 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2778 | } |
| 2779 | |
| 2780 | ret = snd_soc_dapm_new_widgets(dapm->card); |
| 2781 | if (ret < 0) { |
| 2782 | dev_err(tx_dev, "%s: Failed to add widgets\n", __func__); |
| 2783 | return ret; |
| 2784 | } |
| 2785 | |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 2786 | if (tx_priv->version >= BOLERO_VERSION_2_0) { |
| 2787 | ret = snd_soc_add_component_controls(component, |
| 2788 | tx_macro_snd_controls_common, |
| 2789 | ARRAY_SIZE(tx_macro_snd_controls_common)); |
| 2790 | if (ret < 0) { |
| 2791 | dev_err(tx_dev, "%s: Failed to add snd_ctls\n", |
| 2792 | __func__); |
| 2793 | return ret; |
| 2794 | } |
| 2795 | if (tx_priv->version == BOLERO_VERSION_2_0) |
| 2796 | ret = snd_soc_add_component_controls(component, |
| 2797 | tx_macro_snd_controls_v3, |
| 2798 | ARRAY_SIZE(tx_macro_snd_controls_v3)); |
| 2799 | if (ret < 0) { |
| 2800 | dev_err(tx_dev, "%s: Failed to add snd_ctls\n", |
| 2801 | __func__); |
| 2802 | return ret; |
| 2803 | } |
| 2804 | } else { |
| 2805 | ret = snd_soc_add_component_controls(component, |
| 2806 | tx_macro_snd_controls, |
| 2807 | ARRAY_SIZE(tx_macro_snd_controls)); |
| 2808 | if (ret < 0) { |
| 2809 | dev_err(tx_dev, "%s: Failed to add snd_ctls\n", |
| 2810 | __func__); |
| 2811 | return ret; |
| 2812 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2813 | } |
Laxminath Kasam | 638b560 | 2018-09-24 13:19:52 +0530 | [diff] [blame] | 2814 | |
| 2815 | snd_soc_dapm_ignore_suspend(dapm, "TX_AIF1 Capture"); |
| 2816 | snd_soc_dapm_ignore_suspend(dapm, "TX_AIF2 Capture"); |
Karthikeyan Mani | f3bb818 | 2019-07-11 14:38:54 -0700 | [diff] [blame] | 2817 | snd_soc_dapm_ignore_suspend(dapm, "TX_AIF3 Capture"); |
Laxminath Kasam | 4651dcb | 2019-10-10 23:45:21 +0530 | [diff] [blame] | 2818 | if (tx_priv->version >= BOLERO_VERSION_2_0) { |
| 2819 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC0"); |
| 2820 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC1"); |
| 2821 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC2"); |
| 2822 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC3"); |
| 2823 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC4"); |
| 2824 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC5"); |
| 2825 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC6"); |
| 2826 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC7"); |
| 2827 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC8"); |
| 2828 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC9"); |
| 2829 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC10"); |
| 2830 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_MIC11"); |
| 2831 | } else { |
| 2832 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_ADC0"); |
| 2833 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_ADC1"); |
| 2834 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_ADC2"); |
| 2835 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_ADC3"); |
| 2836 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC0"); |
| 2837 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC1"); |
| 2838 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC2"); |
| 2839 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC3"); |
| 2840 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC4"); |
| 2841 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC5"); |
| 2842 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC6"); |
| 2843 | snd_soc_dapm_ignore_suspend(dapm, "TX SWR_DMIC7"); |
| 2844 | } |
Laxminath Kasam | 638b560 | 2018-09-24 13:19:52 +0530 | [diff] [blame] | 2845 | snd_soc_dapm_sync(dapm); |
| 2846 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2847 | for (i = 0; i < NUM_DECIMATORS; i++) { |
| 2848 | tx_priv->tx_hpf_work[i].tx_priv = tx_priv; |
| 2849 | tx_priv->tx_hpf_work[i].decimator = i; |
| 2850 | INIT_DELAYED_WORK(&tx_priv->tx_hpf_work[i].dwork, |
| 2851 | tx_macro_tx_hpf_corner_freq_callback); |
| 2852 | } |
| 2853 | |
| 2854 | for (i = 0; i < NUM_DECIMATORS; i++) { |
| 2855 | tx_priv->tx_mute_dwork[i].tx_priv = tx_priv; |
| 2856 | tx_priv->tx_mute_dwork[i].decimator = i; |
| 2857 | INIT_DELAYED_WORK(&tx_priv->tx_mute_dwork[i].dwork, |
| 2858 | tx_macro_mute_update_callback); |
| 2859 | } |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2860 | tx_priv->component = component; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2861 | |
Sudheer Papothi | 72fef48 | 2019-08-30 11:00:20 +0530 | [diff] [blame] | 2862 | for (i = 0; i < ARRAY_SIZE(tx_macro_reg_init); i++) |
| 2863 | snd_soc_component_update_bits(component, |
| 2864 | tx_macro_reg_init[i].reg, |
| 2865 | tx_macro_reg_init[i].mask, |
| 2866 | tx_macro_reg_init[i].val); |
| 2867 | |
Laxminath Kasam | fbd95ed | 2019-11-05 22:07:06 +0530 | [diff] [blame] | 2868 | if (tx_priv->version == BOLERO_VERSION_2_1) |
| 2869 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 696b14b | 2019-12-03 22:07:34 +0530 | [diff] [blame] | 2870 | BOLERO_CDC_VA_TOP_CSR_SWR_CTRL, 0x0F, 0x0A); |
Laxminath Kasam | fbd95ed | 2019-11-05 22:07:06 +0530 | [diff] [blame] | 2871 | else if (tx_priv->version == BOLERO_VERSION_2_0) |
| 2872 | snd_soc_component_update_bits(component, |
Laxminath Kasam | 696b14b | 2019-12-03 22:07:34 +0530 | [diff] [blame] | 2873 | BOLERO_CDC_TX_TOP_CSR_SWR_CTRL, 0x0F, 0x0A); |
Laxminath Kasam | fbd95ed | 2019-11-05 22:07:06 +0530 | [diff] [blame] | 2874 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2875 | return 0; |
| 2876 | } |
| 2877 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2878 | static int tx_macro_deinit(struct snd_soc_component *component) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2879 | { |
| 2880 | struct device *tx_dev = NULL; |
| 2881 | struct tx_macro_priv *tx_priv = NULL; |
| 2882 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2883 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2884 | return -EINVAL; |
| 2885 | |
Meng Wang | 15c825d | 2018-09-06 10:49:18 +0800 | [diff] [blame] | 2886 | tx_priv->component = NULL; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 2887 | return 0; |
| 2888 | } |
| 2889 | |
| 2890 | static void tx_macro_add_child_devices(struct work_struct *work) |
| 2891 | { |
| 2892 | struct tx_macro_priv *tx_priv = NULL; |
| 2893 | struct platform_device *pdev = NULL; |
| 2894 | struct device_node *node = NULL; |
| 2895 | struct tx_macro_swr_ctrl_data *swr_ctrl_data = NULL, *temp = NULL; |
| 2896 | int ret = 0; |
| 2897 | u16 count = 0, ctrl_num = 0; |
| 2898 | struct tx_macro_swr_ctrl_platform_data *platdata = NULL; |
| 2899 | char plat_dev_name[TX_MACRO_SWR_STRING_LEN] = ""; |
| 2900 | bool tx_swr_master_node = false; |
| 2901 | |
| 2902 | tx_priv = container_of(work, struct tx_macro_priv, |
| 2903 | tx_macro_add_child_devices_work); |
| 2904 | if (!tx_priv) { |
| 2905 | pr_err("%s: Memory for tx_priv does not exist\n", |
| 2906 | __func__); |
| 2907 | return; |
| 2908 | } |
| 2909 | |
| 2910 | if (!tx_priv->dev) { |
| 2911 | pr_err("%s: tx dev does not exist\n", __func__); |
| 2912 | return; |
| 2913 | } |
| 2914 | |
| 2915 | if (!tx_priv->dev->of_node) { |
| 2916 | dev_err(tx_priv->dev, |
| 2917 | "%s: DT node for tx_priv does not exist\n", __func__); |
| 2918 | return; |
| 2919 | } |
| 2920 | |
| 2921 | platdata = &tx_priv->swr_plat_data; |
| 2922 | tx_priv->child_count = 0; |
| 2923 | |
| 2924 | for_each_available_child_of_node(tx_priv->dev->of_node, node) { |
| 2925 | tx_swr_master_node = false; |
| 2926 | if (strnstr(node->name, "tx_swr_master", |
| 2927 | strlen("tx_swr_master")) != NULL) |
| 2928 | tx_swr_master_node = true; |
| 2929 | |
| 2930 | if (tx_swr_master_node) |
| 2931 | strlcpy(plat_dev_name, "tx_swr_ctrl", |
| 2932 | (TX_MACRO_SWR_STRING_LEN - 1)); |
| 2933 | else |
| 2934 | strlcpy(plat_dev_name, node->name, |
| 2935 | (TX_MACRO_SWR_STRING_LEN - 1)); |
| 2936 | |
| 2937 | pdev = platform_device_alloc(plat_dev_name, -1); |
| 2938 | if (!pdev) { |
| 2939 | dev_err(tx_priv->dev, "%s: pdev memory alloc failed\n", |
| 2940 | __func__); |
| 2941 | ret = -ENOMEM; |
| 2942 | goto err; |
| 2943 | } |
| 2944 | pdev->dev.parent = tx_priv->dev; |
| 2945 | pdev->dev.of_node = node; |
| 2946 | |
| 2947 | if (tx_swr_master_node) { |
| 2948 | ret = platform_device_add_data(pdev, platdata, |
| 2949 | sizeof(*platdata)); |
| 2950 | if (ret) { |
| 2951 | dev_err(&pdev->dev, |
| 2952 | "%s: cannot add plat data ctrl:%d\n", |
| 2953 | __func__, ctrl_num); |
| 2954 | goto fail_pdev_add; |
| 2955 | } |
| 2956 | } |
| 2957 | |
| 2958 | ret = platform_device_add(pdev); |
| 2959 | if (ret) { |
| 2960 | dev_err(&pdev->dev, |
| 2961 | "%s: Cannot add platform device\n", |
| 2962 | __func__); |
| 2963 | goto fail_pdev_add; |
| 2964 | } |
| 2965 | |
| 2966 | if (tx_swr_master_node) { |
| 2967 | temp = krealloc(swr_ctrl_data, |
| 2968 | (ctrl_num + 1) * sizeof( |
| 2969 | struct tx_macro_swr_ctrl_data), |
| 2970 | GFP_KERNEL); |
| 2971 | if (!temp) { |
| 2972 | ret = -ENOMEM; |
| 2973 | goto fail_pdev_add; |
| 2974 | } |
| 2975 | swr_ctrl_data = temp; |
| 2976 | swr_ctrl_data[ctrl_num].tx_swr_pdev = pdev; |
| 2977 | ctrl_num++; |
| 2978 | dev_dbg(&pdev->dev, |
| 2979 | "%s: Added soundwire ctrl device(s)\n", |
| 2980 | __func__); |
| 2981 | tx_priv->swr_ctrl_data = swr_ctrl_data; |
| 2982 | } |
| 2983 | if (tx_priv->child_count < TX_MACRO_CHILD_DEVICES_MAX) |
| 2984 | tx_priv->pdev_child_devices[ |
| 2985 | tx_priv->child_count++] = pdev; |
| 2986 | else |
| 2987 | goto err; |
| 2988 | } |
| 2989 | return; |
| 2990 | fail_pdev_add: |
| 2991 | for (count = 0; count < tx_priv->child_count; count++) |
| 2992 | platform_device_put(tx_priv->pdev_child_devices[count]); |
| 2993 | err: |
| 2994 | return; |
| 2995 | } |
| 2996 | |
Sudheer Papothi | a3e969d | 2018-10-27 06:22:10 +0530 | [diff] [blame] | 2997 | static int tx_macro_set_port_map(struct snd_soc_component *component, |
| 2998 | u32 usecase, u32 size, void *data) |
| 2999 | { |
| 3000 | struct device *tx_dev = NULL; |
| 3001 | struct tx_macro_priv *tx_priv = NULL; |
| 3002 | struct swrm_port_config port_cfg; |
| 3003 | int ret = 0; |
| 3004 | |
| 3005 | if (!tx_macro_get_data(component, &tx_dev, &tx_priv, __func__)) |
| 3006 | return -EINVAL; |
| 3007 | |
| 3008 | memset(&port_cfg, 0, sizeof(port_cfg)); |
| 3009 | port_cfg.uc = usecase; |
| 3010 | port_cfg.size = size; |
| 3011 | port_cfg.params = data; |
| 3012 | |
Karthikeyan Mani | 3bd80a5 | 2019-06-04 23:40:16 -0700 | [diff] [blame] | 3013 | if (tx_priv->swr_ctrl_data) |
| 3014 | ret = swrm_wcd_notify( |
| 3015 | tx_priv->swr_ctrl_data[0].tx_swr_pdev, |
| 3016 | SWR_SET_PORT_MAP, &port_cfg); |
Sudheer Papothi | a3e969d | 2018-10-27 06:22:10 +0530 | [diff] [blame] | 3017 | |
| 3018 | return ret; |
| 3019 | } |
| 3020 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3021 | static void tx_macro_init_ops(struct macro_ops *ops, |
| 3022 | char __iomem *tx_io_base) |
| 3023 | { |
| 3024 | memset(ops, 0, sizeof(struct macro_ops)); |
| 3025 | ops->init = tx_macro_init; |
| 3026 | ops->exit = tx_macro_deinit; |
| 3027 | ops->io_base = tx_io_base; |
| 3028 | ops->dai_ptr = tx_macro_dai; |
| 3029 | ops->num_dais = ARRAY_SIZE(tx_macro_dai); |
Laxminath Kasam | fb0d683 | 2018-09-22 01:49:52 +0530 | [diff] [blame] | 3030 | ops->event_handler = tx_macro_event_handler; |
Aditya Bavanari | c4e9612 | 2018-11-14 14:46:38 +0530 | [diff] [blame] | 3031 | ops->reg_wake_irq = tx_macro_reg_wake_irq; |
Sudheer Papothi | a3e969d | 2018-10-27 06:22:10 +0530 | [diff] [blame] | 3032 | ops->set_port_map = tx_macro_set_port_map; |
Sudheer Papothi | d50a581 | 2019-11-21 07:24:42 +0530 | [diff] [blame] | 3033 | ops->clk_div_get = tx_macro_clk_div_get; |
Sudheer Papothi | 6cc7f52 | 2019-06-28 11:04:03 +0530 | [diff] [blame] | 3034 | ops->clk_switch = tx_macro_clk_switch; |
Sudheer Papothi | 06a4c64 | 2019-08-08 05:17:46 +0530 | [diff] [blame] | 3035 | ops->reg_evt_listener = tx_macro_register_event_listener; |
Sudheer Papothi | fc3adb0 | 2019-11-24 10:14:21 +0530 | [diff] [blame] | 3036 | ops->clk_enable = __tx_macro_mclk_enable; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3037 | } |
| 3038 | |
| 3039 | static int tx_macro_probe(struct platform_device *pdev) |
| 3040 | { |
| 3041 | struct macro_ops ops = {0}; |
| 3042 | struct tx_macro_priv *tx_priv = NULL; |
| 3043 | u32 tx_base_addr = 0, sample_rate = 0; |
| 3044 | char __iomem *tx_io_base = NULL; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3045 | int ret = 0; |
| 3046 | const char *dmic_sample_rate = "qcom,tx-dmic-sample-rate"; |
Karthikeyan Mani | 3bd80a5 | 2019-06-04 23:40:16 -0700 | [diff] [blame] | 3047 | u32 is_used_tx_swr_gpio = 1; |
| 3048 | const char *is_used_tx_swr_gpio_dt = "qcom,is-used-swr-gpio"; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3049 | |
| 3050 | tx_priv = devm_kzalloc(&pdev->dev, sizeof(struct tx_macro_priv), |
| 3051 | GFP_KERNEL); |
| 3052 | if (!tx_priv) |
| 3053 | return -ENOMEM; |
| 3054 | platform_set_drvdata(pdev, tx_priv); |
| 3055 | |
| 3056 | tx_priv->dev = &pdev->dev; |
| 3057 | ret = of_property_read_u32(pdev->dev.of_node, "reg", |
| 3058 | &tx_base_addr); |
| 3059 | if (ret) { |
| 3060 | dev_err(&pdev->dev, "%s: could not find %s entry in dt\n", |
| 3061 | __func__, "reg"); |
| 3062 | return ret; |
| 3063 | } |
| 3064 | dev_set_drvdata(&pdev->dev, tx_priv); |
Karthikeyan Mani | 3bd80a5 | 2019-06-04 23:40:16 -0700 | [diff] [blame] | 3065 | if (of_find_property(pdev->dev.of_node, is_used_tx_swr_gpio_dt, |
| 3066 | NULL)) { |
| 3067 | ret = of_property_read_u32(pdev->dev.of_node, |
| 3068 | is_used_tx_swr_gpio_dt, |
| 3069 | &is_used_tx_swr_gpio); |
| 3070 | if (ret) { |
| 3071 | dev_err(&pdev->dev, "%s: error reading %s in dt\n", |
| 3072 | __func__, is_used_tx_swr_gpio_dt); |
| 3073 | is_used_tx_swr_gpio = 1; |
| 3074 | } |
| 3075 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3076 | tx_priv->tx_swr_gpio_p = of_parse_phandle(pdev->dev.of_node, |
| 3077 | "qcom,tx-swr-gpios", 0); |
Karthikeyan Mani | 3bd80a5 | 2019-06-04 23:40:16 -0700 | [diff] [blame] | 3078 | if (!tx_priv->tx_swr_gpio_p && is_used_tx_swr_gpio) { |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3079 | dev_err(&pdev->dev, "%s: swr_gpios handle not provided!\n", |
| 3080 | __func__); |
| 3081 | return -EINVAL; |
| 3082 | } |
Karthikeyan Mani | b44e455 | 2019-09-09 23:06:04 -0700 | [diff] [blame] | 3083 | if (msm_cdc_pinctrl_get_state(tx_priv->tx_swr_gpio_p) < 0 && |
| 3084 | is_used_tx_swr_gpio) { |
Karthikeyan Mani | 326536d | 2019-06-03 13:29:43 -0700 | [diff] [blame] | 3085 | dev_err(&pdev->dev, "%s: failed to get swr pin state\n", |
| 3086 | __func__); |
| 3087 | return -EPROBE_DEFER; |
| 3088 | } |
| 3089 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3090 | tx_io_base = devm_ioremap(&pdev->dev, |
| 3091 | tx_base_addr, TX_MACRO_MAX_OFFSET); |
| 3092 | if (!tx_io_base) { |
| 3093 | dev_err(&pdev->dev, "%s: ioremap failed\n", __func__); |
| 3094 | return -ENOMEM; |
| 3095 | } |
| 3096 | tx_priv->tx_io_base = tx_io_base; |
| 3097 | ret = of_property_read_u32(pdev->dev.of_node, dmic_sample_rate, |
| 3098 | &sample_rate); |
| 3099 | if (ret) { |
| 3100 | dev_err(&pdev->dev, |
| 3101 | "%s: could not find sample_rate entry in dt\n", |
| 3102 | __func__); |
| 3103 | tx_priv->dmic_clk_div = TX_MACRO_CLK_DIV_2; |
| 3104 | } else { |
| 3105 | if (tx_macro_validate_dmic_sample_rate( |
| 3106 | sample_rate, tx_priv) == TX_MACRO_DMIC_SAMPLE_RATE_UNDEFINED) |
| 3107 | return -EINVAL; |
| 3108 | } |
Laxminath Kasam | 2e13d64 | 2019-10-12 01:36:30 +0530 | [diff] [blame] | 3109 | if (is_used_tx_swr_gpio) { |
| 3110 | tx_priv->reset_swr = true; |
| 3111 | INIT_WORK(&tx_priv->tx_macro_add_child_devices_work, |
| 3112 | tx_macro_add_child_devices); |
| 3113 | tx_priv->swr_plat_data.handle = (void *) tx_priv; |
| 3114 | tx_priv->swr_plat_data.read = NULL; |
| 3115 | tx_priv->swr_plat_data.write = NULL; |
| 3116 | tx_priv->swr_plat_data.bulk_write = NULL; |
| 3117 | tx_priv->swr_plat_data.clk = tx_macro_swrm_clock; |
| 3118 | tx_priv->swr_plat_data.core_vote = tx_macro_core_vote; |
| 3119 | tx_priv->swr_plat_data.handle_irq = NULL; |
| 3120 | mutex_init(&tx_priv->swr_clk_lock); |
| 3121 | } |
| 3122 | tx_priv->is_used_tx_swr_gpio = is_used_tx_swr_gpio; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3123 | mutex_init(&tx_priv->mclk_lock); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3124 | tx_macro_init_ops(&ops, tx_io_base); |
Vidyakumar Athota | 5d45f4c | 2019-03-10 22:35:07 -0700 | [diff] [blame] | 3125 | ops.clk_id_req = TX_CORE_CLK; |
| 3126 | ops.default_clk_id = TX_CORE_CLK; |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3127 | ret = bolero_register_macro(&pdev->dev, TX_MACRO, &ops); |
| 3128 | if (ret) { |
| 3129 | dev_err(&pdev->dev, |
| 3130 | "%s: register macro failed\n", __func__); |
| 3131 | goto err_reg_macro; |
| 3132 | } |
Laxminath Kasam | 2e13d64 | 2019-10-12 01:36:30 +0530 | [diff] [blame] | 3133 | if (is_used_tx_swr_gpio) |
| 3134 | schedule_work(&tx_priv->tx_macro_add_child_devices_work); |
Sudheer Papothi | 7601cc6 | 2019-03-30 03:00:52 +0530 | [diff] [blame] | 3135 | pm_runtime_set_autosuspend_delay(&pdev->dev, AUTO_SUSPEND_DELAY); |
| 3136 | pm_runtime_use_autosuspend(&pdev->dev); |
| 3137 | pm_runtime_set_suspended(&pdev->dev); |
Sudheer Papothi | 296867b | 2019-06-20 09:24:09 +0530 | [diff] [blame] | 3138 | pm_suspend_ignore_children(&pdev->dev, true); |
Sudheer Papothi | 7601cc6 | 2019-03-30 03:00:52 +0530 | [diff] [blame] | 3139 | pm_runtime_enable(&pdev->dev); |
| 3140 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3141 | return 0; |
| 3142 | err_reg_macro: |
| 3143 | mutex_destroy(&tx_priv->mclk_lock); |
Laxminath Kasam | 2e13d64 | 2019-10-12 01:36:30 +0530 | [diff] [blame] | 3144 | if (is_used_tx_swr_gpio) |
| 3145 | mutex_destroy(&tx_priv->swr_clk_lock); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3146 | return ret; |
| 3147 | } |
| 3148 | |
| 3149 | static int tx_macro_remove(struct platform_device *pdev) |
| 3150 | { |
| 3151 | struct tx_macro_priv *tx_priv = NULL; |
| 3152 | u16 count = 0; |
| 3153 | |
| 3154 | tx_priv = platform_get_drvdata(pdev); |
| 3155 | |
| 3156 | if (!tx_priv) |
| 3157 | return -EINVAL; |
| 3158 | |
Laxminath Kasam | 2e13d64 | 2019-10-12 01:36:30 +0530 | [diff] [blame] | 3159 | if (tx_priv->is_used_tx_swr_gpio) { |
| 3160 | if (tx_priv->swr_ctrl_data) |
| 3161 | kfree(tx_priv->swr_ctrl_data); |
| 3162 | for (count = 0; count < tx_priv->child_count && |
| 3163 | count < TX_MACRO_CHILD_DEVICES_MAX; count++) |
| 3164 | platform_device_unregister( |
| 3165 | tx_priv->pdev_child_devices[count]); |
| 3166 | } |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3167 | |
Sudheer Papothi | 7601cc6 | 2019-03-30 03:00:52 +0530 | [diff] [blame] | 3168 | pm_runtime_disable(&pdev->dev); |
| 3169 | pm_runtime_set_suspended(&pdev->dev); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3170 | mutex_destroy(&tx_priv->mclk_lock); |
Laxminath Kasam | 2e13d64 | 2019-10-12 01:36:30 +0530 | [diff] [blame] | 3171 | if (tx_priv->is_used_tx_swr_gpio) |
| 3172 | mutex_destroy(&tx_priv->swr_clk_lock); |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3173 | bolero_unregister_macro(&pdev->dev, TX_MACRO); |
| 3174 | return 0; |
| 3175 | } |
| 3176 | |
| 3177 | |
| 3178 | static const struct of_device_id tx_macro_dt_match[] = { |
| 3179 | {.compatible = "qcom,tx-macro"}, |
| 3180 | {} |
| 3181 | }; |
| 3182 | |
Sudheer Papothi | 7601cc6 | 2019-03-30 03:00:52 +0530 | [diff] [blame] | 3183 | static const struct dev_pm_ops bolero_dev_pm_ops = { |
| 3184 | SET_RUNTIME_PM_OPS( |
| 3185 | bolero_runtime_suspend, |
| 3186 | bolero_runtime_resume, |
| 3187 | NULL |
| 3188 | ) |
| 3189 | }; |
| 3190 | |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3191 | static struct platform_driver tx_macro_driver = { |
| 3192 | .driver = { |
| 3193 | .name = "tx_macro", |
| 3194 | .owner = THIS_MODULE, |
Sudheer Papothi | 7601cc6 | 2019-03-30 03:00:52 +0530 | [diff] [blame] | 3195 | .pm = &bolero_dev_pm_ops, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3196 | .of_match_table = tx_macro_dt_match, |
Xiaojun Sang | 53cd13a | 2018-06-29 15:14:37 +0800 | [diff] [blame] | 3197 | .suppress_bind_attrs = true, |
Laxminath Kasam | 989fccf | 2018-06-15 16:53:31 +0530 | [diff] [blame] | 3198 | }, |
| 3199 | .probe = tx_macro_probe, |
| 3200 | .remove = tx_macro_remove, |
| 3201 | }; |
| 3202 | |
| 3203 | module_platform_driver(tx_macro_driver); |
| 3204 | |
| 3205 | MODULE_DESCRIPTION("TX macro driver"); |
| 3206 | MODULE_LICENSE("GPL v2"); |