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gerrit-public.fairphone.software / platform / vendor / opensource / audio-kernel / ec279c75045bf9a729351eebb00e123031d5e52d / . / asoc / sm6150.c
blob: f71ca2d66ffc9e051d5151a8464d1204983b64b0 [file] [log] [blame]
Meng Wang43bbb872018-12-10 12:32:05 +0800[diff] [blame]1// SPDX-License-Identifier: GPL-2.0-only
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]2/*
3 * Copyright (c) 2018, The Linux Foundation. All rights reserved.
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4 */
5
6#include <linux/clk.h>
7#include <linux/delay.h>
8#include <linux/gpio.h>
9#include <linux/of_gpio.h>
10#include <linux/platform_device.h>
11#include <linux/slab.h>
12#include <linux/io.h>
13#include <linux/module.h>
14#include <linux/input.h>
15#include <linux/of_device.h>
16#include <linux/pm_qos.h>
Vatsal Bucha6cb17a02018-08-07 11:07:04 +0530[diff] [blame]17#include <linux/soc/qcom/fsa4480-i2c.h>
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]18#include <sound/core.h>
19#include <sound/soc.h>
20#include <sound/soc-dapm.h>
21#include <sound/pcm.h>
22#include <sound/pcm_params.h>
23#include <sound/info.h>
Vaishnavi Kommaraju9a3d5eb2018-09-19 18:16:39 +0530[diff] [blame]24#include <soc/snd_event.h>
Aditya Bavanari3e19f3c2018-11-12 19:29:50 +0530[diff] [blame]25#include <soc/qcom/socinfo.h>
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]26#include <dsp/q6afe-v2.h>
27#include <dsp/q6core.h>
28#include "device_event.h"
29#include "msm-pcm-routing-v2.h"
30#include "codecs/msm-cdc-pinctrl.h"
31#include "codecs/wcd934x/wcd934x.h"
32#include "codecs/wcd934x/wcd934x-mbhc.h"
Ramprasad Katkam997da402018-08-17 20:20:06 +0530[diff] [blame]33#include "codecs/wcd937x/wcd937x-mbhc.h"
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]34#include "codecs/wsa881x.h"
35#include "codecs/bolero/bolero-cdc.h"
36#include <dt-bindings/sound/audio-codec-port-types.h>
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]37#include "codecs/bolero/wsa-macro.h"
Laxminath Kasam838f0b82018-10-23 20:20:18 +0530[diff] [blame]38#include "codecs/wcd937x/wcd937x.h"
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]39
40#define DRV_NAME "sm6150-asoc-snd"
41
42#define __CHIPSET__ "SM6150 "
43#define MSM_DAILINK_NAME(name) (__CHIPSET__#name)
44
45#define SAMPLING_RATE_8KHZ 8000
46#define SAMPLING_RATE_11P025KHZ 11025
47#define SAMPLING_RATE_16KHZ 16000
48#define SAMPLING_RATE_22P05KHZ 22050
49#define SAMPLING_RATE_32KHZ 32000
50#define SAMPLING_RATE_44P1KHZ 44100
51#define SAMPLING_RATE_48KHZ 48000
52#define SAMPLING_RATE_88P2KHZ 88200
53#define SAMPLING_RATE_96KHZ 96000
54#define SAMPLING_RATE_176P4KHZ 176400
55#define SAMPLING_RATE_192KHZ 192000
56#define SAMPLING_RATE_352P8KHZ 352800
57#define SAMPLING_RATE_384KHZ 384000
58
59#define WCD9XXX_MBHC_DEF_BUTTONS 8
60#define WCD9XXX_MBHC_DEF_RLOADS 5
61#define CODEC_EXT_CLK_RATE 9600000
62#define ADSP_STATE_READY_TIMEOUT_MS 3000
63#define DEV_NAME_STR_LEN 32
64
65#define WSA8810_NAME_1 "wsa881x.20170211"
66#define WSA8810_NAME_2 "wsa881x.20170212"
67#define WCN_CDC_SLIM_RX_CH_MAX 2
68#define WCN_CDC_SLIM_TX_CH_MAX 3
69#define TDM_CHANNEL_MAX 8
70
71#define ADSP_STATE_READY_TIMEOUT_MS 3000
72#define MSM_LL_QOS_VALUE 300 /* time in us to ensure LPM doesn't go in C3/C4 */
73#define MSM_HIFI_ON 1
74
Aditya Bavanari3e19f3c2018-11-12 19:29:50 +0530[diff] [blame]75#define SM6150_SOC_VERSION_1_0 0x00010000
76#define SM6150_SOC_MSM_ID 0x163
77
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]78enum {
79 SLIM_RX_0 = 0,
80 SLIM_RX_1,
81 SLIM_RX_2,
82 SLIM_RX_3,
83 SLIM_RX_4,
84 SLIM_RX_5,
85 SLIM_RX_6,
86 SLIM_RX_7,
87 SLIM_RX_MAX,
88};
89enum {
90 SLIM_TX_0 = 0,
91 SLIM_TX_1,
92 SLIM_TX_2,
93 SLIM_TX_3,
94 SLIM_TX_4,
95 SLIM_TX_5,
96 SLIM_TX_6,
97 SLIM_TX_7,
98 SLIM_TX_8,
99 SLIM_TX_MAX,
100};
101
102enum {
103 PRIM_MI2S = 0,
104 SEC_MI2S,
105 TERT_MI2S,
106 QUAT_MI2S,
107 QUIN_MI2S,
108 MI2S_MAX,
109};
110
111enum {
112 PRIM_AUX_PCM = 0,
113 SEC_AUX_PCM,
114 TERT_AUX_PCM,
115 QUAT_AUX_PCM,
116 QUIN_AUX_PCM,
117 AUX_PCM_MAX,
118};
119
120enum {
121 WSA_CDC_DMA_RX_0 = 0,
122 WSA_CDC_DMA_RX_1,
123 RX_CDC_DMA_RX_0,
124 RX_CDC_DMA_RX_1,
125 RX_CDC_DMA_RX_2,
126 RX_CDC_DMA_RX_3,
127 RX_CDC_DMA_RX_5,
128 CDC_DMA_RX_MAX,
129};
130
131enum {
132 WSA_CDC_DMA_TX_0 = 0,
133 WSA_CDC_DMA_TX_1,
134 WSA_CDC_DMA_TX_2,
135 TX_CDC_DMA_TX_0,
136 TX_CDC_DMA_TX_3,
137 TX_CDC_DMA_TX_4,
138 CDC_DMA_TX_MAX,
139};
140
141struct mi2s_conf {
142 struct mutex lock;
143 u32 ref_cnt;
144 u32 msm_is_mi2s_master;
145};
146
147static u32 mi2s_ebit_clk[MI2S_MAX] = {
148 Q6AFE_LPASS_CLK_ID_PRI_MI2S_EBIT,
149 Q6AFE_LPASS_CLK_ID_SEC_MI2S_EBIT,
150 Q6AFE_LPASS_CLK_ID_TER_MI2S_EBIT,
151 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_EBIT,
152 Q6AFE_LPASS_CLK_ID_QUI_MI2S_EBIT
153};
154
155struct dev_config {
156 u32 sample_rate;
157 u32 bit_format;
158 u32 channels;
159};
160
161enum {
162 DP_RX_IDX = 0,
163 EXT_DISP_RX_IDX_MAX,
164};
165
166struct msm_wsa881x_dev_info {
167 struct device_node *of_node;
168 u32 index;
169};
170
171struct aux_codec_dev_info {
172 struct device_node *of_node;
173 u32 index;
174};
175
176enum pinctrl_pin_state {
177 STATE_DISABLE = 0, /* All pins are in sleep state */
178 STATE_MI2S_ACTIVE, /* I2S = active, TDM = sleep */
179 STATE_TDM_ACTIVE, /* I2S = sleep, TDM = active */
180};
181
182struct msm_pinctrl_info {
183 struct pinctrl *pinctrl;
184 struct pinctrl_state *mi2s_disable;
185 struct pinctrl_state *tdm_disable;
186 struct pinctrl_state *mi2s_active;
187 struct pinctrl_state *tdm_active;
188 enum pinctrl_pin_state curr_state;
189};
190
191struct msm_asoc_mach_data {
192 struct snd_info_entry *codec_root;
193 struct msm_pinctrl_info pinctrl_info;
194 int usbc_en2_gpio; /* used by gpio driver API */
195 struct device_node *dmic01_gpio_p; /* used by pinctrl API */
196 struct device_node *dmic23_gpio_p; /* used by pinctrl API */
197 struct device_node *us_euro_gpio_p; /* used by pinctrl API */
198 struct pinctrl *usbc_en2_gpio_p; /* used by pinctrl API */
199 struct device_node *hph_en1_gpio_p; /* used by pinctrl API */
200 struct device_node *hph_en0_gpio_p; /* used by pinctrl API */
Vaishnavi Kommaraju9a3d5eb2018-09-19 18:16:39 +0530[diff] [blame]201 bool is_afe_config_done;
Vatsal Bucha6cb17a02018-08-07 11:07:04 +0530[diff] [blame]202 struct device_node *fsa_handle;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]203};
204
205struct msm_asoc_wcd93xx_codec {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]206 void* (*get_afe_config_fn)(struct snd_soc_component *component,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]207 enum afe_config_type config_type);
208};
209
210static const char *const pin_states[] = {"sleep", "i2s-active",
211 "tdm-active"};
212
213static struct snd_soc_card snd_soc_card_sm6150_msm;
214
215enum {
216 TDM_0 = 0,
217 TDM_1,
218 TDM_2,
219 TDM_3,
220 TDM_4,
221 TDM_5,
222 TDM_6,
223 TDM_7,
224 TDM_PORT_MAX,
225};
226
227enum {
228 TDM_PRI = 0,
229 TDM_SEC,
230 TDM_TERT,
231 TDM_QUAT,
232 TDM_QUIN,
233 TDM_INTERFACE_MAX,
234};
235
236struct tdm_port {
237 u32 mode;
238 u32 channel;
239};
240
241/* TDM default config */
242static struct dev_config tdm_rx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
243 { /* PRI TDM */
244 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
245 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
246 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
247 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
248 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
249 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
250 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
251 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
252 },
253 { /* SEC TDM */
254 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
255 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
256 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
257 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
258 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
259 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
260 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
261 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
262 },
263 { /* TERT TDM */
264 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
265 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
266 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
267 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
268 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
269 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
270 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
271 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
272 },
273 { /* QUAT TDM */
274 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
275 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
276 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
277 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
278 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
279 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
280 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
281 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
282 },
283 { /* QUIN TDM */
284 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_0 */
285 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_1 */
286 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_2 */
287 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_3 */
288 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_4 */
289 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_5 */
290 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_6 */
291 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* RX_7 */
292 }
293
294};
295
296/* TDM default config */
297static struct dev_config tdm_tx_cfg[TDM_INTERFACE_MAX][TDM_PORT_MAX] = {
298 { /* PRI TDM */
299 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
300 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
301 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
302 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
303 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
304 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
305 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
306 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
307 },
308 { /* SEC TDM */
309 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
310 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
311 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
312 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
313 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
314 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
315 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
316 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
317 },
318 { /* TERT TDM */
319 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
320 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
321 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
322 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
323 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
324 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
325 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
326 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
327 },
328 { /* QUAT TDM */
329 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
330 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
331 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
332 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
333 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
334 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
335 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
336 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
337 },
338 { /* QUIN TDM */
339 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_0 */
340 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_1 */
341 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_2 */
342 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_3 */
343 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_4 */
344 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_5 */
345 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_6 */
346 {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1}, /* TX_7 */
347 }
348};
349
350
351/* Default configuration of slimbus channels */
352static struct dev_config slim_rx_cfg[] = {
353 [SLIM_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
354 [SLIM_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
355 [SLIM_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
356 [SLIM_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
357 [SLIM_RX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
358 [SLIM_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
359 [SLIM_RX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
360 [SLIM_RX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
361};
362
363static struct dev_config slim_tx_cfg[] = {
364 [SLIM_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
365 [SLIM_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
366 [SLIM_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
367 [SLIM_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
368 [SLIM_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
369 [SLIM_TX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
370 [SLIM_TX_6] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
371 [SLIM_TX_7] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
372 [SLIM_TX_8] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
373};
374
375/* Default configuration of Codec DMA Interface Tx */
376static struct dev_config cdc_dma_rx_cfg[] = {
377 [WSA_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
378 [WSA_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
379 [RX_CDC_DMA_RX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
380 [RX_CDC_DMA_RX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
381 [RX_CDC_DMA_RX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
382 [RX_CDC_DMA_RX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
383 [RX_CDC_DMA_RX_5] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
384};
385
386/* Default configuration of Codec DMA Interface Rx */
387static struct dev_config cdc_dma_tx_cfg[] = {
388 [WSA_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
389 [WSA_CDC_DMA_TX_1] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
390 [WSA_CDC_DMA_TX_2] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
391 [TX_CDC_DMA_TX_0] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
392 [TX_CDC_DMA_TX_3] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
393 [TX_CDC_DMA_TX_4] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
394};
395
396/* Default configuration of external display BE */
397static struct dev_config ext_disp_rx_cfg[] = {
398 [DP_RX_IDX] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
399};
400
401static struct dev_config usb_rx_cfg = {
402 .sample_rate = SAMPLING_RATE_48KHZ,
403 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
404 .channels = 2,
405};
406
407static struct dev_config usb_tx_cfg = {
408 .sample_rate = SAMPLING_RATE_48KHZ,
409 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
410 .channels = 1,
411};
412
413static struct dev_config proxy_rx_cfg = {
414 .sample_rate = SAMPLING_RATE_48KHZ,
415 .bit_format = SNDRV_PCM_FORMAT_S16_LE,
416 .channels = 2,
417};
418
419/* Default configuration of MI2S channels */
420static struct dev_config mi2s_rx_cfg[] = {
421 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
422 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
423 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
424 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
425 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 2},
426};
427
428static struct dev_config mi2s_tx_cfg[] = {
429 [PRIM_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
430 [SEC_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
431 [TERT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
432 [QUAT_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
433 [QUIN_MI2S] = {SAMPLING_RATE_48KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
434};
435
436static struct dev_config aux_pcm_rx_cfg[] = {
437 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
438 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
439 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
440 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
441 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
442};
443
444static struct dev_config aux_pcm_tx_cfg[] = {
445 [PRIM_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
446 [SEC_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
447 [TERT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
448 [QUAT_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
449 [QUIN_AUX_PCM] = {SAMPLING_RATE_8KHZ, SNDRV_PCM_FORMAT_S16_LE, 1},
450};
451static int msm_vi_feed_tx_ch = 2;
452static const char *const slim_rx_ch_text[] = {"One", "Two"};
453static const char *const slim_tx_ch_text[] = {"One", "Two", "Three", "Four",
454 "Five", "Six", "Seven",
455 "Eight"};
456static const char *const vi_feed_ch_text[] = {"One", "Two"};
457static char const *bit_format_text[] = {"S16_LE", "S24_LE", "S24_3LE",
458 "S32_LE"};
459static char const *ext_disp_bit_format_text[] = {"S16_LE", "S24_LE",
460 "S24_3LE"};
461static char const *slim_sample_rate_text[] = {"KHZ_8", "KHZ_16",
462 "KHZ_32", "KHZ_44P1", "KHZ_48",
463 "KHZ_88P2", "KHZ_96", "KHZ_176P4",
464 "KHZ_192", "KHZ_352P8", "KHZ_384"};
465static char const *bt_sample_rate_text[] = {"KHZ_8", "KHZ_16",
466 "KHZ_44P1", "KHZ_48",
467 "KHZ_88P2", "KHZ_96"};
Sharad Sangle493a1b32018-09-19 15:52:15 +0530[diff] [blame]468static char const *bt_sample_rate_rx_text[] = {"KHZ_8", "KHZ_16",
469 "KHZ_44P1", "KHZ_48",
470 "KHZ_88P2", "KHZ_96"};
471static char const *bt_sample_rate_tx_text[] = {"KHZ_8", "KHZ_16",
472 "KHZ_44P1", "KHZ_48",
473 "KHZ_88P2", "KHZ_96"};
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]474static const char *const usb_ch_text[] = {"One", "Two", "Three", "Four",
475 "Five", "Six", "Seven",
476 "Eight"};
477static char const *ch_text[] = {"Two", "Three", "Four", "Five",
478 "Six", "Seven", "Eight"};
479static char const *usb_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
480 "KHZ_16", "KHZ_22P05",
481 "KHZ_32", "KHZ_44P1", "KHZ_48",
482 "KHZ_88P2", "KHZ_96", "KHZ_176P4",
483 "KHZ_192", "KHZ_352P8", "KHZ_384"};
484static char const *ext_disp_sample_rate_text[] = {"KHZ_48", "KHZ_96",
485 "KHZ_192", "KHZ_32", "KHZ_44P1",
486 "KHZ_88P2", "KHZ_176P4" };
487static char const *tdm_ch_text[] = {"One", "Two", "Three", "Four",
488 "Five", "Six", "Seven", "Eight"};
489static char const *tdm_bit_format_text[] = {"S16_LE", "S24_LE", "S32_LE"};
490static char const *tdm_sample_rate_text[] = {"KHZ_8", "KHZ_16", "KHZ_32",
491 "KHZ_48", "KHZ_176P4",
492 "KHZ_352P8"};
493static const char *const auxpcm_rate_text[] = {"KHZ_8", "KHZ_16"};
494static char const *mi2s_rate_text[] = {"KHZ_8", "KHZ_11P025", "KHZ_16",
495 "KHZ_22P05", "KHZ_32", "KHZ_44P1",
496 "KHZ_48", "KHZ_96", "KHZ_192"};
497static const char *const mi2s_ch_text[] = {"One", "Two", "Three", "Four",
498 "Five", "Six", "Seven",
499 "Eight"};
500static const char *const hifi_text[] = {"Off", "On"};
501static const char *const qos_text[] = {"Disable", "Enable"};
502
503static const char *const cdc_dma_rx_ch_text[] = {"One", "Two"};
504static const char *const cdc_dma_tx_ch_text[] = {"One", "Two", "Three", "Four",
505 "Five", "Six", "Seven",
506 "Eight"};
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]507static char const *cdc_dma_sample_rate_text[] = {"KHZ_8", "KHZ_11P025",
508 "KHZ_16", "KHZ_22P05",
509 "KHZ_32", "KHZ_44P1", "KHZ_48",
510 "KHZ_88P2", "KHZ_96",
511 "KHZ_176P4", "KHZ_192",
512 "KHZ_352P8", "KHZ_384"};
513
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]514
515static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_chs, slim_rx_ch_text);
516static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_chs, slim_rx_ch_text);
517static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_chs, slim_tx_ch_text);
518static SOC_ENUM_SINGLE_EXT_DECL(slim_1_tx_chs, slim_tx_ch_text);
519static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_chs, slim_rx_ch_text);
520static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_chs, slim_rx_ch_text);
521static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_chs, usb_ch_text);
522static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_chs, usb_ch_text);
523static SOC_ENUM_SINGLE_EXT_DECL(vi_feed_tx_chs, vi_feed_ch_text);
524static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_chs, ch_text);
525static SOC_ENUM_SINGLE_EXT_DECL(proxy_rx_chs, ch_text);
526static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_format, bit_format_text);
527static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_format, bit_format_text);
528static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_format, bit_format_text);
529static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_format, bit_format_text);
530static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_format, bit_format_text);
531static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_format, bit_format_text);
532static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_format, ext_disp_bit_format_text);
533static SOC_ENUM_SINGLE_EXT_DECL(slim_0_rx_sample_rate, slim_sample_rate_text);
534static SOC_ENUM_SINGLE_EXT_DECL(slim_2_rx_sample_rate, slim_sample_rate_text);
535static SOC_ENUM_SINGLE_EXT_DECL(slim_0_tx_sample_rate, slim_sample_rate_text);
536static SOC_ENUM_SINGLE_EXT_DECL(slim_5_rx_sample_rate, slim_sample_rate_text);
537static SOC_ENUM_SINGLE_EXT_DECL(slim_6_rx_sample_rate, slim_sample_rate_text);
538static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate, bt_sample_rate_text);
Sharad Sangle493a1b32018-09-19 15:52:15 +0530[diff] [blame]539static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_rx, bt_sample_rate_rx_text);
540static SOC_ENUM_SINGLE_EXT_DECL(bt_sample_rate_tx, bt_sample_rate_tx_text);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]541static SOC_ENUM_SINGLE_EXT_DECL(usb_rx_sample_rate, usb_sample_rate_text);
542static SOC_ENUM_SINGLE_EXT_DECL(usb_tx_sample_rate, usb_sample_rate_text);
543static SOC_ENUM_SINGLE_EXT_DECL(ext_disp_rx_sample_rate,
544 ext_disp_sample_rate_text);
545static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_chs, tdm_ch_text);
546static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_format, tdm_bit_format_text);
547static SOC_ENUM_SINGLE_EXT_DECL(tdm_tx_sample_rate, tdm_sample_rate_text);
548static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_chs, tdm_ch_text);
549static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_format, tdm_bit_format_text);
550static SOC_ENUM_SINGLE_EXT_DECL(tdm_rx_sample_rate, tdm_sample_rate_text);
551static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_rx_sample_rate, auxpcm_rate_text);
552static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_rx_sample_rate, auxpcm_rate_text);
553static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_rx_sample_rate, auxpcm_rate_text);
554static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_rx_sample_rate, auxpcm_rate_text);
555static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_rx_sample_rate, auxpcm_rate_text);
556static SOC_ENUM_SINGLE_EXT_DECL(prim_aux_pcm_tx_sample_rate, auxpcm_rate_text);
557static SOC_ENUM_SINGLE_EXT_DECL(sec_aux_pcm_tx_sample_rate, auxpcm_rate_text);
558static SOC_ENUM_SINGLE_EXT_DECL(tert_aux_pcm_tx_sample_rate, auxpcm_rate_text);
559static SOC_ENUM_SINGLE_EXT_DECL(quat_aux_pcm_tx_sample_rate, auxpcm_rate_text);
560static SOC_ENUM_SINGLE_EXT_DECL(quin_aux_pcm_tx_sample_rate, auxpcm_rate_text);
561static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_sample_rate, mi2s_rate_text);
562static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_sample_rate, mi2s_rate_text);
563static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_sample_rate, mi2s_rate_text);
564static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_sample_rate, mi2s_rate_text);
565static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_sample_rate, mi2s_rate_text);
566static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_sample_rate, mi2s_rate_text);
567static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_sample_rate, mi2s_rate_text);
568static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_sample_rate, mi2s_rate_text);
569static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_sample_rate, mi2s_rate_text);
570static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_sample_rate, mi2s_rate_text);
571static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_rx_chs, mi2s_ch_text);
572static SOC_ENUM_SINGLE_EXT_DECL(prim_mi2s_tx_chs, mi2s_ch_text);
573static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_rx_chs, mi2s_ch_text);
574static SOC_ENUM_SINGLE_EXT_DECL(sec_mi2s_tx_chs, mi2s_ch_text);
575static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_rx_chs, mi2s_ch_text);
576static SOC_ENUM_SINGLE_EXT_DECL(tert_mi2s_tx_chs, mi2s_ch_text);
577static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_rx_chs, mi2s_ch_text);
578static SOC_ENUM_SINGLE_EXT_DECL(quat_mi2s_tx_chs, mi2s_ch_text);
579static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_rx_chs, mi2s_ch_text);
580static SOC_ENUM_SINGLE_EXT_DECL(quin_mi2s_tx_chs, mi2s_ch_text);
581static SOC_ENUM_SINGLE_EXT_DECL(mi2s_rx_format, bit_format_text);
582static SOC_ENUM_SINGLE_EXT_DECL(mi2s_tx_format, bit_format_text);
583static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_rx_format, bit_format_text);
584static SOC_ENUM_SINGLE_EXT_DECL(aux_pcm_tx_format, bit_format_text);
585static SOC_ENUM_SINGLE_EXT_DECL(hifi_function, hifi_text);
586static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
587static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
588static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_chs, cdc_dma_rx_ch_text);
589static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_chs, cdc_dma_rx_ch_text);
590static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_chs, cdc_dma_rx_ch_text);
591static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_chs, cdc_dma_rx_ch_text);
592static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_chs, cdc_dma_rx_ch_text);
593static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
594static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_chs, cdc_dma_tx_ch_text);
595static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_chs, cdc_dma_tx_ch_text);
596static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_chs, cdc_dma_tx_ch_text);
597static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_chs, cdc_dma_tx_ch_text);
598static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_chs, cdc_dma_tx_ch_text);
599static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_format, bit_format_text);
600static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_format, bit_format_text);
601static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_format, bit_format_text);
602static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_format, bit_format_text);
603static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_format, bit_format_text);
604static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_format, bit_format_text);
605static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_format, bit_format_text);
606static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_format, bit_format_text);
607static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_format, bit_format_text);
608static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_format, bit_format_text);
609static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_format, bit_format_text);
610static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_format, bit_format_text);
611static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_0_sample_rate,
612 cdc_dma_sample_rate_text);
613static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_rx_1_sample_rate,
614 cdc_dma_sample_rate_text);
615static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_0_sample_rate,
616 cdc_dma_sample_rate_text);
617static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_1_sample_rate,
618 cdc_dma_sample_rate_text);
619static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_2_sample_rate,
620 cdc_dma_sample_rate_text);
621static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_3_sample_rate,
622 cdc_dma_sample_rate_text);
623static SOC_ENUM_SINGLE_EXT_DECL(rx_cdc_dma_rx_5_sample_rate,
624 cdc_dma_sample_rate_text);
625static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_0_sample_rate,
626 cdc_dma_sample_rate_text);
627static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_1_sample_rate,
628 cdc_dma_sample_rate_text);
629static SOC_ENUM_SINGLE_EXT_DECL(wsa_cdc_dma_tx_2_sample_rate,
630 cdc_dma_sample_rate_text);
631static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_0_sample_rate,
632 cdc_dma_sample_rate_text);
633static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_3_sample_rate,
634 cdc_dma_sample_rate_text);
635static SOC_ENUM_SINGLE_EXT_DECL(tx_cdc_dma_tx_4_sample_rate,
636 cdc_dma_sample_rate_text);
637
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]638static int msm_hifi_control;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]639static bool codec_reg_done;
640static struct snd_soc_aux_dev *msm_aux_dev;
641static struct snd_soc_codec_conf *msm_codec_conf;
642static struct msm_asoc_wcd93xx_codec msm_codec_fn;
643
644static int dmic_0_1_gpio_cnt;
645static int dmic_2_3_gpio_cnt;
646
647static void *def_wcd_mbhc_cal(void);
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]648static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]649 int enable, bool dapm);
650static int msm_wsa881x_init(struct snd_soc_component *component);
651static int msm_aux_codec_init(struct snd_soc_component *component);
652
653/*
654 * Need to report LINEIN
655 * if R/L channel impedance is larger than 5K ohm
656 */
657static struct wcd_mbhc_config wcd_mbhc_cfg = {
658 .read_fw_bin = false,
659 .calibration = NULL,
660 .detect_extn_cable = true,
661 .mono_stero_detection = false,
662 .swap_gnd_mic = NULL,
663 .hs_ext_micbias = true,
664 .key_code[0] = KEY_MEDIA,
665 .key_code[1] = KEY_VOICECOMMAND,
666 .key_code[2] = KEY_VOLUMEUP,
667 .key_code[3] = KEY_VOLUMEDOWN,
668 .key_code[4] = 0,
669 .key_code[5] = 0,
670 .key_code[6] = 0,
671 .key_code[7] = 0,
672 .linein_th = 5000,
673 .moisture_en = true,
674 .mbhc_micbias = MIC_BIAS_2,
675 .anc_micbias = MIC_BIAS_2,
676 .enable_anc_mic_detect = false,
677};
678
679static struct snd_soc_dapm_route wcd_audio_paths_tavil[] = {
680 {"MIC BIAS1", NULL, "MCLK TX"},
681 {"MIC BIAS2", NULL, "MCLK TX"},
682 {"MIC BIAS3", NULL, "MCLK TX"},
683 {"MIC BIAS4", NULL, "MCLK TX"},
684};
685
686static struct afe_clk_set mi2s_clk[MI2S_MAX] = {
687 {
688 AFE_API_VERSION_I2S_CONFIG,
689 Q6AFE_LPASS_CLK_ID_PRI_MI2S_IBIT,
690 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
691 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
692 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
693 0,
694 },
695 {
696 AFE_API_VERSION_I2S_CONFIG,
697 Q6AFE_LPASS_CLK_ID_SEC_MI2S_IBIT,
698 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
699 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
700 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
701 0,
702 },
703 {
704 AFE_API_VERSION_I2S_CONFIG,
705 Q6AFE_LPASS_CLK_ID_TER_MI2S_IBIT,
706 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
707 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
708 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
709 0,
710 },
711 {
712 AFE_API_VERSION_I2S_CONFIG,
713 Q6AFE_LPASS_CLK_ID_QUAD_MI2S_IBIT,
714 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
715 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
716 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
717 0,
718 },
719 {
720 AFE_API_VERSION_I2S_CONFIG,
721 Q6AFE_LPASS_CLK_ID_QUI_MI2S_IBIT,
722 Q6AFE_LPASS_IBIT_CLK_1_P536_MHZ,
723 Q6AFE_LPASS_CLK_ATTRIBUTE_COUPLE_NO,
724 Q6AFE_LPASS_CLK_ROOT_DEFAULT,
725 0,
726 }
727
728};
729
730static struct mi2s_conf mi2s_intf_conf[MI2S_MAX];
731
732static int slim_get_sample_rate_val(int sample_rate)
733{
734 int sample_rate_val = 0;
735
736 switch (sample_rate) {
737 case SAMPLING_RATE_8KHZ:
738 sample_rate_val = 0;
739 break;
740 case SAMPLING_RATE_16KHZ:
741 sample_rate_val = 1;
742 break;
743 case SAMPLING_RATE_32KHZ:
744 sample_rate_val = 2;
745 break;
746 case SAMPLING_RATE_44P1KHZ:
747 sample_rate_val = 3;
748 break;
749 case SAMPLING_RATE_48KHZ:
750 sample_rate_val = 4;
751 break;
752 case SAMPLING_RATE_88P2KHZ:
753 sample_rate_val = 5;
754 break;
755 case SAMPLING_RATE_96KHZ:
756 sample_rate_val = 6;
757 break;
758 case SAMPLING_RATE_176P4KHZ:
759 sample_rate_val = 7;
760 break;
761 case SAMPLING_RATE_192KHZ:
762 sample_rate_val = 8;
763 break;
764 case SAMPLING_RATE_352P8KHZ:
765 sample_rate_val = 9;
766 break;
767 case SAMPLING_RATE_384KHZ:
768 sample_rate_val = 10;
769 break;
770 default:
771 sample_rate_val = 4;
772 break;
773 }
774 return sample_rate_val;
775}
776
777static int slim_get_sample_rate(int value)
778{
779 int sample_rate = 0;
780
781 switch (value) {
782 case 0:
783 sample_rate = SAMPLING_RATE_8KHZ;
784 break;
785 case 1:
786 sample_rate = SAMPLING_RATE_16KHZ;
787 break;
788 case 2:
789 sample_rate = SAMPLING_RATE_32KHZ;
790 break;
791 case 3:
792 sample_rate = SAMPLING_RATE_44P1KHZ;
793 break;
794 case 4:
795 sample_rate = SAMPLING_RATE_48KHZ;
796 break;
797 case 5:
798 sample_rate = SAMPLING_RATE_88P2KHZ;
799 break;
800 case 6:
801 sample_rate = SAMPLING_RATE_96KHZ;
802 break;
803 case 7:
804 sample_rate = SAMPLING_RATE_176P4KHZ;
805 break;
806 case 8:
807 sample_rate = SAMPLING_RATE_192KHZ;
808 break;
809 case 9:
810 sample_rate = SAMPLING_RATE_352P8KHZ;
811 break;
812 case 10:
813 sample_rate = SAMPLING_RATE_384KHZ;
814 break;
815 default:
816 sample_rate = SAMPLING_RATE_48KHZ;
817 break;
818 }
819 return sample_rate;
820}
821
822static int slim_get_bit_format_val(int bit_format)
823{
824 int val = 0;
825
826 switch (bit_format) {
827 case SNDRV_PCM_FORMAT_S32_LE:
828 val = 3;
829 break;
830 case SNDRV_PCM_FORMAT_S24_3LE:
831 val = 2;
832 break;
833 case SNDRV_PCM_FORMAT_S24_LE:
834 val = 1;
835 break;
836 case SNDRV_PCM_FORMAT_S16_LE:
837 default:
838 val = 0;
839 break;
840 }
841 return val;
842}
843
844static int slim_get_bit_format(int val)
845{
846 int bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
847
848 switch (val) {
849 case 0:
850 bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
851 break;
852 case 1:
853 bit_fmt = SNDRV_PCM_FORMAT_S24_LE;
854 break;
855 case 2:
856 bit_fmt = SNDRV_PCM_FORMAT_S24_3LE;
857 break;
858 case 3:
859 bit_fmt = SNDRV_PCM_FORMAT_S32_LE;
860 break;
861 default:
862 bit_fmt = SNDRV_PCM_FORMAT_S16_LE;
863 break;
864 }
865 return bit_fmt;
866}
867
868static int slim_get_port_idx(struct snd_kcontrol *kcontrol)
869{
870 int port_id = 0;
871
872 if (strnstr(kcontrol->id.name, "SLIM_0_RX", sizeof("SLIM_0_RX"))) {
873 port_id = SLIM_RX_0;
874 } else if (strnstr(kcontrol->id.name,
875 "SLIM_2_RX", sizeof("SLIM_2_RX"))) {
876 port_id = SLIM_RX_2;
877 } else if (strnstr(kcontrol->id.name,
878 "SLIM_5_RX", sizeof("SLIM_5_RX"))) {
879 port_id = SLIM_RX_5;
880 } else if (strnstr(kcontrol->id.name,
881 "SLIM_6_RX", sizeof("SLIM_6_RX"))) {
882 port_id = SLIM_RX_6;
883 } else if (strnstr(kcontrol->id.name,
884 "SLIM_0_TX", sizeof("SLIM_0_TX"))) {
885 port_id = SLIM_TX_0;
886 } else if (strnstr(kcontrol->id.name,
887 "SLIM_1_TX", sizeof("SLIM_1_TX"))) {
888 port_id = SLIM_TX_1;
889 } else {
890 pr_err("%s: unsupported channel: %s\n",
891 __func__, kcontrol->id.name);
892 return -EINVAL;
893 }
894
895 return port_id;
896}
897
898static int slim_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
899 struct snd_ctl_elem_value *ucontrol)
900{
901 int ch_num = slim_get_port_idx(kcontrol);
902
903 if (ch_num < 0)
904 return ch_num;
905
906 ucontrol->value.enumerated.item[0] =
907 slim_get_sample_rate_val(slim_rx_cfg[ch_num].sample_rate);
908
909 pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
910 ch_num, slim_rx_cfg[ch_num].sample_rate,
911 ucontrol->value.enumerated.item[0]);
912
913 return 0;
914}
915
916static int slim_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
917 struct snd_ctl_elem_value *ucontrol)
918{
919 int ch_num = slim_get_port_idx(kcontrol);
920
921 if (ch_num < 0)
922 return ch_num;
923
924 slim_rx_cfg[ch_num].sample_rate =
925 slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
926
927 pr_debug("%s: slim[%d]_rx_sample_rate = %d, item = %d\n", __func__,
928 ch_num, slim_rx_cfg[ch_num].sample_rate,
929 ucontrol->value.enumerated.item[0]);
930
931 return 0;
932}
933
934static int slim_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
935 struct snd_ctl_elem_value *ucontrol)
936{
937 int ch_num = slim_get_port_idx(kcontrol);
938
939 if (ch_num < 0)
940 return ch_num;
941
942 ucontrol->value.enumerated.item[0] =
943 slim_get_sample_rate_val(slim_tx_cfg[ch_num].sample_rate);
944
945 pr_debug("%s: slim[%d]_tx_sample_rate = %d, item = %d\n", __func__,
946 ch_num, slim_tx_cfg[ch_num].sample_rate,
947 ucontrol->value.enumerated.item[0]);
948
949 return 0;
950}
951
952static int slim_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
953 struct snd_ctl_elem_value *ucontrol)
954{
955 int sample_rate = 0;
956 int ch_num = slim_get_port_idx(kcontrol);
957
958 if (ch_num < 0)
959 return ch_num;
960
961 sample_rate = slim_get_sample_rate(ucontrol->value.enumerated.item[0]);
962 if (sample_rate == SAMPLING_RATE_44P1KHZ) {
963 pr_err("%s: Unsupported sample rate %d: for Tx path\n",
964 __func__, sample_rate);
965 return -EINVAL;
966 }
967 slim_tx_cfg[ch_num].sample_rate = sample_rate;
968
969 pr_debug("%s: slim[%d]_tx_sample_rate = %d, value = %d\n", __func__,
970 ch_num, slim_tx_cfg[ch_num].sample_rate,
971 ucontrol->value.enumerated.item[0]);
972
973 return 0;
974}
975
976static int slim_rx_bit_format_get(struct snd_kcontrol *kcontrol,
977 struct snd_ctl_elem_value *ucontrol)
978{
979 int ch_num = slim_get_port_idx(kcontrol);
980
981 if (ch_num < 0)
982 return ch_num;
983
984 ucontrol->value.enumerated.item[0] =
985 slim_get_bit_format_val(slim_rx_cfg[ch_num].bit_format);
986
987 pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
988 __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
989 ucontrol->value.enumerated.item[0]);
990
991 return 0;
992}
993
994static int slim_rx_bit_format_put(struct snd_kcontrol *kcontrol,
995 struct snd_ctl_elem_value *ucontrol)
996{
997 int ch_num = slim_get_port_idx(kcontrol);
998
999 if (ch_num < 0)
1000 return ch_num;
1001
1002 slim_rx_cfg[ch_num].bit_format =
1003 slim_get_bit_format(ucontrol->value.enumerated.item[0]);
1004
1005 pr_debug("%s: slim[%d]_rx_bit_format = %d, ucontrol value = %d\n",
1006 __func__, ch_num, slim_rx_cfg[ch_num].bit_format,
1007 ucontrol->value.enumerated.item[0]);
1008
1009 return 0;
1010}
1011
1012static int slim_tx_bit_format_get(struct snd_kcontrol *kcontrol,
1013 struct snd_ctl_elem_value *ucontrol)
1014{
1015 int ch_num = slim_get_port_idx(kcontrol);
1016
1017 if (ch_num < 0)
1018 return ch_num;
1019
1020 ucontrol->value.enumerated.item[0] =
1021 slim_get_bit_format_val(slim_tx_cfg[ch_num].bit_format);
1022
1023 pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
1024 __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
1025 ucontrol->value.enumerated.item[0]);
1026
1027 return 0;
1028}
1029
1030static int slim_tx_bit_format_put(struct snd_kcontrol *kcontrol,
1031 struct snd_ctl_elem_value *ucontrol)
1032{
1033 int ch_num = slim_get_port_idx(kcontrol);
1034
1035 if (ch_num < 0)
1036 return ch_num;
1037
1038 slim_tx_cfg[ch_num].bit_format =
1039 slim_get_bit_format(ucontrol->value.enumerated.item[0]);
1040
1041 pr_debug("%s: slim[%d]_tx_bit_format = %d, ucontrol value = %d\n",
1042 __func__, ch_num, slim_tx_cfg[ch_num].bit_format,
1043 ucontrol->value.enumerated.item[0]);
1044
1045 return 0;
1046}
1047
1048static int slim_rx_ch_get(struct snd_kcontrol *kcontrol,
1049 struct snd_ctl_elem_value *ucontrol)
1050{
1051 int ch_num = slim_get_port_idx(kcontrol);
1052
1053 if (ch_num < 0)
1054 return ch_num;
1055
1056 pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
1057 ch_num, slim_rx_cfg[ch_num].channels);
1058 ucontrol->value.enumerated.item[0] = slim_rx_cfg[ch_num].channels - 1;
1059
1060 return 0;
1061}
1062
1063static int slim_rx_ch_put(struct snd_kcontrol *kcontrol,
1064 struct snd_ctl_elem_value *ucontrol)
1065{
1066 int ch_num = slim_get_port_idx(kcontrol);
1067
1068 if (ch_num < 0)
1069 return ch_num;
1070
1071 slim_rx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
1072 pr_debug("%s: msm_slim_[%d]_rx_ch = %d\n", __func__,
1073 ch_num, slim_rx_cfg[ch_num].channels);
1074
1075 return 1;
1076}
1077
1078static int slim_tx_ch_get(struct snd_kcontrol *kcontrol,
1079 struct snd_ctl_elem_value *ucontrol)
1080{
1081 int ch_num = slim_get_port_idx(kcontrol);
1082
1083 if (ch_num < 0)
1084 return ch_num;
1085
1086 pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
1087 ch_num, slim_tx_cfg[ch_num].channels);
1088 ucontrol->value.enumerated.item[0] = slim_tx_cfg[ch_num].channels - 1;
1089
1090 return 0;
1091}
1092
1093static int slim_tx_ch_put(struct snd_kcontrol *kcontrol,
1094 struct snd_ctl_elem_value *ucontrol)
1095{
1096 int ch_num = slim_get_port_idx(kcontrol);
1097
1098 if (ch_num < 0)
1099 return ch_num;
1100
1101 slim_tx_cfg[ch_num].channels = ucontrol->value.enumerated.item[0] + 1;
1102 pr_debug("%s: msm_slim_[%d]_tx_ch = %d\n", __func__,
1103 ch_num, slim_tx_cfg[ch_num].channels);
1104
1105 return 1;
1106}
1107
1108static int msm_vi_feed_tx_ch_get(struct snd_kcontrol *kcontrol,
1109 struct snd_ctl_elem_value *ucontrol)
1110{
1111 ucontrol->value.integer.value[0] = msm_vi_feed_tx_ch - 1;
1112 pr_debug("%s: msm_vi_feed_tx_ch = %ld\n", __func__,
1113 ucontrol->value.integer.value[0]);
1114 return 0;
1115}
1116
1117static int msm_vi_feed_tx_ch_put(struct snd_kcontrol *kcontrol,
1118 struct snd_ctl_elem_value *ucontrol)
1119{
1120 msm_vi_feed_tx_ch = ucontrol->value.integer.value[0] + 1;
1121
1122 pr_debug("%s: msm_vi_feed_tx_ch = %d\n", __func__, msm_vi_feed_tx_ch);
1123 return 1;
1124}
1125
1126static int msm_bt_sample_rate_get(struct snd_kcontrol *kcontrol,
1127 struct snd_ctl_elem_value *ucontrol)
1128{
1129 /*
1130 * Slimbus_7_Rx/Tx sample rate values should always be in sync (same)
1131 * when used for BT_SCO use case. Return either Rx or Tx sample rate
1132 * value.
1133 */
1134 switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
1135 case SAMPLING_RATE_96KHZ:
1136 ucontrol->value.integer.value[0] = 5;
1137 break;
1138 case SAMPLING_RATE_88P2KHZ:
1139 ucontrol->value.integer.value[0] = 4;
1140 break;
1141 case SAMPLING_RATE_48KHZ:
1142 ucontrol->value.integer.value[0] = 3;
1143 break;
1144 case SAMPLING_RATE_44P1KHZ:
1145 ucontrol->value.integer.value[0] = 2;
1146 break;
1147 case SAMPLING_RATE_16KHZ:
1148 ucontrol->value.integer.value[0] = 1;
1149 break;
1150 case SAMPLING_RATE_8KHZ:
1151 default:
1152 ucontrol->value.integer.value[0] = 0;
1153 break;
1154 }
1155 pr_debug("%s: sample rate = %d\n", __func__,
1156 slim_rx_cfg[SLIM_RX_7].sample_rate);
1157
1158 return 0;
1159}
1160
1161static int msm_bt_sample_rate_put(struct snd_kcontrol *kcontrol,
1162 struct snd_ctl_elem_value *ucontrol)
1163{
1164 switch (ucontrol->value.integer.value[0]) {
1165 case 1:
1166 slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
1167 slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
1168 break;
1169 case 2:
1170 slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
1171 slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
1172 break;
1173 case 3:
1174 slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
1175 slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
1176 break;
1177 case 4:
1178 slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
1179 slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
1180 break;
1181 case 5:
1182 slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
1183 slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
1184 break;
1185 case 0:
1186 default:
1187 slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
1188 slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
1189 break;
1190 }
1191 pr_debug("%s: sample rates: slim7_rx = %d, slim7_tx = %d, value = %d\n",
1192 __func__,
1193 slim_rx_cfg[SLIM_RX_7].sample_rate,
1194 slim_tx_cfg[SLIM_TX_7].sample_rate,
1195 ucontrol->value.enumerated.item[0]);
1196
1197 return 0;
1198}
Sharad Sangle493a1b32018-09-19 15:52:15 +0530[diff] [blame]1199static int msm_bt_sample_rate_rx_get(struct snd_kcontrol *kcontrol,
1200 struct snd_ctl_elem_value *ucontrol)
1201{
1202 switch (slim_rx_cfg[SLIM_RX_7].sample_rate) {
1203 case SAMPLING_RATE_96KHZ:
1204 ucontrol->value.integer.value[0] = 5;
1205 break;
1206 case SAMPLING_RATE_88P2KHZ:
1207 ucontrol->value.integer.value[0] = 4;
1208 break;
1209 case SAMPLING_RATE_48KHZ:
1210 ucontrol->value.integer.value[0] = 3;
1211 break;
1212 case SAMPLING_RATE_44P1KHZ:
1213 ucontrol->value.integer.value[0] = 2;
1214 break;
1215 case SAMPLING_RATE_16KHZ:
1216 ucontrol->value.integer.value[0] = 1;
1217 break;
1218 case SAMPLING_RATE_8KHZ:
1219 default:
1220 ucontrol->value.integer.value[0] = 0;
1221 break;
1222 }
1223 pr_debug("%s: sample rate rx = %d", __func__,
1224 slim_rx_cfg[SLIM_RX_7].sample_rate);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1225
Sharad Sangle493a1b32018-09-19 15:52:15 +0530[diff] [blame]1226 return 0;
1227}
1228
1229static int msm_bt_sample_rate_rx_put(struct snd_kcontrol *kcontrol,
1230 struct snd_ctl_elem_value *ucontrol)
1231{
1232 switch (ucontrol->value.integer.value[0]) {
1233 case 1:
1234 slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_16KHZ;
1235 break;
1236 case 2:
1237 slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
1238 break;
1239 case 3:
1240 slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_48KHZ;
1241 break;
1242 case 4:
1243 slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
1244 break;
1245 case 5:
1246 slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_96KHZ;
1247 break;
1248 case 0:
1249 default:
1250 slim_rx_cfg[SLIM_RX_7].sample_rate = SAMPLING_RATE_8KHZ;
1251 break;
1252 }
1253 pr_debug("%s: sample rate: slim7_rx = %d, value = %d\n",
1254 __func__,
1255 slim_rx_cfg[SLIM_RX_7].sample_rate,
1256 ucontrol->value.enumerated.item[0]);
1257
1258 return 0;
1259}
1260
1261static int msm_bt_sample_rate_tx_get(struct snd_kcontrol *kcontrol,
1262 struct snd_ctl_elem_value *ucontrol)
1263{
1264 switch (slim_tx_cfg[SLIM_TX_7].sample_rate) {
1265 case SAMPLING_RATE_96KHZ:
1266 ucontrol->value.integer.value[0] = 5;
1267 break;
1268 case SAMPLING_RATE_88P2KHZ:
1269 ucontrol->value.integer.value[0] = 4;
1270 break;
1271 case SAMPLING_RATE_48KHZ:
1272 ucontrol->value.integer.value[0] = 3;
1273 break;
1274 case SAMPLING_RATE_44P1KHZ:
1275 ucontrol->value.integer.value[0] = 2;
1276 break;
1277 case SAMPLING_RATE_16KHZ:
1278 ucontrol->value.integer.value[0] = 1;
1279 break;
1280 case SAMPLING_RATE_8KHZ:
1281 default:
1282 ucontrol->value.integer.value[0] = 0;
1283 break;
1284 }
1285 pr_debug("%s: sample rate tx = %d", __func__,
1286 slim_tx_cfg[SLIM_TX_7].sample_rate);
1287
1288 return 0;
1289}
1290
1291static int msm_bt_sample_rate_tx_put(struct snd_kcontrol *kcontrol,
1292 struct snd_ctl_elem_value *ucontrol)
1293{
1294 switch (ucontrol->value.integer.value[0]) {
1295 case 1:
1296 slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_16KHZ;
1297 break;
1298 case 2:
1299 slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_44P1KHZ;
1300 break;
1301 case 3:
1302 slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_48KHZ;
1303 break;
1304 case 4:
1305 slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_88P2KHZ;
1306 break;
1307 case 5:
1308 slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_96KHZ;
1309 break;
1310 case 0:
1311 default:
1312 slim_tx_cfg[SLIM_TX_7].sample_rate = SAMPLING_RATE_8KHZ;
1313 break;
1314 }
1315 pr_debug("%s: sample rate: slim7_tx = %d, value = %d\n",
1316 __func__,
1317 slim_tx_cfg[SLIM_TX_7].sample_rate,
1318 ucontrol->value.enumerated.item[0]);
1319
1320 return 0;
1321}
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1322static int cdc_dma_get_port_idx(struct snd_kcontrol *kcontrol)
1323{
1324 int idx = 0;
1325
1326 if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_0",
1327 sizeof("WSA_CDC_DMA_RX_0")))
1328 idx = WSA_CDC_DMA_RX_0;
1329 else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_RX_1",
1330 sizeof("WSA_CDC_DMA_RX_0")))
1331 idx = WSA_CDC_DMA_RX_1;
1332 else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_0",
1333 sizeof("RX_CDC_DMA_RX_0")))
1334 idx = RX_CDC_DMA_RX_0;
1335 else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_1",
1336 sizeof("RX_CDC_DMA_RX_1")))
1337 idx = RX_CDC_DMA_RX_1;
1338 else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_2",
1339 sizeof("RX_CDC_DMA_RX_2")))
1340 idx = RX_CDC_DMA_RX_2;
1341 else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_3",
1342 sizeof("RX_CDC_DMA_RX_3")))
1343 idx = RX_CDC_DMA_RX_3;
1344 else if (strnstr(kcontrol->id.name, "RX_CDC_DMA_RX_5",
1345 sizeof("RX_CDC_DMA_RX_5")))
1346 idx = RX_CDC_DMA_RX_5;
1347 else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_0",
1348 sizeof("WSA_CDC_DMA_TX_0")))
1349 idx = WSA_CDC_DMA_TX_0;
1350 else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_1",
1351 sizeof("WSA_CDC_DMA_TX_1")))
1352 idx = WSA_CDC_DMA_TX_1;
1353 else if (strnstr(kcontrol->id.name, "WSA_CDC_DMA_TX_2",
1354 sizeof("WSA_CDC_DMA_TX_2")))
1355 idx = WSA_CDC_DMA_TX_2;
1356 else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_0",
1357 sizeof("TX_CDC_DMA_TX_0")))
1358 idx = TX_CDC_DMA_TX_0;
1359 else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_3",
1360 sizeof("TX_CDC_DMA_TX_3")))
1361 idx = TX_CDC_DMA_TX_3;
1362 else if (strnstr(kcontrol->id.name, "TX_CDC_DMA_TX_4",
1363 sizeof("TX_CDC_DMA_TX_4")))
1364 idx = TX_CDC_DMA_TX_4;
1365 else {
1366 pr_err("%s: unsupported channel: %s\n",
1367 __func__, kcontrol->id.name);
1368 return -EINVAL;
1369 }
1370
1371 return idx;
1372}
1373
1374static int cdc_dma_rx_ch_get(struct snd_kcontrol *kcontrol,
1375 struct snd_ctl_elem_value *ucontrol)
1376{
1377 int ch_num = cdc_dma_get_port_idx(kcontrol);
1378
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1379 if (ch_num < 0) {
1380 pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1381 return ch_num;
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1382 }
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1383
1384 pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
1385 cdc_dma_rx_cfg[ch_num].channels - 1);
1386 ucontrol->value.integer.value[0] = cdc_dma_rx_cfg[ch_num].channels - 1;
1387 return 0;
1388}
1389
1390static int cdc_dma_rx_ch_put(struct snd_kcontrol *kcontrol,
1391 struct snd_ctl_elem_value *ucontrol)
1392{
1393 int ch_num = cdc_dma_get_port_idx(kcontrol);
1394
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1395 if (ch_num < 0) {
1396 pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1397 return ch_num;
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1398 }
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1399
1400 cdc_dma_rx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
1401
1402 pr_debug("%s: cdc_dma_rx_ch = %d\n", __func__,
1403 cdc_dma_rx_cfg[ch_num].channels);
1404 return 1;
1405}
1406
1407static int cdc_dma_rx_format_get(struct snd_kcontrol *kcontrol,
1408 struct snd_ctl_elem_value *ucontrol)
1409{
1410 int ch_num = cdc_dma_get_port_idx(kcontrol);
1411
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1412 if (ch_num < 0) {
1413 pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
1414 return ch_num;
1415 }
1416
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1417 switch (cdc_dma_rx_cfg[ch_num].bit_format) {
1418 case SNDRV_PCM_FORMAT_S32_LE:
1419 ucontrol->value.integer.value[0] = 3;
1420 break;
1421 case SNDRV_PCM_FORMAT_S24_3LE:
1422 ucontrol->value.integer.value[0] = 2;
1423 break;
1424 case SNDRV_PCM_FORMAT_S24_LE:
1425 ucontrol->value.integer.value[0] = 1;
1426 break;
1427 case SNDRV_PCM_FORMAT_S16_LE:
1428 default:
1429 ucontrol->value.integer.value[0] = 0;
1430 break;
1431 }
1432
1433 pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
1434 __func__, cdc_dma_rx_cfg[ch_num].bit_format,
1435 ucontrol->value.integer.value[0]);
1436 return 0;
1437}
1438
1439static int cdc_dma_rx_format_put(struct snd_kcontrol *kcontrol,
1440 struct snd_ctl_elem_value *ucontrol)
1441{
1442 int rc = 0;
1443 int ch_num = cdc_dma_get_port_idx(kcontrol);
1444
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1445 if (ch_num < 0) {
1446 pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
1447 return ch_num;
1448 }
1449
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1450 switch (ucontrol->value.integer.value[0]) {
1451 case 3:
1452 cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
1453 break;
1454 case 2:
1455 cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
1456 break;
1457 case 1:
1458 cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
1459 break;
1460 case 0:
1461 default:
1462 cdc_dma_rx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
1463 break;
1464 }
1465 pr_debug("%s: cdc_dma_rx_format = %d, ucontrol value = %ld\n",
1466 __func__, cdc_dma_rx_cfg[ch_num].bit_format,
1467 ucontrol->value.integer.value[0]);
1468
1469 return rc;
1470}
1471
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1472
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1473static int cdc_dma_get_sample_rate_val(int sample_rate)
1474{
1475 int sample_rate_val = 0;
1476
1477 switch (sample_rate) {
1478 case SAMPLING_RATE_8KHZ:
1479 sample_rate_val = 0;
1480 break;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1481 case SAMPLING_RATE_11P025KHZ:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1482 sample_rate_val = 1;
1483 break;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1484 case SAMPLING_RATE_16KHZ:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1485 sample_rate_val = 2;
1486 break;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1487 case SAMPLING_RATE_22P05KHZ:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1488 sample_rate_val = 3;
1489 break;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1490 case SAMPLING_RATE_32KHZ:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1491 sample_rate_val = 4;
1492 break;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1493 case SAMPLING_RATE_44P1KHZ:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1494 sample_rate_val = 5;
1495 break;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1496 case SAMPLING_RATE_48KHZ:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1497 sample_rate_val = 6;
1498 break;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1499 case SAMPLING_RATE_88P2KHZ:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1500 sample_rate_val = 7;
1501 break;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1502 case SAMPLING_RATE_96KHZ:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1503 sample_rate_val = 8;
1504 break;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1505 case SAMPLING_RATE_176P4KHZ:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1506 sample_rate_val = 9;
1507 break;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1508 case SAMPLING_RATE_192KHZ:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1509 sample_rate_val = 10;
1510 break;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1511 case SAMPLING_RATE_352P8KHZ:
1512 sample_rate_val = 11;
1513 break;
1514 case SAMPLING_RATE_384KHZ:
1515 sample_rate_val = 12;
1516 break;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1517 default:
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1518 sample_rate_val = 6;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1519 break;
1520 }
1521 return sample_rate_val;
1522}
1523
1524static int cdc_dma_get_sample_rate(int value)
1525{
1526 int sample_rate = 0;
1527
1528 switch (value) {
1529 case 0:
1530 sample_rate = SAMPLING_RATE_8KHZ;
1531 break;
1532 case 1:
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1533 sample_rate = SAMPLING_RATE_11P025KHZ;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1534 break;
1535 case 2:
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1536 sample_rate = SAMPLING_RATE_16KHZ;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1537 break;
1538 case 3:
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1539 sample_rate = SAMPLING_RATE_22P05KHZ;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1540 break;
1541 case 4:
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1542 sample_rate = SAMPLING_RATE_32KHZ;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1543 break;
1544 case 5:
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1545 sample_rate = SAMPLING_RATE_44P1KHZ;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1546 break;
1547 case 6:
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1548 sample_rate = SAMPLING_RATE_48KHZ;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1549 break;
1550 case 7:
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1551 sample_rate = SAMPLING_RATE_88P2KHZ;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1552 break;
1553 case 8:
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1554 sample_rate = SAMPLING_RATE_96KHZ;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1555 break;
1556 case 9:
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1557 sample_rate = SAMPLING_RATE_176P4KHZ;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1558 break;
1559 case 10:
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]1560 sample_rate = SAMPLING_RATE_192KHZ;
1561 break;
1562 case 11:
1563 sample_rate = SAMPLING_RATE_352P8KHZ;
1564 break;
1565 case 12:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1566 sample_rate = SAMPLING_RATE_384KHZ;
1567 break;
1568 default:
1569 sample_rate = SAMPLING_RATE_48KHZ;
1570 break;
1571 }
1572 return sample_rate;
1573}
1574
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1575static int cdc_dma_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
1576 struct snd_ctl_elem_value *ucontrol)
1577{
1578 int ch_num = cdc_dma_get_port_idx(kcontrol);
1579
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1580 if (ch_num < 0) {
1581 pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1582 return ch_num;
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1583 }
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1584
1585 ucontrol->value.enumerated.item[0] =
1586 cdc_dma_get_sample_rate_val(cdc_dma_rx_cfg[ch_num].sample_rate);
1587
1588 pr_debug("%s: cdc_dma_rx_sample_rate = %d\n", __func__,
1589 cdc_dma_rx_cfg[ch_num].sample_rate);
1590 return 0;
1591}
1592
1593static int cdc_dma_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
1594 struct snd_ctl_elem_value *ucontrol)
1595{
1596 int ch_num = cdc_dma_get_port_idx(kcontrol);
1597
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1598 if (ch_num < 0) {
1599 pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1600 return ch_num;
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1601 }
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1602
1603 cdc_dma_rx_cfg[ch_num].sample_rate =
1604 cdc_dma_get_sample_rate(ucontrol->value.enumerated.item[0]);
1605
1606
1607 pr_debug("%s: control value = %d, cdc_dma_rx_sample_rate = %d\n",
1608 __func__, ucontrol->value.enumerated.item[0],
1609 cdc_dma_rx_cfg[ch_num].sample_rate);
1610 return 0;
1611}
1612
1613static int cdc_dma_tx_ch_get(struct snd_kcontrol *kcontrol,
1614 struct snd_ctl_elem_value *ucontrol)
1615{
1616 int ch_num = cdc_dma_get_port_idx(kcontrol);
1617
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1618 if (ch_num < 0) {
1619 pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
1620 return ch_num;
1621 }
1622
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1623 pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
1624 cdc_dma_tx_cfg[ch_num].channels);
1625 ucontrol->value.integer.value[0] = cdc_dma_tx_cfg[ch_num].channels - 1;
1626 return 0;
1627}
1628
1629static int cdc_dma_tx_ch_put(struct snd_kcontrol *kcontrol,
1630 struct snd_ctl_elem_value *ucontrol)
1631{
1632 int ch_num = cdc_dma_get_port_idx(kcontrol);
1633
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1634 if (ch_num < 0) {
1635 pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
1636 return ch_num;
1637 }
1638
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1639 cdc_dma_tx_cfg[ch_num].channels = ucontrol->value.integer.value[0] + 1;
1640
1641 pr_debug("%s: cdc_dma_tx_ch = %d\n", __func__,
1642 cdc_dma_tx_cfg[ch_num].channels);
1643 return 1;
1644}
1645
1646static int cdc_dma_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
1647 struct snd_ctl_elem_value *ucontrol)
1648{
1649 int sample_rate_val;
1650 int ch_num = cdc_dma_get_port_idx(kcontrol);
1651
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1652 if (ch_num < 0) {
1653 pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
1654 return ch_num;
1655 }
1656
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1657 switch (cdc_dma_tx_cfg[ch_num].sample_rate) {
1658 case SAMPLING_RATE_384KHZ:
1659 sample_rate_val = 12;
1660 break;
1661 case SAMPLING_RATE_352P8KHZ:
1662 sample_rate_val = 11;
1663 break;
1664 case SAMPLING_RATE_192KHZ:
1665 sample_rate_val = 10;
1666 break;
1667 case SAMPLING_RATE_176P4KHZ:
1668 sample_rate_val = 9;
1669 break;
1670 case SAMPLING_RATE_96KHZ:
1671 sample_rate_val = 8;
1672 break;
1673 case SAMPLING_RATE_88P2KHZ:
1674 sample_rate_val = 7;
1675 break;
1676 case SAMPLING_RATE_48KHZ:
1677 sample_rate_val = 6;
1678 break;
1679 case SAMPLING_RATE_44P1KHZ:
1680 sample_rate_val = 5;
1681 break;
1682 case SAMPLING_RATE_32KHZ:
1683 sample_rate_val = 4;
1684 break;
1685 case SAMPLING_RATE_22P05KHZ:
1686 sample_rate_val = 3;
1687 break;
1688 case SAMPLING_RATE_16KHZ:
1689 sample_rate_val = 2;
1690 break;
1691 case SAMPLING_RATE_11P025KHZ:
1692 sample_rate_val = 1;
1693 break;
1694 case SAMPLING_RATE_8KHZ:
1695 sample_rate_val = 0;
1696 break;
1697 default:
1698 sample_rate_val = 6;
1699 break;
1700 }
1701
1702 ucontrol->value.integer.value[0] = sample_rate_val;
1703 pr_debug("%s: cdc_dma_tx_sample_rate = %d\n", __func__,
1704 cdc_dma_tx_cfg[ch_num].sample_rate);
1705 return 0;
1706}
1707
1708static int cdc_dma_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
1709 struct snd_ctl_elem_value *ucontrol)
1710{
1711 int ch_num = cdc_dma_get_port_idx(kcontrol);
1712
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1713 if (ch_num < 0) {
1714 pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
1715 return ch_num;
1716 }
1717
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1718 switch (ucontrol->value.integer.value[0]) {
1719 case 12:
1720 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_384KHZ;
1721 break;
1722 case 11:
1723 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_352P8KHZ;
1724 break;
1725 case 10:
1726 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_192KHZ;
1727 break;
1728 case 9:
1729 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_176P4KHZ;
1730 break;
1731 case 8:
1732 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_96KHZ;
1733 break;
1734 case 7:
1735 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_88P2KHZ;
1736 break;
1737 case 6:
1738 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
1739 break;
1740 case 5:
1741 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_44P1KHZ;
1742 break;
1743 case 4:
1744 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_32KHZ;
1745 break;
1746 case 3:
1747 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_22P05KHZ;
1748 break;
1749 case 2:
1750 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_16KHZ;
1751 break;
1752 case 1:
1753 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_11P025KHZ;
1754 break;
1755 case 0:
1756 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_8KHZ;
1757 break;
1758 default:
1759 cdc_dma_tx_cfg[ch_num].sample_rate = SAMPLING_RATE_48KHZ;
1760 break;
1761 }
1762
1763 pr_debug("%s: control value = %ld, cdc_dma_tx_sample_rate = %d\n",
1764 __func__, ucontrol->value.integer.value[0],
1765 cdc_dma_tx_cfg[ch_num].sample_rate);
1766 return 0;
1767}
1768
1769static int cdc_dma_tx_format_get(struct snd_kcontrol *kcontrol,
1770 struct snd_ctl_elem_value *ucontrol)
1771{
1772 int ch_num = cdc_dma_get_port_idx(kcontrol);
1773
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1774 if (ch_num < 0) {
1775 pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
1776 return ch_num;
1777 }
1778
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1779 switch (cdc_dma_tx_cfg[ch_num].bit_format) {
1780 case SNDRV_PCM_FORMAT_S32_LE:
1781 ucontrol->value.integer.value[0] = 3;
1782 break;
1783 case SNDRV_PCM_FORMAT_S24_3LE:
1784 ucontrol->value.integer.value[0] = 2;
1785 break;
1786 case SNDRV_PCM_FORMAT_S24_LE:
1787 ucontrol->value.integer.value[0] = 1;
1788 break;
1789 case SNDRV_PCM_FORMAT_S16_LE:
1790 default:
1791 ucontrol->value.integer.value[0] = 0;
1792 break;
1793 }
1794
1795 pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
1796 __func__, cdc_dma_tx_cfg[ch_num].bit_format,
1797 ucontrol->value.integer.value[0]);
1798 return 0;
1799}
1800
1801static int cdc_dma_tx_format_put(struct snd_kcontrol *kcontrol,
1802 struct snd_ctl_elem_value *ucontrol)
1803{
1804 int rc = 0;
1805 int ch_num = cdc_dma_get_port_idx(kcontrol);
1806
Tanya Dixitd85e6f32018-09-14 16:06:20 +0530[diff] [blame]1807 if (ch_num < 0) {
1808 pr_err("%s: ch_num: %d is invalid\n", __func__, ch_num);
1809 return ch_num;
1810 }
1811
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1812 switch (ucontrol->value.integer.value[0]) {
1813 case 3:
1814 cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S32_LE;
1815 break;
1816 case 2:
1817 cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
1818 break;
1819 case 1:
1820 cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S24_LE;
1821 break;
1822 case 0:
1823 default:
1824 cdc_dma_tx_cfg[ch_num].bit_format = SNDRV_PCM_FORMAT_S16_LE;
1825 break;
1826 }
1827 pr_debug("%s: cdc_dma_tx_format = %d, ucontrol value = %ld\n",
1828 __func__, cdc_dma_tx_cfg[ch_num].bit_format,
1829 ucontrol->value.integer.value[0]);
1830
1831 return rc;
1832}
1833
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]1834static int usb_audio_rx_ch_get(struct snd_kcontrol *kcontrol,
1835 struct snd_ctl_elem_value *ucontrol)
1836{
1837 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__,
1838 usb_rx_cfg.channels);
1839 ucontrol->value.integer.value[0] = usb_rx_cfg.channels - 1;
1840 return 0;
1841}
1842
1843static int usb_audio_rx_ch_put(struct snd_kcontrol *kcontrol,
1844 struct snd_ctl_elem_value *ucontrol)
1845{
1846 usb_rx_cfg.channels = ucontrol->value.integer.value[0] + 1;
1847
1848 pr_debug("%s: usb_audio_rx_ch = %d\n", __func__, usb_rx_cfg.channels);
1849 return 1;
1850}
1851
1852static int usb_audio_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
1853 struct snd_ctl_elem_value *ucontrol)
1854{
1855 int sample_rate_val;
1856
1857 switch (usb_rx_cfg.sample_rate) {
1858 case SAMPLING_RATE_384KHZ:
1859 sample_rate_val = 12;
1860 break;
1861 case SAMPLING_RATE_352P8KHZ:
1862 sample_rate_val = 11;
1863 break;
1864 case SAMPLING_RATE_192KHZ:
1865 sample_rate_val = 10;
1866 break;
1867 case SAMPLING_RATE_176P4KHZ:
1868 sample_rate_val = 9;
1869 break;
1870 case SAMPLING_RATE_96KHZ:
1871 sample_rate_val = 8;
1872 break;
1873 case SAMPLING_RATE_88P2KHZ:
1874 sample_rate_val = 7;
1875 break;
1876 case SAMPLING_RATE_48KHZ:
1877 sample_rate_val = 6;
1878 break;
1879 case SAMPLING_RATE_44P1KHZ:
1880 sample_rate_val = 5;
1881 break;
1882 case SAMPLING_RATE_32KHZ:
1883 sample_rate_val = 4;
1884 break;
1885 case SAMPLING_RATE_22P05KHZ:
1886 sample_rate_val = 3;
1887 break;
1888 case SAMPLING_RATE_16KHZ:
1889 sample_rate_val = 2;
1890 break;
1891 case SAMPLING_RATE_11P025KHZ:
1892 sample_rate_val = 1;
1893 break;
1894 case SAMPLING_RATE_8KHZ:
1895 default:
1896 sample_rate_val = 0;
1897 break;
1898 }
1899
1900 ucontrol->value.integer.value[0] = sample_rate_val;
1901 pr_debug("%s: usb_audio_rx_sample_rate = %d\n", __func__,
1902 usb_rx_cfg.sample_rate);
1903 return 0;
1904}
1905
1906static int usb_audio_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
1907 struct snd_ctl_elem_value *ucontrol)
1908{
1909 switch (ucontrol->value.integer.value[0]) {
1910 case 12:
1911 usb_rx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
1912 break;
1913 case 11:
1914 usb_rx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
1915 break;
1916 case 10:
1917 usb_rx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
1918 break;
1919 case 9:
1920 usb_rx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
1921 break;
1922 case 8:
1923 usb_rx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
1924 break;
1925 case 7:
1926 usb_rx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
1927 break;
1928 case 6:
1929 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
1930 break;
1931 case 5:
1932 usb_rx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
1933 break;
1934 case 4:
1935 usb_rx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
1936 break;
1937 case 3:
1938 usb_rx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
1939 break;
1940 case 2:
1941 usb_rx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
1942 break;
1943 case 1:
1944 usb_rx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
1945 break;
1946 case 0:
1947 usb_rx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
1948 break;
1949 default:
1950 usb_rx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
1951 break;
1952 }
1953
1954 pr_debug("%s: control value = %ld, usb_audio_rx_sample_rate = %d\n",
1955 __func__, ucontrol->value.integer.value[0],
1956 usb_rx_cfg.sample_rate);
1957 return 0;
1958}
1959
1960static int usb_audio_rx_format_get(struct snd_kcontrol *kcontrol,
1961 struct snd_ctl_elem_value *ucontrol)
1962{
1963 switch (usb_rx_cfg.bit_format) {
1964 case SNDRV_PCM_FORMAT_S32_LE:
1965 ucontrol->value.integer.value[0] = 3;
1966 break;
1967 case SNDRV_PCM_FORMAT_S24_3LE:
1968 ucontrol->value.integer.value[0] = 2;
1969 break;
1970 case SNDRV_PCM_FORMAT_S24_LE:
1971 ucontrol->value.integer.value[0] = 1;
1972 break;
1973 case SNDRV_PCM_FORMAT_S16_LE:
1974 default:
1975 ucontrol->value.integer.value[0] = 0;
1976 break;
1977 }
1978
1979 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
1980 __func__, usb_rx_cfg.bit_format,
1981 ucontrol->value.integer.value[0]);
1982 return 0;
1983}
1984
1985static int usb_audio_rx_format_put(struct snd_kcontrol *kcontrol,
1986 struct snd_ctl_elem_value *ucontrol)
1987{
1988 int rc = 0;
1989
1990 switch (ucontrol->value.integer.value[0]) {
1991 case 3:
1992 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
1993 break;
1994 case 2:
1995 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
1996 break;
1997 case 1:
1998 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
1999 break;
2000 case 0:
2001 default:
2002 usb_rx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
2003 break;
2004 }
2005 pr_debug("%s: usb_audio_rx_format = %d, ucontrol value = %ld\n",
2006 __func__, usb_rx_cfg.bit_format,
2007 ucontrol->value.integer.value[0]);
2008
2009 return rc;
2010}
2011
2012static int usb_audio_tx_ch_get(struct snd_kcontrol *kcontrol,
2013 struct snd_ctl_elem_value *ucontrol)
2014{
2015 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__,
2016 usb_tx_cfg.channels);
2017 ucontrol->value.integer.value[0] = usb_tx_cfg.channels - 1;
2018 return 0;
2019}
2020
2021static int usb_audio_tx_ch_put(struct snd_kcontrol *kcontrol,
2022 struct snd_ctl_elem_value *ucontrol)
2023{
2024 usb_tx_cfg.channels = ucontrol->value.integer.value[0] + 1;
2025
2026 pr_debug("%s: usb_audio_tx_ch = %d\n", __func__, usb_tx_cfg.channels);
2027 return 1;
2028}
2029
2030static int usb_audio_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2031 struct snd_ctl_elem_value *ucontrol)
2032{
2033 int sample_rate_val;
2034
2035 switch (usb_tx_cfg.sample_rate) {
2036 case SAMPLING_RATE_384KHZ:
2037 sample_rate_val = 12;
2038 break;
2039 case SAMPLING_RATE_352P8KHZ:
2040 sample_rate_val = 11;
2041 break;
2042 case SAMPLING_RATE_192KHZ:
2043 sample_rate_val = 10;
2044 break;
2045 case SAMPLING_RATE_176P4KHZ:
2046 sample_rate_val = 9;
2047 break;
2048 case SAMPLING_RATE_96KHZ:
2049 sample_rate_val = 8;
2050 break;
2051 case SAMPLING_RATE_88P2KHZ:
2052 sample_rate_val = 7;
2053 break;
2054 case SAMPLING_RATE_48KHZ:
2055 sample_rate_val = 6;
2056 break;
2057 case SAMPLING_RATE_44P1KHZ:
2058 sample_rate_val = 5;
2059 break;
2060 case SAMPLING_RATE_32KHZ:
2061 sample_rate_val = 4;
2062 break;
2063 case SAMPLING_RATE_22P05KHZ:
2064 sample_rate_val = 3;
2065 break;
2066 case SAMPLING_RATE_16KHZ:
2067 sample_rate_val = 2;
2068 break;
2069 case SAMPLING_RATE_11P025KHZ:
2070 sample_rate_val = 1;
2071 break;
2072 case SAMPLING_RATE_8KHZ:
2073 sample_rate_val = 0;
2074 break;
2075 default:
2076 sample_rate_val = 6;
2077 break;
2078 }
2079
2080 ucontrol->value.integer.value[0] = sample_rate_val;
2081 pr_debug("%s: usb_audio_tx_sample_rate = %d\n", __func__,
2082 usb_tx_cfg.sample_rate);
2083 return 0;
2084}
2085
2086static int usb_audio_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2087 struct snd_ctl_elem_value *ucontrol)
2088{
2089 switch (ucontrol->value.integer.value[0]) {
2090 case 12:
2091 usb_tx_cfg.sample_rate = SAMPLING_RATE_384KHZ;
2092 break;
2093 case 11:
2094 usb_tx_cfg.sample_rate = SAMPLING_RATE_352P8KHZ;
2095 break;
2096 case 10:
2097 usb_tx_cfg.sample_rate = SAMPLING_RATE_192KHZ;
2098 break;
2099 case 9:
2100 usb_tx_cfg.sample_rate = SAMPLING_RATE_176P4KHZ;
2101 break;
2102 case 8:
2103 usb_tx_cfg.sample_rate = SAMPLING_RATE_96KHZ;
2104 break;
2105 case 7:
2106 usb_tx_cfg.sample_rate = SAMPLING_RATE_88P2KHZ;
2107 break;
2108 case 6:
2109 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
2110 break;
2111 case 5:
2112 usb_tx_cfg.sample_rate = SAMPLING_RATE_44P1KHZ;
2113 break;
2114 case 4:
2115 usb_tx_cfg.sample_rate = SAMPLING_RATE_32KHZ;
2116 break;
2117 case 3:
2118 usb_tx_cfg.sample_rate = SAMPLING_RATE_22P05KHZ;
2119 break;
2120 case 2:
2121 usb_tx_cfg.sample_rate = SAMPLING_RATE_16KHZ;
2122 break;
2123 case 1:
2124 usb_tx_cfg.sample_rate = SAMPLING_RATE_11P025KHZ;
2125 break;
2126 case 0:
2127 usb_tx_cfg.sample_rate = SAMPLING_RATE_8KHZ;
2128 break;
2129 default:
2130 usb_tx_cfg.sample_rate = SAMPLING_RATE_48KHZ;
2131 break;
2132 }
2133
2134 pr_debug("%s: control value = %ld, usb_audio_tx_sample_rate = %d\n",
2135 __func__, ucontrol->value.integer.value[0],
2136 usb_tx_cfg.sample_rate);
2137 return 0;
2138}
2139
2140static int usb_audio_tx_format_get(struct snd_kcontrol *kcontrol,
2141 struct snd_ctl_elem_value *ucontrol)
2142{
2143 switch (usb_tx_cfg.bit_format) {
2144 case SNDRV_PCM_FORMAT_S32_LE:
2145 ucontrol->value.integer.value[0] = 3;
2146 break;
2147 case SNDRV_PCM_FORMAT_S24_3LE:
2148 ucontrol->value.integer.value[0] = 2;
2149 break;
2150 case SNDRV_PCM_FORMAT_S24_LE:
2151 ucontrol->value.integer.value[0] = 1;
2152 break;
2153 case SNDRV_PCM_FORMAT_S16_LE:
2154 default:
2155 ucontrol->value.integer.value[0] = 0;
2156 break;
2157 }
2158
2159 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
2160 __func__, usb_tx_cfg.bit_format,
2161 ucontrol->value.integer.value[0]);
2162 return 0;
2163}
2164
2165static int usb_audio_tx_format_put(struct snd_kcontrol *kcontrol,
2166 struct snd_ctl_elem_value *ucontrol)
2167{
2168 int rc = 0;
2169
2170 switch (ucontrol->value.integer.value[0]) {
2171 case 3:
2172 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S32_LE;
2173 break;
2174 case 2:
2175 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_3LE;
2176 break;
2177 case 1:
2178 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S24_LE;
2179 break;
2180 case 0:
2181 default:
2182 usb_tx_cfg.bit_format = SNDRV_PCM_FORMAT_S16_LE;
2183 break;
2184 }
2185 pr_debug("%s: usb_audio_tx_format = %d, ucontrol value = %ld\n",
2186 __func__, usb_tx_cfg.bit_format,
2187 ucontrol->value.integer.value[0]);
2188
2189 return rc;
2190}
2191
2192static int ext_disp_get_port_idx(struct snd_kcontrol *kcontrol)
2193{
2194 int idx;
2195
2196 if (strnstr(kcontrol->id.name, "Display Port RX",
2197 sizeof("Display Port RX"))) {
2198 idx = DP_RX_IDX;
2199 } else {
2200 pr_err("%s: unsupported BE: %s\n",
2201 __func__, kcontrol->id.name);
2202 idx = -EINVAL;
2203 }
2204
2205 return idx;
2206}
2207
2208static int ext_disp_rx_format_get(struct snd_kcontrol *kcontrol,
2209 struct snd_ctl_elem_value *ucontrol)
2210{
2211 int idx = ext_disp_get_port_idx(kcontrol);
2212
2213 if (idx < 0)
2214 return idx;
2215
2216 switch (ext_disp_rx_cfg[idx].bit_format) {
2217 case SNDRV_PCM_FORMAT_S24_3LE:
2218 ucontrol->value.integer.value[0] = 2;
2219 break;
2220 case SNDRV_PCM_FORMAT_S24_LE:
2221 ucontrol->value.integer.value[0] = 1;
2222 break;
2223 case SNDRV_PCM_FORMAT_S16_LE:
2224 default:
2225 ucontrol->value.integer.value[0] = 0;
2226 break;
2227 }
2228
2229 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
2230 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
2231 ucontrol->value.integer.value[0]);
2232 return 0;
2233}
2234
2235static int ext_disp_rx_format_put(struct snd_kcontrol *kcontrol,
2236 struct snd_ctl_elem_value *ucontrol)
2237{
2238 int idx = ext_disp_get_port_idx(kcontrol);
2239
2240 if (idx < 0)
2241 return idx;
2242
2243 switch (ucontrol->value.integer.value[0]) {
2244 case 2:
2245 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_3LE;
2246 break;
2247 case 1:
2248 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S24_LE;
2249 break;
2250 case 0:
2251 default:
2252 ext_disp_rx_cfg[idx].bit_format = SNDRV_PCM_FORMAT_S16_LE;
2253 break;
2254 }
2255 pr_debug("%s: ext_disp_rx[%d].format = %d, ucontrol value = %ld\n",
2256 __func__, idx, ext_disp_rx_cfg[idx].bit_format,
2257 ucontrol->value.integer.value[0]);
2258
2259 return 0;
2260}
2261
2262static int ext_disp_rx_ch_get(struct snd_kcontrol *kcontrol,
2263 struct snd_ctl_elem_value *ucontrol)
2264{
2265 int idx = ext_disp_get_port_idx(kcontrol);
2266
2267 if (idx < 0)
2268 return idx;
2269
2270 ucontrol->value.integer.value[0] =
2271 ext_disp_rx_cfg[idx].channels - 2;
2272
2273 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
2274 idx, ext_disp_rx_cfg[idx].channels);
2275
2276 return 0;
2277}
2278
2279static int ext_disp_rx_ch_put(struct snd_kcontrol *kcontrol,
2280 struct snd_ctl_elem_value *ucontrol)
2281{
2282 int idx = ext_disp_get_port_idx(kcontrol);
2283
2284 if (idx < 0)
2285 return idx;
2286
2287 ext_disp_rx_cfg[idx].channels =
2288 ucontrol->value.integer.value[0] + 2;
2289
2290 pr_debug("%s: ext_disp_rx[%d].ch = %d\n", __func__,
2291 idx, ext_disp_rx_cfg[idx].channels);
2292 return 1;
2293}
2294
2295static int ext_disp_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2296 struct snd_ctl_elem_value *ucontrol)
2297{
2298 int sample_rate_val;
2299 int idx = ext_disp_get_port_idx(kcontrol);
2300
2301 if (idx < 0)
2302 return idx;
2303
2304 switch (ext_disp_rx_cfg[idx].sample_rate) {
2305 case SAMPLING_RATE_176P4KHZ:
2306 sample_rate_val = 6;
2307 break;
2308
2309 case SAMPLING_RATE_88P2KHZ:
2310 sample_rate_val = 5;
2311 break;
2312
2313 case SAMPLING_RATE_44P1KHZ:
2314 sample_rate_val = 4;
2315 break;
2316
2317 case SAMPLING_RATE_32KHZ:
2318 sample_rate_val = 3;
2319 break;
2320
2321 case SAMPLING_RATE_192KHZ:
2322 sample_rate_val = 2;
2323 break;
2324
2325 case SAMPLING_RATE_96KHZ:
2326 sample_rate_val = 1;
2327 break;
2328
2329 case SAMPLING_RATE_48KHZ:
2330 default:
2331 sample_rate_val = 0;
2332 break;
2333 }
2334
2335 ucontrol->value.integer.value[0] = sample_rate_val;
2336 pr_debug("%s: ext_disp_rx[%d].sample_rate = %d\n", __func__,
2337 idx, ext_disp_rx_cfg[idx].sample_rate);
2338
2339 return 0;
2340}
2341
2342static int ext_disp_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2343 struct snd_ctl_elem_value *ucontrol)
2344{
2345 int idx = ext_disp_get_port_idx(kcontrol);
2346
2347 if (idx < 0)
2348 return idx;
2349
2350 switch (ucontrol->value.integer.value[0]) {
2351 case 6:
2352 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_176P4KHZ;
2353 break;
2354 case 5:
2355 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_88P2KHZ;
2356 break;
2357 case 4:
2358 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_44P1KHZ;
2359 break;
2360 case 3:
2361 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_32KHZ;
2362 break;
2363 case 2:
2364 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_192KHZ;
2365 break;
2366 case 1:
2367 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_96KHZ;
2368 break;
2369 case 0:
2370 default:
2371 ext_disp_rx_cfg[idx].sample_rate = SAMPLING_RATE_48KHZ;
2372 break;
2373 }
2374
2375 pr_debug("%s: control value = %ld, ext_disp_rx[%d].sample_rate = %d\n",
2376 __func__, ucontrol->value.integer.value[0], idx,
2377 ext_disp_rx_cfg[idx].sample_rate);
2378 return 0;
2379}
2380
2381static int proxy_rx_ch_get(struct snd_kcontrol *kcontrol,
2382 struct snd_ctl_elem_value *ucontrol)
2383{
2384 pr_debug("%s: proxy_rx channels = %d\n",
2385 __func__, proxy_rx_cfg.channels);
2386 ucontrol->value.integer.value[0] = proxy_rx_cfg.channels - 2;
2387
2388 return 0;
2389}
2390
2391static int proxy_rx_ch_put(struct snd_kcontrol *kcontrol,
2392 struct snd_ctl_elem_value *ucontrol)
2393{
2394 proxy_rx_cfg.channels = ucontrol->value.integer.value[0] + 2;
2395 pr_debug("%s: proxy_rx channels = %d\n",
2396 __func__, proxy_rx_cfg.channels);
2397
2398 return 1;
2399}
2400
2401static int tdm_get_sample_rate(int value)
2402{
2403 int sample_rate = 0;
2404
2405 switch (value) {
2406 case 0:
2407 sample_rate = SAMPLING_RATE_8KHZ;
2408 break;
2409 case 1:
2410 sample_rate = SAMPLING_RATE_16KHZ;
2411 break;
2412 case 2:
2413 sample_rate = SAMPLING_RATE_32KHZ;
2414 break;
2415 case 3:
2416 sample_rate = SAMPLING_RATE_48KHZ;
2417 break;
2418 case 4:
2419 sample_rate = SAMPLING_RATE_176P4KHZ;
2420 break;
2421 case 5:
2422 sample_rate = SAMPLING_RATE_352P8KHZ;
2423 break;
2424 default:
2425 sample_rate = SAMPLING_RATE_48KHZ;
2426 break;
2427 }
2428 return sample_rate;
2429}
2430
2431static int aux_pcm_get_sample_rate(int value)
2432{
2433 int sample_rate;
2434
2435 switch (value) {
2436 case 1:
2437 sample_rate = SAMPLING_RATE_16KHZ;
2438 break;
2439 case 0:
2440 default:
2441 sample_rate = SAMPLING_RATE_8KHZ;
2442 break;
2443 }
2444 return sample_rate;
2445}
2446
2447static int tdm_get_sample_rate_val(int sample_rate)
2448{
2449 int sample_rate_val = 0;
2450
2451 switch (sample_rate) {
2452 case SAMPLING_RATE_8KHZ:
2453 sample_rate_val = 0;
2454 break;
2455 case SAMPLING_RATE_16KHZ:
2456 sample_rate_val = 1;
2457 break;
2458 case SAMPLING_RATE_32KHZ:
2459 sample_rate_val = 2;
2460 break;
2461 case SAMPLING_RATE_48KHZ:
2462 sample_rate_val = 3;
2463 break;
2464 case SAMPLING_RATE_176P4KHZ:
2465 sample_rate_val = 4;
2466 break;
2467 case SAMPLING_RATE_352P8KHZ:
2468 sample_rate_val = 5;
2469 break;
2470 default:
2471 sample_rate_val = 3;
2472 break;
2473 }
2474 return sample_rate_val;
2475}
2476
2477static int aux_pcm_get_sample_rate_val(int sample_rate)
2478{
2479 int sample_rate_val;
2480
2481 switch (sample_rate) {
2482 case SAMPLING_RATE_16KHZ:
2483 sample_rate_val = 1;
2484 break;
2485 case SAMPLING_RATE_8KHZ:
2486 default:
2487 sample_rate_val = 0;
2488 break;
2489 }
2490 return sample_rate_val;
2491}
2492
2493static int tdm_get_port_idx(struct snd_kcontrol *kcontrol,
2494 struct tdm_port *port)
2495{
2496 if (port) {
2497 if (strnstr(kcontrol->id.name, "PRI",
2498 sizeof(kcontrol->id.name))) {
2499 port->mode = TDM_PRI;
2500 } else if (strnstr(kcontrol->id.name, "SEC",
2501 sizeof(kcontrol->id.name))) {
2502 port->mode = TDM_SEC;
2503 } else if (strnstr(kcontrol->id.name, "TERT",
2504 sizeof(kcontrol->id.name))) {
2505 port->mode = TDM_TERT;
2506 } else if (strnstr(kcontrol->id.name, "QUAT",
2507 sizeof(kcontrol->id.name))) {
2508 port->mode = TDM_QUAT;
2509 } else if (strnstr(kcontrol->id.name, "QUIN",
2510 sizeof(kcontrol->id.name))) {
2511 port->mode = TDM_QUIN;
2512 } else {
2513 pr_err("%s: unsupported mode in: %s\n",
2514 __func__, kcontrol->id.name);
2515 return -EINVAL;
2516 }
2517
2518 if (strnstr(kcontrol->id.name, "RX_0",
2519 sizeof(kcontrol->id.name)) ||
2520 strnstr(kcontrol->id.name, "TX_0",
2521 sizeof(kcontrol->id.name))) {
2522 port->channel = TDM_0;
2523 } else if (strnstr(kcontrol->id.name, "RX_1",
2524 sizeof(kcontrol->id.name)) ||
2525 strnstr(kcontrol->id.name, "TX_1",
2526 sizeof(kcontrol->id.name))) {
2527 port->channel = TDM_1;
2528 } else if (strnstr(kcontrol->id.name, "RX_2",
2529 sizeof(kcontrol->id.name)) ||
2530 strnstr(kcontrol->id.name, "TX_2",
2531 sizeof(kcontrol->id.name))) {
2532 port->channel = TDM_2;
2533 } else if (strnstr(kcontrol->id.name, "RX_3",
2534 sizeof(kcontrol->id.name)) ||
2535 strnstr(kcontrol->id.name, "TX_3",
2536 sizeof(kcontrol->id.name))) {
2537 port->channel = TDM_3;
2538 } else if (strnstr(kcontrol->id.name, "RX_4",
2539 sizeof(kcontrol->id.name)) ||
2540 strnstr(kcontrol->id.name, "TX_4",
2541 sizeof(kcontrol->id.name))) {
2542 port->channel = TDM_4;
2543 } else if (strnstr(kcontrol->id.name, "RX_5",
2544 sizeof(kcontrol->id.name)) ||
2545 strnstr(kcontrol->id.name, "TX_5",
2546 sizeof(kcontrol->id.name))) {
2547 port->channel = TDM_5;
2548 } else if (strnstr(kcontrol->id.name, "RX_6",
2549 sizeof(kcontrol->id.name)) ||
2550 strnstr(kcontrol->id.name, "TX_6",
2551 sizeof(kcontrol->id.name))) {
2552 port->channel = TDM_6;
2553 } else if (strnstr(kcontrol->id.name, "RX_7",
2554 sizeof(kcontrol->id.name)) ||
2555 strnstr(kcontrol->id.name, "TX_7",
2556 sizeof(kcontrol->id.name))) {
2557 port->channel = TDM_7;
2558 } else {
2559 pr_err("%s: unsupported channel in: %s\n",
2560 __func__, kcontrol->id.name);
2561 return -EINVAL;
2562 }
2563 } else {
2564 return -EINVAL;
2565 }
2566 return 0;
2567}
2568
2569static int tdm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2570 struct snd_ctl_elem_value *ucontrol)
2571{
2572 struct tdm_port port;
2573 int ret = tdm_get_port_idx(kcontrol, &port);
2574
2575 if (ret) {
2576 pr_err("%s: unsupported control: %s\n",
2577 __func__, kcontrol->id.name);
2578 } else {
2579 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
2580 tdm_rx_cfg[port.mode][port.channel].sample_rate);
2581
2582 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
2583 tdm_rx_cfg[port.mode][port.channel].sample_rate,
2584 ucontrol->value.enumerated.item[0]);
2585 }
2586 return ret;
2587}
2588
2589static int tdm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2590 struct snd_ctl_elem_value *ucontrol)
2591{
2592 struct tdm_port port;
2593 int ret = tdm_get_port_idx(kcontrol, &port);
2594
2595 if (ret) {
2596 pr_err("%s: unsupported control: %s\n",
2597 __func__, kcontrol->id.name);
2598 } else {
2599 tdm_rx_cfg[port.mode][port.channel].sample_rate =
2600 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2601
2602 pr_debug("%s: tdm_rx_sample_rate = %d, item = %d\n", __func__,
2603 tdm_rx_cfg[port.mode][port.channel].sample_rate,
2604 ucontrol->value.enumerated.item[0]);
2605 }
2606 return ret;
2607}
2608
2609static int tdm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2610 struct snd_ctl_elem_value *ucontrol)
2611{
2612 struct tdm_port port;
2613 int ret = tdm_get_port_idx(kcontrol, &port);
2614
2615 if (ret) {
2616 pr_err("%s: unsupported control: %s\n",
2617 __func__, kcontrol->id.name);
2618 } else {
2619 ucontrol->value.enumerated.item[0] = tdm_get_sample_rate_val(
2620 tdm_tx_cfg[port.mode][port.channel].sample_rate);
2621
2622 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
2623 tdm_tx_cfg[port.mode][port.channel].sample_rate,
2624 ucontrol->value.enumerated.item[0]);
2625 }
2626 return ret;
2627}
2628
2629static int tdm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2630 struct snd_ctl_elem_value *ucontrol)
2631{
2632 struct tdm_port port;
2633 int ret = tdm_get_port_idx(kcontrol, &port);
2634
2635 if (ret) {
2636 pr_err("%s: unsupported control: %s\n",
2637 __func__, kcontrol->id.name);
2638 } else {
2639 tdm_tx_cfg[port.mode][port.channel].sample_rate =
2640 tdm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2641
2642 pr_debug("%s: tdm_tx_sample_rate = %d, item = %d\n", __func__,
2643 tdm_tx_cfg[port.mode][port.channel].sample_rate,
2644 ucontrol->value.enumerated.item[0]);
2645 }
2646 return ret;
2647}
2648
2649static int tdm_get_format(int value)
2650{
2651 int format = 0;
2652
2653 switch (value) {
2654 case 0:
2655 format = SNDRV_PCM_FORMAT_S16_LE;
2656 break;
2657 case 1:
2658 format = SNDRV_PCM_FORMAT_S24_LE;
2659 break;
2660 case 2:
2661 format = SNDRV_PCM_FORMAT_S32_LE;
2662 break;
2663 default:
2664 format = SNDRV_PCM_FORMAT_S16_LE;
2665 break;
2666 }
2667 return format;
2668}
2669
2670static int tdm_get_format_val(int format)
2671{
2672 int value = 0;
2673
2674 switch (format) {
2675 case SNDRV_PCM_FORMAT_S16_LE:
2676 value = 0;
2677 break;
2678 case SNDRV_PCM_FORMAT_S24_LE:
2679 value = 1;
2680 break;
2681 case SNDRV_PCM_FORMAT_S32_LE:
2682 value = 2;
2683 break;
2684 default:
2685 value = 0;
2686 break;
2687 }
2688 return value;
2689}
2690
2691static int tdm_rx_format_get(struct snd_kcontrol *kcontrol,
2692 struct snd_ctl_elem_value *ucontrol)
2693{
2694 struct tdm_port port;
2695 int ret = tdm_get_port_idx(kcontrol, &port);
2696
2697 if (ret) {
2698 pr_err("%s: unsupported control: %s\n",
2699 __func__, kcontrol->id.name);
2700 } else {
2701 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
2702 tdm_rx_cfg[port.mode][port.channel].bit_format);
2703
2704 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
2705 tdm_rx_cfg[port.mode][port.channel].bit_format,
2706 ucontrol->value.enumerated.item[0]);
2707 }
2708 return ret;
2709}
2710
2711static int tdm_rx_format_put(struct snd_kcontrol *kcontrol,
2712 struct snd_ctl_elem_value *ucontrol)
2713{
2714 struct tdm_port port;
2715 int ret = tdm_get_port_idx(kcontrol, &port);
2716
2717 if (ret) {
2718 pr_err("%s: unsupported control: %s\n",
2719 __func__, kcontrol->id.name);
2720 } else {
2721 tdm_rx_cfg[port.mode][port.channel].bit_format =
2722 tdm_get_format(ucontrol->value.enumerated.item[0]);
2723
2724 pr_debug("%s: tdm_rx_bit_format = %d, item = %d\n", __func__,
2725 tdm_rx_cfg[port.mode][port.channel].bit_format,
2726 ucontrol->value.enumerated.item[0]);
2727 }
2728 return ret;
2729}
2730
2731static int tdm_tx_format_get(struct snd_kcontrol *kcontrol,
2732 struct snd_ctl_elem_value *ucontrol)
2733{
2734 struct tdm_port port;
2735 int ret = tdm_get_port_idx(kcontrol, &port);
2736
2737 if (ret) {
2738 pr_err("%s: unsupported control: %s\n",
2739 __func__, kcontrol->id.name);
2740 } else {
2741 ucontrol->value.enumerated.item[0] = tdm_get_format_val(
2742 tdm_tx_cfg[port.mode][port.channel].bit_format);
2743
2744 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
2745 tdm_tx_cfg[port.mode][port.channel].bit_format,
2746 ucontrol->value.enumerated.item[0]);
2747 }
2748 return ret;
2749}
2750
2751static int tdm_tx_format_put(struct snd_kcontrol *kcontrol,
2752 struct snd_ctl_elem_value *ucontrol)
2753{
2754 struct tdm_port port;
2755 int ret = tdm_get_port_idx(kcontrol, &port);
2756
2757 if (ret) {
2758 pr_err("%s: unsupported control: %s\n",
2759 __func__, kcontrol->id.name);
2760 } else {
2761 tdm_tx_cfg[port.mode][port.channel].bit_format =
2762 tdm_get_format(ucontrol->value.enumerated.item[0]);
2763
2764 pr_debug("%s: tdm_tx_bit_format = %d, item = %d\n", __func__,
2765 tdm_tx_cfg[port.mode][port.channel].bit_format,
2766 ucontrol->value.enumerated.item[0]);
2767 }
2768 return ret;
2769}
2770
2771static int tdm_rx_ch_get(struct snd_kcontrol *kcontrol,
2772 struct snd_ctl_elem_value *ucontrol)
2773{
2774 struct tdm_port port;
2775 int ret = tdm_get_port_idx(kcontrol, &port);
2776
2777 if (ret) {
2778 pr_err("%s: unsupported control: %s\n",
2779 __func__, kcontrol->id.name);
2780 } else {
2781
2782 ucontrol->value.enumerated.item[0] =
2783 tdm_rx_cfg[port.mode][port.channel].channels - 1;
2784
2785 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
2786 tdm_rx_cfg[port.mode][port.channel].channels - 1,
2787 ucontrol->value.enumerated.item[0]);
2788 }
2789 return ret;
2790}
2791
2792static int tdm_rx_ch_put(struct snd_kcontrol *kcontrol,
2793 struct snd_ctl_elem_value *ucontrol)
2794{
2795 struct tdm_port port;
2796 int ret = tdm_get_port_idx(kcontrol, &port);
2797
2798 if (ret) {
2799 pr_err("%s: unsupported control: %s\n",
2800 __func__, kcontrol->id.name);
2801 } else {
2802 tdm_rx_cfg[port.mode][port.channel].channels =
2803 ucontrol->value.enumerated.item[0] + 1;
2804
2805 pr_debug("%s: tdm_rx_ch = %d, item = %d\n", __func__,
2806 tdm_rx_cfg[port.mode][port.channel].channels,
2807 ucontrol->value.enumerated.item[0] + 1);
2808 }
2809 return ret;
2810}
2811
2812static int tdm_tx_ch_get(struct snd_kcontrol *kcontrol,
2813 struct snd_ctl_elem_value *ucontrol)
2814{
2815 struct tdm_port port;
2816 int ret = tdm_get_port_idx(kcontrol, &port);
2817
2818 if (ret) {
2819 pr_err("%s: unsupported control: %s\n",
2820 __func__, kcontrol->id.name);
2821 } else {
2822 ucontrol->value.enumerated.item[0] =
2823 tdm_tx_cfg[port.mode][port.channel].channels - 1;
2824
2825 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
2826 tdm_tx_cfg[port.mode][port.channel].channels - 1,
2827 ucontrol->value.enumerated.item[0]);
2828 }
2829 return ret;
2830}
2831
2832static int tdm_tx_ch_put(struct snd_kcontrol *kcontrol,
2833 struct snd_ctl_elem_value *ucontrol)
2834{
2835 struct tdm_port port;
2836 int ret = tdm_get_port_idx(kcontrol, &port);
2837
2838 if (ret) {
2839 pr_err("%s: unsupported control: %s\n",
2840 __func__, kcontrol->id.name);
2841 } else {
2842 tdm_tx_cfg[port.mode][port.channel].channels =
2843 ucontrol->value.enumerated.item[0] + 1;
2844
2845 pr_debug("%s: tdm_tx_ch = %d, item = %d\n", __func__,
2846 tdm_tx_cfg[port.mode][port.channel].channels,
2847 ucontrol->value.enumerated.item[0] + 1);
2848 }
2849 return ret;
2850}
2851
2852static int aux_pcm_get_port_idx(struct snd_kcontrol *kcontrol)
2853{
2854 int idx;
2855
2856 if (strnstr(kcontrol->id.name, "PRIM_AUX_PCM",
2857 sizeof("PRIM_AUX_PCM"))) {
2858 idx = PRIM_AUX_PCM;
2859 } else if (strnstr(kcontrol->id.name, "SEC_AUX_PCM",
2860 sizeof("SEC_AUX_PCM"))) {
2861 idx = SEC_AUX_PCM;
2862 } else if (strnstr(kcontrol->id.name, "TERT_AUX_PCM",
2863 sizeof("TERT_AUX_PCM"))) {
2864 idx = TERT_AUX_PCM;
2865 } else if (strnstr(kcontrol->id.name, "QUAT_AUX_PCM",
2866 sizeof("QUAT_AUX_PCM"))) {
2867 idx = QUAT_AUX_PCM;
2868 } else if (strnstr(kcontrol->id.name, "QUIN_AUX_PCM",
2869 sizeof("QUIN_AUX_PCM"))) {
2870 idx = QUIN_AUX_PCM;
2871 } else {
2872 pr_err("%s: unsupported port: %s\n",
2873 __func__, kcontrol->id.name);
2874 idx = -EINVAL;
2875 }
2876
2877 return idx;
2878}
2879
2880static int aux_pcm_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
2881 struct snd_ctl_elem_value *ucontrol)
2882{
2883 int idx = aux_pcm_get_port_idx(kcontrol);
2884
2885 if (idx < 0)
2886 return idx;
2887
2888 aux_pcm_rx_cfg[idx].sample_rate =
2889 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2890
2891 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2892 idx, aux_pcm_rx_cfg[idx].sample_rate,
2893 ucontrol->value.enumerated.item[0]);
2894
2895 return 0;
2896}
2897
2898static int aux_pcm_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
2899 struct snd_ctl_elem_value *ucontrol)
2900{
2901 int idx = aux_pcm_get_port_idx(kcontrol);
2902
2903 if (idx < 0)
2904 return idx;
2905
2906 ucontrol->value.enumerated.item[0] =
2907 aux_pcm_get_sample_rate_val(aux_pcm_rx_cfg[idx].sample_rate);
2908
2909 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
2910 idx, aux_pcm_rx_cfg[idx].sample_rate,
2911 ucontrol->value.enumerated.item[0]);
2912
2913 return 0;
2914}
2915
2916static int aux_pcm_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
2917 struct snd_ctl_elem_value *ucontrol)
2918{
2919 int idx = aux_pcm_get_port_idx(kcontrol);
2920
2921 if (idx < 0)
2922 return idx;
2923
2924 aux_pcm_tx_cfg[idx].sample_rate =
2925 aux_pcm_get_sample_rate(ucontrol->value.enumerated.item[0]);
2926
2927 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2928 idx, aux_pcm_tx_cfg[idx].sample_rate,
2929 ucontrol->value.enumerated.item[0]);
2930
2931 return 0;
2932}
2933
2934static int aux_pcm_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
2935 struct snd_ctl_elem_value *ucontrol)
2936{
2937 int idx = aux_pcm_get_port_idx(kcontrol);
2938
2939 if (idx < 0)
2940 return idx;
2941
2942 ucontrol->value.enumerated.item[0] =
2943 aux_pcm_get_sample_rate_val(aux_pcm_tx_cfg[idx].sample_rate);
2944
2945 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
2946 idx, aux_pcm_tx_cfg[idx].sample_rate,
2947 ucontrol->value.enumerated.item[0]);
2948
2949 return 0;
2950}
2951
2952static int mi2s_get_port_idx(struct snd_kcontrol *kcontrol)
2953{
2954 int idx;
2955
2956 if (strnstr(kcontrol->id.name, "PRIM_MI2S_RX",
2957 sizeof("PRIM_MI2S_RX"))) {
2958 idx = PRIM_MI2S;
2959 } else if (strnstr(kcontrol->id.name, "SEC_MI2S_RX",
2960 sizeof("SEC_MI2S_RX"))) {
2961 idx = SEC_MI2S;
2962 } else if (strnstr(kcontrol->id.name, "TERT_MI2S_RX",
2963 sizeof("TERT_MI2S_RX"))) {
2964 idx = TERT_MI2S;
2965 } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_RX",
2966 sizeof("QUAT_MI2S_RX"))) {
2967 idx = QUAT_MI2S;
2968 } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_RX",
2969 sizeof("QUIN_MI2S_RX"))) {
2970 idx = QUIN_MI2S;
2971 } else if (strnstr(kcontrol->id.name, "PRIM_MI2S_TX",
2972 sizeof("PRIM_MI2S_TX"))) {
2973 idx = PRIM_MI2S;
2974 } else if (strnstr(kcontrol->id.name, "SEC_MI2S_TX",
2975 sizeof("SEC_MI2S_TX"))) {
2976 idx = SEC_MI2S;
2977 } else if (strnstr(kcontrol->id.name, "TERT_MI2S_TX",
2978 sizeof("TERT_MI2S_TX"))) {
2979 idx = TERT_MI2S;
2980 } else if (strnstr(kcontrol->id.name, "QUAT_MI2S_TX",
2981 sizeof("QUAT_MI2S_TX"))) {
2982 idx = QUAT_MI2S;
2983 } else if (strnstr(kcontrol->id.name, "QUIN_MI2S_TX",
2984 sizeof("QUIN_MI2S_TX"))) {
2985 idx = QUIN_MI2S;
2986 } else {
2987 pr_err("%s: unsupported channel: %s\n",
2988 __func__, kcontrol->id.name);
2989 idx = -EINVAL;
2990 }
2991
2992 return idx;
2993}
2994
2995static int mi2s_get_sample_rate_val(int sample_rate)
2996{
2997 int sample_rate_val;
2998
2999 switch (sample_rate) {
3000 case SAMPLING_RATE_8KHZ:
3001 sample_rate_val = 0;
3002 break;
3003 case SAMPLING_RATE_11P025KHZ:
3004 sample_rate_val = 1;
3005 break;
3006 case SAMPLING_RATE_16KHZ:
3007 sample_rate_val = 2;
3008 break;
3009 case SAMPLING_RATE_22P05KHZ:
3010 sample_rate_val = 3;
3011 break;
3012 case SAMPLING_RATE_32KHZ:
3013 sample_rate_val = 4;
3014 break;
3015 case SAMPLING_RATE_44P1KHZ:
3016 sample_rate_val = 5;
3017 break;
3018 case SAMPLING_RATE_48KHZ:
3019 sample_rate_val = 6;
3020 break;
3021 case SAMPLING_RATE_96KHZ:
3022 sample_rate_val = 7;
3023 break;
3024 case SAMPLING_RATE_192KHZ:
3025 sample_rate_val = 8;
3026 break;
3027 default:
3028 sample_rate_val = 6;
3029 break;
3030 }
3031 return sample_rate_val;
3032}
3033
3034static int mi2s_get_sample_rate(int value)
3035{
3036 int sample_rate;
3037
3038 switch (value) {
3039 case 0:
3040 sample_rate = SAMPLING_RATE_8KHZ;
3041 break;
3042 case 1:
3043 sample_rate = SAMPLING_RATE_11P025KHZ;
3044 break;
3045 case 2:
3046 sample_rate = SAMPLING_RATE_16KHZ;
3047 break;
3048 case 3:
3049 sample_rate = SAMPLING_RATE_22P05KHZ;
3050 break;
3051 case 4:
3052 sample_rate = SAMPLING_RATE_32KHZ;
3053 break;
3054 case 5:
3055 sample_rate = SAMPLING_RATE_44P1KHZ;
3056 break;
3057 case 6:
3058 sample_rate = SAMPLING_RATE_48KHZ;
3059 break;
3060 case 7:
3061 sample_rate = SAMPLING_RATE_96KHZ;
3062 break;
3063 case 8:
3064 sample_rate = SAMPLING_RATE_192KHZ;
3065 break;
3066 default:
3067 sample_rate = SAMPLING_RATE_48KHZ;
3068 break;
3069 }
3070 return sample_rate;
3071}
3072
3073static int mi2s_auxpcm_get_format(int value)
3074{
3075 int format;
3076
3077 switch (value) {
3078 case 0:
3079 format = SNDRV_PCM_FORMAT_S16_LE;
3080 break;
3081 case 1:
3082 format = SNDRV_PCM_FORMAT_S24_LE;
3083 break;
3084 case 2:
3085 format = SNDRV_PCM_FORMAT_S24_3LE;
3086 break;
3087 case 3:
3088 format = SNDRV_PCM_FORMAT_S32_LE;
3089 break;
3090 default:
3091 format = SNDRV_PCM_FORMAT_S16_LE;
3092 break;
3093 }
3094 return format;
3095}
3096
3097static int mi2s_auxpcm_get_format_value(int format)
3098{
3099 int value;
3100
3101 switch (format) {
3102 case SNDRV_PCM_FORMAT_S16_LE:
3103 value = 0;
3104 break;
3105 case SNDRV_PCM_FORMAT_S24_LE:
3106 value = 1;
3107 break;
3108 case SNDRV_PCM_FORMAT_S24_3LE:
3109 value = 2;
3110 break;
3111 case SNDRV_PCM_FORMAT_S32_LE:
3112 value = 3;
3113 break;
3114 default:
3115 value = 0;
3116 break;
3117 }
3118 return value;
3119}
3120
3121static int mi2s_rx_sample_rate_put(struct snd_kcontrol *kcontrol,
3122 struct snd_ctl_elem_value *ucontrol)
3123{
3124 int idx = mi2s_get_port_idx(kcontrol);
3125
3126 if (idx < 0)
3127 return idx;
3128
3129 mi2s_rx_cfg[idx].sample_rate =
3130 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
3131
3132 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
3133 idx, mi2s_rx_cfg[idx].sample_rate,
3134 ucontrol->value.enumerated.item[0]);
3135
3136 return 0;
3137}
3138
3139static int mi2s_rx_sample_rate_get(struct snd_kcontrol *kcontrol,
3140 struct snd_ctl_elem_value *ucontrol)
3141{
3142 int idx = mi2s_get_port_idx(kcontrol);
3143
3144 if (idx < 0)
3145 return idx;
3146
3147 ucontrol->value.enumerated.item[0] =
3148 mi2s_get_sample_rate_val(mi2s_rx_cfg[idx].sample_rate);
3149
3150 pr_debug("%s: idx[%d]_rx_sample_rate = %d, item = %d\n", __func__,
3151 idx, mi2s_rx_cfg[idx].sample_rate,
3152 ucontrol->value.enumerated.item[0]);
3153
3154 return 0;
3155}
3156
3157static int mi2s_tx_sample_rate_put(struct snd_kcontrol *kcontrol,
3158 struct snd_ctl_elem_value *ucontrol)
3159{
3160 int idx = mi2s_get_port_idx(kcontrol);
3161
3162 if (idx < 0)
3163 return idx;
3164
3165 mi2s_tx_cfg[idx].sample_rate =
3166 mi2s_get_sample_rate(ucontrol->value.enumerated.item[0]);
3167
3168 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
3169 idx, mi2s_tx_cfg[idx].sample_rate,
3170 ucontrol->value.enumerated.item[0]);
3171
3172 return 0;
3173}
3174
3175static int mi2s_tx_sample_rate_get(struct snd_kcontrol *kcontrol,
3176 struct snd_ctl_elem_value *ucontrol)
3177{
3178 int idx = mi2s_get_port_idx(kcontrol);
3179
3180 if (idx < 0)
3181 return idx;
3182
3183 ucontrol->value.enumerated.item[0] =
3184 mi2s_get_sample_rate_val(mi2s_tx_cfg[idx].sample_rate);
3185
3186 pr_debug("%s: idx[%d]_tx_sample_rate = %d, item = %d\n", __func__,
3187 idx, mi2s_tx_cfg[idx].sample_rate,
3188 ucontrol->value.enumerated.item[0]);
3189
3190 return 0;
3191}
3192
3193static int msm_mi2s_rx_ch_get(struct snd_kcontrol *kcontrol,
3194 struct snd_ctl_elem_value *ucontrol)
3195{
3196 int idx = mi2s_get_port_idx(kcontrol);
3197
3198 if (idx < 0)
3199 return idx;
3200
3201 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
3202 idx, mi2s_rx_cfg[idx].channels);
3203 ucontrol->value.enumerated.item[0] = mi2s_rx_cfg[idx].channels - 1;
3204
3205 return 0;
3206}
3207
3208static int msm_mi2s_rx_ch_put(struct snd_kcontrol *kcontrol,
3209 struct snd_ctl_elem_value *ucontrol)
3210{
3211 int idx = mi2s_get_port_idx(kcontrol);
3212
3213 if (idx < 0)
3214 return idx;
3215
3216 mi2s_rx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
3217 pr_debug("%s: msm_mi2s_[%d]_rx_ch = %d\n", __func__,
3218 idx, mi2s_rx_cfg[idx].channels);
3219
3220 return 1;
3221}
3222
3223static int msm_mi2s_tx_ch_get(struct snd_kcontrol *kcontrol,
3224 struct snd_ctl_elem_value *ucontrol)
3225{
3226 int idx = mi2s_get_port_idx(kcontrol);
3227
3228 if (idx < 0)
3229 return idx;
3230
3231 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
3232 idx, mi2s_tx_cfg[idx].channels);
3233 ucontrol->value.enumerated.item[0] = mi2s_tx_cfg[idx].channels - 1;
3234
3235 return 0;
3236}
3237
3238static int msm_mi2s_tx_ch_put(struct snd_kcontrol *kcontrol,
3239 struct snd_ctl_elem_value *ucontrol)
3240{
3241 int idx = mi2s_get_port_idx(kcontrol);
3242
3243 if (idx < 0)
3244 return idx;
3245
3246 mi2s_tx_cfg[idx].channels = ucontrol->value.enumerated.item[0] + 1;
3247 pr_debug("%s: msm_mi2s_[%d]_tx_ch = %d\n", __func__,
3248 idx, mi2s_tx_cfg[idx].channels);
3249
3250 return 1;
3251}
3252
3253static int msm_mi2s_rx_format_get(struct snd_kcontrol *kcontrol,
3254 struct snd_ctl_elem_value *ucontrol)
3255{
3256 int idx = mi2s_get_port_idx(kcontrol);
3257
3258 if (idx < 0)
3259 return idx;
3260
3261 ucontrol->value.enumerated.item[0] =
3262 mi2s_auxpcm_get_format_value(mi2s_rx_cfg[idx].bit_format);
3263
3264 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
3265 idx, mi2s_rx_cfg[idx].bit_format,
3266 ucontrol->value.enumerated.item[0]);
3267
3268 return 0;
3269}
3270
3271static int msm_mi2s_rx_format_put(struct snd_kcontrol *kcontrol,
3272 struct snd_ctl_elem_value *ucontrol)
3273{
3274 int idx = mi2s_get_port_idx(kcontrol);
3275
3276 if (idx < 0)
3277 return idx;
3278
3279 mi2s_rx_cfg[idx].bit_format =
3280 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
3281
3282 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
3283 idx, mi2s_rx_cfg[idx].bit_format,
3284 ucontrol->value.enumerated.item[0]);
3285
3286 return 0;
3287}
3288
3289static int msm_mi2s_tx_format_get(struct snd_kcontrol *kcontrol,
3290 struct snd_ctl_elem_value *ucontrol)
3291{
3292 int idx = mi2s_get_port_idx(kcontrol);
3293
3294 if (idx < 0)
3295 return idx;
3296
3297 ucontrol->value.enumerated.item[0] =
3298 mi2s_auxpcm_get_format_value(mi2s_tx_cfg[idx].bit_format);
3299
3300 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
3301 idx, mi2s_tx_cfg[idx].bit_format,
3302 ucontrol->value.enumerated.item[0]);
3303
3304 return 0;
3305}
3306
3307static int msm_mi2s_tx_format_put(struct snd_kcontrol *kcontrol,
3308 struct snd_ctl_elem_value *ucontrol)
3309{
3310 int idx = mi2s_get_port_idx(kcontrol);
3311
3312 if (idx < 0)
3313 return idx;
3314
3315 mi2s_tx_cfg[idx].bit_format =
3316 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
3317
3318 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
3319 idx, mi2s_tx_cfg[idx].bit_format,
3320 ucontrol->value.enumerated.item[0]);
3321
3322 return 0;
3323}
3324
3325static int msm_aux_pcm_rx_format_get(struct snd_kcontrol *kcontrol,
3326 struct snd_ctl_elem_value *ucontrol)
3327{
3328 int idx = aux_pcm_get_port_idx(kcontrol);
3329
3330 if (idx < 0)
3331 return idx;
3332
3333 ucontrol->value.enumerated.item[0] =
3334 mi2s_auxpcm_get_format_value(aux_pcm_rx_cfg[idx].bit_format);
3335
3336 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
3337 idx, aux_pcm_rx_cfg[idx].bit_format,
3338 ucontrol->value.enumerated.item[0]);
3339
3340 return 0;
3341}
3342
3343static int msm_aux_pcm_rx_format_put(struct snd_kcontrol *kcontrol,
3344 struct snd_ctl_elem_value *ucontrol)
3345{
3346 int idx = aux_pcm_get_port_idx(kcontrol);
3347
3348 if (idx < 0)
3349 return idx;
3350
3351 aux_pcm_rx_cfg[idx].bit_format =
3352 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
3353
3354 pr_debug("%s: idx[%d]_rx_format = %d, item = %d\n", __func__,
3355 idx, aux_pcm_rx_cfg[idx].bit_format,
3356 ucontrol->value.enumerated.item[0]);
3357
3358 return 0;
3359}
3360
3361static int msm_aux_pcm_tx_format_get(struct snd_kcontrol *kcontrol,
3362 struct snd_ctl_elem_value *ucontrol)
3363{
3364 int idx = aux_pcm_get_port_idx(kcontrol);
3365
3366 if (idx < 0)
3367 return idx;
3368
3369 ucontrol->value.enumerated.item[0] =
3370 mi2s_auxpcm_get_format_value(aux_pcm_tx_cfg[idx].bit_format);
3371
3372 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
3373 idx, aux_pcm_tx_cfg[idx].bit_format,
3374 ucontrol->value.enumerated.item[0]);
3375
3376 return 0;
3377}
3378
3379static int msm_aux_pcm_tx_format_put(struct snd_kcontrol *kcontrol,
3380 struct snd_ctl_elem_value *ucontrol)
3381{
3382 int idx = aux_pcm_get_port_idx(kcontrol);
3383
3384 if (idx < 0)
3385 return idx;
3386
3387 aux_pcm_tx_cfg[idx].bit_format =
3388 mi2s_auxpcm_get_format(ucontrol->value.enumerated.item[0]);
3389
3390 pr_debug("%s: idx[%d]_tx_format = %d, item = %d\n", __func__,
3391 idx, aux_pcm_tx_cfg[idx].bit_format,
3392 ucontrol->value.enumerated.item[0]);
3393
3394 return 0;
3395}
3396
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3397static int msm_hifi_ctrl(struct snd_soc_component *component)
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3398{
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3399 struct snd_soc_dapm_context *dapm =
3400 snd_soc_component_get_dapm(component);
3401 struct snd_soc_card *card = component->card;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3402 struct msm_asoc_mach_data *pdata =
3403 snd_soc_card_get_drvdata(card);
3404
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3405 dev_dbg(component->dev, "%s: msm_hifi_control = %d\n", __func__,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3406 msm_hifi_control);
3407
3408 if (!pdata || !pdata->hph_en1_gpio_p) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3409 dev_err(component->dev, "%s: hph_en1_gpio is invalid\n",
3410 __func__);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3411 return -EINVAL;
3412 }
3413 if (msm_hifi_control == MSM_HIFI_ON) {
3414 msm_cdc_pinctrl_select_active_state(pdata->hph_en1_gpio_p);
3415 /* 5msec delay needed as per HW requirement */
3416 usleep_range(5000, 5010);
3417 } else {
3418 msm_cdc_pinctrl_select_sleep_state(pdata->hph_en1_gpio_p);
3419 }
3420 snd_soc_dapm_sync(dapm);
3421
3422 return 0;
3423}
3424
3425static int msm_hifi_get(struct snd_kcontrol *kcontrol,
3426 struct snd_ctl_elem_value *ucontrol)
3427{
3428 pr_debug("%s: msm_hifi_control = %d\n",
3429 __func__, msm_hifi_control);
3430 ucontrol->value.integer.value[0] = msm_hifi_control;
3431
3432 return 0;
3433}
3434
3435static int msm_hifi_put(struct snd_kcontrol *kcontrol,
3436 struct snd_ctl_elem_value *ucontrol)
3437{
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3438 struct snd_soc_component *component =
3439 snd_soc_kcontrol_component(kcontrol);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3440
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3441 dev_dbg(component->dev, "%s: ucontrol->value.integer.value[0] = %ld\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3442 __func__, ucontrol->value.integer.value[0]);
3443
3444 msm_hifi_control = ucontrol->value.integer.value[0];
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3445 msm_hifi_ctrl(component);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3446
3447 return 0;
3448}
3449
3450static const struct snd_kcontrol_new msm_int_snd_controls[] = {
3451 SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Channels", wsa_cdc_dma_rx_0_chs,
3452 cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
3453 SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Channels", wsa_cdc_dma_rx_1_chs,
3454 cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
3455 SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Channels", rx_cdc_dma_rx_0_chs,
3456 cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
3457 SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Channels", rx_cdc_dma_rx_1_chs,
3458 cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
3459 SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Channels", rx_cdc_dma_rx_2_chs,
3460 cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
3461 SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Channels", rx_cdc_dma_rx_3_chs,
3462 cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
3463 SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Channels", rx_cdc_dma_rx_5_chs,
3464 cdc_dma_rx_ch_get, cdc_dma_rx_ch_put),
3465 SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 Channels", wsa_cdc_dma_tx_0_chs,
3466 cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
3467 SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Channels", wsa_cdc_dma_tx_1_chs,
3468 cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
3469 SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Channels", wsa_cdc_dma_tx_2_chs,
3470 cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
3471 SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Channels", tx_cdc_dma_tx_0_chs,
3472 cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
3473 SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Channels", tx_cdc_dma_tx_3_chs,
3474 cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
3475 SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Channels", tx_cdc_dma_tx_4_chs,
3476 cdc_dma_tx_ch_get, cdc_dma_tx_ch_put),
3477 SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 Format", wsa_cdc_dma_rx_0_format,
3478 cdc_dma_rx_format_get, cdc_dma_rx_format_put),
3479 SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 Format", wsa_cdc_dma_rx_1_format,
3480 cdc_dma_rx_format_get, cdc_dma_rx_format_put),
3481 SOC_ENUM_EXT("RX_CDC_DMA_RX_0 Format", rx_cdc_dma_rx_0_format,
3482 cdc_dma_rx_format_get, cdc_dma_rx_format_put),
3483 SOC_ENUM_EXT("RX_CDC_DMA_RX_1 Format", rx_cdc_dma_rx_1_format,
3484 cdc_dma_rx_format_get, cdc_dma_rx_format_put),
3485 SOC_ENUM_EXT("RX_CDC_DMA_RX_2 Format", rx_cdc_dma_rx_2_format,
3486 cdc_dma_rx_format_get, cdc_dma_rx_format_put),
3487 SOC_ENUM_EXT("RX_CDC_DMA_RX_3 Format", rx_cdc_dma_rx_3_format,
3488 cdc_dma_rx_format_get, cdc_dma_rx_format_put),
3489 SOC_ENUM_EXT("RX_CDC_DMA_RX_5 Format", rx_cdc_dma_rx_5_format,
3490 cdc_dma_rx_format_get, cdc_dma_rx_format_put),
3491 SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 Format", wsa_cdc_dma_tx_1_format,
3492 cdc_dma_tx_format_get, cdc_dma_tx_format_put),
3493 SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 Format", wsa_cdc_dma_tx_2_format,
3494 cdc_dma_tx_format_get, cdc_dma_tx_format_put),
3495 SOC_ENUM_EXT("TX_CDC_DMA_TX_0 Format", tx_cdc_dma_tx_0_format,
3496 cdc_dma_tx_format_get, cdc_dma_tx_format_put),
3497 SOC_ENUM_EXT("TX_CDC_DMA_TX_3 Format", tx_cdc_dma_tx_3_format,
3498 cdc_dma_tx_format_get, cdc_dma_tx_format_put),
3499 SOC_ENUM_EXT("TX_CDC_DMA_TX_4 Format", tx_cdc_dma_tx_4_format,
3500 cdc_dma_tx_format_get, cdc_dma_tx_format_put),
3501 SOC_ENUM_EXT("WSA_CDC_DMA_RX_0 SampleRate",
3502 wsa_cdc_dma_rx_0_sample_rate,
3503 cdc_dma_rx_sample_rate_get,
3504 cdc_dma_rx_sample_rate_put),
3505 SOC_ENUM_EXT("WSA_CDC_DMA_RX_1 SampleRate",
3506 wsa_cdc_dma_rx_1_sample_rate,
3507 cdc_dma_rx_sample_rate_get,
3508 cdc_dma_rx_sample_rate_put),
3509 SOC_ENUM_EXT("RX_CDC_DMA_RX_0 SampleRate",
3510 rx_cdc_dma_rx_0_sample_rate,
3511 cdc_dma_rx_sample_rate_get,
3512 cdc_dma_rx_sample_rate_put),
3513 SOC_ENUM_EXT("RX_CDC_DMA_RX_1 SampleRate",
3514 rx_cdc_dma_rx_1_sample_rate,
3515 cdc_dma_rx_sample_rate_get,
3516 cdc_dma_rx_sample_rate_put),
3517 SOC_ENUM_EXT("RX_CDC_DMA_RX_2 SampleRate",
3518 rx_cdc_dma_rx_2_sample_rate,
3519 cdc_dma_rx_sample_rate_get,
3520 cdc_dma_rx_sample_rate_put),
3521 SOC_ENUM_EXT("RX_CDC_DMA_RX_3 SampleRate",
3522 rx_cdc_dma_rx_3_sample_rate,
3523 cdc_dma_rx_sample_rate_get,
3524 cdc_dma_rx_sample_rate_put),
3525 SOC_ENUM_EXT("RX_CDC_DMA_RX_5 SampleRate",
3526 rx_cdc_dma_rx_5_sample_rate,
3527 cdc_dma_rx_sample_rate_get,
3528 cdc_dma_rx_sample_rate_put),
3529 SOC_ENUM_EXT("WSA_CDC_DMA_TX_0 SampleRate",
3530 wsa_cdc_dma_tx_0_sample_rate,
3531 cdc_dma_tx_sample_rate_get,
3532 cdc_dma_tx_sample_rate_put),
3533 SOC_ENUM_EXT("WSA_CDC_DMA_TX_1 SampleRate",
3534 wsa_cdc_dma_tx_1_sample_rate,
3535 cdc_dma_tx_sample_rate_get,
3536 cdc_dma_tx_sample_rate_put),
3537 SOC_ENUM_EXT("WSA_CDC_DMA_TX_2 SampleRate",
3538 wsa_cdc_dma_tx_2_sample_rate,
3539 cdc_dma_tx_sample_rate_get,
3540 cdc_dma_tx_sample_rate_put),
3541 SOC_ENUM_EXT("TX_CDC_DMA_TX_0 SampleRate",
3542 tx_cdc_dma_tx_0_sample_rate,
3543 cdc_dma_tx_sample_rate_get,
3544 cdc_dma_tx_sample_rate_put),
3545 SOC_ENUM_EXT("TX_CDC_DMA_TX_3 SampleRate",
3546 tx_cdc_dma_tx_3_sample_rate,
3547 cdc_dma_tx_sample_rate_get,
3548 cdc_dma_tx_sample_rate_put),
3549 SOC_ENUM_EXT("TX_CDC_DMA_TX_4 SampleRate",
3550 tx_cdc_dma_tx_4_sample_rate,
3551 cdc_dma_tx_sample_rate_get,
3552 cdc_dma_tx_sample_rate_put),
3553};
3554
3555static const struct snd_kcontrol_new msm_tavil_snd_controls[] = {
3556 SOC_ENUM_EXT("SLIM_0_RX Channels", slim_0_rx_chs,
3557 slim_rx_ch_get, slim_rx_ch_put),
3558 SOC_ENUM_EXT("SLIM_2_RX Channels", slim_2_rx_chs,
3559 slim_rx_ch_get, slim_rx_ch_put),
3560 SOC_ENUM_EXT("SLIM_0_TX Channels", slim_0_tx_chs,
3561 slim_tx_ch_get, slim_tx_ch_put),
3562 SOC_ENUM_EXT("SLIM_1_TX Channels", slim_1_tx_chs,
3563 slim_tx_ch_get, slim_tx_ch_put),
3564 SOC_ENUM_EXT("SLIM_5_RX Channels", slim_5_rx_chs,
3565 slim_rx_ch_get, slim_rx_ch_put),
3566 SOC_ENUM_EXT("SLIM_6_RX Channels", slim_6_rx_chs,
3567 slim_rx_ch_get, slim_rx_ch_put),
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3568 SOC_ENUM_EXT("SLIM_0_RX Format", slim_0_rx_format,
3569 slim_rx_bit_format_get, slim_rx_bit_format_put),
3570 SOC_ENUM_EXT("SLIM_5_RX Format", slim_5_rx_format,
3571 slim_rx_bit_format_get, slim_rx_bit_format_put),
3572 SOC_ENUM_EXT("SLIM_6_RX Format", slim_6_rx_format,
3573 slim_rx_bit_format_get, slim_rx_bit_format_put),
3574 SOC_ENUM_EXT("SLIM_0_TX Format", slim_0_tx_format,
3575 slim_tx_bit_format_get, slim_tx_bit_format_put),
3576 SOC_ENUM_EXT("SLIM_0_RX SampleRate", slim_0_rx_sample_rate,
3577 slim_rx_sample_rate_get, slim_rx_sample_rate_put),
3578 SOC_ENUM_EXT("SLIM_2_RX SampleRate", slim_2_rx_sample_rate,
3579 slim_rx_sample_rate_get, slim_rx_sample_rate_put),
3580 SOC_ENUM_EXT("SLIM_0_TX SampleRate", slim_0_tx_sample_rate,
3581 slim_tx_sample_rate_get, slim_tx_sample_rate_put),
3582 SOC_ENUM_EXT("SLIM_5_RX SampleRate", slim_5_rx_sample_rate,
3583 slim_rx_sample_rate_get, slim_rx_sample_rate_put),
3584 SOC_ENUM_EXT("SLIM_6_RX SampleRate", slim_6_rx_sample_rate,
3585 slim_rx_sample_rate_get, slim_rx_sample_rate_put),
3586};
3587
3588static const struct snd_kcontrol_new msm_common_snd_controls[] = {
3589 SOC_ENUM_EXT("USB_AUDIO_RX Channels", usb_rx_chs,
3590 usb_audio_rx_ch_get, usb_audio_rx_ch_put),
3591 SOC_ENUM_EXT("USB_AUDIO_TX Channels", usb_tx_chs,
3592 usb_audio_tx_ch_get, usb_audio_tx_ch_put),
3593 SOC_ENUM_EXT("Display Port RX Channels", ext_disp_rx_chs,
3594 ext_disp_rx_ch_get, ext_disp_rx_ch_put),
3595 SOC_ENUM_EXT("PROXY_RX Channels", proxy_rx_chs,
3596 proxy_rx_ch_get, proxy_rx_ch_put),
3597 SOC_ENUM_EXT("USB_AUDIO_RX Format", usb_rx_format,
3598 usb_audio_rx_format_get, usb_audio_rx_format_put),
3599 SOC_ENUM_EXT("USB_AUDIO_TX Format", usb_tx_format,
3600 usb_audio_tx_format_get, usb_audio_tx_format_put),
3601 SOC_ENUM_EXT("Display Port RX Bit Format", ext_disp_rx_format,
3602 ext_disp_rx_format_get, ext_disp_rx_format_put),
3603 SOC_ENUM_EXT("USB_AUDIO_RX SampleRate", usb_rx_sample_rate,
3604 usb_audio_rx_sample_rate_get,
3605 usb_audio_rx_sample_rate_put),
3606 SOC_ENUM_EXT("USB_AUDIO_TX SampleRate", usb_tx_sample_rate,
3607 usb_audio_tx_sample_rate_get,
3608 usb_audio_tx_sample_rate_put),
3609 SOC_ENUM_EXT("Display Port RX SampleRate", ext_disp_rx_sample_rate,
3610 ext_disp_rx_sample_rate_get,
3611 ext_disp_rx_sample_rate_put),
3612 SOC_ENUM_EXT("PRI_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3613 tdm_rx_sample_rate_get,
3614 tdm_rx_sample_rate_put),
3615 SOC_ENUM_EXT("PRI_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3616 tdm_tx_sample_rate_get,
3617 tdm_tx_sample_rate_put),
3618 SOC_ENUM_EXT("PRI_TDM_RX_0 Format", tdm_rx_format,
3619 tdm_rx_format_get,
3620 tdm_rx_format_put),
3621 SOC_ENUM_EXT("PRI_TDM_TX_0 Format", tdm_tx_format,
3622 tdm_tx_format_get,
3623 tdm_tx_format_put),
3624 SOC_ENUM_EXT("PRI_TDM_RX_0 Channels", tdm_rx_chs,
3625 tdm_rx_ch_get,
3626 tdm_rx_ch_put),
3627 SOC_ENUM_EXT("PRI_TDM_TX_0 Channels", tdm_tx_chs,
3628 tdm_tx_ch_get,
3629 tdm_tx_ch_put),
3630 SOC_ENUM_EXT("SEC_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3631 tdm_rx_sample_rate_get,
3632 tdm_rx_sample_rate_put),
3633 SOC_ENUM_EXT("SEC_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3634 tdm_tx_sample_rate_get,
3635 tdm_tx_sample_rate_put),
3636 SOC_ENUM_EXT("SEC_TDM_RX_0 Format", tdm_rx_format,
3637 tdm_rx_format_get,
3638 tdm_rx_format_put),
3639 SOC_ENUM_EXT("SEC_TDM_TX_0 Format", tdm_tx_format,
3640 tdm_tx_format_get,
3641 tdm_tx_format_put),
3642 SOC_ENUM_EXT("SEC_TDM_RX_0 Channels", tdm_rx_chs,
3643 tdm_rx_ch_get,
3644 tdm_rx_ch_put),
3645 SOC_ENUM_EXT("SEC_TDM_TX_0 Channels", tdm_tx_chs,
3646 tdm_tx_ch_get,
3647 tdm_tx_ch_put),
3648 SOC_ENUM_EXT("TERT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3649 tdm_rx_sample_rate_get,
3650 tdm_rx_sample_rate_put),
3651 SOC_ENUM_EXT("TERT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3652 tdm_tx_sample_rate_get,
3653 tdm_tx_sample_rate_put),
3654 SOC_ENUM_EXT("TERT_TDM_RX_0 Format", tdm_rx_format,
3655 tdm_rx_format_get,
3656 tdm_rx_format_put),
3657 SOC_ENUM_EXT("TERT_TDM_TX_0 Format", tdm_tx_format,
3658 tdm_tx_format_get,
3659 tdm_tx_format_put),
3660 SOC_ENUM_EXT("TERT_TDM_RX_0 Channels", tdm_rx_chs,
3661 tdm_rx_ch_get,
3662 tdm_rx_ch_put),
3663 SOC_ENUM_EXT("TERT_TDM_TX_0 Channels", tdm_tx_chs,
3664 tdm_tx_ch_get,
3665 tdm_tx_ch_put),
3666 SOC_ENUM_EXT("QUAT_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3667 tdm_rx_sample_rate_get,
3668 tdm_rx_sample_rate_put),
3669 SOC_ENUM_EXT("QUAT_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3670 tdm_tx_sample_rate_get,
3671 tdm_tx_sample_rate_put),
3672 SOC_ENUM_EXT("QUAT_TDM_RX_0 Format", tdm_rx_format,
3673 tdm_rx_format_get,
3674 tdm_rx_format_put),
3675 SOC_ENUM_EXT("QUAT_TDM_TX_0 Format", tdm_tx_format,
3676 tdm_tx_format_get,
3677 tdm_tx_format_put),
3678 SOC_ENUM_EXT("QUAT_TDM_RX_0 Channels", tdm_rx_chs,
3679 tdm_rx_ch_get,
3680 tdm_rx_ch_put),
3681 SOC_ENUM_EXT("QUAT_TDM_TX_0 Channels", tdm_tx_chs,
3682 tdm_tx_ch_get,
3683 tdm_tx_ch_put),
3684 SOC_ENUM_EXT("QUIN_TDM_RX_0 SampleRate", tdm_rx_sample_rate,
3685 tdm_rx_sample_rate_get,
3686 tdm_rx_sample_rate_put),
3687 SOC_ENUM_EXT("QUIN_TDM_TX_0 SampleRate", tdm_tx_sample_rate,
3688 tdm_tx_sample_rate_get,
3689 tdm_tx_sample_rate_put),
3690 SOC_ENUM_EXT("QUIN_TDM_RX_0 Format", tdm_rx_format,
3691 tdm_rx_format_get,
3692 tdm_rx_format_put),
3693 SOC_ENUM_EXT("QUIN_TDM_TX_0 Format", tdm_tx_format,
3694 tdm_tx_format_get,
3695 tdm_tx_format_put),
3696 SOC_ENUM_EXT("QUIN_TDM_RX_0 Channels", tdm_rx_chs,
3697 tdm_rx_ch_get,
3698 tdm_rx_ch_put),
3699 SOC_ENUM_EXT("QUIN_TDM_TX_0 Channels", tdm_tx_chs,
3700 tdm_tx_ch_get,
3701 tdm_tx_ch_put),
3702 SOC_ENUM_EXT("PRIM_AUX_PCM_RX SampleRate", prim_aux_pcm_rx_sample_rate,
3703 aux_pcm_rx_sample_rate_get,
3704 aux_pcm_rx_sample_rate_put),
3705 SOC_ENUM_EXT("SEC_AUX_PCM_RX SampleRate", sec_aux_pcm_rx_sample_rate,
3706 aux_pcm_rx_sample_rate_get,
3707 aux_pcm_rx_sample_rate_put),
3708 SOC_ENUM_EXT("TERT_AUX_PCM_RX SampleRate", tert_aux_pcm_rx_sample_rate,
3709 aux_pcm_rx_sample_rate_get,
3710 aux_pcm_rx_sample_rate_put),
3711 SOC_ENUM_EXT("QUAT_AUX_PCM_RX SampleRate", quat_aux_pcm_rx_sample_rate,
3712 aux_pcm_rx_sample_rate_get,
3713 aux_pcm_rx_sample_rate_put),
3714 SOC_ENUM_EXT("QUIN_AUX_PCM_RX SampleRate", quin_aux_pcm_rx_sample_rate,
3715 aux_pcm_rx_sample_rate_get,
3716 aux_pcm_rx_sample_rate_put),
3717 SOC_ENUM_EXT("PRIM_AUX_PCM_TX SampleRate", prim_aux_pcm_tx_sample_rate,
3718 aux_pcm_tx_sample_rate_get,
3719 aux_pcm_tx_sample_rate_put),
3720 SOC_ENUM_EXT("SEC_AUX_PCM_TX SampleRate", sec_aux_pcm_tx_sample_rate,
3721 aux_pcm_tx_sample_rate_get,
3722 aux_pcm_tx_sample_rate_put),
3723 SOC_ENUM_EXT("TERT_AUX_PCM_TX SampleRate", tert_aux_pcm_tx_sample_rate,
3724 aux_pcm_tx_sample_rate_get,
3725 aux_pcm_tx_sample_rate_put),
3726 SOC_ENUM_EXT("QUAT_AUX_PCM_TX SampleRate", quat_aux_pcm_tx_sample_rate,
3727 aux_pcm_tx_sample_rate_get,
3728 aux_pcm_tx_sample_rate_put),
3729 SOC_ENUM_EXT("QUIN_AUX_PCM_TX SampleRate", quin_aux_pcm_tx_sample_rate,
3730 aux_pcm_tx_sample_rate_get,
3731 aux_pcm_tx_sample_rate_put),
3732 SOC_ENUM_EXT("PRIM_MI2S_RX SampleRate", prim_mi2s_rx_sample_rate,
3733 mi2s_rx_sample_rate_get,
3734 mi2s_rx_sample_rate_put),
3735 SOC_ENUM_EXT("SEC_MI2S_RX SampleRate", sec_mi2s_rx_sample_rate,
3736 mi2s_rx_sample_rate_get,
3737 mi2s_rx_sample_rate_put),
3738 SOC_ENUM_EXT("TERT_MI2S_RX SampleRate", tert_mi2s_rx_sample_rate,
3739 mi2s_rx_sample_rate_get,
3740 mi2s_rx_sample_rate_put),
3741 SOC_ENUM_EXT("QUAT_MI2S_RX SampleRate", quat_mi2s_rx_sample_rate,
3742 mi2s_rx_sample_rate_get,
3743 mi2s_rx_sample_rate_put),
3744 SOC_ENUM_EXT("QUIN_MI2S_RX SampleRate", quin_mi2s_rx_sample_rate,
3745 mi2s_rx_sample_rate_get,
3746 mi2s_rx_sample_rate_put),
3747 SOC_ENUM_EXT("PRIM_MI2S_TX SampleRate", prim_mi2s_tx_sample_rate,
3748 mi2s_tx_sample_rate_get,
3749 mi2s_tx_sample_rate_put),
3750 SOC_ENUM_EXT("SEC_MI2S_TX SampleRate", sec_mi2s_tx_sample_rate,
3751 mi2s_tx_sample_rate_get,
3752 mi2s_tx_sample_rate_put),
3753 SOC_ENUM_EXT("TERT_MI2S_TX SampleRate", tert_mi2s_tx_sample_rate,
3754 mi2s_tx_sample_rate_get,
3755 mi2s_tx_sample_rate_put),
3756 SOC_ENUM_EXT("QUAT_MI2S_TX SampleRate", quat_mi2s_tx_sample_rate,
3757 mi2s_tx_sample_rate_get,
3758 mi2s_tx_sample_rate_put),
3759 SOC_ENUM_EXT("QUIN_MI2S_TX SampleRate", quin_mi2s_tx_sample_rate,
3760 mi2s_tx_sample_rate_get,
3761 mi2s_tx_sample_rate_put),
3762 SOC_ENUM_EXT("PRIM_MI2S_RX Channels", prim_mi2s_rx_chs,
3763 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3764 SOC_ENUM_EXT("PRIM_MI2S_TX Channels", prim_mi2s_tx_chs,
3765 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3766 SOC_ENUM_EXT("SEC_MI2S_RX Channels", sec_mi2s_rx_chs,
3767 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3768 SOC_ENUM_EXT("SEC_MI2S_TX Channels", sec_mi2s_tx_chs,
3769 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3770 SOC_ENUM_EXT("TERT_MI2S_RX Channels", tert_mi2s_rx_chs,
3771 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3772 SOC_ENUM_EXT("TERT_MI2S_TX Channels", tert_mi2s_tx_chs,
3773 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3774 SOC_ENUM_EXT("QUAT_MI2S_RX Channels", quat_mi2s_rx_chs,
3775 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3776 SOC_ENUM_EXT("QUAT_MI2S_TX Channels", quat_mi2s_tx_chs,
3777 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3778 SOC_ENUM_EXT("QUIN_MI2S_RX Channels", quin_mi2s_rx_chs,
3779 msm_mi2s_rx_ch_get, msm_mi2s_rx_ch_put),
3780 SOC_ENUM_EXT("QUIN_MI2S_TX Channels", quin_mi2s_tx_chs,
3781 msm_mi2s_tx_ch_get, msm_mi2s_tx_ch_put),
3782 SOC_ENUM_EXT("PRIM_MI2S_RX Format", mi2s_rx_format,
3783 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3784 SOC_ENUM_EXT("PRIM_MI2S_TX Format", mi2s_tx_format,
3785 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3786 SOC_ENUM_EXT("SEC_MI2S_RX Format", mi2s_rx_format,
3787 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3788 SOC_ENUM_EXT("SEC_MI2S_TX Format", mi2s_tx_format,
3789 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3790 SOC_ENUM_EXT("TERT_MI2S_RX Format", mi2s_rx_format,
3791 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3792 SOC_ENUM_EXT("TERT_MI2S_TX Format", mi2s_tx_format,
3793 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3794 SOC_ENUM_EXT("QUAT_MI2S_RX Format", mi2s_rx_format,
3795 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3796 SOC_ENUM_EXT("QUAT_MI2S_TX Format", mi2s_tx_format,
3797 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3798 SOC_ENUM_EXT("QUIN_MI2S_RX Format", mi2s_rx_format,
3799 msm_mi2s_rx_format_get, msm_mi2s_rx_format_put),
3800 SOC_ENUM_EXT("QUIN_MI2S_TX Format", mi2s_tx_format,
3801 msm_mi2s_tx_format_get, msm_mi2s_tx_format_put),
3802 SOC_ENUM_EXT("PRIM_AUX_PCM_RX Format", aux_pcm_rx_format,
3803 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3804 SOC_ENUM_EXT("PRIM_AUX_PCM_TX Format", aux_pcm_tx_format,
3805 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3806 SOC_ENUM_EXT("SEC_AUX_PCM_RX Format", aux_pcm_rx_format,
3807 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3808 SOC_ENUM_EXT("SEC_AUX_PCM_TX Format", aux_pcm_tx_format,
3809 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3810 SOC_ENUM_EXT("TERT_AUX_PCM_RX Format", aux_pcm_rx_format,
3811 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3812 SOC_ENUM_EXT("TERT_AUX_PCM_TX Format", aux_pcm_tx_format,
3813 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3814 SOC_ENUM_EXT("QUAT_AUX_PCM_RX Format", aux_pcm_rx_format,
3815 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3816 SOC_ENUM_EXT("QUAT_AUX_PCM_TX Format", aux_pcm_tx_format,
3817 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3818 SOC_ENUM_EXT("QUIN_AUX_PCM_RX Format", aux_pcm_rx_format,
3819 msm_aux_pcm_rx_format_get, msm_aux_pcm_rx_format_put),
3820 SOC_ENUM_EXT("QUIN_AUX_PCM_TX Format", aux_pcm_tx_format,
3821 msm_aux_pcm_tx_format_get, msm_aux_pcm_tx_format_put),
3822 SOC_ENUM_EXT("HiFi Function", hifi_function, msm_hifi_get,
3823 msm_hifi_put),
3824 SOC_ENUM_EXT("BT SampleRate", bt_sample_rate,
3825 msm_bt_sample_rate_get,
3826 msm_bt_sample_rate_put),
Sharad Sangle493a1b32018-09-19 15:52:15 +0530[diff] [blame]3827 SOC_ENUM_EXT("BT SampleRate RX", bt_sample_rate_rx,
3828 msm_bt_sample_rate_rx_get,
3829 msm_bt_sample_rate_rx_put),
3830 SOC_ENUM_EXT("BT SampleRate TX", bt_sample_rate_tx,
3831 msm_bt_sample_rate_tx_get,
3832 msm_bt_sample_rate_tx_put),
Vatsal Bucha89262e62018-08-31 11:57:09 +0530[diff] [blame]3833 SOC_ENUM_EXT("VI_FEED_TX Channels", vi_feed_tx_chs,
3834 msm_vi_feed_tx_ch_get, msm_vi_feed_tx_ch_put),
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3835};
3836
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3837static int msm_snd_enable_codec_ext_clk(struct snd_soc_component *component,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3838 int enable, bool dapm)
3839{
3840 int ret = 0;
3841
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3842 if (!strcmp(component->name, "tavil_codec")) {
3843 ret = tavil_cdc_mclk_enable(component, enable);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3844 } else {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3845 dev_err(component->dev, "%s: unknown codec to enable ext clk\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3846 __func__);
3847 ret = -EINVAL;
3848 }
3849 return ret;
3850}
3851
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3852static int msm_snd_enable_codec_ext_tx_clk(struct snd_soc_component *component,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3853 int enable, bool dapm)
3854{
3855 int ret = 0;
3856
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3857 if (!strcmp(component->name, "tavil_codec")) {
3858 ret = tavil_cdc_mclk_tx_enable(component, enable);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3859 } else {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3860 dev_err(component->dev, "%s: unknown codec to enable TX ext clk\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3861 __func__);
3862 ret = -EINVAL;
3863 }
3864
3865 return ret;
3866}
3867
3868static int msm_mclk_tx_event(struct snd_soc_dapm_widget *w,
3869 struct snd_kcontrol *kcontrol, int event)
3870{
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3871 struct snd_soc_component *component =
3872 snd_soc_dapm_to_component(w->dapm);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3873
3874 pr_debug("%s: event = %d\n", __func__, event);
3875
3876 switch (event) {
3877 case SND_SOC_DAPM_PRE_PMU:
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3878 return msm_snd_enable_codec_ext_tx_clk(component, 1, true);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3879 case SND_SOC_DAPM_POST_PMD:
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3880 return msm_snd_enable_codec_ext_tx_clk(component, 0, true);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3881 }
3882 return 0;
3883}
3884
3885static int msm_mclk_event(struct snd_soc_dapm_widget *w,
3886 struct snd_kcontrol *kcontrol, int event)
3887{
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3888 struct snd_soc_component *component =
3889 snd_soc_dapm_to_component(w->dapm);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3890
3891 pr_debug("%s: event = %d\n", __func__, event);
3892
3893 switch (event) {
3894 case SND_SOC_DAPM_PRE_PMU:
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3895 return msm_snd_enable_codec_ext_clk(component, 1, true);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3896 case SND_SOC_DAPM_POST_PMD:
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3897 return msm_snd_enable_codec_ext_clk(component, 0, true);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3898 }
3899 return 0;
3900}
3901
3902static int msm_hifi_ctrl_event(struct snd_soc_dapm_widget *w,
3903 struct snd_kcontrol *k, int event)
3904{
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3905 struct snd_soc_component *component =
3906 snd_soc_dapm_to_component(w->dapm);
3907 struct snd_soc_card *card = component->card;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3908 struct msm_asoc_mach_data *pdata =
3909 snd_soc_card_get_drvdata(card);
3910
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3911 dev_dbg(component->dev, "%s: msm_hifi_control = %d\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3912 __func__, msm_hifi_control);
3913
3914 if (!pdata || !pdata->hph_en0_gpio_p) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3915 dev_err(component->dev, "%s: hph_en0_gpio is invalid\n",
3916 __func__);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3917 return -EINVAL;
3918 }
3919
3920 if (msm_hifi_control != MSM_HIFI_ON) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3921 dev_dbg(component->dev, "%s: HiFi mixer control is not set\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3922 __func__);
3923 return 0;
3924 }
3925
3926 switch (event) {
3927 case SND_SOC_DAPM_POST_PMU:
3928 msm_cdc_pinctrl_select_active_state(pdata->hph_en0_gpio_p);
3929 break;
3930 case SND_SOC_DAPM_PRE_PMD:
3931 msm_cdc_pinctrl_select_sleep_state(pdata->hph_en0_gpio_p);
3932 break;
3933 }
3934
3935 return 0;
3936}
3937
3938static const struct snd_soc_dapm_widget msm_dapm_widgets_tavil[] = {
3939
3940 SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0,
3941 msm_mclk_event,
3942 SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3943
3944 SND_SOC_DAPM_SUPPLY("MCLK TX", SND_SOC_NOPM, 0, 0,
3945 msm_mclk_tx_event, SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD),
3946
3947 SND_SOC_DAPM_SPK("Lineout_1 amp", NULL),
3948 SND_SOC_DAPM_SPK("Lineout_2 amp", NULL),
3949 SND_SOC_DAPM_SPK("hifi amp", msm_hifi_ctrl_event),
3950 SND_SOC_DAPM_MIC("Handset Mic", NULL),
3951 SND_SOC_DAPM_MIC("Headset Mic", NULL),
3952 SND_SOC_DAPM_MIC("ANCRight Headset Mic", NULL),
3953 SND_SOC_DAPM_MIC("ANCLeft Headset Mic", NULL),
3954 SND_SOC_DAPM_MIC("Analog Mic5", NULL),
3955
3956 SND_SOC_DAPM_MIC("Digital Mic0", NULL),
3957 SND_SOC_DAPM_MIC("Digital Mic1", NULL),
3958 SND_SOC_DAPM_MIC("Digital Mic2", NULL),
3959 SND_SOC_DAPM_MIC("Digital Mic3", NULL),
3960 SND_SOC_DAPM_MIC("Digital Mic4", NULL),
3961 SND_SOC_DAPM_MIC("Digital Mic5", NULL),
3962};
3963
3964static int msm_dmic_event(struct snd_soc_dapm_widget *w,
3965 struct snd_kcontrol *kcontrol, int event)
3966{
3967 struct msm_asoc_mach_data *pdata = NULL;
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3968 struct snd_soc_component *component =
3969 snd_soc_dapm_to_component(w->dapm);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3970 int ret = 0;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]3971 u32 dmic_idx;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3972 int *dmic_gpio_cnt;
3973 struct device_node *dmic_gpio;
3974 char *wname;
3975
3976 wname = strpbrk(w->name, "0123");
3977 if (!wname) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3978 dev_err(component->dev, "%s: widget not found\n", __func__);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3979 return -EINVAL;
3980 }
3981
3982 ret = kstrtouint(wname, 10, &dmic_idx);
3983 if (ret < 0) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3984 dev_err(component->dev, "%s: Invalid DMIC line on the codec\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3985 __func__);
3986 return -EINVAL;
3987 }
3988
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]3989 pdata = snd_soc_card_get_drvdata(component->card);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]3990
3991 switch (dmic_idx) {
3992 case 0:
3993 case 1:
3994 dmic_gpio_cnt = &dmic_0_1_gpio_cnt;
3995 dmic_gpio = pdata->dmic01_gpio_p;
3996 break;
3997 case 2:
3998 case 3:
3999 dmic_gpio_cnt = &dmic_2_3_gpio_cnt;
4000 dmic_gpio = pdata->dmic23_gpio_p;
4001 break;
4002 default:
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4003 dev_err(component->dev, "%s: Invalid DMIC Selection\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4004 __func__);
4005 return -EINVAL;
4006 }
4007
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4008 dev_dbg(component->dev, "%s: event %d DMIC%d dmic_gpio_cnt %d\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4009 __func__, event, dmic_idx, *dmic_gpio_cnt);
4010
4011 switch (event) {
4012 case SND_SOC_DAPM_PRE_PMU:
4013 (*dmic_gpio_cnt)++;
4014 if (*dmic_gpio_cnt == 1) {
4015 ret = msm_cdc_pinctrl_select_active_state(
4016 dmic_gpio);
4017 if (ret < 0) {
4018 pr_err("%s: gpio set cannot be activated %sd",
4019 __func__, "dmic_gpio");
4020 return ret;
4021 }
4022 }
4023
4024 break;
4025 case SND_SOC_DAPM_POST_PMD:
4026 (*dmic_gpio_cnt)--;
4027 if (*dmic_gpio_cnt == 0) {
4028 ret = msm_cdc_pinctrl_select_sleep_state(
4029 dmic_gpio);
4030 if (ret < 0) {
4031 pr_err("%s: gpio set cannot be de-activated %sd",
4032 __func__, "dmic_gpio");
4033 return ret;
4034 }
4035 }
4036 break;
4037 default:
4038 pr_err("%s: invalid DAPM event %d\n", __func__, event);
4039 return -EINVAL;
4040 }
4041 return 0;
4042}
4043
4044static const struct snd_soc_dapm_widget msm_int_dapm_widgets[] = {
4045 SND_SOC_DAPM_MIC("Analog Mic1", NULL),
4046 SND_SOC_DAPM_MIC("Analog Mic2", NULL),
4047 SND_SOC_DAPM_MIC("Analog Mic3", NULL),
4048 SND_SOC_DAPM_MIC("Analog Mic4", NULL),
4049 SND_SOC_DAPM_MIC("Digital Mic0", msm_dmic_event),
4050 SND_SOC_DAPM_MIC("Digital Mic1", msm_dmic_event),
4051 SND_SOC_DAPM_MIC("Digital Mic2", msm_dmic_event),
4052 SND_SOC_DAPM_MIC("Digital Mic3", msm_dmic_event),
4053};
4054
4055static inline int param_is_mask(int p)
4056{
4057 return (p >= SNDRV_PCM_HW_PARAM_FIRST_MASK) &&
4058 (p <= SNDRV_PCM_HW_PARAM_LAST_MASK);
4059}
4060
4061static inline struct snd_mask *param_to_mask(struct snd_pcm_hw_params *p,
4062 int n)
4063{
4064 return &(p->masks[n - SNDRV_PCM_HW_PARAM_FIRST_MASK]);
4065}
4066
4067static void param_set_mask(struct snd_pcm_hw_params *p, int n,
4068 unsigned int bit)
4069{
4070 if (bit >= SNDRV_MASK_MAX)
4071 return;
4072 if (param_is_mask(n)) {
4073 struct snd_mask *m = param_to_mask(p, n);
4074
4075 m->bits[0] = 0;
4076 m->bits[1] = 0;
4077 m->bits[bit >> 5] |= (1 << (bit & 31));
4078 }
4079}
4080
4081static int msm_slim_get_ch_from_beid(int32_t be_id)
4082{
4083 int ch_id = 0;
4084
4085 switch (be_id) {
4086 case MSM_BACKEND_DAI_SLIMBUS_0_RX:
4087 ch_id = SLIM_RX_0;
4088 break;
4089 case MSM_BACKEND_DAI_SLIMBUS_1_RX:
4090 ch_id = SLIM_RX_1;
4091 break;
4092 case MSM_BACKEND_DAI_SLIMBUS_2_RX:
4093 ch_id = SLIM_RX_2;
4094 break;
4095 case MSM_BACKEND_DAI_SLIMBUS_3_RX:
4096 ch_id = SLIM_RX_3;
4097 break;
4098 case MSM_BACKEND_DAI_SLIMBUS_4_RX:
4099 ch_id = SLIM_RX_4;
4100 break;
4101 case MSM_BACKEND_DAI_SLIMBUS_6_RX:
4102 ch_id = SLIM_RX_6;
4103 break;
4104 case MSM_BACKEND_DAI_SLIMBUS_0_TX:
4105 ch_id = SLIM_TX_0;
4106 break;
4107 case MSM_BACKEND_DAI_SLIMBUS_3_TX:
4108 ch_id = SLIM_TX_3;
4109 break;
4110 default:
4111 ch_id = SLIM_RX_0;
4112 break;
4113 }
4114
4115 return ch_id;
4116}
4117
4118static int msm_cdc_dma_get_idx_from_beid(int32_t be_id)
4119{
4120 int idx = 0;
4121
4122 switch (be_id) {
4123 case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
4124 idx = WSA_CDC_DMA_RX_0;
4125 break;
4126 case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
4127 idx = WSA_CDC_DMA_TX_0;
4128 break;
4129 case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
4130 idx = WSA_CDC_DMA_RX_1;
4131 break;
4132 case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
4133 idx = WSA_CDC_DMA_TX_1;
4134 break;
4135 case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
4136 idx = WSA_CDC_DMA_TX_2;
4137 break;
4138 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
4139 idx = RX_CDC_DMA_RX_0;
4140 break;
4141 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
4142 idx = RX_CDC_DMA_RX_1;
4143 break;
4144 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
4145 idx = RX_CDC_DMA_RX_2;
4146 break;
4147 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
4148 idx = RX_CDC_DMA_RX_3;
4149 break;
4150 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
4151 idx = RX_CDC_DMA_RX_5;
4152 break;
4153 case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
4154 idx = TX_CDC_DMA_TX_0;
4155 break;
4156 case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
4157 idx = TX_CDC_DMA_TX_3;
4158 break;
4159 case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
4160 idx = TX_CDC_DMA_TX_4;
4161 break;
4162 default:
4163 idx = RX_CDC_DMA_RX_0;
4164 break;
4165 }
4166
4167 return idx;
4168}
4169
4170static int msm_ext_disp_get_idx_from_beid(int32_t be_id)
4171{
4172 int idx = -EINVAL;
4173
4174 switch (be_id) {
4175 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
4176 idx = DP_RX_IDX;
4177 break;
4178 default:
4179 pr_err("%s: Incorrect ext_disp BE id %d\n", __func__, be_id);
4180 idx = -EINVAL;
4181 break;
4182 }
4183
4184 return idx;
4185}
4186
4187static int msm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
4188 struct snd_pcm_hw_params *params)
4189{
4190 struct snd_soc_dai_link *dai_link = rtd->dai_link;
4191 struct snd_interval *rate = hw_param_interval(params,
4192 SNDRV_PCM_HW_PARAM_RATE);
4193 struct snd_interval *channels = hw_param_interval(params,
4194 SNDRV_PCM_HW_PARAM_CHANNELS);
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4195 struct snd_soc_dai *codec_dai = rtd->codec_dai;
4196
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4197 int rc = 0;
4198 int idx;
4199 void *config = NULL;
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4200 struct snd_soc_component *component = NULL;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4201
4202 pr_debug("%s: format = %d, rate = %d\n",
4203 __func__, params_format(params), params_rate(params));
4204
4205 switch (dai_link->id) {
4206 case MSM_BACKEND_DAI_SLIMBUS_0_RX:
4207 case MSM_BACKEND_DAI_SLIMBUS_1_RX:
4208 case MSM_BACKEND_DAI_SLIMBUS_2_RX:
4209 case MSM_BACKEND_DAI_SLIMBUS_3_RX:
4210 case MSM_BACKEND_DAI_SLIMBUS_4_RX:
4211 case MSM_BACKEND_DAI_SLIMBUS_6_RX:
4212 idx = msm_slim_get_ch_from_beid(dai_link->id);
4213 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4214 slim_rx_cfg[idx].bit_format);
4215 rate->min = rate->max = slim_rx_cfg[idx].sample_rate;
4216 channels->min = channels->max = slim_rx_cfg[idx].channels;
4217 break;
4218
4219 case MSM_BACKEND_DAI_SLIMBUS_0_TX:
4220 case MSM_BACKEND_DAI_SLIMBUS_3_TX:
4221 idx = msm_slim_get_ch_from_beid(dai_link->id);
4222 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4223 slim_tx_cfg[idx].bit_format);
4224 rate->min = rate->max = slim_tx_cfg[idx].sample_rate;
4225 channels->min = channels->max = slim_tx_cfg[idx].channels;
4226 break;
4227
4228 case MSM_BACKEND_DAI_SLIMBUS_1_TX:
4229 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4230 slim_tx_cfg[1].bit_format);
4231 rate->min = rate->max = slim_tx_cfg[1].sample_rate;
4232 channels->min = channels->max = slim_tx_cfg[1].channels;
4233 break;
4234
4235 case MSM_BACKEND_DAI_SLIMBUS_4_TX:
4236 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4237 SNDRV_PCM_FORMAT_S32_LE);
4238 rate->min = rate->max = SAMPLING_RATE_8KHZ;
4239 channels->min = channels->max = msm_vi_feed_tx_ch;
4240 break;
4241
4242 case MSM_BACKEND_DAI_SLIMBUS_5_RX:
4243 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4244 slim_rx_cfg[5].bit_format);
4245 rate->min = rate->max = slim_rx_cfg[5].sample_rate;
4246 channels->min = channels->max = slim_rx_cfg[5].channels;
4247 break;
4248
4249 case MSM_BACKEND_DAI_SLIMBUS_5_TX:
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4250 component = snd_soc_rtdcom_lookup(rtd, "tavil_codec");
4251 if (!component) {
4252 pr_err("%s: component is NULL\n", __func__);
4253 rc = -EINVAL;
4254 goto done;
4255 }
4256
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4257 rate->min = rate->max = SAMPLING_RATE_16KHZ;
4258 channels->min = channels->max = 1;
4259
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4260 config = msm_codec_fn.get_afe_config_fn(component,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4261 AFE_SLIMBUS_SLAVE_PORT_CONFIG);
4262 if (config) {
4263 rc = afe_set_config(AFE_SLIMBUS_SLAVE_PORT_CONFIG,
4264 config, SLIMBUS_5_TX);
4265 if (rc)
4266 pr_err("%s: Failed to set slimbus slave port config %d\n",
4267 __func__, rc);
4268 }
4269 break;
4270
4271 case MSM_BACKEND_DAI_SLIMBUS_7_RX:
4272 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4273 slim_rx_cfg[SLIM_RX_7].bit_format);
4274 rate->min = rate->max = slim_rx_cfg[SLIM_RX_7].sample_rate;
4275 channels->min = channels->max =
4276 slim_rx_cfg[SLIM_RX_7].channels;
4277 break;
4278
4279 case MSM_BACKEND_DAI_SLIMBUS_7_TX:
4280 rate->min = rate->max = slim_tx_cfg[SLIM_TX_7].sample_rate;
4281 channels->min = channels->max =
4282 slim_tx_cfg[SLIM_TX_7].channels;
4283 break;
4284
4285 case MSM_BACKEND_DAI_SLIMBUS_8_TX:
4286 rate->min = rate->max = slim_tx_cfg[SLIM_TX_8].sample_rate;
4287 channels->min = channels->max =
4288 slim_tx_cfg[SLIM_TX_8].channels;
4289 break;
4290
4291 case MSM_BACKEND_DAI_USB_RX:
4292 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4293 usb_rx_cfg.bit_format);
4294 rate->min = rate->max = usb_rx_cfg.sample_rate;
4295 channels->min = channels->max = usb_rx_cfg.channels;
4296 break;
4297
4298 case MSM_BACKEND_DAI_USB_TX:
4299 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4300 usb_tx_cfg.bit_format);
4301 rate->min = rate->max = usb_tx_cfg.sample_rate;
4302 channels->min = channels->max = usb_tx_cfg.channels;
4303 break;
4304
4305 case MSM_BACKEND_DAI_DISPLAY_PORT_RX:
4306 idx = msm_ext_disp_get_idx_from_beid(dai_link->id);
4307 if (idx < 0) {
4308 pr_err("%s: Incorrect ext disp idx %d\n",
4309 __func__, idx);
4310 rc = idx;
4311 goto done;
4312 }
4313
4314 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4315 ext_disp_rx_cfg[idx].bit_format);
4316 rate->min = rate->max = ext_disp_rx_cfg[idx].sample_rate;
4317 channels->min = channels->max = ext_disp_rx_cfg[idx].channels;
4318 break;
4319
4320 case MSM_BACKEND_DAI_AFE_PCM_RX:
4321 channels->min = channels->max = proxy_rx_cfg.channels;
4322 rate->min = rate->max = SAMPLING_RATE_48KHZ;
4323 break;
4324
4325 case MSM_BACKEND_DAI_PRI_TDM_RX_0:
4326 channels->min = channels->max =
4327 tdm_rx_cfg[TDM_PRI][TDM_0].channels;
4328 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4329 tdm_rx_cfg[TDM_PRI][TDM_0].bit_format);
4330 rate->min = rate->max = tdm_rx_cfg[TDM_PRI][TDM_0].sample_rate;
4331 break;
4332
4333 case MSM_BACKEND_DAI_PRI_TDM_TX_0:
4334 channels->min = channels->max =
4335 tdm_tx_cfg[TDM_PRI][TDM_0].channels;
4336 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4337 tdm_tx_cfg[TDM_PRI][TDM_0].bit_format);
4338 rate->min = rate->max = tdm_tx_cfg[TDM_PRI][TDM_0].sample_rate;
4339 break;
4340
4341 case MSM_BACKEND_DAI_SEC_TDM_RX_0:
4342 channels->min = channels->max =
4343 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
4344 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4345 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
4346 rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
4347 break;
4348
4349 case MSM_BACKEND_DAI_SEC_TDM_TX_0:
4350 channels->min = channels->max =
4351 tdm_tx_cfg[TDM_SEC][TDM_0].channels;
4352 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4353 tdm_tx_cfg[TDM_SEC][TDM_0].bit_format);
4354 rate->min = rate->max = tdm_tx_cfg[TDM_SEC][TDM_0].sample_rate;
4355 break;
4356
4357 case MSM_BACKEND_DAI_TERT_TDM_RX_0:
4358 channels->min = channels->max =
4359 tdm_rx_cfg[TDM_TERT][TDM_0].channels;
4360 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4361 tdm_rx_cfg[TDM_TERT][TDM_0].bit_format);
4362 rate->min = rate->max = tdm_rx_cfg[TDM_TERT][TDM_0].sample_rate;
4363 break;
4364
4365 case MSM_BACKEND_DAI_TERT_TDM_TX_0:
4366 channels->min = channels->max =
4367 tdm_tx_cfg[TDM_TERT][TDM_0].channels;
4368 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4369 tdm_tx_cfg[TDM_TERT][TDM_0].bit_format);
4370 rate->min = rate->max = tdm_tx_cfg[TDM_TERT][TDM_0].sample_rate;
4371 break;
4372
4373 case MSM_BACKEND_DAI_QUAT_TDM_RX_0:
4374 channels->min = channels->max =
4375 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
4376 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4377 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
4378 rate->min = rate->max = tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
4379 break;
4380
4381 case MSM_BACKEND_DAI_QUAT_TDM_TX_0:
4382 channels->min = channels->max =
4383 tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
4384 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4385 tdm_tx_cfg[TDM_QUAT][TDM_0].bit_format);
4386 rate->min = rate->max = tdm_tx_cfg[TDM_QUAT][TDM_0].sample_rate;
4387 break;
4388
4389 case MSM_BACKEND_DAI_QUIN_TDM_RX_0:
4390 channels->min = channels->max =
4391 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
4392 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4393 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
4394 rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
4395 break;
4396
4397 case MSM_BACKEND_DAI_QUIN_TDM_TX_0:
4398 channels->min = channels->max =
4399 tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
4400 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4401 tdm_tx_cfg[TDM_QUIN][TDM_0].bit_format);
4402 rate->min = rate->max = tdm_tx_cfg[TDM_QUIN][TDM_0].sample_rate;
4403 break;
4404
4405
4406 case MSM_BACKEND_DAI_AUXPCM_RX:
4407 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4408 aux_pcm_rx_cfg[PRIM_AUX_PCM].bit_format);
4409 rate->min = rate->max =
4410 aux_pcm_rx_cfg[PRIM_AUX_PCM].sample_rate;
4411 channels->min = channels->max =
4412 aux_pcm_rx_cfg[PRIM_AUX_PCM].channels;
4413 break;
4414
4415 case MSM_BACKEND_DAI_AUXPCM_TX:
4416 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4417 aux_pcm_tx_cfg[PRIM_AUX_PCM].bit_format);
4418 rate->min = rate->max =
4419 aux_pcm_tx_cfg[PRIM_AUX_PCM].sample_rate;
4420 channels->min = channels->max =
4421 aux_pcm_tx_cfg[PRIM_AUX_PCM].channels;
4422 break;
4423
4424 case MSM_BACKEND_DAI_SEC_AUXPCM_RX:
4425 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4426 aux_pcm_rx_cfg[SEC_AUX_PCM].bit_format);
4427 rate->min = rate->max =
4428 aux_pcm_rx_cfg[SEC_AUX_PCM].sample_rate;
4429 channels->min = channels->max =
4430 aux_pcm_rx_cfg[SEC_AUX_PCM].channels;
4431 break;
4432
4433 case MSM_BACKEND_DAI_SEC_AUXPCM_TX:
4434 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4435 aux_pcm_tx_cfg[SEC_AUX_PCM].bit_format);
4436 rate->min = rate->max =
4437 aux_pcm_tx_cfg[SEC_AUX_PCM].sample_rate;
4438 channels->min = channels->max =
4439 aux_pcm_tx_cfg[SEC_AUX_PCM].channels;
4440 break;
4441
4442 case MSM_BACKEND_DAI_TERT_AUXPCM_RX:
4443 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4444 aux_pcm_rx_cfg[TERT_AUX_PCM].bit_format);
4445 rate->min = rate->max =
4446 aux_pcm_rx_cfg[TERT_AUX_PCM].sample_rate;
4447 channels->min = channels->max =
4448 aux_pcm_rx_cfg[TERT_AUX_PCM].channels;
4449 break;
4450
4451 case MSM_BACKEND_DAI_TERT_AUXPCM_TX:
4452 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4453 aux_pcm_tx_cfg[TERT_AUX_PCM].bit_format);
4454 rate->min = rate->max =
4455 aux_pcm_tx_cfg[TERT_AUX_PCM].sample_rate;
4456 channels->min = channels->max =
4457 aux_pcm_tx_cfg[TERT_AUX_PCM].channels;
4458 break;
4459
4460 case MSM_BACKEND_DAI_QUAT_AUXPCM_RX:
4461 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4462 aux_pcm_rx_cfg[QUAT_AUX_PCM].bit_format);
4463 rate->min = rate->max =
4464 aux_pcm_rx_cfg[QUAT_AUX_PCM].sample_rate;
4465 channels->min = channels->max =
4466 aux_pcm_rx_cfg[QUAT_AUX_PCM].channels;
4467 break;
4468
4469 case MSM_BACKEND_DAI_QUAT_AUXPCM_TX:
4470 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4471 aux_pcm_tx_cfg[QUAT_AUX_PCM].bit_format);
4472 rate->min = rate->max =
4473 aux_pcm_tx_cfg[QUAT_AUX_PCM].sample_rate;
4474 channels->min = channels->max =
4475 aux_pcm_tx_cfg[QUAT_AUX_PCM].channels;
4476 break;
4477
4478 case MSM_BACKEND_DAI_QUIN_AUXPCM_RX:
4479 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4480 aux_pcm_rx_cfg[QUIN_AUX_PCM].bit_format);
4481 rate->min = rate->max =
4482 aux_pcm_rx_cfg[QUIN_AUX_PCM].sample_rate;
4483 channels->min = channels->max =
4484 aux_pcm_rx_cfg[QUIN_AUX_PCM].channels;
4485 break;
4486
4487 case MSM_BACKEND_DAI_QUIN_AUXPCM_TX:
4488 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4489 aux_pcm_tx_cfg[QUIN_AUX_PCM].bit_format);
4490 rate->min = rate->max =
4491 aux_pcm_tx_cfg[QUIN_AUX_PCM].sample_rate;
4492 channels->min = channels->max =
4493 aux_pcm_tx_cfg[QUIN_AUX_PCM].channels;
4494 break;
4495
4496 case MSM_BACKEND_DAI_PRI_MI2S_RX:
4497 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4498 mi2s_rx_cfg[PRIM_MI2S].bit_format);
4499 rate->min = rate->max = mi2s_rx_cfg[PRIM_MI2S].sample_rate;
4500 channels->min = channels->max =
4501 mi2s_rx_cfg[PRIM_MI2S].channels;
4502 break;
4503
4504 case MSM_BACKEND_DAI_PRI_MI2S_TX:
4505 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4506 mi2s_tx_cfg[PRIM_MI2S].bit_format);
4507 rate->min = rate->max = mi2s_tx_cfg[PRIM_MI2S].sample_rate;
4508 channels->min = channels->max =
4509 mi2s_tx_cfg[PRIM_MI2S].channels;
4510 break;
4511
4512 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
4513 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4514 mi2s_rx_cfg[SEC_MI2S].bit_format);
4515 rate->min = rate->max = mi2s_rx_cfg[SEC_MI2S].sample_rate;
4516 channels->min = channels->max =
4517 mi2s_rx_cfg[SEC_MI2S].channels;
4518 break;
4519
4520 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
4521 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4522 mi2s_tx_cfg[SEC_MI2S].bit_format);
4523 rate->min = rate->max = mi2s_tx_cfg[SEC_MI2S].sample_rate;
4524 channels->min = channels->max =
4525 mi2s_tx_cfg[SEC_MI2S].channels;
4526 break;
4527
4528 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
4529 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4530 mi2s_rx_cfg[TERT_MI2S].bit_format);
4531 rate->min = rate->max = mi2s_rx_cfg[TERT_MI2S].sample_rate;
4532 channels->min = channels->max =
4533 mi2s_rx_cfg[TERT_MI2S].channels;
4534 break;
4535
4536 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
4537 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4538 mi2s_tx_cfg[TERT_MI2S].bit_format);
4539 rate->min = rate->max = mi2s_tx_cfg[TERT_MI2S].sample_rate;
4540 channels->min = channels->max =
4541 mi2s_tx_cfg[TERT_MI2S].channels;
4542 break;
4543
4544 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
4545 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4546 mi2s_rx_cfg[QUAT_MI2S].bit_format);
4547 rate->min = rate->max = mi2s_rx_cfg[QUAT_MI2S].sample_rate;
4548 channels->min = channels->max =
4549 mi2s_rx_cfg[QUAT_MI2S].channels;
4550 break;
4551
4552 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
4553 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4554 mi2s_tx_cfg[QUAT_MI2S].bit_format);
4555 rate->min = rate->max = mi2s_tx_cfg[QUAT_MI2S].sample_rate;
4556 channels->min = channels->max =
4557 mi2s_tx_cfg[QUAT_MI2S].channels;
4558 break;
4559
4560 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
4561 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4562 mi2s_rx_cfg[QUIN_MI2S].bit_format);
4563 rate->min = rate->max = mi2s_rx_cfg[QUIN_MI2S].sample_rate;
4564 channels->min = channels->max =
4565 mi2s_rx_cfg[QUIN_MI2S].channels;
4566 break;
4567
4568 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
4569 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4570 mi2s_tx_cfg[QUIN_MI2S].bit_format);
4571 rate->min = rate->max = mi2s_tx_cfg[QUIN_MI2S].sample_rate;
4572 channels->min = channels->max =
4573 mi2s_tx_cfg[QUIN_MI2S].channels;
4574 break;
4575
4576 case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
4577 case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
4578 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
4579 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
4580 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
4581 idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
4582 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4583 cdc_dma_rx_cfg[idx].bit_format);
4584 rate->min = rate->max = cdc_dma_rx_cfg[idx].sample_rate;
4585 channels->min = channels->max = cdc_dma_rx_cfg[idx].channels;
4586 break;
4587
4588 case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
4589 case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
4590 case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]4591 case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
4592 case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4593 idx = msm_cdc_dma_get_idx_from_beid(dai_link->id);
4594 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4595 cdc_dma_tx_cfg[idx].bit_format);
4596 rate->min = rate->max = cdc_dma_tx_cfg[idx].sample_rate;
4597 channels->min = channels->max = cdc_dma_tx_cfg[idx].channels;
4598 break;
4599
4600 case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
4601 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
4602 SNDRV_PCM_FORMAT_S32_LE);
4603 rate->min = rate->max = SAMPLING_RATE_8KHZ;
4604 channels->min = channels->max = msm_vi_feed_tx_ch;
4605 break;
4606
4607 default:
4608 rate->min = rate->max = SAMPLING_RATE_48KHZ;
4609 break;
4610 }
4611
4612done:
4613 return rc;
4614}
4615
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4616static bool msm_usbc_swap_gnd_mic(struct snd_soc_component *component,
4617 bool active)
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4618{
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4619 struct snd_soc_card *card = component->card;
Vatsal Bucha6cb17a02018-08-07 11:07:04 +0530[diff] [blame]4620 struct msm_asoc_mach_data *pdata =
4621 snd_soc_card_get_drvdata(card);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4622
Vatsal Bucha6cb17a02018-08-07 11:07:04 +0530[diff] [blame]4623 if (!pdata->fsa_handle)
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4624 return false;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4625
Vatsal Bucha6cb17a02018-08-07 11:07:04 +0530[diff] [blame]4626 return fsa4480_switch_event(pdata->fsa_handle, FSA_MIC_GND_SWAP);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4627}
4628
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4629static bool msm_swap_gnd_mic(struct snd_soc_component *component, bool active)
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4630{
4631 int value = 0;
4632 bool ret = false;
4633 struct snd_soc_card *card;
4634 struct msm_asoc_mach_data *pdata;
4635
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4636 if (!component) {
4637 pr_err("%s component is NULL\n", __func__);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4638 return false;
4639 }
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4640 card = component->card;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4641 pdata = snd_soc_card_get_drvdata(card);
4642
4643 if (!pdata)
4644 return false;
4645
4646 if (wcd_mbhc_cfg.enable_usbc_analog)
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4647 return msm_usbc_swap_gnd_mic(component, active);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4648
4649 /* if usbc is not defined, swap using us_euro_gpio_p */
4650 if (pdata->us_euro_gpio_p) {
4651 value = msm_cdc_pinctrl_get_state(
4652 pdata->us_euro_gpio_p);
4653 if (value)
4654 msm_cdc_pinctrl_select_sleep_state(
4655 pdata->us_euro_gpio_p);
4656 else
4657 msm_cdc_pinctrl_select_active_state(
4658 pdata->us_euro_gpio_p);
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4659 dev_dbg(component->dev, "%s: swap select switch %d to %d\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4660 __func__, value, !value);
4661 ret = true;
4662 }
4663 return ret;
4664}
4665
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4666static int msm_afe_set_config(struct snd_soc_component *component)
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4667{
4668 int ret = 0;
4669 void *config_data = NULL;
4670
4671 if (!msm_codec_fn.get_afe_config_fn) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4672 dev_err(component->dev, "%s: codec get afe config not init'ed\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4673 __func__);
4674 return -EINVAL;
4675 }
4676
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4677 config_data = msm_codec_fn.get_afe_config_fn(component,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4678 AFE_CDC_REGISTERS_CONFIG);
4679 if (config_data) {
4680 ret = afe_set_config(AFE_CDC_REGISTERS_CONFIG, config_data, 0);
4681 if (ret) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4682 dev_err(component->dev,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4683 "%s: Failed to set codec registers config %d\n",
4684 __func__, ret);
4685 return ret;
4686 }
4687 }
4688
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4689 config_data = msm_codec_fn.get_afe_config_fn(component,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4690 AFE_CDC_REGISTER_PAGE_CONFIG);
4691 if (config_data) {
4692 ret = afe_set_config(AFE_CDC_REGISTER_PAGE_CONFIG, config_data,
4693 0);
4694 if (ret)
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4695 dev_err(component->dev,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4696 "%s: Failed to set cdc register page config\n",
4697 __func__);
4698 }
4699
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4700 config_data = msm_codec_fn.get_afe_config_fn(component,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4701 AFE_SLIMBUS_SLAVE_CONFIG);
4702 if (config_data) {
4703 ret = afe_set_config(AFE_SLIMBUS_SLAVE_CONFIG, config_data, 0);
4704 if (ret) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4705 dev_err(component->dev,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4706 "%s: Failed to set slimbus slave config %d\n",
4707 __func__, ret);
4708 return ret;
4709 }
4710 }
4711
4712 return 0;
4713}
4714
4715static void msm_afe_clear_config(void)
4716{
4717 afe_clear_config(AFE_CDC_REGISTERS_CONFIG);
4718 afe_clear_config(AFE_SLIMBUS_SLAVE_CONFIG);
4719}
4720
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4721static int msm_audrx_tavil_init(struct snd_soc_pcm_runtime *rtd)
4722{
4723 int ret = 0;
4724 void *config_data;
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4725 struct snd_soc_component *component = NULL;
4726 struct snd_soc_dapm_context *dapm;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4727 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
4728 struct snd_soc_dai *codec_dai = rtd->codec_dai;
4729 struct snd_soc_component *aux_comp;
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4730 struct snd_card *card = rtd->card->snd_card;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4731 struct snd_info_entry *entry;
4732 struct msm_asoc_mach_data *pdata =
4733 snd_soc_card_get_drvdata(rtd->card);
4734
4735 /*
4736 * Codec SLIMBUS configuration
4737 * RX1, RX2, RX3, RX4, RX5, RX6, RX7, RX8
4738 * TX1, TX2, TX3, TX4, TX5, TX6, TX7, TX8, TX9, TX10, TX11, TX12, TX13
4739 * TX14, TX15, TX16
4740 */
4741 unsigned int rx_ch[WCD934X_RX_MAX] = {144, 145, 146, 147, 148, 149,
4742 150, 151};
4743 unsigned int tx_ch[WCD934X_TX_MAX] = {128, 129, 130, 131, 132, 133,
4744 134, 135, 136, 137, 138, 139,
4745 140, 141, 142, 143};
4746
4747 pr_info("%s: dev_name:%s\n", __func__, dev_name(cpu_dai->dev));
4748
4749 rtd->pmdown_time = 0;
4750
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4751 component = snd_soc_rtdcom_lookup(rtd, "tavil_codec");
4752 if (!component) {
4753 pr_err("%s: component is NULL\n", __func__);
4754 return -EINVAL;
4755 }
4756 dapm = snd_soc_component_get_dapm(component);
4757
4758 ret = snd_soc_add_component_controls(component, msm_tavil_snd_controls,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4759 ARRAY_SIZE(msm_tavil_snd_controls));
4760 if (ret < 0) {
4761 pr_err("%s: add_codec_controls failed, err %d\n",
4762 __func__, ret);
4763 return ret;
4764 }
4765
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4766 ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4767 ARRAY_SIZE(msm_common_snd_controls));
4768 if (ret < 0) {
4769 pr_err("%s: add_codec_controls failed, err %d\n",
4770 __func__, ret);
4771 return ret;
4772 }
4773
4774 snd_soc_dapm_new_controls(dapm, msm_dapm_widgets_tavil,
4775 ARRAY_SIZE(msm_dapm_widgets_tavil));
4776
4777 snd_soc_dapm_add_routes(dapm, wcd_audio_paths_tavil,
4778 ARRAY_SIZE(wcd_audio_paths_tavil));
4779
4780 snd_soc_dapm_ignore_suspend(dapm, "Handset Mic");
4781 snd_soc_dapm_ignore_suspend(dapm, "Headset Mic");
4782 snd_soc_dapm_ignore_suspend(dapm, "ANCRight Headset Mic");
4783 snd_soc_dapm_ignore_suspend(dapm, "ANCLeft Headset Mic");
4784 snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
4785 snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
4786 snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
4787 snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
4788 snd_soc_dapm_ignore_suspend(dapm, "Digital Mic4");
4789 snd_soc_dapm_ignore_suspend(dapm, "Digital Mic5");
4790 snd_soc_dapm_ignore_suspend(dapm, "Analog Mic5");
4791 snd_soc_dapm_ignore_suspend(dapm, "MADINPUT");
4792 snd_soc_dapm_ignore_suspend(dapm, "MAD_CPE_INPUT");
4793 snd_soc_dapm_ignore_suspend(dapm, "MAD_CPE_OUT1");
4794 snd_soc_dapm_ignore_suspend(dapm, "MAD_CPE_OUT2");
4795 snd_soc_dapm_ignore_suspend(dapm, "EAR");
4796 snd_soc_dapm_ignore_suspend(dapm, "LINEOUT1");
4797 snd_soc_dapm_ignore_suspend(dapm, "LINEOUT2");
4798 snd_soc_dapm_ignore_suspend(dapm, "ANC EAR");
4799 snd_soc_dapm_ignore_suspend(dapm, "SPK1 OUT");
4800 snd_soc_dapm_ignore_suspend(dapm, "SPK2 OUT");
4801 snd_soc_dapm_ignore_suspend(dapm, "HPHL");
4802 snd_soc_dapm_ignore_suspend(dapm, "HPHR");
4803 snd_soc_dapm_ignore_suspend(dapm, "AIF4 VI");
4804 snd_soc_dapm_ignore_suspend(dapm, "VIINPUT");
4805 snd_soc_dapm_ignore_suspend(dapm, "ANC HPHL");
4806 snd_soc_dapm_ignore_suspend(dapm, "ANC HPHR");
4807
4808 snd_soc_dapm_sync(dapm);
4809
4810 snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
4811 tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
4812
4813 msm_codec_fn.get_afe_config_fn = tavil_get_afe_config;
4814
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4815 ret = msm_afe_set_config(component);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4816 if (ret) {
4817 pr_err("%s: Failed to set AFE config %d\n", __func__, ret);
4818 goto err;
4819 }
Vaishnavi Kommaraju9a3d5eb2018-09-19 18:16:39 +0530[diff] [blame]4820 pdata->is_afe_config_done = true;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4821
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4822 config_data = msm_codec_fn.get_afe_config_fn(component,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4823 AFE_AANC_VERSION);
4824 if (config_data) {
4825 ret = afe_set_config(AFE_AANC_VERSION, config_data, 0);
4826 if (ret) {
4827 pr_err("%s: Failed to set aanc version %d\n",
4828 __func__, ret);
4829 goto err;
4830 }
4831 }
4832
4833 /*
4834 * Send speaker configuration only for WSA8810.
4835 * Default configuration is for WSA8815.
4836 */
4837 pr_debug("%s: Number of aux devices: %d\n",
4838 __func__, rtd->card->num_aux_devs);
4839 if (rtd->card->num_aux_devs &&
4840 !list_empty(&rtd->card->aux_comp_list)) {
4841 aux_comp = list_first_entry(&rtd->card->aux_comp_list,
4842 struct snd_soc_component, card_aux_list);
4843 if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
4844 !strcmp(aux_comp->name, WSA8810_NAME_2)) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4845 tavil_set_spkr_mode(component, WCD934X_SPKR_MODE_1);
4846 tavil_set_spkr_gain_offset(component,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4847 WCD934X_RX_GAIN_OFFSET_M1P5_DB);
4848 }
4849 }
4850
4851 card = rtd->card->snd_card;
4852 entry = snd_info_create_subdir(card->module, "codecs",
4853 card->proc_root);
4854 if (!entry) {
4855 pr_debug("%s: Cannot create codecs module entry\n",
4856 __func__);
4857 ret = 0;
4858 goto err;
4859 }
4860 pdata->codec_root = entry;
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4861 tavil_codec_info_create_codec_entry(pdata->codec_root, component);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4862
4863 codec_reg_done = true;
4864 return 0;
4865err:
4866 return ret;
4867}
4868
4869static int msm_int_audrx_init(struct snd_soc_pcm_runtime *rtd)
4870{
4871 int ret = 0;
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4872 struct snd_soc_component *component;
4873 struct snd_soc_dapm_context *dapm;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4874 struct snd_card *card;
4875 struct snd_info_entry *entry;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]4876 struct snd_soc_component *aux_comp;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4877 struct msm_asoc_mach_data *pdata =
4878 snd_soc_card_get_drvdata(rtd->card);
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4879 struct snd_soc_dai *codec_dai = rtd->codec_dai;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4880
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4881 component = snd_soc_rtdcom_lookup(rtd, "bolero_codec");
4882 if (!component) {
4883 pr_err("%s: component is NULL\n", __func__);
4884 return -EINVAL;
4885 }
4886 dapm = snd_soc_component_get_dapm(component);
4887
4888 ret = snd_soc_add_component_controls(component, msm_int_snd_controls,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4889 ARRAY_SIZE(msm_int_snd_controls));
4890 if (ret < 0) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4891 pr_err("%s: add_component_controls failed: %d\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4892 __func__, ret);
4893 return ret;
4894 }
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4895 ret = snd_soc_add_component_controls(component, msm_common_snd_controls,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4896 ARRAY_SIZE(msm_common_snd_controls));
4897 if (ret < 0) {
4898 pr_err("%s: add common snd controls failed: %d\n",
4899 __func__, ret);
4900 return ret;
4901 }
4902
4903 snd_soc_dapm_new_controls(dapm, msm_int_dapm_widgets,
4904 ARRAY_SIZE(msm_int_dapm_widgets));
4905
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]4906 snd_soc_dapm_ignore_suspend(dapm, "Digital Mic0");
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4907 snd_soc_dapm_ignore_suspend(dapm, "Digital Mic1");
4908 snd_soc_dapm_ignore_suspend(dapm, "Digital Mic2");
4909 snd_soc_dapm_ignore_suspend(dapm, "Digital Mic3");
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4910
4911 snd_soc_dapm_ignore_suspend(dapm, "Analog Mic1");
4912 snd_soc_dapm_ignore_suspend(dapm, "Analog Mic2");
4913 snd_soc_dapm_ignore_suspend(dapm, "Analog Mic3");
4914 snd_soc_dapm_ignore_suspend(dapm, "Analog Mic4");
4915
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]4916 snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK1 OUT");
4917 snd_soc_dapm_ignore_suspend(dapm, "WSA_SPK2 OUT");
4918 snd_soc_dapm_ignore_suspend(dapm, "WSA AIF VI");
4919 snd_soc_dapm_ignore_suspend(dapm, "VIINPUT_WSA");
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4920
4921 snd_soc_dapm_sync(dapm);
4922
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]4923 /*
4924 * Send speaker configuration only for WSA8810.
4925 * Default configuration is for WSA8815.
4926 */
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4927 dev_dbg(component->dev, "%s: Number of aux devices: %d\n",
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]4928 __func__, rtd->card->num_aux_devs);
4929 if (rtd->card->num_aux_devs &&
4930 !list_empty(&rtd->card->component_dev_list)) {
4931 aux_comp = list_first_entry(
4932 &rtd->card->component_dev_list,
4933 struct snd_soc_component,
4934 card_aux_list);
4935 if (!strcmp(aux_comp->name, WSA8810_NAME_1) ||
4936 !strcmp(aux_comp->name, WSA8810_NAME_2)) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4937 wsa_macro_set_spkr_mode(component,
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]4938 WSA_MACRO_SPKR_MODE_1);
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4939 wsa_macro_set_spkr_gain_offset(component,
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]4940 WSA_MACRO_GAIN_OFFSET_M1P5_DB);
4941 }
4942 }
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4943 card = rtd->card->snd_card;
Aditya Bavanari4ae32fc2018-08-13 13:08:34 +0530[diff] [blame]4944 if (!pdata->codec_root) {
4945 entry = snd_info_create_subdir(card->module, "codecs",
4946 card->proc_root);
4947 if (!entry) {
4948 pr_debug("%s: Cannot create codecs module entry\n",
4949 __func__);
4950 ret = 0;
4951 goto err;
4952 }
4953 pdata->codec_root = entry;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4954 }
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4955 bolero_info_create_codec_entry(pdata->codec_root, codec);
Aditya Bavanari3e19f3c2018-11-12 19:29:50 +0530[diff] [blame]4956 /*
4957 * SM6150 MSM 1.0 doesn't have hardware wake up interrupt line
4958 * from AOSS to APSS. So, it uses SW workaround and listens to
4959 * interrupt from AFE over IPC.
4960 * Check for MSM version and MSM ID and register wake irq
4961 * accordingly to provide compatibility to all chipsets.
4962 */
4963 if (socinfo_get_id() == SM6150_SOC_MSM_ID &&
4964 socinfo_get_version() == SM6150_SOC_VERSION_1_0)
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4965 bolero_register_wake_irq(component, true);
Aditya Bavanari3e19f3c2018-11-12 19:29:50 +0530[diff] [blame]4966 else
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]4967 bolero_register_wake_irq(component, false);
Aditya Bavanari3e19f3c2018-11-12 19:29:50 +0530[diff] [blame]4968
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]4969 codec_reg_done = true;
4970 return 0;
4971err:
4972 return ret;
4973}
4974
4975static int msm_wcn_init(struct snd_soc_pcm_runtime *rtd)
4976{
4977 unsigned int rx_ch[WCN_CDC_SLIM_RX_CH_MAX] = {157, 158};
4978 unsigned int tx_ch[WCN_CDC_SLIM_TX_CH_MAX] = {159, 160, 161};
4979 struct snd_soc_dai *codec_dai = rtd->codec_dai;
4980
4981 return snd_soc_dai_set_channel_map(codec_dai, ARRAY_SIZE(tx_ch),
4982 tx_ch, ARRAY_SIZE(rx_ch), rx_ch);
4983}
4984
4985static void *def_wcd_mbhc_cal(void)
4986{
4987 void *wcd_mbhc_cal;
4988 struct wcd_mbhc_btn_detect_cfg *btn_cfg;
4989 u16 *btn_high;
4990
4991 wcd_mbhc_cal = kzalloc(WCD_MBHC_CAL_SIZE(WCD_MBHC_DEF_BUTTONS,
4992 WCD9XXX_MBHC_DEF_RLOADS), GFP_KERNEL);
4993 if (!wcd_mbhc_cal)
4994 return NULL;
4995
4996#define S(X, Y) ((WCD_MBHC_CAL_PLUG_TYPE_PTR(wcd_mbhc_cal)->X) = (Y))
4997 S(v_hs_max, 1600);
4998#undef S
4999#define S(X, Y) ((WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal)->X) = (Y))
5000 S(num_btn, WCD_MBHC_DEF_BUTTONS);
5001#undef S
5002
5003 btn_cfg = WCD_MBHC_CAL_BTN_DET_PTR(wcd_mbhc_cal);
5004 btn_high = ((void *)&btn_cfg->_v_btn_low) +
5005 (sizeof(btn_cfg->_v_btn_low[0]) * btn_cfg->num_btn);
5006
5007 btn_high[0] = 75;
5008 btn_high[1] = 150;
5009 btn_high[2] = 237;
5010 btn_high[3] = 500;
5011 btn_high[4] = 500;
5012 btn_high[5] = 500;
5013 btn_high[6] = 500;
5014 btn_high[7] = 500;
5015
5016 return wcd_mbhc_cal;
5017}
5018
5019static int msm_snd_hw_params(struct snd_pcm_substream *substream,
5020 struct snd_pcm_hw_params *params)
5021{
5022 struct snd_soc_pcm_runtime *rtd = substream->private_data;
5023 struct snd_soc_dai *codec_dai = rtd->codec_dai;
5024 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
5025 struct snd_soc_dai_link *dai_link = rtd->dai_link;
5026
5027 int ret = 0;
5028 u32 rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
5029 u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
5030 u32 user_set_tx_ch = 0;
5031 u32 rx_ch_count;
5032
5033 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5034 ret = snd_soc_dai_get_channel_map(codec_dai,
5035 &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
5036 if (ret < 0) {
5037 pr_err("%s: failed to get codec chan map, err:%d\n",
5038 __func__, ret);
5039 goto err;
5040 }
5041 if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_5_RX) {
5042 pr_debug("%s: rx_5_ch=%d\n", __func__,
5043 slim_rx_cfg[5].channels);
5044 rx_ch_count = slim_rx_cfg[5].channels;
5045 } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_2_RX) {
5046 pr_debug("%s: rx_2_ch=%d\n", __func__,
5047 slim_rx_cfg[2].channels);
5048 rx_ch_count = slim_rx_cfg[2].channels;
5049 } else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_6_RX) {
5050 pr_debug("%s: rx_6_ch=%d\n", __func__,
5051 slim_rx_cfg[6].channels);
5052 rx_ch_count = slim_rx_cfg[6].channels;
5053 } else {
5054 pr_debug("%s: rx_0_ch=%d\n", __func__,
5055 slim_rx_cfg[0].channels);
5056 rx_ch_count = slim_rx_cfg[0].channels;
5057 }
5058 ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
5059 rx_ch_count, rx_ch);
5060 if (ret < 0) {
5061 pr_err("%s: failed to set cpu chan map, err:%d\n",
5062 __func__, ret);
5063 goto err;
5064 }
5065 } else {
5066
5067 pr_debug("%s: %s_tx_dai_id_%d_ch=%d\n", __func__,
5068 codec_dai->name, codec_dai->id, user_set_tx_ch);
5069 ret = snd_soc_dai_get_channel_map(codec_dai,
5070 &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
5071 if (ret < 0) {
5072 pr_err("%s: failed to get tx codec chan map, err:%d\n",
5073 __func__, ret);
5074 goto err;
5075 }
5076 /* For <codec>_tx1 case */
5077 if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_0_TX)
5078 user_set_tx_ch = slim_tx_cfg[0].channels;
5079 /* For <codec>_tx3 case */
5080 else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_1_TX)
5081 user_set_tx_ch = slim_tx_cfg[1].channels;
5082 else if (dai_link->id == MSM_BACKEND_DAI_SLIMBUS_4_TX)
5083 user_set_tx_ch = msm_vi_feed_tx_ch;
5084 else
5085 user_set_tx_ch = tx_ch_cnt;
5086
5087 pr_debug("%s: msm_slim_0_tx_ch(%d) user_set_tx_ch(%d) tx_ch_cnt(%d), BE id (%d)\n",
5088 __func__, slim_tx_cfg[0].channels, user_set_tx_ch,
5089 tx_ch_cnt, dai_link->id);
5090
5091 ret = snd_soc_dai_set_channel_map(cpu_dai,
5092 user_set_tx_ch, tx_ch, 0, 0);
5093 if (ret < 0)
5094 pr_err("%s: failed to set tx cpu chan map, err:%d\n",
5095 __func__, ret);
5096 }
5097
5098err:
5099 return ret;
5100}
5101
5102
5103static int msm_snd_cdc_dma_hw_params(struct snd_pcm_substream *substream,
5104 struct snd_pcm_hw_params *params)
5105{
5106 struct snd_soc_pcm_runtime *rtd = substream->private_data;
5107 struct snd_soc_dai *codec_dai = rtd->codec_dai;
5108 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
5109 struct snd_soc_dai_link *dai_link = rtd->dai_link;
5110
5111 int ret = 0;
5112 u32 rx_ch_cdc_dma, tx_ch_cdc_dma;
5113 u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
5114 u32 user_set_tx_ch = 0;
5115 u32 user_set_rx_ch = 0;
5116 u32 ch_id;
5117
5118 ret = snd_soc_dai_get_channel_map(codec_dai,
5119 &tx_ch_cnt, &tx_ch_cdc_dma, &rx_ch_cnt,
5120 &rx_ch_cdc_dma);
5121 if (ret < 0) {
5122 pr_err("%s: failed to get codec chan map, err:%d\n",
5123 __func__, ret);
5124 goto err;
5125 }
5126
5127 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5128 switch (dai_link->id) {
5129 case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0:
5130 case MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1:
5131 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_0:
5132 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_1:
5133 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_2:
5134 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_3:
5135 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_4:
5136 case MSM_BACKEND_DAI_RX_CDC_DMA_RX_5:
5137 {
5138 ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
5139 pr_debug("%s: id %d rx_ch=%d\n", __func__,
5140 ch_id, cdc_dma_rx_cfg[ch_id].channels);
5141 user_set_rx_ch = cdc_dma_rx_cfg[ch_id].channels;
5142 ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
5143 user_set_rx_ch, &rx_ch_cdc_dma);
5144 if (ret < 0) {
5145 pr_err("%s: failed to set cpu chan map, err:%d\n",
5146 __func__, ret);
5147 goto err;
5148 }
5149
5150 }
5151 break;
5152 }
5153 } else {
5154 switch (dai_link->id) {
5155 case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0:
5156 {
5157 user_set_tx_ch = msm_vi_feed_tx_ch;
5158 }
5159 break;
5160 case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1:
5161 case MSM_BACKEND_DAI_WSA_CDC_DMA_TX_2:
5162 case MSM_BACKEND_DAI_TX_CDC_DMA_TX_0:
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]5163 case MSM_BACKEND_DAI_TX_CDC_DMA_TX_3:
5164 case MSM_BACKEND_DAI_TX_CDC_DMA_TX_4:
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]5165 {
5166 ch_id = msm_cdc_dma_get_idx_from_beid(dai_link->id);
5167 pr_debug("%s: id %d tx_ch=%d\n", __func__,
5168 ch_id, cdc_dma_tx_cfg[ch_id].channels);
5169 user_set_tx_ch = cdc_dma_tx_cfg[ch_id].channels;
5170 }
5171 break;
5172 }
5173
5174 ret = snd_soc_dai_set_channel_map(cpu_dai, user_set_tx_ch,
5175 &tx_ch_cdc_dma, 0, 0);
5176 if (ret < 0) {
5177 pr_err("%s: failed to set cpu chan map, err:%d\n",
5178 __func__, ret);
5179 goto err;
5180 }
5181 }
5182
5183err:
5184 return ret;
5185}
5186
5187static int msm_slimbus_2_hw_params(struct snd_pcm_substream *substream,
5188 struct snd_pcm_hw_params *params)
5189{
5190 struct snd_soc_pcm_runtime *rtd = substream->private_data;
5191 struct snd_soc_dai *codec_dai = rtd->codec_dai;
5192 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
5193 unsigned int rx_ch[SLIM_MAX_RX_PORTS], tx_ch[SLIM_MAX_TX_PORTS];
5194 unsigned int rx_ch_cnt = 0, tx_ch_cnt = 0;
5195 unsigned int num_tx_ch = 0;
5196 unsigned int num_rx_ch = 0;
5197 int ret = 0;
5198
5199 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5200 num_rx_ch = params_channels(params);
5201 pr_debug("%s: %s rx_dai_id = %d num_ch = %d\n", __func__,
5202 codec_dai->name, codec_dai->id, num_rx_ch);
5203 ret = snd_soc_dai_get_channel_map(codec_dai,
5204 &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
5205 if (ret < 0) {
5206 pr_err("%s: failed to get codec chan map, err:%d\n",
5207 __func__, ret);
5208 goto err;
5209 }
5210 ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
5211 num_rx_ch, rx_ch);
5212 if (ret < 0) {
5213 pr_err("%s: failed to set cpu chan map, err:%d\n",
5214 __func__, ret);
5215 goto err;
5216 }
5217 } else {
5218 num_tx_ch = params_channels(params);
5219 pr_debug("%s: %s tx_dai_id = %d num_ch = %d\n", __func__,
5220 codec_dai->name, codec_dai->id, num_tx_ch);
5221 ret = snd_soc_dai_get_channel_map(codec_dai,
5222 &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
5223 if (ret < 0) {
5224 pr_err("%s: failed to get tx codec chan map, err:%d\n",
5225 __func__, ret);
5226 goto err;
5227 }
5228 ret = snd_soc_dai_set_channel_map(cpu_dai,
5229 num_tx_ch, tx_ch, 0, 0);
5230 if (ret < 0) {
5231 pr_err("%s: failed to set tx cpu chan map, err:%d\n",
5232 __func__, ret);
5233 goto err;
5234 }
5235 }
5236
5237err:
5238 return ret;
5239}
5240
5241static int msm_wcn_hw_params(struct snd_pcm_substream *substream,
5242 struct snd_pcm_hw_params *params)
5243{
5244 struct snd_soc_pcm_runtime *rtd = substream->private_data;
5245 struct snd_soc_dai *codec_dai = rtd->codec_dai;
5246 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
5247 struct snd_soc_dai_link *dai_link = rtd->dai_link;
5248 u32 rx_ch[WCN_CDC_SLIM_RX_CH_MAX], tx_ch[WCN_CDC_SLIM_TX_CH_MAX];
5249 u32 rx_ch_cnt = 0, tx_ch_cnt = 0;
5250 int ret;
5251
5252 dev_dbg(rtd->dev, "%s: %s_tx_dai_id_%d\n", __func__,
5253 codec_dai->name, codec_dai->id);
5254 ret = snd_soc_dai_get_channel_map(codec_dai,
5255 &tx_ch_cnt, tx_ch, &rx_ch_cnt, rx_ch);
5256 if (ret) {
5257 dev_err(rtd->dev,
5258 "%s: failed to get BTFM codec chan map\n, err:%d\n",
5259 __func__, ret);
5260 goto err;
5261 }
5262
5263 dev_dbg(rtd->dev, "%s: tx_ch_cnt(%d) BE id %d\n",
5264 __func__, tx_ch_cnt, dai_link->id);
5265
5266 ret = snd_soc_dai_set_channel_map(cpu_dai,
5267 tx_ch_cnt, tx_ch, rx_ch_cnt, rx_ch);
5268 if (ret)
5269 dev_err(rtd->dev, "%s: failed to set cpu chan map, err:%d\n",
5270 __func__, ret);
5271
5272err:
5273 return ret;
5274}
5275
5276static int msm_get_port_id(int be_id)
5277{
5278 int afe_port_id;
5279
5280 switch (be_id) {
5281 case MSM_BACKEND_DAI_PRI_MI2S_RX:
5282 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_RX;
5283 break;
5284 case MSM_BACKEND_DAI_PRI_MI2S_TX:
5285 afe_port_id = AFE_PORT_ID_PRIMARY_MI2S_TX;
5286 break;
5287 case MSM_BACKEND_DAI_SECONDARY_MI2S_RX:
5288 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_RX;
5289 break;
5290 case MSM_BACKEND_DAI_SECONDARY_MI2S_TX:
5291 afe_port_id = AFE_PORT_ID_SECONDARY_MI2S_TX;
5292 break;
5293 case MSM_BACKEND_DAI_TERTIARY_MI2S_RX:
5294 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_RX;
5295 break;
5296 case MSM_BACKEND_DAI_TERTIARY_MI2S_TX:
5297 afe_port_id = AFE_PORT_ID_TERTIARY_MI2S_TX;
5298 break;
5299 case MSM_BACKEND_DAI_QUATERNARY_MI2S_RX:
5300 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_RX;
5301 break;
5302 case MSM_BACKEND_DAI_QUATERNARY_MI2S_TX:
5303 afe_port_id = AFE_PORT_ID_QUATERNARY_MI2S_TX;
5304 break;
5305 case MSM_BACKEND_DAI_QUINARY_MI2S_RX:
5306 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_RX;
5307 break;
5308 case MSM_BACKEND_DAI_QUINARY_MI2S_TX:
5309 afe_port_id = AFE_PORT_ID_QUINARY_MI2S_TX;
5310 break;
5311 default:
5312 pr_err("%s: Invalid BE id: %d\n", __func__, be_id);
5313 afe_port_id = -EINVAL;
5314 }
5315
5316 return afe_port_id;
5317}
5318
5319static u32 get_mi2s_bits_per_sample(u32 bit_format)
5320{
5321 u32 bit_per_sample;
5322
5323 switch (bit_format) {
5324 case SNDRV_PCM_FORMAT_S32_LE:
5325 case SNDRV_PCM_FORMAT_S24_3LE:
5326 case SNDRV_PCM_FORMAT_S24_LE:
5327 bit_per_sample = 32;
5328 break;
5329 case SNDRV_PCM_FORMAT_S16_LE:
5330 default:
5331 bit_per_sample = 16;
5332 break;
5333 }
5334
5335 return bit_per_sample;
5336}
5337
5338static void update_mi2s_clk_val(int dai_id, int stream)
5339{
5340 u32 bit_per_sample;
5341
5342 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
5343 bit_per_sample =
5344 get_mi2s_bits_per_sample(mi2s_rx_cfg[dai_id].bit_format);
5345 mi2s_clk[dai_id].clk_freq_in_hz =
5346 mi2s_rx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
5347 } else {
5348 bit_per_sample =
5349 get_mi2s_bits_per_sample(mi2s_tx_cfg[dai_id].bit_format);
5350 mi2s_clk[dai_id].clk_freq_in_hz =
5351 mi2s_tx_cfg[dai_id].sample_rate * 2 * bit_per_sample;
5352 }
5353}
5354
5355static int msm_mi2s_set_sclk(struct snd_pcm_substream *substream, bool enable)
5356{
5357 int ret = 0;
5358 struct snd_soc_pcm_runtime *rtd = substream->private_data;
5359 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
5360 int port_id = 0;
5361 int index = cpu_dai->id;
5362
5363 port_id = msm_get_port_id(rtd->dai_link->id);
5364 if (port_id < 0) {
5365 dev_err(rtd->card->dev, "%s: Invalid port_id\n", __func__);
5366 ret = port_id;
5367 goto err;
5368 }
5369
5370 if (enable) {
5371 update_mi2s_clk_val(index, substream->stream);
5372 dev_dbg(rtd->card->dev, "%s: clock rate %ul\n", __func__,
5373 mi2s_clk[index].clk_freq_in_hz);
5374 }
5375
5376 mi2s_clk[index].enable = enable;
5377 ret = afe_set_lpass_clock_v2(port_id,
5378 &mi2s_clk[index]);
5379 if (ret < 0) {
5380 dev_err(rtd->card->dev,
5381 "%s: afe lpass clock failed for port 0x%x , err:%d\n",
5382 __func__, port_id, ret);
5383 goto err;
5384 }
5385
5386err:
5387 return ret;
5388}
5389
5390static int msm_set_pinctrl(struct msm_pinctrl_info *pinctrl_info,
5391 enum pinctrl_pin_state new_state)
5392{
5393 int ret = 0;
5394 int curr_state = 0;
5395
5396 if (pinctrl_info == NULL) {
5397 pr_err("%s: pinctrl_info is NULL\n", __func__);
5398 ret = -EINVAL;
5399 goto err;
5400 }
5401
5402 if (pinctrl_info->pinctrl == NULL) {
5403 pr_err("%s: pinctrl_info->pinctrl is NULL\n", __func__);
5404 ret = -EINVAL;
5405 goto err;
5406 }
5407
5408 curr_state = pinctrl_info->curr_state;
5409 pinctrl_info->curr_state = new_state;
5410 pr_debug("%s: curr_state = %s new_state = %s\n", __func__,
5411 pin_states[curr_state], pin_states[pinctrl_info->curr_state]);
5412
5413 if (curr_state == pinctrl_info->curr_state) {
5414 pr_debug("%s: Already in same state\n", __func__);
5415 goto err;
5416 }
5417
5418 if (curr_state != STATE_DISABLE &&
5419 pinctrl_info->curr_state != STATE_DISABLE) {
5420 pr_debug("%s: state already active cannot switch\n", __func__);
5421 ret = -EIO;
5422 goto err;
5423 }
5424
5425 switch (pinctrl_info->curr_state) {
5426 case STATE_MI2S_ACTIVE:
5427 ret = pinctrl_select_state(pinctrl_info->pinctrl,
5428 pinctrl_info->mi2s_active);
5429 if (ret) {
5430 pr_err("%s: MI2S state select failed with %d\n",
5431 __func__, ret);
5432 ret = -EIO;
5433 goto err;
5434 }
5435 break;
5436 case STATE_TDM_ACTIVE:
5437 ret = pinctrl_select_state(pinctrl_info->pinctrl,
5438 pinctrl_info->tdm_active);
5439 if (ret) {
5440 pr_err("%s: TDM state select failed with %d\n",
5441 __func__, ret);
5442 ret = -EIO;
5443 goto err;
5444 }
5445 break;
5446 case STATE_DISABLE:
5447 if (curr_state == STATE_MI2S_ACTIVE) {
5448 ret = pinctrl_select_state(pinctrl_info->pinctrl,
5449 pinctrl_info->mi2s_disable);
5450 } else {
5451 ret = pinctrl_select_state(pinctrl_info->pinctrl,
5452 pinctrl_info->tdm_disable);
5453 }
5454 if (ret) {
5455 pr_err("%s: state disable failed with %d\n",
5456 __func__, ret);
5457 ret = -EIO;
5458 goto err;
5459 }
5460 break;
5461 default:
5462 pr_err("%s: TLMM pin state is invalid\n", __func__);
5463 return -EINVAL;
5464 }
5465
5466err:
5467 return ret;
5468}
5469
5470static int msm_get_pinctrl(struct platform_device *pdev)
5471{
5472 struct snd_soc_card *card = platform_get_drvdata(pdev);
5473 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
5474 struct msm_pinctrl_info *pinctrl_info = NULL;
5475 struct pinctrl *pinctrl;
5476 int ret = 0;
5477
5478 pinctrl_info = &pdata->pinctrl_info;
5479
5480 if (pinctrl_info == NULL) {
5481 pr_err("%s: pinctrl_info is NULL\n", __func__);
5482 return -EINVAL;
5483 }
5484
5485 pinctrl = devm_pinctrl_get(&pdev->dev);
5486 if (IS_ERR_OR_NULL(pinctrl)) {
5487 pr_err("%s: Unable to get pinctrl handle\n", __func__);
5488 return -EINVAL;
5489 }
5490 pinctrl_info->pinctrl = pinctrl;
5491
5492 /* get all the states handles from Device Tree */
5493 pinctrl_info->mi2s_disable = pinctrl_lookup_state(pinctrl,
5494 "quat-mi2s-sleep");
5495 if (IS_ERR(pinctrl_info->mi2s_disable)) {
5496 pr_err("%s: could not get mi2s_disable pinstate\n", __func__);
5497 goto err;
5498 }
5499 pinctrl_info->mi2s_active = pinctrl_lookup_state(pinctrl,
5500 "quat-mi2s-active");
5501 if (IS_ERR(pinctrl_info->mi2s_active)) {
5502 pr_err("%s: could not get mi2s_active pinstate\n", __func__);
5503 goto err;
5504 }
5505 pinctrl_info->tdm_disable = pinctrl_lookup_state(pinctrl,
5506 "quat-tdm-sleep");
5507 if (IS_ERR(pinctrl_info->tdm_disable)) {
5508 pr_err("%s: could not get tdm_disable pinstate\n", __func__);
5509 goto err;
5510 }
5511 pinctrl_info->tdm_active = pinctrl_lookup_state(pinctrl,
5512 "quat-tdm-active");
5513 if (IS_ERR(pinctrl_info->tdm_active)) {
5514 pr_err("%s: could not get tdm_active pinstate\n",
5515 __func__);
5516 goto err;
5517 }
5518 /* Reset the TLMM pins to a default state */
5519 ret = pinctrl_select_state(pinctrl_info->pinctrl,
5520 pinctrl_info->mi2s_disable);
5521 if (ret != 0) {
5522 pr_err("%s: Disable TLMM pins failed with %d\n",
5523 __func__, ret);
5524 ret = -EIO;
5525 goto err;
5526 }
5527 pinctrl_info->curr_state = STATE_DISABLE;
5528
5529 return 0;
5530
5531err:
5532 devm_pinctrl_put(pinctrl);
5533 pinctrl_info->pinctrl = NULL;
5534 return -EINVAL;
5535}
5536
5537static int msm_tdm_be_hw_params_fixup(struct snd_soc_pcm_runtime *rtd,
5538 struct snd_pcm_hw_params *params)
5539{
5540 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
5541 struct snd_interval *rate = hw_param_interval(params,
5542 SNDRV_PCM_HW_PARAM_RATE);
5543 struct snd_interval *channels = hw_param_interval(params,
5544 SNDRV_PCM_HW_PARAM_CHANNELS);
5545
5546 if (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) {
5547 channels->min = channels->max =
5548 tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
5549 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
5550 tdm_rx_cfg[TDM_QUAT][TDM_0].bit_format);
5551 rate->min = rate->max =
5552 tdm_rx_cfg[TDM_QUAT][TDM_0].sample_rate;
5553 } else if (cpu_dai->id == AFE_PORT_ID_SECONDARY_TDM_RX) {
5554 channels->min = channels->max =
5555 tdm_rx_cfg[TDM_SEC][TDM_0].channels;
5556 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
5557 tdm_rx_cfg[TDM_SEC][TDM_0].bit_format);
5558 rate->min = rate->max = tdm_rx_cfg[TDM_SEC][TDM_0].sample_rate;
5559 } else if (cpu_dai->id == AFE_PORT_ID_QUINARY_TDM_RX) {
5560 channels->min = channels->max =
5561 tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
5562 param_set_mask(params, SNDRV_PCM_HW_PARAM_FORMAT,
5563 tdm_rx_cfg[TDM_QUIN][TDM_0].bit_format);
5564 rate->min = rate->max = tdm_rx_cfg[TDM_QUIN][TDM_0].sample_rate;
5565 } else {
5566 pr_err("%s: dai id 0x%x not supported\n",
5567 __func__, cpu_dai->id);
5568 return -EINVAL;
5569 }
5570
5571 pr_debug("%s: dai id = 0x%x channels = %d rate = %d format = 0x%x\n",
5572 __func__, cpu_dai->id, channels->max, rate->max,
5573 params_format(params));
5574
5575 return 0;
5576}
5577
5578static int sm6150_tdm_snd_hw_params(struct snd_pcm_substream *substream,
5579 struct snd_pcm_hw_params *params)
5580{
5581 struct snd_soc_pcm_runtime *rtd = substream->private_data;
5582 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
5583 int ret = 0;
5584 int slot_width = 32;
5585 int channels, slots;
5586 unsigned int slot_mask, rate, clk_freq;
5587 unsigned int slot_offset[8] = {0, 4, 8, 12, 16, 20, 24, 28};
5588
5589 pr_debug("%s: dai id = 0x%x\n", __func__, cpu_dai->id);
5590
5591 /* currently only supporting TDM_RX_0 and TDM_TX_0 */
5592 switch (cpu_dai->id) {
5593 case AFE_PORT_ID_PRIMARY_TDM_RX:
5594 slots = tdm_rx_cfg[TDM_PRI][TDM_0].channels;
5595 break;
5596 case AFE_PORT_ID_SECONDARY_TDM_RX:
5597 slots = tdm_rx_cfg[TDM_SEC][TDM_0].channels;
5598 break;
5599 case AFE_PORT_ID_TERTIARY_TDM_RX:
5600 slots = tdm_rx_cfg[TDM_TERT][TDM_0].channels;
5601 break;
5602 case AFE_PORT_ID_QUATERNARY_TDM_RX:
5603 slots = tdm_rx_cfg[TDM_QUAT][TDM_0].channels;
5604 break;
5605 case AFE_PORT_ID_QUINARY_TDM_RX:
5606 slots = tdm_rx_cfg[TDM_QUIN][TDM_0].channels;
5607 break;
5608 case AFE_PORT_ID_PRIMARY_TDM_TX:
5609 slots = tdm_tx_cfg[TDM_PRI][TDM_0].channels;
5610 break;
5611 case AFE_PORT_ID_SECONDARY_TDM_TX:
5612 slots = tdm_tx_cfg[TDM_SEC][TDM_0].channels;
5613 break;
5614 case AFE_PORT_ID_TERTIARY_TDM_TX:
5615 slots = tdm_tx_cfg[TDM_TERT][TDM_0].channels;
5616 break;
5617 case AFE_PORT_ID_QUATERNARY_TDM_TX:
5618 slots = tdm_tx_cfg[TDM_QUAT][TDM_0].channels;
5619 break;
5620 case AFE_PORT_ID_QUINARY_TDM_TX:
5621 slots = tdm_tx_cfg[TDM_QUIN][TDM_0].channels;
5622 break;
5623
5624 default:
5625 pr_err("%s: dai id 0x%x not supported\n",
5626 __func__, cpu_dai->id);
5627 return -EINVAL;
5628 }
5629
5630 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
5631 /*2 slot config - bits 0 and 1 set for the first two slots */
5632 slot_mask = 0x0000FFFF >> (16-slots);
5633 channels = slots;
5634
5635 pr_debug("%s: tdm rx slot_width %d slots %d\n",
5636 __func__, slot_width, slots);
5637
5638 ret = snd_soc_dai_set_tdm_slot(cpu_dai, 0, slot_mask,
5639 slots, slot_width);
5640 if (ret < 0) {
5641 pr_err("%s: failed to set tdm rx slot, err:%d\n",
5642 __func__, ret);
5643 goto end;
5644 }
5645
5646 ret = snd_soc_dai_set_channel_map(cpu_dai,
5647 0, NULL, channels, slot_offset);
5648 if (ret < 0) {
5649 pr_err("%s: failed to set tdm rx channel map, err:%d\n",
5650 __func__, ret);
5651 goto end;
5652 }
5653 } else if (substream->stream == SNDRV_PCM_STREAM_CAPTURE) {
5654 /*2 slot config - bits 0 and 1 set for the first two slots */
5655 slot_mask = 0x0000FFFF >> (16-slots);
5656 channels = slots;
5657
5658 pr_debug("%s: tdm tx slot_width %d slots %d\n",
5659 __func__, slot_width, slots);
5660
5661 ret = snd_soc_dai_set_tdm_slot(cpu_dai, slot_mask, 0,
5662 slots, slot_width);
5663 if (ret < 0) {
5664 pr_err("%s: failed to set tdm tx slot, err:%d\n",
5665 __func__, ret);
5666 goto end;
5667 }
5668
5669 ret = snd_soc_dai_set_channel_map(cpu_dai,
5670 channels, slot_offset, 0, NULL);
5671 if (ret < 0) {
5672 pr_err("%s: failed to set tdm tx channel map, err:%d\n",
5673 __func__, ret);
5674 goto end;
5675 }
5676 } else {
5677 ret = -EINVAL;
5678 pr_err("%s: invalid use case, err:%d\n",
5679 __func__, ret);
5680 goto end;
5681 }
5682
5683 rate = params_rate(params);
5684 clk_freq = rate * slot_width * slots;
5685 ret = snd_soc_dai_set_sysclk(cpu_dai, 0, clk_freq, SND_SOC_CLOCK_OUT);
5686 if (ret < 0)
5687 pr_err("%s: failed to set tdm clk, err:%d\n",
5688 __func__, ret);
5689
5690end:
5691 return ret;
5692}
5693
5694static int sm6150_tdm_snd_startup(struct snd_pcm_substream *substream)
5695{
5696 int ret = 0;
5697 struct snd_soc_pcm_runtime *rtd = substream->private_data;
5698 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
5699 struct snd_soc_card *card = rtd->card;
5700 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
5701 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
5702
5703 /* currently only supporting TDM_RX_0 and TDM_TX_0 */
5704 if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
5705 (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
5706 ret = msm_set_pinctrl(pinctrl_info, STATE_TDM_ACTIVE);
5707 if (ret)
5708 pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
5709 __func__, ret);
5710 }
5711
5712 return ret;
5713}
5714
5715static void sm6150_tdm_snd_shutdown(struct snd_pcm_substream *substream)
5716{
5717 int ret = 0;
5718 struct snd_soc_pcm_runtime *rtd = substream->private_data;
5719 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
5720 struct snd_soc_card *card = rtd->card;
5721 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
5722 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
5723
5724 /* currently only supporting TDM_RX_0 and TDM_TX_0 */
5725 if ((cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_RX) ||
5726 (cpu_dai->id == AFE_PORT_ID_QUATERNARY_TDM_TX)) {
5727 ret = msm_set_pinctrl(pinctrl_info, STATE_DISABLE);
5728 if (ret)
5729 pr_err("%s: TDM TLMM pinctrl set failed with %d\n",
5730 __func__, ret);
5731 }
5732}
5733
5734static struct snd_soc_ops sm6150_tdm_be_ops = {
5735 .hw_params = sm6150_tdm_snd_hw_params,
5736 .startup = sm6150_tdm_snd_startup,
5737 .shutdown = sm6150_tdm_snd_shutdown
5738};
5739
5740static int msm_fe_qos_prepare(struct snd_pcm_substream *substream)
5741{
5742 cpumask_t mask;
5743
5744 if (pm_qos_request_active(&substream->latency_pm_qos_req))
5745 pm_qos_remove_request(&substream->latency_pm_qos_req);
5746
5747 cpumask_clear(&mask);
5748 cpumask_set_cpu(1, &mask); /* affine to core 1 */
5749 cpumask_set_cpu(2, &mask); /* affine to core 2 */
5750 cpumask_copy(&substream->latency_pm_qos_req.cpus_affine, &mask);
5751
5752 substream->latency_pm_qos_req.type = PM_QOS_REQ_AFFINE_CORES;
5753
5754 pm_qos_add_request(&substream->latency_pm_qos_req,
5755 PM_QOS_CPU_DMA_LATENCY,
5756 MSM_LL_QOS_VALUE);
5757 return 0;
5758}
5759
5760static struct snd_soc_ops msm_fe_qos_ops = {
5761 .prepare = msm_fe_qos_prepare,
5762};
5763
5764static int msm_mi2s_snd_startup(struct snd_pcm_substream *substream)
5765{
5766 int ret = 0;
5767 struct snd_soc_pcm_runtime *rtd = substream->private_data;
5768 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
5769 int index = cpu_dai->id;
5770 unsigned int fmt = SND_SOC_DAIFMT_CBS_CFS;
5771 struct snd_soc_card *card = rtd->card;
5772 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
5773 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
5774 int ret_pinctrl = 0;
5775
5776 dev_dbg(rtd->card->dev,
5777 "%s: substream = %s stream = %d, dai name %s, dai ID %d\n",
5778 __func__, substream->name, substream->stream,
5779 cpu_dai->name, cpu_dai->id);
5780
5781 if (index < PRIM_MI2S || index >= MI2S_MAX) {
5782 ret = -EINVAL;
5783 dev_err(rtd->card->dev,
5784 "%s: CPU DAI id (%d) out of range\n",
5785 __func__, cpu_dai->id);
5786 goto err;
5787 }
5788 /*
5789 * Mutex protection in case the same MI2S
5790 * interface using for both TX and RX so
5791 * that the same clock won't be enable twice.
5792 */
5793 mutex_lock(&mi2s_intf_conf[index].lock);
5794 if (++mi2s_intf_conf[index].ref_cnt == 1) {
5795 /* Check if msm needs to provide the clock to the interface */
5796 if (!mi2s_intf_conf[index].msm_is_mi2s_master) {
5797 mi2s_clk[index].clk_id = mi2s_ebit_clk[index];
5798 fmt = SND_SOC_DAIFMT_CBM_CFM;
5799 }
5800 ret = msm_mi2s_set_sclk(substream, true);
5801 if (ret < 0) {
5802 dev_err(rtd->card->dev,
5803 "%s: afe lpass clock failed to enable MI2S clock, err:%d\n",
5804 __func__, ret);
5805 goto clean_up;
5806 }
5807
5808 ret = snd_soc_dai_set_fmt(cpu_dai, fmt);
5809 if (ret < 0) {
5810 pr_err("%s: set fmt cpu dai failed for MI2S (%d), err:%d\n",
5811 __func__, index, ret);
5812 goto clk_off;
5813 }
5814 if (index == QUAT_MI2S) {
5815 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
5816 STATE_MI2S_ACTIVE);
5817 if (ret_pinctrl)
5818 pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
5819 __func__, ret_pinctrl);
5820 }
5821 }
5822clk_off:
5823 if (ret < 0)
5824 msm_mi2s_set_sclk(substream, false);
5825clean_up:
5826 if (ret < 0)
5827 mi2s_intf_conf[index].ref_cnt--;
5828 mutex_unlock(&mi2s_intf_conf[index].lock);
5829err:
5830 return ret;
5831}
5832
5833static void msm_mi2s_snd_shutdown(struct snd_pcm_substream *substream)
5834{
5835 int ret;
5836 struct snd_soc_pcm_runtime *rtd = substream->private_data;
5837 int index = rtd->cpu_dai->id;
5838 struct snd_soc_card *card = rtd->card;
5839 struct msm_asoc_mach_data *pdata = snd_soc_card_get_drvdata(card);
5840 struct msm_pinctrl_info *pinctrl_info = &pdata->pinctrl_info;
5841 int ret_pinctrl = 0;
5842
5843 pr_debug("%s(): substream = %s stream = %d\n", __func__,
5844 substream->name, substream->stream);
5845 if (index < PRIM_MI2S || index >= MI2S_MAX) {
5846 pr_err("%s:invalid MI2S DAI(%d)\n", __func__, index);
5847 return;
5848 }
5849
5850 mutex_lock(&mi2s_intf_conf[index].lock);
5851 if (--mi2s_intf_conf[index].ref_cnt == 0) {
5852 ret = msm_mi2s_set_sclk(substream, false);
5853 if (ret < 0)
5854 pr_err("%s:clock disable failed for MI2S (%d); ret=%d\n",
5855 __func__, index, ret);
5856 if (index == QUAT_MI2S) {
5857 ret_pinctrl = msm_set_pinctrl(pinctrl_info,
5858 STATE_DISABLE);
5859 if (ret_pinctrl)
5860 pr_err("%s: MI2S TLMM pinctrl set failed with %d\n",
5861 __func__, ret_pinctrl);
5862 }
5863 }
5864 mutex_unlock(&mi2s_intf_conf[index].lock);
5865}
5866
5867static struct snd_soc_ops msm_mi2s_be_ops = {
5868 .startup = msm_mi2s_snd_startup,
5869 .shutdown = msm_mi2s_snd_shutdown,
5870};
5871
5872static struct snd_soc_ops msm_cdc_dma_be_ops = {
5873 .hw_params = msm_snd_cdc_dma_hw_params,
5874};
5875
5876static struct snd_soc_ops msm_be_ops = {
5877 .hw_params = msm_snd_hw_params,
5878};
5879
5880static struct snd_soc_ops msm_slimbus_2_be_ops = {
5881 .hw_params = msm_slimbus_2_hw_params,
5882};
5883
5884static struct snd_soc_ops msm_wcn_ops = {
5885 .hw_params = msm_wcn_hw_params,
5886};
5887
5888
5889/* Digital audio interface glue - connects codec <---> CPU */
5890static struct snd_soc_dai_link msm_common_dai_links[] = {
5891 /* FrontEnd DAI Links */
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]5892 {/* hw:x,0 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]5893 .name = MSM_DAILINK_NAME(Media1),
5894 .stream_name = "MultiMedia1",
5895 .cpu_dai_name = "MultiMedia1",
5896 .platform_name = "msm-pcm-dsp.0",
5897 .dynamic = 1,
5898 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5899 .dpcm_playback = 1,
5900 .dpcm_capture = 1,
5901 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5902 SND_SOC_DPCM_TRIGGER_POST},
5903 .codec_dai_name = "snd-soc-dummy-dai",
5904 .codec_name = "snd-soc-dummy",
5905 .ignore_suspend = 1,
5906 /* this dainlink has playback support */
5907 .ignore_pmdown_time = 1,
5908 .id = MSM_FRONTEND_DAI_MULTIMEDIA1
5909 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]5910 {/* hw:x,1 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]5911 .name = MSM_DAILINK_NAME(Media2),
5912 .stream_name = "MultiMedia2",
5913 .cpu_dai_name = "MultiMedia2",
5914 .platform_name = "msm-pcm-dsp.0",
5915 .dynamic = 1,
5916 .dpcm_playback = 1,
5917 .dpcm_capture = 1,
5918 .codec_dai_name = "snd-soc-dummy-dai",
5919 .codec_name = "snd-soc-dummy",
5920 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5921 SND_SOC_DPCM_TRIGGER_POST},
5922 .ignore_suspend = 1,
5923 /* this dainlink has playback support */
5924 .ignore_pmdown_time = 1,
5925 .id = MSM_FRONTEND_DAI_MULTIMEDIA2,
5926 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]5927 {/* hw:x,2 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]5928 .name = "VoiceMMode1",
5929 .stream_name = "VoiceMMode1",
5930 .cpu_dai_name = "VoiceMMode1",
5931 .platform_name = "msm-pcm-voice",
5932 .dynamic = 1,
5933 .dpcm_playback = 1,
5934 .dpcm_capture = 1,
5935 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5936 SND_SOC_DPCM_TRIGGER_POST},
5937 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5938 .ignore_suspend = 1,
5939 .ignore_pmdown_time = 1,
5940 .codec_dai_name = "snd-soc-dummy-dai",
5941 .codec_name = "snd-soc-dummy",
5942 .id = MSM_FRONTEND_DAI_VOICEMMODE1,
5943 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]5944 {/* hw:x,3 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]5945 .name = "MSM VoIP",
5946 .stream_name = "VoIP",
5947 .cpu_dai_name = "VoIP",
5948 .platform_name = "msm-voip-dsp",
5949 .dynamic = 1,
5950 .dpcm_playback = 1,
5951 .dpcm_capture = 1,
5952 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5953 SND_SOC_DPCM_TRIGGER_POST},
5954 .codec_dai_name = "snd-soc-dummy-dai",
5955 .codec_name = "snd-soc-dummy",
5956 .ignore_suspend = 1,
5957 /* this dainlink has playback support */
5958 .ignore_pmdown_time = 1,
5959 .id = MSM_FRONTEND_DAI_VOIP,
5960 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]5961 {/* hw:x,4 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]5962 .name = MSM_DAILINK_NAME(ULL),
5963 .stream_name = "MultiMedia3",
5964 .cpu_dai_name = "MultiMedia3",
5965 .platform_name = "msm-pcm-dsp.2",
5966 .dynamic = 1,
5967 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
5968 .dpcm_playback = 1,
5969 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5970 SND_SOC_DPCM_TRIGGER_POST},
5971 .codec_dai_name = "snd-soc-dummy-dai",
5972 .codec_name = "snd-soc-dummy",
5973 .ignore_suspend = 1,
5974 /* this dainlink has playback support */
5975 .ignore_pmdown_time = 1,
5976 .id = MSM_FRONTEND_DAI_MULTIMEDIA3,
5977 },
5978 /* Hostless PCM purpose */
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]5979 {/* hw:x,5 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]5980 .name = "SLIMBUS_0 Hostless",
5981 .stream_name = "SLIMBUS_0 Hostless",
5982 .cpu_dai_name = "SLIMBUS0_HOSTLESS",
5983 .platform_name = "msm-pcm-hostless",
5984 .dynamic = 1,
5985 .dpcm_playback = 1,
5986 .dpcm_capture = 1,
5987 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
5988 SND_SOC_DPCM_TRIGGER_POST},
5989 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
5990 .ignore_suspend = 1,
5991 /* this dailink has playback support */
5992 .ignore_pmdown_time = 1,
5993 .codec_dai_name = "snd-soc-dummy-dai",
5994 .codec_name = "snd-soc-dummy",
5995 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]5996 {/* hw:x,6 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]5997 .name = "MSM AFE-PCM RX",
5998 .stream_name = "AFE-PROXY RX",
5999 .cpu_dai_name = "msm-dai-q6-dev.241",
6000 .codec_name = "msm-stub-codec.1",
6001 .codec_dai_name = "msm-stub-rx",
6002 .platform_name = "msm-pcm-afe",
6003 .dpcm_playback = 1,
6004 .ignore_suspend = 1,
6005 /* this dainlink has playback support */
6006 .ignore_pmdown_time = 1,
6007 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6008 {/* hw:x,7 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6009 .name = "MSM AFE-PCM TX",
6010 .stream_name = "AFE-PROXY TX",
6011 .cpu_dai_name = "msm-dai-q6-dev.240",
6012 .codec_name = "msm-stub-codec.1",
6013 .codec_dai_name = "msm-stub-tx",
6014 .platform_name = "msm-pcm-afe",
6015 .dpcm_capture = 1,
6016 .ignore_suspend = 1,
6017 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6018 {/* hw:x,8 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6019 .name = MSM_DAILINK_NAME(Compress1),
6020 .stream_name = "Compress1",
6021 .cpu_dai_name = "MultiMedia4",
6022 .platform_name = "msm-compress-dsp",
6023 .dynamic = 1,
6024 .async_ops = ASYNC_DPCM_SND_SOC_HW_PARAMS,
6025 .dpcm_playback = 1,
6026 .dpcm_capture = 1,
6027 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6028 SND_SOC_DPCM_TRIGGER_POST},
6029 .codec_dai_name = "snd-soc-dummy-dai",
6030 .codec_name = "snd-soc-dummy",
6031 .ignore_suspend = 1,
6032 .ignore_pmdown_time = 1,
6033 /* this dainlink has playback support */
6034 .id = MSM_FRONTEND_DAI_MULTIMEDIA4,
6035 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6036 {/* hw:x,9 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6037 .name = "AUXPCM Hostless",
6038 .stream_name = "AUXPCM Hostless",
6039 .cpu_dai_name = "AUXPCM_HOSTLESS",
6040 .platform_name = "msm-pcm-hostless",
6041 .dynamic = 1,
6042 .dpcm_playback = 1,
6043 .dpcm_capture = 1,
6044 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6045 SND_SOC_DPCM_TRIGGER_POST},
6046 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6047 .ignore_suspend = 1,
6048 /* this dainlink has playback support */
6049 .ignore_pmdown_time = 1,
6050 .codec_dai_name = "snd-soc-dummy-dai",
6051 .codec_name = "snd-soc-dummy",
6052 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6053 {/* hw:x,10 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6054 .name = "SLIMBUS_1 Hostless",
6055 .stream_name = "SLIMBUS_1 Hostless",
6056 .cpu_dai_name = "SLIMBUS1_HOSTLESS",
6057 .platform_name = "msm-pcm-hostless",
6058 .dynamic = 1,
6059 .dpcm_playback = 1,
6060 .dpcm_capture = 1,
6061 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6062 SND_SOC_DPCM_TRIGGER_POST},
6063 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6064 .ignore_suspend = 1,
6065 /* this dailink has playback support */
6066 .ignore_pmdown_time = 1,
6067 .codec_dai_name = "snd-soc-dummy-dai",
6068 .codec_name = "snd-soc-dummy",
6069 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6070 {/* hw:x,11 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6071 .name = "SLIMBUS_3 Hostless",
6072 .stream_name = "SLIMBUS_3 Hostless",
6073 .cpu_dai_name = "SLIMBUS3_HOSTLESS",
6074 .platform_name = "msm-pcm-hostless",
6075 .dynamic = 1,
6076 .dpcm_playback = 1,
6077 .dpcm_capture = 1,
6078 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6079 SND_SOC_DPCM_TRIGGER_POST},
6080 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6081 .ignore_suspend = 1,
6082 /* this dailink has playback support */
6083 .ignore_pmdown_time = 1,
6084 .codec_dai_name = "snd-soc-dummy-dai",
6085 .codec_name = "snd-soc-dummy",
6086 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6087 {/* hw:x,12 */
6088 .name = "SLIMBUS_7 Hostless",
6089 .stream_name = "SLIMBUS_7 Hostless",
6090 .cpu_dai_name = "SLIMBUS7_HOSTLESS",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6091 .platform_name = "msm-pcm-hostless",
6092 .dynamic = 1,
6093 .dpcm_playback = 1,
6094 .dpcm_capture = 1,
6095 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6096 SND_SOC_DPCM_TRIGGER_POST},
6097 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6098 .ignore_suspend = 1,
6099 /* this dailink has playback support */
6100 .ignore_pmdown_time = 1,
6101 .codec_dai_name = "snd-soc-dummy-dai",
6102 .codec_name = "snd-soc-dummy",
6103 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6104 {/* hw:x,13 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6105 .name = MSM_DAILINK_NAME(LowLatency),
6106 .stream_name = "MultiMedia5",
6107 .cpu_dai_name = "MultiMedia5",
6108 .platform_name = "msm-pcm-dsp.1",
6109 .dynamic = 1,
6110 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
6111 .dpcm_playback = 1,
6112 .dpcm_capture = 1,
6113 .codec_dai_name = "snd-soc-dummy-dai",
6114 .codec_name = "snd-soc-dummy",
6115 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6116 SND_SOC_DPCM_TRIGGER_POST},
6117 .ignore_suspend = 1,
6118 /* this dainlink has playback support */
6119 .ignore_pmdown_time = 1,
6120 .id = MSM_FRONTEND_DAI_MULTIMEDIA5,
6121 .ops = &msm_fe_qos_ops,
6122 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6123 {/* hw:x,14 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6124 .name = "Listen 1 Audio Service",
6125 .stream_name = "Listen 1 Audio Service",
6126 .cpu_dai_name = "LSM1",
6127 .platform_name = "msm-lsm-client",
6128 .dynamic = 1,
6129 .dpcm_capture = 1,
6130 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
6131 SND_SOC_DPCM_TRIGGER_POST },
6132 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6133 .ignore_suspend = 1,
6134 .codec_dai_name = "snd-soc-dummy-dai",
6135 .codec_name = "snd-soc-dummy",
6136 .id = MSM_FRONTEND_DAI_LSM1,
6137 },
6138 /* Multiple Tunnel instances */
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6139 {/* hw:x,15 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6140 .name = MSM_DAILINK_NAME(Compress2),
6141 .stream_name = "Compress2",
6142 .cpu_dai_name = "MultiMedia7",
6143 .platform_name = "msm-compress-dsp",
6144 .dynamic = 1,
6145 .dpcm_playback = 1,
6146 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6147 SND_SOC_DPCM_TRIGGER_POST},
6148 .codec_dai_name = "snd-soc-dummy-dai",
6149 .codec_name = "snd-soc-dummy",
6150 .ignore_suspend = 1,
6151 .ignore_pmdown_time = 1,
6152 /* this dainlink has playback support */
6153 .id = MSM_FRONTEND_DAI_MULTIMEDIA7,
6154 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6155 {/* hw:x,16 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6156 .name = MSM_DAILINK_NAME(MultiMedia10),
6157 .stream_name = "MultiMedia10",
6158 .cpu_dai_name = "MultiMedia10",
6159 .platform_name = "msm-pcm-dsp.1",
6160 .dynamic = 1,
6161 .dpcm_playback = 1,
6162 .dpcm_capture = 1,
6163 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6164 SND_SOC_DPCM_TRIGGER_POST},
6165 .codec_dai_name = "snd-soc-dummy-dai",
6166 .codec_name = "snd-soc-dummy",
6167 .ignore_suspend = 1,
6168 .ignore_pmdown_time = 1,
6169 /* this dainlink has playback support */
6170 .id = MSM_FRONTEND_DAI_MULTIMEDIA10,
6171 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6172 {/* hw:x,17 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6173 .name = MSM_DAILINK_NAME(ULL_NOIRQ),
6174 .stream_name = "MM_NOIRQ",
6175 .cpu_dai_name = "MultiMedia8",
6176 .platform_name = "msm-pcm-dsp-noirq",
6177 .dynamic = 1,
6178 .dpcm_playback = 1,
6179 .dpcm_capture = 1,
6180 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6181 SND_SOC_DPCM_TRIGGER_POST},
6182 .codec_dai_name = "snd-soc-dummy-dai",
6183 .codec_name = "snd-soc-dummy",
6184 .ignore_suspend = 1,
6185 .ignore_pmdown_time = 1,
6186 /* this dainlink has playback support */
6187 .id = MSM_FRONTEND_DAI_MULTIMEDIA8,
6188 .ops = &msm_fe_qos_ops,
6189 },
6190 /* HDMI Hostless */
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6191 {/* hw:x,18 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6192 .name = "HDMI_RX_HOSTLESS",
6193 .stream_name = "HDMI_RX_HOSTLESS",
6194 .cpu_dai_name = "HDMI_HOSTLESS",
6195 .platform_name = "msm-pcm-hostless",
6196 .dynamic = 1,
6197 .dpcm_playback = 1,
6198 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6199 SND_SOC_DPCM_TRIGGER_POST},
6200 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6201 .ignore_suspend = 1,
6202 .ignore_pmdown_time = 1,
6203 .codec_dai_name = "snd-soc-dummy-dai",
6204 .codec_name = "snd-soc-dummy",
6205 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6206 {/* hw:x,19 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6207 .name = "VoiceMMode2",
6208 .stream_name = "VoiceMMode2",
6209 .cpu_dai_name = "VoiceMMode2",
6210 .platform_name = "msm-pcm-voice",
6211 .dynamic = 1,
6212 .dpcm_playback = 1,
6213 .dpcm_capture = 1,
6214 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6215 SND_SOC_DPCM_TRIGGER_POST},
6216 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6217 .ignore_suspend = 1,
6218 .ignore_pmdown_time = 1,
6219 .codec_dai_name = "snd-soc-dummy-dai",
6220 .codec_name = "snd-soc-dummy",
6221 .id = MSM_FRONTEND_DAI_VOICEMMODE2,
6222 },
6223 /* LSM FE */
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6224 {/* hw:x,20 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6225 .name = "Listen 2 Audio Service",
6226 .stream_name = "Listen 2 Audio Service",
6227 .cpu_dai_name = "LSM2",
6228 .platform_name = "msm-lsm-client",
6229 .dynamic = 1,
6230 .dpcm_capture = 1,
6231 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
6232 SND_SOC_DPCM_TRIGGER_POST },
6233 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6234 .ignore_suspend = 1,
6235 .codec_dai_name = "snd-soc-dummy-dai",
6236 .codec_name = "snd-soc-dummy",
6237 .id = MSM_FRONTEND_DAI_LSM2,
6238 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6239 {/* hw:x,21 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6240 .name = "Listen 3 Audio Service",
6241 .stream_name = "Listen 3 Audio Service",
6242 .cpu_dai_name = "LSM3",
6243 .platform_name = "msm-lsm-client",
6244 .dynamic = 1,
6245 .dpcm_capture = 1,
6246 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
6247 SND_SOC_DPCM_TRIGGER_POST },
6248 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6249 .ignore_suspend = 1,
6250 .codec_dai_name = "snd-soc-dummy-dai",
6251 .codec_name = "snd-soc-dummy",
6252 .id = MSM_FRONTEND_DAI_LSM3,
6253 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6254 {/* hw:x,22 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6255 .name = "Listen 4 Audio Service",
6256 .stream_name = "Listen 4 Audio Service",
6257 .cpu_dai_name = "LSM4",
6258 .platform_name = "msm-lsm-client",
6259 .dynamic = 1,
6260 .dpcm_capture = 1,
6261 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
6262 SND_SOC_DPCM_TRIGGER_POST },
6263 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6264 .ignore_suspend = 1,
6265 .codec_dai_name = "snd-soc-dummy-dai",
6266 .codec_name = "snd-soc-dummy",
6267 .id = MSM_FRONTEND_DAI_LSM4,
6268 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6269 {/* hw:x,23 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6270 .name = "Listen 5 Audio Service",
6271 .stream_name = "Listen 5 Audio Service",
6272 .cpu_dai_name = "LSM5",
6273 .platform_name = "msm-lsm-client",
6274 .dynamic = 1,
6275 .dpcm_capture = 1,
6276 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
6277 SND_SOC_DPCM_TRIGGER_POST },
6278 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6279 .ignore_suspend = 1,
6280 .codec_dai_name = "snd-soc-dummy-dai",
6281 .codec_name = "snd-soc-dummy",
6282 .id = MSM_FRONTEND_DAI_LSM5,
6283 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6284 {/* hw:x,24 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6285 .name = "Listen 6 Audio Service",
6286 .stream_name = "Listen 6 Audio Service",
6287 .cpu_dai_name = "LSM6",
6288 .platform_name = "msm-lsm-client",
6289 .dynamic = 1,
6290 .dpcm_capture = 1,
6291 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
6292 SND_SOC_DPCM_TRIGGER_POST },
6293 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6294 .ignore_suspend = 1,
6295 .codec_dai_name = "snd-soc-dummy-dai",
6296 .codec_name = "snd-soc-dummy",
6297 .id = MSM_FRONTEND_DAI_LSM6,
6298 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6299 {/* hw:x,25 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6300 .name = "Listen 7 Audio Service",
6301 .stream_name = "Listen 7 Audio Service",
6302 .cpu_dai_name = "LSM7",
6303 .platform_name = "msm-lsm-client",
6304 .dynamic = 1,
6305 .dpcm_capture = 1,
6306 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
6307 SND_SOC_DPCM_TRIGGER_POST },
6308 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6309 .ignore_suspend = 1,
6310 .codec_dai_name = "snd-soc-dummy-dai",
6311 .codec_name = "snd-soc-dummy",
6312 .id = MSM_FRONTEND_DAI_LSM7,
6313 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6314 {/* hw:x,26 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6315 .name = "Listen 8 Audio Service",
6316 .stream_name = "Listen 8 Audio Service",
6317 .cpu_dai_name = "LSM8",
6318 .platform_name = "msm-lsm-client",
6319 .dynamic = 1,
6320 .dpcm_capture = 1,
6321 .trigger = { SND_SOC_DPCM_TRIGGER_POST,
6322 SND_SOC_DPCM_TRIGGER_POST },
6323 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6324 .ignore_suspend = 1,
6325 .codec_dai_name = "snd-soc-dummy-dai",
6326 .codec_name = "snd-soc-dummy",
6327 .id = MSM_FRONTEND_DAI_LSM8,
6328 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6329 {/* hw:x,27 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6330 .name = MSM_DAILINK_NAME(Media9),
6331 .stream_name = "MultiMedia9",
6332 .cpu_dai_name = "MultiMedia9",
6333 .platform_name = "msm-pcm-dsp.0",
6334 .dynamic = 1,
6335 .dpcm_playback = 1,
6336 .dpcm_capture = 1,
6337 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6338 SND_SOC_DPCM_TRIGGER_POST},
6339 .codec_dai_name = "snd-soc-dummy-dai",
6340 .codec_name = "snd-soc-dummy",
6341 .ignore_suspend = 1,
6342 /* this dainlink has playback support */
6343 .ignore_pmdown_time = 1,
6344 .id = MSM_FRONTEND_DAI_MULTIMEDIA9,
6345 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6346 {/* hw:x,28 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6347 .name = MSM_DAILINK_NAME(Compress4),
6348 .stream_name = "Compress4",
6349 .cpu_dai_name = "MultiMedia11",
6350 .platform_name = "msm-compress-dsp",
6351 .dynamic = 1,
6352 .dpcm_playback = 1,
6353 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6354 SND_SOC_DPCM_TRIGGER_POST},
6355 .codec_dai_name = "snd-soc-dummy-dai",
6356 .codec_name = "snd-soc-dummy",
6357 .ignore_suspend = 1,
6358 .ignore_pmdown_time = 1,
6359 /* this dainlink has playback support */
6360 .id = MSM_FRONTEND_DAI_MULTIMEDIA11,
6361 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6362 {/* hw:x,29 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6363 .name = MSM_DAILINK_NAME(Compress5),
6364 .stream_name = "Compress5",
6365 .cpu_dai_name = "MultiMedia12",
6366 .platform_name = "msm-compress-dsp",
6367 .dynamic = 1,
6368 .dpcm_playback = 1,
6369 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6370 SND_SOC_DPCM_TRIGGER_POST},
6371 .codec_dai_name = "snd-soc-dummy-dai",
6372 .codec_name = "snd-soc-dummy",
6373 .ignore_suspend = 1,
6374 .ignore_pmdown_time = 1,
6375 /* this dainlink has playback support */
6376 .id = MSM_FRONTEND_DAI_MULTIMEDIA12,
6377 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6378 {/* hw:x,30 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6379 .name = MSM_DAILINK_NAME(Compress6),
6380 .stream_name = "Compress6",
6381 .cpu_dai_name = "MultiMedia13",
6382 .platform_name = "msm-compress-dsp",
6383 .dynamic = 1,
6384 .dpcm_playback = 1,
6385 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6386 SND_SOC_DPCM_TRIGGER_POST},
6387 .codec_dai_name = "snd-soc-dummy-dai",
6388 .codec_name = "snd-soc-dummy",
6389 .ignore_suspend = 1,
6390 .ignore_pmdown_time = 1,
6391 /* this dainlink has playback support */
6392 .id = MSM_FRONTEND_DAI_MULTIMEDIA13,
6393 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6394 {/* hw:x,31 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6395 .name = MSM_DAILINK_NAME(Compress7),
6396 .stream_name = "Compress7",
6397 .cpu_dai_name = "MultiMedia14",
6398 .platform_name = "msm-compress-dsp",
6399 .dynamic = 1,
6400 .dpcm_playback = 1,
6401 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6402 SND_SOC_DPCM_TRIGGER_POST},
6403 .codec_dai_name = "snd-soc-dummy-dai",
6404 .codec_name = "snd-soc-dummy",
6405 .ignore_suspend = 1,
6406 .ignore_pmdown_time = 1,
6407 /* this dainlink has playback support */
6408 .id = MSM_FRONTEND_DAI_MULTIMEDIA14,
6409 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6410 {/* hw:x,32 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6411 .name = MSM_DAILINK_NAME(Compress8),
6412 .stream_name = "Compress8",
6413 .cpu_dai_name = "MultiMedia15",
6414 .platform_name = "msm-compress-dsp",
6415 .dynamic = 1,
6416 .dpcm_playback = 1,
6417 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6418 SND_SOC_DPCM_TRIGGER_POST},
6419 .codec_dai_name = "snd-soc-dummy-dai",
6420 .codec_name = "snd-soc-dummy",
6421 .ignore_suspend = 1,
6422 .ignore_pmdown_time = 1,
6423 /* this dainlink has playback support */
6424 .id = MSM_FRONTEND_DAI_MULTIMEDIA15,
6425 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6426 {/* hw:x,33 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6427 .name = MSM_DAILINK_NAME(ULL_NOIRQ_2),
6428 .stream_name = "MM_NOIRQ_2",
6429 .cpu_dai_name = "MultiMedia16",
6430 .platform_name = "msm-pcm-dsp-noirq",
6431 .dynamic = 1,
6432 .dpcm_playback = 1,
6433 .dpcm_capture = 1,
6434 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6435 SND_SOC_DPCM_TRIGGER_POST},
6436 .codec_dai_name = "snd-soc-dummy-dai",
6437 .codec_name = "snd-soc-dummy",
6438 .ignore_suspend = 1,
6439 .ignore_pmdown_time = 1,
6440 /* this dainlink has playback support */
6441 .id = MSM_FRONTEND_DAI_MULTIMEDIA16,
6442 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6443 {/* hw:x,34 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6444 .name = "SLIMBUS_8 Hostless",
6445 .stream_name = "SLIMBUS8_HOSTLESS Capture",
6446 .cpu_dai_name = "SLIMBUS8_HOSTLESS",
6447 .platform_name = "msm-pcm-hostless",
6448 .dynamic = 1,
6449 .dpcm_capture = 1,
6450 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6451 SND_SOC_DPCM_TRIGGER_POST},
6452 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6453 .ignore_suspend = 1,
6454 .codec_dai_name = "snd-soc-dummy-dai",
6455 .codec_name = "snd-soc-dummy",
6456 },
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6457 {/* hw:x,35 */
6458 .name = "CDC_DMA Hostless",
6459 .stream_name = "CDC_DMA Hostless",
6460 .cpu_dai_name = "CDC_DMA_HOSTLESS",
6461 .platform_name = "msm-pcm-hostless",
6462 .dynamic = 1,
6463 .dpcm_playback = 1,
6464 .dpcm_capture = 1,
6465 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6466 SND_SOC_DPCM_TRIGGER_POST},
6467 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6468 .ignore_suspend = 1,
6469 /* this dailink has playback support */
6470 .ignore_pmdown_time = 1,
6471 .codec_dai_name = "snd-soc-dummy-dai",
6472 .codec_name = "snd-soc-dummy",
6473 },
6474 {/* hw:x,36 */
6475 .name = "TX3_CDC_DMA Hostless",
6476 .stream_name = "TX3_CDC_DMA Hostless",
6477 .cpu_dai_name = "TX3_CDC_DMA_HOSTLESS",
6478 .platform_name = "msm-pcm-hostless",
6479 .dynamic = 1,
6480 .dpcm_capture = 1,
6481 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6482 SND_SOC_DPCM_TRIGGER_POST},
6483 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6484 .ignore_suspend = 1,
6485 .codec_dai_name = "snd-soc-dummy-dai",
6486 .codec_name = "snd-soc-dummy",
6487 },
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6488};
6489
6490
6491static struct snd_soc_dai_link msm_tavil_fe_dai_links[] = {
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6492 {/* hw:x,37 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6493 .name = LPASS_BE_SLIMBUS_4_TX,
6494 .stream_name = "Slimbus4 Capture",
6495 .cpu_dai_name = "msm-dai-q6-dev.16393",
6496 .platform_name = "msm-pcm-hostless",
6497 .codec_name = "tavil_codec",
6498 .codec_dai_name = "tavil_vifeedback",
6499 .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
6500 .be_hw_params_fixup = msm_be_hw_params_fixup,
6501 .ops = &msm_be_ops,
6502 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6503 .ignore_suspend = 1,
6504 },
6505 /* Ultrasound RX DAI Link */
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6506 {/* hw:x,38 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6507 .name = "SLIMBUS_2 Hostless Playback",
6508 .stream_name = "SLIMBUS_2 Hostless Playback",
6509 .cpu_dai_name = "msm-dai-q6-dev.16388",
6510 .platform_name = "msm-pcm-hostless",
6511 .codec_name = "tavil_codec",
6512 .codec_dai_name = "tavil_rx2",
6513 .ignore_suspend = 1,
6514 .ignore_pmdown_time = 1,
6515 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6516 .ops = &msm_slimbus_2_be_ops,
6517 },
6518 /* Ultrasound TX DAI Link */
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6519 {/* hw:x,39 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6520 .name = "SLIMBUS_2 Hostless Capture",
6521 .stream_name = "SLIMBUS_2 Hostless Capture",
6522 .cpu_dai_name = "msm-dai-q6-dev.16389",
6523 .platform_name = "msm-pcm-hostless",
6524 .codec_name = "tavil_codec",
6525 .codec_dai_name = "tavil_tx2",
6526 .ignore_suspend = 1,
6527 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6528 .ops = &msm_slimbus_2_be_ops,
6529 },
6530};
6531
6532static struct snd_soc_dai_link msm_bolero_fe_dai_links[] = {
Aditya Bavanaric65c7e42018-08-08 14:10:20 +0530[diff] [blame]6533 {/* hw:x,37 */
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]6534 .name = LPASS_BE_WSA_CDC_DMA_TX_0,
6535 .stream_name = "WSA CDC DMA0 Capture",
6536 .cpu_dai_name = "msm-dai-cdc-dma-dev.45057",
6537 .platform_name = "msm-pcm-hostless",
6538 .codec_name = "bolero_codec",
6539 .codec_dai_name = "wsa_macro_vifeedback",
6540 .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_0,
6541 .be_hw_params_fixup = msm_be_hw_params_fixup,
6542 .ignore_suspend = 1,
6543 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6544 .ops = &msm_cdc_dma_be_ops,
6545 },
6546};
6547
6548static struct snd_soc_dai_link msm_common_misc_fe_dai_links[] = {
6549 {
6550 .name = MSM_DAILINK_NAME(ASM Loopback),
6551 .stream_name = "MultiMedia6",
6552 .cpu_dai_name = "MultiMedia6",
6553 .platform_name = "msm-pcm-loopback",
6554 .dynamic = 1,
6555 .dpcm_playback = 1,
6556 .dpcm_capture = 1,
6557 .codec_dai_name = "snd-soc-dummy-dai",
6558 .codec_name = "snd-soc-dummy",
6559 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6560 SND_SOC_DPCM_TRIGGER_POST},
6561 .ignore_suspend = 1,
6562 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6563 .ignore_pmdown_time = 1,
6564 .id = MSM_FRONTEND_DAI_MULTIMEDIA6,
6565 },
6566 {
6567 .name = "USB Audio Hostless",
6568 .stream_name = "USB Audio Hostless",
6569 .cpu_dai_name = "USBAUDIO_HOSTLESS",
6570 .platform_name = "msm-pcm-hostless",
6571 .dynamic = 1,
6572 .dpcm_playback = 1,
6573 .dpcm_capture = 1,
6574 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
6575 SND_SOC_DPCM_TRIGGER_POST},
6576 .no_host_mode = SND_SOC_DAI_LINK_NO_HOST,
6577 .ignore_suspend = 1,
6578 .ignore_pmdown_time = 1,
6579 .codec_dai_name = "snd-soc-dummy-dai",
6580 .codec_name = "snd-soc-dummy",
6581 },
6582};
6583
6584static struct snd_soc_dai_link msm_common_be_dai_links[] = {
6585 /* Backend AFE DAI Links */
6586 {
6587 .name = LPASS_BE_AFE_PCM_RX,
6588 .stream_name = "AFE Playback",
6589 .cpu_dai_name = "msm-dai-q6-dev.224",
6590 .platform_name = "msm-pcm-routing",
6591 .codec_name = "msm-stub-codec.1",
6592 .codec_dai_name = "msm-stub-rx",
6593 .no_pcm = 1,
6594 .dpcm_playback = 1,
6595 .id = MSM_BACKEND_DAI_AFE_PCM_RX,
6596 .be_hw_params_fixup = msm_be_hw_params_fixup,
6597 /* this dainlink has playback support */
6598 .ignore_pmdown_time = 1,
6599 .ignore_suspend = 1,
6600 },
6601 {
6602 .name = LPASS_BE_AFE_PCM_TX,
6603 .stream_name = "AFE Capture",
6604 .cpu_dai_name = "msm-dai-q6-dev.225",
6605 .platform_name = "msm-pcm-routing",
6606 .codec_name = "msm-stub-codec.1",
6607 .codec_dai_name = "msm-stub-tx",
6608 .no_pcm = 1,
6609 .dpcm_capture = 1,
6610 .id = MSM_BACKEND_DAI_AFE_PCM_TX,
6611 .be_hw_params_fixup = msm_be_hw_params_fixup,
6612 .ignore_suspend = 1,
6613 },
6614 /* Incall Record Uplink BACK END DAI Link */
6615 {
6616 .name = LPASS_BE_INCALL_RECORD_TX,
6617 .stream_name = "Voice Uplink Capture",
6618 .cpu_dai_name = "msm-dai-q6-dev.32772",
6619 .platform_name = "msm-pcm-routing",
6620 .codec_name = "msm-stub-codec.1",
6621 .codec_dai_name = "msm-stub-tx",
6622 .no_pcm = 1,
6623 .dpcm_capture = 1,
6624 .id = MSM_BACKEND_DAI_INCALL_RECORD_TX,
6625 .be_hw_params_fixup = msm_be_hw_params_fixup,
6626 .ignore_suspend = 1,
6627 },
6628 /* Incall Record Downlink BACK END DAI Link */
6629 {
6630 .name = LPASS_BE_INCALL_RECORD_RX,
6631 .stream_name = "Voice Downlink Capture",
6632 .cpu_dai_name = "msm-dai-q6-dev.32771",
6633 .platform_name = "msm-pcm-routing",
6634 .codec_name = "msm-stub-codec.1",
6635 .codec_dai_name = "msm-stub-tx",
6636 .no_pcm = 1,
6637 .dpcm_capture = 1,
6638 .id = MSM_BACKEND_DAI_INCALL_RECORD_RX,
6639 .be_hw_params_fixup = msm_be_hw_params_fixup,
6640 .ignore_suspend = 1,
6641 },
6642 /* Incall Music BACK END DAI Link */
6643 {
6644 .name = LPASS_BE_VOICE_PLAYBACK_TX,
6645 .stream_name = "Voice Farend Playback",
6646 .cpu_dai_name = "msm-dai-q6-dev.32773",
6647 .platform_name = "msm-pcm-routing",
6648 .codec_name = "msm-stub-codec.1",
6649 .codec_dai_name = "msm-stub-rx",
6650 .no_pcm = 1,
6651 .dpcm_playback = 1,
6652 .id = MSM_BACKEND_DAI_VOICE_PLAYBACK_TX,
6653 .be_hw_params_fixup = msm_be_hw_params_fixup,
6654 .ignore_suspend = 1,
6655 .ignore_pmdown_time = 1,
6656 },
6657 /* Incall Music 2 BACK END DAI Link */
6658 {
6659 .name = LPASS_BE_VOICE2_PLAYBACK_TX,
6660 .stream_name = "Voice2 Farend Playback",
6661 .cpu_dai_name = "msm-dai-q6-dev.32770",
6662 .platform_name = "msm-pcm-routing",
6663 .codec_name = "msm-stub-codec.1",
6664 .codec_dai_name = "msm-stub-rx",
6665 .no_pcm = 1,
6666 .dpcm_playback = 1,
6667 .id = MSM_BACKEND_DAI_VOICE2_PLAYBACK_TX,
6668 .be_hw_params_fixup = msm_be_hw_params_fixup,
6669 .ignore_suspend = 1,
6670 .ignore_pmdown_time = 1,
6671 },
6672 {
6673 .name = LPASS_BE_USB_AUDIO_RX,
6674 .stream_name = "USB Audio Playback",
6675 .cpu_dai_name = "msm-dai-q6-dev.28672",
6676 .platform_name = "msm-pcm-routing",
6677 .codec_name = "msm-stub-codec.1",
6678 .codec_dai_name = "msm-stub-rx",
6679 .no_pcm = 1,
6680 .dpcm_playback = 1,
6681 .id = MSM_BACKEND_DAI_USB_RX,
6682 .be_hw_params_fixup = msm_be_hw_params_fixup,
6683 .ignore_pmdown_time = 1,
6684 .ignore_suspend = 1,
6685 },
6686 {
6687 .name = LPASS_BE_USB_AUDIO_TX,
6688 .stream_name = "USB Audio Capture",
6689 .cpu_dai_name = "msm-dai-q6-dev.28673",
6690 .platform_name = "msm-pcm-routing",
6691 .codec_name = "msm-stub-codec.1",
6692 .codec_dai_name = "msm-stub-tx",
6693 .no_pcm = 1,
6694 .dpcm_capture = 1,
6695 .id = MSM_BACKEND_DAI_USB_TX,
6696 .be_hw_params_fixup = msm_be_hw_params_fixup,
6697 .ignore_suspend = 1,
6698 },
6699 {
6700 .name = LPASS_BE_PRI_TDM_RX_0,
6701 .stream_name = "Primary TDM0 Playback",
6702 .cpu_dai_name = "msm-dai-q6-tdm.36864",
6703 .platform_name = "msm-pcm-routing",
6704 .codec_name = "msm-stub-codec.1",
6705 .codec_dai_name = "msm-stub-rx",
6706 .no_pcm = 1,
6707 .dpcm_playback = 1,
6708 .id = MSM_BACKEND_DAI_PRI_TDM_RX_0,
6709 .be_hw_params_fixup = msm_be_hw_params_fixup,
6710 .ops = &sm6150_tdm_be_ops,
6711 .ignore_suspend = 1,
6712 .ignore_pmdown_time = 1,
6713 },
6714 {
6715 .name = LPASS_BE_PRI_TDM_TX_0,
6716 .stream_name = "Primary TDM0 Capture",
6717 .cpu_dai_name = "msm-dai-q6-tdm.36865",
6718 .platform_name = "msm-pcm-routing",
6719 .codec_name = "msm-stub-codec.1",
6720 .codec_dai_name = "msm-stub-tx",
6721 .no_pcm = 1,
6722 .dpcm_capture = 1,
6723 .id = MSM_BACKEND_DAI_PRI_TDM_TX_0,
6724 .be_hw_params_fixup = msm_be_hw_params_fixup,
6725 .ops = &sm6150_tdm_be_ops,
6726 .ignore_suspend = 1,
6727 },
6728 {
6729 .name = LPASS_BE_SEC_TDM_RX_0,
6730 .stream_name = "Secondary TDM0 Playback",
6731 .cpu_dai_name = "msm-dai-q6-tdm.36880",
6732 .platform_name = "msm-pcm-routing",
6733 .codec_name = "msm-stub-codec.1",
6734 .codec_dai_name = "msm-stub-rx",
6735 .no_pcm = 1,
6736 .dpcm_playback = 1,
6737 .id = MSM_BACKEND_DAI_SEC_TDM_RX_0,
6738 .be_hw_params_fixup = msm_be_hw_params_fixup,
6739 .ops = &sm6150_tdm_be_ops,
6740 .ignore_suspend = 1,
6741 .ignore_pmdown_time = 1,
6742 },
6743 {
6744 .name = LPASS_BE_SEC_TDM_TX_0,
6745 .stream_name = "Secondary TDM0 Capture",
6746 .cpu_dai_name = "msm-dai-q6-tdm.36881",
6747 .platform_name = "msm-pcm-routing",
6748 .codec_name = "msm-stub-codec.1",
6749 .codec_dai_name = "msm-stub-tx",
6750 .no_pcm = 1,
6751 .dpcm_capture = 1,
6752 .id = MSM_BACKEND_DAI_SEC_TDM_TX_0,
6753 .be_hw_params_fixup = msm_be_hw_params_fixup,
6754 .ops = &sm6150_tdm_be_ops,
6755 .ignore_suspend = 1,
6756 },
6757 {
6758 .name = LPASS_BE_TERT_TDM_RX_0,
6759 .stream_name = "Tertiary TDM0 Playback",
6760 .cpu_dai_name = "msm-dai-q6-tdm.36896",
6761 .platform_name = "msm-pcm-routing",
6762 .codec_name = "msm-stub-codec.1",
6763 .codec_dai_name = "msm-stub-rx",
6764 .no_pcm = 1,
6765 .dpcm_playback = 1,
6766 .id = MSM_BACKEND_DAI_TERT_TDM_RX_0,
6767 .be_hw_params_fixup = msm_be_hw_params_fixup,
6768 .ops = &sm6150_tdm_be_ops,
6769 .ignore_suspend = 1,
6770 .ignore_pmdown_time = 1,
6771 },
6772 {
6773 .name = LPASS_BE_TERT_TDM_TX_0,
6774 .stream_name = "Tertiary TDM0 Capture",
6775 .cpu_dai_name = "msm-dai-q6-tdm.36897",
6776 .platform_name = "msm-pcm-routing",
6777 .codec_name = "msm-stub-codec.1",
6778 .codec_dai_name = "msm-stub-tx",
6779 .no_pcm = 1,
6780 .dpcm_capture = 1,
6781 .id = MSM_BACKEND_DAI_TERT_TDM_TX_0,
6782 .be_hw_params_fixup = msm_be_hw_params_fixup,
6783 .ops = &sm6150_tdm_be_ops,
6784 .ignore_suspend = 1,
6785 },
6786 {
6787 .name = LPASS_BE_QUAT_TDM_RX_0,
6788 .stream_name = "Quaternary TDM0 Playback",
6789 .cpu_dai_name = "msm-dai-q6-tdm.36912",
6790 .platform_name = "msm-pcm-routing",
6791 .codec_name = "msm-stub-codec.1",
6792 .codec_dai_name = "msm-stub-rx",
6793 .no_pcm = 1,
6794 .dpcm_playback = 1,
6795 .id = MSM_BACKEND_DAI_QUAT_TDM_RX_0,
6796 .be_hw_params_fixup = msm_tdm_be_hw_params_fixup,
6797 .ops = &sm6150_tdm_be_ops,
6798 .ignore_suspend = 1,
6799 .ignore_pmdown_time = 1,
6800 },
6801 {
6802 .name = LPASS_BE_QUAT_TDM_TX_0,
6803 .stream_name = "Quaternary TDM0 Capture",
6804 .cpu_dai_name = "msm-dai-q6-tdm.36913",
6805 .platform_name = "msm-pcm-routing",
6806 .codec_name = "msm-stub-codec.1",
6807 .codec_dai_name = "msm-stub-tx",
6808 .no_pcm = 1,
6809 .dpcm_capture = 1,
6810 .id = MSM_BACKEND_DAI_QUAT_TDM_TX_0,
6811 .be_hw_params_fixup = msm_be_hw_params_fixup,
6812 .ops = &sm6150_tdm_be_ops,
6813 .ignore_suspend = 1,
6814 },
6815};
6816
6817static struct snd_soc_dai_link msm_tavil_be_dai_links[] = {
6818 {
6819 .name = LPASS_BE_SLIMBUS_0_RX,
6820 .stream_name = "Slimbus Playback",
6821 .cpu_dai_name = "msm-dai-q6-dev.16384",
6822 .platform_name = "msm-pcm-routing",
6823 .codec_name = "tavil_codec",
6824 .codec_dai_name = "tavil_rx1",
6825 .no_pcm = 1,
6826 .dpcm_playback = 1,
6827 .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
6828 .init = &msm_audrx_tavil_init,
6829 .be_hw_params_fixup = msm_be_hw_params_fixup,
6830 /* this dainlink has playback support */
6831 .ignore_pmdown_time = 1,
6832 .ignore_suspend = 1,
6833 .ops = &msm_be_ops,
6834 },
6835 {
6836 .name = LPASS_BE_SLIMBUS_0_TX,
6837 .stream_name = "Slimbus Capture",
6838 .cpu_dai_name = "msm-dai-q6-dev.16385",
6839 .platform_name = "msm-pcm-routing",
6840 .codec_name = "tavil_codec",
6841 .codec_dai_name = "tavil_tx1",
6842 .no_pcm = 1,
6843 .dpcm_capture = 1,
6844 .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
6845 .be_hw_params_fixup = msm_be_hw_params_fixup,
6846 .ignore_suspend = 1,
6847 .ops = &msm_be_ops,
6848 },
6849 {
6850 .name = LPASS_BE_SLIMBUS_1_RX,
6851 .stream_name = "Slimbus1 Playback",
6852 .cpu_dai_name = "msm-dai-q6-dev.16386",
6853 .platform_name = "msm-pcm-routing",
6854 .codec_name = "tavil_codec",
6855 .codec_dai_name = "tavil_rx1",
6856 .no_pcm = 1,
6857 .dpcm_playback = 1,
6858 .id = MSM_BACKEND_DAI_SLIMBUS_1_RX,
6859 .be_hw_params_fixup = msm_be_hw_params_fixup,
6860 .ops = &msm_be_ops,
6861 /* dai link has playback support */
6862 .ignore_pmdown_time = 1,
6863 .ignore_suspend = 1,
6864 },
6865 {
6866 .name = LPASS_BE_SLIMBUS_1_TX,
6867 .stream_name = "Slimbus1 Capture",
6868 .cpu_dai_name = "msm-dai-q6-dev.16387",
6869 .platform_name = "msm-pcm-routing",
6870 .codec_name = "tavil_codec",
6871 .codec_dai_name = "tavil_tx3",
6872 .no_pcm = 1,
6873 .dpcm_capture = 1,
6874 .id = MSM_BACKEND_DAI_SLIMBUS_1_TX,
6875 .be_hw_params_fixup = msm_be_hw_params_fixup,
6876 .ops = &msm_be_ops,
6877 .ignore_suspend = 1,
6878 },
6879 {
6880 .name = LPASS_BE_SLIMBUS_2_RX,
6881 .stream_name = "Slimbus2 Playback",
6882 .cpu_dai_name = "msm-dai-q6-dev.16388",
6883 .platform_name = "msm-pcm-routing",
6884 .codec_name = "tavil_codec",
6885 .codec_dai_name = "tavil_rx2",
6886 .no_pcm = 1,
6887 .dpcm_playback = 1,
6888 .id = MSM_BACKEND_DAI_SLIMBUS_2_RX,
6889 .be_hw_params_fixup = msm_be_hw_params_fixup,
6890 .ops = &msm_be_ops,
6891 .ignore_pmdown_time = 1,
6892 .ignore_suspend = 1,
6893 },
6894 {
6895 .name = LPASS_BE_SLIMBUS_3_RX,
6896 .stream_name = "Slimbus3 Playback",
6897 .cpu_dai_name = "msm-dai-q6-dev.16390",
6898 .platform_name = "msm-pcm-routing",
6899 .codec_name = "tavil_codec",
6900 .codec_dai_name = "tavil_rx1",
6901 .no_pcm = 1,
6902 .dpcm_playback = 1,
6903 .id = MSM_BACKEND_DAI_SLIMBUS_3_RX,
6904 .be_hw_params_fixup = msm_be_hw_params_fixup,
6905 .ops = &msm_be_ops,
6906 /* dai link has playback support */
6907 .ignore_pmdown_time = 1,
6908 .ignore_suspend = 1,
6909 },
6910 {
6911 .name = LPASS_BE_SLIMBUS_3_TX,
6912 .stream_name = "Slimbus3 Capture",
6913 .cpu_dai_name = "msm-dai-q6-dev.16391",
6914 .platform_name = "msm-pcm-routing",
6915 .codec_name = "tavil_codec",
6916 .codec_dai_name = "tavil_tx1",
6917 .no_pcm = 1,
6918 .dpcm_capture = 1,
6919 .id = MSM_BACKEND_DAI_SLIMBUS_3_TX,
6920 .be_hw_params_fixup = msm_be_hw_params_fixup,
6921 .ops = &msm_be_ops,
6922 .ignore_suspend = 1,
6923 },
6924 {
6925 .name = LPASS_BE_SLIMBUS_4_RX,
6926 .stream_name = "Slimbus4 Playback",
6927 .cpu_dai_name = "msm-dai-q6-dev.16392",
6928 .platform_name = "msm-pcm-routing",
6929 .codec_name = "tavil_codec",
6930 .codec_dai_name = "tavil_rx1",
6931 .no_pcm = 1,
6932 .dpcm_playback = 1,
6933 .id = MSM_BACKEND_DAI_SLIMBUS_4_RX,
6934 .be_hw_params_fixup = msm_be_hw_params_fixup,
6935 .ops = &msm_be_ops,
6936 /* dai link has playback support */
6937 .ignore_pmdown_time = 1,
6938 .ignore_suspend = 1,
6939 },
6940 {
6941 .name = LPASS_BE_SLIMBUS_5_RX,
6942 .stream_name = "Slimbus5 Playback",
6943 .cpu_dai_name = "msm-dai-q6-dev.16394",
6944 .platform_name = "msm-pcm-routing",
6945 .codec_name = "tavil_codec",
6946 .codec_dai_name = "tavil_rx3",
6947 .no_pcm = 1,
6948 .dpcm_playback = 1,
6949 .id = MSM_BACKEND_DAI_SLIMBUS_5_RX,
6950 .be_hw_params_fixup = msm_be_hw_params_fixup,
6951 .ops = &msm_be_ops,
6952 /* dai link has playback support */
6953 .ignore_pmdown_time = 1,
6954 .ignore_suspend = 1,
6955 },
6956 /* MAD BE */
6957 {
6958 .name = LPASS_BE_SLIMBUS_5_TX,
6959 .stream_name = "Slimbus5 Capture",
6960 .cpu_dai_name = "msm-dai-q6-dev.16395",
6961 .platform_name = "msm-pcm-routing",
6962 .codec_name = "tavil_codec",
6963 .codec_dai_name = "tavil_mad1",
6964 .no_pcm = 1,
6965 .dpcm_capture = 1,
6966 .id = MSM_BACKEND_DAI_SLIMBUS_5_TX,
6967 .be_hw_params_fixup = msm_be_hw_params_fixup,
6968 .ops = &msm_be_ops,
6969 .ignore_suspend = 1,
6970 },
6971 {
6972 .name = LPASS_BE_SLIMBUS_6_RX,
6973 .stream_name = "Slimbus6 Playback",
6974 .cpu_dai_name = "msm-dai-q6-dev.16396",
6975 .platform_name = "msm-pcm-routing",
6976 .codec_name = "tavil_codec",
6977 .codec_dai_name = "tavil_rx4",
6978 .no_pcm = 1,
6979 .dpcm_playback = 1,
6980 .id = MSM_BACKEND_DAI_SLIMBUS_6_RX,
6981 .be_hw_params_fixup = msm_be_hw_params_fixup,
6982 .ops = &msm_be_ops,
6983 /* dai link has playback support */
6984 .ignore_pmdown_time = 1,
6985 .ignore_suspend = 1,
6986 },
6987 /* Slimbus VI Recording */
6988 {
6989 .name = LPASS_BE_SLIMBUS_TX_VI,
6990 .stream_name = "Slimbus4 Capture",
6991 .cpu_dai_name = "msm-dai-q6-dev.16393",
6992 .platform_name = "msm-pcm-routing",
6993 .codec_name = "tavil_codec",
6994 .codec_dai_name = "tavil_vifeedback",
6995 .id = MSM_BACKEND_DAI_SLIMBUS_4_TX,
6996 .be_hw_params_fixup = msm_be_hw_params_fixup,
6997 .ops = &msm_be_ops,
6998 .ignore_suspend = 1,
6999 .no_pcm = 1,
7000 .dpcm_capture = 1,
7001 },
7002};
7003
7004static struct snd_soc_dai_link msm_wcn_be_dai_links[] = {
7005 {
7006 .name = LPASS_BE_SLIMBUS_7_RX,
7007 .stream_name = "Slimbus7 Playback",
7008 .cpu_dai_name = "msm-dai-q6-dev.16398",
7009 .platform_name = "msm-pcm-routing",
7010 .codec_name = "btfmslim_slave",
7011 /* BT codec driver determines capabilities based on
7012 * dai name, bt codecdai name should always contains
7013 * supported usecase information
7014 */
7015 .codec_dai_name = "btfm_bt_sco_a2dp_slim_rx",
7016 .no_pcm = 1,
7017 .dpcm_playback = 1,
7018 .id = MSM_BACKEND_DAI_SLIMBUS_7_RX,
7019 .be_hw_params_fixup = msm_be_hw_params_fixup,
7020 .ops = &msm_wcn_ops,
7021 /* dai link has playback support */
7022 .ignore_pmdown_time = 1,
7023 .ignore_suspend = 1,
7024 },
7025 {
7026 .name = LPASS_BE_SLIMBUS_7_TX,
7027 .stream_name = "Slimbus7 Capture",
7028 .cpu_dai_name = "msm-dai-q6-dev.16399",
7029 .platform_name = "msm-pcm-routing",
7030 .codec_name = "btfmslim_slave",
7031 .codec_dai_name = "btfm_bt_sco_slim_tx",
7032 .no_pcm = 1,
7033 .dpcm_capture = 1,
7034 .id = MSM_BACKEND_DAI_SLIMBUS_7_TX,
7035 .be_hw_params_fixup = msm_be_hw_params_fixup,
7036 .ops = &msm_wcn_ops,
7037 .ignore_suspend = 1,
7038 },
7039 {
7040 .name = LPASS_BE_SLIMBUS_8_TX,
7041 .stream_name = "Slimbus8 Capture",
7042 .cpu_dai_name = "msm-dai-q6-dev.16401",
7043 .platform_name = "msm-pcm-routing",
7044 .codec_name = "btfmslim_slave",
7045 .codec_dai_name = "btfm_fm_slim_tx",
7046 .no_pcm = 1,
7047 .dpcm_capture = 1,
7048 .id = MSM_BACKEND_DAI_SLIMBUS_8_TX,
7049 .be_hw_params_fixup = msm_be_hw_params_fixup,
7050 .init = &msm_wcn_init,
7051 .ops = &msm_wcn_ops,
7052 .ignore_suspend = 1,
7053 },
7054};
7055
7056static struct snd_soc_dai_link ext_disp_be_dai_link[] = {
7057 /* DISP PORT BACK END DAI Link */
7058 {
7059 .name = LPASS_BE_DISPLAY_PORT,
7060 .stream_name = "Display Port Playback",
7061 .cpu_dai_name = "msm-dai-q6-dp.24608",
7062 .platform_name = "msm-pcm-routing",
7063 .codec_name = "msm-ext-disp-audio-codec-rx",
7064 .codec_dai_name = "msm_dp_audio_codec_rx_dai",
7065 .no_pcm = 1,
7066 .dpcm_playback = 1,
7067 .id = MSM_BACKEND_DAI_DISPLAY_PORT_RX,
7068 .be_hw_params_fixup = msm_be_hw_params_fixup,
7069 .ignore_pmdown_time = 1,
7070 .ignore_suspend = 1,
7071 },
7072};
7073
7074static struct snd_soc_dai_link msm_mi2s_be_dai_links[] = {
7075 {
7076 .name = LPASS_BE_PRI_MI2S_RX,
7077 .stream_name = "Primary MI2S Playback",
7078 .cpu_dai_name = "msm-dai-q6-mi2s.0",
7079 .platform_name = "msm-pcm-routing",
7080 .codec_name = "msm-stub-codec.1",
7081 .codec_dai_name = "msm-stub-rx",
7082 .no_pcm = 1,
7083 .dpcm_playback = 1,
7084 .id = MSM_BACKEND_DAI_PRI_MI2S_RX,
7085 .be_hw_params_fixup = msm_be_hw_params_fixup,
7086 .ops = &msm_mi2s_be_ops,
7087 .ignore_suspend = 1,
7088 .ignore_pmdown_time = 1,
7089 },
7090 {
7091 .name = LPASS_BE_PRI_MI2S_TX,
7092 .stream_name = "Primary MI2S Capture",
7093 .cpu_dai_name = "msm-dai-q6-mi2s.0",
7094 .platform_name = "msm-pcm-routing",
7095 .codec_name = "msm-stub-codec.1",
7096 .codec_dai_name = "msm-stub-tx",
7097 .no_pcm = 1,
7098 .dpcm_capture = 1,
7099 .id = MSM_BACKEND_DAI_PRI_MI2S_TX,
7100 .be_hw_params_fixup = msm_be_hw_params_fixup,
7101 .ops = &msm_mi2s_be_ops,
7102 .ignore_suspend = 1,
7103 },
7104 {
7105 .name = LPASS_BE_SEC_MI2S_RX,
7106 .stream_name = "Secondary MI2S Playback",
7107 .cpu_dai_name = "msm-dai-q6-mi2s.1",
7108 .platform_name = "msm-pcm-routing",
7109 .codec_name = "msm-stub-codec.1",
7110 .codec_dai_name = "msm-stub-rx",
7111 .no_pcm = 1,
7112 .dpcm_playback = 1,
7113 .id = MSM_BACKEND_DAI_SECONDARY_MI2S_RX,
7114 .be_hw_params_fixup = msm_be_hw_params_fixup,
7115 .ops = &msm_mi2s_be_ops,
7116 .ignore_suspend = 1,
7117 .ignore_pmdown_time = 1,
7118 },
7119 {
7120 .name = LPASS_BE_SEC_MI2S_TX,
7121 .stream_name = "Secondary MI2S Capture",
7122 .cpu_dai_name = "msm-dai-q6-mi2s.1",
7123 .platform_name = "msm-pcm-routing",
7124 .codec_name = "msm-stub-codec.1",
7125 .codec_dai_name = "msm-stub-tx",
7126 .no_pcm = 1,
7127 .dpcm_capture = 1,
7128 .id = MSM_BACKEND_DAI_SECONDARY_MI2S_TX,
7129 .be_hw_params_fixup = msm_be_hw_params_fixup,
7130 .ops = &msm_mi2s_be_ops,
7131 .ignore_suspend = 1,
7132 },
7133 {
7134 .name = LPASS_BE_TERT_MI2S_RX,
7135 .stream_name = "Tertiary MI2S Playback",
7136 .cpu_dai_name = "msm-dai-q6-mi2s.2",
7137 .platform_name = "msm-pcm-routing",
7138 .codec_name = "msm-stub-codec.1",
7139 .codec_dai_name = "msm-stub-rx",
7140 .no_pcm = 1,
7141 .dpcm_playback = 1,
7142 .id = MSM_BACKEND_DAI_TERTIARY_MI2S_RX,
7143 .be_hw_params_fixup = msm_be_hw_params_fixup,
7144 .ops = &msm_mi2s_be_ops,
7145 .ignore_suspend = 1,
7146 .ignore_pmdown_time = 1,
7147 },
7148 {
7149 .name = LPASS_BE_TERT_MI2S_TX,
7150 .stream_name = "Tertiary MI2S Capture",
7151 .cpu_dai_name = "msm-dai-q6-mi2s.2",
7152 .platform_name = "msm-pcm-routing",
7153 .codec_name = "msm-stub-codec.1",
7154 .codec_dai_name = "msm-stub-tx",
7155 .no_pcm = 1,
7156 .dpcm_capture = 1,
7157 .id = MSM_BACKEND_DAI_TERTIARY_MI2S_TX,
7158 .be_hw_params_fixup = msm_be_hw_params_fixup,
7159 .ops = &msm_mi2s_be_ops,
7160 .ignore_suspend = 1,
7161 },
7162 {
7163 .name = LPASS_BE_QUAT_MI2S_RX,
7164 .stream_name = "Quaternary MI2S Playback",
7165 .cpu_dai_name = "msm-dai-q6-mi2s.3",
7166 .platform_name = "msm-pcm-routing",
7167 .codec_name = "msm-stub-codec.1",
7168 .codec_dai_name = "msm-stub-rx",
7169 .no_pcm = 1,
7170 .dpcm_playback = 1,
7171 .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_RX,
7172 .be_hw_params_fixup = msm_be_hw_params_fixup,
7173 .ops = &msm_mi2s_be_ops,
7174 .ignore_suspend = 1,
7175 .ignore_pmdown_time = 1,
7176 },
7177 {
7178 .name = LPASS_BE_QUAT_MI2S_TX,
7179 .stream_name = "Quaternary MI2S Capture",
7180 .cpu_dai_name = "msm-dai-q6-mi2s.3",
7181 .platform_name = "msm-pcm-routing",
7182 .codec_name = "msm-stub-codec.1",
7183 .codec_dai_name = "msm-stub-tx",
7184 .no_pcm = 1,
7185 .dpcm_capture = 1,
7186 .id = MSM_BACKEND_DAI_QUATERNARY_MI2S_TX,
7187 .be_hw_params_fixup = msm_be_hw_params_fixup,
7188 .ops = &msm_mi2s_be_ops,
7189 .ignore_suspend = 1,
7190 },
7191 {
7192 .name = LPASS_BE_QUIN_MI2S_RX,
7193 .stream_name = "Quinary MI2S Playback",
7194 .cpu_dai_name = "msm-dai-q6-mi2s.4",
7195 .platform_name = "msm-pcm-routing",
7196 .codec_name = "msm-stub-codec.1",
7197 .codec_dai_name = "msm-stub-rx",
7198 .no_pcm = 1,
7199 .dpcm_playback = 1,
7200 .id = MSM_BACKEND_DAI_QUINARY_MI2S_RX,
7201 .be_hw_params_fixup = msm_be_hw_params_fixup,
7202 .ops = &msm_mi2s_be_ops,
7203 .ignore_suspend = 1,
7204 .ignore_pmdown_time = 1,
7205 },
7206 {
7207 .name = LPASS_BE_QUIN_MI2S_TX,
7208 .stream_name = "Quinary MI2S Capture",
7209 .cpu_dai_name = "msm-dai-q6-mi2s.4",
7210 .platform_name = "msm-pcm-routing",
7211 .codec_name = "msm-stub-codec.1",
7212 .codec_dai_name = "msm-stub-tx",
7213 .no_pcm = 1,
7214 .dpcm_capture = 1,
7215 .id = MSM_BACKEND_DAI_QUINARY_MI2S_TX,
7216 .be_hw_params_fixup = msm_be_hw_params_fixup,
7217 .ops = &msm_mi2s_be_ops,
7218 .ignore_suspend = 1,
7219 },
7220
7221};
7222
7223static struct snd_soc_dai_link msm_auxpcm_be_dai_links[] = {
7224 /* Primary AUX PCM Backend DAI Links */
7225 {
7226 .name = LPASS_BE_AUXPCM_RX,
7227 .stream_name = "AUX PCM Playback",
7228 .cpu_dai_name = "msm-dai-q6-auxpcm.1",
7229 .platform_name = "msm-pcm-routing",
7230 .codec_name = "msm-stub-codec.1",
7231 .codec_dai_name = "msm-stub-rx",
7232 .no_pcm = 1,
7233 .dpcm_playback = 1,
7234 .id = MSM_BACKEND_DAI_AUXPCM_RX,
7235 .be_hw_params_fixup = msm_be_hw_params_fixup,
7236 .ignore_pmdown_time = 1,
7237 .ignore_suspend = 1,
7238 },
7239 {
7240 .name = LPASS_BE_AUXPCM_TX,
7241 .stream_name = "AUX PCM Capture",
7242 .cpu_dai_name = "msm-dai-q6-auxpcm.1",
7243 .platform_name = "msm-pcm-routing",
7244 .codec_name = "msm-stub-codec.1",
7245 .codec_dai_name = "msm-stub-tx",
7246 .no_pcm = 1,
7247 .dpcm_capture = 1,
7248 .id = MSM_BACKEND_DAI_AUXPCM_TX,
7249 .be_hw_params_fixup = msm_be_hw_params_fixup,
7250 .ignore_suspend = 1,
7251 },
7252 /* Secondary AUX PCM Backend DAI Links */
7253 {
7254 .name = LPASS_BE_SEC_AUXPCM_RX,
7255 .stream_name = "Sec AUX PCM Playback",
7256 .cpu_dai_name = "msm-dai-q6-auxpcm.2",
7257 .platform_name = "msm-pcm-routing",
7258 .codec_name = "msm-stub-codec.1",
7259 .codec_dai_name = "msm-stub-rx",
7260 .no_pcm = 1,
7261 .dpcm_playback = 1,
7262 .id = MSM_BACKEND_DAI_SEC_AUXPCM_RX,
7263 .be_hw_params_fixup = msm_be_hw_params_fixup,
7264 .ignore_pmdown_time = 1,
7265 .ignore_suspend = 1,
7266 },
7267 {
7268 .name = LPASS_BE_SEC_AUXPCM_TX,
7269 .stream_name = "Sec AUX PCM Capture",
7270 .cpu_dai_name = "msm-dai-q6-auxpcm.2",
7271 .platform_name = "msm-pcm-routing",
7272 .codec_name = "msm-stub-codec.1",
7273 .codec_dai_name = "msm-stub-tx",
7274 .no_pcm = 1,
7275 .dpcm_capture = 1,
7276 .id = MSM_BACKEND_DAI_SEC_AUXPCM_TX,
7277 .be_hw_params_fixup = msm_be_hw_params_fixup,
7278 .ignore_suspend = 1,
7279 },
7280 /* Tertiary AUX PCM Backend DAI Links */
7281 {
7282 .name = LPASS_BE_TERT_AUXPCM_RX,
7283 .stream_name = "Tert AUX PCM Playback",
7284 .cpu_dai_name = "msm-dai-q6-auxpcm.3",
7285 .platform_name = "msm-pcm-routing",
7286 .codec_name = "msm-stub-codec.1",
7287 .codec_dai_name = "msm-stub-rx",
7288 .no_pcm = 1,
7289 .dpcm_playback = 1,
7290 .id = MSM_BACKEND_DAI_TERT_AUXPCM_RX,
7291 .be_hw_params_fixup = msm_be_hw_params_fixup,
7292 .ignore_suspend = 1,
7293 },
7294 {
7295 .name = LPASS_BE_TERT_AUXPCM_TX,
7296 .stream_name = "Tert AUX PCM Capture",
7297 .cpu_dai_name = "msm-dai-q6-auxpcm.3",
7298 .platform_name = "msm-pcm-routing",
7299 .codec_name = "msm-stub-codec.1",
7300 .codec_dai_name = "msm-stub-tx",
7301 .no_pcm = 1,
7302 .dpcm_capture = 1,
7303 .id = MSM_BACKEND_DAI_TERT_AUXPCM_TX,
7304 .be_hw_params_fixup = msm_be_hw_params_fixup,
7305 .ignore_suspend = 1,
7306 },
7307 /* Quaternary AUX PCM Backend DAI Links */
7308 {
7309 .name = LPASS_BE_QUAT_AUXPCM_RX,
7310 .stream_name = "Quat AUX PCM Playback",
7311 .cpu_dai_name = "msm-dai-q6-auxpcm.4",
7312 .platform_name = "msm-pcm-routing",
7313 .codec_name = "msm-stub-codec.1",
7314 .codec_dai_name = "msm-stub-rx",
7315 .no_pcm = 1,
7316 .dpcm_playback = 1,
7317 .id = MSM_BACKEND_DAI_QUAT_AUXPCM_RX,
7318 .be_hw_params_fixup = msm_be_hw_params_fixup,
7319 .ignore_pmdown_time = 1,
7320 .ignore_suspend = 1,
7321 },
7322 {
7323 .name = LPASS_BE_QUAT_AUXPCM_TX,
7324 .stream_name = "Quat AUX PCM Capture",
7325 .cpu_dai_name = "msm-dai-q6-auxpcm.4",
7326 .platform_name = "msm-pcm-routing",
7327 .codec_name = "msm-stub-codec.1",
7328 .codec_dai_name = "msm-stub-tx",
7329 .no_pcm = 1,
7330 .dpcm_capture = 1,
7331 .id = MSM_BACKEND_DAI_QUAT_AUXPCM_TX,
7332 .be_hw_params_fixup = msm_be_hw_params_fixup,
7333 .ignore_suspend = 1,
7334 },
7335 /* Quinary AUX PCM Backend DAI Links */
7336 {
7337 .name = LPASS_BE_QUIN_AUXPCM_RX,
7338 .stream_name = "Quin AUX PCM Playback",
7339 .cpu_dai_name = "msm-dai-q6-auxpcm.5",
7340 .platform_name = "msm-pcm-routing",
7341 .codec_name = "msm-stub-codec.1",
7342 .codec_dai_name = "msm-stub-rx",
7343 .no_pcm = 1,
7344 .dpcm_playback = 1,
7345 .id = MSM_BACKEND_DAI_QUIN_AUXPCM_RX,
7346 .be_hw_params_fixup = msm_be_hw_params_fixup,
7347 .ignore_pmdown_time = 1,
7348 .ignore_suspend = 1,
7349 },
7350 {
7351 .name = LPASS_BE_QUIN_AUXPCM_TX,
7352 .stream_name = "Quin AUX PCM Capture",
7353 .cpu_dai_name = "msm-dai-q6-auxpcm.5",
7354 .platform_name = "msm-pcm-routing",
7355 .codec_name = "msm-stub-codec.1",
7356 .codec_dai_name = "msm-stub-tx",
7357 .no_pcm = 1,
7358 .dpcm_capture = 1,
7359 .id = MSM_BACKEND_DAI_QUIN_AUXPCM_TX,
7360 .be_hw_params_fixup = msm_be_hw_params_fixup,
7361 .ignore_suspend = 1,
7362 },
7363};
7364
7365static struct snd_soc_dai_link msm_wsa_cdc_dma_be_dai_links[] = {
7366 /* WSA CDC DMA Backend DAI Links */
7367 {
7368 .name = LPASS_BE_WSA_CDC_DMA_RX_0,
7369 .stream_name = "WSA CDC DMA0 Playback",
7370 .cpu_dai_name = "msm-dai-cdc-dma-dev.45056",
7371 .platform_name = "msm-pcm-routing",
7372 .codec_name = "bolero_codec",
7373 .codec_dai_name = "wsa_macro_rx1",
7374 .no_pcm = 1,
7375 .dpcm_playback = 1,
7376 .init = &msm_int_audrx_init,
7377 .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_0,
7378 .be_hw_params_fixup = msm_be_hw_params_fixup,
7379 .ignore_pmdown_time = 1,
7380 .ignore_suspend = 1,
7381 .ops = &msm_cdc_dma_be_ops,
7382 },
7383 {
7384 .name = LPASS_BE_WSA_CDC_DMA_RX_1,
7385 .stream_name = "WSA CDC DMA1 Playback",
7386 .cpu_dai_name = "msm-dai-cdc-dma-dev.45058",
7387 .platform_name = "msm-pcm-routing",
7388 .codec_name = "bolero_codec",
7389 .codec_dai_name = "wsa_macro_rx_mix",
7390 .no_pcm = 1,
7391 .dpcm_playback = 1,
7392 .id = MSM_BACKEND_DAI_WSA_CDC_DMA_RX_1,
7393 .be_hw_params_fixup = msm_be_hw_params_fixup,
7394 .ignore_pmdown_time = 1,
7395 .ignore_suspend = 1,
7396 .ops = &msm_cdc_dma_be_ops,
7397 },
7398 {
7399 .name = LPASS_BE_WSA_CDC_DMA_TX_1,
7400 .stream_name = "WSA CDC DMA1 Capture",
7401 .cpu_dai_name = "msm-dai-cdc-dma-dev.45059",
7402 .platform_name = "msm-pcm-routing",
7403 .codec_name = "bolero_codec",
7404 .codec_dai_name = "wsa_macro_echo",
7405 .no_pcm = 1,
7406 .dpcm_capture = 1,
7407 .id = MSM_BACKEND_DAI_WSA_CDC_DMA_TX_1,
7408 .be_hw_params_fixup = msm_be_hw_params_fixup,
7409 .ignore_suspend = 1,
7410 .ops = &msm_cdc_dma_be_ops,
7411 },
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7412};
7413
7414static struct snd_soc_dai_link msm_rx_tx_cdc_dma_be_dai_links[] = {
7415 /* RX CDC DMA Backend DAI Links */
7416 {
7417 .name = LPASS_BE_RX_CDC_DMA_RX_0,
7418 .stream_name = "RX CDC DMA0 Playback",
Ramprasad Katkamf83acfb2018-08-11 23:28:57 +0530[diff] [blame]7419 .cpu_dai_name = "msm-dai-cdc-dma-dev.45104",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7420 .platform_name = "msm-pcm-routing",
7421 .codec_name = "bolero_codec",
7422 .codec_dai_name = "rx_macro_rx1",
7423 .no_pcm = 1,
7424 .dpcm_playback = 1,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7425 .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_0,
7426 .be_hw_params_fixup = msm_be_hw_params_fixup,
7427 .ignore_pmdown_time = 1,
7428 .ignore_suspend = 1,
7429 .ops = &msm_cdc_dma_be_ops,
7430 },
7431 {
7432 .name = LPASS_BE_RX_CDC_DMA_RX_1,
7433 .stream_name = "RX CDC DMA1 Playback",
Ramprasad Katkamf83acfb2018-08-11 23:28:57 +0530[diff] [blame]7434 .cpu_dai_name = "msm-dai-cdc-dma-dev.45106",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7435 .platform_name = "msm-pcm-routing",
7436 .codec_name = "bolero_codec",
7437 .codec_dai_name = "rx_macro_rx2",
7438 .no_pcm = 1,
7439 .dpcm_playback = 1,
7440 .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_1,
7441 .be_hw_params_fixup = msm_be_hw_params_fixup,
7442 .ignore_pmdown_time = 1,
7443 .ignore_suspend = 1,
7444 .ops = &msm_cdc_dma_be_ops,
7445 },
7446 {
7447 .name = LPASS_BE_RX_CDC_DMA_RX_2,
7448 .stream_name = "RX CDC DMA2 Playback",
Ramprasad Katkamf83acfb2018-08-11 23:28:57 +0530[diff] [blame]7449 .cpu_dai_name = "msm-dai-cdc-dma-dev.45108",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7450 .platform_name = "msm-pcm-routing",
7451 .codec_name = "bolero_codec",
7452 .codec_dai_name = "rx_macro_rx3",
7453 .no_pcm = 1,
7454 .dpcm_playback = 1,
7455 .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_2,
7456 .be_hw_params_fixup = msm_be_hw_params_fixup,
7457 .ignore_pmdown_time = 1,
7458 .ignore_suspend = 1,
7459 .ops = &msm_cdc_dma_be_ops,
7460 },
7461 {
7462 .name = LPASS_BE_RX_CDC_DMA_RX_3,
7463 .stream_name = "RX CDC DMA3 Playback",
Ramprasad Katkamf83acfb2018-08-11 23:28:57 +0530[diff] [blame]7464 .cpu_dai_name = "msm-dai-cdc-dma-dev.45110",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7465 .platform_name = "msm-pcm-routing",
7466 .codec_name = "bolero_codec",
7467 .codec_dai_name = "rx_macro_rx4",
7468 .no_pcm = 1,
7469 .dpcm_playback = 1,
7470 .id = MSM_BACKEND_DAI_RX_CDC_DMA_RX_3,
7471 .be_hw_params_fixup = msm_be_hw_params_fixup,
7472 .ignore_pmdown_time = 1,
7473 .ignore_suspend = 1,
7474 .ops = &msm_cdc_dma_be_ops,
7475 },
7476 /* TX CDC DMA Backend DAI Links */
7477 {
7478 .name = LPASS_BE_TX_CDC_DMA_TX_3,
7479 .stream_name = "TX CDC DMA3 Capture",
Ramprasad Katkamf83acfb2018-08-11 23:28:57 +0530[diff] [blame]7480 .cpu_dai_name = "msm-dai-cdc-dma-dev.45111",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7481 .platform_name = "msm-pcm-routing",
7482 .codec_name = "bolero_codec",
7483 .codec_dai_name = "tx_macro_tx1",
7484 .no_pcm = 1,
7485 .dpcm_capture = 1,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7486 .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_3,
7487 .be_hw_params_fixup = msm_be_hw_params_fixup,
7488 .ignore_suspend = 1,
7489 .ops = &msm_cdc_dma_be_ops,
7490 },
7491 {
7492 .name = LPASS_BE_TX_CDC_DMA_TX_4,
7493 .stream_name = "TX CDC DMA4 Capture",
Ramprasad Katkamf83acfb2018-08-11 23:28:57 +0530[diff] [blame]7494 .cpu_dai_name = "msm-dai-cdc-dma-dev.45113",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7495 .platform_name = "msm-pcm-routing",
7496 .codec_name = "bolero_codec",
7497 .codec_dai_name = "tx_macro_tx2",
7498 .no_pcm = 1,
7499 .dpcm_capture = 1,
7500 .id = MSM_BACKEND_DAI_TX_CDC_DMA_TX_4,
7501 .be_hw_params_fixup = msm_be_hw_params_fixup,
7502 .ignore_suspend = 1,
7503 .ops = &msm_cdc_dma_be_ops,
7504 },
7505};
7506
7507static struct snd_soc_dai_link msm_sm6150_dai_links[
7508 ARRAY_SIZE(msm_common_dai_links) +
7509 ARRAY_SIZE(msm_tavil_fe_dai_links) +
7510 ARRAY_SIZE(msm_bolero_fe_dai_links) +
7511 ARRAY_SIZE(msm_common_misc_fe_dai_links) +
7512 ARRAY_SIZE(msm_common_be_dai_links) +
7513 ARRAY_SIZE(msm_tavil_be_dai_links) +
7514 ARRAY_SIZE(msm_wcn_be_dai_links) +
7515 ARRAY_SIZE(ext_disp_be_dai_link) +
7516 ARRAY_SIZE(msm_mi2s_be_dai_links) +
7517 ARRAY_SIZE(msm_auxpcm_be_dai_links) +
7518 ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links) +
7519 ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links)];
7520
7521static int msm_snd_card_tavil_late_probe(struct snd_soc_card *card)
7522{
7523 const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
7524 struct snd_soc_pcm_runtime *rtd;
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]7525 struct snd_soc_component *component;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7526 int ret = 0;
7527 void *mbhc_calibration;
7528
7529 rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
7530 if (!rtd) {
7531 dev_err(card->dev,
7532 "%s: snd_soc_get_pcm_runtime for %s failed!\n",
7533 __func__, be_dl_name);
7534 ret = -EINVAL;
7535 goto err_pcm_runtime;
7536 }
7537
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]7538 component = snd_soc_rtdcom_lookup(rtd, "tavil_codec");
7539 if (!component) {
7540 pr_err("%s: component is NULL\n", __func__);
7541 ret = -EINVAL;
7542 goto err_pcm_runtime;
7543 }
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7544 mbhc_calibration = def_wcd_mbhc_cal();
7545 if (!mbhc_calibration) {
7546 ret = -ENOMEM;
7547 goto err_mbhc_cal;
7548 }
7549 wcd_mbhc_cfg.calibration = mbhc_calibration;
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]7550 ret = tavil_mbhc_hs_detect(component, &wcd_mbhc_cfg);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7551 if (ret) {
7552 dev_err(card->dev, "%s: mbhc hs detect failed, err:%d\n",
7553 __func__, ret);
7554 goto err_hs_detect;
7555 }
7556 return 0;
7557
7558err_hs_detect:
7559 kfree(mbhc_calibration);
7560err_mbhc_cal:
7561err_pcm_runtime:
7562 return ret;
7563}
7564
7565
7566static int msm_populate_dai_link_component_of_node(
7567 struct snd_soc_card *card)
7568{
7569 int i, index, ret = 0;
7570 struct device *cdev = card->dev;
7571 struct snd_soc_dai_link *dai_link = card->dai_link;
7572 struct device_node *np;
7573
7574 if (!cdev) {
7575 pr_err("%s: Sound card device memory NULL\n", __func__);
7576 return -ENODEV;
7577 }
7578
7579 for (i = 0; i < card->num_links; i++) {
7580 if (dai_link[i].platform_of_node && dai_link[i].cpu_of_node)
7581 continue;
7582
7583 /* populate platform_of_node for snd card dai links */
7584 if (dai_link[i].platform_name &&
7585 !dai_link[i].platform_of_node) {
7586 index = of_property_match_string(cdev->of_node,
7587 "asoc-platform-names",
7588 dai_link[i].platform_name);
7589 if (index < 0) {
7590 pr_err("%s: No match found for platform name: %s\n",
7591 __func__, dai_link[i].platform_name);
7592 ret = index;
7593 goto err;
7594 }
7595 np = of_parse_phandle(cdev->of_node, "asoc-platform",
7596 index);
7597 if (!np) {
7598 pr_err("%s: retrieving phandle for platform %s, index %d failed\n",
7599 __func__, dai_link[i].platform_name,
7600 index);
7601 ret = -ENODEV;
7602 goto err;
7603 }
7604 dai_link[i].platform_of_node = np;
7605 dai_link[i].platform_name = NULL;
7606 }
7607
7608 /* populate cpu_of_node for snd card dai links */
7609 if (dai_link[i].cpu_dai_name && !dai_link[i].cpu_of_node) {
7610 index = of_property_match_string(cdev->of_node,
7611 "asoc-cpu-names",
7612 dai_link[i].cpu_dai_name);
7613 if (index >= 0) {
7614 np = of_parse_phandle(cdev->of_node, "asoc-cpu",
7615 index);
7616 if (!np) {
7617 pr_err("%s: retrieving phandle for cpu dai %s failed\n",
7618 __func__,
7619 dai_link[i].cpu_dai_name);
7620 ret = -ENODEV;
7621 goto err;
7622 }
7623 dai_link[i].cpu_of_node = np;
7624 dai_link[i].cpu_dai_name = NULL;
7625 }
7626 }
7627
7628 /* populate codec_of_node for snd card dai links */
7629 if (dai_link[i].codec_name && !dai_link[i].codec_of_node) {
7630 index = of_property_match_string(cdev->of_node,
7631 "asoc-codec-names",
7632 dai_link[i].codec_name);
7633 if (index < 0)
7634 continue;
7635 np = of_parse_phandle(cdev->of_node, "asoc-codec",
7636 index);
7637 if (!np) {
7638 pr_err("%s: retrieving phandle for codec %s failed\n",
7639 __func__, dai_link[i].codec_name);
7640 ret = -ENODEV;
7641 goto err;
7642 }
7643 dai_link[i].codec_of_node = np;
7644 dai_link[i].codec_name = NULL;
7645 }
7646 }
7647
7648err:
7649 return ret;
7650}
7651
7652static int msm_audrx_stub_init(struct snd_soc_pcm_runtime *rtd)
7653{
7654 int ret = 0;
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]7655 struct snd_soc_component *component =
7656 snd_soc_rtdcom_lookup(rtd, "msm-stub-codec");
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7657
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]7658 ret = snd_soc_add_component_controls(component, msm_tavil_snd_controls,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7659 ARRAY_SIZE(msm_tavil_snd_controls));
7660 if (ret < 0) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]7661 dev_err(component->dev,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7662 "%s: add_codec_controls failed, err = %d\n",
7663 __func__, ret);
7664 return ret;
7665 }
7666
7667 return 0;
7668}
7669
7670static int msm_snd_stub_hw_params(struct snd_pcm_substream *substream,
7671 struct snd_pcm_hw_params *params)
7672{
7673 struct snd_soc_pcm_runtime *rtd = substream->private_data;
7674 struct snd_soc_dai *cpu_dai = rtd->cpu_dai;
7675
7676 int ret = 0;
7677 unsigned int rx_ch[] = {144, 145, 146, 147, 148, 149, 150,
7678 151};
7679 unsigned int tx_ch[] = {128, 129, 130, 131, 132, 133,
7680 134, 135, 136, 137, 138, 139,
7681 140, 141, 142, 143};
7682
7683 if (substream->stream == SNDRV_PCM_STREAM_PLAYBACK) {
7684 ret = snd_soc_dai_set_channel_map(cpu_dai, 0, 0,
7685 slim_rx_cfg[SLIM_RX_0].channels,
7686 rx_ch);
7687 if (ret < 0)
7688 pr_err("%s: RX failed to set cpu chan map error %d\n",
7689 __func__, ret);
7690 } else {
7691 ret = snd_soc_dai_set_channel_map(cpu_dai,
7692 slim_tx_cfg[SLIM_TX_0].channels,
7693 tx_ch, 0, 0);
7694 if (ret < 0)
7695 pr_err("%s: TX failed to set cpu chan map error %d\n",
7696 __func__, ret);
7697 }
7698
7699 return ret;
7700}
7701
7702static struct snd_soc_ops msm_stub_be_ops = {
7703 .hw_params = msm_snd_stub_hw_params,
7704};
7705
7706static struct snd_soc_dai_link msm_stub_fe_dai_links[] = {
7707
7708 /* FrontEnd DAI Links */
7709 {
7710 .name = "MSMSTUB Media1",
7711 .stream_name = "MultiMedia1",
7712 .cpu_dai_name = "MultiMedia1",
7713 .platform_name = "msm-pcm-dsp.0",
7714 .dynamic = 1,
7715 .async_ops = ASYNC_DPCM_SND_SOC_PREPARE,
7716 .dpcm_playback = 1,
7717 .dpcm_capture = 1,
7718 .trigger = {SND_SOC_DPCM_TRIGGER_POST,
7719 SND_SOC_DPCM_TRIGGER_POST},
7720 .codec_dai_name = "snd-soc-dummy-dai",
7721 .codec_name = "snd-soc-dummy",
7722 .ignore_suspend = 1,
7723 /* this dainlink has playback support */
7724 .ignore_pmdown_time = 1,
7725 .id = MSM_FRONTEND_DAI_MULTIMEDIA1
7726 },
7727};
7728
7729static struct snd_soc_dai_link msm_stub_be_dai_links[] = {
7730
7731 /* Backend DAI Links */
7732 {
7733 .name = LPASS_BE_SLIMBUS_0_RX,
7734 .stream_name = "Slimbus Playback",
7735 .cpu_dai_name = "msm-dai-q6-dev.16384",
7736 .platform_name = "msm-pcm-routing",
7737 .codec_name = "msm-stub-codec.1",
7738 .codec_dai_name = "msm-stub-rx",
7739 .no_pcm = 1,
7740 .dpcm_playback = 1,
7741 .id = MSM_BACKEND_DAI_SLIMBUS_0_RX,
7742 .init = &msm_audrx_stub_init,
7743 .be_hw_params_fixup = msm_be_hw_params_fixup,
7744 .ignore_pmdown_time = 1, /* dai link has playback support */
7745 .ignore_suspend = 1,
7746 .ops = &msm_stub_be_ops,
7747 },
7748 {
7749 .name = LPASS_BE_SLIMBUS_0_TX,
7750 .stream_name = "Slimbus Capture",
7751 .cpu_dai_name = "msm-dai-q6-dev.16385",
7752 .platform_name = "msm-pcm-routing",
7753 .codec_name = "msm-stub-codec.1",
7754 .codec_dai_name = "msm-stub-tx",
7755 .no_pcm = 1,
7756 .dpcm_capture = 1,
7757 .id = MSM_BACKEND_DAI_SLIMBUS_0_TX,
7758 .be_hw_params_fixup = msm_be_hw_params_fixup,
7759 .ignore_suspend = 1,
7760 .ops = &msm_stub_be_ops,
7761 },
7762};
7763
7764static struct snd_soc_dai_link msm_stub_dai_links[
7765 ARRAY_SIZE(msm_stub_fe_dai_links) +
7766 ARRAY_SIZE(msm_stub_be_dai_links)];
7767
7768struct snd_soc_card snd_soc_card_stub_msm = {
7769 .name = "sm6150-stub-snd-card",
7770};
7771
7772static const struct of_device_id sm6150_asoc_machine_of_match[] = {
7773 { .compatible = "qcom,sm6150-asoc-snd",
7774 .data = "codec"},
7775 { .compatible = "qcom,sm6150-asoc-snd-stub",
7776 .data = "stub_codec"},
7777 {},
7778};
7779
7780static struct snd_soc_card *populate_snd_card_dailinks(struct device *dev)
7781{
7782 struct snd_soc_card *card = NULL;
7783 struct snd_soc_dai_link *dailink;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7784 int total_links = 0, rc = 0;
7785 u32 tavil_codec = 0, auxpcm_audio_intf = 0;
7786 u32 mi2s_audio_intf = 0, ext_disp_audio_intf = 0;
7787 u32 wcn_btfm_intf = 0;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7788 const struct of_device_id *match;
7789
7790 match = of_match_node(sm6150_asoc_machine_of_match, dev->of_node);
7791 if (!match) {
7792 dev_err(dev, "%s: No DT match found for sound card\n",
7793 __func__);
7794 return NULL;
7795 }
7796
7797 if (!strcmp(match->data, "codec")) {
7798 card = &snd_soc_card_sm6150_msm;
7799 memcpy(msm_sm6150_dai_links + total_links,
7800 msm_common_dai_links,
7801 sizeof(msm_common_dai_links));
7802
7803 total_links += ARRAY_SIZE(msm_common_dai_links);
7804
7805 memcpy(msm_sm6150_dai_links + total_links,
7806 msm_common_misc_fe_dai_links,
7807 sizeof(msm_common_misc_fe_dai_links));
7808
7809 total_links += ARRAY_SIZE(msm_common_misc_fe_dai_links);
7810
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7811 rc = of_property_read_u32(dev->of_node, "qcom,tavil_codec",
7812 &tavil_codec);
7813 if (rc) {
7814 dev_dbg(dev, "%s: No DT match for tavil codec\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7815 __func__);
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7816 } else {
7817 if (tavil_codec) {
7818 card->late_probe =
7819 msm_snd_card_tavil_late_probe;
7820 memcpy(msm_sm6150_dai_links + total_links,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7821 msm_tavil_fe_dai_links,
7822 sizeof(msm_tavil_fe_dai_links));
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7823 total_links +=
7824 ARRAY_SIZE(msm_tavil_fe_dai_links);
7825 }
7826 }
7827
7828 if (!tavil_codec) {
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7829 memcpy(msm_sm6150_dai_links + total_links,
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7830 msm_bolero_fe_dai_links,
7831 sizeof(msm_bolero_fe_dai_links));
7832 total_links +=
7833 ARRAY_SIZE(msm_bolero_fe_dai_links);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7834 }
7835
7836 memcpy(msm_sm6150_dai_links + total_links,
7837 msm_common_be_dai_links,
7838 sizeof(msm_common_be_dai_links));
7839
7840 total_links += ARRAY_SIZE(msm_common_be_dai_links);
7841
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7842 if (tavil_codec) {
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7843 memcpy(msm_sm6150_dai_links + total_links,
7844 msm_tavil_be_dai_links,
7845 sizeof(msm_tavil_be_dai_links));
7846 total_links += ARRAY_SIZE(msm_tavil_be_dai_links);
7847 } else {
7848 memcpy(msm_sm6150_dai_links + total_links,
7849 msm_wsa_cdc_dma_be_dai_links,
7850 sizeof(msm_wsa_cdc_dma_be_dai_links));
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7851 total_links +=
7852 ARRAY_SIZE(msm_wsa_cdc_dma_be_dai_links);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7853
7854 memcpy(msm_sm6150_dai_links + total_links,
7855 msm_rx_tx_cdc_dma_be_dai_links,
7856 sizeof(msm_rx_tx_cdc_dma_be_dai_links));
7857 total_links +=
7858 ARRAY_SIZE(msm_rx_tx_cdc_dma_be_dai_links);
7859 }
7860
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7861 rc = of_property_read_u32(dev->of_node,
7862 "qcom,ext-disp-audio-rx",
7863 &ext_disp_audio_intf);
7864 if (rc) {
7865 dev_dbg(dev, "%s: No DT match Ext Disp interface\n",
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7866 __func__);
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7867 } else {
Rohit kumare5a1d4f2018-09-17 11:36:25 +0530[diff] [blame]7868 if (ext_disp_audio_intf) {
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7869 memcpy(msm_sm6150_dai_links + total_links,
7870 ext_disp_be_dai_link,
7871 sizeof(ext_disp_be_dai_link));
7872 total_links +=
7873 ARRAY_SIZE(ext_disp_be_dai_link);
7874 }
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7875 }
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7876
7877 rc = of_property_read_u32(dev->of_node, "qcom,mi2s-audio-intf",
7878 &mi2s_audio_intf);
7879 if (rc) {
7880 dev_dbg(dev, "%s: No DT match MI2S audio interface\n",
7881 __func__);
7882 } else {
7883 if (mi2s_audio_intf) {
7884 memcpy(msm_sm6150_dai_links + total_links,
7885 msm_mi2s_be_dai_links,
7886 sizeof(msm_mi2s_be_dai_links));
7887 total_links +=
7888 ARRAY_SIZE(msm_mi2s_be_dai_links);
7889 }
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7890 }
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7891
7892
7893 rc = of_property_read_u32(dev->of_node, "qcom,wcn-btfm",
7894 &wcn_btfm_intf);
7895 if (rc) {
7896 dev_dbg(dev, "%s: No DT match wcn btfm interface\n",
7897 __func__);
7898 } else {
7899 if (wcn_btfm_intf) {
7900 memcpy(msm_sm6150_dai_links + total_links,
7901 msm_wcn_be_dai_links,
7902 sizeof(msm_wcn_be_dai_links));
7903 total_links +=
7904 ARRAY_SIZE(msm_wcn_be_dai_links);
7905 }
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7906 }
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7907
7908 rc = of_property_read_u32(dev->of_node,
7909 "qcom,auxpcm-audio-intf",
7910 &auxpcm_audio_intf);
7911 if (rc) {
7912 dev_dbg(dev, "%s: No DT match Aux PCM interface\n",
7913 __func__);
7914 } else {
7915 if (auxpcm_audio_intf) {
7916 memcpy(msm_sm6150_dai_links + total_links,
7917 msm_auxpcm_be_dai_links,
7918 sizeof(msm_auxpcm_be_dai_links));
7919 total_links +=
7920 ARRAY_SIZE(msm_auxpcm_be_dai_links);
7921 }
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7922 }
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]7923
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7924 dailink = msm_sm6150_dai_links;
7925 } else if (!strcmp(match->data, "stub_codec")) {
7926 card = &snd_soc_card_stub_msm;
7927
7928 memcpy(msm_stub_dai_links + total_links,
7929 msm_stub_fe_dai_links,
7930 sizeof(msm_stub_fe_dai_links));
7931 total_links += ARRAY_SIZE(msm_stub_fe_dai_links);
7932
7933 memcpy(msm_stub_dai_links + total_links,
7934 msm_stub_be_dai_links,
7935 sizeof(msm_stub_be_dai_links));
7936 total_links += ARRAY_SIZE(msm_stub_be_dai_links);
7937
7938 dailink = msm_stub_dai_links;
7939 }
7940
7941 if (card) {
7942 card->dai_link = dailink;
7943 card->num_links = total_links;
7944 }
7945
7946 return card;
7947}
7948
7949static int msm_wsa881x_init(struct snd_soc_component *component)
7950{
7951 u8 spkleft_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
7952 u8 spkright_ports[WSA881X_MAX_SWR_PORTS] = {0, 1, 2, 3};
7953 u8 spkleft_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_L, SPKR_L_COMP,
7954 SPKR_L_BOOST, SPKR_L_VI};
7955 u8 spkright_port_types[WSA881X_MAX_SWR_PORTS] = {SPKR_R, SPKR_R_COMP,
7956 SPKR_R_BOOST, SPKR_R_VI};
7957 unsigned int ch_rate[WSA881X_MAX_SWR_PORTS] = {2400, 600, 300, 1200};
7958 unsigned int ch_mask[WSA881X_MAX_SWR_PORTS] = {0x1, 0xF, 0x3, 0x3};
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7959 struct msm_asoc_mach_data *pdata;
7960 struct snd_soc_dapm_context *dapm;
Aditya Bavanari4ae32fc2018-08-13 13:08:34 +0530[diff] [blame]7961 struct snd_card *card = component->card->snd_card;
7962 struct snd_info_entry *entry;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7963 int ret = 0;
7964
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]7965 if (!component) {
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7966 pr_err("%s codec is NULL\n", __func__);
7967 return -EINVAL;
7968 }
7969
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]7970 dapm = snd_soc_component_get_dapm(component);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7971
7972 if (!strcmp(component->name_prefix, "SpkrLeft")) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]7973 dev_dbg(component->dev, "%s: setting left ch map to codec %s\n",
7974 __func__, component->name);
7975 wsa881x_set_channel_map(component, &spkleft_ports[0],
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7976 WSA881X_MAX_SWR_PORTS, &ch_mask[0],
7977 &ch_rate[0], &spkleft_port_types[0]);
7978 if (dapm->component) {
7979 snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft IN");
7980 snd_soc_dapm_ignore_suspend(dapm, "SpkrLeft SPKR");
7981 }
7982 } else if (!strcmp(component->name_prefix, "SpkrRight")) {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]7983 dev_dbg(component->dev, "%s: setting right ch map to codec %s\n",
7984 __func__, component->name);
7985 wsa881x_set_channel_map(component, &spkright_ports[0],
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7986 WSA881X_MAX_SWR_PORTS, &ch_mask[0],
7987 &ch_rate[0], &spkright_port_types[0]);
7988 if (dapm->component) {
7989 snd_soc_dapm_ignore_suspend(dapm, "SpkrRight IN");
7990 snd_soc_dapm_ignore_suspend(dapm, "SpkrRight SPKR");
7991 }
7992 } else {
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]7993 dev_err(component->dev, "%s: wrong codec name %s\n", __func__,
7994 component->name);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]7995 ret = -EINVAL;
7996 goto err;
7997 }
7998 pdata = snd_soc_card_get_drvdata(component->card);
Aditya Bavanari4ae32fc2018-08-13 13:08:34 +0530[diff] [blame]7999 if (!pdata->codec_root) {
8000 entry = snd_info_create_subdir(card->module, "codecs",
8001 card->proc_root);
8002 if (!entry) {
8003 pr_err("%s: Cannot create codecs module entry\n",
8004 __func__);
8005 ret = 0;
8006 goto err;
8007 }
8008 pdata->codec_root = entry;
8009 }
8010 wsa881x_codec_info_create_codec_entry(pdata->codec_root,
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]8011 component);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8012err:
8013 return ret;
8014}
8015
8016static int msm_aux_codec_init(struct snd_soc_component *component)
8017{
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]8018 struct snd_soc_dapm_context *dapm = snd_soc_component_get_dapm(component);
Ramprasad Katkam997da402018-08-17 20:20:06 +0530[diff] [blame]8019 int ret = 0;
8020 void *mbhc_calibration;
Aditya Bavanari4ae32fc2018-08-13 13:08:34 +0530[diff] [blame]8021 struct snd_info_entry *entry;
8022 struct snd_card *card = component->card->snd_card;
8023 struct msm_asoc_mach_data *pdata;
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]8024
8025 snd_soc_dapm_ignore_suspend(dapm, "EAR");
8026 snd_soc_dapm_ignore_suspend(dapm, "AUX");
8027 snd_soc_dapm_ignore_suspend(dapm, "HPHL");
8028 snd_soc_dapm_ignore_suspend(dapm, "HPHR");
8029 snd_soc_dapm_ignore_suspend(dapm, "AMIC1");
8030 snd_soc_dapm_ignore_suspend(dapm, "AMIC2");
8031 snd_soc_dapm_ignore_suspend(dapm, "AMIC3");
8032 snd_soc_dapm_ignore_suspend(dapm, "AMIC4");
8033 snd_soc_dapm_sync(dapm);
8034
Aditya Bavanari4ae32fc2018-08-13 13:08:34 +0530[diff] [blame]8035 pdata = snd_soc_card_get_drvdata(component->card);
8036 if (!pdata->codec_root) {
8037 entry = snd_info_create_subdir(card->module, "codecs",
8038 card->proc_root);
8039 if (!entry) {
8040 pr_err("%s: Cannot create codecs module entry\n",
8041 __func__);
8042 ret = 0;
8043 goto codec_root_err;
8044 }
8045 pdata->codec_root = entry;
8046 }
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]8047 wcd937x_info_create_codec_entry(pdata->codec_root, component);
Aditya Bavanari4ae32fc2018-08-13 13:08:34 +0530[diff] [blame]8048codec_root_err:
Ramprasad Katkam997da402018-08-17 20:20:06 +0530[diff] [blame]8049 mbhc_calibration = def_wcd_mbhc_cal();
8050 if (!mbhc_calibration) {
8051 return -ENOMEM;
8052 }
8053 wcd_mbhc_cfg.calibration = mbhc_calibration;
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]8054 ret = wcd937x_mbhc_hs_detect(component, &wcd_mbhc_cfg);
Ramprasad Katkam997da402018-08-17 20:20:06 +0530[diff] [blame]8055
8056 return ret;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8057}
8058
8059static int msm_init_aux_dev(struct platform_device *pdev,
8060 struct snd_soc_card *card)
8061{
8062 struct device_node *wsa_of_node;
8063 struct device_node *aux_codec_of_node;
8064 u32 wsa_max_devs;
8065 u32 wsa_dev_cnt;
Aditya Bavanariec279c72018-11-22 15:52:25 +0530[diff] [blame^]8066 u32 codec_max_aux_devs;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8067 u32 codec_aux_dev_cnt = 0;
8068 int i;
Md Mansoor Ahmed2382aaa2018-11-20 11:06:32 +0530[diff] [blame]8069 struct msm_wsa881x_dev_info *wsa881x_dev_info = NULL;
8070 struct aux_codec_dev_info *aux_cdc_dev_info = NULL;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8071 const char *auxdev_name_prefix[1];
8072 char *dev_name_str = NULL;
8073 int found = 0;
8074 int codecs_found = 0;
8075 int ret = 0;
8076
8077 /* Get maximum WSA device count for this platform */
8078 ret = of_property_read_u32(pdev->dev.of_node,
8079 "qcom,wsa-max-devs", &wsa_max_devs);
8080 if (ret) {
Aditya Bavanariec279c72018-11-22 15:52:25 +0530[diff] [blame^]8081 dev_err(&pdev->dev,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8082 "%s: wsa-max-devs property missing in DT %s, ret = %d\n",
8083 __func__, pdev->dev.of_node->full_name, ret);
8084 wsa_max_devs = 0;
8085 goto codec_aux_dev;
8086 }
8087 if (wsa_max_devs == 0) {
Aditya Bavanariec279c72018-11-22 15:52:25 +0530[diff] [blame^]8088 dev_dbg(&pdev->dev,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8089 "%s: Max WSA devices is 0 for this target?\n",
8090 __func__);
8091 goto codec_aux_dev;
8092 }
8093
8094 /* Get count of WSA device phandles for this platform */
8095 wsa_dev_cnt = of_count_phandle_with_args(pdev->dev.of_node,
8096 "qcom,wsa-devs", NULL);
8097 if (wsa_dev_cnt == -ENOENT) {
8098 dev_warn(&pdev->dev, "%s: No wsa device defined in DT.\n",
8099 __func__);
8100 goto err;
8101 } else if (wsa_dev_cnt <= 0) {
8102 dev_err(&pdev->dev,
8103 "%s: Error reading wsa device from DT. wsa_dev_cnt = %d\n",
8104 __func__, wsa_dev_cnt);
8105 ret = -EINVAL;
8106 goto err;
8107 }
8108
8109 /*
8110 * Expect total phandles count to be NOT less than maximum possible
8111 * WSA count. However, if it is less, then assign same value to
8112 * max count as well.
8113 */
8114 if (wsa_dev_cnt < wsa_max_devs) {
8115 dev_dbg(&pdev->dev,
8116 "%s: wsa_max_devs = %d cannot exceed wsa_dev_cnt = %d\n",
8117 __func__, wsa_max_devs, wsa_dev_cnt);
8118 wsa_max_devs = wsa_dev_cnt;
8119 }
8120
8121 /* Make sure prefix string passed for each WSA device */
8122 ret = of_property_count_strings(pdev->dev.of_node,
8123 "qcom,wsa-aux-dev-prefix");
8124 if (ret != wsa_dev_cnt) {
8125 dev_err(&pdev->dev,
8126 "%s: expecting %d wsa prefix. Defined only %d in DT\n",
8127 __func__, wsa_dev_cnt, ret);
8128 ret = -EINVAL;
8129 goto err;
8130 }
8131
8132 /*
8133 * Alloc mem to store phandle and index info of WSA device, if already
8134 * registered with ALSA core
8135 */
8136 wsa881x_dev_info = devm_kcalloc(&pdev->dev, wsa_max_devs,
8137 sizeof(struct msm_wsa881x_dev_info),
8138 GFP_KERNEL);
8139 if (!wsa881x_dev_info) {
8140 ret = -ENOMEM;
8141 goto err;
8142 }
8143
8144 /*
8145 * search and check whether all WSA devices are already
8146 * registered with ALSA core or not. If found a node, store
8147 * the node and the index in a local array of struct for later
8148 * use.
8149 */
8150 for (i = 0; i < wsa_dev_cnt; i++) {
8151 wsa_of_node = of_parse_phandle(pdev->dev.of_node,
8152 "qcom,wsa-devs", i);
8153 if (unlikely(!wsa_of_node)) {
8154 /* we should not be here */
8155 dev_err(&pdev->dev,
8156 "%s: wsa dev node is not present\n",
8157 __func__);
8158 ret = -EINVAL;
8159 goto err;
8160 }
8161 if (soc_find_component(wsa_of_node, NULL)) {
8162 /* WSA device registered with ALSA core */
8163 wsa881x_dev_info[found].of_node = wsa_of_node;
8164 wsa881x_dev_info[found].index = i;
8165 found++;
8166 if (found == wsa_max_devs)
8167 break;
8168 }
8169 }
8170
8171 if (found < wsa_max_devs) {
8172 dev_dbg(&pdev->dev,
8173 "%s: failed to find %d components. Found only %d\n",
8174 __func__, wsa_max_devs, found);
8175 return -EPROBE_DEFER;
8176 }
8177 dev_info(&pdev->dev,
8178 "%s: found %d wsa881x devices registered with ALSA core\n",
8179 __func__, found);
8180
8181codec_aux_dev:
8182 if (strcmp(card->name, "sm6150-tavil-snd-card")) {
Aditya Bavanariec279c72018-11-22 15:52:25 +0530[diff] [blame^]8183 /* Get maximum aux codec device count for this platform */
8184 ret = of_property_read_u32(pdev->dev.of_node,
8185 "qcom,codec-max-aux-devs",
8186 &codec_max_aux_devs);
8187 if (ret) {
8188 dev_err(&pdev->dev,
8189 "%s: codec-max-aux-devs property missing in DT %s, ret = %d\n",
8190 __func__, pdev->dev.of_node->full_name, ret);
8191 codec_max_aux_devs = 0;
8192 goto aux_dev_register;
8193 }
8194 if (codec_max_aux_devs == 0) {
8195 dev_dbg(&pdev->dev,
8196 "%s: Max aux codec devices is 0 for this target?\n",
8197 __func__);
8198 goto aux_dev_register;
8199 }
8200
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8201 /* Get count of aux codec device phandles for this platform */
8202 codec_aux_dev_cnt = of_count_phandle_with_args(
8203 pdev->dev.of_node,
8204 "qcom,codec-aux-devs", NULL);
8205 if (codec_aux_dev_cnt == -ENOENT) {
8206 dev_warn(&pdev->dev, "%s: No aux codec defined in DT.\n",
8207 __func__);
8208 goto err;
8209 } else if (codec_aux_dev_cnt <= 0) {
8210 dev_err(&pdev->dev,
8211 "%s: Error reading aux codec device from DT, dev_cnt=%d\n",
8212 __func__, codec_aux_dev_cnt);
8213 ret = -EINVAL;
8214 goto err;
8215 }
8216
8217 /*
Aditya Bavanariec279c72018-11-22 15:52:25 +0530[diff] [blame^]8218 * Expect total phandles count to be NOT less than maximum possible
8219 * AUX device count. However, if it is less, then assign same value to
8220 * max count as well.
8221 */
8222 if (codec_aux_dev_cnt < codec_max_aux_devs) {
8223 dev_dbg(&pdev->dev,
8224 "%s: codec_max_aux_devs = %d cannot exceed codec_aux_dev_cnt = %d\n",
8225 __func__, codec_max_aux_devs,
8226 codec_aux_dev_cnt);
8227 codec_max_aux_devs = codec_aux_dev_cnt;
8228 }
8229
8230 /*
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8231 * Alloc mem to store phandle and index info of aux codec
8232 * if already registered with ALSA core
8233 */
Aditya Bavanariec279c72018-11-22 15:52:25 +0530[diff] [blame^]8234 aux_cdc_dev_info = devm_kcalloc(&pdev->dev, codec_max_aux_devs,
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8235 sizeof(struct aux_codec_dev_info),
8236 GFP_KERNEL);
8237 if (!aux_cdc_dev_info) {
8238 ret = -ENOMEM;
8239 goto err;
8240 }
8241
8242 /*
8243 * search and check whether all aux codecs are already
8244 * registered with ALSA core or not. If found a node, store
8245 * the node and the index in a local array of struct for later
8246 * use.
8247 */
8248 for (i = 0; i < codec_aux_dev_cnt; i++) {
8249 aux_codec_of_node = of_parse_phandle(pdev->dev.of_node,
8250 "qcom,codec-aux-devs", i);
8251 if (unlikely(!aux_codec_of_node)) {
8252 /* we should not be here */
8253 dev_err(&pdev->dev,
8254 "%s: aux codec dev node is not present\n",
8255 __func__);
8256 ret = -EINVAL;
8257 goto err;
8258 }
8259 if (soc_find_component(aux_codec_of_node, NULL)) {
8260 /* AUX codec registered with ALSA core */
8261 aux_cdc_dev_info[codecs_found].of_node =
8262 aux_codec_of_node;
8263 aux_cdc_dev_info[codecs_found].index = i;
8264 codecs_found++;
8265 }
8266 }
8267
Aditya Bavanariec279c72018-11-22 15:52:25 +0530[diff] [blame^]8268 if (codecs_found < codec_max_aux_devs) {
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8269 dev_dbg(&pdev->dev,
8270 "%s: failed to find %d components. Found only %d\n",
Aditya Bavanariec279c72018-11-22 15:52:25 +0530[diff] [blame^]8271 __func__, codec_max_aux_devs, codecs_found);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8272 return -EPROBE_DEFER;
8273 }
8274 dev_info(&pdev->dev,
8275 "%s: found %d AUX codecs registered with ALSA core\n",
8276 __func__, codecs_found);
8277
8278 }
8279
Aditya Bavanariec279c72018-11-22 15:52:25 +0530[diff] [blame^]8280aux_dev_register:
8281 card->num_aux_devs = wsa_max_devs + codec_max_aux_devs;
8282 card->num_configs = wsa_max_devs + codec_max_aux_devs;
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8283
8284 /* Alloc array of AUX devs struct */
8285 msm_aux_dev = devm_kcalloc(&pdev->dev, card->num_aux_devs,
8286 sizeof(struct snd_soc_aux_dev),
8287 GFP_KERNEL);
8288 if (!msm_aux_dev) {
8289 ret = -ENOMEM;
8290 goto err;
8291 }
8292
8293 /* Alloc array of codec conf struct */
8294 msm_codec_conf = devm_kcalloc(&pdev->dev, card->num_configs,
8295 sizeof(struct snd_soc_codec_conf),
8296 GFP_KERNEL);
8297 if (!msm_codec_conf) {
8298 ret = -ENOMEM;
8299 goto err;
8300 }
8301
8302 for (i = 0; i < wsa_max_devs; i++) {
8303 dev_name_str = devm_kzalloc(&pdev->dev, DEV_NAME_STR_LEN,
8304 GFP_KERNEL);
8305 if (!dev_name_str) {
8306 ret = -ENOMEM;
8307 goto err;
8308 }
8309
8310 ret = of_property_read_string_index(pdev->dev.of_node,
8311 "qcom,wsa-aux-dev-prefix",
8312 wsa881x_dev_info[i].index,
8313 auxdev_name_prefix);
8314 if (ret) {
8315 dev_err(&pdev->dev,
8316 "%s: failed to read wsa aux dev prefix, ret = %d\n",
8317 __func__, ret);
8318 ret = -EINVAL;
8319 goto err;
8320 }
8321
8322 snprintf(dev_name_str, strlen("wsa881x.%d"), "wsa881x.%d", i);
8323 msm_aux_dev[i].name = dev_name_str;
8324 msm_aux_dev[i].codec_name = NULL;
8325 msm_aux_dev[i].codec_of_node =
8326 wsa881x_dev_info[i].of_node;
8327 msm_aux_dev[i].init = msm_wsa881x_init;
8328 msm_codec_conf[i].dev_name = NULL;
8329 msm_codec_conf[i].name_prefix = auxdev_name_prefix[0];
8330 msm_codec_conf[i].of_node =
8331 wsa881x_dev_info[i].of_node;
8332 }
8333
8334 for (i = 0; i < codec_aux_dev_cnt; i++) {
Aditya Bavanariec279c72018-11-22 15:52:25 +0530[diff] [blame^]8335 msm_aux_dev[wsa_max_devs + i].name = "aux_codec";
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8336 msm_aux_dev[wsa_max_devs + i].codec_name = NULL;
8337 msm_aux_dev[wsa_max_devs + i].codec_of_node =
8338 aux_cdc_dev_info[i].of_node;
8339 msm_aux_dev[wsa_max_devs + i].init = msm_aux_codec_init;
8340 msm_codec_conf[wsa_max_devs + i].dev_name = NULL;
8341 msm_codec_conf[wsa_max_devs + i].name_prefix =
8342 NULL;
8343 msm_codec_conf[wsa_max_devs + i].of_node =
8344 aux_cdc_dev_info[i].of_node;
8345 }
8346
8347 card->codec_conf = msm_codec_conf;
8348 card->aux_dev = msm_aux_dev;
8349err:
8350 return ret;
8351}
8352
8353static void msm_i2s_auxpcm_init(struct platform_device *pdev)
8354{
8355 int count;
8356 u32 mi2s_master_slave[MI2S_MAX];
8357 int ret;
8358
8359 for (count = 0; count < MI2S_MAX; count++) {
8360 mutex_init(&mi2s_intf_conf[count].lock);
8361 mi2s_intf_conf[count].ref_cnt = 0;
8362 }
8363
8364 ret = of_property_read_u32_array(pdev->dev.of_node,
8365 "qcom,msm-mi2s-master",
8366 mi2s_master_slave, MI2S_MAX);
8367 if (ret) {
8368 dev_dbg(&pdev->dev, "%s: no qcom,msm-mi2s-master in DT node\n",
8369 __func__);
8370 } else {
8371 for (count = 0; count < MI2S_MAX; count++) {
8372 mi2s_intf_conf[count].msm_is_mi2s_master =
8373 mi2s_master_slave[count];
8374 }
8375 }
8376}
8377
8378static void msm_i2s_auxpcm_deinit(void)
8379{
8380 int count;
8381
8382 for (count = 0; count < MI2S_MAX; count++) {
8383 mutex_destroy(&mi2s_intf_conf[count].lock);
8384 mi2s_intf_conf[count].ref_cnt = 0;
8385 mi2s_intf_conf[count].msm_is_mi2s_master = 0;
8386 }
8387}
Vaishnavi Kommaraju9a3d5eb2018-09-19 18:16:39 +0530[diff] [blame]8388
8389static int sm6150_ssr_enable(struct device *dev, void *data)
8390{
8391 struct platform_device *pdev = to_platform_device(dev);
8392 struct snd_soc_card *card = platform_get_drvdata(pdev);
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]8393 struct msm_asoc_mach_data *pdata = NULL;
8394 struct snd_soc_component *component = NULL;
Vaishnavi Kommaraju9a3d5eb2018-09-19 18:16:39 +0530[diff] [blame]8395 int ret = 0;
8396
8397 if (!card) {
8398 dev_err(dev, "%s: card is NULL\n", __func__);
8399 ret = -EINVAL;
8400 goto err;
8401 }
8402
8403 if (!strcmp(card->name, "sm6150-tavil-snd-card")) {
8404 pdata = snd_soc_card_get_drvdata(card);
8405 if (!pdata->is_afe_config_done) {
8406 const char *be_dl_name = LPASS_BE_SLIMBUS_0_RX;
8407 struct snd_soc_pcm_runtime *rtd;
8408
8409 rtd = snd_soc_get_pcm_runtime(card, be_dl_name);
8410 if (!rtd) {
8411 dev_err(dev,
8412 "%s: snd_soc_get_pcm_runtime for %s failed!\n",
8413 __func__, be_dl_name);
8414 ret = -EINVAL;
8415 goto err;
8416 }
Meng Wang56a0f8f2018-09-06 18:17:30 +0800[diff] [blame]8417 component = snd_soc_rtdcom_lookup(rtd, "tavil_codec");
8418 if (!component) {
8419 dev_err(dev, "%s: component is NULL\n",
8420 __func__);
8421 ret = -EINVAL;
8422 goto err;
8423 }
8424 ret = msm_afe_set_config(component);
Vaishnavi Kommaraju9a3d5eb2018-09-19 18:16:39 +0530[diff] [blame]8425 if (ret)
8426 dev_err(dev, "%s: Failed to set AFE config. err %d\n",
8427 __func__, ret);
8428 else
8429 pdata->is_afe_config_done = true;
8430 }
8431 }
8432 snd_soc_card_change_online_state(card, 1);
8433 dev_dbg(dev, "%s: setting snd_card to ONLINE\n", __func__);
8434
8435err:
8436 return ret;
8437}
8438
8439static void sm6150_ssr_disable(struct device *dev, void *data)
8440{
8441 struct platform_device *pdev = to_platform_device(dev);
8442 struct snd_soc_card *card = platform_get_drvdata(pdev);
8443 struct msm_asoc_mach_data *pdata;
8444
8445 if (!card) {
8446 dev_err(dev, "%s: card is NULL\n", __func__);
8447 return;
8448 }
8449
8450 dev_dbg(dev, "%s: setting snd_card to OFFLINE\n", __func__);
8451 snd_soc_card_change_online_state(card, 0);
8452
8453 if (!strcmp(card->name, "sm6150-tavil-snd-card")) {
8454 pdata = snd_soc_card_get_drvdata(card);
8455 msm_afe_clear_config();
8456 pdata->is_afe_config_done = false;
8457 }
8458}
8459
8460static const struct snd_event_ops sm6150_ssr_ops = {
8461 .enable = sm6150_ssr_enable,
8462 .disable = sm6150_ssr_disable,
8463};
8464
8465static int msm_audio_ssr_compare(struct device *dev, void *data)
8466{
8467 struct device_node *node = data;
8468
8469 dev_dbg(dev, "%s: dev->of_node = 0x%p, node = 0x%p\n",
8470 __func__, dev->of_node, node);
8471 return (dev->of_node && dev->of_node == node);
8472}
8473
8474static int msm_audio_ssr_register(struct device *dev)
8475{
8476 struct device_node *np = dev->of_node;
8477 struct snd_event_clients *ssr_clients = NULL;
8478 struct device_node *node;
8479 int ret;
8480 int i;
8481
8482 for (i = 0; ; i++) {
8483 node = of_parse_phandle(np, "qcom,msm_audio_ssr_devs", i);
8484 if (!node)
8485 break;
8486 snd_event_mstr_add_client(&ssr_clients,
8487 msm_audio_ssr_compare, node);
8488 }
8489
8490 ret = snd_event_master_register(dev, &sm6150_ssr_ops,
8491 ssr_clients, NULL);
8492 if (!ret)
8493 snd_event_notify(dev, SND_EVENT_UP);
8494
8495 return ret;
8496}
8497
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8498static int msm_asoc_machine_probe(struct platform_device *pdev)
8499{
8500 struct snd_soc_card *card;
8501 struct msm_asoc_mach_data *pdata;
8502 const char *mbhc_audio_jack_type = NULL;
8503 int ret;
8504
8505 if (!pdev->dev.of_node) {
8506 dev_err(&pdev->dev, "No platform supplied from device tree\n");
8507 return -EINVAL;
8508 }
8509
8510 pdata = devm_kzalloc(&pdev->dev,
8511 sizeof(struct msm_asoc_mach_data), GFP_KERNEL);
8512 if (!pdata)
8513 return -ENOMEM;
8514
8515 card = populate_snd_card_dailinks(&pdev->dev);
8516 if (!card) {
8517 dev_err(&pdev->dev, "%s: Card uninitialized\n", __func__);
8518 ret = -EINVAL;
8519 goto err;
8520 }
8521 card->dev = &pdev->dev;
8522 platform_set_drvdata(pdev, card);
8523 snd_soc_card_set_drvdata(card, pdata);
8524
8525 ret = snd_soc_of_parse_card_name(card, "qcom,model");
8526 if (ret) {
8527 dev_err(&pdev->dev, "parse card name failed, err:%d\n",
8528 ret);
8529 goto err;
8530 }
8531
8532 ret = snd_soc_of_parse_audio_routing(card, "qcom,audio-routing");
8533 if (ret) {
8534 dev_err(&pdev->dev, "parse audio routing failed, err:%d\n",
8535 ret);
8536 goto err;
8537 }
8538
8539 ret = msm_populate_dai_link_component_of_node(card);
8540 if (ret) {
8541 ret = -EPROBE_DEFER;
8542 goto err;
8543 }
8544
8545 ret = msm_init_aux_dev(pdev, card);
8546 if (ret)
8547 goto err;
8548
8549 ret = devm_snd_soc_register_card(&pdev->dev, card);
8550 if (ret == -EPROBE_DEFER) {
8551 if (codec_reg_done)
8552 ret = -EINVAL;
8553 goto err;
8554 } else if (ret) {
8555 dev_err(&pdev->dev, "snd_soc_register_card failed (%d)\n",
8556 ret);
8557 goto err;
8558 }
8559 dev_info(&pdev->dev, "Sound card %s registered\n", card->name);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8560
8561 pdata->hph_en1_gpio_p = of_parse_phandle(pdev->dev.of_node,
8562 "qcom,hph-en1-gpio", 0);
8563 if (!pdata->hph_en1_gpio_p) {
8564 dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
8565 "qcom,hph-en1-gpio",
8566 pdev->dev.of_node->full_name);
8567 }
8568
8569 pdata->hph_en0_gpio_p = of_parse_phandle(pdev->dev.of_node,
8570 "qcom,hph-en0-gpio", 0);
8571 if (!pdata->hph_en0_gpio_p) {
8572 dev_dbg(&pdev->dev, "property %s not detected in node %s\n",
8573 "qcom,hph-en0-gpio",
8574 pdev->dev.of_node->full_name);
8575 }
8576
8577 ret = of_property_read_string(pdev->dev.of_node,
8578 "qcom,mbhc-audio-jack-type", &mbhc_audio_jack_type);
8579 if (ret) {
8580 dev_dbg(&pdev->dev, "Looking up %s property in node %s failed\n",
8581 "qcom,mbhc-audio-jack-type",
8582 pdev->dev.of_node->full_name);
8583 dev_dbg(&pdev->dev, "Jack type properties set to default\n");
8584 } else {
8585 if (!strcmp(mbhc_audio_jack_type, "4-pole-jack")) {
8586 wcd_mbhc_cfg.enable_anc_mic_detect = false;
8587 dev_dbg(&pdev->dev, "This hardware has 4 pole jack");
8588 } else if (!strcmp(mbhc_audio_jack_type, "5-pole-jack")) {
8589 wcd_mbhc_cfg.enable_anc_mic_detect = true;
8590 dev_dbg(&pdev->dev, "This hardware has 5 pole jack");
8591 } else if (!strcmp(mbhc_audio_jack_type, "6-pole-jack")) {
8592 wcd_mbhc_cfg.enable_anc_mic_detect = true;
8593 dev_dbg(&pdev->dev, "This hardware has 6 pole jack");
8594 } else {
8595 wcd_mbhc_cfg.enable_anc_mic_detect = false;
8596 dev_dbg(&pdev->dev, "Unknown value, set to default\n");
8597 }
8598 }
8599 /*
8600 * Parse US-Euro gpio info from DT. Report no error if us-euro
8601 * entry is not found in DT file as some targets do not support
8602 * US-Euro detection
8603 */
8604 pdata->us_euro_gpio_p = of_parse_phandle(pdev->dev.of_node,
8605 "qcom,us-euro-gpios", 0);
8606 if (!pdata->us_euro_gpio_p) {
8607 dev_dbg(&pdev->dev, "property %s not detected in node %s",
8608 "qcom,us-euro-gpios", pdev->dev.of_node->full_name);
8609 } else {
8610 dev_dbg(&pdev->dev, "%s detected\n",
8611 "qcom,us-euro-gpios");
8612 wcd_mbhc_cfg.swap_gnd_mic = msm_swap_gnd_mic;
8613 }
Vatsal Bucha6cb17a02018-08-07 11:07:04 +0530[diff] [blame]8614
8615 if (wcd_mbhc_cfg.enable_usbc_analog) {
8616 wcd_mbhc_cfg.swap_gnd_mic = msm_usbc_swap_gnd_mic;
8617
8618 pdata->fsa_handle = of_parse_phandle(pdev->dev.of_node,
8619 "fsa4480-i2c-handle", 0);
8620 if (!pdata->fsa_handle)
8621 dev_err(&pdev->dev,
8622 "property %s not detected in node %s\n",
8623 "fsa4480-i2c-handle",
8624 pdev->dev.of_node->full_name);
8625 }
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8626 /* Parse pinctrl info from devicetree */
8627 ret = msm_get_pinctrl(pdev);
8628 if (!ret) {
8629 pr_debug("%s: pinctrl parsing successful\n", __func__);
8630 } else {
8631 dev_dbg(&pdev->dev,
8632 "%s: Parsing pinctrl failed with %d. Cannot use Ports\n",
8633 __func__, ret);
8634 ret = 0;
8635 }
8636
8637 msm_i2s_auxpcm_init(pdev);
Vaishnavi Kommaraju9a3d5eb2018-09-19 18:16:39 +0530[diff] [blame]8638 if (strcmp(card->name, "sm6150-tavil-snd-card")) {
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8639 pdata->dmic01_gpio_p = of_parse_phandle(pdev->dev.of_node,
8640 "qcom,cdc-dmic01-gpios",
8641 0);
8642 pdata->dmic23_gpio_p = of_parse_phandle(pdev->dev.of_node,
8643 "qcom,cdc-dmic23-gpios",
8644 0);
8645 }
Vaishnavi Kommaraju9a3d5eb2018-09-19 18:16:39 +0530[diff] [blame]8646
8647 ret = msm_audio_ssr_register(&pdev->dev);
8648 if (ret)
8649 pr_err("%s: Registration with SND event FWK failed ret = %d\n",
8650 __func__, ret);
8651
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8652err:
8653 return ret;
8654}
8655
8656static int msm_asoc_machine_remove(struct platform_device *pdev)
8657{
Vaishnavi Kommaraju9a3d5eb2018-09-19 18:16:39 +0530[diff] [blame]8658 snd_event_master_deregister(&pdev->dev);
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8659 msm_i2s_auxpcm_deinit();
8660
8661 return 0;
8662}
8663
8664static struct platform_driver sm6150_asoc_machine_driver = {
8665 .driver = {
8666 .name = DRV_NAME,
8667 .owner = THIS_MODULE,
8668 .pm = &snd_soc_pm_ops,
8669 .of_match_table = sm6150_asoc_machine_of_match,
8670 },
8671 .probe = msm_asoc_machine_probe,
8672 .remove = msm_asoc_machine_remove,
8673};
8674module_platform_driver(sm6150_asoc_machine_driver);
8675
Aditya Bavanari0b26ab32018-08-03 23:53:01 +0530[diff] [blame]8676MODULE_DESCRIPTION("ALSA SoC SM6150 Machine driver");
Aditya Bavanari44eb8952018-05-09 19:01:50 +0530[diff] [blame]8677MODULE_LICENSE("GPL v2");
8678MODULE_ALIAS("platform:" DRV_NAME);
8679MODULE_DEVICE_TABLE(of, sm6150_asoc_machine_of_match);