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Vivek126db5d2018-07-25 22:05:04 +05301/*
Karunakar Dasineni1f1acf52018-12-27 09:27:46 -08002 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
Vivek126db5d2018-07-25 22:05:04 +05303 *
4 * Permission to use, copy, modify, and/or distribute this software for
5 * any purpose with or without fee is hereby granted, provided that the
6 * above copyright notice and this permission notice appear in all
7 * copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL
10 * WARRANTIES WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED
11 * WARRANTIES OF MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE
12 * AUTHOR BE LIABLE FOR ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL
13 * DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR
14 * PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR OTHER
15 * TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
16 * PERFORMANCE OF THIS SOFTWARE.
17 */
18
19/**
20 * DOC: This file contains definitions of Data Path configuration.
21 */
22
23#ifndef _CFG_DP_H_
24#define _CFG_DP_H_
25
26#include "cfg_define.h"
27
28#define WLAN_CFG_MAX_CLIENTS 64
Pratik Gandhi4cce3e02018-09-05 19:43:11 +053029#define WLAN_CFG_MAX_CLIENTS_MIN 8
Vivek126db5d2018-07-25 22:05:04 +053030#define WLAN_CFG_MAX_CLIENTS_MAX 64
31
32/* Change this to a lower value to enforce scattered idle list mode */
33#define WLAN_CFG_MAX_ALLOC_SIZE 0x200000
sumedh baikady3c05f972019-04-18 15:30:30 -070034#define WLAN_CFG_MAX_ALLOC_SIZE_MIN 0x80000
Vivek126db5d2018-07-25 22:05:04 +053035#define WLAN_CFG_MAX_ALLOC_SIZE_MAX 0x200000
36
37#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
38#define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3
39#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
40
hangtian04f0ad42019-06-07 11:04:02 +080041#if defined(QCA_LL_TX_FLOW_CONTROL_V2) || \
42 defined(QCA_LL_PDEV_TX_FLOW_CONTROL)
jitiphil60ac9aa2018-10-05 19:54:04 +053043#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 10
44#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 15
Vivek126db5d2018-07-25 22:05:04 +053045#else
jitiphil60ac9aa2018-10-05 19:54:04 +053046#define WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET 0
47#define WLAN_CFG_TX_FLOW_STOP_QUEUE_TH 0
Vivek126db5d2018-07-25 22:05:04 +053048#endif
Vivek126db5d2018-07-25 22:05:04 +053049
50#define WLAN_CFG_PER_PDEV_TX_RING_MIN 0
51#define WLAN_CFG_PER_PDEV_TX_RING_MAX 1
52
Vevek Venkatesan4a6c3e82019-06-24 14:29:19 +053053#if defined(WLAN_MAX_PDEVS) && (WLAN_MAX_PDEVS == 1)
Vivek126db5d2018-07-25 22:05:04 +053054#define WLAN_CFG_PER_PDEV_RX_RING 0
55#define WLAN_CFG_PER_PDEV_LMAC_RING 0
jitiphil60ac9aa2018-10-05 19:54:04 +053056#define WLAN_LRO_ENABLE 0
Venkata Sharath Chandra Manchala8d583a82019-04-21 12:32:24 -070057#define WLAN_CFG_MAC_PER_TARGET 2
Vivek126db5d2018-07-25 22:05:04 +053058#ifdef IPA_OFFLOAD
Mohit Khanna81179cb2018-08-16 20:50:43 -070059/* Size of TCL TX Ring */
60#define WLAN_CFG_TX_RING_SIZE 1024
jitiphil60ac9aa2018-10-05 19:54:04 +053061#define WLAN_CFG_PER_PDEV_TX_RING 0
62#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 2048
63#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 3000
64#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 1024
Vivek126db5d2018-07-25 22:05:04 +053065#else
66#define WLAN_CFG_TX_RING_SIZE 512
jitiphil60ac9aa2018-10-05 19:54:04 +053067#define WLAN_CFG_PER_PDEV_TX_RING 1
68#define WLAN_CFG_IPA_UC_TX_BUF_SIZE 0
69#define WLAN_CFG_IPA_UC_TX_PARTITION_BASE 0
70#define WLAN_CFG_IPA_UC_RX_IND_RING_COUNT 0
Vivek126db5d2018-07-25 22:05:04 +053071#endif
72#define WLAN_CFG_TX_COMP_RING_SIZE 1024
73
74/* Tx Descriptor and Tx Extension Descriptor pool sizes */
75#define WLAN_CFG_NUM_TX_DESC 1024
76#define WLAN_CFG_NUM_TX_EXT_DESC 1024
77
78/* Interrupt Mitigation - Batch threshold in terms of number of frames */
79#define WLAN_CFG_INT_BATCH_THRESHOLD_TX 1
80#define WLAN_CFG_INT_BATCH_THRESHOLD_RX 1
81#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER 1
82
83/* Interrupt Mitigation - Timer threshold in us */
84#define WLAN_CFG_INT_TIMER_THRESHOLD_TX 8
85#define WLAN_CFG_INT_TIMER_THRESHOLD_RX 8
86#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER 8
Vivek126db5d2018-07-25 22:05:04 +053087#endif
88
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -070089#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING 256
Mohit Khanna664e64c2019-07-29 00:37:36 -070090#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING 512
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -070091
Vivek126db5d2018-07-25 22:05:04 +053092#define WLAN_CFG_PER_PDEV_RX_RING_MIN 0
93#define WLAN_CFG_PER_PDEV_RX_RING_MAX 0
94
95#define WLAN_CFG_PER_PDEV_LMAC_RING_MIN 0
96#define WLAN_CFG_PER_PDEV_LMAC_RING_MAX 1
97
98#define WLAN_CFG_TX_RING_SIZE_MIN 512
99#define WLAN_CFG_TX_RING_SIZE_MAX 2048
100
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530101#define WLAN_CFG_TX_COMP_RING_SIZE_MIN 512
Vivek126db5d2018-07-25 22:05:04 +0530102#define WLAN_CFG_TX_COMP_RING_SIZE_MAX 0x80000
103
104#define WLAN_CFG_NUM_TX_DESC_MIN 1024
Shashikala Prabhu550e69c2019-03-13 17:41:17 +0530105#define WLAN_CFG_NUM_TX_DESC_MAX 32768
Vivek126db5d2018-07-25 22:05:04 +0530106
107#define WLAN_CFG_NUM_TX_EXT_DESC_MIN 1024
108#define WLAN_CFG_NUM_TX_EXT_DESC_MAX 0x80000
109
110#define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN 1
111#define WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX 256
112
113#define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN 1
114#define WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX 128
115
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700116#define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MIN 1
117#define WLAN_CFG_INT_BATCH_THRESHOLD_REO_RING_MAX 128
118
119#define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MIN 1
120#define WLAN_CFG_INT_BATCH_THRESHOLD_WBM_RELEASE_RING_MAX 128
121
Vivek126db5d2018-07-25 22:05:04 +0530122#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN 1
123#define WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX 1
124
125#define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN 8
126#define WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX 100
127
128#define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN 8
129#define WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX 500
130
131#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN 8
132#define WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX 1000
133
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700134#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN 8
135#define WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX 500
136
137#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN 8
138#define WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX 500
139
Aniruddha Paul7d991b32018-09-03 17:40:00 +0530140#define WLAN_CFG_NSS_TX_COMP_RING_SIZE 0x2000
141#define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN 0x2000
Aniruddha Paul1b267242019-03-15 12:01:06 +0530142#define WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX 0xc000
Vivek126db5d2018-07-25 22:05:04 +0530143
144#ifdef QCA_LL_TX_FLOW_CONTROL_V2
145
146/* Per vdev pools */
147#define WLAN_CFG_NUM_TX_DESC_POOL 3
148#define WLAN_CFG_NUM_TXEXT_DESC_POOL 3
149
150#else /* QCA_LL_TX_FLOW_CONTROL_V2 */
151
152#ifdef TX_PER_PDEV_DESC_POOL
153#define WLAN_CFG_NUM_TX_DESC_POOL MAX_PDEV_CNT
154#define WLAN_CFG_NUM_TXEXT_DESC_POOL MAX_PDEV_CNT
155
156#else /* TX_PER_PDEV_DESC_POOL */
157
158#define WLAN_CFG_NUM_TX_DESC_POOL 3
159#define WLAN_CFG_NUM_TXEXT_DESC_POOL 3
160
161#endif /* TX_PER_PDEV_DESC_POOL */
162#endif /* QCA_LL_TX_FLOW_CONTROL_V2 */
163
164#define WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN 1
165#define WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX 4
166
167#define WLAN_CFG_HTT_PKT_TYPE 2
168#define WLAN_CFG_HTT_PKT_TYPE_MIN 2
169#define WLAN_CFG_HTT_PKT_TYPE_MAX 2
170
171#define WLAN_CFG_MAX_PEER_ID 64
172#define WLAN_CFG_MAX_PEER_ID_MIN 64
173#define WLAN_CFG_MAX_PEER_ID_MAX 64
174
175#define WLAN_CFG_RX_DEFRAG_TIMEOUT 100
176#define WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN 100
177#define WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX 100
178
179#define WLAN_CFG_NUM_TCL_DATA_RINGS 3
180#define WLAN_CFG_NUM_TCL_DATA_RINGS_MIN 3
181#define WLAN_CFG_NUM_TCL_DATA_RINGS_MAX 3
182
183#define WLAN_CFG_NUM_REO_DEST_RING 4
184#define WLAN_CFG_NUM_REO_DEST_RING_MIN 4
185#define WLAN_CFG_NUM_REO_DEST_RING_MAX 4
186
187#define WLAN_CFG_WBM_RELEASE_RING_SIZE 64
188#define WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN 64
189#define WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX 64
190
191#define WLAN_CFG_TCL_CMD_RING_SIZE 32
192#define WLAN_CFG_TCL_CMD_RING_SIZE_MIN 32
193#define WLAN_CFG_TCL_CMD_RING_SIZE_MAX 32
194
195#define WLAN_CFG_TCL_STATUS_RING_SIZE 32
196#define WLAN_CFG_TCL_STATUS_RING_SIZE_MIN 32
197#define WLAN_CFG_TCL_STATUS_RING_SIZE_MAX 32
198
199#if defined(QCA_WIFI_QCA6290)
200#define WLAN_CFG_REO_DST_RING_SIZE 1024
201#else
202#define WLAN_CFG_REO_DST_RING_SIZE 2048
203#endif
204
205#define WLAN_CFG_REO_DST_RING_SIZE_MIN 1024
206#define WLAN_CFG_REO_DST_RING_SIZE_MAX 2048
207
208#define WLAN_CFG_REO_REINJECT_RING_SIZE 32
209#define WLAN_CFG_REO_REINJECT_RING_SIZE_MIN 32
210#define WLAN_CFG_REO_REINJECT_RING_SIZE_MAX 32
211
212#define WLAN_CFG_RX_RELEASE_RING_SIZE 1024
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530213#define WLAN_CFG_RX_RELEASE_RING_SIZE_MIN 8
Tallapragada Kalyan0ef58ee2019-03-29 17:18:47 +0530214#if defined(QCA_WIFI_QCA6390)
Vivek126db5d2018-07-25 22:05:04 +0530215#define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 1024
Tallapragada Kalyan0ef58ee2019-03-29 17:18:47 +0530216#else
217#define WLAN_CFG_RX_RELEASE_RING_SIZE_MAX 8192
218#endif
Vivek126db5d2018-07-25 22:05:04 +0530219
220#define WLAN_CFG_REO_EXCEPTION_RING_SIZE 128
221#define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN 128
222#define WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX 128
223
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700224#define WLAN_CFG_REO_CMD_RING_SIZE 128
Vivek126db5d2018-07-25 22:05:04 +0530225#define WLAN_CFG_REO_CMD_RING_SIZE_MIN 64
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700226#define WLAN_CFG_REO_CMD_RING_SIZE_MAX 128
Vivek126db5d2018-07-25 22:05:04 +0530227
Karunakar Dasineni26ebbe42018-05-31 07:59:10 -0700228#define WLAN_CFG_REO_STATUS_RING_SIZE 256
Vivek126db5d2018-07-25 22:05:04 +0530229#define WLAN_CFG_REO_STATUS_RING_SIZE_MIN 128
Karunakar Dasineni1f1acf52018-12-27 09:27:46 -0800230#define WLAN_CFG_REO_STATUS_RING_SIZE_MAX 2048
Vivek126db5d2018-07-25 22:05:04 +0530231
232#define WLAN_CFG_RXDMA_BUF_RING_SIZE 1024
233#define WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN 1024
234#define WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX 1024
235
236#define WLAN_CFG_RXDMA_REFILL_RING_SIZE 4096
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530237#define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN 16
Vivek126db5d2018-07-25 22:05:04 +0530238#define WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX 4096
239
Prathyusha Guduri36ce8172019-07-19 19:43:39 +0530240#define WLAN_CFG_TX_DESC_LIMIT_0 0
241#define WLAN_CFG_TX_DESC_LIMIT_0_MIN 4096
242#define WLAN_CFG_TX_DESC_LIMIT_0_MAX 32768
243
244#define WLAN_CFG_TX_DESC_LIMIT_1 0
245#define WLAN_CFG_TX_DESC_LIMIT_1_MIN 4096
246#define WLAN_CFG_TX_DESC_LIMIT_1_MAX 32768
247
248#define WLAN_CFG_TX_DESC_LIMIT_2 0
249#define WLAN_CFG_TX_DESC_LIMIT_2_MIN 4096
250#define WLAN_CFG_TX_DESC_LIMIT_2_MAX 32768
251
Prathyusha Guduriaed67e12019-07-21 23:55:52 +0530252#define WLAN_CFG_TX_DEVICE_LIMIT 65536
253#define WLAN_CFG_TX_DEVICE_LIMIT_MIN 16384
254#define WLAN_CFG_TX_DEVICE_LIMIT_MAX 65536
255
Prathyusha Guduriabac9ee2019-07-24 23:49:45 +0530256#define WLAN_CFG_TX_SW_INTERNODE_QUEUE 1024
257#define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN 128
258#define WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX 1024
259
Vivek126db5d2018-07-25 22:05:04 +0530260#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE 4096
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530261#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN 16
Kai Chen692850b2018-12-05 15:06:07 -0800262#define WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530263
264#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE 2048
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530265#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN 48
Kai Chen692850b2018-12-05 15:06:07 -0800266#define WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530267
268#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE 1024
Pratik Gandhi4cce3e02018-09-05 19:43:11 +0530269#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN 16
Kai Chen692850b2018-12-05 15:06:07 -0800270#define WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530271
272#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE 4096
273#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN 4096
Kai Chen692850b2018-12-05 15:06:07 -0800274#define WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX 16384
Vivek126db5d2018-07-25 22:05:04 +0530275
276#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE 1024
277#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN 1024
Karunakar Dasineni79768452018-09-07 11:32:34 -0700278#define WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX 8192
Vivek126db5d2018-07-25 22:05:04 +0530279
Ruben Columbusb7a1c572019-08-12 11:11:29 -0700280#define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE 32
281#define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN 0
282#define WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX 256
283
Mainak Sen95502732019-07-25 00:48:59 +0530284/**
285 * Allocate as many RX descriptors as buffers in the SW2RXDMA
286 * ring. This value may need to be tuned later.
287 */
288#if defined(QCA_HOST2FW_RXBUF_RING)
289#define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1
290#define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1
291#define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 1
292
293/**
294 * For low memory AP cases using 1 will reduce the rx descriptors memory req
295 */
296#elif defined(QCA_LOWMEM_CONFIG) || defined(QCA_512M_CONFIG)
297#define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 1
298#define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1
299#define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3
300
301/**
302 * AP use cases need to allocate more RX Descriptors than the number of
303 * entries avaialable in the SW2RXDMA buffer replenish ring. This is to account
304 * for frames sitting in REO queues, HW-HW DMA rings etc. Hence using a
305 * multiplication factor of 3, to allocate three times as many RX descriptors
306 * as RX buffers.
307 */
308#else
309#define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE 3
310#define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN 1
311#define WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX 3
312#endif //QCA_HOST2FW_RXBUF_RING
313
Sumeet Rao76aa8d52019-06-20 12:23:14 -0700314#define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE 16384
315#define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN 1
316#define WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX 16384
317
Vivek126db5d2018-07-25 22:05:04 +0530318/* DP INI Declerations */
319#define CFG_DP_HTT_PACKET_TYPE \
320 CFG_INI_UINT("dp_htt_packet_type", \
321 WLAN_CFG_HTT_PKT_TYPE_MIN, \
322 WLAN_CFG_HTT_PKT_TYPE_MAX, \
323 WLAN_CFG_HTT_PKT_TYPE, \
324 CFG_VALUE_OR_DEFAULT, "DP HTT packet type")
325
326#define CFG_DP_INT_BATCH_THRESHOLD_OTHER \
327 CFG_INI_UINT("dp_int_batch_threshold_other", \
Karunakar Dasineni2b7628c2018-10-23 22:59:37 -0700328 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MIN, \
329 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER_MAX, \
330 WLAN_CFG_INT_BATCH_THRESHOLD_OTHER, \
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700331 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Other")
Vivek126db5d2018-07-25 22:05:04 +0530332
333#define CFG_DP_INT_BATCH_THRESHOLD_RX \
334 CFG_INI_UINT("dp_int_batch_threshold_rx", \
335 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MIN, \
336 WLAN_CFG_INT_BATCH_THRESHOLD_RX_MAX, \
337 WLAN_CFG_INT_BATCH_THRESHOLD_RX, \
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700338 CFG_VALUE_OR_DEFAULT, "DP INT batch threshold Rx")
Vivek126db5d2018-07-25 22:05:04 +0530339
340#define CFG_DP_INT_BATCH_THRESHOLD_TX \
341 CFG_INI_UINT("dp_int_batch_threshold_tx", \
342 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MIN, \
343 WLAN_CFG_INT_BATCH_THRESHOLD_TX_MAX, \
344 WLAN_CFG_INT_BATCH_THRESHOLD_TX, \
345 CFG_VALUE_OR_DEFAULT, "DP INT threshold Tx")
346
347#define CFG_DP_INT_TIMER_THRESHOLD_OTHER \
348 CFG_INI_UINT("dp_int_timer_threshold_other", \
349 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MIN, \
350 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER_MAX, \
351 WLAN_CFG_INT_TIMER_THRESHOLD_OTHER, \
352 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Other")
353
354#define CFG_DP_INT_TIMER_THRESHOLD_RX \
355 CFG_INI_UINT("dp_int_timer_threshold_rx", \
356 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MIN, \
357 WLAN_CFG_INT_TIMER_THRESHOLD_RX_MAX, \
358 WLAN_CFG_INT_TIMER_THRESHOLD_RX, \
359 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Rx")
360
Venkata Sharath Chandra Manchalacb6d0c02019-05-16 17:33:18 -0700361#define CFG_DP_INT_TIMER_THRESHOLD_REO_RING \
362 CFG_INI_UINT("dp_int_timer_threshold_reo_ring", \
363 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MIN, \
364 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING_MAX, \
365 WLAN_CFG_INT_TIMER_THRESHOLD_REO_RING, \
366 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Reo ring")
367
368#define CFG_DP_INT_TIMER_THRESHOLD_WBM_RELEASE_RING \
369 CFG_INI_UINT("dp_int_timer_threshold_wbm_release_ring", \
370 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MIN, \
371 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING_MAX, \
372 WLAN_CFG_INT_TIMER_THRESHOLD_WBM_RELEASE_RING, \
373 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold wbm release ring")
374
Vivek126db5d2018-07-25 22:05:04 +0530375#define CFG_DP_INT_TIMER_THRESHOLD_TX \
376 CFG_INI_UINT("dp_int_timer_threshold_tx", \
377 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MIN, \
378 WLAN_CFG_INT_TIMER_THRESHOLD_TX_MAX, \
379 WLAN_CFG_INT_TIMER_THRESHOLD_TX, \
380 CFG_VALUE_OR_DEFAULT, "DP INT timer threshold Tx")
381
382#define CFG_DP_MAX_ALLOC_SIZE \
383 CFG_INI_UINT("dp_max_alloc_size", \
384 WLAN_CFG_MAX_ALLOC_SIZE_MIN, \
385 WLAN_CFG_MAX_ALLOC_SIZE_MAX, \
386 WLAN_CFG_MAX_ALLOC_SIZE, \
387 CFG_VALUE_OR_DEFAULT, "DP Max Alloc Size")
388
389#define CFG_DP_MAX_CLIENTS \
390 CFG_INI_UINT("dp_max_clients", \
391 WLAN_CFG_MAX_CLIENTS_MIN, \
392 WLAN_CFG_MAX_CLIENTS_MAX, \
393 WLAN_CFG_MAX_CLIENTS, \
394 CFG_VALUE_OR_DEFAULT, "DP Max Clients")
395
396#define CFG_DP_MAX_PEER_ID \
397 CFG_INI_UINT("dp_max_peer_id", \
398 WLAN_CFG_MAX_PEER_ID_MIN, \
399 WLAN_CFG_MAX_PEER_ID_MAX, \
400 WLAN_CFG_MAX_PEER_ID, \
401 CFG_VALUE_OR_DEFAULT, "DP Max Peer ID")
402
403#define CFG_DP_REO_DEST_RINGS \
404 CFG_INI_UINT("dp_reo_dest_rings", \
405 WLAN_CFG_NUM_REO_DEST_RING_MIN, \
406 WLAN_CFG_NUM_REO_DEST_RING_MAX, \
407 WLAN_CFG_NUM_REO_DEST_RING, \
408 CFG_VALUE_OR_DEFAULT, "DP REO Destination Rings")
409
410#define CFG_DP_TCL_DATA_RINGS \
411 CFG_INI_UINT("dp_tcl_data_rings", \
412 WLAN_CFG_NUM_TCL_DATA_RINGS_MIN, \
413 WLAN_CFG_NUM_TCL_DATA_RINGS_MAX, \
414 WLAN_CFG_NUM_TCL_DATA_RINGS, \
415 CFG_VALUE_OR_DEFAULT, "DP TCL Data Rings")
416
417#define CFG_DP_TX_DESC \
418 CFG_INI_UINT("dp_tx_desc", \
419 WLAN_CFG_NUM_TX_DESC_MIN, \
420 WLAN_CFG_NUM_TX_DESC_MAX, \
421 WLAN_CFG_NUM_TX_DESC, \
422 CFG_VALUE_OR_DEFAULT, "DP Tx Descriptors")
423
424#define CFG_DP_TX_EXT_DESC \
425 CFG_INI_UINT("dp_tx_ext_desc", \
426 WLAN_CFG_NUM_TX_EXT_DESC_MIN, \
427 WLAN_CFG_NUM_TX_EXT_DESC_MAX, \
428 WLAN_CFG_NUM_TX_EXT_DESC, \
429 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors")
430
431#define CFG_DP_TX_EXT_DESC_POOLS \
432 CFG_INI_UINT("dp_tx_ext_desc_pool", \
433 WLAN_CFG_NUM_TXEXT_DESC_POOL_MIN, \
434 WLAN_CFG_NUM_TXEXT_DESC_POOL_MAX, \
435 WLAN_CFG_NUM_TXEXT_DESC_POOL, \
436 CFG_VALUE_OR_DEFAULT, "DP Tx Ext Descriptors Pool")
437
438#define CFG_DP_PDEV_RX_RING \
439 CFG_INI_UINT("dp_pdev_rx_ring", \
440 WLAN_CFG_PER_PDEV_RX_RING_MIN, \
441 WLAN_CFG_PER_PDEV_RX_RING_MAX, \
442 WLAN_CFG_PER_PDEV_RX_RING, \
443 CFG_VALUE_OR_DEFAULT, "DP PDEV Rx Ring")
444
445#define CFG_DP_PDEV_TX_RING \
446 CFG_INI_UINT("dp_pdev_tx_ring", \
447 WLAN_CFG_PER_PDEV_TX_RING_MIN, \
448 WLAN_CFG_PER_PDEV_TX_RING_MAX, \
449 WLAN_CFG_PER_PDEV_TX_RING, \
450 CFG_VALUE_OR_DEFAULT, \
451 "DP PDEV Tx Ring")
452
453#define CFG_DP_RX_DEFRAG_TIMEOUT \
454 CFG_INI_UINT("dp_rx_defrag_timeout", \
455 WLAN_CFG_RX_DEFRAG_TIMEOUT_MIN, \
456 WLAN_CFG_RX_DEFRAG_TIMEOUT_MAX, \
457 WLAN_CFG_RX_DEFRAG_TIMEOUT, \
458 CFG_VALUE_OR_DEFAULT, "DP Rx Defrag Timeout")
459
460#define CFG_DP_TX_COMPL_RING_SIZE \
461 CFG_INI_UINT("dp_tx_compl_ring_size", \
462 WLAN_CFG_TX_COMP_RING_SIZE_MIN, \
463 WLAN_CFG_TX_COMP_RING_SIZE_MAX, \
464 WLAN_CFG_TX_COMP_RING_SIZE, \
465 CFG_VALUE_OR_DEFAULT, "DP Tx Completion Ring Size")
466
467#define CFG_DP_TX_RING_SIZE \
468 CFG_INI_UINT("dp_tx_ring_size", \
469 WLAN_CFG_TX_RING_SIZE_MIN,\
470 WLAN_CFG_TX_RING_SIZE_MAX,\
471 WLAN_CFG_TX_RING_SIZE,\
472 CFG_VALUE_OR_DEFAULT, "DP Tx Ring Size")
473
474#define CFG_DP_NSS_COMP_RING_SIZE \
475 CFG_INI_UINT("dp_nss_comp_ring_size", \
476 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MIN, \
477 WLAN_CFG_NSS_TX_COMP_RING_SIZE_MAX, \
478 WLAN_CFG_NSS_TX_COMP_RING_SIZE, \
479 CFG_VALUE_OR_DEFAULT, "DP NSS completion Ring Size")
480
481#define CFG_DP_PDEV_LMAC_RING \
482 CFG_INI_UINT("dp_pdev_lmac_ring", \
483 WLAN_CFG_PER_PDEV_LMAC_RING_MIN, \
484 WLAN_CFG_PER_PDEV_LMAC_RING_MAX, \
485 WLAN_CFG_PER_PDEV_LMAC_RING, \
486 CFG_VALUE_OR_DEFAULT, "DP pdev LMAC ring")
487
488#define CFG_DP_BASE_HW_MAC_ID \
489 CFG_INI_UINT("dp_base_hw_macid", \
490 0, 1, 1, \
491 CFG_VALUE_OR_DEFAULT, "DP Base HW Mac ID")
492
Vivek126db5d2018-07-25 22:05:04 +0530493#define CFG_DP_RX_HASH \
494 CFG_INI_BOOL("dp_rx_hash", true, \
495 "DP Rx Hash")
496
497#define CFG_DP_TSO \
498 CFG_INI_BOOL("TSOEnable", false, \
499 "DP TSO Enabled")
500
Akshay Kosigia4f6e172018-09-03 21:42:27 +0530501#define CFG_DP_LRO \
502 CFG_INI_BOOL("LROEnable", WLAN_LRO_ENABLE, \
503 "DP LRO Enable")
504
505#define CFG_DP_SG \
506 CFG_INI_BOOL("dp_sg_support", false, \
507 "DP SG Enable")
508
509#define CFG_DP_GRO \
510 CFG_INI_BOOL("GROEnable", false, \
511 "DP GRO Enable")
512
513#define CFG_DP_OL_TX_CSUM \
514 CFG_INI_BOOL("dp_offload_tx_csum_support", false, \
515 "DP tx csum Enable")
516
517#define CFG_DP_OL_RX_CSUM \
518 CFG_INI_BOOL("dp_offload_rx_csum_support", false, \
519 "DP rx csum Enable")
520
521#define CFG_DP_RAWMODE \
522 CFG_INI_BOOL("dp_rawmode_support", false, \
523 "DP rawmode Enable")
524
525#define CFG_DP_PEER_FLOW_CTRL \
526 CFG_INI_BOOL("dp_peer_flow_control_support", false, \
527 "DP peer flow ctrl Enable")
528
Vivek126db5d2018-07-25 22:05:04 +0530529#define CFG_DP_NAPI \
Vivek7047d0d2019-07-09 19:30:40 +0530530 CFG_INI_BOOL("dp_napi_enabled", PLATFORM_VALUE(true, false), \
Vivek126db5d2018-07-25 22:05:04 +0530531 "DP Napi Enabled")
532
533#define CFG_DP_TCP_UDP_CKSUM_OFFLOAD \
jitiphil60ac9aa2018-10-05 19:54:04 +0530534 CFG_INI_BOOL("gEnableIpTcpUdpChecksumOffload", true, \
Vivek126db5d2018-07-25 22:05:04 +0530535 "DP TCP UDP Checksum Offload")
536
537#define CFG_DP_DEFRAG_TIMEOUT_CHECK \
538 CFG_INI_BOOL("dp_defrag_timeout_check", true, \
539 "DP Defrag Timeout Check")
540
541#define CFG_DP_WBM_RELEASE_RING \
542 CFG_INI_UINT("dp_wbm_release_ring", \
543 WLAN_CFG_WBM_RELEASE_RING_SIZE_MIN, \
544 WLAN_CFG_WBM_RELEASE_RING_SIZE_MAX, \
545 WLAN_CFG_WBM_RELEASE_RING_SIZE, \
546 CFG_VALUE_OR_DEFAULT, "DP WBM Release Ring")
547
548#define CFG_DP_TCL_CMD_RING \
549 CFG_INI_UINT("dp_tcl_cmd_ring", \
550 WLAN_CFG_TCL_CMD_RING_SIZE_MIN, \
551 WLAN_CFG_TCL_CMD_RING_SIZE_MAX, \
552 WLAN_CFG_TCL_CMD_RING_SIZE, \
553 CFG_VALUE_OR_DEFAULT, "DP TCL command ring")
554
555#define CFG_DP_TCL_STATUS_RING \
556 CFG_INI_UINT("dp_tcl_status_ring",\
557 WLAN_CFG_TCL_STATUS_RING_SIZE_MIN, \
558 WLAN_CFG_TCL_STATUS_RING_SIZE_MAX, \
559 WLAN_CFG_TCL_STATUS_RING_SIZE, \
560 CFG_VALUE_OR_DEFAULT, "DP TCL status ring")
561
562#define CFG_DP_REO_REINJECT_RING \
563 CFG_INI_UINT("dp_reo_reinject_ring", \
564 WLAN_CFG_REO_REINJECT_RING_SIZE_MIN, \
565 WLAN_CFG_REO_REINJECT_RING_SIZE_MAX, \
566 WLAN_CFG_REO_REINJECT_RING_SIZE, \
567 CFG_VALUE_OR_DEFAULT, "DP REO reinject ring")
568
569#define CFG_DP_RX_RELEASE_RING \
570 CFG_INI_UINT("dp_rx_release_ring", \
571 WLAN_CFG_RX_RELEASE_RING_SIZE_MIN, \
572 WLAN_CFG_RX_RELEASE_RING_SIZE_MAX, \
573 WLAN_CFG_RX_RELEASE_RING_SIZE, \
574 CFG_VALUE_OR_DEFAULT, "DP Rx release ring")
575
576#define CFG_DP_REO_EXCEPTION_RING \
577 CFG_INI_UINT("dp_reo_exception_ring", \
578 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MIN, \
579 WLAN_CFG_REO_EXCEPTION_RING_SIZE_MAX, \
580 WLAN_CFG_REO_EXCEPTION_RING_SIZE, \
581 CFG_VALUE_OR_DEFAULT, "DP REO exception ring")
582
583#define CFG_DP_REO_CMD_RING \
584 CFG_INI_UINT("dp_reo_cmd_ring", \
585 WLAN_CFG_REO_CMD_RING_SIZE_MIN, \
586 WLAN_CFG_REO_CMD_RING_SIZE_MAX, \
587 WLAN_CFG_REO_CMD_RING_SIZE, \
588 CFG_VALUE_OR_DEFAULT, "DP REO command ring")
589
590#define CFG_DP_REO_STATUS_RING \
591 CFG_INI_UINT("dp_reo_status_ring", \
592 WLAN_CFG_REO_STATUS_RING_SIZE_MIN, \
593 WLAN_CFG_REO_STATUS_RING_SIZE_MAX, \
594 WLAN_CFG_REO_STATUS_RING_SIZE, \
595 CFG_VALUE_OR_DEFAULT, "DP REO status ring")
596
597#define CFG_DP_RXDMA_BUF_RING \
598 CFG_INI_UINT("dp_rxdma_buf_ring", \
599 WLAN_CFG_RXDMA_BUF_RING_SIZE_MIN, \
600 WLAN_CFG_RXDMA_BUF_RING_SIZE_MAX, \
601 WLAN_CFG_RXDMA_BUF_RING_SIZE, \
602 CFG_VALUE_OR_DEFAULT, "DP RXDMA buffer ring")
603
604#define CFG_DP_RXDMA_REFILL_RING \
605 CFG_INI_UINT("dp_rxdma_refill_ring", \
606 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MIN, \
607 WLAN_CFG_RXDMA_REFILL_RING_SIZE_MAX, \
608 WLAN_CFG_RXDMA_REFILL_RING_SIZE, \
609 CFG_VALUE_OR_DEFAULT, "DP RXDMA refilll ring")
610
Prathyusha Guduri36ce8172019-07-19 19:43:39 +0530611#define CFG_DP_TX_DESC_LIMIT_0 \
612 CFG_INI_UINT("dp_tx_desc_limit_0", \
613 WLAN_CFG_TX_DESC_LIMIT_0_MIN, \
614 WLAN_CFG_TX_DESC_LIMIT_0_MAX, \
615 WLAN_CFG_TX_DESC_LIMIT_0, \
616 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 0")
617
618#define CFG_DP_TX_DESC_LIMIT_1 \
619 CFG_INI_UINT("dp_tx_desc_limit_1", \
620 WLAN_CFG_TX_DESC_LIMIT_1_MIN, \
621 WLAN_CFG_TX_DESC_LIMIT_1_MAX, \
622 WLAN_CFG_TX_DESC_LIMIT_1, \
623 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 1")
624
625#define CFG_DP_TX_DESC_LIMIT_2 \
626 CFG_INI_UINT("dp_tx_desc_limit_2", \
627 WLAN_CFG_TX_DESC_LIMIT_2_MIN, \
628 WLAN_CFG_TX_DESC_LIMIT_2_MAX, \
629 WLAN_CFG_TX_DESC_LIMIT_2, \
630 CFG_VALUE_OR_DEFAULT, "DP TX DESC limit 2")
631
Prathyusha Guduriaed67e12019-07-21 23:55:52 +0530632#define CFG_DP_TX_DEVICE_LIMIT \
633 CFG_INI_UINT("dp_tx_device_limit", \
634 WLAN_CFG_TX_DEVICE_LIMIT_MIN, \
635 WLAN_CFG_TX_DEVICE_LIMIT_MAX, \
636 WLAN_CFG_TX_DEVICE_LIMIT, \
637 CFG_VALUE_OR_DEFAULT, "DP TX DEVICE limit")
638
Prathyusha Guduriabac9ee2019-07-24 23:49:45 +0530639#define CFG_DP_TX_SW_INTERNODE_QUEUE \
640 CFG_INI_UINT("dp_tx_sw_internode_queue", \
641 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MIN, \
642 WLAN_CFG_TX_SW_INTERNODE_QUEUE_MAX, \
643 WLAN_CFG_TX_SW_INTERNODE_QUEUE, \
644 CFG_VALUE_OR_DEFAULT, "DP TX SW internode queue")
645
Vivek126db5d2018-07-25 22:05:04 +0530646#define CFG_DP_RXDMA_MONITOR_BUF_RING \
647 CFG_INI_UINT("dp_rxdma_monitor_buf_ring", \
648 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MIN, \
649 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE_MAX, \
650 WLAN_CFG_RXDMA_MONITOR_BUF_RING_SIZE, \
651 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor buffer ring")
652
653#define CFG_DP_RXDMA_MONITOR_DST_RING \
654 CFG_INI_UINT("dp_rxdma_monitor_dst_ring", \
655 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MIN, \
656 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE_MAX, \
657 WLAN_CFG_RXDMA_MONITOR_DST_RING_SIZE, \
658 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring")
659
660#define CFG_DP_RXDMA_MONITOR_STATUS_RING \
661 CFG_INI_UINT("dp_rxdma_monitor_status_ring", \
662 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MIN, \
663 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE_MAX, \
664 WLAN_CFG_RXDMA_MONITOR_STATUS_RING_SIZE, \
665 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor status ring")
666
667#define CFG_DP_RXDMA_MONITOR_DESC_RING \
668 CFG_INI_UINT("dp_rxdma_monitor_desc_ring", \
669 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MIN, \
670 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE_MAX, \
671 WLAN_CFG_RXDMA_MONITOR_DESC_RING_SIZE, \
672 CFG_VALUE_OR_DEFAULT, "DP RXDMA monitor destination ring")
673
674#define CFG_DP_RXDMA_ERR_DST_RING \
675 CFG_INI_UINT("dp_rxdma_err_dst_ring", \
676 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MIN, \
677 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE_MAX, \
678 WLAN_CFG_RXDMA_ERR_DST_RING_SIZE, \
679 CFG_VALUE_OR_DEFAULT, "RXDMA err destination ring")
680
Krunal Soni03ba0f52019-02-12 11:44:46 -0800681#define CFG_DP_PER_PKT_LOGGING \
682 CFG_INI_UINT("enable_verbose_debug", \
683 0, 0xffff, 0, \
684 CFG_VALUE_OR_DEFAULT, "Enable excessive per packet logging")
685
jitiphil60ac9aa2018-10-05 19:54:04 +0530686#define CFG_DP_TX_FLOW_START_QUEUE_OFFSET \
687 CFG_INI_UINT("TxFlowStartQueueOffset", \
688 0, 30, WLAN_CFG_TX_FLOW_START_QUEUE_OFFSET, \
689 CFG_VALUE_OR_DEFAULT, "Start queue offset")
690
691#define CFG_DP_TX_FLOW_STOP_QUEUE_TH \
692 CFG_INI_UINT("TxFlowStopQueueThreshold", \
693 0, 50, 15, \
694 CFG_VALUE_OR_DEFAULT, "Stop queue Threshold")
695
696#define CFG_DP_IPA_UC_TX_BUF_SIZE \
697 CFG_INI_UINT("IpaUcTxBufSize", \
698 0, 4096, WLAN_CFG_IPA_UC_TX_BUF_SIZE, \
699 CFG_VALUE_OR_DEFAULT, "IPA tx buffer size")
700
701#define CFG_DP_IPA_UC_TX_PARTITION_BASE \
702 CFG_INI_UINT("IpaUcTxPartitionBase", \
703 0, 9000, WLAN_CFG_IPA_UC_TX_PARTITION_BASE, \
704 CFG_VALUE_OR_DEFAULT, "IPA tx partition base")
705
706#define CFG_DP_IPA_UC_RX_IND_RING_COUNT \
707 CFG_INI_UINT("IpaUcRxIndRingCount", \
708 0, 2048, WLAN_CFG_IPA_UC_RX_IND_RING_COUNT, \
709 CFG_VALUE_OR_DEFAULT, "IPA rx indication ring count")
710
711#define CFG_DP_REORDER_OFFLOAD_SUPPORT \
712 CFG_INI_UINT("gReorderOffloadSupported", \
713 0, 1, 1, \
714 CFG_VALUE_OR_DEFAULT, "Packet reordering offload to firmware")
715
716#define CFG_DP_AP_STA_SECURITY_SEPERATION \
717 CFG_INI_BOOL("gDisableIntraBssFwd", \
718 false, "Disable intrs BSS Rx packets")
719
720#define CFG_DP_ENABLE_DATA_STALL_DETECTION \
721 CFG_INI_BOOL("gEnableDataStallDetection", \
722 true, "Enable/Disable Data stall detection")
723
Mainak Sen95502732019-07-25 00:48:59 +0530724#define CFG_DP_RX_SW_DESC_WEIGHT \
725 CFG_INI_UINT("dp_rx_sw_desc_weight", \
726 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MIN, \
727 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE_MAX, \
728 WLAN_CFG_RX_SW_DESC_WEIGHT_SIZE, \
729 CFG_VALUE_OR_DEFAULT, "DP RX SW DESC weight")
730
Sumeet Rao76aa8d52019-06-20 12:23:14 -0700731#define CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE \
732 CFG_INI_UINT("dp_rx_flow_search_table_size", \
733 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MIN, \
734 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE_MAX, \
735 WLAN_CFG_RX_FLOW_SEARCH_TABLE_SIZE, \
736 CFG_VALUE_OR_DEFAULT, \
737 "DP Rx Flow Search Table Size in number of entries")
738
739#define CFG_DP_RX_FLOW_TAG_ENABLE \
740 CFG_INI_BOOL("dp_rx_flow_tag_enable", false, \
741 "Enable/Disable DP Rx Flow Tag")
742
743#define CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV \
744 CFG_INI_BOOL("dp_rx_per_pdev_flow_search", false, \
745 "DP Rx Flow Search Table Is Per PDev")
746
747#define CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE \
748 CFG_INI_BOOL("dp_rx_monitor_protocol_flow_tag_enable", true, \
749 "Enable/Disable Rx Protocol & Flow tags in Monitor mode")
750
Ruben Columbusb7a1c572019-08-12 11:11:29 -0700751#define CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD \
752 CFG_INI_UINT("mon_drop_thresh", \
753 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MIN, \
754 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE_MAX, \
755 WLAN_CFG_RXDMA_MONITOR_RX_DROP_THRESH_SIZE, \
756 CFG_VALUE_OR_DEFAULT, "RXDMA monitor rx drop theshold")
757
Vivek126db5d2018-07-25 22:05:04 +0530758#define CFG_DP \
759 CFG(CFG_DP_HTT_PACKET_TYPE) \
760 CFG(CFG_DP_INT_BATCH_THRESHOLD_OTHER) \
761 CFG(CFG_DP_INT_BATCH_THRESHOLD_RX) \
762 CFG(CFG_DP_INT_BATCH_THRESHOLD_TX) \
763 CFG(CFG_DP_INT_TIMER_THRESHOLD_OTHER) \
764 CFG(CFG_DP_INT_TIMER_THRESHOLD_RX) \
765 CFG(CFG_DP_INT_TIMER_THRESHOLD_TX) \
766 CFG(CFG_DP_MAX_ALLOC_SIZE) \
767 CFG(CFG_DP_MAX_CLIENTS) \
768 CFG(CFG_DP_MAX_PEER_ID) \
769 CFG(CFG_DP_REO_DEST_RINGS) \
770 CFG(CFG_DP_TCL_DATA_RINGS) \
771 CFG(CFG_DP_TX_DESC) \
772 CFG(CFG_DP_TX_EXT_DESC) \
773 CFG(CFG_DP_TX_EXT_DESC_POOLS) \
774 CFG(CFG_DP_PDEV_RX_RING) \
775 CFG(CFG_DP_PDEV_TX_RING) \
776 CFG(CFG_DP_RX_DEFRAG_TIMEOUT) \
777 CFG(CFG_DP_TX_COMPL_RING_SIZE) \
778 CFG(CFG_DP_TX_RING_SIZE) \
779 CFG(CFG_DP_NSS_COMP_RING_SIZE) \
780 CFG(CFG_DP_PDEV_LMAC_RING) \
781 CFG(CFG_DP_BASE_HW_MAC_ID) \
Vivek126db5d2018-07-25 22:05:04 +0530782 CFG(CFG_DP_RX_HASH) \
783 CFG(CFG_DP_TSO) \
Akshay Kosigia4f6e172018-09-03 21:42:27 +0530784 CFG(CFG_DP_LRO) \
785 CFG(CFG_DP_SG) \
786 CFG(CFG_DP_GRO) \
787 CFG(CFG_DP_OL_TX_CSUM) \
788 CFG(CFG_DP_OL_RX_CSUM) \
789 CFG(CFG_DP_RAWMODE) \
790 CFG(CFG_DP_PEER_FLOW_CTRL) \
Vivek126db5d2018-07-25 22:05:04 +0530791 CFG(CFG_DP_NAPI) \
792 CFG(CFG_DP_TCP_UDP_CKSUM_OFFLOAD) \
793 CFG(CFG_DP_DEFRAG_TIMEOUT_CHECK) \
794 CFG(CFG_DP_WBM_RELEASE_RING) \
795 CFG(CFG_DP_TCL_CMD_RING) \
796 CFG(CFG_DP_TCL_STATUS_RING) \
797 CFG(CFG_DP_REO_REINJECT_RING) \
798 CFG(CFG_DP_RX_RELEASE_RING) \
799 CFG(CFG_DP_REO_EXCEPTION_RING) \
800 CFG(CFG_DP_REO_CMD_RING) \
801 CFG(CFG_DP_REO_STATUS_RING) \
802 CFG(CFG_DP_RXDMA_BUF_RING) \
803 CFG(CFG_DP_RXDMA_REFILL_RING) \
Prathyusha Guduri36ce8172019-07-19 19:43:39 +0530804 CFG(CFG_DP_TX_DESC_LIMIT_0) \
805 CFG(CFG_DP_TX_DESC_LIMIT_1) \
806 CFG(CFG_DP_TX_DESC_LIMIT_2) \
Prathyusha Guduriaed67e12019-07-21 23:55:52 +0530807 CFG(CFG_DP_TX_DEVICE_LIMIT) \
Prathyusha Guduriabac9ee2019-07-24 23:49:45 +0530808 CFG(CFG_DP_TX_SW_INTERNODE_QUEUE) \
Vivek126db5d2018-07-25 22:05:04 +0530809 CFG(CFG_DP_RXDMA_MONITOR_BUF_RING) \
810 CFG(CFG_DP_RXDMA_MONITOR_DST_RING) \
811 CFG(CFG_DP_RXDMA_MONITOR_STATUS_RING) \
812 CFG(CFG_DP_RXDMA_MONITOR_DESC_RING) \
jitiphil60ac9aa2018-10-05 19:54:04 +0530813 CFG(CFG_DP_RXDMA_ERR_DST_RING) \
Krunal Soni03ba0f52019-02-12 11:44:46 -0800814 CFG(CFG_DP_PER_PKT_LOGGING) \
jitiphil60ac9aa2018-10-05 19:54:04 +0530815 CFG(CFG_DP_TX_FLOW_START_QUEUE_OFFSET) \
816 CFG(CFG_DP_TX_FLOW_STOP_QUEUE_TH) \
817 CFG(CFG_DP_IPA_UC_TX_BUF_SIZE) \
818 CFG(CFG_DP_IPA_UC_TX_PARTITION_BASE) \
819 CFG(CFG_DP_IPA_UC_RX_IND_RING_COUNT) \
820 CFG(CFG_DP_REORDER_OFFLOAD_SUPPORT) \
821 CFG(CFG_DP_AP_STA_SECURITY_SEPERATION) \
Mainak Sen95502732019-07-25 00:48:59 +0530822 CFG(CFG_DP_ENABLE_DATA_STALL_DETECTION) \
Sumeet Rao76aa8d52019-06-20 12:23:14 -0700823 CFG(CFG_DP_RX_SW_DESC_WEIGHT) \
824 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_SIZE) \
825 CFG(CFG_DP_RX_FLOW_TAG_ENABLE) \
826 CFG(CFG_DP_RX_FLOW_SEARCH_TABLE_PER_PDEV) \
Ruben Columbusb7a1c572019-08-12 11:11:29 -0700827 CFG(CFG_DP_RX_MON_PROTOCOL_FLOW_TAG_ENABLE) \
828 CFG(CFG_DP_RXDMA_MONITOR_RX_DROP_THRESHOLD)
Vivek126db5d2018-07-25 22:05:04 +0530829#endif /* _CFG_DP_H_ */