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Quentin Colombet2ad1f852016-02-11 17:44:59 +00001//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the MachineIRBuidler class.
11//===----------------------------------------------------------------------===//
12#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
13
14#include "llvm/CodeGen/MachineFunction.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
Tim Northover0f140c72016-09-09 11:46:34 +000017#include "llvm/CodeGen/MachineRegisterInfo.h"
Tim Northover09aac4a2017-01-26 23:39:14 +000018#include "llvm/IR/DebugInfo.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000019#include "llvm/Target/TargetInstrInfo.h"
Quentin Colombet8fd67182016-02-11 21:16:56 +000020#include "llvm/Target/TargetOpcodes.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000021#include "llvm/Target/TargetSubtargetInfo.h"
22
23using namespace llvm;
24
Quentin Colombet000b5802016-03-11 17:27:51 +000025void MachineIRBuilder::setMF(MachineFunction &MF) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000026 this->MF = &MF;
27 this->MBB = nullptr;
Tim Northover0f140c72016-09-09 11:46:34 +000028 this->MRI = &MF.getRegInfo();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000029 this->TII = MF.getSubtarget().getInstrInfo();
30 this->DL = DebugLoc();
Tim Northover05cc4852016-12-07 21:05:38 +000031 this->II = MachineBasicBlock::iterator();
Tim Northover438c77c2016-08-25 17:37:32 +000032 this->InsertedInstr = nullptr;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000033}
34
Tim Northover05cc4852016-12-07 21:05:38 +000035void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000036 this->MBB = &MBB;
Tim Northover05cc4852016-12-07 21:05:38 +000037 this->II = MBB.end();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000038 assert(&getMF() == MBB.getParent() &&
39 "Basic block is in a different function");
40}
41
Tim Northover05cc4852016-12-07 21:05:38 +000042void MachineIRBuilder::setInstr(MachineInstr &MI) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000043 assert(MI.getParent() && "Instruction is not part of a basic block");
Quentin Colombet91ebd712016-03-11 17:27:47 +000044 setMBB(*MI.getParent());
Tim Northover05cc4852016-12-07 21:05:38 +000045 this->II = MI.getIterator();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000046}
47
Tim Northover05cc4852016-12-07 21:05:38 +000048void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator II) {
50 assert(MBB.getParent() == &getMF() &&
51 "Basic block is in a different function");
52 this->MBB = &MBB;
53 this->II = II;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000054}
55
Tim Northover438c77c2016-08-25 17:37:32 +000056void MachineIRBuilder::recordInsertions(
57 std::function<void(MachineInstr *)> Inserted) {
Benjamin Kramer061f4a52017-01-13 14:39:03 +000058 InsertedInstr = std::move(Inserted);
Tim Northover438c77c2016-08-25 17:37:32 +000059}
60
61void MachineIRBuilder::stopRecordingInsertions() {
62 InsertedInstr = nullptr;
63}
64
Quentin Colombetf9b49342016-03-11 17:27:58 +000065//------------------------------------------------------------------------------
66// Build instruction variants.
67//------------------------------------------------------------------------------
Tim Northovercc5f7622016-07-26 16:45:26 +000068
Tim Northover0f140c72016-09-09 11:46:34 +000069MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
Tim Northovera5e38fa2016-09-22 13:49:25 +000070 return insertInstr(buildInstrNoInsert(Opcode));
71}
72
73MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
Tim Northovera51575f2016-07-29 17:43:52 +000074 MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode));
Tim Northovera5e38fa2016-09-22 13:49:25 +000075 return MIB;
76}
77
78
79MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
Tim Northovera51575f2016-07-29 17:43:52 +000080 getMBB().insert(getInsertPt(), MIB);
Tim Northover438c77c2016-08-25 17:37:32 +000081 if (InsertedInstr)
82 InsertedInstr(MIB);
Tim Northovera51575f2016-07-29 17:43:52 +000083 return MIB;
Quentin Colombet74d7d2f2016-02-11 18:53:28 +000084}
85
Adrian Prantlaac78ce2017-08-01 22:37:35 +000086MachineInstrBuilder
87MachineIRBuilder::buildDirectDbgValue(unsigned Reg, const MDNode *Variable,
88 const MDNode *Expr) {
Tim Northover09aac4a2017-01-26 23:39:14 +000089 assert(isa<DILocalVariable>(Variable) && "not a variable");
90 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
91 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
92 "Expected inlined-at fields to agree");
Adrian Prantlaac78ce2017-08-01 22:37:35 +000093 return insertInstr(BuildMI(getMF(), DL, getTII().get(TargetOpcode::DBG_VALUE),
94 /*IsIndirect*/ false, Reg, Variable, Expr));
Tim Northover09aac4a2017-01-26 23:39:14 +000095}
96
Adrian Prantld92ac5a2017-07-28 22:46:20 +000097MachineInstrBuilder
98MachineIRBuilder::buildIndirectDbgValue(unsigned Reg, const MDNode *Variable,
99 const MDNode *Expr) {
Tim Northover09aac4a2017-01-26 23:39:14 +0000100 assert(isa<DILocalVariable>(Variable) && "not a variable");
101 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
102 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
103 "Expected inlined-at fields to agree");
Adrian Prantlaac78ce2017-08-01 22:37:35 +0000104 return insertInstr(BuildMI(getMF(), DL, getTII().get(TargetOpcode::DBG_VALUE),
105 /*IsIndirect*/ true, Reg, Variable, Expr));
Tim Northover09aac4a2017-01-26 23:39:14 +0000106}
107
108MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
109 const MDNode *Variable,
110 const MDNode *Expr) {
111 assert(isa<DILocalVariable>(Variable) && "not a variable");
112 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
113 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
114 "Expected inlined-at fields to agree");
115 return buildInstr(TargetOpcode::DBG_VALUE)
116 .addFrameIndex(FI)
117 .addImm(0)
118 .addMetadata(Variable)
119 .addMetadata(Expr);
120}
121
122MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
Tim Northover09aac4a2017-01-26 23:39:14 +0000123 const MDNode *Variable,
124 const MDNode *Expr) {
125 assert(isa<DILocalVariable>(Variable) && "not a variable");
126 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
127 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
128 "Expected inlined-at fields to agree");
129 auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
130 if (auto *CI = dyn_cast<ConstantInt>(&C)) {
131 if (CI->getBitWidth() > 64)
132 MIB.addCImm(CI);
133 else
134 MIB.addImm(CI->getZExtValue());
Ahmed Bougacha4826bae2017-03-07 20:34:20 +0000135 } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
Ahmed Bougachaadce3ee2017-03-07 20:52:57 +0000136 MIB.addFPImm(CFP);
Ahmed Bougacha4826bae2017-03-07 20:34:20 +0000137 } else {
138 // Insert %noreg if we didn't find a usable constant and had to drop it.
139 MIB.addReg(0U);
140 }
Tim Northover09aac4a2017-01-26 23:39:14 +0000141
Adrian Prantld92ac5a2017-07-28 22:46:20 +0000142 return MIB.addImm(0).addMetadata(Variable).addMetadata(Expr);
Tim Northover09aac4a2017-01-26 23:39:14 +0000143}
144
Tim Northover0f140c72016-09-09 11:46:34 +0000145MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000146 assert(MRI->getType(Res).isPointer() && "invalid operand type");
Tim Northover0f140c72016-09-09 11:46:34 +0000147 return buildInstr(TargetOpcode::G_FRAME_INDEX)
Tim Northovera51575f2016-07-29 17:43:52 +0000148 .addDef(Res)
149 .addFrameIndex(Idx);
Tim Northoverbd505462016-07-22 16:59:52 +0000150}
Tim Northover33b07d62016-07-22 20:03:43 +0000151
Tim Northover032548f2016-09-12 12:10:41 +0000152MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
153 const GlobalValue *GV) {
154 assert(MRI->getType(Res).isPointer() && "invalid operand type");
155 assert(MRI->getType(Res).getAddressSpace() ==
156 GV->getType()->getAddressSpace() &&
157 "address space mismatch");
158
159 return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
160 .addDef(Res)
161 .addGlobalAddress(GV);
162}
163
Diana Picus05e704f2017-07-05 11:02:31 +0000164MachineInstrBuilder MachineIRBuilder::buildBinaryOp(unsigned Opcode, unsigned Res, unsigned Op0,
Tim Northover0f140c72016-09-09 11:46:34 +0000165 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000166 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
167 "invalid operand type");
168 assert(MRI->getType(Res) == MRI->getType(Op0) &&
169 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
170
Diana Picus05e704f2017-07-05 11:02:31 +0000171 return buildInstr(Opcode)
Tim Northovera51575f2016-07-29 17:43:52 +0000172 .addDef(Res)
173 .addUse(Op0)
174 .addUse(Op1);
Tim Northover33b07d62016-07-22 20:03:43 +0000175}
176
Diana Picus05e704f2017-07-05 11:02:31 +0000177MachineInstrBuilder MachineIRBuilder::buildAdd(unsigned Res, unsigned Op0,
178 unsigned Op1) {
179 return buildBinaryOp(TargetOpcode::G_ADD, Res, Op0, Op1);
180}
181
Tim Northovera7653b32016-09-12 11:20:22 +0000182MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
183 unsigned Op1) {
184 assert(MRI->getType(Res).isPointer() &&
185 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
186 assert(MRI->getType(Op1).isScalar() && "invalid offset type");
187
188 return buildInstr(TargetOpcode::G_GEP)
189 .addDef(Res)
190 .addUse(Op0)
191 .addUse(Op1);
192}
193
Daniel Sanders4e523662017-06-13 23:42:32 +0000194Optional<MachineInstrBuilder>
195MachineIRBuilder::materializeGEP(unsigned &Res, unsigned Op0,
196 const LLT &ValueTy, uint64_t Value) {
197 assert(Res == 0 && "Res is a result argument");
198 assert(ValueTy.isScalar() && "invalid offset type");
199
200 if (Value == 0) {
201 Res = Op0;
202 return None;
203 }
204
205 Res = MRI->createGenericVirtualRegister(MRI->getType(Op0));
206 unsigned TmpReg = MRI->createGenericVirtualRegister(ValueTy);
207
208 buildConstant(TmpReg, Value);
209 return buildGEP(Res, Op0, TmpReg);
210}
211
Tim Northoverc2f89562017-02-14 20:56:18 +0000212MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
213 uint32_t NumBits) {
214 assert(MRI->getType(Res).isPointer() &&
215 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
216
217 return buildInstr(TargetOpcode::G_PTR_MASK)
218 .addDef(Res)
219 .addUse(Op0)
220 .addImm(NumBits);
221}
222
Tim Northover0f140c72016-09-09 11:46:34 +0000223MachineInstrBuilder MachineIRBuilder::buildSub(unsigned Res, unsigned Op0,
224 unsigned Op1) {
Diana Picus05e704f2017-07-05 11:02:31 +0000225 return buildBinaryOp(TargetOpcode::G_SUB, Res, Op0, Op1);
Tim Northovercecee562016-08-26 17:46:13 +0000226}
227
Tim Northover0f140c72016-09-09 11:46:34 +0000228MachineInstrBuilder MachineIRBuilder::buildMul(unsigned Res, unsigned Op0,
229 unsigned Op1) {
Diana Picus05e704f2017-07-05 11:02:31 +0000230 return buildBinaryOp(TargetOpcode::G_MUL, Res, Op0, Op1);
Tim Northovercecee562016-08-26 17:46:13 +0000231}
232
Tim Northoverc3e3f592017-02-03 18:22:45 +0000233MachineInstrBuilder MachineIRBuilder::buildAnd(unsigned Res, unsigned Op0,
234 unsigned Op1) {
Diana Picus05e704f2017-07-05 11:02:31 +0000235 return buildBinaryOp(TargetOpcode::G_AND, Res, Op0, Op1);
Tim Northoverc3e3f592017-02-03 18:22:45 +0000236}
237
Diana Picus3e40b462017-07-05 11:32:12 +0000238MachineInstrBuilder MachineIRBuilder::buildOr(unsigned Res, unsigned Op0,
Diana Picus97a5d9b2017-07-05 11:47:23 +0000239 unsigned Op1) {
Diana Picus3e40b462017-07-05 11:32:12 +0000240 return buildBinaryOp(TargetOpcode::G_OR, Res, Op0, Op1);
241}
Diana Picus05e704f2017-07-05 11:02:31 +0000242
Tim Northovera51575f2016-07-29 17:43:52 +0000243MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
Tim Northover0f140c72016-09-09 11:46:34 +0000244 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
Tim Northovercc5f7622016-07-26 16:45:26 +0000245}
246
Kristof Beyls65a12c02017-01-30 09:13:18 +0000247MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) {
Tim Northoverc9902362017-06-27 22:45:35 +0000248 assert(MRI->getType(Tgt).isPointer() && "invalid branch destination");
Kristof Beyls65a12c02017-01-30 09:13:18 +0000249 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
250}
251
Tim Northovera51575f2016-07-29 17:43:52 +0000252MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) {
Tim Northover849fcca2017-06-27 21:41:40 +0000253 assert(MRI->getType(Res) == LLT() || MRI->getType(Op) == LLT() ||
254 MRI->getType(Res) == MRI->getType(Op));
Tim Northovera51575f2016-07-29 17:43:52 +0000255 return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
Tim Northover756eca32016-07-26 16:45:30 +0000256}
257
Tim Northover9267ac52016-12-05 21:47:07 +0000258MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
259 const ConstantInt &Val) {
260 LLT Ty = MRI->getType(Res);
Tim Northover1f8b1db2016-09-09 11:46:58 +0000261
Sam McCall03435f52016-12-06 10:14:36 +0000262 assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type");
Tim Northover9267ac52016-12-05 21:47:07 +0000263
264 const ConstantInt *NewVal = &Val;
265 if (Ty.getSizeInBits() != Val.getBitWidth())
266 NewVal = ConstantInt::get(MF->getFunction()->getContext(),
267 Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
268
269 return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal);
270}
271
272MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
273 int64_t Val) {
274 auto IntN = IntegerType::get(MF->getFunction()->getContext(),
275 MRI->getType(Res).getSizeInBits());
276 ConstantInt *CI = ConstantInt::get(IntN, Val, true);
277 return buildConstant(Res, *CI);
Tim Northover9656f142016-08-04 20:54:13 +0000278}
279
Tim Northover0f140c72016-09-09 11:46:34 +0000280MachineInstrBuilder MachineIRBuilder::buildFConstant(unsigned Res,
281 const ConstantFP &Val) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000282 assert(MRI->getType(Res).isScalar() && "invalid operand type");
283
Tim Northover0f140c72016-09-09 11:46:34 +0000284 return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val);
Tim Northoverb16734f2016-08-19 20:09:15 +0000285}
286
Tim Northover0f140c72016-09-09 11:46:34 +0000287MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
Tim Northover69c2ba52016-07-29 17:58:00 +0000288 MachineBasicBlock &Dest) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000289 assert(MRI->getType(Tst).isScalar() && "invalid operand type");
290
Tim Northover0f140c72016-09-09 11:46:34 +0000291 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
Tim Northover69c2ba52016-07-29 17:58:00 +0000292}
293
Tim Northover0f140c72016-09-09 11:46:34 +0000294MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
295 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000296 assert(MRI->getType(Res).isValid() && "invalid operand type");
297 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
298
Tim Northover0f140c72016-09-09 11:46:34 +0000299 return buildInstr(TargetOpcode::G_LOAD)
Tim Northovera51575f2016-07-29 17:43:52 +0000300 .addDef(Res)
301 .addUse(Addr)
302 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000303}
304
Tim Northover0f140c72016-09-09 11:46:34 +0000305MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
306 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000307 assert(MRI->getType(Val).isValid() && "invalid operand type");
308 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
309
Tim Northover0f140c72016-09-09 11:46:34 +0000310 return buildInstr(TargetOpcode::G_STORE)
Tim Northovera51575f2016-07-29 17:43:52 +0000311 .addUse(Val)
312 .addUse(Addr)
313 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000314}
315
Tim Northover0f140c72016-09-09 11:46:34 +0000316MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res,
317 unsigned CarryOut,
318 unsigned Op0, unsigned Op1,
319 unsigned CarryIn) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000320 assert(MRI->getType(Res).isScalar() && "invalid operand type");
321 assert(MRI->getType(Res) == MRI->getType(Op0) &&
322 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
323 assert(MRI->getType(CarryOut).isScalar() && "invalid operand type");
324 assert(MRI->getType(CarryOut) == MRI->getType(CarryIn) && "type mismatch");
325
Tim Northover0f140c72016-09-09 11:46:34 +0000326 return buildInstr(TargetOpcode::G_UADDE)
Tim Northover9656f142016-08-04 20:54:13 +0000327 .addDef(Res)
328 .addDef(CarryOut)
329 .addUse(Op0)
330 .addUse(Op1)
331 .addUse(CarryIn);
332}
333
Tim Northover0f140c72016-09-09 11:46:34 +0000334MachineInstrBuilder MachineIRBuilder::buildAnyExt(unsigned Res, unsigned Op) {
335 validateTruncExt(Res, Op, true);
336 return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000337}
338
Tim Northover0f140c72016-09-09 11:46:34 +0000339MachineInstrBuilder MachineIRBuilder::buildSExt(unsigned Res, unsigned Op) {
340 validateTruncExt(Res, Op, true);
341 return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000342}
343
Tim Northover0f140c72016-09-09 11:46:34 +0000344MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) {
345 validateTruncExt(Res, Op, true);
346 return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000347}
348
Tim Northovera7653b32016-09-12 11:20:22 +0000349MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res,
350 unsigned Op) {
Tim Northoverc9902362017-06-27 22:45:35 +0000351 assert(MRI->getType(Res).isScalar() || MRI->getType(Res).isVector());
352 assert(MRI->getType(Res).isScalar() == MRI->getType(Op).isScalar());
353
Tim Northovera7653b32016-09-12 11:20:22 +0000354 unsigned Opcode = TargetOpcode::COPY;
355 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
356 Opcode = TargetOpcode::G_SEXT;
357 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
358 Opcode = TargetOpcode::G_TRUNC;
Tim Northoverc9902362017-06-27 22:45:35 +0000359 else
360 assert(MRI->getType(Res) == MRI->getType(Op));
Tim Northovera7653b32016-09-12 11:20:22 +0000361
362 return buildInstr(Opcode).addDef(Res).addUse(Op);
363}
364
Tim Northoverc3e3f592017-02-03 18:22:45 +0000365MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(unsigned Res,
366 unsigned Op) {
Tim Northoverc9902362017-06-27 22:45:35 +0000367 assert(MRI->getType(Res).isScalar() || MRI->getType(Res).isVector());
368 assert(MRI->getType(Res).isScalar() == MRI->getType(Op).isScalar());
369
Tim Northoverc3e3f592017-02-03 18:22:45 +0000370 unsigned Opcode = TargetOpcode::COPY;
371 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
372 Opcode = TargetOpcode::G_ZEXT;
373 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
374 Opcode = TargetOpcode::G_TRUNC;
Tim Northoverc9902362017-06-27 22:45:35 +0000375 else
376 assert(MRI->getType(Res) == MRI->getType(Op));
Tim Northoverc3e3f592017-02-03 18:22:45 +0000377
378 return buildInstr(Opcode).addDef(Res).addUse(Op);
379}
380
Tim Northover95b6d5f2017-03-06 19:04:17 +0000381MachineInstrBuilder MachineIRBuilder::buildCast(unsigned Dst, unsigned Src) {
382 LLT SrcTy = MRI->getType(Src);
383 LLT DstTy = MRI->getType(Dst);
384 if (SrcTy == DstTy)
385 return buildCopy(Dst, Src);
386
387 unsigned Opcode;
388 if (SrcTy.isPointer() && DstTy.isScalar())
389 Opcode = TargetOpcode::G_PTRTOINT;
390 else if (DstTy.isPointer() && SrcTy.isScalar())
391 Opcode = TargetOpcode::G_INTTOPTR;
392 else {
393 assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
394 Opcode = TargetOpcode::G_BITCAST;
395 }
396
397 return buildInstr(Opcode).addDef(Dst).addUse(Src);
398}
399
Tim Northoverc2c545b2017-03-06 23:50:28 +0000400MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src,
401 uint64_t Index) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000402#ifndef NDEBUG
Tim Northover1f8b1db2016-09-09 11:46:58 +0000403 assert(MRI->getType(Src).isValid() && "invalid operand type");
Tim Northoverc2c545b2017-03-06 23:50:28 +0000404 assert(MRI->getType(Res).isValid() && "invalid operand type");
405 assert(Index + MRI->getType(Res).getSizeInBits() <=
406 MRI->getType(Src).getSizeInBits() &&
407 "extracting off end of register");
Tim Northover1f8b1db2016-09-09 11:46:58 +0000408#endif
409
Tim Northoverc2c545b2017-03-06 23:50:28 +0000410 if (MRI->getType(Res).getSizeInBits() == MRI->getType(Src).getSizeInBits()) {
411 assert(Index == 0 && "insertion past the end of a register");
412 return buildCast(Res, Src);
413 }
Tim Northover33b07d62016-07-22 20:03:43 +0000414
Tim Northoverc2c545b2017-03-06 23:50:28 +0000415 return buildInstr(TargetOpcode::G_EXTRACT)
416 .addDef(Res)
417 .addUse(Src)
418 .addImm(Index);
Tim Northover33b07d62016-07-22 20:03:43 +0000419}
420
Tim Northoverb57bf2a2017-06-23 16:15:37 +0000421void MachineIRBuilder::buildSequence(unsigned Res, ArrayRef<unsigned> Ops,
422 ArrayRef<uint64_t> Indices) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000423#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000424 assert(Ops.size() == Indices.size() && "incompatible args");
Tim Northover26b76f22016-08-19 18:32:14 +0000425 assert(!Ops.empty() && "invalid trivial sequence");
Tim Northover991b12b2016-08-30 20:51:25 +0000426 assert(std::is_sorted(Indices.begin(), Indices.end()) &&
427 "sequence offsets must be in ascending order");
Tim Northover91c81732016-08-19 17:17:06 +0000428
Tim Northover1f8b1db2016-09-09 11:46:58 +0000429 assert(MRI->getType(Res).isValid() && "invalid operand type");
430 for (auto Op : Ops)
431 assert(MRI->getType(Op).isValid() && "invalid operand type");
432#endif
433
Tim Northoverb57bf2a2017-06-23 16:15:37 +0000434 LLT ResTy = MRI->getType(Res);
435 LLT OpTy = MRI->getType(Ops[0]);
436 unsigned OpSize = OpTy.getSizeInBits();
437 bool MaybeMerge = true;
Tim Northover91c81732016-08-19 17:17:06 +0000438 for (unsigned i = 0; i < Ops.size(); ++i) {
Tim Northoverb57bf2a2017-06-23 16:15:37 +0000439 if (MRI->getType(Ops[i]) != OpTy || Indices[i] != i * OpSize) {
440 MaybeMerge = false;
441 break;
442 }
Tim Northover91c81732016-08-19 17:17:06 +0000443 }
Tim Northoverb57bf2a2017-06-23 16:15:37 +0000444
445 if (MaybeMerge && Ops.size() * OpSize == ResTy.getSizeInBits()) {
446 buildMerge(Res, Ops);
447 return;
448 }
449
450 unsigned ResIn = MRI->createGenericVirtualRegister(ResTy);
451 buildUndef(ResIn);
452
453 for (unsigned i = 0; i < Ops.size(); ++i) {
454 unsigned ResOut =
455 i + 1 == Ops.size() ? Res : MRI->createGenericVirtualRegister(ResTy);
456 buildInsert(ResOut, ResIn, Ops[i], Indices[i]);
457 ResIn = ResOut;
458 }
Tim Northover33b07d62016-07-22 20:03:43 +0000459}
Tim Northover5fb414d2016-07-29 22:32:36 +0000460
Tim Northover81dafc12017-03-06 18:36:40 +0000461MachineInstrBuilder MachineIRBuilder::buildUndef(unsigned Res) {
Tim Northoverff5e7e12017-06-30 20:27:36 +0000462 return buildInstr(TargetOpcode::G_IMPLICIT_DEF).addDef(Res);
Tim Northover81dafc12017-03-06 18:36:40 +0000463}
464
Tim Northoverbf017292017-03-03 22:46:09 +0000465MachineInstrBuilder MachineIRBuilder::buildMerge(unsigned Res,
466 ArrayRef<unsigned> Ops) {
467
468#ifndef NDEBUG
469 assert(!Ops.empty() && "invalid trivial sequence");
470 LLT Ty = MRI->getType(Ops[0]);
471 for (auto Reg : Ops)
472 assert(MRI->getType(Reg) == Ty && "type mismatch in input list");
473 assert(Ops.size() * MRI->getType(Ops[0]).getSizeInBits() ==
474 MRI->getType(Res).getSizeInBits() &&
475 "input operands do not cover output register");
476#endif
477
Tim Northoverc2d5e6d2017-06-26 20:34:13 +0000478 if (Ops.size() == 1)
Tim Northover849fcca2017-06-27 21:41:40 +0000479 return buildCast(Res, Ops[0]);
Tim Northoverc2d5e6d2017-06-26 20:34:13 +0000480
Tim Northoverbf017292017-03-03 22:46:09 +0000481 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_MERGE_VALUES);
482 MIB.addDef(Res);
483 for (unsigned i = 0; i < Ops.size(); ++i)
484 MIB.addUse(Ops[i]);
485 return MIB;
486}
487
488MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
489 unsigned Op) {
490
491#ifndef NDEBUG
492 assert(!Res.empty() && "invalid trivial sequence");
493 LLT Ty = MRI->getType(Res[0]);
494 for (auto Reg : Res)
495 assert(MRI->getType(Reg) == Ty && "type mismatch in input list");
496 assert(Res.size() * MRI->getType(Res[0]).getSizeInBits() ==
497 MRI->getType(Op).getSizeInBits() &&
498 "input operands do not cover output register");
499#endif
500
501 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_UNMERGE_VALUES);
502 for (unsigned i = 0; i < Res.size(); ++i)
503 MIB.addDef(Res[i]);
504 MIB.addUse(Op);
505 return MIB;
506}
507
Tim Northover3e6a7af2017-03-03 23:05:47 +0000508MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
509 unsigned Op, unsigned Index) {
Tim Northoverc9902362017-06-27 22:45:35 +0000510 assert(Index + MRI->getType(Op).getSizeInBits() <=
511 MRI->getType(Res).getSizeInBits() &&
512 "insertion past the end of a register");
513
Tim Northover95b6d5f2017-03-06 19:04:17 +0000514 if (MRI->getType(Res).getSizeInBits() == MRI->getType(Op).getSizeInBits()) {
Tim Northover95b6d5f2017-03-06 19:04:17 +0000515 return buildCast(Res, Op);
516 }
517
Tim Northover3e6a7af2017-03-03 23:05:47 +0000518 return buildInstr(TargetOpcode::G_INSERT)
519 .addDef(Res)
520 .addUse(Src)
521 .addUse(Op)
522 .addImm(Index);
523}
524
Tim Northover0f140c72016-09-09 11:46:34 +0000525MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
Tim Northover5fb414d2016-07-29 22:32:36 +0000526 unsigned Res,
527 bool HasSideEffects) {
528 auto MIB =
529 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
Tim Northover0f140c72016-09-09 11:46:34 +0000530 : TargetOpcode::G_INTRINSIC);
Tim Northover5fb414d2016-07-29 22:32:36 +0000531 if (Res)
532 MIB.addDef(Res);
533 MIB.addIntrinsicID(ID);
534 return MIB;
535}
Tim Northover32335812016-08-04 18:35:11 +0000536
Tim Northover0f140c72016-09-09 11:46:34 +0000537MachineInstrBuilder MachineIRBuilder::buildTrunc(unsigned Res, unsigned Op) {
538 validateTruncExt(Res, Op, false);
539 return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000540}
Tim Northoverde3aea0412016-08-17 20:25:25 +0000541
Tim Northover0f140c72016-09-09 11:46:34 +0000542MachineInstrBuilder MachineIRBuilder::buildFPTrunc(unsigned Res, unsigned Op) {
543 validateTruncExt(Res, Op, false);
544 return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op);
Tim Northovera11be042016-08-19 22:40:08 +0000545}
546
Tim Northover0f140c72016-09-09 11:46:34 +0000547MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
Tim Northoverde3aea0412016-08-17 20:25:25 +0000548 unsigned Res, unsigned Op0,
549 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000550#ifndef NDEBUG
Tim Northover1f8b1db2016-09-09 11:46:58 +0000551 assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch");
552 assert(CmpInst::isIntPredicate(Pred) && "invalid predicate");
Tim Northover4cf0a482016-09-15 10:40:38 +0000553 if (MRI->getType(Op0).isScalar() || MRI->getType(Op0).isPointer())
Tim Northover1f8b1db2016-09-09 11:46:58 +0000554 assert(MRI->getType(Res).isScalar() && "type mismatch");
555 else
556 assert(MRI->getType(Res).isVector() &&
557 MRI->getType(Res).getNumElements() ==
558 MRI->getType(Op0).getNumElements() &&
559 "type mismatch");
560#endif
561
Tim Northover0f140c72016-09-09 11:46:34 +0000562 return buildInstr(TargetOpcode::G_ICMP)
Tim Northoverde3aea0412016-08-17 20:25:25 +0000563 .addDef(Res)
564 .addPredicate(Pred)
565 .addUse(Op0)
566 .addUse(Op1);
567}
Tim Northover5a28c362016-08-19 20:09:07 +0000568
Tim Northover0f140c72016-09-09 11:46:34 +0000569MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000570 unsigned Res, unsigned Op0,
571 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000572#ifndef NDEBUG
573 assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) &&
574 "invalid operand type");
575 assert(MRI->getType(Op0) == MRI->getType(Op1) && "type mismatch");
576 assert(CmpInst::isFPPredicate(Pred) && "invalid predicate");
577 if (MRI->getType(Op0).isScalar())
578 assert(MRI->getType(Res).isScalar() && "type mismatch");
579 else
580 assert(MRI->getType(Res).isVector() &&
581 MRI->getType(Res).getNumElements() ==
582 MRI->getType(Op0).getNumElements() &&
583 "type mismatch");
584#endif
585
Tim Northover0f140c72016-09-09 11:46:34 +0000586 return buildInstr(TargetOpcode::G_FCMP)
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000587 .addDef(Res)
588 .addPredicate(Pred)
589 .addUse(Op0)
590 .addUse(Op1);
591}
592
Tim Northover0f140c72016-09-09 11:46:34 +0000593MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst,
Tim Northover5a28c362016-08-19 20:09:07 +0000594 unsigned Op0, unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000595#ifndef NDEBUG
Tim Northoverf50f2f32016-12-06 18:38:34 +0000596 LLT ResTy = MRI->getType(Res);
597 assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
Tim Northover1f8b1db2016-09-09 11:46:58 +0000598 "invalid operand type");
Tim Northoverf50f2f32016-12-06 18:38:34 +0000599 assert(ResTy == MRI->getType(Op0) && ResTy == MRI->getType(Op1) &&
600 "type mismatch");
601 if (ResTy.isScalar() || ResTy.isPointer())
Tim Northover1f8b1db2016-09-09 11:46:58 +0000602 assert(MRI->getType(Tst).isScalar() && "type mismatch");
603 else
Ahmed Bougacha38455ea2017-03-07 20:53:03 +0000604 assert((MRI->getType(Tst).isScalar() ||
605 (MRI->getType(Tst).isVector() &&
606 MRI->getType(Tst).getNumElements() ==
607 MRI->getType(Op0).getNumElements())) &&
Tim Northover1f8b1db2016-09-09 11:46:58 +0000608 "type mismatch");
609#endif
610
Tim Northover0f140c72016-09-09 11:46:34 +0000611 return buildInstr(TargetOpcode::G_SELECT)
Tim Northover5a28c362016-08-19 20:09:07 +0000612 .addDef(Res)
613 .addUse(Tst)
614 .addUse(Op0)
615 .addUse(Op1);
616}
Tim Northoverbdf67c92016-08-23 21:01:33 +0000617
Volkan Keles04cb08c2017-03-10 19:08:28 +0000618MachineInstrBuilder MachineIRBuilder::buildInsertVectorElement(unsigned Res,
619 unsigned Val,
620 unsigned Elt,
621 unsigned Idx) {
622#ifndef NDEBUG
623 LLT ResTy = MRI->getType(Res);
624 LLT ValTy = MRI->getType(Val);
625 LLT EltTy = MRI->getType(Elt);
626 LLT IdxTy = MRI->getType(Idx);
627 assert(ResTy.isVector() && ValTy.isVector() && "invalid operand type");
Kristof Beyls0f36e682017-04-19 07:23:57 +0000628 assert(IdxTy.isScalar() && "invalid operand type");
Volkan Keles04cb08c2017-03-10 19:08:28 +0000629 assert(ResTy.getNumElements() == ValTy.getNumElements() && "type mismatch");
630 assert(ResTy.getElementType() == EltTy && "type mismatch");
631#endif
632
633 return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT)
634 .addDef(Res)
635 .addUse(Val)
636 .addUse(Elt)
637 .addUse(Idx);
638}
639
640MachineInstrBuilder MachineIRBuilder::buildExtractVectorElement(unsigned Res,
641 unsigned Val,
642 unsigned Idx) {
643#ifndef NDEBUG
644 LLT ResTy = MRI->getType(Res);
645 LLT ValTy = MRI->getType(Val);
646 LLT IdxTy = MRI->getType(Idx);
647 assert(ValTy.isVector() && "invalid operand type");
Kristof Beyls0f36e682017-04-19 07:23:57 +0000648 assert((ResTy.isScalar() || ResTy.isPointer()) && "invalid operand type");
649 assert(IdxTy.isScalar() && "invalid operand type");
Volkan Keles04cb08c2017-03-10 19:08:28 +0000650 assert(ValTy.getElementType() == ResTy && "type mismatch");
651#endif
652
653 return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT)
654 .addDef(Res)
655 .addUse(Val)
656 .addUse(Idx);
657}
658
Tim Northover0f140c72016-09-09 11:46:34 +0000659void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src,
660 bool IsExtend) {
Richard Smith418237b2016-08-23 22:14:15 +0000661#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000662 LLT SrcTy = MRI->getType(Src);
663 LLT DstTy = MRI->getType(Dst);
Tim Northoverbdf67c92016-08-23 21:01:33 +0000664
665 if (DstTy.isVector()) {
666 assert(SrcTy.isVector() && "mismatched cast between vecot and non-vector");
667 assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
668 "different number of elements in a trunc/ext");
669 } else
670 assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
671
672 if (IsExtend)
673 assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
674 "invalid narrowing extend");
675 else
676 assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
677 "invalid widening trunc");
Richard Smith418237b2016-08-23 22:14:15 +0000678#endif
Tim Northoverbdf67c92016-08-23 21:01:33 +0000679}