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Quentin Colombet2ad1f852016-02-11 17:44:59 +00001//===-- llvm/CodeGen/GlobalISel/MachineIRBuilder.cpp - MIBuilder--*- C++ -*-==//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9/// \file
10/// This file implements the MachineIRBuidler class.
11//===----------------------------------------------------------------------===//
12#include "llvm/CodeGen/GlobalISel/MachineIRBuilder.h"
13
14#include "llvm/CodeGen/MachineFunction.h"
15#include "llvm/CodeGen/MachineInstr.h"
16#include "llvm/CodeGen/MachineInstrBuilder.h"
Tim Northover0f140c72016-09-09 11:46:34 +000017#include "llvm/CodeGen/MachineRegisterInfo.h"
Tim Northover09aac4a2017-01-26 23:39:14 +000018#include "llvm/IR/DebugInfo.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000019#include "llvm/Target/TargetInstrInfo.h"
Quentin Colombet8fd67182016-02-11 21:16:56 +000020#include "llvm/Target/TargetOpcodes.h"
Quentin Colombet2ad1f852016-02-11 17:44:59 +000021#include "llvm/Target/TargetSubtargetInfo.h"
22
23using namespace llvm;
24
Quentin Colombet000b5802016-03-11 17:27:51 +000025void MachineIRBuilder::setMF(MachineFunction &MF) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000026 this->MF = &MF;
27 this->MBB = nullptr;
Tim Northover0f140c72016-09-09 11:46:34 +000028 this->MRI = &MF.getRegInfo();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000029 this->TII = MF.getSubtarget().getInstrInfo();
30 this->DL = DebugLoc();
Tim Northover05cc4852016-12-07 21:05:38 +000031 this->II = MachineBasicBlock::iterator();
Tim Northover438c77c2016-08-25 17:37:32 +000032 this->InsertedInstr = nullptr;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000033}
34
Tim Northover05cc4852016-12-07 21:05:38 +000035void MachineIRBuilder::setMBB(MachineBasicBlock &MBB) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000036 this->MBB = &MBB;
Tim Northover05cc4852016-12-07 21:05:38 +000037 this->II = MBB.end();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000038 assert(&getMF() == MBB.getParent() &&
39 "Basic block is in a different function");
40}
41
Tim Northover05cc4852016-12-07 21:05:38 +000042void MachineIRBuilder::setInstr(MachineInstr &MI) {
Quentin Colombet2ad1f852016-02-11 17:44:59 +000043 assert(MI.getParent() && "Instruction is not part of a basic block");
Quentin Colombet91ebd712016-03-11 17:27:47 +000044 setMBB(*MI.getParent());
Tim Northover05cc4852016-12-07 21:05:38 +000045 this->II = MI.getIterator();
Quentin Colombet2ad1f852016-02-11 17:44:59 +000046}
47
Tim Northover05cc4852016-12-07 21:05:38 +000048void MachineIRBuilder::setInsertPt(MachineBasicBlock &MBB,
49 MachineBasicBlock::iterator II) {
50 assert(MBB.getParent() == &getMF() &&
51 "Basic block is in a different function");
52 this->MBB = &MBB;
53 this->II = II;
Quentin Colombet2ad1f852016-02-11 17:44:59 +000054}
55
Tim Northover438c77c2016-08-25 17:37:32 +000056void MachineIRBuilder::recordInsertions(
57 std::function<void(MachineInstr *)> Inserted) {
Benjamin Kramer061f4a52017-01-13 14:39:03 +000058 InsertedInstr = std::move(Inserted);
Tim Northover438c77c2016-08-25 17:37:32 +000059}
60
61void MachineIRBuilder::stopRecordingInsertions() {
62 InsertedInstr = nullptr;
63}
64
Quentin Colombetf9b49342016-03-11 17:27:58 +000065//------------------------------------------------------------------------------
66// Build instruction variants.
67//------------------------------------------------------------------------------
Tim Northovercc5f7622016-07-26 16:45:26 +000068
Tim Northover0f140c72016-09-09 11:46:34 +000069MachineInstrBuilder MachineIRBuilder::buildInstr(unsigned Opcode) {
Tim Northovera5e38fa2016-09-22 13:49:25 +000070 return insertInstr(buildInstrNoInsert(Opcode));
71}
72
73MachineInstrBuilder MachineIRBuilder::buildInstrNoInsert(unsigned Opcode) {
Tim Northovera51575f2016-07-29 17:43:52 +000074 MachineInstrBuilder MIB = BuildMI(getMF(), DL, getTII().get(Opcode));
Tim Northovera5e38fa2016-09-22 13:49:25 +000075 return MIB;
76}
77
78
79MachineInstrBuilder MachineIRBuilder::insertInstr(MachineInstrBuilder MIB) {
Tim Northovera51575f2016-07-29 17:43:52 +000080 getMBB().insert(getInsertPt(), MIB);
Tim Northover438c77c2016-08-25 17:37:32 +000081 if (InsertedInstr)
82 InsertedInstr(MIB);
Tim Northovera51575f2016-07-29 17:43:52 +000083 return MIB;
Quentin Colombet74d7d2f2016-02-11 18:53:28 +000084}
85
Tim Northover09aac4a2017-01-26 23:39:14 +000086MachineInstrBuilder MachineIRBuilder::buildDirectDbgValue(
87 unsigned Reg, const MDNode *Variable, const MDNode *Expr) {
88 assert(isa<DILocalVariable>(Variable) && "not a variable");
89 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
90 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
91 "Expected inlined-at fields to agree");
92 return buildInstr(TargetOpcode::DBG_VALUE)
93 .addReg(Reg, RegState::Debug)
94 .addReg(0, RegState::Debug)
95 .addMetadata(Variable)
96 .addMetadata(Expr);
97}
98
99MachineInstrBuilder MachineIRBuilder::buildIndirectDbgValue(
100 unsigned Reg, unsigned Offset, const MDNode *Variable, const MDNode *Expr) {
101 assert(isa<DILocalVariable>(Variable) && "not a variable");
102 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
103 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
104 "Expected inlined-at fields to agree");
105 return buildInstr(TargetOpcode::DBG_VALUE)
106 .addReg(Reg, RegState::Debug)
107 .addImm(Offset)
108 .addMetadata(Variable)
109 .addMetadata(Expr);
110}
111
112MachineInstrBuilder MachineIRBuilder::buildFIDbgValue(int FI,
113 const MDNode *Variable,
114 const MDNode *Expr) {
115 assert(isa<DILocalVariable>(Variable) && "not a variable");
116 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
117 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
118 "Expected inlined-at fields to agree");
119 return buildInstr(TargetOpcode::DBG_VALUE)
120 .addFrameIndex(FI)
121 .addImm(0)
122 .addMetadata(Variable)
123 .addMetadata(Expr);
124}
125
126MachineInstrBuilder MachineIRBuilder::buildConstDbgValue(const Constant &C,
127 unsigned Offset,
128 const MDNode *Variable,
129 const MDNode *Expr) {
130 assert(isa<DILocalVariable>(Variable) && "not a variable");
131 assert(cast<DIExpression>(Expr)->isValid() && "not an expression");
132 assert(cast<DILocalVariable>(Variable)->isValidLocationForIntrinsic(DL) &&
133 "Expected inlined-at fields to agree");
134 auto MIB = buildInstr(TargetOpcode::DBG_VALUE);
135 if (auto *CI = dyn_cast<ConstantInt>(&C)) {
136 if (CI->getBitWidth() > 64)
137 MIB.addCImm(CI);
138 else
139 MIB.addImm(CI->getZExtValue());
Ahmed Bougacha4826bae2017-03-07 20:34:20 +0000140 } else if (auto *CFP = dyn_cast<ConstantFP>(&C)) {
Ahmed Bougachaadce3ee2017-03-07 20:52:57 +0000141 MIB.addFPImm(CFP);
Ahmed Bougacha4826bae2017-03-07 20:34:20 +0000142 } else {
143 // Insert %noreg if we didn't find a usable constant and had to drop it.
144 MIB.addReg(0U);
145 }
Tim Northover09aac4a2017-01-26 23:39:14 +0000146
147 return MIB.addImm(Offset).addMetadata(Variable).addMetadata(Expr);
148}
149
Tim Northover0f140c72016-09-09 11:46:34 +0000150MachineInstrBuilder MachineIRBuilder::buildFrameIndex(unsigned Res, int Idx) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000151 assert(MRI->getType(Res).isPointer() && "invalid operand type");
Tim Northover0f140c72016-09-09 11:46:34 +0000152 return buildInstr(TargetOpcode::G_FRAME_INDEX)
Tim Northovera51575f2016-07-29 17:43:52 +0000153 .addDef(Res)
154 .addFrameIndex(Idx);
Tim Northoverbd505462016-07-22 16:59:52 +0000155}
Tim Northover33b07d62016-07-22 20:03:43 +0000156
Tim Northover032548f2016-09-12 12:10:41 +0000157MachineInstrBuilder MachineIRBuilder::buildGlobalValue(unsigned Res,
158 const GlobalValue *GV) {
159 assert(MRI->getType(Res).isPointer() && "invalid operand type");
160 assert(MRI->getType(Res).getAddressSpace() ==
161 GV->getType()->getAddressSpace() &&
162 "address space mismatch");
163
164 return buildInstr(TargetOpcode::G_GLOBAL_VALUE)
165 .addDef(Res)
166 .addGlobalAddress(GV);
167}
168
Tim Northover0f140c72016-09-09 11:46:34 +0000169MachineInstrBuilder MachineIRBuilder::buildAdd(unsigned Res, unsigned Op0,
170 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000171 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
172 "invalid operand type");
173 assert(MRI->getType(Res) == MRI->getType(Op0) &&
174 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
175
Tim Northover0f140c72016-09-09 11:46:34 +0000176 return buildInstr(TargetOpcode::G_ADD)
Tim Northovera51575f2016-07-29 17:43:52 +0000177 .addDef(Res)
178 .addUse(Op0)
179 .addUse(Op1);
Tim Northover33b07d62016-07-22 20:03:43 +0000180}
181
Tim Northovera7653b32016-09-12 11:20:22 +0000182MachineInstrBuilder MachineIRBuilder::buildGEP(unsigned Res, unsigned Op0,
183 unsigned Op1) {
184 assert(MRI->getType(Res).isPointer() &&
185 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
186 assert(MRI->getType(Op1).isScalar() && "invalid offset type");
187
188 return buildInstr(TargetOpcode::G_GEP)
189 .addDef(Res)
190 .addUse(Op0)
191 .addUse(Op1);
192}
193
Tim Northoverc2f89562017-02-14 20:56:18 +0000194MachineInstrBuilder MachineIRBuilder::buildPtrMask(unsigned Res, unsigned Op0,
195 uint32_t NumBits) {
196 assert(MRI->getType(Res).isPointer() &&
197 MRI->getType(Res) == MRI->getType(Op0) && "type mismatch");
198
199 return buildInstr(TargetOpcode::G_PTR_MASK)
200 .addDef(Res)
201 .addUse(Op0)
202 .addImm(NumBits);
203}
204
Tim Northover0f140c72016-09-09 11:46:34 +0000205MachineInstrBuilder MachineIRBuilder::buildSub(unsigned Res, unsigned Op0,
206 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000207 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
208 "invalid operand type");
209 assert(MRI->getType(Res) == MRI->getType(Op0) &&
210 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
211
Tim Northover0f140c72016-09-09 11:46:34 +0000212 return buildInstr(TargetOpcode::G_SUB)
Tim Northovercecee562016-08-26 17:46:13 +0000213 .addDef(Res)
214 .addUse(Op0)
215 .addUse(Op1);
216}
217
Tim Northover0f140c72016-09-09 11:46:34 +0000218MachineInstrBuilder MachineIRBuilder::buildMul(unsigned Res, unsigned Op0,
219 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000220 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
221 "invalid operand type");
222 assert(MRI->getType(Res) == MRI->getType(Op0) &&
223 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
224
Tim Northover0f140c72016-09-09 11:46:34 +0000225 return buildInstr(TargetOpcode::G_MUL)
Tim Northovercecee562016-08-26 17:46:13 +0000226 .addDef(Res)
227 .addUse(Op0)
228 .addUse(Op1);
229}
230
Tim Northoverc3e3f592017-02-03 18:22:45 +0000231MachineInstrBuilder MachineIRBuilder::buildAnd(unsigned Res, unsigned Op0,
232 unsigned Op1) {
233 assert((MRI->getType(Res).isScalar() || MRI->getType(Res).isVector()) &&
234 "invalid operand type");
235 assert(MRI->getType(Res) == MRI->getType(Op0) &&
236 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
237
238 return buildInstr(TargetOpcode::G_AND)
239 .addDef(Res)
240 .addUse(Op0)
241 .addUse(Op1);
242}
243
Tim Northovera51575f2016-07-29 17:43:52 +0000244MachineInstrBuilder MachineIRBuilder::buildBr(MachineBasicBlock &Dest) {
Tim Northover0f140c72016-09-09 11:46:34 +0000245 return buildInstr(TargetOpcode::G_BR).addMBB(&Dest);
Tim Northovercc5f7622016-07-26 16:45:26 +0000246}
247
Kristof Beyls65a12c02017-01-30 09:13:18 +0000248MachineInstrBuilder MachineIRBuilder::buildBrIndirect(unsigned Tgt) {
249 return buildInstr(TargetOpcode::G_BRINDIRECT).addUse(Tgt);
250}
251
Tim Northovera51575f2016-07-29 17:43:52 +0000252MachineInstrBuilder MachineIRBuilder::buildCopy(unsigned Res, unsigned Op) {
253 return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op);
Tim Northover756eca32016-07-26 16:45:30 +0000254}
255
Tim Northover9267ac52016-12-05 21:47:07 +0000256MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
257 const ConstantInt &Val) {
258 LLT Ty = MRI->getType(Res);
Tim Northover1f8b1db2016-09-09 11:46:58 +0000259
Sam McCall03435f52016-12-06 10:14:36 +0000260 assert((Ty.isScalar() || Ty.isPointer()) && "invalid operand type");
Tim Northover9267ac52016-12-05 21:47:07 +0000261
262 const ConstantInt *NewVal = &Val;
263 if (Ty.getSizeInBits() != Val.getBitWidth())
264 NewVal = ConstantInt::get(MF->getFunction()->getContext(),
265 Val.getValue().sextOrTrunc(Ty.getSizeInBits()));
266
267 return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal);
268}
269
270MachineInstrBuilder MachineIRBuilder::buildConstant(unsigned Res,
271 int64_t Val) {
272 auto IntN = IntegerType::get(MF->getFunction()->getContext(),
273 MRI->getType(Res).getSizeInBits());
274 ConstantInt *CI = ConstantInt::get(IntN, Val, true);
275 return buildConstant(Res, *CI);
Tim Northover9656f142016-08-04 20:54:13 +0000276}
277
Tim Northover0f140c72016-09-09 11:46:34 +0000278MachineInstrBuilder MachineIRBuilder::buildFConstant(unsigned Res,
279 const ConstantFP &Val) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000280 assert(MRI->getType(Res).isScalar() && "invalid operand type");
281
Tim Northover0f140c72016-09-09 11:46:34 +0000282 return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val);
Tim Northoverb16734f2016-08-19 20:09:15 +0000283}
284
Tim Northover0f140c72016-09-09 11:46:34 +0000285MachineInstrBuilder MachineIRBuilder::buildBrCond(unsigned Tst,
Tim Northover69c2ba52016-07-29 17:58:00 +0000286 MachineBasicBlock &Dest) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000287 assert(MRI->getType(Tst).isScalar() && "invalid operand type");
288
Tim Northover0f140c72016-09-09 11:46:34 +0000289 return buildInstr(TargetOpcode::G_BRCOND).addUse(Tst).addMBB(&Dest);
Tim Northover69c2ba52016-07-29 17:58:00 +0000290}
291
Tim Northover0f140c72016-09-09 11:46:34 +0000292MachineInstrBuilder MachineIRBuilder::buildLoad(unsigned Res, unsigned Addr,
293 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000294 assert(MRI->getType(Res).isValid() && "invalid operand type");
295 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
296
Tim Northover0f140c72016-09-09 11:46:34 +0000297 return buildInstr(TargetOpcode::G_LOAD)
Tim Northovera51575f2016-07-29 17:43:52 +0000298 .addDef(Res)
299 .addUse(Addr)
300 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000301}
302
Tim Northover0f140c72016-09-09 11:46:34 +0000303MachineInstrBuilder MachineIRBuilder::buildStore(unsigned Val, unsigned Addr,
304 MachineMemOperand &MMO) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000305 assert(MRI->getType(Val).isValid() && "invalid operand type");
306 assert(MRI->getType(Addr).isPointer() && "invalid operand type");
307
Tim Northover0f140c72016-09-09 11:46:34 +0000308 return buildInstr(TargetOpcode::G_STORE)
Tim Northovera51575f2016-07-29 17:43:52 +0000309 .addUse(Val)
310 .addUse(Addr)
311 .addMemOperand(&MMO);
Tim Northoverad2b7172016-07-26 20:23:26 +0000312}
313
Tim Northover0f140c72016-09-09 11:46:34 +0000314MachineInstrBuilder MachineIRBuilder::buildUAdde(unsigned Res,
315 unsigned CarryOut,
316 unsigned Op0, unsigned Op1,
317 unsigned CarryIn) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000318 assert(MRI->getType(Res).isScalar() && "invalid operand type");
319 assert(MRI->getType(Res) == MRI->getType(Op0) &&
320 MRI->getType(Res) == MRI->getType(Op1) && "type mismatch");
321 assert(MRI->getType(CarryOut).isScalar() && "invalid operand type");
322 assert(MRI->getType(CarryOut) == MRI->getType(CarryIn) && "type mismatch");
323
Tim Northover0f140c72016-09-09 11:46:34 +0000324 return buildInstr(TargetOpcode::G_UADDE)
Tim Northover9656f142016-08-04 20:54:13 +0000325 .addDef(Res)
326 .addDef(CarryOut)
327 .addUse(Op0)
328 .addUse(Op1)
329 .addUse(CarryIn);
330}
331
Tim Northover0f140c72016-09-09 11:46:34 +0000332MachineInstrBuilder MachineIRBuilder::buildAnyExt(unsigned Res, unsigned Op) {
333 validateTruncExt(Res, Op, true);
334 return buildInstr(TargetOpcode::G_ANYEXT).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000335}
336
Tim Northover0f140c72016-09-09 11:46:34 +0000337MachineInstrBuilder MachineIRBuilder::buildSExt(unsigned Res, unsigned Op) {
338 validateTruncExt(Res, Op, true);
339 return buildInstr(TargetOpcode::G_SEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000340}
341
Tim Northover0f140c72016-09-09 11:46:34 +0000342MachineInstrBuilder MachineIRBuilder::buildZExt(unsigned Res, unsigned Op) {
343 validateTruncExt(Res, Op, true);
344 return buildInstr(TargetOpcode::G_ZEXT).addDef(Res).addUse(Op);
Tim Northover6cd4b232016-08-23 21:01:26 +0000345}
346
Tim Northovera7653b32016-09-12 11:20:22 +0000347MachineInstrBuilder MachineIRBuilder::buildSExtOrTrunc(unsigned Res,
348 unsigned Op) {
349 unsigned Opcode = TargetOpcode::COPY;
350 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
351 Opcode = TargetOpcode::G_SEXT;
352 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
353 Opcode = TargetOpcode::G_TRUNC;
354
355 return buildInstr(Opcode).addDef(Res).addUse(Op);
356}
357
Tim Northoverc3e3f592017-02-03 18:22:45 +0000358MachineInstrBuilder MachineIRBuilder::buildZExtOrTrunc(unsigned Res,
359 unsigned Op) {
360 unsigned Opcode = TargetOpcode::COPY;
361 if (MRI->getType(Res).getSizeInBits() > MRI->getType(Op).getSizeInBits())
362 Opcode = TargetOpcode::G_ZEXT;
363 else if (MRI->getType(Res).getSizeInBits() < MRI->getType(Op).getSizeInBits())
364 Opcode = TargetOpcode::G_TRUNC;
365
366 return buildInstr(Opcode).addDef(Res).addUse(Op);
367}
368
Tim Northover95b6d5f2017-03-06 19:04:17 +0000369
370MachineInstrBuilder MachineIRBuilder::buildCast(unsigned Dst, unsigned Src) {
371 LLT SrcTy = MRI->getType(Src);
372 LLT DstTy = MRI->getType(Dst);
373 if (SrcTy == DstTy)
374 return buildCopy(Dst, Src);
375
376 unsigned Opcode;
377 if (SrcTy.isPointer() && DstTy.isScalar())
378 Opcode = TargetOpcode::G_PTRTOINT;
379 else if (DstTy.isPointer() && SrcTy.isScalar())
380 Opcode = TargetOpcode::G_INTTOPTR;
381 else {
382 assert(!SrcTy.isPointer() && !DstTy.isPointer() && "n G_ADDRCAST yet");
383 Opcode = TargetOpcode::G_BITCAST;
384 }
385
386 return buildInstr(Opcode).addDef(Dst).addUse(Src);
387}
388
Tim Northoverc2c545b2017-03-06 23:50:28 +0000389MachineInstrBuilder MachineIRBuilder::buildExtract(unsigned Res, unsigned Src,
390 uint64_t Index) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000391#ifndef NDEBUG
Tim Northover1f8b1db2016-09-09 11:46:58 +0000392 assert(MRI->getType(Src).isValid() && "invalid operand type");
Tim Northoverc2c545b2017-03-06 23:50:28 +0000393 assert(MRI->getType(Res).isValid() && "invalid operand type");
394 assert(Index + MRI->getType(Res).getSizeInBits() <=
395 MRI->getType(Src).getSizeInBits() &&
396 "extracting off end of register");
Tim Northover1f8b1db2016-09-09 11:46:58 +0000397#endif
398
Tim Northoverc2c545b2017-03-06 23:50:28 +0000399 if (MRI->getType(Res).getSizeInBits() == MRI->getType(Src).getSizeInBits()) {
400 assert(Index == 0 && "insertion past the end of a register");
401 return buildCast(Res, Src);
402 }
Tim Northover33b07d62016-07-22 20:03:43 +0000403
Tim Northoverc2c545b2017-03-06 23:50:28 +0000404 return buildInstr(TargetOpcode::G_EXTRACT)
405 .addDef(Res)
406 .addUse(Src)
407 .addImm(Index);
Tim Northover33b07d62016-07-22 20:03:43 +0000408}
409
Tim Northover91c81732016-08-19 17:17:06 +0000410MachineInstrBuilder
Tim Northover0f140c72016-09-09 11:46:34 +0000411MachineIRBuilder::buildSequence(unsigned Res,
Tim Northover91c81732016-08-19 17:17:06 +0000412 ArrayRef<unsigned> Ops,
Tim Northoverb18ea162016-09-20 15:20:36 +0000413 ArrayRef<uint64_t> Indices) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000414#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000415 assert(Ops.size() == Indices.size() && "incompatible args");
Tim Northover26b76f22016-08-19 18:32:14 +0000416 assert(!Ops.empty() && "invalid trivial sequence");
Tim Northover991b12b2016-08-30 20:51:25 +0000417 assert(std::is_sorted(Indices.begin(), Indices.end()) &&
418 "sequence offsets must be in ascending order");
Tim Northover91c81732016-08-19 17:17:06 +0000419
Tim Northover1f8b1db2016-09-09 11:46:58 +0000420 assert(MRI->getType(Res).isValid() && "invalid operand type");
421 for (auto Op : Ops)
422 assert(MRI->getType(Op).isValid() && "invalid operand type");
423#endif
424
Tim Northover0f140c72016-09-09 11:46:34 +0000425 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_SEQUENCE);
Tim Northovera51575f2016-07-29 17:43:52 +0000426 MIB.addDef(Res);
Tim Northover91c81732016-08-19 17:17:06 +0000427 for (unsigned i = 0; i < Ops.size(); ++i) {
428 MIB.addUse(Ops[i]);
Tim Northover26b76f22016-08-19 18:32:14 +0000429 MIB.addImm(Indices[i]);
Tim Northover91c81732016-08-19 17:17:06 +0000430 }
Tim Northovera51575f2016-07-29 17:43:52 +0000431 return MIB;
Tim Northover33b07d62016-07-22 20:03:43 +0000432}
Tim Northover5fb414d2016-07-29 22:32:36 +0000433
Tim Northover81dafc12017-03-06 18:36:40 +0000434MachineInstrBuilder MachineIRBuilder::buildUndef(unsigned Res) {
435 return buildInstr(TargetOpcode::IMPLICIT_DEF).addDef(Res);
436}
437
Tim Northoverbf017292017-03-03 22:46:09 +0000438MachineInstrBuilder MachineIRBuilder::buildMerge(unsigned Res,
439 ArrayRef<unsigned> Ops) {
440
441#ifndef NDEBUG
442 assert(!Ops.empty() && "invalid trivial sequence");
443 LLT Ty = MRI->getType(Ops[0]);
444 for (auto Reg : Ops)
445 assert(MRI->getType(Reg) == Ty && "type mismatch in input list");
446 assert(Ops.size() * MRI->getType(Ops[0]).getSizeInBits() ==
447 MRI->getType(Res).getSizeInBits() &&
448 "input operands do not cover output register");
449#endif
450
451 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_MERGE_VALUES);
452 MIB.addDef(Res);
453 for (unsigned i = 0; i < Ops.size(); ++i)
454 MIB.addUse(Ops[i]);
455 return MIB;
456}
457
458MachineInstrBuilder MachineIRBuilder::buildUnmerge(ArrayRef<unsigned> Res,
459 unsigned Op) {
460
461#ifndef NDEBUG
462 assert(!Res.empty() && "invalid trivial sequence");
463 LLT Ty = MRI->getType(Res[0]);
464 for (auto Reg : Res)
465 assert(MRI->getType(Reg) == Ty && "type mismatch in input list");
466 assert(Res.size() * MRI->getType(Res[0]).getSizeInBits() ==
467 MRI->getType(Op).getSizeInBits() &&
468 "input operands do not cover output register");
469#endif
470
471 MachineInstrBuilder MIB = buildInstr(TargetOpcode::G_UNMERGE_VALUES);
472 for (unsigned i = 0; i < Res.size(); ++i)
473 MIB.addDef(Res[i]);
474 MIB.addUse(Op);
475 return MIB;
476}
477
Tim Northover3e6a7af2017-03-03 23:05:47 +0000478MachineInstrBuilder MachineIRBuilder::buildInsert(unsigned Res, unsigned Src,
479 unsigned Op, unsigned Index) {
Tim Northover95b6d5f2017-03-06 19:04:17 +0000480 if (MRI->getType(Res).getSizeInBits() == MRI->getType(Op).getSizeInBits()) {
481 assert(Index == 0 && "insertion past the end of a register");
482 return buildCast(Res, Op);
483 }
484
Tim Northover3e6a7af2017-03-03 23:05:47 +0000485 return buildInstr(TargetOpcode::G_INSERT)
486 .addDef(Res)
487 .addUse(Src)
488 .addUse(Op)
489 .addImm(Index);
490}
491
Tim Northover0f140c72016-09-09 11:46:34 +0000492MachineInstrBuilder MachineIRBuilder::buildIntrinsic(Intrinsic::ID ID,
Tim Northover5fb414d2016-07-29 22:32:36 +0000493 unsigned Res,
494 bool HasSideEffects) {
495 auto MIB =
496 buildInstr(HasSideEffects ? TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS
Tim Northover0f140c72016-09-09 11:46:34 +0000497 : TargetOpcode::G_INTRINSIC);
Tim Northover5fb414d2016-07-29 22:32:36 +0000498 if (Res)
499 MIB.addDef(Res);
500 MIB.addIntrinsicID(ID);
501 return MIB;
502}
Tim Northover32335812016-08-04 18:35:11 +0000503
Tim Northover0f140c72016-09-09 11:46:34 +0000504MachineInstrBuilder MachineIRBuilder::buildTrunc(unsigned Res, unsigned Op) {
505 validateTruncExt(Res, Op, false);
506 return buildInstr(TargetOpcode::G_TRUNC).addDef(Res).addUse(Op);
Tim Northover32335812016-08-04 18:35:11 +0000507}
Tim Northoverde3aea0412016-08-17 20:25:25 +0000508
Tim Northover0f140c72016-09-09 11:46:34 +0000509MachineInstrBuilder MachineIRBuilder::buildFPTrunc(unsigned Res, unsigned Op) {
510 validateTruncExt(Res, Op, false);
511 return buildInstr(TargetOpcode::G_FPTRUNC).addDef(Res).addUse(Op);
Tim Northovera11be042016-08-19 22:40:08 +0000512}
513
Tim Northover0f140c72016-09-09 11:46:34 +0000514MachineInstrBuilder MachineIRBuilder::buildICmp(CmpInst::Predicate Pred,
Tim Northoverde3aea0412016-08-17 20:25:25 +0000515 unsigned Res, unsigned Op0,
516 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000517#ifndef NDEBUG
Tim Northover1f8b1db2016-09-09 11:46:58 +0000518 assert(MRI->getType(Op0) == MRI->getType(Op0) && "type mismatch");
519 assert(CmpInst::isIntPredicate(Pred) && "invalid predicate");
Tim Northover4cf0a482016-09-15 10:40:38 +0000520 if (MRI->getType(Op0).isScalar() || MRI->getType(Op0).isPointer())
Tim Northover1f8b1db2016-09-09 11:46:58 +0000521 assert(MRI->getType(Res).isScalar() && "type mismatch");
522 else
523 assert(MRI->getType(Res).isVector() &&
524 MRI->getType(Res).getNumElements() ==
525 MRI->getType(Op0).getNumElements() &&
526 "type mismatch");
527#endif
528
Tim Northover0f140c72016-09-09 11:46:34 +0000529 return buildInstr(TargetOpcode::G_ICMP)
Tim Northoverde3aea0412016-08-17 20:25:25 +0000530 .addDef(Res)
531 .addPredicate(Pred)
532 .addUse(Op0)
533 .addUse(Op1);
534}
Tim Northover5a28c362016-08-19 20:09:07 +0000535
Tim Northover0f140c72016-09-09 11:46:34 +0000536MachineInstrBuilder MachineIRBuilder::buildFCmp(CmpInst::Predicate Pred,
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000537 unsigned Res, unsigned Op0,
538 unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000539#ifndef NDEBUG
540 assert((MRI->getType(Op0).isScalar() || MRI->getType(Op0).isVector()) &&
541 "invalid operand type");
542 assert(MRI->getType(Op0) == MRI->getType(Op1) && "type mismatch");
543 assert(CmpInst::isFPPredicate(Pred) && "invalid predicate");
544 if (MRI->getType(Op0).isScalar())
545 assert(MRI->getType(Res).isScalar() && "type mismatch");
546 else
547 assert(MRI->getType(Res).isVector() &&
548 MRI->getType(Res).getNumElements() ==
549 MRI->getType(Op0).getNumElements() &&
550 "type mismatch");
551#endif
552
Tim Northover0f140c72016-09-09 11:46:34 +0000553 return buildInstr(TargetOpcode::G_FCMP)
Tim Northoverd5c23bc2016-08-19 20:48:16 +0000554 .addDef(Res)
555 .addPredicate(Pred)
556 .addUse(Op0)
557 .addUse(Op1);
558}
559
Tim Northover0f140c72016-09-09 11:46:34 +0000560MachineInstrBuilder MachineIRBuilder::buildSelect(unsigned Res, unsigned Tst,
Tim Northover5a28c362016-08-19 20:09:07 +0000561 unsigned Op0, unsigned Op1) {
Tim Northover1f8b1db2016-09-09 11:46:58 +0000562#ifndef NDEBUG
Tim Northoverf50f2f32016-12-06 18:38:34 +0000563 LLT ResTy = MRI->getType(Res);
564 assert((ResTy.isScalar() || ResTy.isVector() || ResTy.isPointer()) &&
Tim Northover1f8b1db2016-09-09 11:46:58 +0000565 "invalid operand type");
Tim Northoverf50f2f32016-12-06 18:38:34 +0000566 assert(ResTy == MRI->getType(Op0) && ResTy == MRI->getType(Op1) &&
567 "type mismatch");
568 if (ResTy.isScalar() || ResTy.isPointer())
Tim Northover1f8b1db2016-09-09 11:46:58 +0000569 assert(MRI->getType(Tst).isScalar() && "type mismatch");
570 else
Ahmed Bougacha38455ea2017-03-07 20:53:03 +0000571 assert((MRI->getType(Tst).isScalar() ||
572 (MRI->getType(Tst).isVector() &&
573 MRI->getType(Tst).getNumElements() ==
574 MRI->getType(Op0).getNumElements())) &&
Tim Northover1f8b1db2016-09-09 11:46:58 +0000575 "type mismatch");
576#endif
577
Tim Northover0f140c72016-09-09 11:46:34 +0000578 return buildInstr(TargetOpcode::G_SELECT)
Tim Northover5a28c362016-08-19 20:09:07 +0000579 .addDef(Res)
580 .addUse(Tst)
581 .addUse(Op0)
582 .addUse(Op1);
583}
Tim Northoverbdf67c92016-08-23 21:01:33 +0000584
Volkan Keles04cb08c2017-03-10 19:08:28 +0000585MachineInstrBuilder MachineIRBuilder::buildInsertVectorElement(unsigned Res,
586 unsigned Val,
587 unsigned Elt,
588 unsigned Idx) {
589#ifndef NDEBUG
590 LLT ResTy = MRI->getType(Res);
591 LLT ValTy = MRI->getType(Val);
592 LLT EltTy = MRI->getType(Elt);
593 LLT IdxTy = MRI->getType(Idx);
594 assert(ResTy.isVector() && ValTy.isVector() && "invalid operand type");
595 assert(EltTy.isScalar() && IdxTy.isScalar() && "invalid operand type");
596 assert(ResTy.getNumElements() == ValTy.getNumElements() && "type mismatch");
597 assert(ResTy.getElementType() == EltTy && "type mismatch");
598#endif
599
600 return buildInstr(TargetOpcode::G_INSERT_VECTOR_ELT)
601 .addDef(Res)
602 .addUse(Val)
603 .addUse(Elt)
604 .addUse(Idx);
605}
606
607MachineInstrBuilder MachineIRBuilder::buildExtractVectorElement(unsigned Res,
608 unsigned Val,
609 unsigned Idx) {
610#ifndef NDEBUG
611 LLT ResTy = MRI->getType(Res);
612 LLT ValTy = MRI->getType(Val);
613 LLT IdxTy = MRI->getType(Idx);
614 assert(ValTy.isVector() && "invalid operand type");
615 assert(ResTy.isScalar() && IdxTy.isScalar() && "invalid operand type");
616 assert(ValTy.getElementType() == ResTy && "type mismatch");
617#endif
618
619 return buildInstr(TargetOpcode::G_EXTRACT_VECTOR_ELT)
620 .addDef(Res)
621 .addUse(Val)
622 .addUse(Idx);
623}
624
Tim Northover0f140c72016-09-09 11:46:34 +0000625void MachineIRBuilder::validateTruncExt(unsigned Dst, unsigned Src,
626 bool IsExtend) {
Richard Smith418237b2016-08-23 22:14:15 +0000627#ifndef NDEBUG
Tim Northover0f140c72016-09-09 11:46:34 +0000628 LLT SrcTy = MRI->getType(Src);
629 LLT DstTy = MRI->getType(Dst);
Tim Northoverbdf67c92016-08-23 21:01:33 +0000630
631 if (DstTy.isVector()) {
632 assert(SrcTy.isVector() && "mismatched cast between vecot and non-vector");
633 assert(SrcTy.getNumElements() == DstTy.getNumElements() &&
634 "different number of elements in a trunc/ext");
635 } else
636 assert(DstTy.isScalar() && SrcTy.isScalar() && "invalid extend/trunc");
637
638 if (IsExtend)
639 assert(DstTy.getSizeInBits() > SrcTy.getSizeInBits() &&
640 "invalid narrowing extend");
641 else
642 assert(DstTy.getSizeInBits() < SrcTy.getSizeInBits() &&
643 "invalid widening trunc");
Richard Smith418237b2016-08-23 22:14:15 +0000644#endif
Tim Northoverbdf67c92016-08-23 21:01:33 +0000645}