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gerrit-public.fairphone.software / toolchain / llvm-project / 16c4da03d5c8741a4ebbc4bec76c3bfa0c0259c3 / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: 4a8bedceb49165514bcc6fb88ea5ddccec1d0d45 [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]21#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]22#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]23#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]25#include "llvm/CodeGen/MachineInstrBuilder.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]26#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]27#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]28#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]29#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]30#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]31#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]32#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]33#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]34#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]35#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]36#include "llvm/Support/ErrorHandling.h"
37#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]38#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]39#include <limits>
40
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]41using namespace llvm;
42
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]43#define DEBUG_TYPE "x86-instr-info"
44
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]45#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]46#include "X86GenInstrInfo.inc"
47
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]48static cl::opt<bool>
49NoFusing("disable-spill-fusing",
50 cl::desc("Disable fusing of spill code into instructions"));
51static cl::opt<bool>
52PrintFailedFusing("print-failed-fuse-candidates",
53 cl::desc("Print instructions that the allocator wants to"
54 " fuse, but the X86 backend currently can't"),
55 cl::Hidden);
56static cl::opt<bool>
57ReMatPICStubLoad("remat-pic-stub-load",
58 cl::desc("Re-materialize load from stub in PIC mode"),
59 cl::init(false), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]60
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]61enum {
62 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]63 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]64 TB_INDEX_0 = 0,
65 TB_INDEX_1 = 1,
66 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]67 TB_INDEX_3 = 3,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]68 TB_INDEX_4 = 4,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]69 TB_INDEX_MASK = 0xf,
70
71 // Do not insert the reverse map (MemOp -> RegOp) into the table.
72 // This may be needed because there is a many -> one mapping.
73 TB_NO_REVERSE = 1 << 4,
74
75 // Do not insert the forward map (RegOp -> MemOp) into the table.
76 // This is needed for Native Client, which prohibits branch
77 // instructions from using a memory operand.
78 TB_NO_FORWARD = 1 << 5,
79
80 TB_FOLDED_LOAD = 1 << 6,
81 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]82
83 // Minimum alignment required for load/store.
84 // Used for RegOp->MemOp conversion.
85 // (stored in bits 8 - 15)
86 TB_ALIGN_SHIFT = 8,
87 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
88 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
89 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]90 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]91 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]92};
93
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]94struct X86MemoryFoldTableEntry {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]95 uint16_t RegOp;
96 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]97 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]98};
99
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]100// Pin the vtable to this file.
101void X86InstrInfo::anchor() {}
102
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]103X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
104 : X86GenInstrInfo(
Pavel Chupinbe9f1212014-09-22 13:11:35 +0000[diff] [blame]105 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64 : X86::ADJCALLSTACKDOWN32),
106 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64 : X86::ADJCALLSTACKUP32)),
Eric Christophered6a4462015-03-12 17:54:19 +0000[diff] [blame]107 Subtarget(STI), RI(STI.getTargetTriple()) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]108
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]109 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]110 { X86::ADC32ri, X86::ADC32mi, 0 },
111 { X86::ADC32ri8, X86::ADC32mi8, 0 },
112 { X86::ADC32rr, X86::ADC32mr, 0 },
113 { X86::ADC64ri32, X86::ADC64mi32, 0 },
114 { X86::ADC64ri8, X86::ADC64mi8, 0 },
115 { X86::ADC64rr, X86::ADC64mr, 0 },
116 { X86::ADD16ri, X86::ADD16mi, 0 },
117 { X86::ADD16ri8, X86::ADD16mi8, 0 },
118 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
119 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
120 { X86::ADD16rr, X86::ADD16mr, 0 },
121 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
122 { X86::ADD32ri, X86::ADD32mi, 0 },
123 { X86::ADD32ri8, X86::ADD32mi8, 0 },
124 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
125 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
126 { X86::ADD32rr, X86::ADD32mr, 0 },
127 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
128 { X86::ADD64ri32, X86::ADD64mi32, 0 },
129 { X86::ADD64ri8, X86::ADD64mi8, 0 },
130 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
131 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
132 { X86::ADD64rr, X86::ADD64mr, 0 },
133 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
134 { X86::ADD8ri, X86::ADD8mi, 0 },
135 { X86::ADD8rr, X86::ADD8mr, 0 },
136 { X86::AND16ri, X86::AND16mi, 0 },
137 { X86::AND16ri8, X86::AND16mi8, 0 },
138 { X86::AND16rr, X86::AND16mr, 0 },
139 { X86::AND32ri, X86::AND32mi, 0 },
140 { X86::AND32ri8, X86::AND32mi8, 0 },
141 { X86::AND32rr, X86::AND32mr, 0 },
142 { X86::AND64ri32, X86::AND64mi32, 0 },
143 { X86::AND64ri8, X86::AND64mi8, 0 },
144 { X86::AND64rr, X86::AND64mr, 0 },
145 { X86::AND8ri, X86::AND8mi, 0 },
146 { X86::AND8rr, X86::AND8mr, 0 },
147 { X86::DEC16r, X86::DEC16m, 0 },
148 { X86::DEC32r, X86::DEC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]149 { X86::DEC64r, X86::DEC64m, 0 },
150 { X86::DEC8r, X86::DEC8m, 0 },
151 { X86::INC16r, X86::INC16m, 0 },
152 { X86::INC32r, X86::INC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]153 { X86::INC64r, X86::INC64m, 0 },
154 { X86::INC8r, X86::INC8m, 0 },
155 { X86::NEG16r, X86::NEG16m, 0 },
156 { X86::NEG32r, X86::NEG32m, 0 },
157 { X86::NEG64r, X86::NEG64m, 0 },
158 { X86::NEG8r, X86::NEG8m, 0 },
159 { X86::NOT16r, X86::NOT16m, 0 },
160 { X86::NOT32r, X86::NOT32m, 0 },
161 { X86::NOT64r, X86::NOT64m, 0 },
162 { X86::NOT8r, X86::NOT8m, 0 },
163 { X86::OR16ri, X86::OR16mi, 0 },
164 { X86::OR16ri8, X86::OR16mi8, 0 },
165 { X86::OR16rr, X86::OR16mr, 0 },
166 { X86::OR32ri, X86::OR32mi, 0 },
167 { X86::OR32ri8, X86::OR32mi8, 0 },
168 { X86::OR32rr, X86::OR32mr, 0 },
169 { X86::OR64ri32, X86::OR64mi32, 0 },
170 { X86::OR64ri8, X86::OR64mi8, 0 },
171 { X86::OR64rr, X86::OR64mr, 0 },
172 { X86::OR8ri, X86::OR8mi, 0 },
173 { X86::OR8rr, X86::OR8mr, 0 },
174 { X86::ROL16r1, X86::ROL16m1, 0 },
175 { X86::ROL16rCL, X86::ROL16mCL, 0 },
176 { X86::ROL16ri, X86::ROL16mi, 0 },
177 { X86::ROL32r1, X86::ROL32m1, 0 },
178 { X86::ROL32rCL, X86::ROL32mCL, 0 },
179 { X86::ROL32ri, X86::ROL32mi, 0 },
180 { X86::ROL64r1, X86::ROL64m1, 0 },
181 { X86::ROL64rCL, X86::ROL64mCL, 0 },
182 { X86::ROL64ri, X86::ROL64mi, 0 },
183 { X86::ROL8r1, X86::ROL8m1, 0 },
184 { X86::ROL8rCL, X86::ROL8mCL, 0 },
185 { X86::ROL8ri, X86::ROL8mi, 0 },
186 { X86::ROR16r1, X86::ROR16m1, 0 },
187 { X86::ROR16rCL, X86::ROR16mCL, 0 },
188 { X86::ROR16ri, X86::ROR16mi, 0 },
189 { X86::ROR32r1, X86::ROR32m1, 0 },
190 { X86::ROR32rCL, X86::ROR32mCL, 0 },
191 { X86::ROR32ri, X86::ROR32mi, 0 },
192 { X86::ROR64r1, X86::ROR64m1, 0 },
193 { X86::ROR64rCL, X86::ROR64mCL, 0 },
194 { X86::ROR64ri, X86::ROR64mi, 0 },
195 { X86::ROR8r1, X86::ROR8m1, 0 },
196 { X86::ROR8rCL, X86::ROR8mCL, 0 },
197 { X86::ROR8ri, X86::ROR8mi, 0 },
198 { X86::SAR16r1, X86::SAR16m1, 0 },
199 { X86::SAR16rCL, X86::SAR16mCL, 0 },
200 { X86::SAR16ri, X86::SAR16mi, 0 },
201 { X86::SAR32r1, X86::SAR32m1, 0 },
202 { X86::SAR32rCL, X86::SAR32mCL, 0 },
203 { X86::SAR32ri, X86::SAR32mi, 0 },
204 { X86::SAR64r1, X86::SAR64m1, 0 },
205 { X86::SAR64rCL, X86::SAR64mCL, 0 },
206 { X86::SAR64ri, X86::SAR64mi, 0 },
207 { X86::SAR8r1, X86::SAR8m1, 0 },
208 { X86::SAR8rCL, X86::SAR8mCL, 0 },
209 { X86::SAR8ri, X86::SAR8mi, 0 },
210 { X86::SBB32ri, X86::SBB32mi, 0 },
211 { X86::SBB32ri8, X86::SBB32mi8, 0 },
212 { X86::SBB32rr, X86::SBB32mr, 0 },
213 { X86::SBB64ri32, X86::SBB64mi32, 0 },
214 { X86::SBB64ri8, X86::SBB64mi8, 0 },
215 { X86::SBB64rr, X86::SBB64mr, 0 },
216 { X86::SHL16rCL, X86::SHL16mCL, 0 },
217 { X86::SHL16ri, X86::SHL16mi, 0 },
218 { X86::SHL32rCL, X86::SHL32mCL, 0 },
219 { X86::SHL32ri, X86::SHL32mi, 0 },
220 { X86::SHL64rCL, X86::SHL64mCL, 0 },
221 { X86::SHL64ri, X86::SHL64mi, 0 },
222 { X86::SHL8rCL, X86::SHL8mCL, 0 },
223 { X86::SHL8ri, X86::SHL8mi, 0 },
224 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
225 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
226 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
227 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
228 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
229 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
230 { X86::SHR16r1, X86::SHR16m1, 0 },
231 { X86::SHR16rCL, X86::SHR16mCL, 0 },
232 { X86::SHR16ri, X86::SHR16mi, 0 },
233 { X86::SHR32r1, X86::SHR32m1, 0 },
234 { X86::SHR32rCL, X86::SHR32mCL, 0 },
235 { X86::SHR32ri, X86::SHR32mi, 0 },
236 { X86::SHR64r1, X86::SHR64m1, 0 },
237 { X86::SHR64rCL, X86::SHR64mCL, 0 },
238 { X86::SHR64ri, X86::SHR64mi, 0 },
239 { X86::SHR8r1, X86::SHR8m1, 0 },
240 { X86::SHR8rCL, X86::SHR8mCL, 0 },
241 { X86::SHR8ri, X86::SHR8mi, 0 },
242 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
243 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
244 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
245 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
246 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
247 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
248 { X86::SUB16ri, X86::SUB16mi, 0 },
249 { X86::SUB16ri8, X86::SUB16mi8, 0 },
250 { X86::SUB16rr, X86::SUB16mr, 0 },
251 { X86::SUB32ri, X86::SUB32mi, 0 },
252 { X86::SUB32ri8, X86::SUB32mi8, 0 },
253 { X86::SUB32rr, X86::SUB32mr, 0 },
254 { X86::SUB64ri32, X86::SUB64mi32, 0 },
255 { X86::SUB64ri8, X86::SUB64mi8, 0 },
256 { X86::SUB64rr, X86::SUB64mr, 0 },
257 { X86::SUB8ri, X86::SUB8mi, 0 },
258 { X86::SUB8rr, X86::SUB8mr, 0 },
259 { X86::XOR16ri, X86::XOR16mi, 0 },
260 { X86::XOR16ri8, X86::XOR16mi8, 0 },
261 { X86::XOR16rr, X86::XOR16mr, 0 },
262 { X86::XOR32ri, X86::XOR32mi, 0 },
263 { X86::XOR32ri8, X86::XOR32mi8, 0 },
264 { X86::XOR32rr, X86::XOR32mr, 0 },
265 { X86::XOR64ri32, X86::XOR64mi32, 0 },
266 { X86::XOR64ri8, X86::XOR64mi8, 0 },
267 { X86::XOR64rr, X86::XOR64mr, 0 },
268 { X86::XOR8ri, X86::XOR8mi, 0 },
269 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]270 };
271
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]272 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]273 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]274 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]275 // Index 0, folded load and store, no alignment requirement.
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]276 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]277 }
278
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]279 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]280 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
281 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
282 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
283 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
284 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]285 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
286 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
287 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
288 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
289 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
290 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
291 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
292 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
293 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
294 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
295 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
296 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
297 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
298 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
299 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]300 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]301 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
302 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
303 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
304 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
305 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
306 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
307 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
308 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
309 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
310 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
311 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
312 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
313 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
314 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
315 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
316 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
317 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
318 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
319 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
320 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
321 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
322 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]323 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
324 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
325 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
326 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
327 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
328 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]329 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
330 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
331 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
332 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]333 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
334 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]335 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
336 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
337 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]338 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
339 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
340 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
341 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
342 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
343 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
344 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
345 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
346 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
347 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
348 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
349 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
350 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
351 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
352 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
353 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
354 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
355 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
Reid Klecknera580b6e2015-01-30 21:03:31 +0000[diff] [blame]356 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]357 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
358 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
359 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]360 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]361
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]362 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]363 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]364 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]365 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
366 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
367 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
368 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
369 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
370 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
371 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
372 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
373 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]374 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
375 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]376
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]377 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]378 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]379 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
380 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
381 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
382 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]383 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]384
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]385 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]386 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
387 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
388 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
389 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
390 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
391 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
392 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]393 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
394 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]395 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]396 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]397
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]398 // AVX-512 foldable instructions (256-bit versions)
399 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
400 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
401 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
402 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
403 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
404 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
405 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
406 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
407 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
408 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]409
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]410 // AVX-512 foldable instructions (128-bit versions)
411 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
412 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
413 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
414 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
415 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
416 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
417 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
418 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
419 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]420 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]421
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]422 // F16C foldable instructions
423 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
424 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]425 };
426
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]427 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]428 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]429 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]430 }
431
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]432 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
Simon Pilgrim3a771802015-06-07 18:34:25 +0000[diff] [blame]433 { X86::BSF16rr, X86::BSF16rm, 0 },
434 { X86::BSF32rr, X86::BSF32rm, 0 },
435 { X86::BSF64rr, X86::BSF64rm, 0 },
436 { X86::BSR16rr, X86::BSR16rm, 0 },
437 { X86::BSR32rr, X86::BSR32rm, 0 },
438 { X86::BSR64rr, X86::BSR64rm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]439 { X86::CMP16rr, X86::CMP16rm, 0 },
440 { X86::CMP32rr, X86::CMP32rm, 0 },
441 { X86::CMP64rr, X86::CMP64rm, 0 },
442 { X86::CMP8rr, X86::CMP8rm, 0 },
443 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
444 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
445 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
446 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
447 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
448 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
449 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
450 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
451 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
452 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]453 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
454 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
455 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
456 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
457 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
458 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
459 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
460 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]461 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
462 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]463 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
464 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]465 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]466 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]467 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]468 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]469 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]470 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]471 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
472 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
473 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
474 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
475 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
476 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
477 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
478 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]479 { X86::MOV16rr, X86::MOV16rm, 0 },
480 { X86::MOV32rr, X86::MOV32rm, 0 },
481 { X86::MOV64rr, X86::MOV64rm, 0 },
482 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
483 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
484 { X86::MOV8rr, X86::MOV8rm, 0 },
485 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
486 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]487 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
488 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
489 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
490 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]491 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
492 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
493 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
494 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
495 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
496 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
497 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
498 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
499 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
500 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]501 { X86::MOVZQI2PQIrr, X86::MOVZQI2PQIrm, 0 },
502 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
503 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
504 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
505 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
506 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]507 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
508 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
509 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]510 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
511 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
512 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
513 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
514 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
515 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
516 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
517 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
518 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
519 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
520 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
521 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
522 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
523 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
524 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
525 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
526 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]527 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
528 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
529 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]530 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]531 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]532 { X86::RCPSSr, X86::RCPSSm, 0 },
533 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]534 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
535 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]536 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]537 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
538 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
539 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]540 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]541 { X86::SQRTSDr, X86::SQRTSDm, 0 },
542 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
543 { X86::SQRTSSr, X86::SQRTSSm, 0 },
544 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
545 { X86::TEST16rr, X86::TEST16rm, 0 },
546 { X86::TEST32rr, X86::TEST32rm, 0 },
547 { X86::TEST64rr, X86::TEST64rm, 0 },
548 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]549 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]550 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
551 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]552
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]553 // MMX version of foldable instructions
554 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
555 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
556 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
557 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
558 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
559 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
560 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
561 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
562 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
563 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
564
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]565 // 3DNow! version of foldable instructions
566 { X86::PF2IDrr, X86::PF2IDrm, 0 },
567 { X86::PF2IWrr, X86::PF2IWrm, 0 },
568 { X86::PFRCPrr, X86::PFRCPrm, 0 },
569 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
570 { X86::PI2FDrr, X86::PI2FDrm, 0 },
571 { X86::PI2FWrr, X86::PI2FWrm, 0 },
572 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
573
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]574 // AVX 128-bit versions of foldable instructions
575 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
576 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]577 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
578 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]579 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
580 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]581 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]582 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
583 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
584 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
585 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
586 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
587 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
588 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
589 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
590 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]591 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]592 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]593 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]594 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]595 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]596 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]597 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
598 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]599 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
600 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
601 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
602 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
603 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
604 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
605 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
606 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]607 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
608 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]609 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]610 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]611 { X86::VMOVZQI2PQIrr, X86::VMOVZQI2PQIrm, 0 },
612 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]613 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
614 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
615 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]616 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
617 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
618 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
619 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
620 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]621 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
622 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]623 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
624 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
625 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
626 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
627 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
628 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
629 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
630 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
631 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
632 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
633 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
634 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]635 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
636 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
637 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]638 { X86::VPTESTrr, X86::VPTESTrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]639 { X86::VRCPPSr, X86::VRCPPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]640 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
641 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]642 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]643 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]644 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]645 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
646 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]647 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]648 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]649
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]650 // AVX 256-bit foldable instructions
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]651 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]652 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]653 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]654 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]655 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]656 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]657 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
658 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]659 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
660 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]661 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]662 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]663 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
664 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]665 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]666 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]667 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
668 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima2618672015-02-07 21:44:06 +0000[diff] [blame]669 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]670 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]671 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
672 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]673 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
674 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
675 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]676 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
677 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]678
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]679 // AVX2 foldable instructions
Sanjay Patel1a20fdf2015-02-17 22:09:54 +0000[diff] [blame]680
681 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
682 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
683 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
684 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
685 // so they don't need an equivalent limitation.
Simon Pilgrimd11b0132015-02-08 17:13:54 +0000[diff] [blame]686 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
687 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
688 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]689 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
690 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
691 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]692 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
693 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
694 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
695 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
696 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
697 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
698 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
699 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
700 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
701 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
702 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
703 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
704 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
705 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
706 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
707 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
708 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
709 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
710 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
711 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
712 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
713 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]714 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
715 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
716 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]717
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]718 // XOP foldable instructions
719 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
720 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
721 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
722 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
723 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
724 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
725 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
726 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
727 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
728 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
729 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
730 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
731 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
732 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
733 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
734 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
735 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
736 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
737 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
738 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
739 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
740 { X86::VPROTBri, X86::VPROTBmi, 0 },
741 { X86::VPROTBrr, X86::VPROTBmr, 0 },
742 { X86::VPROTDri, X86::VPROTDmi, 0 },
743 { X86::VPROTDrr, X86::VPROTDmr, 0 },
744 { X86::VPROTQri, X86::VPROTQmi, 0 },
745 { X86::VPROTQrr, X86::VPROTQmr, 0 },
746 { X86::VPROTWri, X86::VPROTWmi, 0 },
747 { X86::VPROTWrr, X86::VPROTWmr, 0 },
748 { X86::VPSHABrr, X86::VPSHABmr, 0 },
749 { X86::VPSHADrr, X86::VPSHADmr, 0 },
750 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
751 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
752 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
753 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
754 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
755 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
756
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]757 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]758 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
759 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]760 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
761 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
762 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
763 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
764 { X86::BLCI32rr, X86::BLCI32rm, 0 },
765 { X86::BLCI64rr, X86::BLCI64rm, 0 },
766 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
767 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
768 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
769 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
770 { X86::BLCS32rr, X86::BLCS32rm, 0 },
771 { X86::BLCS64rr, X86::BLCS64rm, 0 },
772 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
773 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]774 { X86::BLSI32rr, X86::BLSI32rm, 0 },
775 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]776 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
777 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]778 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
779 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
780 { X86::BLSR32rr, X86::BLSR32rm, 0 },
781 { X86::BLSR64rr, X86::BLSR64rm, 0 },
782 { X86::BZHI32rr, X86::BZHI32rm, 0 },
783 { X86::BZHI64rr, X86::BZHI64rm, 0 },
784 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
785 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
786 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
787 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
788 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
789 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]790 { X86::RORX32ri, X86::RORX32mi, 0 },
791 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]792 { X86::SARX32rr, X86::SARX32rm, 0 },
793 { X86::SARX64rr, X86::SARX64rm, 0 },
794 { X86::SHRX32rr, X86::SHRX32rm, 0 },
795 { X86::SHRX64rr, X86::SHRX64rm, 0 },
796 { X86::SHLX32rr, X86::SHLX32rm, 0 },
797 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]798 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
799 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]800 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
801 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
802 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]803 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
804 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]805
806 // AVX-512 foldable instructions
807 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
808 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]809 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
810 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]811 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
812 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]813 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
814 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]815 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
816 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]817 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
818 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]819 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
820 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]821 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
822 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]823
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]824 // AVX-512 foldable instructions (256-bit versions)
825 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
826 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
827 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
828 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
829 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
830 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
831 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
832 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
833 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
834 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]835 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
836 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]837
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]838 // AVX-512 foldable instructions (256-bit versions)
839 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
840 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
841 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
842 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
843 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
844 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
845 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
846 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
847 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
848 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]849 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]850
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]851 // F16C foldable instructions
852 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
853 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]854
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]855 // AES foldable instructions
856 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
857 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
Simon Pilgrim295eaad2015-02-12 20:01:03 +0000[diff] [blame]858 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
859 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]860 };
861
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]862 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]863 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]864 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]865 // Index 1, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]866 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]867 }
868
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]869 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]870 { X86::ADC32rr, X86::ADC32rm, 0 },
871 { X86::ADC64rr, X86::ADC64rm, 0 },
872 { X86::ADD16rr, X86::ADD16rm, 0 },
873 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
874 { X86::ADD32rr, X86::ADD32rm, 0 },
875 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
876 { X86::ADD64rr, X86::ADD64rm, 0 },
877 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
878 { X86::ADD8rr, X86::ADD8rm, 0 },
879 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
880 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
881 { X86::ADDSDrr, X86::ADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]882 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]883 { X86::ADDSSrr, X86::ADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]884 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]885 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
886 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
887 { X86::AND16rr, X86::AND16rm, 0 },
888 { X86::AND32rr, X86::AND32rm, 0 },
889 { X86::AND64rr, X86::AND64rm, 0 },
890 { X86::AND8rr, X86::AND8rm, 0 },
891 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
892 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
893 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
894 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]895 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
896 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
897 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
898 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]899 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
900 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
901 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
902 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
903 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
904 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
905 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
906 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
907 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
908 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
909 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
910 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
911 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
912 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
913 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
914 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
915 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
916 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
917 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
918 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
919 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
920 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
921 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
922 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
923 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
924 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
925 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
926 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
927 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
928 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
929 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
930 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
931 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
932 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
933 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
934 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
935 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
936 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
937 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
938 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
939 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
940 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
941 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
942 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
943 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
944 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
945 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
946 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
947 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
948 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
949 { X86::CMPSDrr, X86::CMPSDrm, 0 },
950 { X86::CMPSSrr, X86::CMPSSrm, 0 },
Simon Pilgrim01846222015-04-03 14:24:40 +0000[diff] [blame]951 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
952 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]953 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
954 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
955 { X86::DIVSDrr, X86::DIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]956 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]957 { X86::DIVSSrr, X86::DIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]958 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
959 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
960 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]961
Sanjay Patel8c13e362015-07-28 00:48:32 +0000[diff] [blame]962 // Do not fold Fs* scalar logical op loads because there are no scalar
963 // load variants for these instructions. When folded, the load is required
964 // to be 128-bits, so the load size would not match.
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]965
966 { X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 },
967 { X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 },
968 { X86::FvANDPDrr, X86::FvANDPDrm, TB_ALIGN_16 },
969 { X86::FvANDPSrr, X86::FvANDPSrm, TB_ALIGN_16 },
970 { X86::FvORPDrr, X86::FvORPDrm, TB_ALIGN_16 },
971 { X86::FvORPSrr, X86::FvORPSrm, TB_ALIGN_16 },
972 { X86::FvXORPDrr, X86::FvXORPDrm, TB_ALIGN_16 },
973 { X86::FvXORPSrr, X86::FvXORPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]974 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
975 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
976 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
977 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
978 { X86::IMUL16rr, X86::IMUL16rm, 0 },
979 { X86::IMUL32rr, X86::IMUL32rm, 0 },
980 { X86::IMUL64rr, X86::IMUL64rm, 0 },
981 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
982 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]983 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
984 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
985 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
986 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
987 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
988 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]989 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]990 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]991 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]992 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]993 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]994 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]995 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]996 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]997 { X86::MINSDrr, X86::MINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]998 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]999 { X86::MINSSrr, X86::MINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1000 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1001 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1002 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1003 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1004 { X86::MULSDrr, X86::MULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1005 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1006 { X86::MULSSrr, X86::MULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1007 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1008 { X86::OR16rr, X86::OR16rm, 0 },
1009 { X86::OR32rr, X86::OR32rm, 0 },
1010 { X86::OR64rr, X86::OR64rm, 0 },
1011 { X86::OR8rr, X86::OR8rm, 0 },
1012 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1013 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1014 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1015 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1016 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1017 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1018 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1019 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1020 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1021 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1022 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1023 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1024 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1025 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1026 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1027 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1028 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1029 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1030 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1031 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1032 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1033 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1034 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1035 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1036 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1037 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1038 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1039 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1040 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1041 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1042 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1043 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1044 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1045 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1046 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1047 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1048 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1049 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1050 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1051 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1052 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1053 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1054 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1055 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1056 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1057 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]1058 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1059 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1060 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1061 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1062 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1063 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1064 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1065 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1066 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1067 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1068 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1069 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1070 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1071 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1072 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1073 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1074 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1075 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
1076 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
1077 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
1078 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1079 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1080 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1081 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1082 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1083 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1084 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1085 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1086 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1087 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1088 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1089 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1090 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1091 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1092 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1093 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1094 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1095 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1096 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1097 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1098 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1099 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1100 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1101 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1102 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1103 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1104 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
1105 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1106 { X86::SBB32rr, X86::SBB32rm, 0 },
1107 { X86::SBB64rr, X86::SBB64rm, 0 },
1108 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1109 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1110 { X86::SUB16rr, X86::SUB16rm, 0 },
1111 { X86::SUB32rr, X86::SUB32rm, 0 },
1112 { X86::SUB64rr, X86::SUB64rm, 0 },
1113 { X86::SUB8rr, X86::SUB8rm, 0 },
1114 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1115 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1116 { X86::SUBSDrr, X86::SUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1117 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1118 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1119 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1120 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1121 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1122 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1123 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1124 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1125 { X86::XOR16rr, X86::XOR16rm, 0 },
1126 { X86::XOR32rr, X86::XOR32rm, 0 },
1127 { X86::XOR64rr, X86::XOR64rm, 0 },
1128 { X86::XOR8rr, X86::XOR8rm, 0 },
1129 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1130 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1131
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]1132 // MMX version of foldable instructions
1133 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1134 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1135 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1136 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1137 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1138 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1139 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1140 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1141 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1142 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1143 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1144 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1145 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1146 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1147 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1148 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1149 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1150 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1151 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1152 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1153 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1154 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1155 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1156 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1157 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1158 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1159 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1160 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1161 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1162 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1163 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1164 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1165 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1166 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1167 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1168 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1169 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1170 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1171 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1172 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1173 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1174 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1175 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1176 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1177 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1178 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1179 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1180 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1181 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1182 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1183 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1184 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1185 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1186 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1187 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1188 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1189 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1190 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1191 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1192 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1193 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1194 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1195 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1196 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1197 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1198 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1199 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1200 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1201 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1202 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1203
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]1204 // 3DNow! version of foldable instructions
1205 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1206 { X86::PFACCrr, X86::PFACCrm, 0 },
1207 { X86::PFADDrr, X86::PFADDrm, 0 },
1208 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1209 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1210 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1211 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1212 { X86::PFMINrr, X86::PFMINrm, 0 },
1213 { X86::PFMULrr, X86::PFMULrm, 0 },
1214 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1215 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1216 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1217 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1218 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1219 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1220 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1221 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1222
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1223 // AVX 128-bit versions of foldable instructions
1224 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1225 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1226 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1227 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1228 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1229 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1230 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1231 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1232 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1233 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]1234 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1235 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1236 { X86::VRCPSSr, X86::VRCPSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1237 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1238 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1239 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1240 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1241 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1242 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1243 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1244 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1245 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1246 { X86::VADDSDrr, X86::VADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1247 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1248 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1249 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1250 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1251 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1252 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1253 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1254 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1255 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1256 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1257 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1258 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1259 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1260 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1261 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1262 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1263 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1264 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1265 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1266 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1267 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1268 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1269 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1270 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1271 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]1272 // Do not fold VFs* loads because there are no scalar load variants for
1273 // these instructions. When folded, the load is required to be 128-bits, so
1274 // the load size would not match.
1275 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 },
1276 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 },
1277 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 },
1278 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 },
1279 { X86::VFvORPDrr, X86::VFvORPDrm, 0 },
1280 { X86::VFvORPSrr, X86::VFvORPSrm, 0 },
1281 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 },
1282 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1283 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1284 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1285 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1286 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1287 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1288 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1289 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1290 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1291 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1292 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1293 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1294 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1295 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1296 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1297 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1298 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1299 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1300 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1301 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1302 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1303 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1304 { X86::VMULSDrr, X86::VMULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1305 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1306 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1307 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1308 { X86::VORPDrr, X86::VORPDrm, 0 },
1309 { X86::VORPSrr, X86::VORPSrm, 0 },
1310 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1311 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1312 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1313 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1314 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1315 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1316 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1317 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1318 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1319 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1320 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1321 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1322 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
1323 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1324 { X86::VPANDrr, X86::VPANDrm, 0 },
1325 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1326 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1327 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1328 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1329 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1330 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1331 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1332 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1333 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1334 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1335 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1336 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1337 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1338 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1339 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1340 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1341 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1342 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1343 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1344 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1345 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1346 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1347 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1348 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1349 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1350 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1351 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1352 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1353 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1354 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1355 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1356 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1357 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1358 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1359 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1360 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1361 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1362 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1363 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1364 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1365 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1366 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1367 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1368 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1369 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1370 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1371 { X86::VPORrr, X86::VPORrm, 0 },
1372 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1373 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1374 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
1375 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
1376 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
1377 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1378 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1379 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1380 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1381 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1382 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1383 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1384 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1385 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1386 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1387 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1388 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1389 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1390 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1391 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1392 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1393 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1394 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1395 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1396 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1397 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1398 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1399 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1400 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1401 { X86::VPXORrr, X86::VPXORrm, 0 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1402 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1403 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1404 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1405 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1406 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1407 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1408 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1409 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1410 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1411 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1412 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1413 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1414 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1415 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1416 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1417 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1418
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1419 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1420 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1421 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1422 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1423 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1424 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1425 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1426 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1427 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1428 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1429 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1430 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1431 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1432 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1433 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1434 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1435 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1436 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1437 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1438 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1439 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1440 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1441 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1442 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1443 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1444 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1445 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1446 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1447 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1448 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1449 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1450 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1451 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1452 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1453 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1454 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1455 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1456 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1457 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1458 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1459 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1460 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1461 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1462 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1463
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1464 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1465 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1466 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1467 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1468 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1469 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1470 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1471 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1472 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1473 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1474 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1475 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1476 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1477 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1478 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1479 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1480 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1481 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1482 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1483 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1484 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1485 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1486 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1487 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1488 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1489 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1490 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1491 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1492 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1493 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1494 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1495 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1496 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1497 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1498 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1499 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1500 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1501 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1502 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1503 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1504 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1505 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1506 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1507 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1508 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1509 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1510 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1511 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1512 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1513 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1514 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1515 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1516 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1517 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1518 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1519 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1520 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1521 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1522 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1523 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1524 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1525 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1526 { X86::VPORYrr, X86::VPORYrm, 0 },
1527 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1528 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1529 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1530 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1531 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1532 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1533 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1534 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1535 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1536 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1537 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1538 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1539 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1540 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1541 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1542 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1543 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1544 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1545 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1546 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1547 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1548 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1549 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1550 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1551 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1552 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1553 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1554 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1555 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1556 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1557 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1558 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1559 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1560 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1561 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1562 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1563 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1564 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1565 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1566 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1567
1568 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1569 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE },
1570 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE },
1571 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE },
1572 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE },
1573 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_NONE },
1574 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_NONE },
1575 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE },
1576 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE },
1577 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE },
1578 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE },
1579 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_NONE },
1580 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_NONE },
1581 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE },
1582 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE },
1583 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE },
1584 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE },
1585 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_NONE },
1586 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_NONE },
1587 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE },
1588 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE },
1589 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE },
1590 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE },
1591 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_NONE },
1592 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_NONE },
1593 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE },
1594 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE },
1595 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_NONE },
1596 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_NONE },
1597 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE },
1598 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE },
1599 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_NONE },
1600 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_NONE },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1601
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1602 // XOP foldable instructions
1603 { X86::VPCMOVrr, X86::VPCMOVmr, 0 },
1604 { X86::VPCMOVrrY, X86::VPCMOVmrY, 0 },
1605 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1606 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1607 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1608 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1609 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1610 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1611 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1612 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1613 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1614 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1615 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1616 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1617 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1618 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1619 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1620 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1621 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1622 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1623 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1624 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1625 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1626 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1627 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1628 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
1629 { X86::VPPERMrr, X86::VPPERMmr, 0 },
1630 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1631 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1632 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1633 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1634 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1635 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1636 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1637 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1638 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1639 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1640 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1641 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1642
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1643 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1644 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1645 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1646 { X86::MULX32rr, X86::MULX32rm, 0 },
1647 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1648 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1649 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1650 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1651 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1652
1653 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1654 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1655 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1656 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1657 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1658 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1659 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1660 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1661 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1662 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1663 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1664 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1665 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1666 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1667 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1668 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1669 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1670 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1671 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1672 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1673 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1674 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1675 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1676 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1677 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1678 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1679 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1680 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1681 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1682 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1683 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1684 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1685 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1686 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1687 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
Igor Breger00d9f842015-06-08 14:03:17 +0000[diff] [blame]1688 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1689 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1690 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1691 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1692 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1693
1694 // AVX-512{F,VL} foldable instructions
1695 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1696 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1697 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1698
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1699 // AVX-512{F,VL} foldable instructions
1700 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1701 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1702 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1703 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1704
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1705 // AES foldable instructions
1706 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1707 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1708 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1709 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1710 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1711 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1712 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1713 { X86::VAESENCrr, X86::VAESENCrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1714
1715 // SHA foldable instructions
1716 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1717 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1718 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1719 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1720 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1721 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1722 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1723 };
1724
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1725 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1726 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1727 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1728 // Index 2, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1729 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1730 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1731
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1732 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1733 // FMA foldable instructions
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1734 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
1735 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
1736 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
1737 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
1738 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
1739 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1740
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1741 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1742 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1743 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1744 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1745 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1746 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1747 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1748 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1749 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1750 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1751 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1752 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1753
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1754 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
1755 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
1756 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
1757 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
1758 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
1759 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1760
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1761 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1762 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1763 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1764 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1765 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1766 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1767 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1768 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1769 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1770 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1771 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1772 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1773
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1774 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
1775 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
1776 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
1777 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
1778 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
1779 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1780
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1781 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1782 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1783 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1784 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1785 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1786 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1787 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1788 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1789 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1790 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1791 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1792 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1793
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1794 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
1795 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
1796 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
1797 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
1798 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
1799 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1800
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1801 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1802 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1803 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1804 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1805 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1806 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1807 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1808 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1809 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1810 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1811 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1812 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1813
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1814 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1815 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1816 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1817 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1818 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1819 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1820 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1821 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1822 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1823 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1824 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1825 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1826
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1827 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1828 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1829 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1830 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1831 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1832 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1833 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1834 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1835 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1836 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1837 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1838 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1839
1840 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1841 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE },
1842 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE },
1843 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE },
1844 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE },
1845 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_NONE },
1846 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_NONE },
1847 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE },
1848 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE },
1849 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE },
1850 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE },
1851 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_NONE },
1852 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_NONE },
1853 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE },
1854 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE },
1855 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE },
1856 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE },
1857 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_NONE },
1858 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_NONE },
1859 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE },
1860 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE },
1861 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE },
1862 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE },
1863 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_NONE },
1864 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_NONE },
1865 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE },
1866 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE },
1867 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_NONE },
1868 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_NONE },
1869 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE },
1870 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE },
1871 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_NONE },
1872 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_NONE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1873
1874 // XOP foldable instructions
1875 { X86::VPCMOVrr, X86::VPCMOVrm, 0 },
1876 { X86::VPCMOVrrY, X86::VPCMOVrmY, 0 },
1877 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1878 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1879 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1880 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
1881 { X86::VPPERMrr, X86::VPPERMrm, 0 },
1882
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]1883 // AVX-512 VPERMI instructions with 3 source operands.
1884 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1885 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1886 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1887 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1888 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1889 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1890 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1891 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1892 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1893 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1894 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1895 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1896 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1897 // AVX-512 arithmetic instructions
1898 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1899 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1900 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1901 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1902 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1903 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1904 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1905 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1906 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1907 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1908 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1909 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1910 // AVX-512{F,VL} arithmetic instructions 256-bit
1911 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1912 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1913 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1914 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1915 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1916 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1917 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1918 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1919 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1920 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1921 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1922 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1923 // AVX-512{F,VL} arithmetic instructions 128-bit
1924 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1925 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1926 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1927 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1928 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1929 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1930 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1931 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1932 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1933 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1934 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1935 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1936 };
1937
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1938 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1939 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1940 Entry.RegOp, Entry.MemOp,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1941 // Index 3, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1942 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1943 }
1944
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1945 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1946 // AVX-512 foldable instructions
1947 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1948 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
1949 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
1950 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
1951 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
1952 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
1953 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
1954 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
1955 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
1956 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
1957 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
1958 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
1959 // AVX-512{F,VL} foldable instructions 256-bit
1960 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
1961 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
1962 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
1963 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
1964 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
1965 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
1966 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
1967 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
1968 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
1969 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
1970 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
1971 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
1972 // AVX-512{F,VL} foldable instructions 128-bit
1973 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
1974 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
1975 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
1976 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
1977 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
1978 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
1979 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
1980 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
1981 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
1982 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
1983 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
1984 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
1985 };
1986
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1987 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1988 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1989 Entry.RegOp, Entry.MemOp,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1990 // Index 4, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1991 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1992 }
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]1993}
1994
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1995void
1996X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
1997 MemOp2RegOpTableType &M2RTable,
1998 unsigned RegOp, unsigned MemOp, unsigned Flags) {
1999 if ((Flags & TB_NO_FORWARD) == 0) {
2000 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2001 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2002 }
2003 if ((Flags & TB_NO_REVERSE) == 0) {
2004 assert(!M2RTable.count(MemOp) &&
2005 "Duplicated entries in unfolding maps?");
2006 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2007 }
2008}
2009
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2010bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2011X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2012 unsigned &SrcReg, unsigned &DstReg,
2013 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2014 switch (MI.getOpcode()) {
2015 default: break;
2016 case X86::MOVSX16rr8:
2017 case X86::MOVZX16rr8:
2018 case X86::MOVSX32rr8:
2019 case X86::MOVZX32rr8:
2020 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2021 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]2022 // It's not always legal to reference the low 8-bit of the larger
2023 // register in 32-bit mode.
2024 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2025 case X86::MOVSX32rr16:
2026 case X86::MOVZX32rr16:
2027 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]2028 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2029 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2030 // Be conservative.
2031 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2032 SrcReg = MI.getOperand(1).getReg();
2033 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2034 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2035 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2036 case X86::MOVSX16rr8:
2037 case X86::MOVZX16rr8:
2038 case X86::MOVSX32rr8:
2039 case X86::MOVZX32rr8:
2040 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2041 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2042 break;
2043 case X86::MOVSX32rr16:
2044 case X86::MOVZX32rr16:
2045 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2046 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2047 break;
2048 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2049 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2050 break;
2051 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2052 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2053 }
2054 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2055 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2056}
2057
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2058int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
2059 const MachineFunction *MF = MI->getParent()->getParent();
2060 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2061
2062 if (MI->getOpcode() == getCallFrameSetupOpcode() ||
2063 MI->getOpcode() == getCallFrameDestroyOpcode()) {
2064 unsigned StackAlign = TFI->getStackAlignment();
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2065 int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2066 StackAlign;
2067
2068 SPAdj -= MI->getOperand(1).getImm();
2069
2070 if (MI->getOpcode() == getCallFrameSetupOpcode())
2071 return SPAdj;
2072 else
2073 return -SPAdj;
2074 }
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2075
2076 // To know whether a call adjusts the stack, we need information
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2077 // that is bound to the following ADJCALLSTACKUP pseudo.
2078 // Look for the next ADJCALLSTACKUP that follows the call.
2079 if (MI->isCall()) {
2080 const MachineBasicBlock* MBB = MI->getParent();
2081 auto I = ++MachineBasicBlock::const_iterator(MI);
2082 for (auto E = MBB->end(); I != E; ++I) {
2083 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2084 I->isCall())
2085 break;
2086 }
2087
2088 // If we could not find a frame destroy opcode, then it has already
2089 // been simplified, so we don't care.
2090 if (I->getOpcode() != getCallFrameDestroyOpcode())
2091 return 0;
2092
2093 return -(I->getOperand(1).getImm());
2094 }
2095
2096 // Currently handle only PUSHes we can reasonably expect to see
2097 // in call sequences
2098 switch (MI->getOpcode()) {
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2099 default:
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2100 return 0;
2101 case X86::PUSH32i8:
2102 case X86::PUSH32r:
2103 case X86::PUSH32rmm:
2104 case X86::PUSH32rmr:
2105 case X86::PUSHi32:
2106 return 4;
2107 }
2108}
2109
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2110/// Return true and the FrameIndex if the specified
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2111/// operand and follow operands form a reference to the stack frame.
2112bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2113 int &FrameIndex) const {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2114 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2115 MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2116 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2117 MI->getOperand(Op+X86::AddrDisp).isImm() &&
2118 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2119 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2120 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2121 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2122 return true;
2123 }
2124 return false;
2125}
2126
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2127static bool isFrameLoadOpcode(int Opcode) {
2128 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]2129 default:
2130 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2131 case X86::MOV8rm:
2132 case X86::MOV16rm:
2133 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]2134 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]2135 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2136 case X86::MOVSSrm:
2137 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2138 case X86::MOVAPSrm:
2139 case X86::MOVAPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]2140 case X86::MOVDQArm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2141 case X86::VMOVSSrm:
2142 case X86::VMOVSDrm:
2143 case X86::VMOVAPSrm:
2144 case X86::VMOVAPDrm:
2145 case X86::VMOVDQArm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2146 case X86::VMOVUPSYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2147 case X86::VMOVAPSYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2148 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2149 case X86::VMOVAPDYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2150 case X86::VMOVDQUYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2151 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]2152 case X86::MMX_MOVD64rm:
2153 case X86::MMX_MOVQ64rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2154 case X86::VMOVAPSZrm:
2155 case X86::VMOVUPSZrm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2156 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2157 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2158}
2159
2160static bool isFrameStoreOpcode(int Opcode) {
2161 switch (Opcode) {
2162 default: break;
2163 case X86::MOV8mr:
2164 case X86::MOV16mr:
2165 case X86::MOV32mr:
2166 case X86::MOV64mr:
2167 case X86::ST_FpP64m:
2168 case X86::MOVSSmr:
2169 case X86::MOVSDmr:
2170 case X86::MOVAPSmr:
2171 case X86::MOVAPDmr:
2172 case X86::MOVDQAmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2173 case X86::VMOVSSmr:
2174 case X86::VMOVSDmr:
2175 case X86::VMOVAPSmr:
2176 case X86::VMOVAPDmr:
2177 case X86::VMOVDQAmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2178 case X86::VMOVUPSYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2179 case X86::VMOVAPSYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2180 case X86::VMOVUPDYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2181 case X86::VMOVAPDYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2182 case X86::VMOVDQUYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2183 case X86::VMOVDQAYmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2184 case X86::VMOVUPSZmr:
2185 case X86::VMOVAPSZmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2186 case X86::MMX_MOVD64mr:
2187 case X86::MMX_MOVQ64mr:
2188 case X86::MMX_MOVNTQmr:
2189 return true;
2190 }
2191 return false;
2192}
2193
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2194unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2195 int &FrameIndex) const {
2196 if (isFrameLoadOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2197 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2198 return MI->getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2199 return 0;
2200}
2201
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2202unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2203 int &FrameIndex) const {
2204 if (isFrameLoadOpcode(MI->getOpcode())) {
2205 unsigned Reg;
2206 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2207 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2208 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2209 const MachineMemOperand *Dummy;
2210 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2211 }
2212 return 0;
2213}
2214
Dan Gohman0b273252008-11-18 19:49:32 +0000[diff] [blame]2215unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2216 int &FrameIndex) const {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2217 if (isFrameStoreOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2218 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2219 isFrameOperand(MI, 0, FrameIndex))
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]2220 return MI->getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2221 return 0;
2222}
2223
2224unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2225 int &FrameIndex) const {
2226 if (isFrameStoreOpcode(MI->getOpcode())) {
2227 unsigned Reg;
2228 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2229 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2230 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2231 const MachineMemOperand *Dummy;
2232 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2233 }
2234 return 0;
2235}
2236
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2237/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2238static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]2239 // Don't waste compile time scanning use-def chains of physregs.
2240 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2241 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2242 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]2243 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2244 E = MRI.def_instr_end(); I != E; ++I) {
2245 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2246 if (DefMI->getOpcode() != X86::MOVPC32r)
2247 return false;
2248 assert(!isPICBase && "More than one PIC base?");
2249 isPICBase = true;
2250 }
2251 return isPICBase;
2252}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]2253
Bill Wendling1e117682008-05-12 20:54:26 +0000[diff] [blame]2254bool
Dan Gohmane919de52009-10-10 00:34:18 +0000[diff] [blame]2255X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2256 AliasAnalysis *AA) const {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2257 switch (MI->getOpcode()) {
2258 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2259 case X86::MOV8rm:
2260 case X86::MOV16rm:
2261 case X86::MOV32rm:
2262 case X86::MOV64rm:
2263 case X86::LD_Fp64m:
2264 case X86::MOVSSrm:
2265 case X86::MOVSDrm:
2266 case X86::MOVAPSrm:
2267 case X86::MOVUPSrm:
2268 case X86::MOVAPDrm:
2269 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2270 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2271 case X86::VMOVSSrm:
2272 case X86::VMOVSDrm:
2273 case X86::VMOVAPSrm:
2274 case X86::VMOVUPSrm:
2275 case X86::VMOVAPDrm:
2276 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2277 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2278 case X86::VMOVAPSYrm:
2279 case X86::VMOVUPSYrm:
2280 case X86::VMOVAPDYrm:
2281 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2282 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2283 case X86::MMX_MOVD64rm:
2284 case X86::MMX_MOVQ64rm:
2285 case X86::FsVMOVAPSrm:
2286 case X86::FsVMOVAPDrm:
2287 case X86::FsMOVAPSrm:
2288 case X86::FsMOVAPDrm: {
2289 // Loads from constant pools are trivially rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2290 if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2291 MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2292 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2293 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2294 MI->isInvariantLoad(AA)) {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2295 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2296 if (BaseReg == 0 || BaseReg == X86::RIP)
2297 return true;
2298 // Allow re-materialization of PIC load.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2299 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2300 return false;
2301 const MachineFunction &MF = *MI->getParent()->getParent();
2302 const MachineRegisterInfo &MRI = MF.getRegInfo();
2303 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]2304 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2305 return false;
2306 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2307
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2308 case X86::LEA32r:
2309 case X86::LEA64r: {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2310 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2311 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2312 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2313 !MI->getOperand(1+X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2314 // lea fi#, lea GV, etc. are all rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2315 if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2316 return true;
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2317 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2318 if (BaseReg == 0)
2319 return true;
2320 // Allow re-materialization of lea PICBase + x.
2321 const MachineFunction &MF = *MI->getParent()->getParent();
2322 const MachineRegisterInfo &MRI = MF.getRegInfo();
2323 return regIsPICBase(BaseReg, MRI);
2324 }
2325 return false;
2326 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2327 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]2328
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]2329 // All other instructions marked M_REMATERIALIZABLE are always trivially
2330 // rematerializable.
2331 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2332}
2333
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]2334bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2335 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2336 MachineBasicBlock::iterator E = MBB.end();
2337
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2338 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2339 // safety after visiting 4 instructions in each direction, we will assume
2340 // it's not safe.
2341 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2342 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2343 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2344 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2345 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2346 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2347 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2348 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2349 continue;
2350 if (MO.getReg() == X86::EFLAGS) {
2351 if (MO.isUse())
2352 return false;
2353 SeenDef = true;
2354 }
2355 }
2356
2357 if (SeenDef)
2358 // This instruction defines EFLAGS, no need to look any further.
2359 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2360 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2361 // Skip over DBG_VALUE.
2362 while (Iter != E && Iter->isDebugValue())
2363 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2364 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2365
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2366 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2367 // live in.
2368 if (Iter == E) {
2369 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2370 SE = MBB.succ_end(); SI != SE; ++SI)
2371 if ((*SI)->isLiveIn(X86::EFLAGS))
2372 return false;
2373 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2374 }
2375
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2376 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2377 Iter = I;
2378 for (unsigned i = 0; i < 4; ++i) {
2379 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]2380 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2381 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2382 return !MBB.isLiveIn(X86::EFLAGS);
2383
2384 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2385 // Skip over DBG_VALUE.
2386 while (Iter != B && Iter->isDebugValue())
2387 --Iter;
2388
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2389 bool SawKill = false;
2390 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2391 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2392 // A register mask may clobber EFLAGS, but we should still look for a
2393 // live EFLAGS def.
2394 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2395 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2396 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2397 if (MO.isDef()) return MO.isDead();
2398 if (MO.isKill()) SawKill = true;
2399 }
2400 }
2401
2402 if (SawKill)
2403 // This instruction kills EFLAGS and doesn't redefine it, so
2404 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2405 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2406 }
2407
2408 // Conservative answer.
2409 return false;
2410}
2411
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2412void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2413 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2414 unsigned DestReg, unsigned SubIdx,
Evan Cheng6ad7da92009-11-14 02:55:43 +0000[diff] [blame]2415 const MachineInstr *Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2416 const TargetRegisterInfo &TRI) const {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2417 // MOV32r0 is implemented with a xor which clobbers condition code.
2418 // Re-materialize it as movri instructions to avoid side effects.
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2419 unsigned Opc = Orig->getOpcode();
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2420 if (Opc == X86::MOV32r0 && !isSafeToClobberEFLAGS(MBB, I)) {
2421 DebugLoc DL = Orig->getDebugLoc();
2422 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
2423 .addImm(0);
2424 } else {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2425 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2426 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2427 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]2428
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2429 MachineInstr *NewMI = std::prev(I);
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2430 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2431}
2432
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2433/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
Andrew Kayloraf083d42015-08-26 20:36:52 +0000[diff] [blame]2434bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr *MI) const {
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2435 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2436 MachineOperand &MO = MI->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2437 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2438 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2439 return true;
2440 }
2441 }
2442 return false;
2443}
2444
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2445/// Check whether the shift count for a machine operand is non-zero.
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2446inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2447 unsigned ShiftAmtOperandIdx) {
2448 // The shift count is six bits with the REX.W prefix and five bits without.
2449 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2450 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2451 return Imm & ShiftCountMask;
2452}
2453
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2454/// Check whether the given shift count is appropriate
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2455/// can be represented by a LEA instruction.
2456inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2457 // Left shift instructions can be transformed into load-effective-address
2458 // instructions if we can encode them appropriately.
Sanjay Pateldc87d142015-08-12 15:09:09 +0000[diff] [blame]2459 // A LEA instruction utilizes a SIB byte to encode its scale factor.
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2460 // The SIB.scale field is two bits wide which means that we can encode any
2461 // shift amount less than 4.
2462 return ShAmt < 4 && ShAmt > 0;
2463}
2464
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2465bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2466 unsigned Opc, bool AllowSP,
2467 unsigned &NewSrc, bool &isKill, bool &isUndef,
2468 MachineOperand &ImplicitOp) const {
2469 MachineFunction &MF = *MI->getParent()->getParent();
2470 const TargetRegisterClass *RC;
2471 if (AllowSP) {
2472 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2473 } else {
2474 RC = Opc != X86::LEA32r ?
2475 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2476 }
2477 unsigned SrcReg = Src.getReg();
2478
2479 // For both LEA64 and LEA32 the register already has essentially the right
2480 // type (32-bit or 64-bit) we may just need to forbid SP.
2481 if (Opc != X86::LEA64_32r) {
2482 NewSrc = SrcReg;
2483 isKill = Src.isKill();
2484 isUndef = Src.isUndef();
2485
2486 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2487 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2488 return false;
2489
2490 return true;
2491 }
2492
2493 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2494 // another we need to add 64-bit registers to the final MI.
2495 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2496 ImplicitOp = Src;
2497 ImplicitOp.setImplicit();
2498
2499 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2500 MachineBasicBlock::LivenessQueryResult LQR =
2501 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2502
2503 switch (LQR) {
2504 case MachineBasicBlock::LQR_Unknown:
2505 // We can't give sane liveness flags to the instruction, abandon LEA
2506 // formation.
2507 return false;
2508 case MachineBasicBlock::LQR_Live:
2509 isKill = MI->killsRegister(SrcReg);
2510 isUndef = false;
2511 break;
2512 default:
2513 // The physreg itself is dead, so we have to use it as an <undef>.
2514 isKill = false;
2515 isUndef = true;
2516 break;
2517 }
2518 } else {
2519 // Virtual register of the wrong class, we have to create a temporary 64-bit
2520 // vreg to feed into the LEA.
2521 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2522 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2523 get(TargetOpcode::COPY))
2524 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2525 .addOperand(Src);
2526
2527 // Which is obviously going to be dead after we're done with it.
2528 isKill = true;
2529 isUndef = false;
2530 }
2531
2532 // We've set all the parameters without issue.
2533 return true;
2534}
2535
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2536/// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2537/// LEA to form 3-address code by promoting to a 32-bit superregister and then
2538/// truncating back down to a 16-bit subregister.
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2539MachineInstr *
2540X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2541 MachineFunction::iterator &MFI,
2542 MachineBasicBlock::iterator &MBBI,
2543 LiveVariables *LV) const {
2544 MachineInstr *MI = MBBI;
2545 unsigned Dest = MI->getOperand(0).getReg();
2546 unsigned Src = MI->getOperand(1).getReg();
2547 bool isDead = MI->getOperand(0).isDead();
2548 bool isKill = MI->getOperand(1).isKill();
2549
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2550 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2551 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2552 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2553 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2554 Opc = X86::LEA64_32r;
2555 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2556 } else {
2557 Opc = X86::LEA32r;
2558 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2559 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2560
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2561 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2562 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2563 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2564 // movw (%rbp,%rcx,2), %dx
2565 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2566 // But testing has shown this *does* help performance in 64-bit mode (at
2567 // least on modern x86 machines).
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2568 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2569 MachineInstr *InsMI =
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2570 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2571 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2572 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2573
2574 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2575 get(Opc), leaOutReg);
2576 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2577 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2578 case X86::SHL16ri: {
2579 unsigned ShAmt = MI->getOperand(2).getImm();
2580 MIB.addReg(0).addImm(1 << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2581 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2582 break;
2583 }
2584 case X86::INC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2585 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2586 break;
2587 case X86::DEC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2588 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2589 break;
2590 case X86::ADD16ri:
2591 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2592 case X86::ADD16ri_DB:
2593 case X86::ADD16ri8_DB:
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2594 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2595 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2596 case X86::ADD16rr:
2597 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2598 unsigned Src2 = MI->getOperand(2).getReg();
2599 bool isKill2 = MI->getOperand(2).isKill();
2600 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2601 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2602 if (Src == Src2) {
2603 // ADD16rr %reg1028<kill>, %reg1028
2604 // just a single insert_subreg.
2605 addRegReg(MIB, leaInReg, true, leaInReg, false);
2606 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2607 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2608 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2609 else
2610 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2611 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2612 // well be shifting and then extracting the lower 16-bits.
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2613 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2614 InsMI2 =
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2615 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2616 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2617 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2618 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2619 }
2620 if (LV && isKill2 && InsMI2)
2621 LV->replaceKillInstruction(Src2, MI, InsMI2);
2622 break;
2623 }
2624 }
2625
2626 MachineInstr *NewMI = MIB;
2627 MachineInstr *ExtMI =
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2628 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2629 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2630 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2631
2632 if (LV) {
2633 // Update live variables
2634 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2635 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2636 if (isKill)
2637 LV->replaceKillInstruction(Src, MI, InsMI);
2638 if (isDead)
2639 LV->replaceKillInstruction(Dest, MI, ExtMI);
2640 }
2641
2642 return ExtMI;
2643}
2644
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2645/// This method must be implemented by targets that
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2646/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2647/// may be able to convert a two-address instruction into a true
2648/// three-address instruction on demand. This allows the X86 target (for
2649/// example) to convert ADD and SHL instructions into LEA instructions if they
2650/// would require register copies due to two-addressness.
2651///
2652/// This method returns a null pointer if the transformation cannot be
2653/// performed, otherwise it returns the new instruction.
2654///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2655MachineInstr *
2656X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2657 MachineBasicBlock::iterator &MBBI,
Owen Anderson30cc0282008-07-02 23:41:07 +0000[diff] [blame]2658 LiveVariables *LV) const {
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2659 MachineInstr *MI = MBBI;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2660
2661 // The following opcodes also sets the condition code register(s). Only
2662 // convert them to equivalent lea if the condition code register def's
2663 // are dead!
2664 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2665 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2666
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2667 MachineFunction &MF = *MI->getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2668 // All instructions input are two-addr instructions. Get the known operands.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2669 const MachineOperand &Dest = MI->getOperand(0);
2670 const MachineOperand &Src = MI->getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2671
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2672 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2673 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2674 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2675 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2676 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2677 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2678
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2679 unsigned MIOpc = MI->getOpcode();
2680 switch (MIOpc) {
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2681 default: return nullptr;
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2682 case X86::SHL64ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2683 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2684 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2685 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2686
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2687 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2688 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2689 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2690 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2691 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2692
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2693 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2694 .addOperand(Dest)
2695 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2696 break;
2697 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2698 case X86::SHL32ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2699 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2700 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2701 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2702
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2703 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2704
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2705 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2706 bool isKill, isUndef;
2707 unsigned SrcReg;
2708 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2709 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2710 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2711 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2712
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2713 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2714 .addOperand(Dest)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2715 .addReg(0).addImm(1 << ShAmt)
2716 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2717 .addImm(0).addReg(0);
2718 if (ImplicitOp.getReg() != 0)
2719 MIB.addOperand(ImplicitOp);
2720 NewMI = MIB;
2721
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2722 break;
2723 }
2724 case X86::SHL16ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2725 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2726 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2727 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2728
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2729 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2730 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2731 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2732 .addOperand(Dest)
2733 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2734 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2735 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2736 case X86::INC64r:
2737 case X86::INC32r: {
2738 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2739 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2740 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2741 bool isKill, isUndef;
2742 unsigned SrcReg;
2743 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2744 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2745 SrcReg, isKill, isUndef, ImplicitOp))
2746 return nullptr;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2747
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2748 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2749 .addOperand(Dest)
2750 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2751 if (ImplicitOp.getReg() != 0)
2752 MIB.addOperand(ImplicitOp);
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2753
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2754 NewMI = addOffset(MIB, 1);
2755 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2756 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2757 case X86::INC16r:
2758 if (DisableLEA16)
2759 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2760 : nullptr;
2761 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2762 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2763 .addOperand(Dest).addOperand(Src), 1);
2764 break;
2765 case X86::DEC64r:
2766 case X86::DEC32r: {
2767 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2768 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2769 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2770
2771 bool isKill, isUndef;
2772 unsigned SrcReg;
2773 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2774 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2775 SrcReg, isKill, isUndef, ImplicitOp))
2776 return nullptr;
2777
2778 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2779 .addOperand(Dest)
2780 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2781 if (ImplicitOp.getReg() != 0)
2782 MIB.addOperand(ImplicitOp);
2783
2784 NewMI = addOffset(MIB, -1);
2785
2786 break;
2787 }
2788 case X86::DEC16r:
2789 if (DisableLEA16)
2790 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2791 : nullptr;
2792 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2793 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2794 .addOperand(Dest).addOperand(Src), -1);
2795 break;
2796 case X86::ADD64rr:
2797 case X86::ADD64rr_DB:
2798 case X86::ADD32rr:
2799 case X86::ADD32rr_DB: {
2800 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2801 unsigned Opc;
2802 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2803 Opc = X86::LEA64r;
2804 else
2805 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2806
2807 bool isKill, isUndef;
2808 unsigned SrcReg;
2809 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2810 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2811 SrcReg, isKill, isUndef, ImplicitOp))
2812 return nullptr;
2813
2814 const MachineOperand &Src2 = MI->getOperand(2);
2815 bool isKill2, isUndef2;
2816 unsigned SrcReg2;
2817 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2818 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2819 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2820 return nullptr;
2821
2822 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2823 .addOperand(Dest);
2824 if (ImplicitOp.getReg() != 0)
2825 MIB.addOperand(ImplicitOp);
2826 if (ImplicitOp2.getReg() != 0)
2827 MIB.addOperand(ImplicitOp2);
2828
2829 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2830
2831 // Preserve undefness of the operands.
2832 NewMI->getOperand(1).setIsUndef(isUndef);
2833 NewMI->getOperand(3).setIsUndef(isUndef2);
2834
2835 if (LV && Src2.isKill())
2836 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2837 break;
2838 }
2839 case X86::ADD16rr:
2840 case X86::ADD16rr_DB: {
2841 if (DisableLEA16)
2842 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2843 : nullptr;
2844 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2845 unsigned Src2 = MI->getOperand(2).getReg();
2846 bool isKill2 = MI->getOperand(2).isKill();
2847 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2848 .addOperand(Dest),
2849 Src.getReg(), Src.isKill(), Src2, isKill2);
2850
2851 // Preserve undefness of the operands.
2852 bool isUndef = MI->getOperand(1).isUndef();
2853 bool isUndef2 = MI->getOperand(2).isUndef();
2854 NewMI->getOperand(1).setIsUndef(isUndef);
2855 NewMI->getOperand(3).setIsUndef(isUndef2);
2856
2857 if (LV && isKill2)
2858 LV->replaceKillInstruction(Src2, MI, NewMI);
2859 break;
2860 }
2861 case X86::ADD64ri32:
2862 case X86::ADD64ri8:
2863 case X86::ADD64ri32_DB:
2864 case X86::ADD64ri8_DB:
2865 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2866 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2867 .addOperand(Dest).addOperand(Src),
2868 MI->getOperand(2).getImm());
2869 break;
2870 case X86::ADD32ri:
2871 case X86::ADD32ri8:
2872 case X86::ADD32ri_DB:
2873 case X86::ADD32ri8_DB: {
2874 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2875 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2876
2877 bool isKill, isUndef;
2878 unsigned SrcReg;
2879 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2880 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2881 SrcReg, isKill, isUndef, ImplicitOp))
2882 return nullptr;
2883
2884 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2885 .addOperand(Dest)
2886 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2887 if (ImplicitOp.getReg() != 0)
2888 MIB.addOperand(ImplicitOp);
2889
2890 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2891 break;
2892 }
2893 case X86::ADD16ri:
2894 case X86::ADD16ri8:
2895 case X86::ADD16ri_DB:
2896 case X86::ADD16ri8_DB:
2897 if (DisableLEA16)
2898 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2899 : nullptr;
2900 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2901 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2902 .addOperand(Dest).addOperand(Src),
2903 MI->getOperand(2).getImm());
2904 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2905 }
2906
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2907 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]2908
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2909 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2910 if (Src.isKill())
2911 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2912 if (Dest.isDead())
2913 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2914 }
2915
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2916 MFI->insert(MBBI, NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]2917 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2918}
2919
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]2920MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr *MI,
2921 bool NewMI,
2922 unsigned OpIdx1,
2923 unsigned OpIdx2) const {
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2924 switch (MI->getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2925 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
2926 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2927 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2928 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
2929 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
2930 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2931 unsigned Opc;
2932 unsigned Size;
2933 switch (MI->getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]2934 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2935 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
2936 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
2937 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
2938 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]2939 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
2940 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]2941 }
Chris Lattner5c463782007-12-30 20:49:49 +0000[diff] [blame]2942 unsigned Amt = MI->getOperand(3).getImm();
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2943 if (NewMI) {
2944 MachineFunction &MF = *MI->getParent()->getParent();
2945 MI = MF.CloneMachineInstr(MI);
2946 NewMI = false;
Evan Cheng244183e2008-02-13 02:46:49 +0000[diff] [blame]2947 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]2948 MI->setDesc(get(Opc));
2949 MI->getOperand(3).setImm(Size-Amt);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]2950 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]2951 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]2952 case X86::BLENDPDrri:
2953 case X86::BLENDPSrri:
2954 case X86::PBLENDWrri:
2955 case X86::VBLENDPDrri:
2956 case X86::VBLENDPSrri:
2957 case X86::VBLENDPDYrri:
2958 case X86::VBLENDPSYrri:
2959 case X86::VPBLENDDrri:
2960 case X86::VPBLENDWrri:
2961 case X86::VPBLENDDYrri:
2962 case X86::VPBLENDWYrri:{
2963 unsigned Mask;
2964 switch (MI->getOpcode()) {
2965 default: llvm_unreachable("Unreachable!");
2966 case X86::BLENDPDrri: Mask = 0x03; break;
2967 case X86::BLENDPSrri: Mask = 0x0F; break;
2968 case X86::PBLENDWrri: Mask = 0xFF; break;
2969 case X86::VBLENDPDrri: Mask = 0x03; break;
2970 case X86::VBLENDPSrri: Mask = 0x0F; break;
2971 case X86::VBLENDPDYrri: Mask = 0x0F; break;
2972 case X86::VBLENDPSYrri: Mask = 0xFF; break;
2973 case X86::VPBLENDDrri: Mask = 0x0F; break;
2974 case X86::VPBLENDWrri: Mask = 0xFF; break;
2975 case X86::VPBLENDDYrri: Mask = 0xFF; break;
2976 case X86::VPBLENDWYrri: Mask = 0xFF; break;
2977 }
Andrea Di Biagio7ecd22c2014-11-06 14:36:45 +0000[diff] [blame]2978 // Only the least significant bits of Imm are used.
2979 unsigned Imm = MI->getOperand(3).getImm() & Mask;
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]2980 if (NewMI) {
2981 MachineFunction &MF = *MI->getParent()->getParent();
2982 MI = MF.CloneMachineInstr(MI);
2983 NewMI = false;
2984 }
2985 MI->getOperand(3).setImm(Mask ^ Imm);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]2986 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]2987 }
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]2988 case X86::PCLMULQDQrr:
2989 case X86::VPCLMULQDQrr:{
2990 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
2991 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
2992 unsigned Imm = MI->getOperand(3).getImm();
2993 unsigned Src1Hi = Imm & 0x01;
2994 unsigned Src2Hi = Imm & 0x10;
2995 if (NewMI) {
2996 MachineFunction &MF = *MI->getParent()->getParent();
2997 MI = MF.CloneMachineInstr(MI);
2998 NewMI = false;
2999 }
3000 MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]3001 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3002 }
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3003 case X86::CMPPDrri:
3004 case X86::CMPPSrri:
3005 case X86::VCMPPDrri:
3006 case X86::VCMPPSrri:
3007 case X86::VCMPPDYrri:
3008 case X86::VCMPPSYrri: {
3009 // Float comparison can be safely commuted for
3010 // Ordered/Unordered/Equal/NotEqual tests
3011 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3012 switch (Imm) {
3013 case 0x00: // EQUAL
3014 case 0x03: // UNORDERED
3015 case 0x04: // NOT EQUAL
3016 case 0x07: // ORDERED
3017 if (NewMI) {
3018 MachineFunction &MF = *MI->getParent()->getParent();
3019 MI = MF.CloneMachineInstr(MI);
3020 NewMI = false;
3021 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]3022 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3023 default:
3024 return nullptr;
3025 }
3026 }
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3027 case X86::VPCOMBri: case X86::VPCOMUBri:
3028 case X86::VPCOMDri: case X86::VPCOMUDri:
3029 case X86::VPCOMQri: case X86::VPCOMUQri:
3030 case X86::VPCOMWri: case X86::VPCOMUWri: {
3031 // Flip comparison mode immediate (if necessary).
3032 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3033 switch (Imm) {
3034 case 0x00: Imm = 0x02; break; // LT -> GT
3035 case 0x01: Imm = 0x03; break; // LE -> GE
3036 case 0x02: Imm = 0x00; break; // GT -> LT
3037 case 0x03: Imm = 0x01; break; // GE -> LE
3038 case 0x04: // EQ
3039 case 0x05: // NE
3040 case 0x06: // FALSE
3041 case 0x07: // TRUE
3042 default:
3043 break;
3044 }
3045 if (NewMI) {
3046 MachineFunction &MF = *MI->getParent()->getParent();
3047 MI = MF.CloneMachineInstr(MI);
3048 NewMI = false;
3049 }
3050 MI->getOperand(3).setImm(Imm);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]3051 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3052 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3053 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
3054 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3055 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
3056 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3057 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3058 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
3059 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
3060 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3061 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3062 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
3063 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
3064 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3065 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
3066 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3067 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
3068 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3069 unsigned Opc;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3070 switch (MI->getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3071 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3072 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
3073 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
3074 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
3075 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3076 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3077 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3078 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
3079 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
3080 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
3081 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3082 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3083 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]3084 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3085 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3086 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3087 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
3088 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
3089 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3090 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
3091 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
3092 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
3093 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3094 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3095 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3096 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3097 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3098 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3099 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
3100 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3101 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3102 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3103 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3104 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3105 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3106 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3107 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3108 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3109 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3110 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3111 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3112 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3113 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3114 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3115 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3116 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3117 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3118 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3119 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3120 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]3121 if (NewMI) {
3122 MachineFunction &MF = *MI->getParent()->getParent();
3123 MI = MF.CloneMachineInstr(MI);
3124 NewMI = false;
3125 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]3126 MI->setDesc(get(Opc));
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3127 // Fallthrough intended.
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3128 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3129 default:
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]3130 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3131 }
3132}
3133
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]3134bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI,
3135 unsigned &SrcOpIdx1,
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3136 unsigned &SrcOpIdx2) const {
3137 switch (MI->getOpcode()) {
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3138 case X86::CMPPDrri:
3139 case X86::CMPPSrri:
3140 case X86::VCMPPDrri:
3141 case X86::VCMPPSrri:
3142 case X86::VCMPPDYrri:
3143 case X86::VCMPPSYrri: {
3144 // Float comparison can be safely commuted for
3145 // Ordered/Unordered/Equal/NotEqual tests
3146 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3147 switch (Imm) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]3148 case 0x00: // EQUAL
3149 case 0x03: // UNORDERED
3150 case 0x04: // NOT EQUAL
3151 case 0x07: // ORDERED
3152 // The indices of the commutable operands are 1 and 2.
3153 // Assign them to the returned operand indices here.
3154 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3155 }
3156 return false;
3157 }
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3158 case X86::VFMADDPDr231r:
3159 case X86::VFMADDPSr231r:
3160 case X86::VFMADDSDr231r:
3161 case X86::VFMADDSSr231r:
3162 case X86::VFMSUBPDr231r:
3163 case X86::VFMSUBPSr231r:
3164 case X86::VFMSUBSDr231r:
3165 case X86::VFMSUBSSr231r:
3166 case X86::VFNMADDPDr231r:
3167 case X86::VFNMADDPSr231r:
3168 case X86::VFNMADDSDr231r:
3169 case X86::VFNMADDSSr231r:
3170 case X86::VFNMSUBPDr231r:
3171 case X86::VFNMSUBPSr231r:
3172 case X86::VFNMSUBSDr231r:
3173 case X86::VFNMSUBSSr231r:
3174 case X86::VFMADDPDr231rY:
3175 case X86::VFMADDPSr231rY:
3176 case X86::VFMSUBPDr231rY:
3177 case X86::VFMSUBPSr231rY:
3178 case X86::VFNMADDPDr231rY:
3179 case X86::VFNMADDPSr231rY:
3180 case X86::VFNMSUBPDr231rY:
3181 case X86::VFNMSUBPSr231rY:
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]3182 // The indices of the commutable operands are 2 and 3.
3183 // Assign them to the returned operand indices here.
3184 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3);
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3185 default:
3186 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3187 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]3188 return false;
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3189}
3190
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3191static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3192 switch (BrOpc) {
3193 default: return X86::COND_INVALID;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3194 case X86::JE_1: return X86::COND_E;
3195 case X86::JNE_1: return X86::COND_NE;
3196 case X86::JL_1: return X86::COND_L;
3197 case X86::JLE_1: return X86::COND_LE;
3198 case X86::JG_1: return X86::COND_G;
3199 case X86::JGE_1: return X86::COND_GE;
3200 case X86::JB_1: return X86::COND_B;
3201 case X86::JBE_1: return X86::COND_BE;
3202 case X86::JA_1: return X86::COND_A;
3203 case X86::JAE_1: return X86::COND_AE;
3204 case X86::JS_1: return X86::COND_S;
3205 case X86::JNS_1: return X86::COND_NS;
3206 case X86::JP_1: return X86::COND_P;
3207 case X86::JNP_1: return X86::COND_NP;
3208 case X86::JO_1: return X86::COND_O;
3209 case X86::JNO_1: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3210 }
3211}
3212
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3213/// Return condition code of a SET opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3214static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3215 switch (Opc) {
3216 default: return X86::COND_INVALID;
3217 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3218 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3219 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3220 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3221 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3222 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3223 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3224 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3225 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3226 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3227 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3228 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3229 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3230 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3231 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3232 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3233 }
3234}
3235
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3236/// Return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3237X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3238 switch (Opc) {
3239 default: return X86::COND_INVALID;
3240 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3241 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3242 return X86::COND_A;
3243 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3244 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3245 return X86::COND_AE;
3246 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3247 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3248 return X86::COND_B;
3249 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3250 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3251 return X86::COND_BE;
3252 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3253 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3254 return X86::COND_E;
3255 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3256 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3257 return X86::COND_G;
3258 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3259 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3260 return X86::COND_GE;
3261 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3262 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3263 return X86::COND_L;
3264 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3265 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3266 return X86::COND_LE;
3267 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3268 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3269 return X86::COND_NE;
3270 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3271 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3272 return X86::COND_NO;
3273 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3274 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3275 return X86::COND_NP;
3276 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3277 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3278 return X86::COND_NS;
3279 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3280 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3281 return X86::COND_O;
3282 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3283 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3284 return X86::COND_P;
3285 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3286 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3287 return X86::COND_S;
3288 }
3289}
3290
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3291unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3292 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3293 default: llvm_unreachable("Illegal condition code!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3294 case X86::COND_E: return X86::JE_1;
3295 case X86::COND_NE: return X86::JNE_1;
3296 case X86::COND_L: return X86::JL_1;
3297 case X86::COND_LE: return X86::JLE_1;
3298 case X86::COND_G: return X86::JG_1;
3299 case X86::COND_GE: return X86::JGE_1;
3300 case X86::COND_B: return X86::JB_1;
3301 case X86::COND_BE: return X86::JBE_1;
3302 case X86::COND_A: return X86::JA_1;
3303 case X86::COND_AE: return X86::JAE_1;
3304 case X86::COND_S: return X86::JS_1;
3305 case X86::COND_NS: return X86::JNS_1;
3306 case X86::COND_P: return X86::JP_1;
3307 case X86::COND_NP: return X86::JNP_1;
3308 case X86::COND_O: return X86::JO_1;
3309 case X86::COND_NO: return X86::JNO_1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3310 }
3311}
3312
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3313/// Return the inverse of the specified condition,
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3314/// e.g. turning COND_E to COND_NE.
3315X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3316 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3317 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3318 case X86::COND_E: return X86::COND_NE;
3319 case X86::COND_NE: return X86::COND_E;
3320 case X86::COND_L: return X86::COND_GE;
3321 case X86::COND_LE: return X86::COND_G;
3322 case X86::COND_G: return X86::COND_LE;
3323 case X86::COND_GE: return X86::COND_L;
3324 case X86::COND_B: return X86::COND_AE;
3325 case X86::COND_BE: return X86::COND_A;
3326 case X86::COND_A: return X86::COND_BE;
3327 case X86::COND_AE: return X86::COND_B;
3328 case X86::COND_S: return X86::COND_NS;
3329 case X86::COND_NS: return X86::COND_S;
3330 case X86::COND_P: return X86::COND_NP;
3331 case X86::COND_NP: return X86::COND_P;
3332 case X86::COND_O: return X86::COND_NO;
3333 case X86::COND_NO: return X86::COND_O;
3334 }
3335}
3336
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3337/// Assuming the flags are set by MI(a,b), return the condition code if we
3338/// modify the instructions such that flags are set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]3339static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3340 switch (CC) {
3341 default: return X86::COND_INVALID;
3342 case X86::COND_E: return X86::COND_E;
3343 case X86::COND_NE: return X86::COND_NE;
3344 case X86::COND_L: return X86::COND_G;
3345 case X86::COND_LE: return X86::COND_GE;
3346 case X86::COND_G: return X86::COND_L;
3347 case X86::COND_GE: return X86::COND_LE;
3348 case X86::COND_B: return X86::COND_A;
3349 case X86::COND_BE: return X86::COND_AE;
3350 case X86::COND_A: return X86::COND_B;
3351 case X86::COND_AE: return X86::COND_BE;
3352 }
3353}
3354
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3355/// Return a set opcode for the given condition and
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3356/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3357unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3358 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3359 { X86::SETAr, X86::SETAm },
3360 { X86::SETAEr, X86::SETAEm },
3361 { X86::SETBr, X86::SETBm },
3362 { X86::SETBEr, X86::SETBEm },
3363 { X86::SETEr, X86::SETEm },
3364 { X86::SETGr, X86::SETGm },
3365 { X86::SETGEr, X86::SETGEm },
3366 { X86::SETLr, X86::SETLm },
3367 { X86::SETLEr, X86::SETLEm },
3368 { X86::SETNEr, X86::SETNEm },
3369 { X86::SETNOr, X86::SETNOm },
3370 { X86::SETNPr, X86::SETNPm },
3371 { X86::SETNSr, X86::SETNSm },
3372 { X86::SETOr, X86::SETOm },
3373 { X86::SETPr, X86::SETPm },
3374 { X86::SETSr, X86::SETSm }
3375 };
3376
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3377 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3378 return Opc[CC][HasMemoryOperand ? 1 : 0];
3379}
3380
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3381/// Return a cmov opcode for the given condition,
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3382/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]3383unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3384 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3385 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3386 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3387 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3388 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3389 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3390 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3391 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3392 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3393 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3394 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3395 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3396 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3397 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3398 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3399 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3400 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3401 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3402 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3403 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3404 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3405 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3406 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3407 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3408 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3409 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3410 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3411 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3412 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3413 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3414 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3415 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3416 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3417 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3418 };
3419
3420 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3421 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3422 switch(RegBytes) {
3423 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3424 case 2: return Opc[Idx][0];
3425 case 4: return Opc[Idx][1];
3426 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3427 }
3428}
3429
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3430bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3431 if (!MI->isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3432
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3433 // Conditional branch is a special case.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3434 if (MI->isBranch() && !MI->isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3435 return true;
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3436 if (!MI->isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3437 return true;
3438 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3439}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3440
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]3441bool X86InstrInfo::AnalyzeBranchImpl(
3442 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3443 SmallVectorImpl<MachineOperand> &Cond,
3444 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3445
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3446 // Start from the bottom of the block and work up, examining the
3447 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3448 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3449 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3450 while (I != MBB.begin()) {
3451 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]3452 if (I->isDebugValue())
3453 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3454
3455 // Working from the bottom, when we see a non-terminator instruction, we're
3456 // done.
Jakob Stoklund Olesenc30b4dd2010-07-16 17:41:44 +0000[diff] [blame]3457 if (!isUnpredicatedTerminator(I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3458 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3459
3460 // A terminator that isn't a branch can't easily be handled by this
3461 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3462 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3463 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3464
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3465 // Handle unconditional branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3466 if (I->getOpcode() == X86::JMP_1) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3467 UnCondBrIter = I;
3468
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3469 if (!AllowModify) {
3470 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]3471 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3472 }
3473
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3474 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]3475 while (std::next(I) != MBB.end())
3476 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3477
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3478 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3479 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3480
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3481 // Delete the JMP if it's equivalent to a fall-through.
3482 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3483 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3484 I->eraseFromParent();
3485 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3486 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3487 continue;
3488 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3489
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3490 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3491 TBB = I->getOperand(0).getMBB();
3492 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3493 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3494
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3495 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3496 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3497 if (BranchCode == X86::COND_INVALID)
3498 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3499
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3500 // Working from the bottom, handle the first conditional branch.
3501 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3502 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3503 if (AllowModify && UnCondBrIter != MBB.end() &&
3504 MBB.isLayoutSuccessor(TargetBB)) {
3505 // If we can modify the code and it ends in something like:
3506 //
3507 // jCC L1
3508 // jmp L2
3509 // L1:
3510 // ...
3511 // L2:
3512 //
3513 // Then we can change this to:
3514 //
3515 // jnCC L2
3516 // L1:
3517 // ...
3518 // L2:
3519 //
3520 // Which is a bit more efficient.
3521 // We conditionally jump to the fall-through block.
3522 BranchCode = GetOppositeBranchCondition(BranchCode);
3523 unsigned JNCC = GetCondBranchFromCond(BranchCode);
3524 MachineBasicBlock::iterator OldInst = I;
3525
3526 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3527 .addMBB(UnCondBrIter->getOperand(0).getMBB());
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3528 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3529 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3530
3531 OldInst->eraseFromParent();
3532 UnCondBrIter->eraseFromParent();
3533
3534 // Restart the analysis.
3535 UnCondBrIter = MBB.end();
3536 I = MBB.end();
3537 continue;
3538 }
3539
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3540 FBB = TBB;
3541 TBB = I->getOperand(0).getMBB();
3542 Cond.push_back(MachineOperand::CreateImm(BranchCode));
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]3543 CondBranches.push_back(I);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3544 continue;
3545 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3546
3547 // Handle subsequent conditional branches. Only handle the case where all
3548 // conditional branches branch to the same destination and their condition
3549 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3550 assert(Cond.size() == 1);
3551 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3552
3553 // Only handle the case where all conditional branches branch to the same
3554 // destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3555 if (TBB != I->getOperand(0).getMBB())
3556 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3557
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3558 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3559 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3560 if (OldBranchCode == BranchCode)
3561 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3562
3563 // If they differ, see if they fit one of the known patterns. Theoretically,
3564 // we could handle more patterns here, but we shouldn't expect to see them
3565 // if instruction selection has done a reasonable job.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3566 if ((OldBranchCode == X86::COND_NP &&
3567 BranchCode == X86::COND_E) ||
3568 (OldBranchCode == X86::COND_E &&
3569 BranchCode == X86::COND_NP))
3570 BranchCode = X86::COND_NP_OR_E;
3571 else if ((OldBranchCode == X86::COND_P &&
3572 BranchCode == X86::COND_NE) ||
3573 (OldBranchCode == X86::COND_NE &&
3574 BranchCode == X86::COND_P))
3575 BranchCode = X86::COND_NE_OR_P;
3576 else
3577 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3578
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3579 // Update the MachineOperand.
3580 Cond[0].setImm(BranchCode);
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]3581 CondBranches.push_back(I);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]3582 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3583
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3584 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3585}
3586
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]3587bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
3588 MachineBasicBlock *&TBB,
3589 MachineBasicBlock *&FBB,
3590 SmallVectorImpl<MachineOperand> &Cond,
3591 bool AllowModify) const {
3592 SmallVector<MachineInstr *, 4> CondBranches;
3593 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
3594}
3595
3596bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB,
3597 MachineBranchPredicate &MBP,
3598 bool AllowModify) const {
3599 using namespace std::placeholders;
3600
3601 SmallVector<MachineOperand, 4> Cond;
3602 SmallVector<MachineInstr *, 4> CondBranches;
3603 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
3604 AllowModify))
3605 return true;
3606
3607 if (Cond.size() != 1)
3608 return true;
3609
3610 assert(MBP.TrueDest && "expected!");
3611
3612 if (!MBP.FalseDest)
3613 MBP.FalseDest = MBB.getNextNode();
3614
3615 const TargetRegisterInfo *TRI = &getRegisterInfo();
3616
3617 MachineInstr *ConditionDef = nullptr;
3618 bool SingleUseCondition = true;
3619
3620 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
3621 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
3622 ConditionDef = &*I;
3623 break;
3624 }
3625
3626 if (I->readsRegister(X86::EFLAGS, TRI))
3627 SingleUseCondition = false;
3628 }
3629
3630 if (!ConditionDef)
3631 return true;
3632
3633 if (SingleUseCondition) {
3634 for (auto *Succ : MBB.successors())
3635 if (Succ->isLiveIn(X86::EFLAGS))
3636 SingleUseCondition = false;
3637 }
3638
3639 MBP.ConditionDef = ConditionDef;
3640 MBP.SingleUseCondition = SingleUseCondition;
3641
3642 // Currently we only recognize the simple pattern:
3643 //
3644 // test %reg, %reg
3645 // je %label
3646 //
3647 const unsigned TestOpcode =
3648 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
3649
3650 if (ConditionDef->getOpcode() == TestOpcode &&
3651 ConditionDef->getNumOperands() == 3 &&
3652 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
3653 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
3654 MBP.LHS = ConditionDef->getOperand(0);
3655 MBP.RHS = MachineOperand::CreateImm(0);
3656 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
3657 ? MachineBranchPredicate::PRED_NE
3658 : MachineBranchPredicate::PRED_EQ;
3659 return false;
3660 }
3661
3662 return true;
3663}
3664
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3665unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3666 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3667 unsigned Count = 0;
3668
3669 while (I != MBB.begin()) {
3670 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]3671 if (I->isDebugValue())
3672 continue;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3673 if (I->getOpcode() != X86::JMP_1 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3674 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3675 break;
3676 // Remove the branch.
3677 I->eraseFromParent();
3678 I = MBB.end();
3679 ++Count;
3680 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3681
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3682 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3683}
3684
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3685unsigned
3686X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]3687 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3688 DebugLoc DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3689 // Shouldn't be a fall through.
3690 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]3691 assert((Cond.size() == 1 || Cond.size() == 0) &&
3692 "X86 branch conditions have one component!");
3693
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3694 if (Cond.empty()) {
3695 // Unconditional branch?
3696 assert(!FBB && "Unconditional branch with multiple successors!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3697 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]3698 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3699 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3700
3701 // Conditional branch.
3702 unsigned Count = 0;
3703 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
3704 switch (CC) {
3705 case X86::COND_NP_OR_E:
3706 // Synthesize NP_OR_E with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3707 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3708 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3709 BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3710 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3711 break;
3712 case X86::COND_NE_OR_P:
3713 // Synthesize NE_OR_P with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3714 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3715 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3716 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3717 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3718 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3719 default: {
3720 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]3721 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3722 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3723 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]3724 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3725 if (FBB) {
3726 // Two-way Conditional branch. Insert the second branch.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3727 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3728 ++Count;
3729 }
3730 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3731}
3732
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3733bool X86InstrInfo::
3734canInsertSelect(const MachineBasicBlock &MBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]3735 ArrayRef<MachineOperand> Cond,
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3736 unsigned TrueReg, unsigned FalseReg,
3737 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
3738 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3739 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3740 return false;
3741 if (Cond.size() != 1)
3742 return false;
3743 // We cannot do the composite conditions, at least not in SSA form.
3744 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
3745 return false;
3746
3747 // Check register classes.
3748 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3749 const TargetRegisterClass *RC =
3750 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
3751 if (!RC)
3752 return false;
3753
3754 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
3755 if (X86::GR16RegClass.hasSubClassEq(RC) ||
3756 X86::GR32RegClass.hasSubClassEq(RC) ||
3757 X86::GR64RegClass.hasSubClassEq(RC)) {
3758 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
3759 // Bridge. Probably Ivy Bridge as well.
3760 CondCycles = 2;
3761 TrueCycles = 2;
3762 FalseCycles = 2;
3763 return true;
3764 }
3765
3766 // Can't do vectors.
3767 return false;
3768}
3769
3770void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
3771 MachineBasicBlock::iterator I, DebugLoc DL,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]3772 unsigned DstReg, ArrayRef<MachineOperand> Cond,
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3773 unsigned TrueReg, unsigned FalseReg) const {
3774 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
3775 assert(Cond.size() == 1 && "Invalid Cond array");
3776 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3777 MRI.getRegClass(DstReg)->getSize(),
3778 false/*HasMemoryOperand*/);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3779 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
3780}
3781
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3782/// Test if the given register is a physical h register.
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]3783static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]3784 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]3785}
3786
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3787// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3788static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3789 const X86Subtarget &Subtarget) {
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3790
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3791 // SrcReg(VR128) -> DestReg(GR64)
3792 // SrcReg(VR64) -> DestReg(GR64)
3793 // SrcReg(GR64) -> DestReg(VR128)
3794 // SrcReg(GR64) -> DestReg(VR64)
3795
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3796 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3797 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3798 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3799 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3800 // Copy from a VR128 register to a GR64 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3801 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
3802 X86::MOVPQIto64rr);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3803 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3804 // Copy from a VR64 register to a GR64 register.
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]3805 return X86::MMX_MOVD64from64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3806 } else if (X86::GR64RegClass.contains(SrcReg)) {
3807 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3808 if (X86::VR128XRegClass.contains(DestReg))
3809 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
3810 X86::MOV64toPQIrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3811 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3812 if (X86::VR64RegClass.contains(DestReg))
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]3813 return X86::MMX_MOVD64to64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3814 }
3815
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]3816 // SrcReg(FR32) -> DestReg(GR32)
3817 // SrcReg(GR32) -> DestReg(FR32)
3818
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3819 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3820 // Copy from a FR32 register to a GR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3821 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]3822
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3823 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3824 // Copy from a GR32 register to a FR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3825 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]3826 return 0;
3827}
3828
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3829inline static bool MaskRegClassContains(unsigned Reg) {
3830 return X86::VK8RegClass.contains(Reg) ||
3831 X86::VK16RegClass.contains(Reg) ||
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]3832 X86::VK32RegClass.contains(Reg) ||
3833 X86::VK64RegClass.contains(Reg) ||
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3834 X86::VK1RegClass.contains(Reg);
3835}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3836static
3837unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg) {
3838 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
3839 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
3840 X86::VR512RegClass.contains(DestReg, SrcReg)) {
3841 DestReg = get512BitSuperRegister(DestReg);
3842 SrcReg = get512BitSuperRegister(SrcReg);
3843 return X86::VMOVAPSZrr;
3844 }
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3845 if (MaskRegClassContains(DestReg) &&
3846 MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3847 return X86::KMOVWkk;
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3848 if (MaskRegClassContains(DestReg) &&
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]3849 (X86::GR32RegClass.contains(SrcReg) ||
3850 X86::GR16RegClass.contains(SrcReg) ||
3851 X86::GR8RegClass.contains(SrcReg))) {
3852 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
3853 return X86::KMOVWkr;
3854 }
3855 if ((X86::GR32RegClass.contains(DestReg) ||
3856 X86::GR16RegClass.contains(DestReg) ||
3857 X86::GR8RegClass.contains(DestReg)) &&
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]3858 MaskRegClassContains(SrcReg)) {
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]3859 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
3860 return X86::KMOVWrk;
3861 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3862 return 0;
3863}
3864
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3865void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
3866 MachineBasicBlock::iterator MI, DebugLoc DL,
3867 unsigned DestReg, unsigned SrcReg,
3868 bool KillSrc) const {
3869 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3870 bool HasAVX = Subtarget.hasAVX();
3871 bool HasAVX512 = Subtarget.hasAVX512();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3872 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3873 if (X86::GR64RegClass.contains(DestReg, SrcReg))
3874 Opc = X86::MOV64rr;
3875 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
3876 Opc = X86::MOV32rr;
3877 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
3878 Opc = X86::MOV16rr;
3879 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
3880 // Copying to or from a physical H register on x86-64 requires a NOREX
3881 // move. Otherwise use a normal move.
3882 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3883 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3884 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]3885 // Both operands must be encodable without an REX prefix.
3886 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
3887 "8-bit H register can not be copied outside GR8_NOREX");
3888 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3889 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3890 }
3891 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
3892 Opc = X86::MMX_MOVQ64rr;
3893 else if (HasAVX512)
3894 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg);
3895 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]3896 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]3897 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
3898 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]3899 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3900 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3901
3902 if (Opc) {
3903 BuildMI(MBB, MI, DL, get(Opc), DestReg)
3904 .addReg(SrcReg, getKillRegState(KillSrc));
3905 return;
3906 }
3907
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]3908 bool FromEFLAGS = SrcReg == X86::EFLAGS;
3909 bool ToEFLAGS = DestReg == X86::EFLAGS;
3910 int Reg = FromEFLAGS ? DestReg : SrcReg;
3911 bool is32 = X86::GR32RegClass.contains(Reg);
3912 bool is64 = X86::GR64RegClass.contains(Reg);
3913 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
3914 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
3915 // inefficient. Instead:
3916 // - Save the overflow flag OF into AL using SETO, and restore it using a
3917 // signed 8-bit addition of AL and INT8_MAX.
3918 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
3919 // using LAHF/SAHF.
3920 // - When RAX/EAX is live and isn't the destination register, make sure it
3921 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
3922 // the flags.
3923 // This approach is ~2.25x faster than using PUSHF/POPF.
3924 //
3925 // This is still somewhat inefficient because we don't know which flags are
3926 // actually live inside EFLAGS. Were we able to do a single SETcc instead of
3927 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
3928 //
3929 // PUSHF/POPF is also potentially incorrect because it affects other flags
3930 // such as TF/IF/DF, which LLVM doesn't model.
3931 //
3932 // Notice that we have to adjust the stack if we don't want to clobber the
3933 // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
3934
3935 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
3936 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
3937 int Pop = is64 ? X86::POP64r : X86::POP32r;
3938 int AX = is64 ? X86::RAX : X86::EAX;
3939
3940 bool AXDead = (Reg == AX) ||
3941 (MachineBasicBlock::LQR_Dead ==
3942 MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI));
3943
3944 if (!AXDead)
3945 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
3946 if (FromEFLAGS) {
3947 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
3948 BuildMI(MBB, MI, DL, get(X86::LAHF));
3949 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]3950 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]3951 if (ToEFLAGS) {
3952 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
3953 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
3954 .addReg(X86::AL)
3955 .addImm(INT8_MAX);
3956 BuildMI(MBB, MI, DL, get(X86::SAHF));
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3957 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]3958 if (!AXDead)
3959 BuildMI(MBB, MI, DL, get(Pop), AX);
3960 return;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]3961 }
3962
3963 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
3964 << " to " << RI.getName(DestReg) << '\n');
3965 llvm_unreachable("Cannot emit physreg copy instruction");
3966}
3967
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3968static unsigned getLoadStoreRegOpcode(unsigned Reg,
3969 const TargetRegisterClass *RC,
3970 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3971 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]3972 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3973 if (STI.hasAVX512()) {
Andrew Trick8460a3b2013-10-14 22:18:56 +0000[diff] [blame]3974 if (X86::VK8RegClass.hasSubClassEq(RC) ||
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3975 X86::VK16RegClass.hasSubClassEq(RC))
3976 return load ? X86::KMOVWkm : X86::KMOVWmk;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3977 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3978 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3979 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3980 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]3981 if (X86::VR512RegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]3982 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
3983 }
3984
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3985 bool HasAVX = STI.hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3986 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]3987 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3988 llvm_unreachable("Unknown spill size");
3989 case 1:
3990 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]3991 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]3992 // Copying to or from a physical H register on x86-64 requires a NOREX
3993 // move. Otherwise use a normal move.
3994 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
3995 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
3996 return load ? X86::MOV8rm : X86::MOV8mr;
3997 case 2:
3998 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
3999 return load ? X86::MOV16rm : X86::MOV16mr;
4000 case 4:
4001 if (X86::GR32RegClass.hasSubClassEq(RC))
4002 return load ? X86::MOV32rm : X86::MOV32mr;
4003 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4004 return load ?
4005 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4006 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4007 if (X86::RFP32RegClass.hasSubClassEq(RC))
4008 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4009 llvm_unreachable("Unknown 4-byte regclass");
4010 case 8:
4011 if (X86::GR64RegClass.hasSubClassEq(RC))
4012 return load ? X86::MOV64rm : X86::MOV64mr;
4013 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4014 return load ?
4015 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4016 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4017 if (X86::VR64RegClass.hasSubClassEq(RC))
4018 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4019 if (X86::RFP64RegClass.hasSubClassEq(RC))
4020 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4021 llvm_unreachable("Unknown 8-byte regclass");
4022 case 10:
4023 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4024 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4025 case 16: {
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4026 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4027 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4028 // If stack is realigned we can use aligned stores.
4029 if (isStackAligned)
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4030 return load ?
4031 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
4032 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4033 else
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4034 return load ?
4035 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
4036 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4037 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4038 case 32:
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4039 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4040 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4041 // If stack is realigned we can use aligned stores.
4042 if (isStackAligned)
4043 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4044 else
4045 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4046 case 64:
4047 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4048 if (isStackAligned)
4049 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4050 else
4051 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4052 }
4053}
4054
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4055bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
4056 unsigned &Offset,
4057 const TargetRegisterInfo *TRI) const {
4058 const MCInstrDesc &Desc = MemOp->getDesc();
4059 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags, MemOp->getOpcode());
4060 if (MemRefBegin < 0)
4061 return false;
4062
4063 MemRefBegin += X86II::getOperandBias(Desc);
4064
4065 BaseReg = MemOp->getOperand(MemRefBegin + X86::AddrBaseReg).getReg();
4066 if (MemOp->getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4067 return false;
4068
4069 if (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
4070 X86::NoRegister)
4071 return false;
4072
4073 const MachineOperand &DispMO = MemOp->getOperand(MemRefBegin + X86::AddrDisp);
4074
4075 // Displacement can be symbolic
4076 if (!DispMO.isImm())
4077 return false;
4078
4079 Offset = DispMO.getImm();
4080
4081 return (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4082 X86::NoRegister);
4083}
4084
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4085static unsigned getStoreRegOpcode(unsigned SrcReg,
4086 const TargetRegisterClass *RC,
4087 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4088 const X86Subtarget &STI) {
4089 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4090}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4091
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4092
4093static unsigned getLoadRegOpcode(unsigned DestReg,
4094 const TargetRegisterClass *RC,
4095 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4096 const X86Subtarget &STI) {
4097 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4098}
4099
4100void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4101 MachineBasicBlock::iterator MI,
4102 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4103 const TargetRegisterClass *RC,
4104 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4105 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]4106 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4107 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4108 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4109 bool isAligned =
4110 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4111 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4112 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4113 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4114 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4115 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4116}
4117
4118void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4119 bool isKill,
4120 SmallVectorImpl<MachineOperand> &Addr,
4121 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4122 MachineInstr::mmo_iterator MMOBegin,
4123 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4124 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4125 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4126 bool isAligned = MMOBegin != MMOEnd &&
4127 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4128 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4129 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4130 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4131 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4132 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4133 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4134 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4135 NewMIs.push_back(MIB);
4136}
4137
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4138
4139void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4140 MachineBasicBlock::iterator MI,
4141 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4142 const TargetRegisterClass *RC,
4143 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4144 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4145 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4146 bool isAligned =
4147 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4148 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4149 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4150 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4151 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4152}
4153
4154void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]4155 SmallVectorImpl<MachineOperand> &Addr,
4156 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4157 MachineInstr::mmo_iterator MMOBegin,
4158 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4159 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4160 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4161 bool isAligned = MMOBegin != MMOEnd &&
4162 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4163 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4164 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4165 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4166 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4167 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4168 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4169 NewMIs.push_back(MIB);
4170}
4171
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4172bool X86InstrInfo::
4173analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
4174 int &CmpMask, int &CmpValue) const {
4175 switch (MI->getOpcode()) {
4176 default: break;
4177 case X86::CMP64ri32:
4178 case X86::CMP64ri8:
4179 case X86::CMP32ri:
4180 case X86::CMP32ri8:
4181 case X86::CMP16ri:
4182 case X86::CMP16ri8:
4183 case X86::CMP8ri:
4184 SrcReg = MI->getOperand(0).getReg();
4185 SrcReg2 = 0;
4186 CmpMask = ~0;
4187 CmpValue = MI->getOperand(1).getImm();
4188 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4189 // A SUB can be used to perform comparison.
4190 case X86::SUB64rm:
4191 case X86::SUB32rm:
4192 case X86::SUB16rm:
4193 case X86::SUB8rm:
4194 SrcReg = MI->getOperand(1).getReg();
4195 SrcReg2 = 0;
4196 CmpMask = ~0;
4197 CmpValue = 0;
4198 return true;
4199 case X86::SUB64rr:
4200 case X86::SUB32rr:
4201 case X86::SUB16rr:
4202 case X86::SUB8rr:
4203 SrcReg = MI->getOperand(1).getReg();
4204 SrcReg2 = MI->getOperand(2).getReg();
4205 CmpMask = ~0;
4206 CmpValue = 0;
4207 return true;
4208 case X86::SUB64ri32:
4209 case X86::SUB64ri8:
4210 case X86::SUB32ri:
4211 case X86::SUB32ri8:
4212 case X86::SUB16ri:
4213 case X86::SUB16ri8:
4214 case X86::SUB8ri:
4215 SrcReg = MI->getOperand(1).getReg();
4216 SrcReg2 = 0;
4217 CmpMask = ~0;
4218 CmpValue = MI->getOperand(2).getImm();
4219 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4220 case X86::CMP64rr:
4221 case X86::CMP32rr:
4222 case X86::CMP16rr:
4223 case X86::CMP8rr:
4224 SrcReg = MI->getOperand(0).getReg();
4225 SrcReg2 = MI->getOperand(1).getReg();
4226 CmpMask = ~0;
4227 CmpValue = 0;
4228 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4229 case X86::TEST8rr:
4230 case X86::TEST16rr:
4231 case X86::TEST32rr:
4232 case X86::TEST64rr:
4233 SrcReg = MI->getOperand(0).getReg();
4234 if (MI->getOperand(1).getReg() != SrcReg) return false;
4235 // Compare against zero.
4236 SrcReg2 = 0;
4237 CmpMask = ~0;
4238 CmpValue = 0;
4239 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4240 }
4241 return false;
4242}
4243
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4244/// Check whether the first instruction, whose only
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4245/// purpose is to update flags, can be made redundant.
4246/// CMPrr can be made redundant by SUBrr if the operands are the same.
4247/// This function can be extended later on.
4248/// SrcReg, SrcRegs: register operands for FlagI.
4249/// ImmValue: immediate for FlagI if it takes an immediate.
4250inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4251 unsigned SrcReg2, int ImmValue,
4252 MachineInstr *OI) {
4253 if (((FlagI->getOpcode() == X86::CMP64rr &&
4254 OI->getOpcode() == X86::SUB64rr) ||
4255 (FlagI->getOpcode() == X86::CMP32rr &&
4256 OI->getOpcode() == X86::SUB32rr)||
4257 (FlagI->getOpcode() == X86::CMP16rr &&
4258 OI->getOpcode() == X86::SUB16rr)||
4259 (FlagI->getOpcode() == X86::CMP8rr &&
4260 OI->getOpcode() == X86::SUB8rr)) &&
4261 ((OI->getOperand(1).getReg() == SrcReg &&
4262 OI->getOperand(2).getReg() == SrcReg2) ||
4263 (OI->getOperand(1).getReg() == SrcReg2 &&
4264 OI->getOperand(2).getReg() == SrcReg)))
4265 return true;
4266
4267 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4268 OI->getOpcode() == X86::SUB64ri32) ||
4269 (FlagI->getOpcode() == X86::CMP64ri8 &&
4270 OI->getOpcode() == X86::SUB64ri8) ||
4271 (FlagI->getOpcode() == X86::CMP32ri &&
4272 OI->getOpcode() == X86::SUB32ri) ||
4273 (FlagI->getOpcode() == X86::CMP32ri8 &&
4274 OI->getOpcode() == X86::SUB32ri8) ||
4275 (FlagI->getOpcode() == X86::CMP16ri &&
4276 OI->getOpcode() == X86::SUB16ri) ||
4277 (FlagI->getOpcode() == X86::CMP16ri8 &&
4278 OI->getOpcode() == X86::SUB16ri8) ||
4279 (FlagI->getOpcode() == X86::CMP8ri &&
4280 OI->getOpcode() == X86::SUB8ri)) &&
4281 OI->getOperand(1).getReg() == SrcReg &&
4282 OI->getOperand(2).getImm() == ImmValue)
4283 return true;
4284 return false;
4285}
4286
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4287/// Check whether the definition can be converted
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4288/// to remove a comparison against zero.
4289inline static bool isDefConvertible(MachineInstr *MI) {
4290 switch (MI->getOpcode()) {
4291 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]4292
4293 // The shift instructions only modify ZF if their shift count is non-zero.
4294 // N.B.: The processor truncates the shift count depending on the encoding.
4295 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
4296 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
4297 return getTruncatedShiftCount(MI, 2) != 0;
4298
4299 // Some left shift instructions can be turned into LEA instructions but only
4300 // if their flags aren't used. Avoid transforming such instructions.
4301 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
4302 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4303 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4304 return ShAmt != 0;
4305 }
4306
4307 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4308 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4309 return getTruncatedShiftCount(MI, 3) != 0;
4310
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4311 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4312 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
4313 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
4314 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
4315 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4316 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4317 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4318 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
4319 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
4320 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
4321 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4322 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4323 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4324 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
4325 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
4326 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
4327 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
4328 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4329 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
4330 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
4331 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
4332 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
4333 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
4334 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
4335 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
4336 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
4337 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4338 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4339 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4340 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4341 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
4342 case X86::ADC32ri: case X86::ADC32ri8:
4343 case X86::ADC32rr: case X86::ADC64ri32:
4344 case X86::ADC64ri8: case X86::ADC64rr:
4345 case X86::SBB32ri: case X86::SBB32ri8:
4346 case X86::SBB32rr: case X86::SBB64ri32:
4347 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]4348 case X86::ANDN32rr: case X86::ANDN32rm:
4349 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4350 case X86::BEXTR32rr: case X86::BEXTR64rr:
4351 case X86::BEXTR32rm: case X86::BEXTR64rm:
4352 case X86::BLSI32rr: case X86::BLSI32rm:
4353 case X86::BLSI64rr: case X86::BLSI64rm:
4354 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4355 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4356 case X86::BLSR32rr: case X86::BLSR32rm:
4357 case X86::BLSR64rr: case X86::BLSR64rm:
4358 case X86::BZHI32rr: case X86::BZHI32rm:
4359 case X86::BZHI64rr: case X86::BZHI64rm:
4360 case X86::LZCNT16rr: case X86::LZCNT16rm:
4361 case X86::LZCNT32rr: case X86::LZCNT32rm:
4362 case X86::LZCNT64rr: case X86::LZCNT64rm:
4363 case X86::POPCNT16rr:case X86::POPCNT16rm:
4364 case X86::POPCNT32rr:case X86::POPCNT32rm:
4365 case X86::POPCNT64rr:case X86::POPCNT64rm:
4366 case X86::TZCNT16rr: case X86::TZCNT16rm:
4367 case X86::TZCNT32rr: case X86::TZCNT32rm:
4368 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4369 return true;
4370 }
4371}
4372
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4373/// Check whether the use can be converted to remove a comparison against zero.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4374static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
4375 switch (MI->getOpcode()) {
4376 default: return X86::COND_INVALID;
4377 case X86::LZCNT16rr: case X86::LZCNT16rm:
4378 case X86::LZCNT32rr: case X86::LZCNT32rm:
4379 case X86::LZCNT64rr: case X86::LZCNT64rm:
4380 return X86::COND_B;
4381 case X86::POPCNT16rr:case X86::POPCNT16rm:
4382 case X86::POPCNT32rr:case X86::POPCNT32rm:
4383 case X86::POPCNT64rr:case X86::POPCNT64rm:
4384 return X86::COND_E;
4385 case X86::TZCNT16rr: case X86::TZCNT16rm:
4386 case X86::TZCNT32rr: case X86::TZCNT32rm:
4387 case X86::TZCNT64rr: case X86::TZCNT64rm:
4388 return X86::COND_B;
4389 }
4390}
4391
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4392/// Check if there exists an earlier instruction that
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4393/// operates on the same source operands and sets flags in the same way as
4394/// Compare; remove Compare if possible.
4395bool X86InstrInfo::
4396optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
4397 int CmpMask, int CmpValue,
4398 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4399 // Check whether we can replace SUB with CMP.
4400 unsigned NewOpcode = 0;
4401 switch (CmpInstr->getOpcode()) {
4402 default: break;
4403 case X86::SUB64ri32:
4404 case X86::SUB64ri8:
4405 case X86::SUB32ri:
4406 case X86::SUB32ri8:
4407 case X86::SUB16ri:
4408 case X86::SUB16ri8:
4409 case X86::SUB8ri:
4410 case X86::SUB64rm:
4411 case X86::SUB32rm:
4412 case X86::SUB16rm:
4413 case X86::SUB8rm:
4414 case X86::SUB64rr:
4415 case X86::SUB32rr:
4416 case X86::SUB16rr:
4417 case X86::SUB8rr: {
4418 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
4419 return false;
4420 // There is no use of the destination register, we can replace SUB with CMP.
4421 switch (CmpInstr->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]4422 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4423 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
4424 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
4425 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
4426 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
4427 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
4428 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
4429 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
4430 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
4431 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4432 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
4433 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
4434 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
4435 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
4436 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
4437 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
4438 }
4439 CmpInstr->setDesc(get(NewOpcode));
4440 CmpInstr->RemoveOperand(0);
4441 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4442 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4443 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4444 return false;
4445 }
4446 }
4447
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4448 // Get the unique definition of SrcReg.
4449 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4450 if (!MI) return false;
4451
4452 // CmpInstr is the first instruction of the BB.
4453 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4454
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4455 // If we are comparing against zero, check whether we can use MI to update
4456 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4457 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4458 if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4459 return false;
4460
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4461 // If we have a use of the source register between the def and our compare
4462 // instruction we can eliminate the compare iff the use sets EFLAGS in the
4463 // right way.
4464 bool ShouldUpdateCC = false;
4465 X86::CondCode NewCC = X86::COND_INVALID;
4466 if (IsCmpZero && !isDefConvertible(MI)) {
4467 // Scan forward from the use until we hit the use we're looking for or the
4468 // compare instruction.
4469 for (MachineBasicBlock::iterator J = MI;; ++J) {
4470 // Do we have a convertible instruction?
4471 NewCC = isUseDefConvertible(J);
4472 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4473 J->getOperand(1).getReg() == SrcReg) {
4474 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
4475 ShouldUpdateCC = true; // Update CC later on.
4476 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
4477 // with the new def.
4478 MI = Def = J;
4479 break;
4480 }
4481
4482 if (J == I)
4483 return false;
4484 }
4485 }
4486
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4487 // We are searching for an earlier instruction that can make CmpInstr
4488 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4489 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4490 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4491
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4492 // We iterate backward, starting from the instruction before CmpInstr and
4493 // stop when reaching the definition of a source register or done with the BB.
4494 // RI points to the instruction before CmpInstr.
4495 // If the definition is in this basic block, RE points to the definition;
4496 // otherwise, RE is the rend of the basic block.
4497 MachineBasicBlock::reverse_iterator
4498 RI = MachineBasicBlock::reverse_iterator(I),
4499 RE = CmpInstr->getParent() == MI->getParent() ?
4500 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
4501 CmpInstr->getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4502 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4503 for (; RI != RE; ++RI) {
4504 MachineInstr *Instr = &*RI;
4505 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4506 if (!IsCmpZero &&
4507 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4508 Sub = Instr;
4509 break;
4510 }
4511
4512 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4513 Instr->readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4514 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4515
4516 // MOV32r0 etc. are implemented with xor which clobbers condition code.
4517 // They are safe to move up, if the definition to EFLAGS is dead and
4518 // earlier instructions do not read or write EFLAGS.
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4519 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4520 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
4521 Movr0Inst = Instr;
4522 continue;
4523 }
4524
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4525 // We can't remove CmpInstr.
4526 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4527 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4528 }
4529
4530 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4531 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4532 return false;
4533
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4534 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
4535 Sub->getOperand(2).getReg() == SrcReg);
4536
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4537 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4538 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
4539 // If we are done with the basic block, we need to check whether EFLAGS is
4540 // live-out.
4541 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4542 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
4543 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
4544 for (++I; I != E; ++I) {
4545 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]4546 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
4547 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
4548 // We should check the usage if this instruction uses and updates EFLAGS.
4549 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4550 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4551 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4552 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4553 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]4554 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4555 continue;
4556
4557 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]4558 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4559 bool OpcIsSET = false;
4560 if (IsCmpZero || IsSwapped) {
4561 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4562 if (Instr.isBranch())
4563 OldCC = getCondFromBranchOpc(Instr.getOpcode());
4564 else {
4565 OldCC = getCondFromSETOpc(Instr.getOpcode());
4566 if (OldCC != X86::COND_INVALID)
4567 OpcIsSET = true;
4568 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]4569 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4570 }
4571 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4572 }
4573 if (IsCmpZero) {
4574 switch (OldCC) {
4575 default: break;
4576 case X86::COND_A: case X86::COND_AE:
4577 case X86::COND_B: case X86::COND_BE:
4578 case X86::COND_G: case X86::COND_GE:
4579 case X86::COND_L: case X86::COND_LE:
4580 case X86::COND_O: case X86::COND_NO:
4581 // CF and OF are used, we can't perform this optimization.
4582 return false;
4583 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4584
4585 // If we're updating the condition code check if we have to reverse the
4586 // condition.
4587 if (ShouldUpdateCC)
4588 switch (OldCC) {
4589 default:
4590 return false;
4591 case X86::COND_E:
4592 break;
4593 case X86::COND_NE:
4594 NewCC = GetOppositeBranchCondition(NewCC);
4595 break;
4596 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4597 } else if (IsSwapped) {
4598 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
4599 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
4600 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4601 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4602 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4603 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4604
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4605 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4606 // Synthesize the new opcode.
4607 bool HasMemoryOperand = Instr.hasOneMemOperand();
4608 unsigned NewOpc;
4609 if (Instr.isBranch())
4610 NewOpc = GetCondBranchFromCond(NewCC);
4611 else if(OpcIsSET)
4612 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
4613 else {
4614 unsigned DstReg = Instr.getOperand(0).getReg();
4615 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
4616 HasMemoryOperand);
4617 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4618
4619 // Push the MachineInstr to OpsToUpdate.
4620 // If it is safe to remove CmpInstr, the condition code of these
4621 // instructions will be modified.
4622 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
4623 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]4624 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
4625 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4626 IsSafe = true;
4627 break;
4628 }
4629 }
4630
4631 // If EFLAGS is not killed nor re-defined, we should check whether it is
4632 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4633 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]4634 MachineBasicBlock *MBB = CmpInstr->getParent();
4635 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
4636 SE = MBB->succ_end(); SI != SE; ++SI)
4637 if ((*SI)->isLiveIn(X86::EFLAGS))
4638 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4639 }
4640
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4641 // The instruction to be updated is either Sub or MI.
4642 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]4643 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4644 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]4645 // Look backwards until we find a def that doesn't use the current EFLAGS.
4646 Def = Sub;
4647 MachineBasicBlock::reverse_iterator
4648 InsertI = MachineBasicBlock::reverse_iterator(++Def),
4649 InsertE = Sub->getParent()->rend();
4650 for (; InsertI != InsertE; ++InsertI) {
4651 MachineInstr *Instr = &*InsertI;
4652 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
4653 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
4654 Sub->getParent()->remove(Movr0Inst);
4655 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
4656 Movr0Inst);
4657 break;
4658 }
4659 }
4660 if (InsertI == InsertE)
4661 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]4662 }
4663
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]4664 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4665 unsigned i = 0, e = Sub->getNumOperands();
4666 for (; i != e; ++i) {
4667 MachineOperand &MO = Sub->getOperand(i);
4668 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
4669 MO.setIsDead(false);
4670 break;
4671 }
4672 }
4673 assert(i != e && "Unable to locate a def EFLAGS operand");
4674
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4675 CmpInstr->eraseFromParent();
4676
4677 // Modify the condition code of instructions in OpsToUpdate.
4678 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
4679 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
4680 return true;
4681}
4682
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4683/// Try to remove the load by folding it to a register
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4684/// operand at the use. We fold the load instructions if load defines a virtual
4685/// register, the virtual register is used once in the same BB, and the
4686/// instructions in-between do not load or store, and have no side effects.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4687MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
4688 const MachineRegisterInfo *MRI,
4689 unsigned &FoldAsLoadDefReg,
4690 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4691 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4692 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4693 // To be conservative, if there exists another load, clear the load candidate.
4694 if (MI->mayLoad()) {
4695 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4696 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4697 }
4698
4699 // Check whether we can move DefMI here.
4700 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
4701 assert(DefMI);
4702 bool SawStore = false;
Matthias Braun07066cc2015-05-19 21:22:20 +0000[diff] [blame]4703 if (!DefMI->isSafeToMove(nullptr, SawStore))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4704 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4705
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4706 // Collect information about virtual register operands of MI.
4707 unsigned SrcOperandId = 0;
4708 bool FoundSrcOperand = false;
4709 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
4710 MachineOperand &MO = MI->getOperand(i);
4711 if (!MO.isReg())
4712 continue;
4713 unsigned Reg = MO.getReg();
4714 if (Reg != FoldAsLoadDefReg)
4715 continue;
4716 // Do not fold if we have a subreg use or a def or multiple uses.
4717 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4718 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4719
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4720 SrcOperandId = i;
4721 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4722 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4723 if (!FoundSrcOperand)
4724 return nullptr;
4725
4726 // Check whether we can fold the def into SrcOperandId.
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]4727 MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4728 if (FoldMI) {
4729 FoldAsLoadDefReg = 0;
4730 return FoldMI;
4731 }
4732
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4733 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]4734}
4735
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4736/// Expand a single-def pseudo instruction to a two-addr
4737/// instruction with two undef reads of the register being defined.
4738/// This is used for mapping:
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4739/// %xmm4 = V_SET0
4740/// to:
4741/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
4742///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4743static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
4744 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4745 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4746 unsigned Reg = MIB->getOperand(0).getReg();
4747 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4748
4749 // MachineInstr::addOperand() will insert explicit operands before any
4750 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4751 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4752 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4753 assert(MIB->getOperand(1).getReg() == Reg &&
4754 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4755 return true;
4756}
4757
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4758// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
4759// code sequence is needed for other targets.
4760static void expandLoadStackGuard(MachineInstrBuilder &MIB,
4761 const TargetInstrInfo &TII) {
4762 MachineBasicBlock &MBB = *MIB->getParent();
4763 DebugLoc DL = MIB->getDebugLoc();
4764 unsigned Reg = MIB->getOperand(0).getReg();
4765 const GlobalValue *GV =
4766 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
4767 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]4768 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
4769 MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]4770 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4771
4772 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
4773 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
4774 .addMemOperand(MMO);
4775 MIB->setDebugLoc(DL);
4776 MIB->setDesc(TII.get(X86::MOV64rm));
4777 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
4778}
4779
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4780bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4781 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4782 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4783 switch (MI->getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]4784 case X86::MOV32r0:
4785 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4786 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4787 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4788 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4789 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4790 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4791 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]4792 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4793 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4794 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]4795 case X86::FsFLD0SS:
4796 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4797 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]4798 case X86::AVX_SET0:
4799 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4800 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]4801 case X86::AVX512_512_SET0:
4802 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4803 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4804 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]4805 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4806 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]4807 case X86::TEST8ri_NOREX:
4808 MI->setDesc(get(X86::TEST8ri));
4809 return true;
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]4810 case X86::KSET0B:
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]4811 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
Elena Demikhovsky702a6ad2015-09-17 06:53:12 +0000[diff] [blame]4812 case X86::KSET0D: return Expand2AddrUndef(MIB, get(X86::KXORDrr));
4813 case X86::KSET0Q: return Expand2AddrUndef(MIB, get(X86::KXORQrr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]4814 case X86::KSET1B:
4815 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
Elena Demikhovsky702a6ad2015-09-17 06:53:12 +0000[diff] [blame]4816 case X86::KSET1D: return Expand2AddrUndef(MIB, get(X86::KXNORDrr));
4817 case X86::KSET1Q: return Expand2AddrUndef(MIB, get(X86::KXNORQrr));
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]4818 case TargetOpcode::LOAD_STACK_GUARD:
4819 expandLoadStackGuard(MIB, *this);
4820 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]4821 }
4822 return false;
4823}
4824
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4825static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs) {
4826 unsigned NumAddrOps = MOs.size();
4827 for (unsigned i = 0; i != NumAddrOps; ++i)
4828 MIB.addOperand(MOs[i]);
4829 if (NumAddrOps < 4) // FrameIndex only
4830 addOffset(MIB, 0);
4831}
4832
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]4833static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]4834 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4835 MachineBasicBlock::iterator InsertPt,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4836 MachineInstr *MI,
4837 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4838 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4839 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4840 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4841 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4842 MachineInstrBuilder MIB(MF, NewMI);
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4843 addOperands(MIB, MOs);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4844
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4845 // Loop over the rest of the ri operands, converting them over.
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4846 unsigned NumOps = MI->getDesc().getNumOperands()-2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4847 for (unsigned i = 0; i != NumOps; ++i) {
4848 MachineOperand &MO = MI->getOperand(i+2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4849 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4850 }
4851 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
4852 MachineOperand &MO = MI->getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4853 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4854 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4855
4856 MachineBasicBlock *MBB = InsertPt->getParent();
4857 MBB->insert(InsertPt, NewMI);
4858
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4859 return MIB;
4860}
4861
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]4862static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
4863 unsigned OpNo, ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4864 MachineBasicBlock::iterator InsertPt,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4865 MachineInstr *MI, const TargetInstrInfo &TII) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4866 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]4867 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
4868 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]4869 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4870
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4871 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
4872 MachineOperand &MO = MI->getOperand(i);
4873 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4874 assert(MO.isReg() && "Expected to fold into reg operand!");
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4875 addOperands(MIB, MOs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4876 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4877 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4878 }
4879 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4880
4881 MachineBasicBlock *MBB = InsertPt->getParent();
4882 MBB->insert(InsertPt, NewMI);
4883
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4884 return MIB;
4885}
4886
4887static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]4888 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4889 MachineBasicBlock::iterator InsertPt,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4890 MachineInstr *MI) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4891 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
4892 MI->getDebugLoc(), TII.get(Opcode));
4893 addOperands(MIB, MOs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4894 return MIB.addImm(0);
4895}
4896
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4897MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
4898 MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
4899 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
4900 unsigned Size, unsigned Align, bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4901 const DenseMap<unsigned,
4902 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4903 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4904 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4905
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]4906 // For CPUs that favor the register form of a call or push,
4907 // do not fold loads into calls or pushes, unless optimizing for size
4908 // aggressively.
Sanjay Patel924879a2015-08-04 15:49:57 +0000[diff] [blame]4909 if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]4910 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r ||
4911 MI->getOpcode() == X86::PUSH16r || MI->getOpcode() == X86::PUSH32r ||
4912 MI->getOpcode() == X86::PUSH64r))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4913 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]4914
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]4915 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4916 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]4917 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4918
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4919 // FIXME: AsmPrinter doesn't know how to handle
4920 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
4921 if (MI->getOpcode() == X86::ADD32ri &&
4922 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4923 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]4924
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4925 MachineInstr *NewMI = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4926 // Folding a memory location into the two-address part of a two-address
4927 // instruction is different than folding it other places. It requires
4928 // replacing the *two* registers with the memory location.
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4929 if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]4930 MI->getOperand(0).isReg() &&
4931 MI->getOperand(1).isReg() &&
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4932 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4933 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
4934 isTwoAddrFold = true;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4935 } else if (OpNum == 0) {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4936 if (MI->getOpcode() == X86::MOV32r0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4937 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]4938 if (NewMI)
4939 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]4940 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4941
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4942 OpcodeTablePtr = &RegOp2MemOpTable0;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4943 } else if (OpNum == 1) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4944 OpcodeTablePtr = &RegOp2MemOpTable1;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4945 } else if (OpNum == 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4946 OpcodeTablePtr = &RegOp2MemOpTable2;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4947 } else if (OpNum == 3) {
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]4948 OpcodeTablePtr = &RegOp2MemOpTable3;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4949 } else if (OpNum == 4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]4950 OpcodeTablePtr = &RegOp2MemOpTable4;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4951 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4952
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4953 // If table selected...
4954 if (OpcodeTablePtr) {
4955 // Find the Opcode to fuse
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]4956 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
4957 OpcodeTablePtr->find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4958 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4959 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]4960 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]4961 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4962 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4963 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4964 if (Size) {
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]4965 unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4966 if (Size < RCSize) {
4967 // Check if it's safe to fold the load. If the size of the object is
4968 // narrower than the load width, then it's not.
4969 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4970 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4971 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4972 // a 32-bit load which is implicitly zero-extended. This likely is
4973 // due to live interval analysis remat'ing a load from stack slot.
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4974 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4975 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4976 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4977 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]4978 }
4979 }
4980
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4981 if (isTwoAddrFold)
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4982 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4983 else
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]4984 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4985
4986 if (NarrowToMOV32rm) {
4987 // If this is the special case where we use a MOV32rm to load a 32-bit
4988 // value and zero-extend the top bits. Change the destination register
4989 // to a 32-bit one.
4990 unsigned DstReg = NewMI->getOperand(0).getReg();
4991 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]4992 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4993 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]4994 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]4995 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]4996 return NewMI;
4997 }
4998 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4999
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5000 // If the instruction and target operand are commutable, commute the
5001 // instruction and try again.
5002 if (AllowCommute) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]5003 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5004 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5005 bool HasDef = MI->getDesc().getNumDefs();
5006 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
5007 unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
5008 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5009 bool Tied1 =
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]5010 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5011 bool Tied2 =
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5012 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5013
5014 // If either of the commutable operands are tied to the destination
5015 // then we can not commute + fold.
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]5016 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5017 (HasDef && Reg0 == Reg2 && Tied2))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5018 return nullptr;
5019
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]5020 MachineInstr *CommutedMI =
5021 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5022 if (!CommutedMI) {
5023 // Unable to commute.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5024 return nullptr;
5025 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame^]5026 if (CommutedMI != MI) {
5027 // New instruction. We can't fold from this.
5028 CommutedMI->eraseFromParent();
5029 return nullptr;
5030 }
5031
5032 // Attempt to fold with the commuted version of the instruction.
5033 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5034 Size, Align, /*AllowCommute=*/false);
5035 if (NewMI)
5036 return NewMI;
5037
5038 // Folding failed again - undo the commute before returning.
5039 MachineInstr *UncommutedMI =
5040 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5041 if (!UncommutedMI) {
5042 // Unable to commute.
5043 return nullptr;
5044 }
5045 if (UncommutedMI != MI) {
5046 // New instruction. It doesn't need to be kept.
5047 UncommutedMI->eraseFromParent();
5048 return nullptr;
5049 }
5050
5051 // Return here to prevent duplicate fuse failure report.
5052 return nullptr;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5053 }
5054 }
5055
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5056 // No fusion
Jakob Stoklund Olesen51702ec2010-07-09 20:43:09 +0000[diff] [blame]5057 if (PrintFailedFusing && !MI->isCopy())
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5058 dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5059 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5060}
5061
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5062/// Return true for all instructions that only update
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5063/// the first 32 or 64-bits of the destination register and leave the rest
5064/// unmodified. This can be used to avoid folding loads if the instructions
5065/// only update part of the destination register, and the non-updated part is
5066/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5067/// instructions breaks the partial register dependency and it can improve
5068/// performance. e.g.:
5069///
5070/// movss (%rdi), %xmm0
5071/// cvtss2sd %xmm0, %xmm0
5072///
5073/// Instead of
5074/// cvtss2sd (%rdi), %xmm0
5075///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]5076/// FIXME: This should be turned into a TSFlags.
5077///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5078static bool hasPartialRegUpdate(unsigned Opcode) {
5079 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5080 case X86::CVTSI2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5081 case X86::CVTSI2SSrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5082 case X86::CVTSI2SS64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5083 case X86::CVTSI2SS64rm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5084 case X86::CVTSI2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5085 case X86::CVTSI2SDrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5086 case X86::CVTSI2SD64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5087 case X86::CVTSI2SD64rm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5088 case X86::CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5089 case X86::CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5090 case X86::Int_CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5091 case X86::Int_CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5092 case X86::CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5093 case X86::CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5094 case X86::Int_CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5095 case X86::Int_CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5096 case X86::RCPSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5097 case X86::RCPSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5098 case X86::RCPSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5099 case X86::RCPSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5100 case X86::ROUNDSDr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5101 case X86::ROUNDSDm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]5102 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5103 case X86::ROUNDSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5104 case X86::ROUNDSSm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]5105 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5106 case X86::RSQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5107 case X86::RSQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5108 case X86::RSQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5109 case X86::RSQRTSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5110 case X86::SQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5111 case X86::SQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5112 case X86::SQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5113 case X86::SQRTSSm_Int:
5114 case X86::SQRTSDr:
5115 case X86::SQRTSDm:
5116 case X86::SQRTSDr_Int:
5117 case X86::SQRTSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5118 return true;
5119 }
5120
5121 return false;
5122}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5123
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5124/// Inform the ExeDepsFix pass how many idle
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5125/// instructions we would like before a partial register update.
5126unsigned X86InstrInfo::
5127getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
5128 const TargetRegisterInfo *TRI) const {
5129 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
5130 return 0;
5131
5132 // If MI is marked as reading Reg, the partial register update is wanted.
5133 const MachineOperand &MO = MI->getOperand(0);
5134 unsigned Reg = MO.getReg();
5135 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
5136 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
5137 return 0;
5138 } else {
5139 if (MI->readsRegister(Reg, TRI))
5140 return 0;
5141 }
5142
5143 // If any of the preceding 16 instructions are reading Reg, insert a
5144 // dependency breaking instruction. The magic number is based on a few
5145 // Nehalem experiments.
5146 return 16;
5147}
5148
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5149// Return true for any instruction the copies the high bits of the first source
5150// operand into the unused high bits of the destination operand.
5151static bool hasUndefRegUpdate(unsigned Opcode) {
5152 switch (Opcode) {
5153 case X86::VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5154 case X86::VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5155 case X86::Int_VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5156 case X86::Int_VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5157 case X86::VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5158 case X86::VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5159 case X86::Int_VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5160 case X86::Int_VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5161 case X86::VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5162 case X86::VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5163 case X86::Int_VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5164 case X86::Int_VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5165 case X86::VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5166 case X86::VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5167 case X86::Int_VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5168 case X86::Int_VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5169 case X86::VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5170 case X86::VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5171 case X86::Int_VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5172 case X86::Int_VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5173 case X86::VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5174 case X86::VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5175 case X86::Int_VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5176 case X86::Int_VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5177 case X86::VRCPSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5178 case X86::VRCPSSm:
5179 case X86::VRCPSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5180 case X86::VROUNDSDr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5181 case X86::VROUNDSDm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5182 case X86::VROUNDSDr_Int:
5183 case X86::VROUNDSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5184 case X86::VROUNDSSm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5185 case X86::VROUNDSSr_Int:
5186 case X86::VRSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5187 case X86::VRSQRTSSm:
5188 case X86::VRSQRTSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5189 case X86::VSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5190 case X86::VSQRTSSm:
5191 case X86::VSQRTSSm_Int:
5192 case X86::VSQRTSDr:
5193 case X86::VSQRTSDm:
5194 case X86::VSQRTSDm_Int:
5195 // AVX-512
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5196 case X86::VCVTSD2SSZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5197 case X86::VCVTSD2SSZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5198 case X86::VCVTSS2SDZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5199 case X86::VCVTSS2SDZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5200 return true;
5201 }
5202
5203 return false;
5204}
5205
5206/// Inform the ExeDepsFix pass how many idle instructions we would like before
5207/// certain undef register reads.
5208///
5209/// This catches the VCVTSI2SD family of instructions:
5210///
5211/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
5212///
5213/// We should to be careful *not* to catch VXOR idioms which are presumably
5214/// handled specially in the pipeline:
5215///
5216/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
5217///
5218/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5219/// high bits that are passed-through are not live.
5220unsigned X86InstrInfo::
5221getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
5222 const TargetRegisterInfo *TRI) const {
5223 if (!hasUndefRegUpdate(MI->getOpcode()))
5224 return 0;
5225
5226 // Set the OpNum parameter to the first source operand.
5227 OpNum = 1;
5228
5229 const MachineOperand &MO = MI->getOperand(OpNum);
5230 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
5231 // Use the same magic number as getPartialRegUpdateClearance.
5232 return 16;
5233 }
5234 return 0;
5235}
5236
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5237void X86InstrInfo::
5238breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
5239 const TargetRegisterInfo *TRI) const {
5240 unsigned Reg = MI->getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5241 // If MI kills this register, the false dependence is already broken.
5242 if (MI->killsRegister(Reg, TRI))
5243 return;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5244 if (X86::VR128RegClass.contains(Reg)) {
5245 // These instructions are all floating point domain, so xorps is the best
5246 // choice.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5247 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5248 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
5249 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
5250 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5251 } else if (X86::VR256RegClass.contains(Reg)) {
5252 // Use vxorps to clear the full ymm register.
5253 // It wants to read and write the xmm sub-register.
5254 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5255 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
5256 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
5257 .addReg(Reg, RegState::ImplicitDefine);
5258 } else
5259 return;
5260 MI->addRegisterKilled(Reg, TRI, true);
5261}
5262
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5263MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5264 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
5265 MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5266 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5267 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5268
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5269 // Unless optimizing for size, don't fold to avoid partial
5270 // register update stalls
Sanjay Patel10294b52015-08-10 17:15:17 +0000[diff] [blame]5271 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5272 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]5273
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]5274 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5275 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]5276 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]5277 // If the function stack isn't realigned we don't want to fold instructions
5278 // that need increased alignment.
5279 if (!RI.needsStackRealignment(MF))
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]5280 Alignment =
5281 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5282 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5283 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5284 unsigned RCSize = 0;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5285 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5286 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5287 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]5288 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5289 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5290 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5291 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5292 // Check if it's safe to fold the load. If the size of the object is
5293 // narrower than the load width, then it's not.
5294 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5295 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5296 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]5297 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5298 MI->getOperand(1).ChangeToImmediate(0);
5299 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5300 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5301
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5302 return foldMemoryOperandImpl(MF, MI, Ops[0],
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5303 MachineOperand::CreateFI(FrameIndex), InsertPt,
5304 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5305}
5306
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5307/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5308/// because the latter uses contents that wouldn't be defined in the folded
5309/// version. For instance, this transformation isn't legal:
5310/// movss (%rdi), %xmm0
5311/// addps %xmm0, %xmm0
5312/// ->
5313/// addps (%rdi), %xmm0
5314///
5315/// But this one is:
5316/// movss (%rdi), %xmm0
5317/// addss %xmm0, %xmm0
5318/// ->
5319/// addss (%rdi), %xmm0
5320///
5321static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5322 const MachineInstr &UserMI,
5323 const MachineFunction &MF) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5324 unsigned Opc = LoadMI.getOpcode();
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5325 unsigned UserOpc = UserMI.getOpcode();
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5326 unsigned RegSize =
5327 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
5328
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5329 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5330 // These instructions only load 32 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5331 // destination register is wider than 32 bits (4 bytes), and its user
5332 // instruction isn't scalar (SS).
5333 switch (UserOpc) {
5334 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
5335 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
5336 case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
5337 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
5338 return false;
5339 default:
5340 return true;
5341 }
5342 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5343
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5344 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5345 // These instructions only load 64 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5346 // destination register is wider than 64 bits (8 bytes), and its user
5347 // instruction isn't scalar (SD).
5348 switch (UserOpc) {
5349 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
5350 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
5351 case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
5352 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
5353 return false;
5354 default:
5355 return true;
5356 }
5357 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5358
5359 return false;
5360}
5361
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5362MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5363 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
5364 MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]5365 // If loading from a FrameIndex, fold directly from the FrameIndex.
5366 unsigned NumOps = LoadMI->getDesc().getNumOperands();
5367 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5368 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5369 if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5370 return nullptr;
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5371 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5372 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]5373
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5374 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5375 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5376
Sanjay Pateld09391c2015-08-10 20:45:44 +0000[diff] [blame]5377 // Avoid partial register update stalls unless optimizing for size.
5378 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5379 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]5380
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]5381 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]5382 unsigned Alignment = 0;
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]5383 if (LoadMI->hasOneMemOperand())
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]5384 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5385 else
5386 switch (LoadMI->getOpcode()) {
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]5387 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5388 case X86::AVX_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5389 Alignment = 32;
5390 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5391 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5392 case X86::V_SETALLONES:
5393 Alignment = 16;
5394 break;
5395 case X86::FsFLD0SD:
5396 Alignment = 8;
5397 break;
5398 case X86::FsFLD0SS:
5399 Alignment = 4;
5400 break;
5401 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5402 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5403 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5404 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5405 unsigned NewOpc = 0;
5406 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5407 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5408 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5409 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
5410 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
5411 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5412 }
5413 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]5414 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5415 MI->getOperand(1).ChangeToImmediate(0);
5416 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5417 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5418
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]5419 // Make sure the subregisters match.
5420 // Otherwise we risk changing the size of the load.
5421 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5422 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]5423
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5424 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5425 switch (LoadMI->getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5426 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5427 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]5428 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5429 case X86::AVX_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5430 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5431 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5432 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5433 // Create a constant-pool entry and operands to load from it.
5434
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]5435 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5436 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
5437 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5438 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]5439
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5440 // x86-32 PIC requires a PIC base register for constant pools.
5441 unsigned PICBase = 0;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5442 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
5443 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]5444 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]5445 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]5446 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]5447 // This doesn't work for several reasons.
5448 // 1. GlobalBaseReg may have been spilled.
5449 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5450 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]5451 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5452
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5453 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5454 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]5455 Type *Ty;
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]5456 unsigned Opc = LoadMI->getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5457 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5458 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5459 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5460 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5461 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]5462 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5463 else
5464 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]5465
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5466 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]5467 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
5468 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5469 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5470
5471 // Create operands to load from the constant pool entry.
5472 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
5473 MOs.push_back(MachineOperand::CreateImm(1));
5474 MOs.push_back(MachineOperand::CreateReg(0, false));
5475 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]5476 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5477 break;
5478 }
5479 default: {
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5480 if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5481 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]5482
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5483 // Folding a normal load. Just copy the load's address operands.
Benjamin Kramer5fbfe2f2015-02-28 13:20:15 +0000[diff] [blame]5484 MOs.append(LoadMI->operands_begin() + NumOps - X86::AddrNumOperands,
5485 LoadMI->operands_begin() + NumOps);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]5486 break;
5487 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]5488 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5489 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5490 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5491}
5492
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5493bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
5494 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]5495 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5496 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5497 MemOp2RegOpTable.find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5498 if (I == MemOp2RegOpTable.end())
5499 return false;
5500 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5501 unsigned Index = I->second.second & TB_INDEX_MASK;
5502 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5503 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5504 if (UnfoldLoad && !FoldedLoad)
5505 return false;
5506 UnfoldLoad &= FoldedLoad;
5507 if (UnfoldStore && !FoldedStore)
5508 return false;
5509 UnfoldStore &= FoldedStore;
5510
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5511 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5512 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]5513 // TODO: Check if 32-byte or greater accesses are slow too?
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5514 if (!MI->hasOneMemOperand() &&
5515 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]5516 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5517 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
5518 // conservatively assume the address is unaligned. That's bad for
5519 // performance.
5520 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5521 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5522 SmallVector<MachineOperand,2> BeforeOps;
5523 SmallVector<MachineOperand,2> AfterOps;
5524 SmallVector<MachineOperand,4> ImpOps;
5525 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5526 MachineOperand &Op = MI->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5527 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5528 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5529 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5530 ImpOps.push_back(Op);
5531 else if (i < Index)
5532 BeforeOps.push_back(Op);
5533 else if (i > Index)
5534 AfterOps.push_back(Op);
5535 }
5536
5537 // Emit the load instruction.
5538 if (UnfoldLoad) {
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5539 std::pair<MachineInstr::mmo_iterator,
5540 MachineInstr::mmo_iterator> MMOs =
5541 MF.extractLoadMemRefs(MI->memoperands_begin(),
5542 MI->memoperands_end());
5543 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5544 if (UnfoldStore) {
5545 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5546 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5547 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5548 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5549 MO.setIsKill(false);
5550 }
5551 }
5552 }
5553
5554 // Emit the data processing instruction.
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5555 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5556 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5557
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5558 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]5559 MIB.addReg(Reg, RegState::Define);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5560 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5561 MIB.addOperand(BeforeOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5562 if (FoldedLoad)
5563 MIB.addReg(Reg);
5564 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5565 MIB.addOperand(AfterOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5566 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
5567 MachineOperand &MO = ImpOps[i];
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]5568 MIB.addReg(MO.getReg(),
5569 getDefRegState(MO.isDef()) |
5570 RegState::Implicit |
5571 getKillRegState(MO.isKill()) |
Evan Cheng0dc101b2009-06-30 08:49:04 +0000[diff] [blame]5572 getDeadRegState(MO.isDead()) |
5573 getUndefRegState(MO.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5574 }
5575 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5576 switch (DataMI->getOpcode()) {
5577 default: break;
5578 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5579 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5580 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5581 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5582 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5583 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5584 case X86::CMP8ri: {
5585 MachineOperand &MO0 = DataMI->getOperand(0);
5586 MachineOperand &MO1 = DataMI->getOperand(1);
5587 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5588 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5589 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5590 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5591 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5592 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5593 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5594 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]5595 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5596 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
5597 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
5598 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]5599 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5600 MO1.ChangeToRegister(MO0.getReg(), false);
5601 }
5602 }
5603 }
5604 NewMIs.push_back(DataMI);
5605
5606 // Emit the store instruction.
5607 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5608 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5609 std::pair<MachineInstr::mmo_iterator,
5610 MachineInstr::mmo_iterator> MMOs =
5611 MF.extractStoreMemRefs(MI->memoperands_begin(),
5612 MI->memoperands_end());
5613 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5614 }
5615
5616 return true;
5617}
5618
5619bool
5620X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]5621 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]5622 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5623 return false;
5624
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5625 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5626 MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5627 if (I == MemOp2RegOpTable.end())
5628 return false;
5629 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5630 unsigned Index = I->second.second & TB_INDEX_MASK;
5631 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5632 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5633 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5634 MachineFunction &MF = DAG.getMachineFunction();
5635 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5636 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5637 std::vector<SDValue> AddrOps;
5638 std::vector<SDValue> BeforeOps;
5639 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]5640 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5641 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]5642 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5643 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]5644 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5645 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]5646 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5647 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]5648 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5649 AfterOps.push_back(Op);
5650 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5651 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5652 AddrOps.push_back(Chain);
5653
5654 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5655 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5656 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]5657 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]5658 std::pair<MachineInstr::mmo_iterator,
5659 MachineInstr::mmo_iterator> MMOs =
5660 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5661 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5662 if (!(*MMOs.first) &&
5663 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]5664 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5665 // Do not introduce a slow unaligned load.
5666 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]5667 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5668 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5669 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5670 bool isAligned = (*MMOs.first) &&
5671 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5672 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]5673 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5674 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5675
5676 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5677 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5678 }
5679
5680 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]5681 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5682 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5683 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]5684 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5685 VTs.push_back(*DstRC->vt_begin());
5686 }
5687 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]5688 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5689 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5690 VTs.push_back(VT);
5691 }
5692 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5693 BeforeOps.push_back(SDValue(Load, 0));
Benjamin Kramer4f6ac162015-02-28 10:11:12 +0000[diff] [blame]5694 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]5695 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5696 NewNodes.push_back(NewNode);
5697
5698 // Emit the store instruction.
5699 if (FoldedStore) {
5700 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]5701 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5702 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]5703 std::pair<MachineInstr::mmo_iterator,
5704 MachineInstr::mmo_iterator> MMOs =
5705 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
5706 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5707 if (!(*MMOs.first) &&
5708 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]5709 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]5710 // Do not introduce a slow unaligned store.
5711 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]5712 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
5713 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5714 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
5715 bool isAligned = (*MMOs.first) &&
5716 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5717 SDNode *Store =
5718 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
5719 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5720 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]5721
5722 // Preserve memory reference information.
Craig Topper9e71b822015-02-10 06:29:28 +0000[diff] [blame]5723 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5724 }
5725
5726 return true;
5727}
5728
5729unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]5730 bool UnfoldLoad, bool UnfoldStore,
5731 unsigned *LoadRegIndex) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5732 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5733 MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5734 if (I == MemOp2RegOpTable.end())
5735 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5736 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
5737 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5738 if (UnfoldLoad && !FoldedLoad)
5739 return 0;
5740 if (UnfoldStore && !FoldedStore)
5741 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]5742 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5743 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5744 return I->second.first;
5745}
5746
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5747bool
5748X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
5749 int64_t &Offset1, int64_t &Offset2) const {
5750 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
5751 return false;
5752 unsigned Opc1 = Load1->getMachineOpcode();
5753 unsigned Opc2 = Load2->getMachineOpcode();
5754 switch (Opc1) {
5755 default: return false;
5756 case X86::MOV8rm:
5757 case X86::MOV16rm:
5758 case X86::MOV32rm:
5759 case X86::MOV64rm:
5760 case X86::LD_Fp32m:
5761 case X86::LD_Fp64m:
5762 case X86::LD_Fp80m:
5763 case X86::MOVSSrm:
5764 case X86::MOVSDrm:
5765 case X86::MMX_MOVD64rm:
5766 case X86::MMX_MOVQ64rm:
5767 case X86::FsMOVAPSrm:
5768 case X86::FsMOVAPDrm:
5769 case X86::MOVAPSrm:
5770 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5771 case X86::MOVAPDrm:
5772 case X86::MOVDQArm:
5773 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5774 // AVX load instructions
5775 case X86::VMOVSSrm:
5776 case X86::VMOVSDrm:
5777 case X86::FsVMOVAPSrm:
5778 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5779 case X86::VMOVAPSrm:
5780 case X86::VMOVUPSrm:
5781 case X86::VMOVAPDrm:
5782 case X86::VMOVDQArm:
5783 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5784 case X86::VMOVAPSYrm:
5785 case X86::VMOVUPSYrm:
5786 case X86::VMOVAPDYrm:
5787 case X86::VMOVDQAYrm:
5788 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5789 break;
5790 }
5791 switch (Opc2) {
5792 default: return false;
5793 case X86::MOV8rm:
5794 case X86::MOV16rm:
5795 case X86::MOV32rm:
5796 case X86::MOV64rm:
5797 case X86::LD_Fp32m:
5798 case X86::LD_Fp64m:
5799 case X86::LD_Fp80m:
5800 case X86::MOVSSrm:
5801 case X86::MOVSDrm:
5802 case X86::MMX_MOVD64rm:
5803 case X86::MMX_MOVQ64rm:
5804 case X86::FsMOVAPSrm:
5805 case X86::FsMOVAPDrm:
5806 case X86::MOVAPSrm:
5807 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5808 case X86::MOVAPDrm:
5809 case X86::MOVDQArm:
5810 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]5811 // AVX load instructions
5812 case X86::VMOVSSrm:
5813 case X86::VMOVSDrm:
5814 case X86::FsVMOVAPSrm:
5815 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]5816 case X86::VMOVAPSrm:
5817 case X86::VMOVUPSrm:
5818 case X86::VMOVAPDrm:
5819 case X86::VMOVDQArm:
5820 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]5821 case X86::VMOVAPSYrm:
5822 case X86::VMOVUPSYrm:
5823 case X86::VMOVAPDYrm:
5824 case X86::VMOVDQAYrm:
5825 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5826 break;
5827 }
5828
5829 // Check if chain operands and base addresses match.
5830 if (Load1->getOperand(0) != Load2->getOperand(0) ||
5831 Load1->getOperand(5) != Load2->getOperand(5))
5832 return false;
5833 // Segment operands should match as well.
5834 if (Load1->getOperand(4) != Load2->getOperand(4))
5835 return false;
5836 // Scale should be 1, Index should be Reg0.
5837 if (Load1->getOperand(1) == Load2->getOperand(1) &&
5838 Load1->getOperand(2) == Load2->getOperand(2)) {
5839 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
5840 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5841
5842 // Now let's examine the displacements.
5843 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
5844 isa<ConstantSDNode>(Load2->getOperand(3))) {
5845 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
5846 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
5847 return true;
5848 }
5849 }
5850 return false;
5851}
5852
5853bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
5854 int64_t Offset1, int64_t Offset2,
5855 unsigned NumLoads) const {
5856 assert(Offset2 > Offset1);
5857 if ((Offset2 - Offset1) / 8 > 64)
5858 return false;
5859
5860 unsigned Opc1 = Load1->getMachineOpcode();
5861 unsigned Opc2 = Load2->getMachineOpcode();
5862 if (Opc1 != Opc2)
5863 return false; // FIXME: overly conservative?
5864
5865 switch (Opc1) {
5866 default: break;
5867 case X86::LD_Fp32m:
5868 case X86::LD_Fp64m:
5869 case X86::LD_Fp80m:
5870 case X86::MMX_MOVD64rm:
5871 case X86::MMX_MOVQ64rm:
5872 return false;
5873 }
5874
5875 EVT VT = Load1->getValueType(0);
5876 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5877 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5878 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
5879 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5880 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5881 if (NumLoads >= 3)
5882 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5883 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5884 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5885 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5886 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5887 case MVT::i8:
5888 case MVT::i16:
5889 case MVT::i32:
5890 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]5891 case MVT::f32:
5892 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5893 if (NumLoads)
5894 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]5895 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]5896 }
5897
5898 return true;
5899}
5900
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5901bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
5902 MachineInstr *Second) const {
5903 // Check if this processor supports macro-fusion. Since this is a minor
5904 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
5905 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5906 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5907 return false;
5908
5909 enum {
5910 FuseTest,
5911 FuseCmp,
5912 FuseInc
5913 } FuseKind;
5914
5915 switch(Second->getOpcode()) {
5916 default:
5917 return false;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5918 case X86::JE_1:
5919 case X86::JNE_1:
5920 case X86::JL_1:
5921 case X86::JLE_1:
5922 case X86::JG_1:
5923 case X86::JGE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5924 FuseKind = FuseInc;
5925 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5926 case X86::JB_1:
5927 case X86::JBE_1:
5928 case X86::JA_1:
5929 case X86::JAE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5930 FuseKind = FuseCmp;
5931 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]5932 case X86::JS_1:
5933 case X86::JNS_1:
5934 case X86::JP_1:
5935 case X86::JNP_1:
5936 case X86::JO_1:
5937 case X86::JNO_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5938 FuseKind = FuseTest;
5939 break;
5940 }
5941 switch (First->getOpcode()) {
5942 default:
5943 return false;
5944 case X86::TEST8rr:
5945 case X86::TEST16rr:
5946 case X86::TEST32rr:
5947 case X86::TEST64rr:
5948 case X86::TEST8ri:
5949 case X86::TEST16ri:
5950 case X86::TEST32ri:
5951 case X86::TEST32i32:
5952 case X86::TEST64i32:
5953 case X86::TEST64ri32:
5954 case X86::TEST8rm:
5955 case X86::TEST16rm:
5956 case X86::TEST32rm:
5957 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]5958 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]5959 case X86::AND16i16:
5960 case X86::AND16ri:
5961 case X86::AND16ri8:
5962 case X86::AND16rm:
5963 case X86::AND16rr:
5964 case X86::AND32i32:
5965 case X86::AND32ri:
5966 case X86::AND32ri8:
5967 case X86::AND32rm:
5968 case X86::AND32rr:
5969 case X86::AND64i32:
5970 case X86::AND64ri32:
5971 case X86::AND64ri8:
5972 case X86::AND64rm:
5973 case X86::AND64rr:
5974 case X86::AND8i8:
5975 case X86::AND8ri:
5976 case X86::AND8rm:
5977 case X86::AND8rr:
5978 return true;
5979 case X86::CMP16i16:
5980 case X86::CMP16ri:
5981 case X86::CMP16ri8:
5982 case X86::CMP16rm:
5983 case X86::CMP16rr:
5984 case X86::CMP32i32:
5985 case X86::CMP32ri:
5986 case X86::CMP32ri8:
5987 case X86::CMP32rm:
5988 case X86::CMP32rr:
5989 case X86::CMP64i32:
5990 case X86::CMP64ri32:
5991 case X86::CMP64ri8:
5992 case X86::CMP64rm:
5993 case X86::CMP64rr:
5994 case X86::CMP8i8:
5995 case X86::CMP8ri:
5996 case X86::CMP8rm:
5997 case X86::CMP8rr:
5998 case X86::ADD16i16:
5999 case X86::ADD16ri:
6000 case X86::ADD16ri8:
6001 case X86::ADD16ri8_DB:
6002 case X86::ADD16ri_DB:
6003 case X86::ADD16rm:
6004 case X86::ADD16rr:
6005 case X86::ADD16rr_DB:
6006 case X86::ADD32i32:
6007 case X86::ADD32ri:
6008 case X86::ADD32ri8:
6009 case X86::ADD32ri8_DB:
6010 case X86::ADD32ri_DB:
6011 case X86::ADD32rm:
6012 case X86::ADD32rr:
6013 case X86::ADD32rr_DB:
6014 case X86::ADD64i32:
6015 case X86::ADD64ri32:
6016 case X86::ADD64ri32_DB:
6017 case X86::ADD64ri8:
6018 case X86::ADD64ri8_DB:
6019 case X86::ADD64rm:
6020 case X86::ADD64rr:
6021 case X86::ADD64rr_DB:
6022 case X86::ADD8i8:
6023 case X86::ADD8mi:
6024 case X86::ADD8mr:
6025 case X86::ADD8ri:
6026 case X86::ADD8rm:
6027 case X86::ADD8rr:
6028 case X86::SUB16i16:
6029 case X86::SUB16ri:
6030 case X86::SUB16ri8:
6031 case X86::SUB16rm:
6032 case X86::SUB16rr:
6033 case X86::SUB32i32:
6034 case X86::SUB32ri:
6035 case X86::SUB32ri8:
6036 case X86::SUB32rm:
6037 case X86::SUB32rr:
6038 case X86::SUB64i32:
6039 case X86::SUB64ri32:
6040 case X86::SUB64ri8:
6041 case X86::SUB64rm:
6042 case X86::SUB64rr:
6043 case X86::SUB8i8:
6044 case X86::SUB8ri:
6045 case X86::SUB8rm:
6046 case X86::SUB8rr:
6047 return FuseKind == FuseCmp || FuseKind == FuseInc;
6048 case X86::INC16r:
6049 case X86::INC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6050 case X86::INC64r:
6051 case X86::INC8r:
6052 case X86::DEC16r:
6053 case X86::DEC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6054 case X86::DEC64r:
6055 case X86::DEC8r:
6056 return FuseKind == FuseInc;
6057 }
6058}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6059
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]6060bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]6061ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]6062 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]6063 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]6064 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
6065 return true;
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]6066 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]6067 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]6068}
6069
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]6070bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]6071isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6072 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]6073 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]6074 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6075 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]6076}
6077
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6078/// Return a virtual register initialized with the
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6079/// the global base register value. Output instructions required to
6080/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]6081///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6082/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6083///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6084unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6085 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6086 "X86-64 PIC uses RIP relative addressing");
6087
6088 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6089 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6090 if (GlobalBaseReg != 0)
6091 return GlobalBaseReg;
6092
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6093 // Create the register. The code to initialize it is inserted
6094 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]6095 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]6096 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6097 X86FI->setGlobalBaseReg(GlobalBaseReg);
6098 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]6099}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6100
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6101// These are the replaceable SSE instructions. Some of these have Int variants
6102// that we don't include here. We don't want to replace instructions selected
6103// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6104static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]6105 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]6106 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
6107 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
6108 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
6109 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
6110 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
Sanjay Patelc03d93b2015-04-15 15:47:51 +0000[diff] [blame]6111 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]6112 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
6113 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
6114 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
6115 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
6116 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
6117 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
6118 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
6119 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
6120 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6121 // AVX 128-bit support
6122 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
6123 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
6124 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
6125 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
6126 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
Sanjay Patel2161c492015-04-17 17:02:37 +0000[diff] [blame]6127 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6128 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6129 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
6130 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
6131 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
6132 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
6133 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
6134 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6135 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
6136 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6137 // AVX 256-bit support
6138 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
6139 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
6140 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
6141 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
6142 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]6143 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
6144};
6145
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6146static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]6147 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]6148 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
6149 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
6150 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
6151 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
6152 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
6153 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
6154 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]6155 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
6156 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6157 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6158 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
6159 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
6160 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]6161 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
6162 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6163 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6164 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6165 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6166 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6167 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6168};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6169
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6170// FIXME: Some shuffle and unpack instructions have equivalents in different
6171// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6172
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6173static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6174 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6175 if (ReplaceableInstrs[i][domain-1] == opcode)
6176 return ReplaceableInstrs[i];
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6177 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]6178}
6179
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6180static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]6181 for (unsigned i = 0, e = array_lengthof(ReplaceableInstrsAVX2); i != e; ++i)
6182 if (ReplaceableInstrsAVX2[i][domain-1] == opcode)
6183 return ReplaceableInstrsAVX2[i];
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6184 return nullptr;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6185}
6186
6187std::pair<uint16_t, uint16_t>
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]6188X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6189 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6190 bool hasAVX2 = Subtarget.hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]6191 uint16_t validDomains = 0;
6192 if (domain && lookup(MI->getOpcode(), domain))
6193 validDomains = 0xe;
6194 else if (domain && lookupAVX2(MI->getOpcode(), domain))
6195 validDomains = hasAVX2 ? 0xe : 0x6;
6196 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6197}
6198
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]6199void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6200 assert(Domain>0 && Domain<4 && "Invalid execution domain");
6201 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6202 assert(dom && "Not an SSE instruction");
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6203 const uint16_t *table = lookup(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]6204 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6205 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]6206 "256-bit vector operations only available in AVX2");
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]6207 table = lookupAVX2(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]6208 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6209 assert(table && "Cannot change domain");
6210 MI->setDesc(get(table[Domain-1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6211}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]6212
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6213/// Return the noop instruction to use for a noop.
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]6214void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
6215 NopInst.setOpcode(X86::NOOP);
6216}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6217
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]6218// This code must remain in sync with getJumpInstrTableEntryBound in this class!
6219// In particular, getJumpInstrTableEntryBound must always return an upper bound
6220// on the encoding lengths of the instructions generated by
6221// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]6222void X86InstrInfo::getUnconditionalBranch(
6223 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6224 Branch.setOpcode(X86::JMP_1);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]6225 Branch.addOperand(MCOperand::createExpr(BranchTarget));
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]6226}
6227
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]6228// This code must remain in sync with getJumpInstrTableEntryBound in this class!
6229// In particular, getJumpInstrTableEntryBound must always return an upper bound
6230// on the encoding lengths of the instructions generated by
6231// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]6232void X86InstrInfo::getTrap(MCInst &MI) const {
6233 MI.setOpcode(X86::TRAP);
6234}
6235
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]6236// See getTrap and getUnconditionalBranch for conditions on the value returned
6237// by this function.
6238unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
6239 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
6240 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
6241 return 5;
6242}
6243
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]6244bool X86InstrInfo::isHighLatencyDef(int opc) const {
6245 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6246 default: return false;
6247 case X86::DIVSDrm:
6248 case X86::DIVSDrm_Int:
6249 case X86::DIVSDrr:
6250 case X86::DIVSDrr_Int:
6251 case X86::DIVSSrm:
6252 case X86::DIVSSrm_Int:
6253 case X86::DIVSSrr:
6254 case X86::DIVSSrr_Int:
6255 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6256 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6257 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6258 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6259 case X86::SQRTSDm:
6260 case X86::SQRTSDm_Int:
6261 case X86::SQRTSDr:
6262 case X86::SQRTSDr_Int:
6263 case X86::SQRTSSm:
6264 case X86::SQRTSSm_Int:
6265 case X86::SQRTSSr:
6266 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6267 // AVX instructions with high latency
6268 case X86::VDIVSDrm:
6269 case X86::VDIVSDrm_Int:
6270 case X86::VDIVSDrr:
6271 case X86::VDIVSDrr_Int:
6272 case X86::VDIVSSrm:
6273 case X86::VDIVSSrm_Int:
6274 case X86::VDIVSSrr:
6275 case X86::VDIVSSrr_Int:
6276 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6277 case X86::VSQRTPDr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6278 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6279 case X86::VSQRTPSr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6280 case X86::VSQRTSDm:
6281 case X86::VSQRTSDm_Int:
6282 case X86::VSQRTSDr:
6283 case X86::VSQRTSSm:
6284 case X86::VSQRTSSm_Int:
6285 case X86::VSQRTSSr:
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]6286 case X86::VSQRTPDZm:
6287 case X86::VSQRTPDZr:
6288 case X86::VSQRTPSZm:
6289 case X86::VSQRTPSZr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]6290 case X86::VSQRTSDZm:
6291 case X86::VSQRTSDZm_Int:
6292 case X86::VSQRTSDZr:
6293 case X86::VSQRTSSZm_Int:
6294 case X86::VSQRTSSZr:
6295 case X86::VSQRTSSZm:
6296 case X86::VDIVSDZrm:
6297 case X86::VDIVSDZrr:
6298 case X86::VDIVSSZrm:
6299 case X86::VDIVSSZrr:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]6300
6301 case X86::VGATHERQPSZrm:
6302 case X86::VGATHERQPDZrm:
6303 case X86::VGATHERDPDZrm:
6304 case X86::VGATHERDPSZrm:
6305 case X86::VPGATHERQDZrm:
6306 case X86::VPGATHERQQZrm:
6307 case X86::VPGATHERDDZrm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]6308 case X86::VPGATHERDQZrm:
6309 case X86::VSCATTERQPDZmr:
6310 case X86::VSCATTERQPSZmr:
6311 case X86::VSCATTERDPDZmr:
6312 case X86::VSCATTERDPSZmr:
6313 case X86::VPSCATTERQDZmr:
6314 case X86::VPSCATTERQQZmr:
6315 case X86::VPSCATTERDDZmr:
6316 case X86::VPSCATTERDQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6317 return true;
6318 }
6319}
6320
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]6321bool X86InstrInfo::
Matthias Braun88e21312015-06-13 03:42:11 +0000[diff] [blame]6322hasHighOperandLatency(const TargetSchedModel &SchedModel,
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]6323 const MachineRegisterInfo *MRI,
6324 const MachineInstr *DefMI, unsigned DefIdx,
6325 const MachineInstr *UseMI, unsigned UseIdx) const {
6326 return isHighLatencyDef(DefMI->getOpcode());
6327}
6328
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]6329bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
6330 const MachineBasicBlock *MBB) const {
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]6331 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
6332 "Reassociation needs binary operators");
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]6333
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]6334 // Integer binary math/logic instructions have a third source operand:
6335 // the EFLAGS register. That operand must be both defined here and never
6336 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
6337 // not change anything because rearranging the operands could affect other
6338 // instructions that depend on the exact status flags (zero, sign, etc.)
6339 // that are set by using these particular operands with this operation.
6340 if (Inst.getNumOperands() == 4) {
6341 assert(Inst.getOperand(3).isReg() &&
6342 Inst.getOperand(3).getReg() == X86::EFLAGS &&
6343 "Unexpected operand in reassociable instruction");
6344 if (!Inst.getOperand(3).isDead())
6345 return false;
6346 }
Sanjay Patele79b43a2015-06-23 00:39:40 +0000[diff] [blame]6347
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]6348 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]6349}
6350
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]6351// TODO: There are many more machine instruction opcodes to match:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]6352// 1. Other data types (integer, vectors)
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]6353// 2. Other math / logic operations (xor, or)
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]6354// 3. Other forms of the same operation (intrinsics and other variants)
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]6355bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]6356 switch (Inst.getOpcode()) {
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]6357 case X86::AND8rr:
6358 case X86::AND16rr:
6359 case X86::AND32rr:
6360 case X86::AND64rr:
Sanjay Pateld9a5c222015-08-31 20:27:03 +0000[diff] [blame]6361 case X86::OR8rr:
6362 case X86::OR16rr:
6363 case X86::OR32rr:
6364 case X86::OR64rr:
Sanjay Patelc9ae9d72015-09-03 16:36:16 +0000[diff] [blame]6365 case X86::XOR8rr:
6366 case X86::XOR16rr:
6367 case X86::XOR32rr:
6368 case X86::XOR64rr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]6369 case X86::IMUL16rr:
6370 case X86::IMUL32rr:
6371 case X86::IMUL64rr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]6372 case X86::PANDrr:
6373 case X86::PORrr:
6374 case X86::PXORrr:
6375 case X86::VPANDrr:
6376 case X86::VPORrr:
6377 case X86::VPXORrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]6378 // Normal min/max instructions are not commutative because of NaN and signed
6379 // zero semantics, but these are. Thus, there's no need to check for global
6380 // relaxed math; the instructions themselves have the properties we need.
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]6381 case X86::MAXCPDrr:
6382 case X86::MAXCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]6383 case X86::MAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]6384 case X86::MAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]6385 case X86::MINCPDrr:
6386 case X86::MINCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]6387 case X86::MINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]6388 case X86::MINCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]6389 case X86::VMAXCPDrr:
6390 case X86::VMAXCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]6391 case X86::VMAXCPDYrr:
6392 case X86::VMAXCPSYrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]6393 case X86::VMAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]6394 case X86::VMAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]6395 case X86::VMINCPDrr:
6396 case X86::VMINCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]6397 case X86::VMINCPDYrr:
6398 case X86::VMINCPSYrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]6399 case X86::VMINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]6400 case X86::VMINCSSrr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]6401 return true;
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]6402 case X86::ADDPDrr:
6403 case X86::ADDPSrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]6404 case X86::ADDSDrr:
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]6405 case X86::ADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]6406 case X86::MULPDrr:
6407 case X86::MULPSrr:
6408 case X86::MULSDrr:
6409 case X86::MULSSrr:
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]6410 case X86::VADDPDrr:
6411 case X86::VADDPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]6412 case X86::VADDPDYrr:
6413 case X86::VADDPSYrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]6414 case X86::VADDSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]6415 case X86::VADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]6416 case X86::VMULPDrr:
6417 case X86::VMULPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]6418 case X86::VMULPDYrr:
6419 case X86::VMULPSYrr:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]6420 case X86::VMULSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]6421 case X86::VMULSSrr:
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]6422 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]6423 default:
6424 return false;
6425 }
6426}
6427
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]6428/// This is an architecture-specific helper function of reassociateOps.
6429/// Set special operand attributes for new instructions after reassociation.
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]6430void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
6431 MachineInstr &OldMI2,
6432 MachineInstr &NewMI1,
6433 MachineInstr &NewMI2) const {
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]6434 // Integer instructions define an implicit EFLAGS source register operand as
6435 // the third source (fourth total) operand.
6436 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
6437 return;
6438
6439 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
6440 "Unexpected instruction type for reassociation");
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]6441
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]6442 MachineOperand &OldOp1 = OldMI1.getOperand(3);
6443 MachineOperand &OldOp2 = OldMI2.getOperand(3);
6444 MachineOperand &NewOp1 = NewMI1.getOperand(3);
6445 MachineOperand &NewOp2 = NewMI2.getOperand(3);
6446
6447 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
6448 "Must have dead EFLAGS operand in reassociable instruction");
6449 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
6450 "Must have dead EFLAGS operand in reassociable instruction");
6451
6452 (void)OldOp1;
6453 (void)OldOp2;
6454
6455 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
6456 "Unexpected operand in reassociable instruction");
6457 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
6458 "Unexpected operand in reassociable instruction");
6459
6460 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
6461 // of this pass or other passes. The EFLAGS operands must be dead in these new
6462 // instructions because the EFLAGS operands in the original instructions must
6463 // be dead in order for reassociation to occur.
6464 NewOp1.setIsDead();
6465 NewOp2.setIsDead();
6466}
6467
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]6468std::pair<unsigned, unsigned>
6469X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
6470 return std::make_pair(TF, 0u);
6471}
6472
6473ArrayRef<std::pair<unsigned, const char *>>
6474X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
6475 using namespace X86II;
Hal Finkel982e8d42015-08-30 08:07:29 +0000[diff] [blame]6476 static const std::pair<unsigned, const char *> TargetFlags[] = {
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]6477 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
6478 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
6479 {MO_GOT, "x86-got"},
6480 {MO_GOTOFF, "x86-gotoff"},
6481 {MO_GOTPCREL, "x86-gotpcrel"},
6482 {MO_PLT, "x86-plt"},
6483 {MO_TLSGD, "x86-tlsgd"},
6484 {MO_TLSLD, "x86-tlsld"},
6485 {MO_TLSLDM, "x86-tlsldm"},
6486 {MO_GOTTPOFF, "x86-gottpoff"},
6487 {MO_INDNTPOFF, "x86-indntpoff"},
6488 {MO_TPOFF, "x86-tpoff"},
6489 {MO_DTPOFF, "x86-dtpoff"},
6490 {MO_NTPOFF, "x86-ntpoff"},
6491 {MO_GOTNTPOFF, "x86-gotntpoff"},
6492 {MO_DLLIMPORT, "x86-dllimport"},
6493 {MO_DARWIN_STUB, "x86-darwin-stub"},
6494 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
6495 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
6496 {MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, "x86-darwin-hidden-nonlazy-pic-base"},
6497 {MO_TLVP, "x86-tlvp"},
6498 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
6499 {MO_SECREL, "x86-secrel"}};
6500 return makeArrayRef(TargetFlags);
6501}
6502
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6503namespace {
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6504 /// Create Global Base Reg pass. This initializes the PIC
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6505 /// global base register for x86-32.
6506 struct CGBR : public MachineFunctionPass {
6507 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]6508 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6509
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6510 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6511 const X86TargetMachine *TM =
6512 static_cast<const X86TargetMachine *>(&MF.getTarget());
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6513 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6514
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]6515 // Don't do anything if this is 64-bit as 64-bit PIC
6516 // uses RIP relative addressing.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6517 if (STI.is64Bit())
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]6518 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6519
6520 // Only emit a global base reg in PIC mode.
6521 if (TM->getRelocationModel() != Reloc::PIC_)
6522 return false;
6523
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]6524 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
6525 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6526
6527 // If we didn't need a GlobalBaseReg, don't insert code.
6528 if (GlobalBaseReg == 0)
6529 return false;
6530
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6531 // Insert the set of GlobalBaseReg into the first MBB of the function
6532 MachineBasicBlock &FirstMBB = MF.front();
6533 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
6534 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
6535 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6536 const X86InstrInfo *TII = STI.getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6537
6538 unsigned PC;
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6539 if (STI.isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]6540 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6541 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]6542 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6543
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6544 // Operand of MovePCtoStack is completely ignored by asm printer. It's
6545 // only used in JIT code emission as displacement to pc.
6546 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6547
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6548 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
6549 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6550 if (STI.isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6551 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
6552 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
6553 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
6554 X86II::MO_GOT_ABSOLUTE_ADDRESS);
6555 }
6556
6557 return true;
6558 }
6559
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6560 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6561 return "X86 PIC Global Base Reg Initialization";
6562 }
6563
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6564 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6565 AU.setPreservesCFG();
6566 MachineFunctionPass::getAnalysisUsage(AU);
6567 }
6568 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]6569}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6570
6571char CGBR::ID = 0;
6572FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]6573llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6574
6575namespace {
6576 struct LDTLSCleanup : public MachineFunctionPass {
6577 static char ID;
6578 LDTLSCleanup() : MachineFunctionPass(ID) {}
6579
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6580 bool runOnMachineFunction(MachineFunction &MF) override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6581 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
6582 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
6583 // No point folding accesses if there isn't at least two.
6584 return false;
6585 }
6586
6587 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
6588 return VisitNode(DT->getRootNode(), 0);
6589 }
6590
6591 // Visit the dominator subtree rooted at Node in pre-order.
6592 // If TLSBaseAddrReg is non-null, then use that to replace any
6593 // TLS_base_addr instructions. Otherwise, create the register
6594 // when the first such instruction is seen, and then use it
6595 // as we encounter more instructions.
6596 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
6597 MachineBasicBlock *BB = Node->getBlock();
6598 bool Changed = false;
6599
6600 // Traverse the current block.
6601 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
6602 ++I) {
6603 switch (I->getOpcode()) {
6604 case X86::TLS_base_addr32:
6605 case X86::TLS_base_addr64:
6606 if (TLSBaseAddrReg)
6607 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
6608 else
6609 I = SetRegister(I, &TLSBaseAddrReg);
6610 Changed = true;
6611 break;
6612 default:
6613 break;
6614 }
6615 }
6616
6617 // Visit the children of this block in the dominator tree.
6618 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
6619 I != E; ++I) {
6620 Changed |= VisitNode(*I, TLSBaseAddrReg);
6621 }
6622
6623 return Changed;
6624 }
6625
6626 // Replace the TLS_base_addr instruction I with a copy from
6627 // TLSBaseAddrReg, returning the new instruction.
6628 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
6629 unsigned TLSBaseAddrReg) {
6630 MachineFunction *MF = I->getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6631 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6632 const bool is64Bit = STI.is64Bit();
6633 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6634
6635 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
6636 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
6637 TII->get(TargetOpcode::COPY),
6638 is64Bit ? X86::RAX : X86::EAX)
6639 .addReg(TLSBaseAddrReg);
6640
6641 // Erase the TLS_base_addr instruction.
6642 I->eraseFromParent();
6643
6644 return Copy;
6645 }
6646
6647 // Create a virtal register in *TLSBaseAddrReg, and populate it by
6648 // inserting a copy instruction after I. Returns the new instruction.
6649 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
6650 MachineFunction *MF = I->getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6651 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
6652 const bool is64Bit = STI.is64Bit();
6653 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6654
6655 // Create a virtual register for the TLS base address.
6656 MachineRegisterInfo &RegInfo = MF->getRegInfo();
6657 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
6658 ? &X86::GR64RegClass
6659 : &X86::GR32RegClass);
6660
6661 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
6662 MachineInstr *Next = I->getNextNode();
6663 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
6664 TII->get(TargetOpcode::COPY),
6665 *TLSBaseAddrReg)
6666 .addReg(is64Bit ? X86::RAX : X86::EAX);
6667
6668 return Copy;
6669 }
6670
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6671 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6672 return "Local Dynamic TLS Access Clean-up";
6673 }
6674
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]6675 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6676 AU.setPreservesCFG();
6677 AU.addRequired<MachineDominatorTree>();
6678 MachineFunctionPass::getAnalysisUsage(AU);
6679 }
6680 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]6681}
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]6682
6683char LDTLSCleanup::ID = 0;
6684FunctionPass*
6685llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }