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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- SIISelLowering.cpp - SI DAG Lowering Implementation ---------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10/// \file
11/// \brief Custom DAG lowering for SI
12//
13//===----------------------------------------------------------------------===//
14
NAKAMURA Takumi45e0a832014-07-20 11:15:07 +000015#ifdef _MSC_VER
16// Provide M_PI.
17#define _USE_MATH_DEFINES
18#include <cmath>
19#endif
20
Christian Konig99ee0f42013-03-07 09:04:14 +000021#include "AMDGPU.h"
Matt Arsenaultc791f392014-06-23 18:00:31 +000022#include "AMDGPUIntrinsicInfo.h"
Matt Arsenault41e2f2b2014-02-24 21:01:28 +000023#include "AMDGPUSubtarget.h"
Tom Stellard8485fa02016-12-07 02:42:15 +000024#include "SIDefines.h"
Mehdi Aminib550cb12016-04-18 09:17:29 +000025#include "SIISelLowering.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000026#include "SIInstrInfo.h"
27#include "SIMachineFunctionInfo.h"
28#include "SIRegisterInfo.h"
Alexey Samsonova253bf92014-08-27 19:36:53 +000029#include "llvm/ADT/BitVector.h"
Matt Arsenault9a10cea2016-01-26 04:29:24 +000030#include "llvm/ADT/StringSwitch.h"
Christian Konig2c8f6d52013-03-07 09:03:52 +000031#include "llvm/CodeGen/CallingConvLower.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000032#include "llvm/CodeGen/MachineInstrBuilder.h"
33#include "llvm/CodeGen/MachineRegisterInfo.h"
34#include "llvm/CodeGen/SelectionDAG.h"
Wei Ding07e03712016-07-28 16:42:13 +000035#include "llvm/CodeGen/Analysis.h"
Oliver Stannard7e7d9832016-02-02 13:52:43 +000036#include "llvm/IR/DiagnosticInfo.h"
Benjamin Kramerd78bb462013-05-23 17:10:37 +000037#include "llvm/IR/Function.h"
Tom Stellard75aadc22012-12-11 21:25:42 +000038
39using namespace llvm;
40
Matt Arsenaultd486d3f2016-10-12 18:49:05 +000041static cl::opt<bool> EnableVGPRIndexMode(
42 "amdgpu-vgpr-index-mode",
43 cl::desc("Use GPR indexing mode instead of movrel for vector indexing"),
44 cl::init(false));
45
46
Tom Stellardf110f8f2016-04-14 16:27:03 +000047static unsigned findFirstFreeSGPR(CCState &CCInfo) {
48 unsigned NumSGPRs = AMDGPU::SGPR_32RegClass.getNumRegs();
49 for (unsigned Reg = 0; Reg < NumSGPRs; ++Reg) {
50 if (!CCInfo.isAllocated(AMDGPU::SGPR0 + Reg)) {
51 return AMDGPU::SGPR0 + Reg;
52 }
53 }
54 llvm_unreachable("Cannot allocate sgpr");
55}
56
Matt Arsenault43e92fe2016-06-24 06:30:11 +000057SITargetLowering::SITargetLowering(const TargetMachine &TM,
58 const SISubtarget &STI)
Eric Christopher7792e322015-01-30 23:24:40 +000059 : AMDGPUTargetLowering(TM, STI) {
Tom Stellard1bd80722014-04-30 15:31:33 +000060 addRegisterClass(MVT::i1, &AMDGPU::VReg_1RegClass);
Tom Stellard436780b2014-05-15 14:41:57 +000061 addRegisterClass(MVT::i64, &AMDGPU::SReg_64RegClass);
Christian Konig2214f142013-03-07 09:03:38 +000062
Marek Olsak79c05872016-11-25 17:37:09 +000063 addRegisterClass(MVT::i32, &AMDGPU::SReg_32_XM0RegClass);
Tom Stellard45c0b3a2015-01-07 20:59:25 +000064 addRegisterClass(MVT::f32, &AMDGPU::VGPR_32RegClass);
Tom Stellard75aadc22012-12-11 21:25:42 +000065
Tom Stellard436780b2014-05-15 14:41:57 +000066 addRegisterClass(MVT::f64, &AMDGPU::VReg_64RegClass);
67 addRegisterClass(MVT::v2i32, &AMDGPU::SReg_64RegClass);
68 addRegisterClass(MVT::v2f32, &AMDGPU::VReg_64RegClass);
Christian Konig2214f142013-03-07 09:03:38 +000069
Matt Arsenault61001bb2015-11-25 19:58:34 +000070 addRegisterClass(MVT::v2i64, &AMDGPU::SReg_128RegClass);
71 addRegisterClass(MVT::v2f64, &AMDGPU::SReg_128RegClass);
72
Tom Stellard436780b2014-05-15 14:41:57 +000073 addRegisterClass(MVT::v4i32, &AMDGPU::SReg_128RegClass);
74 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
Christian Konig2214f142013-03-07 09:03:38 +000075
Tom Stellardf0a21072014-11-18 20:39:39 +000076 addRegisterClass(MVT::v8i32, &AMDGPU::SReg_256RegClass);
Christian Konig2214f142013-03-07 09:03:38 +000077 addRegisterClass(MVT::v8f32, &AMDGPU::VReg_256RegClass);
78
Tom Stellardf0a21072014-11-18 20:39:39 +000079 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
Christian Konig2214f142013-03-07 09:03:38 +000080 addRegisterClass(MVT::v16f32, &AMDGPU::VReg_512RegClass);
Tom Stellard75aadc22012-12-11 21:25:42 +000081
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +000082 if (Subtarget->has16BitInsts()) {
Marek Olsak79c05872016-11-25 17:37:09 +000083 addRegisterClass(MVT::i16, &AMDGPU::SReg_32_XM0RegClass);
84 addRegisterClass(MVT::f16, &AMDGPU::SReg_32_XM0RegClass);
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +000085 }
Tom Stellard115a6152016-11-10 16:02:37 +000086
Eric Christopher23a3a7c2015-02-26 00:00:24 +000087 computeRegisterProperties(STI.getRegisterInfo());
Tom Stellard75aadc22012-12-11 21:25:42 +000088
Tom Stellard35bb18c2013-08-26 15:06:04 +000089 // We need to custom lower vector stores from local memory
Matt Arsenault71e66762016-05-21 02:27:49 +000090 setOperationAction(ISD::LOAD, MVT::v2i32, Custom);
Tom Stellard35bb18c2013-08-26 15:06:04 +000091 setOperationAction(ISD::LOAD, MVT::v4i32, Custom);
Tom Stellardaf775432013-10-23 00:44:32 +000092 setOperationAction(ISD::LOAD, MVT::v8i32, Custom);
93 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
Matt Arsenault71e66762016-05-21 02:27:49 +000094 setOperationAction(ISD::LOAD, MVT::i1, Custom);
Matt Arsenault2b957b52016-05-02 20:07:26 +000095
Matt Arsenaultbcdfee72016-05-02 20:13:51 +000096 setOperationAction(ISD::STORE, MVT::v2i32, Custom);
Matt Arsenault71e66762016-05-21 02:27:49 +000097 setOperationAction(ISD::STORE, MVT::v4i32, Custom);
98 setOperationAction(ISD::STORE, MVT::v8i32, Custom);
99 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
100 setOperationAction(ISD::STORE, MVT::i1, Custom);
Matt Arsenaultbcdfee72016-05-02 20:13:51 +0000101
Matt Arsenault71e66762016-05-21 02:27:49 +0000102 setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
103 setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
Matt Arsenault71e66762016-05-21 02:27:49 +0000104 setOperationAction(ISD::ConstantPool, MVT::v2i64, Expand);
105
106 setOperationAction(ISD::SELECT, MVT::i1, Promote);
Tom Stellard0ec134f2014-02-04 17:18:40 +0000107 setOperationAction(ISD::SELECT, MVT::i64, Custom);
Tom Stellardda99c6e2014-03-24 16:07:30 +0000108 setOperationAction(ISD::SELECT, MVT::f64, Promote);
109 AddPromotedToType(ISD::SELECT, MVT::f64, MVT::i64);
Tom Stellard81d871d2013-11-13 23:36:50 +0000110
Tom Stellard3ca1bfc2014-06-10 16:01:22 +0000111 setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
112 setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
113 setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
114 setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
Matt Arsenault71e66762016-05-21 02:27:49 +0000115 setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
Tom Stellard754f80f2013-04-05 23:31:51 +0000116
Tom Stellardd1efda82016-01-20 21:48:24 +0000117 setOperationAction(ISD::SETCC, MVT::i1, Promote);
Tom Stellard83747202013-07-18 21:43:53 +0000118 setOperationAction(ISD::SETCC, MVT::v2i1, Expand);
119 setOperationAction(ISD::SETCC, MVT::v4i1, Expand);
120
Matt Arsenault71e66762016-05-21 02:27:49 +0000121 setOperationAction(ISD::TRUNCATE, MVT::v2i32, Expand);
122 setOperationAction(ISD::FP_ROUND, MVT::v2f32, Expand);
Matt Arsenaulte306a322014-10-21 16:25:08 +0000123
Matt Arsenault4e466652014-04-16 01:41:30 +0000124 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i1, Custom);
125 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i1, Custom);
Matt Arsenault4e466652014-04-16 01:41:30 +0000126 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i8, Custom);
127 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i8, Custom);
Matt Arsenault4e466652014-04-16 01:41:30 +0000128 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v2i16, Custom);
129 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::v4i16, Custom);
Matt Arsenault4e466652014-04-16 01:41:30 +0000130 setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::Other, Custom);
131
Tom Stellard9fa17912013-08-14 23:24:45 +0000132 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::f32, Custom);
Tom Stellard9fa17912013-08-14 23:24:45 +0000133 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::v4f32, Custom);
Matt Arsenaulta9dbdca2016-04-12 14:05:04 +0000134 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
135
Matt Arsenaulte54e1c32014-06-23 18:00:44 +0000136 setOperationAction(ISD::BRCOND, MVT::Other, Custom);
Matt Arsenault71e66762016-05-21 02:27:49 +0000137 setOperationAction(ISD::BR_CC, MVT::i1, Expand);
Tom Stellardbc4497b2016-02-12 23:45:29 +0000138 setOperationAction(ISD::BR_CC, MVT::i32, Expand);
139 setOperationAction(ISD::BR_CC, MVT::i64, Expand);
140 setOperationAction(ISD::BR_CC, MVT::f32, Expand);
141 setOperationAction(ISD::BR_CC, MVT::f64, Expand);
Tom Stellardafcf12f2013-09-12 02:55:14 +0000142
Benjamin Kramer867bfc52015-03-07 17:41:00 +0000143 // We only support LOAD/STORE and vector manipulation ops for vectors
144 // with > 4 elements.
Matt Arsenault61001bb2015-11-25 19:58:34 +0000145 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) {
Tom Stellard967bf582014-02-13 23:34:15 +0000146 for (unsigned Op = 0; Op < ISD::BUILTIN_OP_END; ++Op) {
Matt Arsenault71e66762016-05-21 02:27:49 +0000147 switch (Op) {
Tom Stellard967bf582014-02-13 23:34:15 +0000148 case ISD::LOAD:
149 case ISD::STORE:
150 case ISD::BUILD_VECTOR:
151 case ISD::BITCAST:
152 case ISD::EXTRACT_VECTOR_ELT:
153 case ISD::INSERT_VECTOR_ELT:
Tom Stellard967bf582014-02-13 23:34:15 +0000154 case ISD::INSERT_SUBVECTOR:
155 case ISD::EXTRACT_SUBVECTOR:
Matt Arsenault61001bb2015-11-25 19:58:34 +0000156 case ISD::SCALAR_TO_VECTOR:
Tom Stellard967bf582014-02-13 23:34:15 +0000157 break;
Tom Stellardc0503db2014-08-09 01:06:56 +0000158 case ISD::CONCAT_VECTORS:
159 setOperationAction(Op, VT, Custom);
160 break;
Tom Stellard967bf582014-02-13 23:34:15 +0000161 default:
Matt Arsenaultd504a742014-05-15 21:44:05 +0000162 setOperationAction(Op, VT, Expand);
Tom Stellard967bf582014-02-13 23:34:15 +0000163 break;
164 }
165 }
166 }
167
Matt Arsenaultcb540bc2016-07-19 00:35:03 +0000168 // TODO: For dynamic 64-bit vector inserts/extracts, should emit a pseudo that
169 // is expanded to avoid having two separate loops in case the index is a VGPR.
170
Matt Arsenault61001bb2015-11-25 19:58:34 +0000171 // Most operations are naturally 32-bit vector operations. We only support
172 // load and store of i64 vectors, so promote v2i64 vector operations to v4i32.
173 for (MVT Vec64 : { MVT::v2i64, MVT::v2f64 }) {
174 setOperationAction(ISD::BUILD_VECTOR, Vec64, Promote);
175 AddPromotedToType(ISD::BUILD_VECTOR, Vec64, MVT::v4i32);
176
177 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Vec64, Promote);
178 AddPromotedToType(ISD::EXTRACT_VECTOR_ELT, Vec64, MVT::v4i32);
179
180 setOperationAction(ISD::INSERT_VECTOR_ELT, Vec64, Promote);
181 AddPromotedToType(ISD::INSERT_VECTOR_ELT, Vec64, MVT::v4i32);
182
183 setOperationAction(ISD::SCALAR_TO_VECTOR, Vec64, Promote);
184 AddPromotedToType(ISD::SCALAR_TO_VECTOR, Vec64, MVT::v4i32);
185 }
186
Matt Arsenault71e66762016-05-21 02:27:49 +0000187 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8i32, Expand);
188 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v8f32, Expand);
189 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
190 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16f32, Expand);
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +0000191
Tom Stellard354a43c2016-04-01 18:27:37 +0000192 // BUFFER/FLAT_ATOMIC_CMP_SWAP on GCN GPUs needs input marshalling,
193 // and output demarshalling
194 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i32, Custom);
195 setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i64, Custom);
196
197 // We can't return success/failure, only the old value,
198 // let LLVM add the comparison
199 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i32, Expand);
200 setOperationAction(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS, MVT::i64, Expand);
201
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000202 if (getSubtarget()->hasFlatAddressSpace()) {
Matt Arsenault99c14522016-04-25 19:27:24 +0000203 setOperationAction(ISD::ADDRSPACECAST, MVT::i32, Custom);
204 setOperationAction(ISD::ADDRSPACECAST, MVT::i64, Custom);
205 }
206
Matt Arsenault71e66762016-05-21 02:27:49 +0000207 setOperationAction(ISD::BSWAP, MVT::i32, Legal);
208 setOperationAction(ISD::BITREVERSE, MVT::i32, Legal);
209
210 // On SI this is s_memtime and s_memrealtime on VI.
211 setOperationAction(ISD::READCYCLECOUNTER, MVT::i64, Legal);
Matt Arsenault0bb294b2016-06-17 22:27:03 +0000212 setOperationAction(ISD::TRAP, MVT::Other, Custom);
Matt Arsenault71e66762016-05-21 02:27:49 +0000213
214 setOperationAction(ISD::FMINNUM, MVT::f64, Legal);
215 setOperationAction(ISD::FMAXNUM, MVT::f64, Legal);
216
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000217 if (Subtarget->getGeneration() >= SISubtarget::SEA_ISLANDS) {
Matt Arsenault71e66762016-05-21 02:27:49 +0000218 setOperationAction(ISD::FTRUNC, MVT::f64, Legal);
219 setOperationAction(ISD::FCEIL, MVT::f64, Legal);
220 setOperationAction(ISD::FRINT, MVT::f64, Legal);
221 }
222
223 setOperationAction(ISD::FFLOOR, MVT::f64, Legal);
224
225 setOperationAction(ISD::FSIN, MVT::f32, Custom);
226 setOperationAction(ISD::FCOS, MVT::f32, Custom);
227 setOperationAction(ISD::FDIV, MVT::f32, Custom);
228 setOperationAction(ISD::FDIV, MVT::f64, Custom);
229
Tom Stellard115a6152016-11-10 16:02:37 +0000230 if (Subtarget->has16BitInsts()) {
231 setOperationAction(ISD::Constant, MVT::i16, Legal);
232
233 setOperationAction(ISD::SMIN, MVT::i16, Legal);
234 setOperationAction(ISD::SMAX, MVT::i16, Legal);
235
236 setOperationAction(ISD::UMIN, MVT::i16, Legal);
237 setOperationAction(ISD::UMAX, MVT::i16, Legal);
238
239 setOperationAction(ISD::SETCC, MVT::i16, Promote);
240 AddPromotedToType(ISD::SETCC, MVT::i16, MVT::i32);
241
242 setOperationAction(ISD::SIGN_EXTEND, MVT::i16, Promote);
243 AddPromotedToType(ISD::SIGN_EXTEND, MVT::i16, MVT::i32);
244
245 setOperationAction(ISD::ROTR, MVT::i16, Promote);
246 setOperationAction(ISD::ROTL, MVT::i16, Promote);
247
248 setOperationAction(ISD::SDIV, MVT::i16, Promote);
249 setOperationAction(ISD::UDIV, MVT::i16, Promote);
250 setOperationAction(ISD::SREM, MVT::i16, Promote);
251 setOperationAction(ISD::UREM, MVT::i16, Promote);
252
253 setOperationAction(ISD::BSWAP, MVT::i16, Promote);
254 setOperationAction(ISD::BITREVERSE, MVT::i16, Promote);
255
256 setOperationAction(ISD::CTTZ, MVT::i16, Promote);
257 setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Promote);
258 setOperationAction(ISD::CTLZ, MVT::i16, Promote);
259 setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Promote);
260
261 setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
262
263 setOperationAction(ISD::BR_CC, MVT::i16, Expand);
264
265 setOperationAction(ISD::LOAD, MVT::i16, Custom);
266
267 setTruncStoreAction(MVT::i64, MVT::i16, Expand);
268
Tom Stellard115a6152016-11-10 16:02:37 +0000269 setOperationAction(ISD::FP16_TO_FP, MVT::i16, Promote);
270 AddPromotedToType(ISD::FP16_TO_FP, MVT::i16, MVT::i32);
271 setOperationAction(ISD::FP_TO_FP16, MVT::i16, Promote);
272 AddPromotedToType(ISD::FP_TO_FP16, MVT::i16, MVT::i32);
Tom Stellardb4c8e8e2016-11-12 00:19:11 +0000273
Konstantin Zhuravlyov3f0cdc72016-11-17 04:00:46 +0000274 setOperationAction(ISD::FP_TO_SINT, MVT::i16, Promote);
275 setOperationAction(ISD::FP_TO_UINT, MVT::i16, Promote);
276 setOperationAction(ISD::SINT_TO_FP, MVT::i16, Promote);
277 setOperationAction(ISD::UINT_TO_FP, MVT::i16, Promote);
Tom Stellardb4c8e8e2016-11-12 00:19:11 +0000278
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000279 // F16 - Constant Actions.
Matt Arsenaulte96d0372016-12-08 20:14:46 +0000280 setOperationAction(ISD::ConstantFP, MVT::f16, Legal);
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000281
282 // F16 - Load/Store Actions.
283 setOperationAction(ISD::LOAD, MVT::f16, Promote);
284 AddPromotedToType(ISD::LOAD, MVT::f16, MVT::i16);
285 setOperationAction(ISD::STORE, MVT::f16, Promote);
286 AddPromotedToType(ISD::STORE, MVT::f16, MVT::i16);
287
288 // F16 - VOP1 Actions.
Konstantin Zhuravlyovd709efb2016-11-17 04:28:37 +0000289 setOperationAction(ISD::FP_ROUND, MVT::f16, Custom);
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000290 setOperationAction(ISD::FCOS, MVT::f16, Promote);
291 setOperationAction(ISD::FSIN, MVT::f16, Promote);
Konstantin Zhuravlyov3f0cdc72016-11-17 04:00:46 +0000292 setOperationAction(ISD::FP_TO_SINT, MVT::f16, Promote);
293 setOperationAction(ISD::FP_TO_UINT, MVT::f16, Promote);
294 setOperationAction(ISD::SINT_TO_FP, MVT::f16, Promote);
295 setOperationAction(ISD::UINT_TO_FP, MVT::f16, Promote);
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000296
297 // F16 - VOP2 Actions.
Konstantin Zhuravlyov662e01d2016-11-17 03:49:01 +0000298 setOperationAction(ISD::BR_CC, MVT::f16, Expand);
Konstantin Zhuravlyov2a87a422016-11-16 03:16:26 +0000299 setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000300 setOperationAction(ISD::FMAXNUM, MVT::f16, Legal);
301 setOperationAction(ISD::FMINNUM, MVT::f16, Legal);
302 setOperationAction(ISD::FDIV, MVT::f16, Promote);
303
304 // F16 - VOP3 Actions.
305 setOperationAction(ISD::FMA, MVT::f16, Legal);
306 if (!Subtarget->hasFP16Denormals())
307 setOperationAction(ISD::FMAD, MVT::f16, Legal);
Tom Stellard115a6152016-11-10 16:02:37 +0000308 }
309
Matt Arsenault02cb0ff2014-09-29 14:59:34 +0000310 setTargetDAGCombine(ISD::FADD);
Matt Arsenault8675db12014-08-29 16:01:14 +0000311 setTargetDAGCombine(ISD::FSUB);
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +0000312 setTargetDAGCombine(ISD::FMINNUM);
313 setTargetDAGCombine(ISD::FMAXNUM);
Matt Arsenault5881f4e2015-06-09 00:52:37 +0000314 setTargetDAGCombine(ISD::SMIN);
315 setTargetDAGCombine(ISD::SMAX);
316 setTargetDAGCombine(ISD::UMIN);
317 setTargetDAGCombine(ISD::UMAX);
Tom Stellard75aadc22012-12-11 21:25:42 +0000318 setTargetDAGCombine(ISD::SETCC);
Matt Arsenaultd0101a22015-01-06 23:00:46 +0000319 setTargetDAGCombine(ISD::AND);
Matt Arsenaultf2290332015-01-06 23:00:39 +0000320 setTargetDAGCombine(ISD::OR);
Matt Arsenaultfa5f7672016-09-14 15:19:03 +0000321 setTargetDAGCombine(ISD::XOR);
Konstantin Zhuravlyovfda33ea2016-10-21 22:10:03 +0000322 setTargetDAGCombine(ISD::SINT_TO_FP);
Matt Arsenault364a6742014-06-11 17:50:44 +0000323 setTargetDAGCombine(ISD::UINT_TO_FP);
Matt Arsenault9cd90712016-04-14 01:42:16 +0000324 setTargetDAGCombine(ISD::FCANONICALIZE);
Matt Arsenault364a6742014-06-11 17:50:44 +0000325
Matt Arsenaultb2baffa2014-08-15 17:49:05 +0000326 // All memory operations. Some folding on the pointer operand is done to help
327 // matching the constant offsets in the addressing modes.
328 setTargetDAGCombine(ISD::LOAD);
329 setTargetDAGCombine(ISD::STORE);
330 setTargetDAGCombine(ISD::ATOMIC_LOAD);
331 setTargetDAGCombine(ISD::ATOMIC_STORE);
332 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP);
333 setTargetDAGCombine(ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS);
334 setTargetDAGCombine(ISD::ATOMIC_SWAP);
335 setTargetDAGCombine(ISD::ATOMIC_LOAD_ADD);
336 setTargetDAGCombine(ISD::ATOMIC_LOAD_SUB);
337 setTargetDAGCombine(ISD::ATOMIC_LOAD_AND);
338 setTargetDAGCombine(ISD::ATOMIC_LOAD_OR);
339 setTargetDAGCombine(ISD::ATOMIC_LOAD_XOR);
340 setTargetDAGCombine(ISD::ATOMIC_LOAD_NAND);
341 setTargetDAGCombine(ISD::ATOMIC_LOAD_MIN);
342 setTargetDAGCombine(ISD::ATOMIC_LOAD_MAX);
343 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMIN);
344 setTargetDAGCombine(ISD::ATOMIC_LOAD_UMAX);
345
Christian Konigeecebd02013-03-26 14:04:02 +0000346 setSchedulingPreference(Sched::RegPressure);
Tom Stellard75aadc22012-12-11 21:25:42 +0000347}
348
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000349const SISubtarget *SITargetLowering::getSubtarget() const {
350 return static_cast<const SISubtarget *>(Subtarget);
351}
352
Tom Stellard0125f2a2013-06-25 02:39:35 +0000353//===----------------------------------------------------------------------===//
354// TargetLowering queries
355//===----------------------------------------------------------------------===//
356
Matt Arsenaulta9dbdca2016-04-12 14:05:04 +0000357bool SITargetLowering::getTgtMemIntrinsic(IntrinsicInfo &Info,
358 const CallInst &CI,
359 unsigned IntrID) const {
360 switch (IntrID) {
361 case Intrinsic::amdgcn_atomic_inc:
362 case Intrinsic::amdgcn_atomic_dec:
363 Info.opc = ISD::INTRINSIC_W_CHAIN;
364 Info.memVT = MVT::getVT(CI.getType());
365 Info.ptrVal = CI.getOperand(0);
366 Info.align = 0;
367 Info.vol = false;
368 Info.readMem = true;
369 Info.writeMem = true;
370 return true;
371 default:
372 return false;
373 }
374}
375
Matt Arsenaulte306a322014-10-21 16:25:08 +0000376bool SITargetLowering::isShuffleMaskLegal(const SmallVectorImpl<int> &,
377 EVT) const {
378 // SI has some legal vector types, but no legal vector operations. Say no
379 // shuffles are legal in order to prefer scalarizing some vector operations.
380 return false;
381}
382
Tom Stellard70580f82015-07-20 14:28:41 +0000383bool SITargetLowering::isLegalFlatAddressingMode(const AddrMode &AM) const {
384 // Flat instructions do not have offsets, and only have the register
385 // address.
386 return AM.BaseOffs == 0 && (AM.Scale == 0 || AM.Scale == 1);
387}
388
Matt Arsenault711b3902015-08-07 20:18:34 +0000389bool SITargetLowering::isLegalMUBUFAddressingMode(const AddrMode &AM) const {
390 // MUBUF / MTBUF instructions have a 12-bit unsigned byte offset, and
391 // additionally can do r + r + i with addr64. 32-bit has more addressing
392 // mode options. Depending on the resource constant, it can also do
393 // (i64 r0) + (i32 r1) * (i14 i).
394 //
395 // Private arrays end up using a scratch buffer most of the time, so also
396 // assume those use MUBUF instructions. Scratch loads / stores are currently
397 // implemented as mubuf instructions with offen bit set, so slightly
398 // different than the normal addr64.
399 if (!isUInt<12>(AM.BaseOffs))
400 return false;
401
402 // FIXME: Since we can split immediate into soffset and immediate offset,
403 // would it make sense to allow any immediate?
404
405 switch (AM.Scale) {
406 case 0: // r + i or just i, depending on HasBaseReg.
407 return true;
408 case 1:
409 return true; // We have r + r or r + i.
410 case 2:
411 if (AM.HasBaseReg) {
412 // Reject 2 * r + r.
413 return false;
414 }
415
416 // Allow 2 * r as r + r
417 // Or 2 * r + i is allowed as r + r + i.
418 return true;
419 default: // Don't allow n * r
420 return false;
421 }
422}
423
Mehdi Amini0cdec1e2015-07-09 02:09:40 +0000424bool SITargetLowering::isLegalAddressingMode(const DataLayout &DL,
425 const AddrMode &AM, Type *Ty,
426 unsigned AS) const {
Matt Arsenault5015a892014-08-15 17:17:07 +0000427 // No global is ever allowed as a base.
428 if (AM.BaseGV)
429 return false;
430
Matt Arsenault73e06fa2015-06-04 16:17:42 +0000431 switch (AS) {
Matt Arsenault711b3902015-08-07 20:18:34 +0000432 case AMDGPUAS::GLOBAL_ADDRESS: {
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000433 if (Subtarget->getGeneration() >= SISubtarget::VOLCANIC_ISLANDS) {
Tom Stellard70580f82015-07-20 14:28:41 +0000434 // Assume the we will use FLAT for all global memory accesses
435 // on VI.
436 // FIXME: This assumption is currently wrong. On VI we still use
437 // MUBUF instructions for the r + i addressing mode. As currently
438 // implemented, the MUBUF instructions only work on buffer < 4GB.
439 // It may be possible to support > 4GB buffers with MUBUF instructions,
440 // by setting the stride value in the resource descriptor which would
441 // increase the size limit to (stride * 4GB). However, this is risky,
442 // because it has never been validated.
443 return isLegalFlatAddressingMode(AM);
444 }
Matt Arsenault5015a892014-08-15 17:17:07 +0000445
Matt Arsenault711b3902015-08-07 20:18:34 +0000446 return isLegalMUBUFAddressingMode(AM);
Matt Arsenault73e06fa2015-06-04 16:17:42 +0000447 }
Matt Arsenault711b3902015-08-07 20:18:34 +0000448 case AMDGPUAS::CONSTANT_ADDRESS: {
449 // If the offset isn't a multiple of 4, it probably isn't going to be
450 // correctly aligned.
Matt Arsenault3cc1e002016-08-13 01:43:51 +0000451 // FIXME: Can we get the real alignment here?
Matt Arsenault711b3902015-08-07 20:18:34 +0000452 if (AM.BaseOffs % 4 != 0)
453 return isLegalMUBUFAddressingMode(AM);
454
455 // There are no SMRD extloads, so if we have to do a small type access we
456 // will use a MUBUF load.
457 // FIXME?: We also need to do this if unaligned, but we don't know the
458 // alignment here.
459 if (DL.getTypeStoreSize(Ty) < 4)
460 return isLegalMUBUFAddressingMode(AM);
461
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000462 if (Subtarget->getGeneration() == SISubtarget::SOUTHERN_ISLANDS) {
Matt Arsenault711b3902015-08-07 20:18:34 +0000463 // SMRD instructions have an 8-bit, dword offset on SI.
464 if (!isUInt<8>(AM.BaseOffs / 4))
465 return false;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000466 } else if (Subtarget->getGeneration() == SISubtarget::SEA_ISLANDS) {
Matt Arsenault711b3902015-08-07 20:18:34 +0000467 // On CI+, this can also be a 32-bit literal constant offset. If it fits
468 // in 8-bits, it can use a smaller encoding.
469 if (!isUInt<32>(AM.BaseOffs / 4))
470 return false;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000471 } else if (Subtarget->getGeneration() == SISubtarget::VOLCANIC_ISLANDS) {
Matt Arsenault711b3902015-08-07 20:18:34 +0000472 // On VI, these use the SMEM format and the offset is 20-bit in bytes.
473 if (!isUInt<20>(AM.BaseOffs))
474 return false;
475 } else
476 llvm_unreachable("unhandled generation");
477
478 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
479 return true;
480
481 if (AM.Scale == 1 && AM.HasBaseReg)
482 return true;
483
484 return false;
485 }
486
487 case AMDGPUAS::PRIVATE_ADDRESS:
Matt Arsenault711b3902015-08-07 20:18:34 +0000488 return isLegalMUBUFAddressingMode(AM);
489
Matt Arsenault73e06fa2015-06-04 16:17:42 +0000490 case AMDGPUAS::LOCAL_ADDRESS:
491 case AMDGPUAS::REGION_ADDRESS: {
492 // Basic, single offset DS instructions allow a 16-bit unsigned immediate
493 // field.
494 // XXX - If doing a 4-byte aligned 8-byte type access, we effectively have
495 // an 8-bit dword offset but we don't know the alignment here.
496 if (!isUInt<16>(AM.BaseOffs))
Matt Arsenault5015a892014-08-15 17:17:07 +0000497 return false;
Matt Arsenault73e06fa2015-06-04 16:17:42 +0000498
499 if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
500 return true;
501
502 if (AM.Scale == 1 && AM.HasBaseReg)
503 return true;
504
Matt Arsenault5015a892014-08-15 17:17:07 +0000505 return false;
506 }
Tom Stellard70580f82015-07-20 14:28:41 +0000507 case AMDGPUAS::FLAT_ADDRESS:
Matt Arsenault7d1b6c82016-04-29 06:25:10 +0000508 case AMDGPUAS::UNKNOWN_ADDRESS_SPACE:
509 // For an unknown address space, this usually means that this is for some
510 // reason being used for pure arithmetic, and not based on some addressing
511 // computation. We don't have instructions that compute pointers with any
512 // addressing modes, so treat them as having no offset like flat
513 // instructions.
Tom Stellard70580f82015-07-20 14:28:41 +0000514 return isLegalFlatAddressingMode(AM);
515
Matt Arsenault73e06fa2015-06-04 16:17:42 +0000516 default:
517 llvm_unreachable("unhandled address space");
518 }
Matt Arsenault5015a892014-08-15 17:17:07 +0000519}
520
Matt Arsenaulte6986632015-01-14 01:35:22 +0000521bool SITargetLowering::allowsMisalignedMemoryAccesses(EVT VT,
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000522 unsigned AddrSpace,
523 unsigned Align,
524 bool *IsFast) const {
Matt Arsenault1018c892014-04-24 17:08:26 +0000525 if (IsFast)
526 *IsFast = false;
527
Matt Arsenault1018c892014-04-24 17:08:26 +0000528 // TODO: I think v3i32 should allow unaligned accesses on CI with DS_READ_B96,
529 // which isn't a simple VT.
Alina Sbirlea6f937b12016-08-04 16:38:44 +0000530 // Until MVT is extended to handle this, simply check for the size and
531 // rely on the condition below: allow accesses if the size is a multiple of 4.
532 if (VT == MVT::Other || (VT != MVT::Other && VT.getSizeInBits() > 1024 &&
533 VT.getStoreSize() > 16)) {
Tom Stellard81d871d2013-11-13 23:36:50 +0000534 return false;
Alina Sbirlea6f937b12016-08-04 16:38:44 +0000535 }
Matt Arsenault1018c892014-04-24 17:08:26 +0000536
Matt Arsenault7f681ac2016-07-01 23:03:44 +0000537 if (AddrSpace == AMDGPUAS::LOCAL_ADDRESS ||
538 AddrSpace == AMDGPUAS::REGION_ADDRESS) {
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000539 // ds_read/write_b64 require 8-byte alignment, but we can do a 4 byte
540 // aligned, 8 byte access in a single operation using ds_read2/write2_b32
541 // with adjacent offsets.
Sanjay Patelce74db92015-09-03 15:03:19 +0000542 bool AlignedBy4 = (Align % 4 == 0);
543 if (IsFast)
544 *IsFast = AlignedBy4;
Matt Arsenault7f681ac2016-07-01 23:03:44 +0000545
Sanjay Patelce74db92015-09-03 15:03:19 +0000546 return AlignedBy4;
Matt Arsenault6f2a5262014-07-27 17:46:40 +0000547 }
Matt Arsenault1018c892014-04-24 17:08:26 +0000548
Tom Stellard64a9d082016-10-14 18:10:39 +0000549 // FIXME: We have to be conservative here and assume that flat operations
550 // will access scratch. If we had access to the IR function, then we
551 // could determine if any private memory was used in the function.
552 if (!Subtarget->hasUnalignedScratchAccess() &&
553 (AddrSpace == AMDGPUAS::PRIVATE_ADDRESS ||
554 AddrSpace == AMDGPUAS::FLAT_ADDRESS)) {
555 return false;
556 }
557
Matt Arsenault7f681ac2016-07-01 23:03:44 +0000558 if (Subtarget->hasUnalignedBufferAccess()) {
559 // If we have an uniform constant load, it still requires using a slow
560 // buffer instruction if unaligned.
561 if (IsFast) {
562 *IsFast = (AddrSpace == AMDGPUAS::CONSTANT_ADDRESS) ?
563 (Align % 4 == 0) : true;
564 }
565
566 return true;
567 }
568
Tom Stellard33e64c62015-02-04 20:49:52 +0000569 // Smaller than dword value must be aligned.
Tom Stellard33e64c62015-02-04 20:49:52 +0000570 if (VT.bitsLT(MVT::i32))
571 return false;
572
Matt Arsenault1018c892014-04-24 17:08:26 +0000573 // 8.1.6 - For Dword or larger reads or writes, the two LSBs of the
574 // byte-address are ignored, thus forcing Dword alignment.
Tom Stellarde812f2f2014-07-21 15:45:06 +0000575 // This applies to private, global, and constant memory.
Matt Arsenault1018c892014-04-24 17:08:26 +0000576 if (IsFast)
577 *IsFast = true;
Tom Stellardc6b299c2015-02-02 18:02:28 +0000578
579 return VT.bitsGT(MVT::i32) && Align % 4 == 0;
Tom Stellard0125f2a2013-06-25 02:39:35 +0000580}
581
Matt Arsenault46645fa2014-07-28 17:49:26 +0000582EVT SITargetLowering::getOptimalMemOpType(uint64_t Size, unsigned DstAlign,
583 unsigned SrcAlign, bool IsMemset,
584 bool ZeroMemset,
585 bool MemcpyStrSrc,
586 MachineFunction &MF) const {
587 // FIXME: Should account for address space here.
588
589 // The default fallback uses the private pointer size as a guess for a type to
590 // use. Make sure we switch these to 64-bit accesses.
591
592 if (Size >= 16 && DstAlign >= 4) // XXX: Should only do for global
593 return MVT::v4i32;
594
595 if (Size >= 8 && DstAlign >= 4)
596 return MVT::v2i32;
597
598 // Use the default.
599 return MVT::Other;
600}
601
Matt Arsenaultf9bfeaf2015-12-01 23:04:00 +0000602static bool isFlatGlobalAddrSpace(unsigned AS) {
603 return AS == AMDGPUAS::GLOBAL_ADDRESS ||
Matt Arsenaultd4da0ed2016-12-02 18:12:53 +0000604 AS == AMDGPUAS::FLAT_ADDRESS ||
605 AS == AMDGPUAS::CONSTANT_ADDRESS;
Matt Arsenaultf9bfeaf2015-12-01 23:04:00 +0000606}
607
608bool SITargetLowering::isNoopAddrSpaceCast(unsigned SrcAS,
609 unsigned DestAS) const {
Matt Arsenault37fefd62016-06-10 02:18:02 +0000610 return isFlatGlobalAddrSpace(SrcAS) && isFlatGlobalAddrSpace(DestAS);
Matt Arsenaultf9bfeaf2015-12-01 23:04:00 +0000611}
612
Alexander Timofeev18009562016-12-08 17:28:47 +0000613bool SITargetLowering::isMemOpHasNoClobberedMemOperand(const SDNode *N) const {
614 const MemSDNode *MemNode = cast<MemSDNode>(N);
615 const Value *Ptr = MemNode->getMemOperand()->getValue();
616 const Instruction *I = dyn_cast<Instruction>(Ptr);
617 return I && I->getMetadata("amdgpu.noclobber");
618}
619
Matt Arsenaultd4da0ed2016-12-02 18:12:53 +0000620bool SITargetLowering::isCheapAddrSpaceCast(unsigned SrcAS,
621 unsigned DestAS) const {
622 // Flat -> private/local is a simple truncate.
623 // Flat -> global is no-op
624 if (SrcAS == AMDGPUAS::FLAT_ADDRESS)
625 return true;
626
627 return isNoopAddrSpaceCast(SrcAS, DestAS);
628}
629
Tom Stellarda6f24c62015-12-15 20:55:55 +0000630bool SITargetLowering::isMemOpUniform(const SDNode *N) const {
631 const MemSDNode *MemNode = cast<MemSDNode>(N);
632 const Value *Ptr = MemNode->getMemOperand()->getValue();
633
634 // UndefValue means this is a load of a kernel input. These are uniform.
Tom Stellard418beb72016-07-13 14:23:33 +0000635 // Sometimes LDS instructions have constant pointers.
636 // If Ptr is null, then that means this mem operand contains a
637 // PseudoSourceValue like GOT.
638 if (!Ptr || isa<UndefValue>(Ptr) || isa<Argument>(Ptr) ||
639 isa<Constant>(Ptr) || isa<GlobalValue>(Ptr))
Tom Stellarda6f24c62015-12-15 20:55:55 +0000640 return true;
641
Tom Stellard418beb72016-07-13 14:23:33 +0000642 const Instruction *I = dyn_cast<Instruction>(Ptr);
Tom Stellarda6f24c62015-12-15 20:55:55 +0000643 return I && I->getMetadata("amdgpu.uniform");
644}
645
Chandler Carruth9d010ff2014-07-03 00:23:43 +0000646TargetLoweringBase::LegalizeTypeAction
647SITargetLowering::getPreferredVectorAction(EVT VT) const {
648 if (VT.getVectorNumElements() != 1 && VT.getScalarType().bitsLE(MVT::i16))
649 return TypeSplitVector;
650
651 return TargetLoweringBase::getPreferredVectorAction(VT);
Tom Stellardd86003e2013-08-14 23:25:00 +0000652}
Tom Stellard0125f2a2013-06-25 02:39:35 +0000653
Matt Arsenaultd7bdcc42014-03-31 19:54:27 +0000654bool SITargetLowering::shouldConvertConstantLoadToIntImm(const APInt &Imm,
655 Type *Ty) const {
Matt Arsenault749035b2016-07-30 01:40:36 +0000656 // FIXME: Could be smarter if called for vector constants.
657 return true;
Matt Arsenaultd7bdcc42014-03-31 19:54:27 +0000658}
659
Tom Stellard2e045bb2016-01-20 00:13:22 +0000660bool SITargetLowering::isTypeDesirableForOp(unsigned Op, EVT VT) const {
Matt Arsenault7b00cf42016-12-09 17:57:43 +0000661 if (Subtarget->has16BitInsts() && VT == MVT::i16) {
662 switch (Op) {
663 case ISD::LOAD:
664 case ISD::STORE:
Tom Stellard2e045bb2016-01-20 00:13:22 +0000665
Matt Arsenault7b00cf42016-12-09 17:57:43 +0000666 // These operations are done with 32-bit instructions anyway.
667 case ISD::AND:
668 case ISD::OR:
669 case ISD::XOR:
670 case ISD::SELECT:
671 // TODO: Extensions?
672 return true;
673 default:
674 return false;
675 }
676 }
Konstantin Zhuravlyove14df4b2016-09-28 20:05:39 +0000677
Tom Stellard2e045bb2016-01-20 00:13:22 +0000678 // SimplifySetCC uses this function to determine whether or not it should
679 // create setcc with i1 operands. We don't have instructions for i1 setcc.
680 if (VT == MVT::i1 && Op == ISD::SETCC)
681 return false;
682
683 return TargetLowering::isTypeDesirableForOp(Op, VT);
684}
685
Jan Veselyfea814d2016-06-21 20:46:20 +0000686SDValue SITargetLowering::LowerParameterPtr(SelectionDAG &DAG,
687 const SDLoc &SL, SDValue Chain,
688 unsigned Offset) const {
Mehdi Aminia749f2a2015-07-09 02:09:52 +0000689 const DataLayout &DL = DAG.getDataLayout();
Tom Stellardec2e43c2014-09-22 15:35:29 +0000690 MachineFunction &MF = DAG.getMachineFunction();
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000691 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
Matt Arsenaultac234b62015-11-30 21:15:57 +0000692 unsigned InputPtrReg = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
Tom Stellard94593ee2013-06-03 17:40:18 +0000693
Matt Arsenault86033ca2014-07-28 17:31:39 +0000694 MachineRegisterInfo &MRI = DAG.getMachineFunction().getRegInfo();
Mehdi Aminia749f2a2015-07-09 02:09:52 +0000695 MVT PtrVT = getPointerTy(DL, AMDGPUAS::CONSTANT_ADDRESS);
Matt Arsenaulta0269b62015-06-01 21:58:24 +0000696 SDValue BasePtr = DAG.getCopyFromReg(Chain, SL,
697 MRI.getLiveInVirtReg(InputPtrReg), PtrVT);
Jan Veselyfea814d2016-06-21 20:46:20 +0000698 return DAG.getNode(ISD::ADD, SL, PtrVT, BasePtr,
699 DAG.getConstant(Offset, SL, PtrVT));
700}
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000701
Jan Veselyfea814d2016-06-21 20:46:20 +0000702SDValue SITargetLowering::LowerParameter(SelectionDAG &DAG, EVT VT, EVT MemVT,
703 const SDLoc &SL, SDValue Chain,
704 unsigned Offset, bool Signed) const {
705 const DataLayout &DL = DAG.getDataLayout();
Tom Stellard083f1622016-10-17 16:56:19 +0000706 Type *Ty = MemVT.getTypeForEVT(*DAG.getContext());
Jan Veselyfea814d2016-06-21 20:46:20 +0000707 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
Matt Arsenault86033ca2014-07-28 17:31:39 +0000708 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
709
Mehdi Aminia749f2a2015-07-09 02:09:52 +0000710 unsigned Align = DL.getABITypeAlignment(Ty);
Matt Arsenault81c7ae22015-06-04 16:00:27 +0000711
Jan Veselyfea814d2016-06-21 20:46:20 +0000712 SDValue Ptr = LowerParameterPtr(DAG, SL, Chain, Offset);
Tom Stellardbc6c5232016-10-17 16:21:45 +0000713 SDValue Load = DAG.getLoad(MemVT, SL, Chain, Ptr, PtrInfo, Align,
714 MachineMemOperand::MONonTemporal |
715 MachineMemOperand::MODereferenceable |
716 MachineMemOperand::MOInvariant);
717
718 SDValue Val;
719 if (MemVT.isFloatingPoint())
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000720 Val = getFPExtOrFPTrunc(DAG, Load, SL, VT);
Tom Stellardbc6c5232016-10-17 16:21:45 +0000721 else if (Signed)
722 Val = DAG.getSExtOrTrunc(Load, SL, VT);
723 else
724 Val = DAG.getZExtOrTrunc(Load, SL, VT);
725
726 SDValue Ops[] = {
727 Val,
728 Load.getValue(1)
729 };
730
731 return DAG.getMergeValues(Ops, SL);
Tom Stellard94593ee2013-06-03 17:40:18 +0000732}
733
Christian Konig2c8f6d52013-03-07 09:03:52 +0000734SDValue SITargetLowering::LowerFormalArguments(
Eric Christopher7792e322015-01-30 23:24:40 +0000735 SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000736 const SmallVectorImpl<ISD::InputArg> &Ins, const SDLoc &DL,
737 SelectionDAG &DAG, SmallVectorImpl<SDValue> &InVals) const {
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000738 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
Christian Konig2c8f6d52013-03-07 09:03:52 +0000739
740 MachineFunction &MF = DAG.getMachineFunction();
741 FunctionType *FType = MF.getFunction()->getFunctionType();
Christian Konig99ee0f42013-03-07 09:04:14 +0000742 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000743 const SISubtarget &ST = MF.getSubtarget<SISubtarget>();
Christian Konig2c8f6d52013-03-07 09:03:52 +0000744
Nicolai Haehnledf3a20c2016-04-06 19:40:20 +0000745 if (Subtarget->isAmdHsaOS() && AMDGPU::isShader(CallConv)) {
Matt Arsenaultd48da142015-11-02 23:23:02 +0000746 const Function *Fn = MF.getFunction();
Oliver Stannard7e7d9832016-02-02 13:52:43 +0000747 DiagnosticInfoUnsupported NoGraphicsHSA(
748 *Fn, "unsupported non-compute shaders with HSA", DL.getDebugLoc());
Matt Arsenaultd48da142015-11-02 23:23:02 +0000749 DAG.getContext()->diagnose(NoGraphicsHSA);
Diana Picus81bc3172016-05-26 15:24:55 +0000750 return DAG.getEntryNode();
Matt Arsenaultd48da142015-11-02 23:23:02 +0000751 }
752
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +0000753 // Create stack objects that are used for emitting debugger prologue if
754 // "amdgpu-debugger-emit-prologue" attribute was specified.
755 if (ST.debuggerEmitPrologue())
756 createDebuggerPrologueStackObjects(MF);
757
Christian Konig2c8f6d52013-03-07 09:03:52 +0000758 SmallVector<ISD::InputArg, 16> Splits;
Alexey Samsonova253bf92014-08-27 19:36:53 +0000759 BitVector Skipped(Ins.size());
Christian Konig99ee0f42013-03-07 09:04:14 +0000760
761 for (unsigned i = 0, e = Ins.size(), PSInputNum = 0; i != e; ++i) {
Christian Konig2c8f6d52013-03-07 09:03:52 +0000762 const ISD::InputArg &Arg = Ins[i];
Matt Arsenault758659232013-05-18 00:21:46 +0000763
764 // First check if it's a PS input addr
Nicolai Haehnledf3a20c2016-04-06 19:40:20 +0000765 if (CallConv == CallingConv::AMDGPU_PS && !Arg.Flags.isInReg() &&
Marek Olsakb6c8c3d2016-01-13 11:46:10 +0000766 !Arg.Flags.isByVal() && PSInputNum <= 15) {
Christian Konig99ee0f42013-03-07 09:04:14 +0000767
Marek Olsakfccabaf2016-01-13 11:45:36 +0000768 if (!Arg.Used && !Info->isPSInputAllocated(PSInputNum)) {
Benjamin Kramerdf005cb2015-08-08 18:27:36 +0000769 // We can safely skip PS inputs
Alexey Samsonova253bf92014-08-27 19:36:53 +0000770 Skipped.set(i);
Christian Konig99ee0f42013-03-07 09:04:14 +0000771 ++PSInputNum;
772 continue;
773 }
774
Marek Olsakfccabaf2016-01-13 11:45:36 +0000775 Info->markPSInputAllocated(PSInputNum);
776 if (Arg.Used)
777 Info->PSInputEna |= 1 << PSInputNum;
778
779 ++PSInputNum;
Christian Konig99ee0f42013-03-07 09:04:14 +0000780 }
781
Matt Arsenault539ca882016-05-05 20:27:02 +0000782 if (AMDGPU::isShader(CallConv)) {
783 // Second split vertices into their elements
784 if (Arg.VT.isVector()) {
785 ISD::InputArg NewArg = Arg;
786 NewArg.Flags.setSplit();
787 NewArg.VT = Arg.VT.getVectorElementType();
Christian Konig2c8f6d52013-03-07 09:03:52 +0000788
Matt Arsenault539ca882016-05-05 20:27:02 +0000789 // We REALLY want the ORIGINAL number of vertex elements here, e.g. a
790 // three or five element vertex only needs three or five registers,
791 // NOT four or eight.
792 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
793 unsigned NumElements = ParamType->getVectorNumElements();
Christian Konig2c8f6d52013-03-07 09:03:52 +0000794
Matt Arsenault539ca882016-05-05 20:27:02 +0000795 for (unsigned j = 0; j != NumElements; ++j) {
796 Splits.push_back(NewArg);
797 NewArg.PartOffset += NewArg.VT.getStoreSize();
798 }
799 } else {
800 Splits.push_back(Arg);
Christian Konig2c8f6d52013-03-07 09:03:52 +0000801 }
Christian Konig2c8f6d52013-03-07 09:03:52 +0000802 }
803 }
804
805 SmallVector<CCValAssign, 16> ArgLocs;
Eric Christopherb5217502014-08-06 18:45:26 +0000806 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), ArgLocs,
807 *DAG.getContext());
Christian Konig2c8f6d52013-03-07 09:03:52 +0000808
Christian Konig99ee0f42013-03-07 09:04:14 +0000809 // At least one interpolation mode must be enabled or else the GPU will hang.
Marek Olsakfccabaf2016-01-13 11:45:36 +0000810 //
811 // Check PSInputAddr instead of PSInputEna. The idea is that if the user set
812 // PSInputAddr, the user wants to enable some bits after the compilation
813 // based on run-time states. Since we can't know what the final PSInputEna
814 // will look like, so we shouldn't do anything here and the user should take
815 // responsibility for the correct programming.
Marek Olsak46dadbf2016-01-13 17:23:20 +0000816 //
817 // Otherwise, the following restrictions apply:
818 // - At least one of PERSP_* (0xF) or LINEAR_* (0x70) must be enabled.
819 // - If POS_W_FLOAT (11) is enabled, at least one of PERSP_* must be
820 // enabled too.
Nicolai Haehnledf3a20c2016-04-06 19:40:20 +0000821 if (CallConv == CallingConv::AMDGPU_PS &&
Marek Olsak46dadbf2016-01-13 17:23:20 +0000822 ((Info->getPSInputAddr() & 0x7F) == 0 ||
NAKAMURA Takumife1202c2016-06-20 00:37:41 +0000823 ((Info->getPSInputAddr() & 0xF) == 0 && Info->isPSInputAllocated(11)))) {
Christian Konig99ee0f42013-03-07 09:04:14 +0000824 CCInfo.AllocateReg(AMDGPU::VGPR0);
825 CCInfo.AllocateReg(AMDGPU::VGPR1);
Marek Olsakfccabaf2016-01-13 11:45:36 +0000826 Info->markPSInputAllocated(0);
827 Info->PSInputEna |= 1;
Christian Konig99ee0f42013-03-07 09:04:14 +0000828 }
829
Nicolai Haehnledf3a20c2016-04-06 19:40:20 +0000830 if (!AMDGPU::isShader(CallConv)) {
Tom Stellardf110f8f2016-04-14 16:27:03 +0000831 assert(Info->hasWorkGroupIDX() && Info->hasWorkItemIDX());
832 } else {
833 assert(!Info->hasPrivateSegmentBuffer() && !Info->hasDispatchPtr() &&
834 !Info->hasKernargSegmentPtr() && !Info->hasFlatScratchInit() &&
835 !Info->hasWorkGroupIDX() && !Info->hasWorkGroupIDY() &&
836 !Info->hasWorkGroupIDZ() && !Info->hasWorkGroupInfo() &&
837 !Info->hasWorkItemIDX() && !Info->hasWorkItemIDY() &&
838 !Info->hasWorkItemIDZ());
Tom Stellardaf775432013-10-23 00:44:32 +0000839 }
840
Matt Arsenault26f8f3d2015-11-30 21:16:03 +0000841 // FIXME: How should these inputs interact with inreg / custom SGPR inputs?
842 if (Info->hasPrivateSegmentBuffer()) {
843 unsigned PrivateSegmentBufferReg = Info->addPrivateSegmentBuffer(*TRI);
844 MF.addLiveIn(PrivateSegmentBufferReg, &AMDGPU::SReg_128RegClass);
845 CCInfo.AllocateReg(PrivateSegmentBufferReg);
846 }
847
848 if (Info->hasDispatchPtr()) {
849 unsigned DispatchPtrReg = Info->addDispatchPtr(*TRI);
Matt Arsenaultcdad3162016-11-29 19:39:48 +0000850 MF.addLiveIn(DispatchPtrReg, &AMDGPU::SGPR_64RegClass);
Matt Arsenault26f8f3d2015-11-30 21:16:03 +0000851 CCInfo.AllocateReg(DispatchPtrReg);
852 }
853
Matt Arsenault48ab5262016-04-25 19:27:18 +0000854 if (Info->hasQueuePtr()) {
855 unsigned QueuePtrReg = Info->addQueuePtr(*TRI);
Matt Arsenaultcdad3162016-11-29 19:39:48 +0000856 MF.addLiveIn(QueuePtrReg, &AMDGPU::SGPR_64RegClass);
Matt Arsenault48ab5262016-04-25 19:27:18 +0000857 CCInfo.AllocateReg(QueuePtrReg);
858 }
859
Matt Arsenault26f8f3d2015-11-30 21:16:03 +0000860 if (Info->hasKernargSegmentPtr()) {
861 unsigned InputPtrReg = Info->addKernargSegmentPtr(*TRI);
Matt Arsenaultcdad3162016-11-29 19:39:48 +0000862 MF.addLiveIn(InputPtrReg, &AMDGPU::SGPR_64RegClass);
Matt Arsenault26f8f3d2015-11-30 21:16:03 +0000863 CCInfo.AllocateReg(InputPtrReg);
864 }
865
Matt Arsenault8d718dc2016-07-22 17:01:30 +0000866 if (Info->hasDispatchID()) {
867 unsigned DispatchIDReg = Info->addDispatchID(*TRI);
Matt Arsenaultcdad3162016-11-29 19:39:48 +0000868 MF.addLiveIn(DispatchIDReg, &AMDGPU::SGPR_64RegClass);
Matt Arsenault8d718dc2016-07-22 17:01:30 +0000869 CCInfo.AllocateReg(DispatchIDReg);
870 }
871
Matt Arsenault296b8492016-02-12 06:31:30 +0000872 if (Info->hasFlatScratchInit()) {
873 unsigned FlatScratchInitReg = Info->addFlatScratchInit(*TRI);
Matt Arsenaultcdad3162016-11-29 19:39:48 +0000874 MF.addLiveIn(FlatScratchInitReg, &AMDGPU::SGPR_64RegClass);
Matt Arsenault296b8492016-02-12 06:31:30 +0000875 CCInfo.AllocateReg(FlatScratchInitReg);
876 }
877
Tom Stellardbbeb45a2016-09-16 21:53:00 +0000878 if (!AMDGPU::isShader(CallConv))
879 analyzeFormalArgumentsCompute(CCInfo, Ins);
880 else
881 AnalyzeFormalArguments(CCInfo, Splits);
Christian Konig2c8f6d52013-03-07 09:03:52 +0000882
Matt Arsenaultcf13d182015-07-10 22:51:36 +0000883 SmallVector<SDValue, 16> Chains;
884
Christian Konig2c8f6d52013-03-07 09:03:52 +0000885 for (unsigned i = 0, e = Ins.size(), ArgIdx = 0; i != e; ++i) {
886
Christian Konigb7be72d2013-05-17 09:46:48 +0000887 const ISD::InputArg &Arg = Ins[i];
Alexey Samsonova253bf92014-08-27 19:36:53 +0000888 if (Skipped[i]) {
Christian Konigb7be72d2013-05-17 09:46:48 +0000889 InVals.push_back(DAG.getUNDEF(Arg.VT));
Christian Konig99ee0f42013-03-07 09:04:14 +0000890 continue;
891 }
892
Christian Konig2c8f6d52013-03-07 09:03:52 +0000893 CCValAssign &VA = ArgLocs[ArgIdx++];
Craig Topper7f416c82014-11-16 21:17:18 +0000894 MVT VT = VA.getLocVT();
Tom Stellarded882c22013-06-03 17:40:11 +0000895
896 if (VA.isMemLoc()) {
Tom Stellardaf775432013-10-23 00:44:32 +0000897 VT = Ins[i].VT;
Tom Stellardbbeb45a2016-09-16 21:53:00 +0000898 EVT MemVT = VA.getLocVT();
Tom Stellardb5798b02015-06-26 21:15:03 +0000899 const unsigned Offset = Subtarget->getExplicitKernelArgOffset() +
900 VA.getLocMemOffset();
Tom Stellard94593ee2013-06-03 17:40:18 +0000901 // The first 36 bytes of the input buffer contains information about
902 // thread group and global sizes.
Matt Arsenault0d519732015-07-10 22:28:41 +0000903 SDValue Arg = LowerParameter(DAG, VT, MemVT, DL, Chain,
Jan Veselye5121f32014-10-14 20:05:26 +0000904 Offset, Ins[i].Flags.isSExt());
Matt Arsenaultcf13d182015-07-10 22:51:36 +0000905 Chains.push_back(Arg.getValue(1));
Tom Stellardca7ecf32014-08-22 18:49:31 +0000906
Craig Toppere3dcce92015-08-01 22:20:21 +0000907 auto *ParamTy =
Andrew Trick05938a52015-02-16 18:10:47 +0000908 dyn_cast<PointerType>(FType->getParamType(Ins[i].getOrigArgIndex()));
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000909 if (Subtarget->getGeneration() == SISubtarget::SOUTHERN_ISLANDS &&
Tom Stellardca7ecf32014-08-22 18:49:31 +0000910 ParamTy && ParamTy->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS) {
911 // On SI local pointers are just offsets into LDS, so they are always
912 // less than 16-bits. On CI and newer they could potentially be
913 // real pointers, so we can't guarantee their size.
914 Arg = DAG.getNode(ISD::AssertZext, DL, Arg.getValueType(), Arg,
915 DAG.getValueType(MVT::i16));
916 }
917
Tom Stellarded882c22013-06-03 17:40:11 +0000918 InVals.push_back(Arg);
Matt Arsenault52ef4012016-07-26 16:45:58 +0000919 Info->setABIArgOffset(Offset + MemVT.getStoreSize());
Tom Stellarded882c22013-06-03 17:40:11 +0000920 continue;
921 }
Christian Konig2c8f6d52013-03-07 09:03:52 +0000922 assert(VA.isRegLoc() && "Parameter must be in a register!");
923
924 unsigned Reg = VA.getLocReg();
Christian Konig2c8f6d52013-03-07 09:03:52 +0000925
926 if (VT == MVT::i64) {
927 // For now assume it is a pointer
928 Reg = TRI->getMatchingSuperReg(Reg, AMDGPU::sub0,
Matt Arsenaultcdad3162016-11-29 19:39:48 +0000929 &AMDGPU::SGPR_64RegClass);
930 Reg = MF.addLiveIn(Reg, &AMDGPU::SGPR_64RegClass);
Matt Arsenaultcf13d182015-07-10 22:51:36 +0000931 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
932 InVals.push_back(Copy);
Christian Konig2c8f6d52013-03-07 09:03:52 +0000933 continue;
934 }
935
936 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg, VT);
937
938 Reg = MF.addLiveIn(Reg, RC);
939 SDValue Val = DAG.getCopyFromReg(Chain, DL, Reg, VT);
940
Christian Konig2c8f6d52013-03-07 09:03:52 +0000941 if (Arg.VT.isVector()) {
942
943 // Build a vector from the registers
Andrew Trick05938a52015-02-16 18:10:47 +0000944 Type *ParamType = FType->getParamType(Arg.getOrigArgIndex());
Christian Konig2c8f6d52013-03-07 09:03:52 +0000945 unsigned NumElements = ParamType->getVectorNumElements();
946
947 SmallVector<SDValue, 4> Regs;
948 Regs.push_back(Val);
949 for (unsigned j = 1; j != NumElements; ++j) {
950 Reg = ArgLocs[ArgIdx++].getLocReg();
951 Reg = MF.addLiveIn(Reg, RC);
Matt Arsenaultcf13d182015-07-10 22:51:36 +0000952
953 SDValue Copy = DAG.getCopyFromReg(Chain, DL, Reg, VT);
954 Regs.push_back(Copy);
Christian Konig2c8f6d52013-03-07 09:03:52 +0000955 }
956
957 // Fill up the missing vector elements
958 NumElements = Arg.VT.getVectorNumElements() - NumElements;
Benjamin Kramer6cd780f2015-02-17 15:29:18 +0000959 Regs.append(NumElements, DAG.getUNDEF(VT));
Matt Arsenault758659232013-05-18 00:21:46 +0000960
Ahmed Bougacha128f8732016-04-26 21:15:30 +0000961 InVals.push_back(DAG.getBuildVector(Arg.VT, DL, Regs));
Christian Konig2c8f6d52013-03-07 09:03:52 +0000962 continue;
963 }
964
965 InVals.push_back(Val);
966 }
Tom Stellarde99fb652015-01-20 19:33:04 +0000967
Matt Arsenault26f8f3d2015-11-30 21:16:03 +0000968 // TODO: Add GridWorkGroupCount user SGPRs when used. For now with HSA we read
969 // these from the dispatch pointer.
970
971 // Start adding system SGPRs.
972 if (Info->hasWorkGroupIDX()) {
973 unsigned Reg = Info->addWorkGroupIDX();
Marek Olsak79c05872016-11-25 17:37:09 +0000974 MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
Matt Arsenault26f8f3d2015-11-30 21:16:03 +0000975 CCInfo.AllocateReg(Reg);
Tom Stellardf110f8f2016-04-14 16:27:03 +0000976 }
Matt Arsenault26f8f3d2015-11-30 21:16:03 +0000977
978 if (Info->hasWorkGroupIDY()) {
979 unsigned Reg = Info->addWorkGroupIDY();
Marek Olsak79c05872016-11-25 17:37:09 +0000980 MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
Matt Arsenault26f8f3d2015-11-30 21:16:03 +0000981 CCInfo.AllocateReg(Reg);
Tom Stellarde99fb652015-01-20 19:33:04 +0000982 }
Matt Arsenaultcf13d182015-07-10 22:51:36 +0000983
Matt Arsenault26f8f3d2015-11-30 21:16:03 +0000984 if (Info->hasWorkGroupIDZ()) {
985 unsigned Reg = Info->addWorkGroupIDZ();
Marek Olsak79c05872016-11-25 17:37:09 +0000986 MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
Matt Arsenault26f8f3d2015-11-30 21:16:03 +0000987 CCInfo.AllocateReg(Reg);
988 }
989
990 if (Info->hasWorkGroupInfo()) {
991 unsigned Reg = Info->addWorkGroupInfo();
Marek Olsak79c05872016-11-25 17:37:09 +0000992 MF.addLiveIn(Reg, &AMDGPU::SReg_32_XM0RegClass);
Matt Arsenault26f8f3d2015-11-30 21:16:03 +0000993 CCInfo.AllocateReg(Reg);
994 }
995
996 if (Info->hasPrivateSegmentWaveByteOffset()) {
997 // Scratch wave offset passed in system SGPR.
Tom Stellardf110f8f2016-04-14 16:27:03 +0000998 unsigned PrivateSegmentWaveByteOffsetReg;
999
1000 if (AMDGPU::isShader(CallConv)) {
1001 PrivateSegmentWaveByteOffsetReg = findFirstFreeSGPR(CCInfo);
1002 Info->setPrivateSegmentWaveByteOffset(PrivateSegmentWaveByteOffsetReg);
1003 } else
1004 PrivateSegmentWaveByteOffsetReg = Info->addPrivateSegmentWaveByteOffset();
Matt Arsenault26f8f3d2015-11-30 21:16:03 +00001005
1006 MF.addLiveIn(PrivateSegmentWaveByteOffsetReg, &AMDGPU::SGPR_32RegClass);
1007 CCInfo.AllocateReg(PrivateSegmentWaveByteOffsetReg);
1008 }
1009
1010 // Now that we've figured out where the scratch register inputs are, see if
1011 // should reserve the arguments and use them directly.
Matthias Braun941a7052016-07-28 18:40:00 +00001012 bool HasStackObjects = MF.getFrameInfo().hasStackObjects();
Matt Arsenault296b8492016-02-12 06:31:30 +00001013 // Record that we know we have non-spill stack objects so we don't need to
1014 // check all stack objects later.
1015 if (HasStackObjects)
1016 Info->setHasNonSpillStackObjects(true);
Matt Arsenault26f8f3d2015-11-30 21:16:03 +00001017
Matt Arsenault253640e2016-10-13 13:10:00 +00001018 // Everything live out of a block is spilled with fast regalloc, so it's
1019 // almost certain that spilling will be required.
1020 if (getTargetMachine().getOptLevel() == CodeGenOpt::None)
1021 HasStackObjects = true;
1022
Tom Stellard0b76fc4c2016-09-16 21:34:26 +00001023 if (ST.isAmdCodeObjectV2()) {
Matt Arsenault26f8f3d2015-11-30 21:16:03 +00001024 if (HasStackObjects) {
1025 // If we have stack objects, we unquestionably need the private buffer
Tom Stellard0b76fc4c2016-09-16 21:34:26 +00001026 // resource. For the Code Object V2 ABI, this will be the first 4 user
1027 // SGPR inputs. We can reserve those and use them directly.
Matt Arsenault26f8f3d2015-11-30 21:16:03 +00001028
1029 unsigned PrivateSegmentBufferReg = TRI->getPreloadedValue(
1030 MF, SIRegisterInfo::PRIVATE_SEGMENT_BUFFER);
1031 Info->setScratchRSrcReg(PrivateSegmentBufferReg);
1032
1033 unsigned PrivateSegmentWaveByteOffsetReg = TRI->getPreloadedValue(
1034 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
1035 Info->setScratchWaveOffsetReg(PrivateSegmentWaveByteOffsetReg);
1036 } else {
1037 unsigned ReservedBufferReg
1038 = TRI->reservedPrivateSegmentBufferReg(MF);
1039 unsigned ReservedOffsetReg
1040 = TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
1041
1042 // We tentatively reserve the last registers (skipping the last two
1043 // which may contain VCC). After register allocation, we'll replace
1044 // these with the ones immediately after those which were really
1045 // allocated. In the prologue copies will be inserted from the argument
1046 // to these reserved registers.
1047 Info->setScratchRSrcReg(ReservedBufferReg);
1048 Info->setScratchWaveOffsetReg(ReservedOffsetReg);
1049 }
1050 } else {
1051 unsigned ReservedBufferReg = TRI->reservedPrivateSegmentBufferReg(MF);
1052
1053 // Without HSA, relocations are used for the scratch pointer and the
1054 // buffer resource setup is always inserted in the prologue. Scratch wave
1055 // offset is still in an input SGPR.
1056 Info->setScratchRSrcReg(ReservedBufferReg);
1057
1058 if (HasStackObjects) {
1059 unsigned ScratchWaveOffsetReg = TRI->getPreloadedValue(
1060 MF, SIRegisterInfo::PRIVATE_SEGMENT_WAVE_BYTE_OFFSET);
1061 Info->setScratchWaveOffsetReg(ScratchWaveOffsetReg);
1062 } else {
1063 unsigned ReservedOffsetReg
1064 = TRI->reservedPrivateSegmentWaveByteOffsetReg(MF);
1065 Info->setScratchWaveOffsetReg(ReservedOffsetReg);
1066 }
1067 }
1068
1069 if (Info->hasWorkItemIDX()) {
1070 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X);
1071 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1072 CCInfo.AllocateReg(Reg);
Tom Stellardf110f8f2016-04-14 16:27:03 +00001073 }
Matt Arsenault26f8f3d2015-11-30 21:16:03 +00001074
1075 if (Info->hasWorkItemIDY()) {
1076 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y);
1077 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1078 CCInfo.AllocateReg(Reg);
1079 }
1080
1081 if (Info->hasWorkItemIDZ()) {
1082 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z);
1083 MF.addLiveIn(Reg, &AMDGPU::VGPR_32RegClass);
1084 CCInfo.AllocateReg(Reg);
1085 }
Matt Arsenault0e3d3892015-11-30 21:15:53 +00001086
Matt Arsenaultcf13d182015-07-10 22:51:36 +00001087 if (Chains.empty())
1088 return Chain;
1089
1090 return DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Chains);
Christian Konig2c8f6d52013-03-07 09:03:52 +00001091}
1092
Benjamin Kramerbdc49562016-06-12 15:39:02 +00001093SDValue
1094SITargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
1095 bool isVarArg,
1096 const SmallVectorImpl<ISD::OutputArg> &Outs,
1097 const SmallVectorImpl<SDValue> &OutVals,
1098 const SDLoc &DL, SelectionDAG &DAG) const {
Marek Olsak8a0f3352016-01-13 17:23:04 +00001099 MachineFunction &MF = DAG.getMachineFunction();
1100 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1101
Nicolai Haehnledf3a20c2016-04-06 19:40:20 +00001102 if (!AMDGPU::isShader(CallConv))
Marek Olsak8a0f3352016-01-13 17:23:04 +00001103 return AMDGPUTargetLowering::LowerReturn(Chain, CallConv, isVarArg, Outs,
1104 OutVals, DL, DAG);
1105
Marek Olsak8e9cc632016-01-13 17:23:09 +00001106 Info->setIfReturnsVoid(Outs.size() == 0);
1107
Marek Olsak8a0f3352016-01-13 17:23:04 +00001108 SmallVector<ISD::OutputArg, 48> Splits;
1109 SmallVector<SDValue, 48> SplitVals;
1110
1111 // Split vectors into their elements.
1112 for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
1113 const ISD::OutputArg &Out = Outs[i];
1114
1115 if (Out.VT.isVector()) {
1116 MVT VT = Out.VT.getVectorElementType();
1117 ISD::OutputArg NewOut = Out;
1118 NewOut.Flags.setSplit();
1119 NewOut.VT = VT;
1120
1121 // We want the original number of vector elements here, e.g.
1122 // three or five, not four or eight.
1123 unsigned NumElements = Out.ArgVT.getVectorNumElements();
1124
1125 for (unsigned j = 0; j != NumElements; ++j) {
1126 SDValue Elem = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, VT, OutVals[i],
1127 DAG.getConstant(j, DL, MVT::i32));
1128 SplitVals.push_back(Elem);
1129 Splits.push_back(NewOut);
1130 NewOut.PartOffset += NewOut.VT.getStoreSize();
1131 }
1132 } else {
1133 SplitVals.push_back(OutVals[i]);
1134 Splits.push_back(Out);
1135 }
1136 }
1137
1138 // CCValAssign - represent the assignment of the return value to a location.
1139 SmallVector<CCValAssign, 48> RVLocs;
1140
1141 // CCState - Info about the registers and stack slots.
1142 CCState CCInfo(CallConv, isVarArg, DAG.getMachineFunction(), RVLocs,
1143 *DAG.getContext());
1144
1145 // Analyze outgoing return values.
1146 AnalyzeReturn(CCInfo, Splits);
1147
1148 SDValue Flag;
1149 SmallVector<SDValue, 48> RetOps;
1150 RetOps.push_back(Chain); // Operand #0 = Chain (updated below)
1151
1152 // Copy the result values into the output registers.
1153 for (unsigned i = 0, realRVLocIdx = 0;
1154 i != RVLocs.size();
1155 ++i, ++realRVLocIdx) {
1156 CCValAssign &VA = RVLocs[i];
1157 assert(VA.isRegLoc() && "Can only return in registers!");
1158
1159 SDValue Arg = SplitVals[realRVLocIdx];
1160
1161 // Copied from other backends.
1162 switch (VA.getLocInfo()) {
1163 default: llvm_unreachable("Unknown loc info!");
1164 case CCValAssign::Full:
1165 break;
1166 case CCValAssign::BCvt:
1167 Arg = DAG.getNode(ISD::BITCAST, DL, VA.getLocVT(), Arg);
1168 break;
1169 }
1170
1171 Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Arg, Flag);
1172 Flag = Chain.getValue(1);
1173 RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
1174 }
1175
1176 // Update chain and glue.
1177 RetOps[0] = Chain;
1178 if (Flag.getNode())
1179 RetOps.push_back(Flag);
1180
Matt Arsenault9babdf42016-06-22 20:15:28 +00001181 unsigned Opc = Info->returnsVoid() ? AMDGPUISD::ENDPGM : AMDGPUISD::RETURN;
1182 return DAG.getNode(Opc, DL, MVT::Other, RetOps);
Marek Olsak8a0f3352016-01-13 17:23:04 +00001183}
1184
Matt Arsenault9a10cea2016-01-26 04:29:24 +00001185unsigned SITargetLowering::getRegisterByName(const char* RegName, EVT VT,
1186 SelectionDAG &DAG) const {
1187 unsigned Reg = StringSwitch<unsigned>(RegName)
1188 .Case("m0", AMDGPU::M0)
1189 .Case("exec", AMDGPU::EXEC)
1190 .Case("exec_lo", AMDGPU::EXEC_LO)
1191 .Case("exec_hi", AMDGPU::EXEC_HI)
1192 .Case("flat_scratch", AMDGPU::FLAT_SCR)
1193 .Case("flat_scratch_lo", AMDGPU::FLAT_SCR_LO)
1194 .Case("flat_scratch_hi", AMDGPU::FLAT_SCR_HI)
1195 .Default(AMDGPU::NoRegister);
1196
1197 if (Reg == AMDGPU::NoRegister) {
1198 report_fatal_error(Twine("invalid register name \""
1199 + StringRef(RegName) + "\"."));
1200
1201 }
1202
Matt Arsenault43e92fe2016-06-24 06:30:11 +00001203 if (Subtarget->getGeneration() == SISubtarget::SOUTHERN_ISLANDS &&
Matt Arsenault9a10cea2016-01-26 04:29:24 +00001204 Subtarget->getRegisterInfo()->regsOverlap(Reg, AMDGPU::FLAT_SCR)) {
1205 report_fatal_error(Twine("invalid register \""
1206 + StringRef(RegName) + "\" for subtarget."));
1207 }
1208
1209 switch (Reg) {
1210 case AMDGPU::M0:
1211 case AMDGPU::EXEC_LO:
1212 case AMDGPU::EXEC_HI:
1213 case AMDGPU::FLAT_SCR_LO:
1214 case AMDGPU::FLAT_SCR_HI:
1215 if (VT.getSizeInBits() == 32)
1216 return Reg;
1217 break;
1218 case AMDGPU::EXEC:
1219 case AMDGPU::FLAT_SCR:
1220 if (VT.getSizeInBits() == 64)
1221 return Reg;
1222 break;
1223 default:
1224 llvm_unreachable("missing register type checking");
1225 }
1226
1227 report_fatal_error(Twine("invalid type for register \""
1228 + StringRef(RegName) + "\"."));
1229}
1230
Matt Arsenault786724a2016-07-12 21:41:32 +00001231// If kill is not the last instruction, split the block so kill is always a
1232// proper terminator.
1233MachineBasicBlock *SITargetLowering::splitKillBlock(MachineInstr &MI,
1234 MachineBasicBlock *BB) const {
1235 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
1236
1237 MachineBasicBlock::iterator SplitPoint(&MI);
1238 ++SplitPoint;
1239
1240 if (SplitPoint == BB->end()) {
1241 // Don't bother with a new block.
1242 MI.setDesc(TII->get(AMDGPU::SI_KILL_TERMINATOR));
1243 return BB;
1244 }
1245
1246 MachineFunction *MF = BB->getParent();
1247 MachineBasicBlock *SplitBB
1248 = MF->CreateMachineBasicBlock(BB->getBasicBlock());
1249
Matt Arsenault786724a2016-07-12 21:41:32 +00001250 MF->insert(++MachineFunction::iterator(BB), SplitBB);
1251 SplitBB->splice(SplitBB->begin(), BB, SplitPoint, BB->end());
1252
Matt Arsenaultd40ded62016-07-22 17:01:15 +00001253 SplitBB->transferSuccessorsAndUpdatePHIs(BB);
Matt Arsenault786724a2016-07-12 21:41:32 +00001254 BB->addSuccessor(SplitBB);
1255
1256 MI.setDesc(TII->get(AMDGPU::SI_KILL_TERMINATOR));
1257 return SplitBB;
1258}
1259
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001260// Do a v_movrels_b32 or v_movreld_b32 for each unique value of \p IdxReg in the
1261// wavefront. If the value is uniform and just happens to be in a VGPR, this
1262// will only do one iteration. In the worst case, this will loop 64 times.
1263//
1264// TODO: Just use v_readlane_b32 if we know the VGPR has a uniform value.
Matt Arsenaultdcf0cfc2016-10-04 01:41:05 +00001265static MachineBasicBlock::iterator emitLoadM0FromVGPRLoop(
1266 const SIInstrInfo *TII,
1267 MachineRegisterInfo &MRI,
1268 MachineBasicBlock &OrigBB,
1269 MachineBasicBlock &LoopBB,
1270 const DebugLoc &DL,
1271 const MachineOperand &IdxReg,
1272 unsigned InitReg,
1273 unsigned ResultReg,
1274 unsigned PhiReg,
1275 unsigned InitSaveExecReg,
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001276 int Offset,
1277 bool UseGPRIdxMode) {
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001278 MachineBasicBlock::iterator I = LoopBB.begin();
1279
1280 unsigned PhiExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1281 unsigned NewExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1282 unsigned CurrentIdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1283 unsigned CondReg = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1284
1285 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiReg)
1286 .addReg(InitReg)
1287 .addMBB(&OrigBB)
1288 .addReg(ResultReg)
1289 .addMBB(&LoopBB);
1290
1291 BuildMI(LoopBB, I, DL, TII->get(TargetOpcode::PHI), PhiExec)
1292 .addReg(InitSaveExecReg)
1293 .addMBB(&OrigBB)
1294 .addReg(NewExec)
1295 .addMBB(&LoopBB);
1296
1297 // Read the next variant <- also loop target.
1298 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_READFIRSTLANE_B32), CurrentIdxReg)
1299 .addReg(IdxReg.getReg(), getUndefRegState(IdxReg.isUndef()));
1300
1301 // Compare the just read M0 value to all possible Idx values.
1302 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::V_CMP_EQ_U32_e64), CondReg)
1303 .addReg(CurrentIdxReg)
Matt Arsenaultf0ba86a2016-07-21 09:40:57 +00001304 .addReg(IdxReg.getReg(), 0, IdxReg.getSubReg());
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001305
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001306 if (UseGPRIdxMode) {
1307 unsigned IdxReg;
1308 if (Offset == 0) {
1309 IdxReg = CurrentIdxReg;
1310 } else {
1311 IdxReg = MRI.createVirtualRegister(&AMDGPU::SGPR_32RegClass);
1312 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), IdxReg)
1313 .addReg(CurrentIdxReg, RegState::Kill)
1314 .addImm(Offset);
1315 }
1316
1317 MachineInstr *SetIdx =
1318 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_IDX))
1319 .addReg(IdxReg, RegState::Kill);
Matt Arsenaultdac31db2016-10-13 12:45:16 +00001320 SetIdx->getOperand(2).setIsUndef();
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001321 } else {
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001322 // Move index from VCC into M0
1323 if (Offset == 0) {
1324 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
1325 .addReg(CurrentIdxReg, RegState::Kill);
1326 } else {
1327 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
1328 .addReg(CurrentIdxReg, RegState::Kill)
1329 .addImm(Offset);
1330 }
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001331 }
1332
1333 // Update EXEC, save the original EXEC value to VCC.
1334 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), NewExec)
1335 .addReg(CondReg, RegState::Kill);
1336
1337 MRI.setSimpleHint(NewExec, CondReg);
1338
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001339 // Update EXEC, switch all done bits to 0 and all todo bits to 1.
Matt Arsenaultdcf0cfc2016-10-04 01:41:05 +00001340 MachineInstr *InsertPt =
1341 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_XOR_B64), AMDGPU::EXEC)
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001342 .addReg(AMDGPU::EXEC)
1343 .addReg(NewExec);
1344
1345 // XXX - s_xor_b64 sets scc to 1 if the result is nonzero, so can we use
1346 // s_cbranch_scc0?
1347
1348 // Loop back to V_READFIRSTLANE_B32 if there are still variants to cover.
1349 BuildMI(LoopBB, I, DL, TII->get(AMDGPU::S_CBRANCH_EXECNZ))
1350 .addMBB(&LoopBB);
Matt Arsenaultdcf0cfc2016-10-04 01:41:05 +00001351
1352 return InsertPt->getIterator();
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001353}
1354
1355// This has slightly sub-optimal regalloc when the source vector is killed by
1356// the read. The register allocator does not understand that the kill is
1357// per-workitem, so is kept alive for the whole loop so we end up not re-using a
1358// subregister from it, using 1 more VGPR than necessary. This was saved when
1359// this was expanded after register allocation.
Matt Arsenaultdcf0cfc2016-10-04 01:41:05 +00001360static MachineBasicBlock::iterator loadM0FromVGPR(const SIInstrInfo *TII,
1361 MachineBasicBlock &MBB,
1362 MachineInstr &MI,
1363 unsigned InitResultReg,
1364 unsigned PhiReg,
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001365 int Offset,
1366 bool UseGPRIdxMode) {
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001367 MachineFunction *MF = MBB.getParent();
1368 MachineRegisterInfo &MRI = MF->getRegInfo();
1369 const DebugLoc &DL = MI.getDebugLoc();
1370 MachineBasicBlock::iterator I(&MI);
1371
1372 unsigned DstReg = MI.getOperand(0).getReg();
1373 unsigned SaveExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1374 unsigned TmpExec = MRI.createVirtualRegister(&AMDGPU::SReg_64RegClass);
1375
1376 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), TmpExec);
1377
1378 // Save the EXEC mask
1379 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_MOV_B64), SaveExec)
1380 .addReg(AMDGPU::EXEC);
1381
1382 // To insert the loop we need to split the block. Move everything after this
1383 // point to a new block, and insert a new empty block between the two.
1384 MachineBasicBlock *LoopBB = MF->CreateMachineBasicBlock();
1385 MachineBasicBlock *RemainderBB = MF->CreateMachineBasicBlock();
1386 MachineFunction::iterator MBBI(MBB);
1387 ++MBBI;
1388
1389 MF->insert(MBBI, LoopBB);
1390 MF->insert(MBBI, RemainderBB);
1391
1392 LoopBB->addSuccessor(LoopBB);
1393 LoopBB->addSuccessor(RemainderBB);
1394
1395 // Move the rest of the block into a new block.
Matt Arsenaultd40ded62016-07-22 17:01:15 +00001396 RemainderBB->transferSuccessorsAndUpdatePHIs(&MBB);
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001397 RemainderBB->splice(RemainderBB->begin(), &MBB, I, MBB.end());
1398
1399 MBB.addSuccessor(LoopBB);
1400
1401 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
1402
Matt Arsenaultdcf0cfc2016-10-04 01:41:05 +00001403 auto InsPt = emitLoadM0FromVGPRLoop(TII, MRI, MBB, *LoopBB, DL, *Idx,
1404 InitResultReg, DstReg, PhiReg, TmpExec,
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001405 Offset, UseGPRIdxMode);
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001406
1407 MachineBasicBlock::iterator First = RemainderBB->begin();
1408 BuildMI(*RemainderBB, First, DL, TII->get(AMDGPU::S_MOV_B64), AMDGPU::EXEC)
1409 .addReg(SaveExec);
1410
Matt Arsenaultdcf0cfc2016-10-04 01:41:05 +00001411 return InsPt;
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001412}
1413
1414// Returns subreg index, offset
1415static std::pair<unsigned, int>
1416computeIndirectRegAndOffset(const SIRegisterInfo &TRI,
1417 const TargetRegisterClass *SuperRC,
1418 unsigned VecReg,
1419 int Offset) {
1420 int NumElts = SuperRC->getSize() / 4;
1421
1422 // Skip out of bounds offsets, or else we would end up using an undefined
1423 // register.
1424 if (Offset >= NumElts || Offset < 0)
1425 return std::make_pair(AMDGPU::sub0, Offset);
1426
1427 return std::make_pair(AMDGPU::sub0 + Offset, 0);
1428}
1429
1430// Return true if the index is an SGPR and was set.
1431static bool setM0ToIndexFromSGPR(const SIInstrInfo *TII,
1432 MachineRegisterInfo &MRI,
1433 MachineInstr &MI,
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001434 int Offset,
1435 bool UseGPRIdxMode,
1436 bool IsIndirectSrc) {
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001437 MachineBasicBlock *MBB = MI.getParent();
1438 const DebugLoc &DL = MI.getDebugLoc();
1439 MachineBasicBlock::iterator I(&MI);
1440
1441 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
1442 const TargetRegisterClass *IdxRC = MRI.getRegClass(Idx->getReg());
1443
1444 assert(Idx->getReg() != AMDGPU::NoRegister);
1445
1446 if (!TII->getRegisterInfo().isSGPRClass(IdxRC))
1447 return false;
1448
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001449 if (UseGPRIdxMode) {
1450 unsigned IdxMode = IsIndirectSrc ?
1451 VGPRIndexMode::SRC0_ENABLE : VGPRIndexMode::DST_ENABLE;
1452 if (Offset == 0) {
1453 MachineInstr *SetOn =
1454 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
1455 .addOperand(*Idx)
1456 .addImm(IdxMode);
1457
Matt Arsenaultdac31db2016-10-13 12:45:16 +00001458 SetOn->getOperand(3).setIsUndef();
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001459 } else {
1460 unsigned Tmp = MRI.createVirtualRegister(&AMDGPU::SReg_32_XM0RegClass);
1461 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), Tmp)
1462 .addOperand(*Idx)
1463 .addImm(Offset);
1464 MachineInstr *SetOn =
1465 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
1466 .addReg(Tmp, RegState::Kill)
1467 .addImm(IdxMode);
1468
Matt Arsenaultdac31db2016-10-13 12:45:16 +00001469 SetOn->getOperand(3).setIsUndef();
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001470 }
1471
1472 return true;
1473 }
1474
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001475 if (Offset == 0) {
1476 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
1477 .addOperand(*Idx);
1478 } else {
1479 BuildMI(*MBB, I, DL, TII->get(AMDGPU::S_ADD_I32), AMDGPU::M0)
1480 .addOperand(*Idx)
1481 .addImm(Offset);
1482 }
1483
1484 return true;
1485}
1486
1487// Control flow needs to be inserted if indexing with a VGPR.
1488static MachineBasicBlock *emitIndirectSrc(MachineInstr &MI,
1489 MachineBasicBlock &MBB,
Matt Arsenaultdcf0cfc2016-10-04 01:41:05 +00001490 const SISubtarget &ST) {
1491 const SIInstrInfo *TII = ST.getInstrInfo();
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001492 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1493 MachineFunction *MF = MBB.getParent();
1494 MachineRegisterInfo &MRI = MF->getRegInfo();
1495
1496 unsigned Dst = MI.getOperand(0).getReg();
Nicolai Haehnlebd15c322016-10-14 09:03:04 +00001497 unsigned SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg();
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001498 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
1499
Nicolai Haehnlebd15c322016-10-14 09:03:04 +00001500 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg);
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001501
1502 unsigned SubReg;
1503 std::tie(SubReg, Offset)
Nicolai Haehnlebd15c322016-10-14 09:03:04 +00001504 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset);
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001505
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001506 bool UseGPRIdxMode = ST.hasVGPRIndexMode() && EnableVGPRIndexMode;
1507
1508 if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, true)) {
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001509 MachineBasicBlock::iterator I(&MI);
1510 const DebugLoc &DL = MI.getDebugLoc();
1511
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001512 if (UseGPRIdxMode) {
1513 // TODO: Look at the uses to avoid the copy. This may require rescheduling
1514 // to avoid interfering with other uses, so probably requires a new
1515 // optimization pass.
1516 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
Nicolai Haehnlebd15c322016-10-14 09:03:04 +00001517 .addReg(SrcReg, RegState::Undef, SubReg)
1518 .addReg(SrcReg, RegState::Implicit)
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001519 .addReg(AMDGPU::M0, RegState::Implicit);
1520 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
1521 } else {
1522 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
Nicolai Haehnlebd15c322016-10-14 09:03:04 +00001523 .addReg(SrcReg, RegState::Undef, SubReg)
1524 .addReg(SrcReg, RegState::Implicit);
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001525 }
1526
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001527 MI.eraseFromParent();
1528
1529 return &MBB;
1530 }
1531
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001532
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001533 const DebugLoc &DL = MI.getDebugLoc();
1534 MachineBasicBlock::iterator I(&MI);
1535
1536 unsigned PhiReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1537 unsigned InitReg = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1538
1539 BuildMI(MBB, I, DL, TII->get(TargetOpcode::IMPLICIT_DEF), InitReg);
1540
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001541 if (UseGPRIdxMode) {
1542 MachineInstr *SetOn = BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
1543 .addImm(0) // Reset inside loop.
1544 .addImm(VGPRIndexMode::SRC0_ENABLE);
Matt Arsenaultdac31db2016-10-13 12:45:16 +00001545 SetOn->getOperand(3).setIsUndef();
Matt Arsenaultdcf0cfc2016-10-04 01:41:05 +00001546
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001547 // Disable again after the loop.
1548 BuildMI(MBB, std::next(I), DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
1549 }
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001550
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001551 auto InsPt = loadM0FromVGPR(TII, MBB, MI, InitReg, PhiReg, Offset, UseGPRIdxMode);
1552 MachineBasicBlock *LoopBB = InsPt->getParent();
1553
1554 if (UseGPRIdxMode) {
1555 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_e32), Dst)
Nicolai Haehnlebd15c322016-10-14 09:03:04 +00001556 .addReg(SrcReg, RegState::Undef, SubReg)
1557 .addReg(SrcReg, RegState::Implicit)
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001558 .addReg(AMDGPU::M0, RegState::Implicit);
1559 } else {
1560 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOVRELS_B32_e32), Dst)
Nicolai Haehnlebd15c322016-10-14 09:03:04 +00001561 .addReg(SrcReg, RegState::Undef, SubReg)
1562 .addReg(SrcReg, RegState::Implicit);
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001563 }
1564
Nicolai Haehnlebd15c322016-10-14 09:03:04 +00001565 MI.eraseFromParent();
1566
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001567 return LoopBB;
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001568}
1569
Nicolai Haehnlea7852092016-10-24 14:56:02 +00001570static unsigned getMOVRELDPseudo(const TargetRegisterClass *VecRC) {
1571 switch (VecRC->getSize()) {
1572 case 4:
1573 return AMDGPU::V_MOVRELD_B32_V1;
1574 case 8:
1575 return AMDGPU::V_MOVRELD_B32_V2;
1576 case 16:
1577 return AMDGPU::V_MOVRELD_B32_V4;
1578 case 32:
1579 return AMDGPU::V_MOVRELD_B32_V8;
1580 case 64:
1581 return AMDGPU::V_MOVRELD_B32_V16;
1582 default:
1583 llvm_unreachable("unsupported size for MOVRELD pseudos");
1584 }
1585}
1586
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001587static MachineBasicBlock *emitIndirectDst(MachineInstr &MI,
1588 MachineBasicBlock &MBB,
Matt Arsenaultdcf0cfc2016-10-04 01:41:05 +00001589 const SISubtarget &ST) {
1590 const SIInstrInfo *TII = ST.getInstrInfo();
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001591 const SIRegisterInfo &TRI = TII->getRegisterInfo();
1592 MachineFunction *MF = MBB.getParent();
1593 MachineRegisterInfo &MRI = MF->getRegInfo();
1594
1595 unsigned Dst = MI.getOperand(0).getReg();
1596 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src);
1597 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx);
1598 const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val);
1599 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm();
1600 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg());
1601
1602 // This can be an immediate, but will be folded later.
1603 assert(Val->getReg());
1604
1605 unsigned SubReg;
1606 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC,
1607 SrcVec->getReg(),
1608 Offset);
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001609 bool UseGPRIdxMode = ST.hasVGPRIndexMode() && EnableVGPRIndexMode;
1610
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001611 if (Idx->getReg() == AMDGPU::NoRegister) {
1612 MachineBasicBlock::iterator I(&MI);
1613 const DebugLoc &DL = MI.getDebugLoc();
1614
1615 assert(Offset == 0);
1616
1617 BuildMI(MBB, I, DL, TII->get(TargetOpcode::INSERT_SUBREG), Dst)
1618 .addOperand(*SrcVec)
1619 .addOperand(*Val)
1620 .addImm(SubReg);
1621
1622 MI.eraseFromParent();
1623 return &MBB;
1624 }
1625
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001626 if (setM0ToIndexFromSGPR(TII, MRI, MI, Offset, UseGPRIdxMode, false)) {
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001627 MachineBasicBlock::iterator I(&MI);
1628 const DebugLoc &DL = MI.getDebugLoc();
1629
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001630 if (UseGPRIdxMode) {
1631 BuildMI(MBB, I, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
1632 .addReg(SrcVec->getReg(), RegState::Undef, SubReg) // vdst
1633 .addOperand(*Val)
1634 .addReg(Dst, RegState::ImplicitDefine)
1635 .addReg(SrcVec->getReg(), RegState::Implicit)
1636 .addReg(AMDGPU::M0, RegState::Implicit);
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001637
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001638 BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
1639 } else {
Nicolai Haehnlea7852092016-10-24 14:56:02 +00001640 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(VecRC));
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001641
Nicolai Haehnlea7852092016-10-24 14:56:02 +00001642 BuildMI(MBB, I, DL, MovRelDesc)
1643 .addReg(Dst, RegState::Define)
1644 .addReg(SrcVec->getReg())
1645 .addOperand(*Val)
1646 .addImm(SubReg - AMDGPU::sub0);
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001647 }
1648
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001649 MI.eraseFromParent();
1650 return &MBB;
1651 }
1652
1653 if (Val->isReg())
1654 MRI.clearKillFlags(Val->getReg());
1655
1656 const DebugLoc &DL = MI.getDebugLoc();
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001657
1658 if (UseGPRIdxMode) {
1659 MachineBasicBlock::iterator I(&MI);
1660
1661 MachineInstr *SetOn = BuildMI(MBB, I, DL, TII->get(AMDGPU::S_SET_GPR_IDX_ON))
1662 .addImm(0) // Reset inside loop.
1663 .addImm(VGPRIndexMode::DST_ENABLE);
Matt Arsenaultdac31db2016-10-13 12:45:16 +00001664 SetOn->getOperand(3).setIsUndef();
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001665
1666 // Disable again after the loop.
1667 BuildMI(MBB, std::next(I), DL, TII->get(AMDGPU::S_SET_GPR_IDX_OFF));
1668 }
1669
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001670 unsigned PhiReg = MRI.createVirtualRegister(VecRC);
1671
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001672 auto InsPt = loadM0FromVGPR(TII, MBB, MI, SrcVec->getReg(), PhiReg,
1673 Offset, UseGPRIdxMode);
1674 MachineBasicBlock *LoopBB = InsPt->getParent();
Matt Arsenaultdcf0cfc2016-10-04 01:41:05 +00001675
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001676 if (UseGPRIdxMode) {
1677 BuildMI(*LoopBB, InsPt, DL, TII->get(AMDGPU::V_MOV_B32_indirect))
1678 .addReg(PhiReg, RegState::Undef, SubReg) // vdst
1679 .addOperand(*Val) // src0
1680 .addReg(Dst, RegState::ImplicitDefine)
1681 .addReg(PhiReg, RegState::Implicit)
1682 .addReg(AMDGPU::M0, RegState::Implicit);
1683 } else {
Nicolai Haehnlea7852092016-10-24 14:56:02 +00001684 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(VecRC));
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001685
Nicolai Haehnlea7852092016-10-24 14:56:02 +00001686 BuildMI(*LoopBB, InsPt, DL, MovRelDesc)
1687 .addReg(Dst, RegState::Define)
1688 .addReg(PhiReg)
1689 .addOperand(*Val)
1690 .addImm(SubReg - AMDGPU::sub0);
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001691 }
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001692
Nicolai Haehnlebd15c322016-10-14 09:03:04 +00001693 MI.eraseFromParent();
1694
Matt Arsenaultd486d3f2016-10-12 18:49:05 +00001695 return LoopBB;
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001696}
1697
Matt Arsenault786724a2016-07-12 21:41:32 +00001698MachineBasicBlock *SITargetLowering::EmitInstrWithCustomInserter(
1699 MachineInstr &MI, MachineBasicBlock *BB) const {
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00001700 switch (MI.getOpcode()) {
Matt Arsenault4ac341c2016-04-14 21:58:15 +00001701 case AMDGPU::SI_INIT_M0: {
Matt Arsenault43e92fe2016-06-24 06:30:11 +00001702 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00001703 BuildMI(*BB, MI.getIterator(), MI.getDebugLoc(),
Matt Arsenault4ac341c2016-04-14 21:58:15 +00001704 TII->get(AMDGPU::S_MOV_B32), AMDGPU::M0)
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001705 .addOperand(MI.getOperand(0));
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00001706 MI.eraseFromParent();
Matt Arsenault20711b72015-02-20 22:10:45 +00001707 return BB;
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001708 }
Changpeng Fang01f60622016-03-15 17:28:44 +00001709 case AMDGPU::GET_GROUPSTATICSIZE: {
Matt Arsenault43e92fe2016-06-24 06:30:11 +00001710 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
1711
Changpeng Fang01f60622016-03-15 17:28:44 +00001712 MachineFunction *MF = BB->getParent();
1713 SIMachineFunctionInfo *MFI = MF->getInfo<SIMachineFunctionInfo>();
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00001714 DebugLoc DL = MI.getDebugLoc();
Matt Arsenault3c07c812016-07-22 17:01:33 +00001715 BuildMI(*BB, MI, DL, TII->get(AMDGPU::S_MOV_B32))
1716 .addOperand(MI.getOperand(0))
Matt Arsenault52ef4012016-07-26 16:45:58 +00001717 .addImm(MFI->getLDSSize());
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00001718 MI.eraseFromParent();
Changpeng Fang01f60622016-03-15 17:28:44 +00001719 return BB;
1720 }
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001721 case AMDGPU::SI_INDIRECT_SRC_V1:
1722 case AMDGPU::SI_INDIRECT_SRC_V2:
1723 case AMDGPU::SI_INDIRECT_SRC_V4:
1724 case AMDGPU::SI_INDIRECT_SRC_V8:
1725 case AMDGPU::SI_INDIRECT_SRC_V16:
Matt Arsenaultdcf0cfc2016-10-04 01:41:05 +00001726 return emitIndirectSrc(MI, *BB, *getSubtarget());
Matt Arsenaultcb540bc2016-07-19 00:35:03 +00001727 case AMDGPU::SI_INDIRECT_DST_V1:
1728 case AMDGPU::SI_INDIRECT_DST_V2:
1729 case AMDGPU::SI_INDIRECT_DST_V4:
1730 case AMDGPU::SI_INDIRECT_DST_V8:
1731 case AMDGPU::SI_INDIRECT_DST_V16:
Matt Arsenaultdcf0cfc2016-10-04 01:41:05 +00001732 return emitIndirectDst(MI, *BB, *getSubtarget());
Matt Arsenault786724a2016-07-12 21:41:32 +00001733 case AMDGPU::SI_KILL:
1734 return splitKillBlock(MI, BB);
Matt Arsenault22e41792016-08-27 01:00:37 +00001735 case AMDGPU::V_CNDMASK_B64_PSEUDO: {
1736 MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
1737 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
1738
1739 unsigned Dst = MI.getOperand(0).getReg();
1740 unsigned Src0 = MI.getOperand(1).getReg();
1741 unsigned Src1 = MI.getOperand(2).getReg();
1742 const DebugLoc &DL = MI.getDebugLoc();
1743 unsigned SrcCond = MI.getOperand(3).getReg();
1744
1745 unsigned DstLo = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1746 unsigned DstHi = MRI.createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1747
1748 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstLo)
1749 .addReg(Src0, 0, AMDGPU::sub0)
1750 .addReg(Src1, 0, AMDGPU::sub0)
1751 .addReg(SrcCond);
1752 BuildMI(*BB, MI, DL, TII->get(AMDGPU::V_CNDMASK_B32_e64), DstHi)
1753 .addReg(Src0, 0, AMDGPU::sub1)
1754 .addReg(Src1, 0, AMDGPU::sub1)
1755 .addReg(SrcCond);
1756
1757 BuildMI(*BB, MI, DL, TII->get(AMDGPU::REG_SEQUENCE), Dst)
1758 .addReg(DstLo)
1759 .addImm(AMDGPU::sub0)
1760 .addReg(DstHi)
1761 .addImm(AMDGPU::sub1);
1762 MI.eraseFromParent();
1763 return BB;
1764 }
Changpeng Fang01f60622016-03-15 17:28:44 +00001765 default:
1766 return AMDGPUTargetLowering::EmitInstrWithCustomInserter(MI, BB);
Tom Stellard75aadc22012-12-11 21:25:42 +00001767 }
Tom Stellard75aadc22012-12-11 21:25:42 +00001768}
1769
Matt Arsenault423bf3f2015-01-29 19:34:32 +00001770bool SITargetLowering::enableAggressiveFMAFusion(EVT VT) const {
1771 // This currently forces unfolding various combinations of fsub into fma with
1772 // free fneg'd operands. As long as we have fast FMA (controlled by
1773 // isFMAFasterThanFMulAndFAdd), we should perform these.
1774
1775 // When fma is quarter rate, for f64 where add / sub are at best half rate,
1776 // most of these combines appear to be cycle neutral but save on instruction
1777 // count / code size.
1778 return true;
1779}
1780
Mehdi Amini44ede332015-07-09 02:09:04 +00001781EVT SITargetLowering::getSetCCResultType(const DataLayout &DL, LLVMContext &Ctx,
1782 EVT VT) const {
Tom Stellard83747202013-07-18 21:43:53 +00001783 if (!VT.isVector()) {
1784 return MVT::i1;
1785 }
Matt Arsenault8596f712014-11-28 22:51:38 +00001786 return EVT::getVectorVT(Ctx, MVT::i1, VT.getVectorNumElements());
Tom Stellard75aadc22012-12-11 21:25:42 +00001787}
1788
Mehdi Aminieaabc512015-07-09 15:12:23 +00001789MVT SITargetLowering::getScalarShiftAmountTy(const DataLayout &, EVT) const {
Christian Konig082a14a2013-03-18 11:34:05 +00001790 return MVT::i32;
1791}
1792
Matt Arsenault423bf3f2015-01-29 19:34:32 +00001793// Answering this is somewhat tricky and depends on the specific device which
1794// have different rates for fma or all f64 operations.
1795//
1796// v_fma_f64 and v_mul_f64 always take the same number of cycles as each other
1797// regardless of which device (although the number of cycles differs between
1798// devices), so it is always profitable for f64.
1799//
1800// v_fma_f32 takes 4 or 16 cycles depending on the device, so it is profitable
1801// only on full rate devices. Normally, we should prefer selecting v_mad_f32
1802// which we can always do even without fused FP ops since it returns the same
1803// result as the separate operations and since it is always full
1804// rate. Therefore, we lie and report that it is not faster for f32. v_mad_f32
1805// however does not support denormals, so we do report fma as faster if we have
1806// a fast fma device and require denormals.
1807//
Niels Ole Salscheiderd3a039f2013-08-10 10:38:54 +00001808bool SITargetLowering::isFMAFasterThanFMulAndFAdd(EVT VT) const {
1809 VT = VT.getScalarType();
1810
1811 if (!VT.isSimple())
1812 return false;
1813
1814 switch (VT.getSimpleVT().SimpleTy) {
1815 case MVT::f32:
Matt Arsenault423bf3f2015-01-29 19:34:32 +00001816 // This is as fast on some subtargets. However, we always have full rate f32
1817 // mad available which returns the same result as the separate operations
Matt Arsenault8d630032015-02-20 22:10:41 +00001818 // which we should prefer over fma. We can't use this if we want to support
1819 // denormals, so only report this in these cases.
1820 return Subtarget->hasFP32Denormals() && Subtarget->hasFastFMAF32();
Niels Ole Salscheiderd3a039f2013-08-10 10:38:54 +00001821 case MVT::f64:
1822 return true;
1823 default:
1824 break;
1825 }
1826
1827 return false;
1828}
1829
Tom Stellard75aadc22012-12-11 21:25:42 +00001830//===----------------------------------------------------------------------===//
1831// Custom DAG Lowering Operations
1832//===----------------------------------------------------------------------===//
1833
1834SDValue SITargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1835 switch (Op.getOpcode()) {
1836 default: return AMDGPUTargetLowering::LowerOperation(Op, DAG);
Tom Stellardf8794352012-12-19 22:10:31 +00001837 case ISD::BRCOND: return LowerBRCOND(Op, DAG);
Tom Stellard35bb18c2013-08-26 15:06:04 +00001838 case ISD::LOAD: {
Tom Stellarde812f2f2014-07-21 15:45:06 +00001839 SDValue Result = LowerLOAD(Op, DAG);
1840 assert((!Result.getNode() ||
1841 Result.getNode()->getNumValues() == 2) &&
1842 "Load should return a value and a chain");
1843 return Result;
Tom Stellard35bb18c2013-08-26 15:06:04 +00001844 }
Tom Stellardaf775432013-10-23 00:44:32 +00001845
Matt Arsenaultad14ce82014-07-19 18:44:39 +00001846 case ISD::FSIN:
1847 case ISD::FCOS:
1848 return LowerTrig(Op, DAG);
Tom Stellard0ec134f2014-02-04 17:18:40 +00001849 case ISD::SELECT: return LowerSELECT(Op, DAG);
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +00001850 case ISD::FDIV: return LowerFDIV(Op, DAG);
Tom Stellard354a43c2016-04-01 18:27:37 +00001851 case ISD::ATOMIC_CMP_SWAP: return LowerATOMIC_CMP_SWAP(Op, DAG);
Tom Stellard81d871d2013-11-13 23:36:50 +00001852 case ISD::STORE: return LowerSTORE(Op, DAG);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00001853 case ISD::GlobalAddress: {
1854 MachineFunction &MF = DAG.getMachineFunction();
1855 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
1856 return LowerGlobalAddress(MFI, Op, DAG);
Tom Stellard94593ee2013-06-03 17:40:18 +00001857 }
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00001858 case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG);
Matt Arsenaulta9dbdca2016-04-12 14:05:04 +00001859 case ISD::INTRINSIC_W_CHAIN: return LowerINTRINSIC_W_CHAIN(Op, DAG);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00001860 case ISD::INTRINSIC_VOID: return LowerINTRINSIC_VOID(Op, DAG);
Matt Arsenault99c14522016-04-25 19:27:24 +00001861 case ISD::ADDRSPACECAST: return lowerADDRSPACECAST(Op, DAG);
Matt Arsenault0bb294b2016-06-17 22:27:03 +00001862 case ISD::TRAP: return lowerTRAP(Op, DAG);
Konstantin Zhuravlyovd709efb2016-11-17 04:28:37 +00001863 case ISD::FP_ROUND:
1864 return lowerFP_ROUND(Op, DAG);
Tom Stellard75aadc22012-12-11 21:25:42 +00001865 }
1866 return SDValue();
1867}
1868
Tom Stellardf8794352012-12-19 22:10:31 +00001869/// \brief Helper function for LowerBRCOND
1870static SDNode *findUser(SDValue Value, unsigned Opcode) {
Tom Stellard75aadc22012-12-11 21:25:42 +00001871
Tom Stellardf8794352012-12-19 22:10:31 +00001872 SDNode *Parent = Value.getNode();
1873 for (SDNode::use_iterator I = Parent->use_begin(), E = Parent->use_end();
1874 I != E; ++I) {
1875
1876 if (I.getUse().get() != Value)
1877 continue;
1878
1879 if (I->getOpcode() == Opcode)
1880 return *I;
1881 }
Craig Topper062a2ba2014-04-25 05:30:21 +00001882 return nullptr;
Tom Stellardf8794352012-12-19 22:10:31 +00001883}
1884
Tom Stellardbc4497b2016-02-12 23:45:29 +00001885bool SITargetLowering::isCFIntrinsic(const SDNode *Intr) const {
Matt Arsenault6408c912016-09-16 22:11:18 +00001886 if (Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN) {
1887 switch (cast<ConstantSDNode>(Intr->getOperand(1))->getZExtValue()) {
1888 case AMDGPUIntrinsic::amdgcn_if:
1889 case AMDGPUIntrinsic::amdgcn_else:
1890 case AMDGPUIntrinsic::amdgcn_end_cf:
1891 case AMDGPUIntrinsic::amdgcn_loop:
1892 return true;
1893 default:
1894 return false;
1895 }
Tom Stellardbc4497b2016-02-12 23:45:29 +00001896 }
Matt Arsenault6408c912016-09-16 22:11:18 +00001897
1898 if (Intr->getOpcode() == ISD::INTRINSIC_WO_CHAIN) {
1899 switch (cast<ConstantSDNode>(Intr->getOperand(0))->getZExtValue()) {
1900 case AMDGPUIntrinsic::amdgcn_break:
1901 case AMDGPUIntrinsic::amdgcn_if_break:
1902 case AMDGPUIntrinsic::amdgcn_else_break:
1903 return true;
1904 default:
1905 return false;
1906 }
1907 }
1908
1909 return false;
Tom Stellardbc4497b2016-02-12 23:45:29 +00001910}
1911
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +00001912void SITargetLowering::createDebuggerPrologueStackObjects(
1913 MachineFunction &MF) const {
1914 // Create stack objects that are used for emitting debugger prologue.
1915 //
1916 // Debugger prologue writes work group IDs and work item IDs to scratch memory
1917 // at fixed location in the following format:
1918 // offset 0: work group ID x
1919 // offset 4: work group ID y
1920 // offset 8: work group ID z
1921 // offset 16: work item ID x
1922 // offset 20: work item ID y
1923 // offset 24: work item ID z
1924 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
1925 int ObjectIdx = 0;
1926
1927 // For each dimension:
1928 for (unsigned i = 0; i < 3; ++i) {
1929 // Create fixed stack object for work group ID.
Matthias Braun941a7052016-07-28 18:40:00 +00001930 ObjectIdx = MF.getFrameInfo().CreateFixedObject(4, i * 4, true);
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +00001931 Info->setDebuggerWorkGroupIDStackObjectIndex(i, ObjectIdx);
1932 // Create fixed stack object for work item ID.
Matthias Braun941a7052016-07-28 18:40:00 +00001933 ObjectIdx = MF.getFrameInfo().CreateFixedObject(4, i * 4 + 16, true);
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +00001934 Info->setDebuggerWorkItemIDStackObjectIndex(i, ObjectIdx);
1935 }
1936}
1937
Konstantin Zhuravlyov08326b62016-10-20 18:12:38 +00001938bool SITargetLowering::shouldEmitFixup(const GlobalValue *GV) const {
1939 const Triple &TT = getTargetMachine().getTargetTriple();
1940 return GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS &&
1941 AMDGPU::shouldEmitConstantsToTextSection(TT);
1942}
1943
1944bool SITargetLowering::shouldEmitGOTReloc(const GlobalValue *GV) const {
1945 return (GV->getType()->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
1946 GV->getType()->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) &&
1947 !shouldEmitFixup(GV) &&
1948 !getTargetMachine().shouldAssumeDSOLocal(*GV->getParent(), GV);
1949}
1950
1951bool SITargetLowering::shouldEmitPCReloc(const GlobalValue *GV) const {
1952 return !shouldEmitFixup(GV) && !shouldEmitGOTReloc(GV);
1953}
1954
Tom Stellardf8794352012-12-19 22:10:31 +00001955/// This transforms the control flow intrinsics to get the branch destination as
1956/// last parameter, also switches branch target with BR if the need arise
1957SDValue SITargetLowering::LowerBRCOND(SDValue BRCOND,
1958 SelectionDAG &DAG) const {
1959
Andrew Trickef9de2a2013-05-25 02:42:55 +00001960 SDLoc DL(BRCOND);
Tom Stellardf8794352012-12-19 22:10:31 +00001961
1962 SDNode *Intr = BRCOND.getOperand(1).getNode();
1963 SDValue Target = BRCOND.getOperand(2);
Craig Topper062a2ba2014-04-25 05:30:21 +00001964 SDNode *BR = nullptr;
Tom Stellardbc4497b2016-02-12 23:45:29 +00001965 SDNode *SetCC = nullptr;
Tom Stellardf8794352012-12-19 22:10:31 +00001966
1967 if (Intr->getOpcode() == ISD::SETCC) {
1968 // As long as we negate the condition everything is fine
Tom Stellardbc4497b2016-02-12 23:45:29 +00001969 SetCC = Intr;
Tom Stellardf8794352012-12-19 22:10:31 +00001970 Intr = SetCC->getOperand(0).getNode();
1971
1972 } else {
1973 // Get the target from BR if we don't negate the condition
1974 BR = findUser(BRCOND, ISD::BR);
1975 Target = BR->getOperand(1);
1976 }
1977
Matt Arsenault6408c912016-09-16 22:11:18 +00001978 // FIXME: This changes the types of the intrinsics instead of introducing new
1979 // nodes with the correct types.
1980 // e.g. llvm.amdgcn.loop
1981
1982 // eg: i1,ch = llvm.amdgcn.loop t0, TargetConstant:i32<6271>, t3
1983 // => t9: ch = llvm.amdgcn.loop t0, TargetConstant:i32<6271>, t3, BasicBlock:ch<bb1 0x7fee5286d088>
1984
Nicolai Haehnleffbd56a2016-05-05 17:36:36 +00001985 if (!isCFIntrinsic(Intr)) {
Tom Stellardbc4497b2016-02-12 23:45:29 +00001986 // This is a uniform branch so we don't need to legalize.
1987 return BRCOND;
1988 }
1989
Matt Arsenault6408c912016-09-16 22:11:18 +00001990 bool HaveChain = Intr->getOpcode() == ISD::INTRINSIC_VOID ||
1991 Intr->getOpcode() == ISD::INTRINSIC_W_CHAIN;
1992
Tom Stellardbc4497b2016-02-12 23:45:29 +00001993 assert(!SetCC ||
1994 (SetCC->getConstantOperandVal(1) == 1 &&
Tom Stellardbc4497b2016-02-12 23:45:29 +00001995 cast<CondCodeSDNode>(SetCC->getOperand(2).getNode())->get() ==
1996 ISD::SETNE));
Tom Stellardf8794352012-12-19 22:10:31 +00001997
Tom Stellardf8794352012-12-19 22:10:31 +00001998 // operands of the new intrinsic call
1999 SmallVector<SDValue, 4> Ops;
Matt Arsenault6408c912016-09-16 22:11:18 +00002000 if (HaveChain)
2001 Ops.push_back(BRCOND.getOperand(0));
2002
2003 Ops.append(Intr->op_begin() + (HaveChain ? 1 : 0), Intr->op_end());
Tom Stellardf8794352012-12-19 22:10:31 +00002004 Ops.push_back(Target);
2005
Matt Arsenault6408c912016-09-16 22:11:18 +00002006 ArrayRef<EVT> Res(Intr->value_begin() + 1, Intr->value_end());
2007
Tom Stellardf8794352012-12-19 22:10:31 +00002008 // build the new intrinsic call
2009 SDNode *Result = DAG.getNode(
2010 Res.size() > 1 ? ISD::INTRINSIC_W_CHAIN : ISD::INTRINSIC_VOID, DL,
Craig Topper48d114b2014-04-26 18:35:24 +00002011 DAG.getVTList(Res), Ops).getNode();
Tom Stellardf8794352012-12-19 22:10:31 +00002012
Matt Arsenault6408c912016-09-16 22:11:18 +00002013 if (!HaveChain) {
2014 SDValue Ops[] = {
2015 SDValue(Result, 0),
2016 BRCOND.getOperand(0)
2017 };
2018
2019 Result = DAG.getMergeValues(Ops, DL).getNode();
2020 }
2021
Tom Stellardf8794352012-12-19 22:10:31 +00002022 if (BR) {
2023 // Give the branch instruction our target
2024 SDValue Ops[] = {
2025 BR->getOperand(0),
2026 BRCOND.getOperand(2)
2027 };
Chandler Carruth356665a2014-08-01 22:09:43 +00002028 SDValue NewBR = DAG.getNode(ISD::BR, DL, BR->getVTList(), Ops);
2029 DAG.ReplaceAllUsesWith(BR, NewBR.getNode());
2030 BR = NewBR.getNode();
Tom Stellardf8794352012-12-19 22:10:31 +00002031 }
2032
2033 SDValue Chain = SDValue(Result, Result->getNumValues() - 1);
2034
2035 // Copy the intrinsic results to registers
2036 for (unsigned i = 1, e = Intr->getNumValues() - 1; i != e; ++i) {
2037 SDNode *CopyToReg = findUser(SDValue(Intr, i), ISD::CopyToReg);
2038 if (!CopyToReg)
2039 continue;
2040
2041 Chain = DAG.getCopyToReg(
2042 Chain, DL,
2043 CopyToReg->getOperand(1),
2044 SDValue(Result, i - 1),
2045 SDValue());
2046
2047 DAG.ReplaceAllUsesWith(SDValue(CopyToReg, 0), CopyToReg->getOperand(0));
2048 }
2049
2050 // Remove the old intrinsic from the chain
2051 DAG.ReplaceAllUsesOfValueWith(
2052 SDValue(Intr, Intr->getNumValues() - 1),
2053 Intr->getOperand(0));
2054
2055 return Chain;
Tom Stellard75aadc22012-12-11 21:25:42 +00002056}
2057
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +00002058SDValue SITargetLowering::getFPExtOrFPTrunc(SelectionDAG &DAG,
2059 SDValue Op,
2060 const SDLoc &DL,
2061 EVT VT) const {
2062 return Op.getValueType().bitsLE(VT) ?
2063 DAG.getNode(ISD::FP_EXTEND, DL, VT, Op) :
2064 DAG.getNode(ISD::FTRUNC, DL, VT, Op);
2065}
2066
Konstantin Zhuravlyovd709efb2016-11-17 04:28:37 +00002067SDValue SITargetLowering::lowerFP_ROUND(SDValue Op, SelectionDAG &DAG) const {
Matt Arsenaultafe614c2016-11-18 18:33:36 +00002068 assert(Op.getValueType() == MVT::f16 &&
Konstantin Zhuravlyovd709efb2016-11-17 04:28:37 +00002069 "Do not know how to custom lower FP_ROUND for non-f16 type");
2070
Matt Arsenaultafe614c2016-11-18 18:33:36 +00002071 SDValue Src = Op.getOperand(0);
2072 EVT SrcVT = Src.getValueType();
Konstantin Zhuravlyovd709efb2016-11-17 04:28:37 +00002073 if (SrcVT != MVT::f64)
2074 return Op;
2075
2076 SDLoc DL(Op);
Matt Arsenaultafe614c2016-11-18 18:33:36 +00002077
Konstantin Zhuravlyovd709efb2016-11-17 04:28:37 +00002078 SDValue FpToFp16 = DAG.getNode(ISD::FP_TO_FP16, DL, MVT::i32, Src);
2079 SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FpToFp16);
2080 return DAG.getNode(ISD::BITCAST, DL, MVT::f16, Trunc);;
2081}
2082
Matt Arsenault99c14522016-04-25 19:27:24 +00002083SDValue SITargetLowering::getSegmentAperture(unsigned AS,
2084 SelectionDAG &DAG) const {
2085 SDLoc SL;
2086 MachineFunction &MF = DAG.getMachineFunction();
2087 SIMachineFunctionInfo *Info = MF.getInfo<SIMachineFunctionInfo>();
Matt Arsenault3b2e2a52016-06-06 20:03:31 +00002088 unsigned UserSGPR = Info->getQueuePtrUserSGPR();
2089 assert(UserSGPR != AMDGPU::NoRegister);
2090
Matt Arsenault99c14522016-04-25 19:27:24 +00002091 SDValue QueuePtr = CreateLiveInRegister(
Matt Arsenault3b2e2a52016-06-06 20:03:31 +00002092 DAG, &AMDGPU::SReg_64RegClass, UserSGPR, MVT::i64);
Matt Arsenault99c14522016-04-25 19:27:24 +00002093
2094 // Offset into amd_queue_t for group_segment_aperture_base_hi /
2095 // private_segment_aperture_base_hi.
2096 uint32_t StructOffset = (AS == AMDGPUAS::LOCAL_ADDRESS) ? 0x40 : 0x44;
2097
2098 SDValue Ptr = DAG.getNode(ISD::ADD, SL, MVT::i64, QueuePtr,
2099 DAG.getConstant(StructOffset, SL, MVT::i64));
2100
2101 // TODO: Use custom target PseudoSourceValue.
2102 // TODO: We should use the value from the IR intrinsic call, but it might not
2103 // be available and how do we get it?
2104 Value *V = UndefValue::get(PointerType::get(Type::getInt8Ty(*DAG.getContext()),
2105 AMDGPUAS::CONSTANT_ADDRESS));
2106
2107 MachinePointerInfo PtrInfo(V, StructOffset);
Justin Lebar9c375812016-07-15 18:27:10 +00002108 return DAG.getLoad(MVT::i32, SL, QueuePtr.getValue(1), Ptr, PtrInfo,
2109 MinAlign(64, StructOffset),
Justin Lebaradbf09e2016-09-11 01:38:58 +00002110 MachineMemOperand::MODereferenceable |
2111 MachineMemOperand::MOInvariant);
Matt Arsenault99c14522016-04-25 19:27:24 +00002112}
2113
2114SDValue SITargetLowering::lowerADDRSPACECAST(SDValue Op,
2115 SelectionDAG &DAG) const {
2116 SDLoc SL(Op);
2117 const AddrSpaceCastSDNode *ASC = cast<AddrSpaceCastSDNode>(Op);
2118
2119 SDValue Src = ASC->getOperand(0);
2120
2121 // FIXME: Really support non-0 null pointers.
2122 SDValue SegmentNullPtr = DAG.getConstant(-1, SL, MVT::i32);
2123 SDValue FlatNullPtr = DAG.getConstant(0, SL, MVT::i64);
2124
2125 // flat -> local/private
2126 if (ASC->getSrcAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
2127 if (ASC->getDestAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
2128 ASC->getDestAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
2129 SDValue NonNull = DAG.getSetCC(SL, MVT::i1, Src, FlatNullPtr, ISD::SETNE);
2130 SDValue Ptr = DAG.getNode(ISD::TRUNCATE, SL, MVT::i32, Src);
2131
2132 return DAG.getNode(ISD::SELECT, SL, MVT::i32,
2133 NonNull, Ptr, SegmentNullPtr);
2134 }
2135 }
2136
2137 // local/private -> flat
2138 if (ASC->getDestAddressSpace() == AMDGPUAS::FLAT_ADDRESS) {
2139 if (ASC->getSrcAddressSpace() == AMDGPUAS::LOCAL_ADDRESS ||
2140 ASC->getSrcAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
2141 SDValue NonNull
2142 = DAG.getSetCC(SL, MVT::i1, Src, SegmentNullPtr, ISD::SETNE);
2143
2144 SDValue Aperture = getSegmentAperture(ASC->getSrcAddressSpace(), DAG);
2145 SDValue CvtPtr
2146 = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32, Src, Aperture);
2147
2148 return DAG.getNode(ISD::SELECT, SL, MVT::i64, NonNull,
2149 DAG.getNode(ISD::BITCAST, SL, MVT::i64, CvtPtr),
2150 FlatNullPtr);
2151 }
2152 }
2153
2154 // global <-> flat are no-ops and never emitted.
2155
2156 const MachineFunction &MF = DAG.getMachineFunction();
2157 DiagnosticInfoUnsupported InvalidAddrSpaceCast(
2158 *MF.getFunction(), "invalid addrspacecast", SL.getDebugLoc());
2159 DAG.getContext()->diagnose(InvalidAddrSpaceCast);
2160
2161 return DAG.getUNDEF(ASC->getValueType(0));
2162}
2163
Tom Stellard418beb72016-07-13 14:23:33 +00002164bool
2165SITargetLowering::isOffsetFoldingLegal(const GlobalAddressSDNode *GA) const {
2166 // We can fold offsets for anything that doesn't require a GOT relocation.
Konstantin Zhuravlyov08326b62016-10-20 18:12:38 +00002167 return (GA->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS ||
2168 GA->getAddressSpace() == AMDGPUAS::CONSTANT_ADDRESS) &&
2169 !shouldEmitGOTReloc(GA->getGlobal());
Tom Stellard418beb72016-07-13 14:23:33 +00002170}
Tom Stellardbf3e6e52016-06-14 20:29:59 +00002171
Tom Stellard418beb72016-07-13 14:23:33 +00002172static SDValue buildPCRelGlobalAddress(SelectionDAG &DAG, const GlobalValue *GV,
2173 SDLoc DL, unsigned Offset, EVT PtrVT,
2174 unsigned GAFlags = SIInstrInfo::MO_NONE) {
Tom Stellardbf3e6e52016-06-14 20:29:59 +00002175 // In order to support pc-relative addressing, the PC_ADD_REL_OFFSET SDNode is
2176 // lowered to the following code sequence:
Tom Stellardbf3e6e52016-06-14 20:29:59 +00002177 //
Konstantin Zhuravlyovc96b5d72016-10-14 04:37:34 +00002178 // For constant address space:
2179 // s_getpc_b64 s[0:1]
2180 // s_add_u32 s0, s0, $symbol
2181 // s_addc_u32 s1, s1, 0
2182 //
2183 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
2184 // a fixup or relocation is emitted to replace $symbol with a literal
2185 // constant, which is a pc-relative offset from the encoding of the $symbol
2186 // operand to the global variable.
2187 //
2188 // For global address space:
2189 // s_getpc_b64 s[0:1]
2190 // s_add_u32 s0, s0, $symbol@{gotpc}rel32@lo
2191 // s_addc_u32 s1, s1, $symbol@{gotpc}rel32@hi
2192 //
2193 // s_getpc_b64 returns the address of the s_add_u32 instruction and then
2194 // fixups or relocations are emitted to replace $symbol@*@lo and
2195 // $symbol@*@hi with lower 32 bits and higher 32 bits of a literal constant,
2196 // which is a 64-bit pc-relative offset from the encoding of the $symbol
2197 // operand to the global variable.
Tom Stellardbf3e6e52016-06-14 20:29:59 +00002198 //
2199 // What we want here is an offset from the value returned by s_getpc
2200 // (which is the address of the s_add_u32 instruction) to the global
2201 // variable, but since the encoding of $symbol starts 4 bytes after the start
2202 // of the s_add_u32 instruction, we end up with an offset that is 4 bytes too
2203 // small. This requires us to add 4 to the global variable offset in order to
2204 // compute the correct address.
Konstantin Zhuravlyovc96b5d72016-10-14 04:37:34 +00002205 SDValue PtrLo = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4,
2206 GAFlags);
2207 SDValue PtrHi = DAG.getTargetGlobalAddress(GV, DL, MVT::i32, Offset + 4,
2208 GAFlags == SIInstrInfo::MO_NONE ?
2209 GAFlags : GAFlags + 1);
2210 return DAG.getNode(AMDGPUISD::PC_ADD_REL_OFFSET, DL, PtrVT, PtrLo, PtrHi);
Tom Stellardbf3e6e52016-06-14 20:29:59 +00002211}
2212
Tom Stellard418beb72016-07-13 14:23:33 +00002213SDValue SITargetLowering::LowerGlobalAddress(AMDGPUMachineFunction *MFI,
2214 SDValue Op,
2215 SelectionDAG &DAG) const {
2216 GlobalAddressSDNode *GSD = cast<GlobalAddressSDNode>(Op);
2217
2218 if (GSD->getAddressSpace() != AMDGPUAS::CONSTANT_ADDRESS &&
2219 GSD->getAddressSpace() != AMDGPUAS::GLOBAL_ADDRESS)
2220 return AMDGPUTargetLowering::LowerGlobalAddress(MFI, Op, DAG);
2221
2222 SDLoc DL(GSD);
2223 const GlobalValue *GV = GSD->getGlobal();
2224 EVT PtrVT = Op.getValueType();
2225
Konstantin Zhuravlyov08326b62016-10-20 18:12:38 +00002226 if (shouldEmitFixup(GV))
Tom Stellard418beb72016-07-13 14:23:33 +00002227 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT);
Konstantin Zhuravlyov08326b62016-10-20 18:12:38 +00002228 else if (shouldEmitPCReloc(GV))
Konstantin Zhuravlyovc96b5d72016-10-14 04:37:34 +00002229 return buildPCRelGlobalAddress(DAG, GV, DL, GSD->getOffset(), PtrVT,
2230 SIInstrInfo::MO_REL32);
Tom Stellard418beb72016-07-13 14:23:33 +00002231
2232 SDValue GOTAddr = buildPCRelGlobalAddress(DAG, GV, DL, 0, PtrVT,
Konstantin Zhuravlyovc96b5d72016-10-14 04:37:34 +00002233 SIInstrInfo::MO_GOTPCREL32);
Tom Stellard418beb72016-07-13 14:23:33 +00002234
2235 Type *Ty = PtrVT.getTypeForEVT(*DAG.getContext());
2236 PointerType *PtrTy = PointerType::get(Ty, AMDGPUAS::CONSTANT_ADDRESS);
2237 const DataLayout &DataLayout = DAG.getDataLayout();
2238 unsigned Align = DataLayout.getABITypeAlignment(PtrTy);
2239 // FIXME: Use a PseudoSourceValue once those can be assigned an address space.
2240 MachinePointerInfo PtrInfo(UndefValue::get(PtrTy));
2241
Justin Lebar9c375812016-07-15 18:27:10 +00002242 return DAG.getLoad(PtrVT, DL, DAG.getEntryNode(), GOTAddr, PtrInfo, Align,
Justin Lebaradbf09e2016-09-11 01:38:58 +00002243 MachineMemOperand::MODereferenceable |
2244 MachineMemOperand::MOInvariant);
Tom Stellard418beb72016-07-13 14:23:33 +00002245}
2246
Matt Arsenault0bb294b2016-06-17 22:27:03 +00002247SDValue SITargetLowering::lowerTRAP(SDValue Op,
2248 SelectionDAG &DAG) const {
2249 const MachineFunction &MF = DAG.getMachineFunction();
2250 DiagnosticInfoUnsupported NoTrap(*MF.getFunction(),
2251 "trap handler not supported",
2252 Op.getDebugLoc(),
2253 DS_Warning);
2254 DAG.getContext()->diagnose(NoTrap);
2255
2256 // Emit s_endpgm.
2257
2258 // FIXME: This should really be selected to s_trap, but that requires
2259 // setting up the trap handler for it o do anything.
Matt Arsenault9babdf42016-06-22 20:15:28 +00002260 return DAG.getNode(AMDGPUISD::ENDPGM, SDLoc(Op), MVT::Other,
2261 Op.getOperand(0));
Matt Arsenault0bb294b2016-06-17 22:27:03 +00002262}
2263
Benjamin Kramerbdc49562016-06-12 15:39:02 +00002264SDValue SITargetLowering::copyToM0(SelectionDAG &DAG, SDValue Chain,
2265 const SDLoc &DL, SDValue V) const {
Matt Arsenault4ac341c2016-04-14 21:58:15 +00002266 // We can't use S_MOV_B32 directly, because there is no way to specify m0 as
2267 // the destination register.
2268 //
Tom Stellardfc92e772015-05-12 14:18:14 +00002269 // We can't use CopyToReg, because MachineCSE won't combine COPY instructions,
2270 // so we will end up with redundant moves to m0.
2271 //
Matt Arsenault4ac341c2016-04-14 21:58:15 +00002272 // We use a pseudo to ensure we emit s_mov_b32 with m0 as the direct result.
2273
2274 // A Null SDValue creates a glue result.
2275 SDNode *M0 = DAG.getMachineNode(AMDGPU::SI_INIT_M0, DL, MVT::Other, MVT::Glue,
2276 V, Chain);
2277 return SDValue(M0, 0);
Tom Stellardfc92e772015-05-12 14:18:14 +00002278}
2279
Matt Arsenaultff6da2f2015-11-30 21:15:45 +00002280SDValue SITargetLowering::lowerImplicitZextParam(SelectionDAG &DAG,
2281 SDValue Op,
2282 MVT VT,
2283 unsigned Offset) const {
2284 SDLoc SL(Op);
2285 SDValue Param = LowerParameter(DAG, MVT::i32, MVT::i32, SL,
2286 DAG.getEntryNode(), Offset, false);
2287 // The local size values will have the hi 16-bits as zero.
2288 return DAG.getNode(ISD::AssertZext, SL, MVT::i32, Param,
2289 DAG.getValueType(VT));
2290}
2291
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002292static SDValue emitNonHSAIntrinsicError(SelectionDAG& DAG, SDLoc DL, EVT VT) {
Matt Arsenaulte0132462016-01-30 05:19:45 +00002293 DiagnosticInfoUnsupported BadIntrin(*DAG.getMachineFunction().getFunction(),
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002294 "non-hsa intrinsic with hsa target",
2295 DL.getDebugLoc());
2296 DAG.getContext()->diagnose(BadIntrin);
2297 return DAG.getUNDEF(VT);
2298}
2299
2300static SDValue emitRemovedIntrinsicError(SelectionDAG& DAG, SDLoc DL, EVT VT) {
2301 DiagnosticInfoUnsupported BadIntrin(*DAG.getMachineFunction().getFunction(),
2302 "intrinsic not supported on subtarget",
2303 DL.getDebugLoc());
Matt Arsenaulte0132462016-01-30 05:19:45 +00002304 DAG.getContext()->diagnose(BadIntrin);
2305 return DAG.getUNDEF(VT);
2306}
2307
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002308SDValue SITargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
2309 SelectionDAG &DAG) const {
2310 MachineFunction &MF = DAG.getMachineFunction();
Tom Stellarddcb9f092015-07-09 21:20:37 +00002311 auto MFI = MF.getInfo<SIMachineFunctionInfo>();
Matt Arsenault43e92fe2016-06-24 06:30:11 +00002312 const SIRegisterInfo *TRI = getSubtarget()->getRegisterInfo();
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002313
2314 EVT VT = Op.getValueType();
2315 SDLoc DL(Op);
2316 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(0))->getZExtValue();
2317
Sanjay Patela2607012015-09-16 16:31:21 +00002318 // TODO: Should this propagate fast-math-flags?
2319
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002320 switch (IntrinsicID) {
Tom Stellard48f29f22015-11-26 00:43:29 +00002321 case Intrinsic::amdgcn_dispatch_ptr:
Matt Arsenault48ab5262016-04-25 19:27:18 +00002322 case Intrinsic::amdgcn_queue_ptr: {
Tom Stellard0b76fc4c2016-09-16 21:34:26 +00002323 if (!Subtarget->isAmdCodeObjectV2()) {
Oliver Stannard7e7d9832016-02-02 13:52:43 +00002324 DiagnosticInfoUnsupported BadIntrin(
2325 *MF.getFunction(), "unsupported hsa intrinsic without hsa target",
2326 DL.getDebugLoc());
Matt Arsenault800fecf2016-01-11 21:18:33 +00002327 DAG.getContext()->diagnose(BadIntrin);
2328 return DAG.getUNDEF(VT);
2329 }
2330
Matt Arsenault48ab5262016-04-25 19:27:18 +00002331 auto Reg = IntrinsicID == Intrinsic::amdgcn_dispatch_ptr ?
2332 SIRegisterInfo::DISPATCH_PTR : SIRegisterInfo::QUEUE_PTR;
Tom Stellard48f29f22015-11-26 00:43:29 +00002333 return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass,
Matt Arsenault48ab5262016-04-25 19:27:18 +00002334 TRI->getPreloadedValue(MF, Reg), VT);
2335 }
Jan Veselyfea814d2016-06-21 20:46:20 +00002336 case Intrinsic::amdgcn_implicitarg_ptr: {
2337 unsigned offset = getImplicitParameterOffset(MFI, FIRST_IMPLICIT);
2338 return LowerParameterPtr(DAG, DL, DAG.getEntryNode(), offset);
2339 }
Matt Arsenaultdc4ebad2016-04-29 21:16:52 +00002340 case Intrinsic::amdgcn_kernarg_segment_ptr: {
2341 unsigned Reg
2342 = TRI->getPreloadedValue(MF, SIRegisterInfo::KERNARG_SEGMENT_PTR);
2343 return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass, Reg, VT);
2344 }
Matt Arsenault8d718dc2016-07-22 17:01:30 +00002345 case Intrinsic::amdgcn_dispatch_id: {
2346 unsigned Reg = TRI->getPreloadedValue(MF, SIRegisterInfo::DISPATCH_ID);
2347 return CreateLiveInRegister(DAG, &AMDGPU::SReg_64RegClass, Reg, VT);
2348 }
Matt Arsenaultf75257a2016-01-23 05:32:20 +00002349 case Intrinsic::amdgcn_rcp:
2350 return DAG.getNode(AMDGPUISD::RCP, DL, VT, Op.getOperand(1));
2351 case Intrinsic::amdgcn_rsq:
Matt Arsenault0c3e2332016-01-26 04:14:16 +00002352 case AMDGPUIntrinsic::AMDGPU_rsq: // Legacy name
Matt Arsenaultf75257a2016-01-23 05:32:20 +00002353 return DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002354 case Intrinsic::amdgcn_rsq_legacy: {
Matt Arsenault43e92fe2016-06-24 06:30:11 +00002355 if (Subtarget->getGeneration() >= SISubtarget::VOLCANIC_ISLANDS)
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002356 return emitRemovedIntrinsicError(DAG, DL, VT);
2357
2358 return DAG.getNode(AMDGPUISD::RSQ_LEGACY, DL, VT, Op.getOperand(1));
2359 }
Matt Arsenault32fc5272016-07-26 16:45:45 +00002360 case Intrinsic::amdgcn_rcp_legacy: {
2361 if (Subtarget->getGeneration() >= SISubtarget::VOLCANIC_ISLANDS)
2362 return emitRemovedIntrinsicError(DAG, DL, VT);
2363 return DAG.getNode(AMDGPUISD::RCP_LEGACY, DL, VT, Op.getOperand(1));
2364 }
Matt Arsenault09b2c4a2016-07-15 21:26:52 +00002365 case Intrinsic::amdgcn_rsq_clamp: {
Matt Arsenault43e92fe2016-06-24 06:30:11 +00002366 if (Subtarget->getGeneration() < SISubtarget::VOLCANIC_ISLANDS)
Matt Arsenault79963e82016-02-13 01:03:00 +00002367 return DAG.getNode(AMDGPUISD::RSQ_CLAMP, DL, VT, Op.getOperand(1));
Tom Stellard48f29f22015-11-26 00:43:29 +00002368
Matt Arsenaultf75257a2016-01-23 05:32:20 +00002369 Type *Type = VT.getTypeForEVT(*DAG.getContext());
2370 APFloat Max = APFloat::getLargest(Type->getFltSemantics());
2371 APFloat Min = APFloat::getLargest(Type->getFltSemantics(), true);
2372
2373 SDValue Rsq = DAG.getNode(AMDGPUISD::RSQ, DL, VT, Op.getOperand(1));
2374 SDValue Tmp = DAG.getNode(ISD::FMINNUM, DL, VT, Rsq,
2375 DAG.getConstantFP(Max, DL, VT));
2376 return DAG.getNode(ISD::FMAXNUM, DL, VT, Tmp,
2377 DAG.getConstantFP(Min, DL, VT));
2378 }
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002379 case Intrinsic::r600_read_ngroups_x:
Matt Arsenaulte0132462016-01-30 05:19:45 +00002380 if (Subtarget->isAmdHsaOS())
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002381 return emitNonHSAIntrinsicError(DAG, DL, VT);
Matt Arsenaulte0132462016-01-30 05:19:45 +00002382
Tom Stellardec2e43c2014-09-22 15:35:29 +00002383 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
2384 SI::KernelInputOffsets::NGROUPS_X, false);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002385 case Intrinsic::r600_read_ngroups_y:
Matt Arsenaulte0132462016-01-30 05:19:45 +00002386 if (Subtarget->isAmdHsaOS())
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002387 return emitNonHSAIntrinsicError(DAG, DL, VT);
Matt Arsenaulte0132462016-01-30 05:19:45 +00002388
Tom Stellardec2e43c2014-09-22 15:35:29 +00002389 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
2390 SI::KernelInputOffsets::NGROUPS_Y, false);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002391 case Intrinsic::r600_read_ngroups_z:
Matt Arsenaulte0132462016-01-30 05:19:45 +00002392 if (Subtarget->isAmdHsaOS())
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002393 return emitNonHSAIntrinsicError(DAG, DL, VT);
Matt Arsenaulte0132462016-01-30 05:19:45 +00002394
Tom Stellardec2e43c2014-09-22 15:35:29 +00002395 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
2396 SI::KernelInputOffsets::NGROUPS_Z, false);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002397 case Intrinsic::r600_read_global_size_x:
Matt Arsenaulte0132462016-01-30 05:19:45 +00002398 if (Subtarget->isAmdHsaOS())
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002399 return emitNonHSAIntrinsicError(DAG, DL, VT);
Matt Arsenaulte0132462016-01-30 05:19:45 +00002400
Tom Stellardec2e43c2014-09-22 15:35:29 +00002401 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
2402 SI::KernelInputOffsets::GLOBAL_SIZE_X, false);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002403 case Intrinsic::r600_read_global_size_y:
Matt Arsenaulte0132462016-01-30 05:19:45 +00002404 if (Subtarget->isAmdHsaOS())
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002405 return emitNonHSAIntrinsicError(DAG, DL, VT);
Matt Arsenaulte0132462016-01-30 05:19:45 +00002406
Tom Stellardec2e43c2014-09-22 15:35:29 +00002407 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
2408 SI::KernelInputOffsets::GLOBAL_SIZE_Y, false);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002409 case Intrinsic::r600_read_global_size_z:
Matt Arsenaulte0132462016-01-30 05:19:45 +00002410 if (Subtarget->isAmdHsaOS())
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002411 return emitNonHSAIntrinsicError(DAG, DL, VT);
Matt Arsenaulte0132462016-01-30 05:19:45 +00002412
Tom Stellardec2e43c2014-09-22 15:35:29 +00002413 return LowerParameter(DAG, VT, VT, DL, DAG.getEntryNode(),
2414 SI::KernelInputOffsets::GLOBAL_SIZE_Z, false);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002415 case Intrinsic::r600_read_local_size_x:
Matt Arsenaulte0132462016-01-30 05:19:45 +00002416 if (Subtarget->isAmdHsaOS())
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002417 return emitNonHSAIntrinsicError(DAG, DL, VT);
Matt Arsenaulte0132462016-01-30 05:19:45 +00002418
Matt Arsenaultff6da2f2015-11-30 21:15:45 +00002419 return lowerImplicitZextParam(DAG, Op, MVT::i16,
2420 SI::KernelInputOffsets::LOCAL_SIZE_X);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002421 case Intrinsic::r600_read_local_size_y:
Matt Arsenaulte0132462016-01-30 05:19:45 +00002422 if (Subtarget->isAmdHsaOS())
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002423 return emitNonHSAIntrinsicError(DAG, DL, VT);
Matt Arsenaulte0132462016-01-30 05:19:45 +00002424
Matt Arsenaultff6da2f2015-11-30 21:15:45 +00002425 return lowerImplicitZextParam(DAG, Op, MVT::i16,
2426 SI::KernelInputOffsets::LOCAL_SIZE_Y);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002427 case Intrinsic::r600_read_local_size_z:
Matt Arsenaulte0132462016-01-30 05:19:45 +00002428 if (Subtarget->isAmdHsaOS())
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00002429 return emitNonHSAIntrinsicError(DAG, DL, VT);
Matt Arsenaulte0132462016-01-30 05:19:45 +00002430
Matt Arsenaultff6da2f2015-11-30 21:15:45 +00002431 return lowerImplicitZextParam(DAG, Op, MVT::i16,
2432 SI::KernelInputOffsets::LOCAL_SIZE_Z);
Matt Arsenault43976df2016-01-30 04:25:19 +00002433 case Intrinsic::amdgcn_workgroup_id_x:
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002434 case Intrinsic::r600_read_tgid_x:
Marek Olsak79c05872016-11-25 17:37:09 +00002435 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32_XM0RegClass,
Matt Arsenaultac234b62015-11-30 21:15:57 +00002436 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_X), VT);
Matt Arsenault43976df2016-01-30 04:25:19 +00002437 case Intrinsic::amdgcn_workgroup_id_y:
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002438 case Intrinsic::r600_read_tgid_y:
Marek Olsak79c05872016-11-25 17:37:09 +00002439 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32_XM0RegClass,
Matt Arsenaultac234b62015-11-30 21:15:57 +00002440 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Y), VT);
Matt Arsenault43976df2016-01-30 04:25:19 +00002441 case Intrinsic::amdgcn_workgroup_id_z:
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002442 case Intrinsic::r600_read_tgid_z:
Marek Olsak79c05872016-11-25 17:37:09 +00002443 return CreateLiveInRegister(DAG, &AMDGPU::SReg_32_XM0RegClass,
Matt Arsenaultac234b62015-11-30 21:15:57 +00002444 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKGROUP_ID_Z), VT);
Matt Arsenault43976df2016-01-30 04:25:19 +00002445 case Intrinsic::amdgcn_workitem_id_x:
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002446 case Intrinsic::r600_read_tidig_x:
Tom Stellard45c0b3a2015-01-07 20:59:25 +00002447 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
Matt Arsenaultac234b62015-11-30 21:15:57 +00002448 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_X), VT);
Matt Arsenault43976df2016-01-30 04:25:19 +00002449 case Intrinsic::amdgcn_workitem_id_y:
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002450 case Intrinsic::r600_read_tidig_y:
Tom Stellard45c0b3a2015-01-07 20:59:25 +00002451 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
Matt Arsenaultac234b62015-11-30 21:15:57 +00002452 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Y), VT);
Matt Arsenault43976df2016-01-30 04:25:19 +00002453 case Intrinsic::amdgcn_workitem_id_z:
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002454 case Intrinsic::r600_read_tidig_z:
Tom Stellard45c0b3a2015-01-07 20:59:25 +00002455 return CreateLiveInRegister(DAG, &AMDGPU::VGPR_32RegClass,
Matt Arsenaultac234b62015-11-30 21:15:57 +00002456 TRI->getPreloadedValue(MF, SIRegisterInfo::WORKITEM_ID_Z), VT);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002457 case AMDGPUIntrinsic::SI_load_const: {
2458 SDValue Ops[] = {
2459 Op.getOperand(1),
2460 Op.getOperand(2)
2461 };
2462
2463 MachineMemOperand *MMO = MF.getMachineMemOperand(
Justin Lebaradbf09e2016-09-11 01:38:58 +00002464 MachinePointerInfo(),
2465 MachineMemOperand::MOLoad | MachineMemOperand::MODereferenceable |
2466 MachineMemOperand::MOInvariant,
2467 VT.getStoreSize(), 4);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002468 return DAG.getMemIntrinsicNode(AMDGPUISD::LOAD_CONSTANT, DL,
2469 Op->getVTList(), Ops, VT, MMO);
2470 }
Matt Arsenaulta1fe17c2016-07-19 23:16:53 +00002471 case AMDGPUIntrinsic::amdgcn_fdiv_fast: {
2472 return lowerFDIV_FAST(Op, DAG);
2473 }
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002474 case AMDGPUIntrinsic::SI_vs_load_input:
2475 return DAG.getNode(AMDGPUISD::LOAD_INPUT, DL, VT,
2476 Op.getOperand(1),
2477 Op.getOperand(2),
2478 Op.getOperand(3));
Marek Olsak43650e42015-03-24 13:40:08 +00002479
Tom Stellard2a9d9472015-05-12 15:00:46 +00002480 case AMDGPUIntrinsic::SI_fs_constant: {
2481 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
2482 SDValue Glue = M0.getValue(1);
2483 return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32,
2484 DAG.getConstant(2, DL, MVT::i32), // P0
2485 Op.getOperand(1), Op.getOperand(2), Glue);
2486 }
Marek Olsak6f6d3182015-10-29 15:29:09 +00002487 case AMDGPUIntrinsic::SI_packf16:
2488 if (Op.getOperand(1).isUndef() && Op.getOperand(2).isUndef())
2489 return DAG.getUNDEF(MVT::i32);
2490 return Op;
Tom Stellard2a9d9472015-05-12 15:00:46 +00002491 case AMDGPUIntrinsic::SI_fs_interp: {
2492 SDValue IJ = Op.getOperand(4);
2493 SDValue I = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
2494 DAG.getConstant(0, DL, MVT::i32));
2495 SDValue J = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, IJ,
2496 DAG.getConstant(1, DL, MVT::i32));
Tom Stellard1473f072016-11-26 02:26:04 +00002497 I = DAG.getNode(ISD::BITCAST, DL, MVT::f32, I);
2498 J = DAG.getNode(ISD::BITCAST, DL, MVT::f32, J);
Tom Stellard2a9d9472015-05-12 15:00:46 +00002499 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(3));
2500 SDValue Glue = M0.getValue(1);
2501 SDValue P1 = DAG.getNode(AMDGPUISD::INTERP_P1, DL,
2502 DAG.getVTList(MVT::f32, MVT::Glue),
2503 I, Op.getOperand(1), Op.getOperand(2), Glue);
2504 Glue = SDValue(P1.getNode(), 1);
2505 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, P1, J,
2506 Op.getOperand(1), Op.getOperand(2), Glue);
2507 }
Tom Stellard2187bb82016-12-06 23:52:13 +00002508 case Intrinsic::amdgcn_interp_mov: {
2509 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
2510 SDValue Glue = M0.getValue(1);
2511 return DAG.getNode(AMDGPUISD::INTERP_MOV, DL, MVT::f32, Op.getOperand(1),
2512 Op.getOperand(2), Op.getOperand(3), Glue);
2513 }
Tom Stellardad7d03d2015-12-15 17:02:49 +00002514 case Intrinsic::amdgcn_interp_p1: {
2515 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(4));
2516 SDValue Glue = M0.getValue(1);
2517 return DAG.getNode(AMDGPUISD::INTERP_P1, DL, MVT::f32, Op.getOperand(1),
2518 Op.getOperand(2), Op.getOperand(3), Glue);
2519 }
2520 case Intrinsic::amdgcn_interp_p2: {
2521 SDValue M0 = copyToM0(DAG, DAG.getEntryNode(), DL, Op.getOperand(5));
2522 SDValue Glue = SDValue(M0.getNode(), 1);
2523 return DAG.getNode(AMDGPUISD::INTERP_P2, DL, MVT::f32, Op.getOperand(1),
2524 Op.getOperand(2), Op.getOperand(3), Op.getOperand(4),
2525 Glue);
2526 }
Matt Arsenaultce56a0e2016-02-13 01:19:56 +00002527 case Intrinsic::amdgcn_sin:
2528 return DAG.getNode(AMDGPUISD::SIN_HW, DL, VT, Op.getOperand(1));
2529
2530 case Intrinsic::amdgcn_cos:
2531 return DAG.getNode(AMDGPUISD::COS_HW, DL, VT, Op.getOperand(1));
2532
2533 case Intrinsic::amdgcn_log_clamp: {
Matt Arsenault43e92fe2016-06-24 06:30:11 +00002534 if (Subtarget->getGeneration() < SISubtarget::VOLCANIC_ISLANDS)
Matt Arsenaultce56a0e2016-02-13 01:19:56 +00002535 return SDValue();
2536
2537 DiagnosticInfoUnsupported BadIntrin(
2538 *MF.getFunction(), "intrinsic not supported on subtarget",
2539 DL.getDebugLoc());
2540 DAG.getContext()->diagnose(BadIntrin);
2541 return DAG.getUNDEF(VT);
2542 }
Matt Arsenaultf75257a2016-01-23 05:32:20 +00002543 case Intrinsic::amdgcn_ldexp:
2544 return DAG.getNode(AMDGPUISD::LDEXP, DL, VT,
2545 Op.getOperand(1), Op.getOperand(2));
Matt Arsenault74015162016-05-28 00:19:52 +00002546
2547 case Intrinsic::amdgcn_fract:
2548 return DAG.getNode(AMDGPUISD::FRACT, DL, VT, Op.getOperand(1));
2549
Matt Arsenaultf75257a2016-01-23 05:32:20 +00002550 case Intrinsic::amdgcn_class:
2551 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, VT,
2552 Op.getOperand(1), Op.getOperand(2));
2553 case Intrinsic::amdgcn_div_fmas:
2554 return DAG.getNode(AMDGPUISD::DIV_FMAS, DL, VT,
2555 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3),
2556 Op.getOperand(4));
2557
2558 case Intrinsic::amdgcn_div_fixup:
2559 return DAG.getNode(AMDGPUISD::DIV_FIXUP, DL, VT,
2560 Op.getOperand(1), Op.getOperand(2), Op.getOperand(3));
2561
2562 case Intrinsic::amdgcn_trig_preop:
2563 return DAG.getNode(AMDGPUISD::TRIG_PREOP, DL, VT,
2564 Op.getOperand(1), Op.getOperand(2));
2565 case Intrinsic::amdgcn_div_scale: {
2566 // 3rd parameter required to be a constant.
2567 const ConstantSDNode *Param = dyn_cast<ConstantSDNode>(Op.getOperand(3));
2568 if (!Param)
2569 return DAG.getUNDEF(VT);
2570
2571 // Translate to the operands expected by the machine instruction. The
2572 // first parameter must be the same as the first instruction.
2573 SDValue Numerator = Op.getOperand(1);
2574 SDValue Denominator = Op.getOperand(2);
2575
2576 // Note this order is opposite of the machine instruction's operations,
2577 // which is s0.f = Quotient, s1.f = Denominator, s2.f = Numerator. The
2578 // intrinsic has the numerator as the first operand to match a normal
2579 // division operation.
2580
2581 SDValue Src0 = Param->isAllOnesValue() ? Numerator : Denominator;
2582
2583 return DAG.getNode(AMDGPUISD::DIV_SCALE, DL, Op->getVTList(), Src0,
2584 Denominator, Numerator);
2585 }
Wei Ding07e03712016-07-28 16:42:13 +00002586 case Intrinsic::amdgcn_icmp: {
2587 const auto *CD = dyn_cast<ConstantSDNode>(Op.getOperand(3));
2588 int CondCode = CD->getSExtValue();
2589
2590 if (CondCode < ICmpInst::Predicate::FIRST_ICMP_PREDICATE ||
NAKAMURA Takumi59a20642016-08-22 00:58:04 +00002591 CondCode >= ICmpInst::Predicate::BAD_ICMP_PREDICATE)
Wei Ding07e03712016-07-28 16:42:13 +00002592 return DAG.getUNDEF(VT);
2593
NAKAMURA Takumi59a20642016-08-22 00:58:04 +00002594 ICmpInst::Predicate IcInput = static_cast<ICmpInst::Predicate>(CondCode);
Wei Ding07e03712016-07-28 16:42:13 +00002595 ISD::CondCode CCOpcode = getICmpCondCode(IcInput);
2596 return DAG.getNode(AMDGPUISD::SETCC, DL, VT, Op.getOperand(1),
2597 Op.getOperand(2), DAG.getCondCode(CCOpcode));
2598 }
2599 case Intrinsic::amdgcn_fcmp: {
2600 const auto *CD = dyn_cast<ConstantSDNode>(Op.getOperand(3));
2601 int CondCode = CD->getSExtValue();
2602
2603 if (CondCode <= FCmpInst::Predicate::FCMP_FALSE ||
NAKAMURA Takumi59a20642016-08-22 00:58:04 +00002604 CondCode >= FCmpInst::Predicate::FCMP_TRUE)
Wei Ding07e03712016-07-28 16:42:13 +00002605 return DAG.getUNDEF(VT);
2606
NAKAMURA Takumi59a20642016-08-22 00:58:04 +00002607 FCmpInst::Predicate IcInput = static_cast<FCmpInst::Predicate>(CondCode);
Wei Ding07e03712016-07-28 16:42:13 +00002608 ISD::CondCode CCOpcode = getFCmpCondCode(IcInput);
2609 return DAG.getNode(AMDGPUISD::SETCC, DL, VT, Op.getOperand(1),
2610 Op.getOperand(2), DAG.getCondCode(CCOpcode));
2611 }
Matt Arsenault32fc5272016-07-26 16:45:45 +00002612 case Intrinsic::amdgcn_fmul_legacy:
2613 return DAG.getNode(AMDGPUISD::FMUL_LEGACY, DL, VT,
2614 Op.getOperand(1), Op.getOperand(2));
Matt Arsenaultc96e1de2016-07-18 18:35:05 +00002615 case Intrinsic::amdgcn_sffbh:
2616 case AMDGPUIntrinsic::AMDGPU_flbit_i32: // Legacy name.
2617 return DAG.getNode(AMDGPUISD::FFBH_I32, DL, VT, Op.getOperand(1));
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002618 default:
2619 return AMDGPUTargetLowering::LowerOperation(Op, DAG);
2620 }
2621}
2622
Matt Arsenaulta9dbdca2016-04-12 14:05:04 +00002623SDValue SITargetLowering::LowerINTRINSIC_W_CHAIN(SDValue Op,
2624 SelectionDAG &DAG) const {
2625 unsigned IntrID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2626 switch (IntrID) {
2627 case Intrinsic::amdgcn_atomic_inc:
2628 case Intrinsic::amdgcn_atomic_dec: {
2629 MemSDNode *M = cast<MemSDNode>(Op);
2630 unsigned Opc = (IntrID == Intrinsic::amdgcn_atomic_inc) ?
2631 AMDGPUISD::ATOMIC_INC : AMDGPUISD::ATOMIC_DEC;
2632 SDValue Ops[] = {
2633 M->getOperand(0), // Chain
2634 M->getOperand(2), // Ptr
2635 M->getOperand(3) // Value
2636 };
2637
2638 return DAG.getMemIntrinsicNode(Opc, SDLoc(Op), M->getVTList(), Ops,
2639 M->getMemoryVT(), M->getMemOperand());
2640 }
2641 default:
2642 return SDValue();
2643 }
2644}
2645
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002646SDValue SITargetLowering::LowerINTRINSIC_VOID(SDValue Op,
2647 SelectionDAG &DAG) const {
2648 MachineFunction &MF = DAG.getMachineFunction();
Tom Stellardfc92e772015-05-12 14:18:14 +00002649 SDLoc DL(Op);
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002650 SDValue Chain = Op.getOperand(0);
2651 unsigned IntrinsicID = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
2652
2653 switch (IntrinsicID) {
Tom Stellardfc92e772015-05-12 14:18:14 +00002654 case AMDGPUIntrinsic::SI_sendmsg: {
2655 Chain = copyToM0(DAG, Chain, DL, Op.getOperand(3));
2656 SDValue Glue = Chain.getValue(1);
2657 return DAG.getNode(AMDGPUISD::SENDMSG, DL, MVT::Other, Chain,
2658 Op.getOperand(2), Glue);
2659 }
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002660 case AMDGPUIntrinsic::SI_tbuffer_store: {
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002661 SDValue Ops[] = {
2662 Chain,
2663 Op.getOperand(2),
2664 Op.getOperand(3),
2665 Op.getOperand(4),
2666 Op.getOperand(5),
2667 Op.getOperand(6),
2668 Op.getOperand(7),
2669 Op.getOperand(8),
2670 Op.getOperand(9),
2671 Op.getOperand(10),
2672 Op.getOperand(11),
2673 Op.getOperand(12),
2674 Op.getOperand(13),
2675 Op.getOperand(14)
2676 };
2677
2678 EVT VT = Op.getOperand(3).getValueType();
2679
2680 MachineMemOperand *MMO = MF.getMachineMemOperand(
2681 MachinePointerInfo(),
2682 MachineMemOperand::MOStore,
2683 VT.getStoreSize(), 4);
2684 return DAG.getMemIntrinsicNode(AMDGPUISD::TBUFFER_STORE_FORMAT, DL,
2685 Op->getVTList(), Ops, VT, MMO);
2686 }
Matt Arsenault00568682016-07-13 06:04:22 +00002687 case AMDGPUIntrinsic::AMDGPU_kill: {
Matt Arsenault03006fd2016-07-19 16:27:56 +00002688 SDValue Src = Op.getOperand(2);
2689 if (const ConstantFPSDNode *K = dyn_cast<ConstantFPSDNode>(Src)) {
Matt Arsenault00568682016-07-13 06:04:22 +00002690 if (!K->isNegative())
2691 return Chain;
Matt Arsenault03006fd2016-07-19 16:27:56 +00002692
2693 SDValue NegOne = DAG.getTargetConstant(FloatToBits(-1.0f), DL, MVT::i32);
2694 return DAG.getNode(AMDGPUISD::KILL, DL, MVT::Other, Chain, NegOne);
Matt Arsenault00568682016-07-13 06:04:22 +00002695 }
2696
Matt Arsenault03006fd2016-07-19 16:27:56 +00002697 SDValue Cast = DAG.getNode(ISD::BITCAST, DL, MVT::i32, Src);
2698 return DAG.getNode(AMDGPUISD::KILL, DL, MVT::Other, Chain, Cast);
Matt Arsenault00568682016-07-13 06:04:22 +00002699 }
Matt Arsenault7bee6ac2016-12-05 20:23:10 +00002700 case AMDGPUIntrinsic::SI_export: {
2701 const ConstantSDNode *En = cast<ConstantSDNode>(Op.getOperand(2));
2702 const ConstantSDNode *VM = cast<ConstantSDNode>(Op.getOperand(3));
2703 const ConstantSDNode *Done = cast<ConstantSDNode>(Op.getOperand(4));
2704 const ConstantSDNode *Tgt = cast<ConstantSDNode>(Op.getOperand(5));
2705 const ConstantSDNode *Compr = cast<ConstantSDNode>(Op.getOperand(6));
2706
2707 const SDValue Ops[] = {
2708 Chain,
2709 DAG.getTargetConstant(En->getZExtValue(), DL, MVT::i8),
2710 DAG.getTargetConstant(VM->getZExtValue(), DL, MVT::i1),
2711 DAG.getTargetConstant(Tgt->getZExtValue(), DL, MVT::i8),
2712 DAG.getTargetConstant(Compr->getZExtValue(), DL, MVT::i1),
2713 Op.getOperand(7), // src0
2714 Op.getOperand(8), // src1
2715 Op.getOperand(9), // src2
2716 Op.getOperand(10) // src3
2717 };
2718
2719 unsigned Opc = Done->isNullValue() ?
2720 AMDGPUISD::EXPORT : AMDGPUISD::EXPORT_DONE;
2721 return DAG.getNode(Opc, DL, Op->getVTList(), Ops);
2722 }
Matt Arsenaulta5789bb2014-07-26 06:23:37 +00002723 default:
2724 return SDValue();
2725 }
2726}
2727
Tom Stellard81d871d2013-11-13 23:36:50 +00002728SDValue SITargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
2729 SDLoc DL(Op);
2730 LoadSDNode *Load = cast<LoadSDNode>(Op);
Matt Arsenault6dfda962016-02-10 18:21:39 +00002731 ISD::LoadExtType ExtType = Load->getExtensionType();
Matt Arsenaulta1436412016-02-10 18:21:45 +00002732 EVT MemVT = Load->getMemoryVT();
Matt Arsenault6dfda962016-02-10 18:21:39 +00002733
Matt Arsenaulta1436412016-02-10 18:21:45 +00002734 if (ExtType == ISD::NON_EXTLOAD && MemVT.getSizeInBits() < 32) {
Matt Arsenault6dfda962016-02-10 18:21:39 +00002735 // FIXME: Copied from PPC
2736 // First, load into 32 bits, then truncate to 1 bit.
2737
2738 SDValue Chain = Load->getChain();
2739 SDValue BasePtr = Load->getBasePtr();
2740 MachineMemOperand *MMO = Load->getMemOperand();
2741
Tom Stellard115a6152016-11-10 16:02:37 +00002742 EVT RealMemVT = (MemVT == MVT::i1) ? MVT::i8 : MVT::i16;
2743
Matt Arsenault6dfda962016-02-10 18:21:39 +00002744 SDValue NewLD = DAG.getExtLoad(ISD::EXTLOAD, DL, MVT::i32, Chain,
Tom Stellard115a6152016-11-10 16:02:37 +00002745 BasePtr, RealMemVT, MMO);
Matt Arsenault6dfda962016-02-10 18:21:39 +00002746
2747 SDValue Ops[] = {
Matt Arsenaulta1436412016-02-10 18:21:45 +00002748 DAG.getNode(ISD::TRUNCATE, DL, MemVT, NewLD),
Matt Arsenault6dfda962016-02-10 18:21:39 +00002749 NewLD.getValue(1)
2750 };
2751
2752 return DAG.getMergeValues(Ops, DL);
2753 }
Tom Stellard81d871d2013-11-13 23:36:50 +00002754
Matt Arsenaulta1436412016-02-10 18:21:45 +00002755 if (!MemVT.isVector())
2756 return SDValue();
Matt Arsenault4d801cd2015-11-24 12:05:03 +00002757
Matt Arsenaulta1436412016-02-10 18:21:45 +00002758 assert(Op.getValueType().getVectorElementType() == MVT::i32 &&
2759 "Custom lowering for non-i32 vectors hasn't been implemented.");
Matt Arsenault4d801cd2015-11-24 12:05:03 +00002760
Matt Arsenaultbcdfee72016-05-02 20:13:51 +00002761 unsigned AS = Load->getAddressSpace();
2762 if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), MemVT,
2763 AS, Load->getAlignment())) {
2764 SDValue Ops[2];
2765 std::tie(Ops[0], Ops[1]) = expandUnalignedLoad(Load, DAG);
2766 return DAG.getMergeValues(Ops, DL);
2767 }
2768
Tom Stellardf8e6eaf2016-10-26 14:38:47 +00002769 MachineFunction &MF = DAG.getMachineFunction();
2770 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
2771 // If there is a possibilty that flat instruction access scratch memory
2772 // then we need to use the same legalization rules we use for private.
2773 if (AS == AMDGPUAS::FLAT_ADDRESS)
2774 AS = MFI->hasFlatScratchInit() ?
2775 AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS;
2776
Matt Arsenaultbcdfee72016-05-02 20:13:51 +00002777 unsigned NumElements = MemVT.getVectorNumElements();
2778 switch (AS) {
Matt Arsenaulta1436412016-02-10 18:21:45 +00002779 case AMDGPUAS::CONSTANT_ADDRESS:
2780 if (isMemOpUniform(Load))
2781 return SDValue();
2782 // Non-uniform loads will be selected to MUBUF instructions, so they
Alexander Timofeev18009562016-12-08 17:28:47 +00002783 // have the same legalization requirements as global and private
Matt Arsenaulta1436412016-02-10 18:21:45 +00002784 // loads.
2785 //
Justin Bognerb03fd122016-08-17 05:10:15 +00002786 LLVM_FALLTHROUGH;
Alexander Timofeev18009562016-12-08 17:28:47 +00002787 case AMDGPUAS::GLOBAL_ADDRESS: {
Alexander Timofeeva57511c2016-12-15 15:17:19 +00002788 if (Subtarget->getScalarizeGlobalBehavior() && isMemOpUniform(Load) &&
2789 isMemOpHasNoClobberedMemOperand(Load))
Alexander Timofeev18009562016-12-08 17:28:47 +00002790 return SDValue();
2791 // Non-uniform loads will be selected to MUBUF instructions, so they
2792 // have the same legalization requirements as global and private
2793 // loads.
2794 //
2795 }
2796 LLVM_FALLTHROUGH;
Matt Arsenaultf2ddbf02016-02-13 04:18:53 +00002797 case AMDGPUAS::FLAT_ADDRESS:
2798 if (NumElements > 4)
Matt Arsenaulta1436412016-02-10 18:21:45 +00002799 return SplitVectorLoad(Op, DAG);
2800 // v4 loads are supported for private and global memory.
2801 return SDValue();
Matt Arsenaultf2ddbf02016-02-13 04:18:53 +00002802 case AMDGPUAS::PRIVATE_ADDRESS: {
2803 // Depending on the setting of the private_element_size field in the
2804 // resource descriptor, we can only make private accesses up to a certain
2805 // size.
2806 switch (Subtarget->getMaxPrivateElementSize()) {
2807 case 4:
Matt Arsenault9c499c32016-04-14 23:31:26 +00002808 return scalarizeVectorLoad(Load, DAG);
Matt Arsenaultf2ddbf02016-02-13 04:18:53 +00002809 case 8:
2810 if (NumElements > 2)
2811 return SplitVectorLoad(Op, DAG);
2812 return SDValue();
2813 case 16:
2814 // Same as global/flat
2815 if (NumElements > 4)
2816 return SplitVectorLoad(Op, DAG);
2817 return SDValue();
2818 default:
2819 llvm_unreachable("unsupported private_element_size");
2820 }
2821 }
Matt Arsenaultbcdfee72016-05-02 20:13:51 +00002822 case AMDGPUAS::LOCAL_ADDRESS: {
2823 if (NumElements > 2)
2824 return SplitVectorLoad(Op, DAG);
2825
2826 if (NumElements == 2)
2827 return SDValue();
2828
Matt Arsenaulta1436412016-02-10 18:21:45 +00002829 // If properly aligned, if we split we might be able to use ds_read_b64.
2830 return SplitVectorLoad(Op, DAG);
Matt Arsenaultbcdfee72016-05-02 20:13:51 +00002831 }
Matt Arsenaulta1436412016-02-10 18:21:45 +00002832 default:
2833 return SDValue();
Tom Stellarde9373602014-01-22 19:24:14 +00002834 }
Tom Stellard81d871d2013-11-13 23:36:50 +00002835}
2836
Tom Stellard0ec134f2014-02-04 17:18:40 +00002837SDValue SITargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
2838 if (Op.getValueType() != MVT::i64)
2839 return SDValue();
2840
2841 SDLoc DL(Op);
2842 SDValue Cond = Op.getOperand(0);
Tom Stellard0ec134f2014-02-04 17:18:40 +00002843
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00002844 SDValue Zero = DAG.getConstant(0, DL, MVT::i32);
2845 SDValue One = DAG.getConstant(1, DL, MVT::i32);
Tom Stellard0ec134f2014-02-04 17:18:40 +00002846
Tom Stellard7ea3d6d2014-03-31 14:01:55 +00002847 SDValue LHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(1));
2848 SDValue RHS = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Op.getOperand(2));
2849
2850 SDValue Lo0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, Zero);
2851 SDValue Lo1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, Zero);
Tom Stellard0ec134f2014-02-04 17:18:40 +00002852
2853 SDValue Lo = DAG.getSelect(DL, MVT::i32, Cond, Lo0, Lo1);
2854
Tom Stellard7ea3d6d2014-03-31 14:01:55 +00002855 SDValue Hi0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, LHS, One);
2856 SDValue Hi1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, MVT::i32, RHS, One);
Tom Stellard0ec134f2014-02-04 17:18:40 +00002857
2858 SDValue Hi = DAG.getSelect(DL, MVT::i32, Cond, Hi0, Hi1);
2859
Ahmed Bougacha128f8732016-04-26 21:15:30 +00002860 SDValue Res = DAG.getBuildVector(MVT::v2i32, DL, {Lo, Hi});
Tom Stellard7ea3d6d2014-03-31 14:01:55 +00002861 return DAG.getNode(ISD::BITCAST, DL, MVT::i64, Res);
Tom Stellard0ec134f2014-02-04 17:18:40 +00002862}
2863
Matt Arsenault22ca3f82014-07-15 23:50:10 +00002864// Catch division cases where we can use shortcuts with rcp and rsq
2865// instructions.
Matt Arsenaulta1fe17c2016-07-19 23:16:53 +00002866SDValue SITargetLowering::lowerFastUnsafeFDIV(SDValue Op,
2867 SelectionDAG &DAG) const {
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +00002868 SDLoc SL(Op);
2869 SDValue LHS = Op.getOperand(0);
2870 SDValue RHS = Op.getOperand(1);
2871 EVT VT = Op.getValueType();
Matt Arsenault22ca3f82014-07-15 23:50:10 +00002872 bool Unsafe = DAG.getTarget().Options.UnsafeFPMath;
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +00002873
2874 if (const ConstantFPSDNode *CLHS = dyn_cast<ConstantFPSDNode>(LHS)) {
Matt Arsenault979902b2016-08-02 22:25:04 +00002875 if ((Unsafe || (VT == MVT::f32 && !Subtarget->hasFP32Denormals()))) {
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +00002876
Matt Arsenault979902b2016-08-02 22:25:04 +00002877 if (CLHS->isExactlyValue(1.0)) {
2878 // v_rcp_f32 and v_rsq_f32 do not support denormals, and according to
2879 // the CI documentation has a worst case error of 1 ulp.
2880 // OpenCL requires <= 2.5 ulp for 1.0 / x, so it should always be OK to
2881 // use it as long as we aren't trying to use denormals.
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +00002882
Matt Arsenault979902b2016-08-02 22:25:04 +00002883 // 1.0 / sqrt(x) -> rsq(x)
2884 //
2885 // XXX - Is UnsafeFPMath sufficient to do this for f64? The maximum ULP
2886 // error seems really high at 2^29 ULP.
2887 if (RHS.getOpcode() == ISD::FSQRT)
2888 return DAG.getNode(AMDGPUISD::RSQ, SL, VT, RHS.getOperand(0));
2889
2890 // 1.0 / x -> rcp(x)
2891 return DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
2892 }
2893
2894 // Same as for 1.0, but expand the sign out of the constant.
2895 if (CLHS->isExactlyValue(-1.0)) {
2896 // -1.0 / x -> rcp (fneg x)
2897 SDValue FNegRHS = DAG.getNode(ISD::FNEG, SL, VT, RHS);
2898 return DAG.getNode(AMDGPUISD::RCP, SL, VT, FNegRHS);
2899 }
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +00002900 }
2901 }
2902
Wei Dinged0f97f2016-06-09 19:17:15 +00002903 const SDNodeFlags *Flags = Op->getFlags();
2904
2905 if (Unsafe || Flags->hasAllowReciprocal()) {
Matt Arsenault22ca3f82014-07-15 23:50:10 +00002906 // Turn into multiply by the reciprocal.
2907 // x / y -> x * (1.0 / y)
Sanjay Patela2607012015-09-16 16:31:21 +00002908 SDNodeFlags Flags;
2909 Flags.setUnsafeAlgebra(true);
Matt Arsenault22ca3f82014-07-15 23:50:10 +00002910 SDValue Recip = DAG.getNode(AMDGPUISD::RCP, SL, VT, RHS);
Sanjay Patela2607012015-09-16 16:31:21 +00002911 return DAG.getNode(ISD::FMUL, SL, VT, LHS, Recip, &Flags);
Matt Arsenault22ca3f82014-07-15 23:50:10 +00002912 }
2913
2914 return SDValue();
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +00002915}
2916
Tom Stellard8485fa02016-12-07 02:42:15 +00002917static SDValue getFPBinOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL,
2918 EVT VT, SDValue A, SDValue B, SDValue GlueChain) {
2919 if (GlueChain->getNumValues() <= 1) {
2920 return DAG.getNode(Opcode, SL, VT, A, B);
2921 }
2922
2923 assert(GlueChain->getNumValues() == 3);
2924
2925 SDVTList VTList = DAG.getVTList(VT, MVT::Other, MVT::Glue);
2926 switch (Opcode) {
2927 default: llvm_unreachable("no chain equivalent for opcode");
2928 case ISD::FMUL:
2929 Opcode = AMDGPUISD::FMUL_W_CHAIN;
2930 break;
2931 }
2932
2933 return DAG.getNode(Opcode, SL, VTList, GlueChain.getValue(1), A, B,
2934 GlueChain.getValue(2));
2935}
2936
2937static SDValue getFPTernOp(SelectionDAG &DAG, unsigned Opcode, const SDLoc &SL,
2938 EVT VT, SDValue A, SDValue B, SDValue C,
2939 SDValue GlueChain) {
2940 if (GlueChain->getNumValues() <= 1) {
2941 return DAG.getNode(Opcode, SL, VT, A, B, C);
2942 }
2943
2944 assert(GlueChain->getNumValues() == 3);
2945
2946 SDVTList VTList = DAG.getVTList(VT, MVT::Other, MVT::Glue);
2947 switch (Opcode) {
2948 default: llvm_unreachable("no chain equivalent for opcode");
2949 case ISD::FMA:
2950 Opcode = AMDGPUISD::FMA_W_CHAIN;
2951 break;
2952 }
2953
2954 return DAG.getNode(Opcode, SL, VTList, GlueChain.getValue(1), A, B, C,
2955 GlueChain.getValue(2));
2956}
2957
Matt Arsenaulta1fe17c2016-07-19 23:16:53 +00002958// Faster 2.5 ULP division that does not support denormals.
2959SDValue SITargetLowering::lowerFDIV_FAST(SDValue Op, SelectionDAG &DAG) const {
2960 SDLoc SL(Op);
2961 SDValue LHS = Op.getOperand(1);
2962 SDValue RHS = Op.getOperand(2);
2963
2964 SDValue r1 = DAG.getNode(ISD::FABS, SL, MVT::f32, RHS);
2965
2966 const APFloat K0Val(BitsToFloat(0x6f800000));
2967 const SDValue K0 = DAG.getConstantFP(K0Val, SL, MVT::f32);
2968
2969 const APFloat K1Val(BitsToFloat(0x2f800000));
2970 const SDValue K1 = DAG.getConstantFP(K1Val, SL, MVT::f32);
2971
2972 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
2973
2974 EVT SetCCVT =
2975 getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), MVT::f32);
2976
2977 SDValue r2 = DAG.getSetCC(SL, SetCCVT, r1, K0, ISD::SETOGT);
2978
2979 SDValue r3 = DAG.getNode(ISD::SELECT, SL, MVT::f32, r2, K1, One);
2980
2981 // TODO: Should this propagate fast-math-flags?
2982 r1 = DAG.getNode(ISD::FMUL, SL, MVT::f32, RHS, r3);
2983
2984 // rcp does not support denormals.
2985 SDValue r0 = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32, r1);
2986
2987 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f32, LHS, r0);
2988
2989 return DAG.getNode(ISD::FMUL, SL, MVT::f32, r3, Mul);
2990}
2991
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +00002992SDValue SITargetLowering::LowerFDIV32(SDValue Op, SelectionDAG &DAG) const {
Matt Arsenaulta1fe17c2016-07-19 23:16:53 +00002993 if (SDValue FastLowered = lowerFastUnsafeFDIV(Op, DAG))
Eric Christopher538d09d02016-06-07 20:27:12 +00002994 return FastLowered;
Matt Arsenault22ca3f82014-07-15 23:50:10 +00002995
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +00002996 SDLoc SL(Op);
2997 SDValue LHS = Op.getOperand(0);
2998 SDValue RHS = Op.getOperand(1);
2999
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003000 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f32);
Matt Arsenault37fefd62016-06-10 02:18:02 +00003001
Wei Dinged0f97f2016-06-09 19:17:15 +00003002 SDVTList ScaleVT = DAG.getVTList(MVT::f32, MVT::i1);
Matt Arsenault37fefd62016-06-10 02:18:02 +00003003
Tom Stellard8485fa02016-12-07 02:42:15 +00003004 SDValue DenominatorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT,
3005 RHS, RHS, LHS);
3006 SDValue NumeratorScaled = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT,
3007 LHS, RHS, LHS);
Matt Arsenault37fefd62016-06-10 02:18:02 +00003008
Matt Arsenaultdfec5ce2016-07-09 07:48:11 +00003009 // Denominator is scaled to not be denormal, so using rcp is ok.
Tom Stellard8485fa02016-12-07 02:42:15 +00003010 SDValue ApproxRcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f32,
3011 DenominatorScaled);
3012 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f32,
3013 DenominatorScaled);
Matt Arsenault37fefd62016-06-10 02:18:02 +00003014
Tom Stellard8485fa02016-12-07 02:42:15 +00003015 const unsigned Denorm32Reg = AMDGPU::Hwreg::ID_MODE |
3016 (4 << AMDGPU::Hwreg::OFFSET_SHIFT_) |
3017 (1 << AMDGPU::Hwreg::WIDTH_M1_SHIFT_);
Matt Arsenault37fefd62016-06-10 02:18:02 +00003018
Tom Stellard8485fa02016-12-07 02:42:15 +00003019 const SDValue BitField = DAG.getTargetConstant(Denorm32Reg, SL, MVT::i16);
Matt Arsenault37fefd62016-06-10 02:18:02 +00003020
Tom Stellard8485fa02016-12-07 02:42:15 +00003021 if (!Subtarget->hasFP32Denormals()) {
3022 SDVTList BindParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
3023 const SDValue EnableDenormValue = DAG.getConstant(FP_DENORM_FLUSH_NONE,
3024 SL, MVT::i32);
3025 SDValue EnableDenorm = DAG.getNode(AMDGPUISD::SETREG, SL, BindParamVTs,
3026 DAG.getEntryNode(),
3027 EnableDenormValue, BitField);
3028 SDValue Ops[3] = {
3029 NegDivScale0,
3030 EnableDenorm.getValue(0),
3031 EnableDenorm.getValue(1)
3032 };
Matt Arsenault37fefd62016-06-10 02:18:02 +00003033
Tom Stellard8485fa02016-12-07 02:42:15 +00003034 NegDivScale0 = DAG.getMergeValues(Ops, SL);
3035 }
3036
3037 SDValue Fma0 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0,
3038 ApproxRcp, One, NegDivScale0);
3039
3040 SDValue Fma1 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, Fma0, ApproxRcp,
3041 ApproxRcp, Fma0);
3042
3043 SDValue Mul = getFPBinOp(DAG, ISD::FMUL, SL, MVT::f32, NumeratorScaled,
3044 Fma1, Fma1);
3045
3046 SDValue Fma2 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Mul,
3047 NumeratorScaled, Mul);
3048
3049 SDValue Fma3 = getFPTernOp(DAG, ISD::FMA,SL, MVT::f32, Fma2, Fma1, Mul, Fma2);
3050
3051 SDValue Fma4 = getFPTernOp(DAG, ISD::FMA, SL, MVT::f32, NegDivScale0, Fma3,
3052 NumeratorScaled, Fma3);
3053
3054 if (!Subtarget->hasFP32Denormals()) {
3055 const SDValue DisableDenormValue =
3056 DAG.getConstant(FP_DENORM_FLUSH_IN_FLUSH_OUT, SL, MVT::i32);
3057 SDValue DisableDenorm = DAG.getNode(AMDGPUISD::SETREG, SL, MVT::Other,
3058 Fma4.getValue(1),
3059 DisableDenormValue,
3060 BitField,
3061 Fma4.getValue(2));
3062
3063 SDValue OutputChain = DAG.getNode(ISD::TokenFactor, SL, MVT::Other,
3064 DisableDenorm, DAG.getRoot());
3065 DAG.setRoot(OutputChain);
3066 }
Matt Arsenault37fefd62016-06-10 02:18:02 +00003067
Wei Dinged0f97f2016-06-09 19:17:15 +00003068 SDValue Scale = NumeratorScaled.getValue(1);
Tom Stellard8485fa02016-12-07 02:42:15 +00003069 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f32,
3070 Fma4, Fma1, Fma3, Scale);
Matt Arsenault37fefd62016-06-10 02:18:02 +00003071
Wei Dinged0f97f2016-06-09 19:17:15 +00003072 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f32, Fmas, RHS, LHS);
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +00003073}
3074
3075SDValue SITargetLowering::LowerFDIV64(SDValue Op, SelectionDAG &DAG) const {
Matt Arsenault0bbcd8b2015-02-14 04:30:08 +00003076 if (DAG.getTarget().Options.UnsafeFPMath)
Matt Arsenaulta1fe17c2016-07-19 23:16:53 +00003077 return lowerFastUnsafeFDIV(Op, DAG);
Matt Arsenault0bbcd8b2015-02-14 04:30:08 +00003078
3079 SDLoc SL(Op);
3080 SDValue X = Op.getOperand(0);
3081 SDValue Y = Op.getOperand(1);
3082
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003083 const SDValue One = DAG.getConstantFP(1.0, SL, MVT::f64);
Matt Arsenault0bbcd8b2015-02-14 04:30:08 +00003084
3085 SDVTList ScaleVT = DAG.getVTList(MVT::f64, MVT::i1);
3086
3087 SDValue DivScale0 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, Y, Y, X);
3088
3089 SDValue NegDivScale0 = DAG.getNode(ISD::FNEG, SL, MVT::f64, DivScale0);
3090
3091 SDValue Rcp = DAG.getNode(AMDGPUISD::RCP, SL, MVT::f64, DivScale0);
3092
3093 SDValue Fma0 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Rcp, One);
3094
3095 SDValue Fma1 = DAG.getNode(ISD::FMA, SL, MVT::f64, Rcp, Fma0, Rcp);
3096
3097 SDValue Fma2 = DAG.getNode(ISD::FMA, SL, MVT::f64, NegDivScale0, Fma1, One);
3098
3099 SDValue DivScale1 = DAG.getNode(AMDGPUISD::DIV_SCALE, SL, ScaleVT, X, Y, X);
3100
3101 SDValue Fma3 = DAG.getNode(ISD::FMA, SL, MVT::f64, Fma1, Fma2, Fma1);
3102 SDValue Mul = DAG.getNode(ISD::FMUL, SL, MVT::f64, DivScale1, Fma3);
3103
3104 SDValue Fma4 = DAG.getNode(ISD::FMA, SL, MVT::f64,
3105 NegDivScale0, Mul, DivScale1);
3106
3107 SDValue Scale;
3108
Matt Arsenault43e92fe2016-06-24 06:30:11 +00003109 if (Subtarget->getGeneration() == SISubtarget::SOUTHERN_ISLANDS) {
Matt Arsenault0bbcd8b2015-02-14 04:30:08 +00003110 // Workaround a hardware bug on SI where the condition output from div_scale
3111 // is not usable.
3112
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003113 const SDValue Hi = DAG.getConstant(1, SL, MVT::i32);
Matt Arsenault0bbcd8b2015-02-14 04:30:08 +00003114
3115 // Figure out if the scale to use for div_fmas.
3116 SDValue NumBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, X);
3117 SDValue DenBC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, Y);
3118 SDValue Scale0BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale0);
3119 SDValue Scale1BC = DAG.getNode(ISD::BITCAST, SL, MVT::v2i32, DivScale1);
3120
3121 SDValue NumHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, NumBC, Hi);
3122 SDValue DenHi = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, DenBC, Hi);
3123
3124 SDValue Scale0Hi
3125 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale0BC, Hi);
3126 SDValue Scale1Hi
3127 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SL, MVT::i32, Scale1BC, Hi);
3128
3129 SDValue CmpDen = DAG.getSetCC(SL, MVT::i1, DenHi, Scale0Hi, ISD::SETEQ);
3130 SDValue CmpNum = DAG.getSetCC(SL, MVT::i1, NumHi, Scale1Hi, ISD::SETEQ);
3131 Scale = DAG.getNode(ISD::XOR, SL, MVT::i1, CmpNum, CmpDen);
3132 } else {
3133 Scale = DivScale1.getValue(1);
3134 }
3135
3136 SDValue Fmas = DAG.getNode(AMDGPUISD::DIV_FMAS, SL, MVT::f64,
3137 Fma4, Fma3, Mul, Scale);
3138
3139 return DAG.getNode(AMDGPUISD::DIV_FIXUP, SL, MVT::f64, Fmas, Y, X);
Matt Arsenaulte9fa3b82014-07-15 20:18:31 +00003140}
3141
3142SDValue SITargetLowering::LowerFDIV(SDValue Op, SelectionDAG &DAG) const {
3143 EVT VT = Op.getValueType();
3144
3145 if (VT == MVT::f32)
3146 return LowerFDIV32(Op, DAG);
3147
3148 if (VT == MVT::f64)
3149 return LowerFDIV64(Op, DAG);
3150
3151 llvm_unreachable("Unexpected type for fdiv");
3152}
3153
Tom Stellard81d871d2013-11-13 23:36:50 +00003154SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
3155 SDLoc DL(Op);
3156 StoreSDNode *Store = cast<StoreSDNode>(Op);
3157 EVT VT = Store->getMemoryVT();
3158
Matt Arsenault95245662016-02-11 05:32:46 +00003159 if (VT == MVT::i1) {
3160 return DAG.getTruncStore(Store->getChain(), DL,
3161 DAG.getSExtOrTrunc(Store->getValue(), DL, MVT::i32),
3162 Store->getBasePtr(), MVT::i1, Store->getMemOperand());
Tom Stellardb02094e2014-07-21 15:45:01 +00003163 }
3164
Matt Arsenaultbcdfee72016-05-02 20:13:51 +00003165 assert(VT.isVector() &&
3166 Store->getValue().getValueType().getScalarType() == MVT::i32);
3167
3168 unsigned AS = Store->getAddressSpace();
3169 if (!allowsMemoryAccess(*DAG.getContext(), DAG.getDataLayout(), VT,
3170 AS, Store->getAlignment())) {
3171 return expandUnalignedStore(Store, DAG);
3172 }
Tom Stellard81d871d2013-11-13 23:36:50 +00003173
Tom Stellardf8e6eaf2016-10-26 14:38:47 +00003174 MachineFunction &MF = DAG.getMachineFunction();
3175 SIMachineFunctionInfo *MFI = MF.getInfo<SIMachineFunctionInfo>();
3176 // If there is a possibilty that flat instruction access scratch memory
3177 // then we need to use the same legalization rules we use for private.
3178 if (AS == AMDGPUAS::FLAT_ADDRESS)
3179 AS = MFI->hasFlatScratchInit() ?
3180 AMDGPUAS::PRIVATE_ADDRESS : AMDGPUAS::GLOBAL_ADDRESS;
3181
Matt Arsenaultf2ddbf02016-02-13 04:18:53 +00003182 unsigned NumElements = VT.getVectorNumElements();
Matt Arsenaultbcdfee72016-05-02 20:13:51 +00003183 switch (AS) {
Matt Arsenaultf2ddbf02016-02-13 04:18:53 +00003184 case AMDGPUAS::GLOBAL_ADDRESS:
3185 case AMDGPUAS::FLAT_ADDRESS:
3186 if (NumElements > 4)
3187 return SplitVectorStore(Op, DAG);
3188 return SDValue();
3189 case AMDGPUAS::PRIVATE_ADDRESS: {
3190 switch (Subtarget->getMaxPrivateElementSize()) {
3191 case 4:
Matt Arsenault9c499c32016-04-14 23:31:26 +00003192 return scalarizeVectorStore(Store, DAG);
Matt Arsenaultf2ddbf02016-02-13 04:18:53 +00003193 case 8:
3194 if (NumElements > 2)
3195 return SplitVectorStore(Op, DAG);
3196 return SDValue();
3197 case 16:
3198 if (NumElements > 4)
3199 return SplitVectorStore(Op, DAG);
3200 return SDValue();
3201 default:
3202 llvm_unreachable("unsupported private_element_size");
3203 }
3204 }
Matt Arsenaultbcdfee72016-05-02 20:13:51 +00003205 case AMDGPUAS::LOCAL_ADDRESS: {
3206 if (NumElements > 2)
3207 return SplitVectorStore(Op, DAG);
3208
3209 if (NumElements == 2)
3210 return Op;
3211
Matt Arsenault95245662016-02-11 05:32:46 +00003212 // If properly aligned, if we split we might be able to use ds_write_b64.
3213 return SplitVectorStore(Op, DAG);
Matt Arsenaultbcdfee72016-05-02 20:13:51 +00003214 }
Matt Arsenaultf2ddbf02016-02-13 04:18:53 +00003215 default:
3216 llvm_unreachable("unhandled address space");
Matt Arsenault95245662016-02-11 05:32:46 +00003217 }
Tom Stellard81d871d2013-11-13 23:36:50 +00003218}
3219
Matt Arsenaultad14ce82014-07-19 18:44:39 +00003220SDValue SITargetLowering::LowerTrig(SDValue Op, SelectionDAG &DAG) const {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003221 SDLoc DL(Op);
Matt Arsenaultad14ce82014-07-19 18:44:39 +00003222 EVT VT = Op.getValueType();
3223 SDValue Arg = Op.getOperand(0);
Sanjay Patela2607012015-09-16 16:31:21 +00003224 // TODO: Should this propagate fast-math-flags?
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003225 SDValue FractPart = DAG.getNode(AMDGPUISD::FRACT, DL, VT,
3226 DAG.getNode(ISD::FMUL, DL, VT, Arg,
3227 DAG.getConstantFP(0.5/M_PI, DL,
3228 VT)));
Matt Arsenaultad14ce82014-07-19 18:44:39 +00003229
3230 switch (Op.getOpcode()) {
3231 case ISD::FCOS:
3232 return DAG.getNode(AMDGPUISD::COS_HW, SDLoc(Op), VT, FractPart);
3233 case ISD::FSIN:
3234 return DAG.getNode(AMDGPUISD::SIN_HW, SDLoc(Op), VT, FractPart);
3235 default:
3236 llvm_unreachable("Wrong trig opcode");
3237 }
3238}
3239
Tom Stellard354a43c2016-04-01 18:27:37 +00003240SDValue SITargetLowering::LowerATOMIC_CMP_SWAP(SDValue Op, SelectionDAG &DAG) const {
3241 AtomicSDNode *AtomicNode = cast<AtomicSDNode>(Op);
3242 assert(AtomicNode->isCompareAndSwap());
3243 unsigned AS = AtomicNode->getAddressSpace();
3244
3245 // No custom lowering required for local address space
3246 if (!isFlatGlobalAddrSpace(AS))
3247 return Op;
3248
3249 // Non-local address space requires custom lowering for atomic compare
3250 // and swap; cmp and swap should be in a v2i32 or v2i64 in case of _X2
3251 SDLoc DL(Op);
3252 SDValue ChainIn = Op.getOperand(0);
3253 SDValue Addr = Op.getOperand(1);
3254 SDValue Old = Op.getOperand(2);
3255 SDValue New = Op.getOperand(3);
3256 EVT VT = Op.getValueType();
3257 MVT SimpleVT = VT.getSimpleVT();
3258 MVT VecType = MVT::getVectorVT(SimpleVT, 2);
3259
Ahmed Bougacha128f8732016-04-26 21:15:30 +00003260 SDValue NewOld = DAG.getBuildVector(VecType, DL, {New, Old});
Tom Stellard354a43c2016-04-01 18:27:37 +00003261 SDValue Ops[] = { ChainIn, Addr, NewOld };
Matt Arsenault88701812016-06-09 23:42:48 +00003262
3263 return DAG.getMemIntrinsicNode(AMDGPUISD::ATOMIC_CMP_SWAP, DL, Op->getVTList(),
3264 Ops, VT, AtomicNode->getMemOperand());
Tom Stellard354a43c2016-04-01 18:27:37 +00003265}
3266
Tom Stellard75aadc22012-12-11 21:25:42 +00003267//===----------------------------------------------------------------------===//
3268// Custom DAG optimizations
3269//===----------------------------------------------------------------------===//
3270
Matt Arsenault364a6742014-06-11 17:50:44 +00003271SDValue SITargetLowering::performUCharToFloatCombine(SDNode *N,
Matt Arsenaulte6986632015-01-14 01:35:22 +00003272 DAGCombinerInfo &DCI) const {
Matt Arsenault364a6742014-06-11 17:50:44 +00003273 EVT VT = N->getValueType(0);
3274 EVT ScalarVT = VT.getScalarType();
3275 if (ScalarVT != MVT::f32)
3276 return SDValue();
3277
3278 SelectionDAG &DAG = DCI.DAG;
3279 SDLoc DL(N);
3280
3281 SDValue Src = N->getOperand(0);
3282 EVT SrcVT = Src.getValueType();
3283
3284 // TODO: We could try to match extracting the higher bytes, which would be
3285 // easier if i8 vectors weren't promoted to i32 vectors, particularly after
3286 // types are legalized. v4i8 -> v4f32 is probably the only case to worry
3287 // about in practice.
3288 if (DCI.isAfterLegalizeVectorOps() && SrcVT == MVT::i32) {
3289 if (DAG.MaskedValueIsZero(Src, APInt::getHighBitsSet(32, 24))) {
3290 SDValue Cvt = DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0, DL, VT, Src);
3291 DCI.AddToWorklist(Cvt.getNode());
3292 return Cvt;
3293 }
3294 }
3295
Matt Arsenault364a6742014-06-11 17:50:44 +00003296 return SDValue();
3297}
3298
Eric Christopher6c5b5112015-03-11 18:43:21 +00003299/// \brief Return true if the given offset Size in bytes can be folded into
3300/// the immediate offsets of a memory instruction for the given address space.
3301static bool canFoldOffset(unsigned OffsetSize, unsigned AS,
Matt Arsenault43e92fe2016-06-24 06:30:11 +00003302 const SISubtarget &STI) {
Eric Christopher6c5b5112015-03-11 18:43:21 +00003303 switch (AS) {
3304 case AMDGPUAS::GLOBAL_ADDRESS: {
3305 // MUBUF instructions a 12-bit offset in bytes.
3306 return isUInt<12>(OffsetSize);
3307 }
3308 case AMDGPUAS::CONSTANT_ADDRESS: {
3309 // SMRD instructions have an 8-bit offset in dwords on SI and
3310 // a 20-bit offset in bytes on VI.
Matt Arsenault43e92fe2016-06-24 06:30:11 +00003311 if (STI.getGeneration() >= SISubtarget::VOLCANIC_ISLANDS)
Eric Christopher6c5b5112015-03-11 18:43:21 +00003312 return isUInt<20>(OffsetSize);
3313 else
3314 return (OffsetSize % 4 == 0) && isUInt<8>(OffsetSize / 4);
3315 }
3316 case AMDGPUAS::LOCAL_ADDRESS:
3317 case AMDGPUAS::REGION_ADDRESS: {
3318 // The single offset versions have a 16-bit offset in bytes.
3319 return isUInt<16>(OffsetSize);
3320 }
3321 case AMDGPUAS::PRIVATE_ADDRESS:
3322 // Indirect register addressing does not use any offsets.
3323 default:
3324 return 0;
3325 }
3326}
3327
Matt Arsenaultb2baffa2014-08-15 17:49:05 +00003328// (shl (add x, c1), c2) -> add (shl x, c2), (shl c1, c2)
3329
3330// This is a variant of
3331// (mul (add x, c1), c2) -> add (mul x, c2), (mul c1, c2),
3332//
3333// The normal DAG combiner will do this, but only if the add has one use since
3334// that would increase the number of instructions.
3335//
3336// This prevents us from seeing a constant offset that can be folded into a
3337// memory instruction's addressing mode. If we know the resulting add offset of
3338// a pointer can be folded into an addressing offset, we can replace the pointer
3339// operand with the add of new constant offset. This eliminates one of the uses,
3340// and may allow the remaining use to also be simplified.
3341//
3342SDValue SITargetLowering::performSHLPtrCombine(SDNode *N,
3343 unsigned AddrSpace,
3344 DAGCombinerInfo &DCI) const {
3345 SDValue N0 = N->getOperand(0);
3346 SDValue N1 = N->getOperand(1);
3347
3348 if (N0.getOpcode() != ISD::ADD)
3349 return SDValue();
3350
3351 const ConstantSDNode *CN1 = dyn_cast<ConstantSDNode>(N1);
3352 if (!CN1)
3353 return SDValue();
3354
3355 const ConstantSDNode *CAdd = dyn_cast<ConstantSDNode>(N0.getOperand(1));
3356 if (!CAdd)
3357 return SDValue();
3358
Matt Arsenaultb2baffa2014-08-15 17:49:05 +00003359 // If the resulting offset is too large, we can't fold it into the addressing
3360 // mode offset.
3361 APInt Offset = CAdd->getAPIntValue() << CN1->getAPIntValue();
Matt Arsenault43e92fe2016-06-24 06:30:11 +00003362 if (!canFoldOffset(Offset.getZExtValue(), AddrSpace, *getSubtarget()))
Matt Arsenaultb2baffa2014-08-15 17:49:05 +00003363 return SDValue();
3364
3365 SelectionDAG &DAG = DCI.DAG;
3366 SDLoc SL(N);
3367 EVT VT = N->getValueType(0);
3368
3369 SDValue ShlX = DAG.getNode(ISD::SHL, SL, VT, N0.getOperand(0), N1);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003370 SDValue COffset = DAG.getConstant(Offset, SL, MVT::i32);
Matt Arsenaultb2baffa2014-08-15 17:49:05 +00003371
3372 return DAG.getNode(ISD::ADD, SL, VT, ShlX, COffset);
3373}
3374
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003375static bool bitOpWithConstantIsReducible(unsigned Opc, uint32_t Val) {
3376 return (Opc == ISD::AND && (Val == 0 || Val == 0xffffffff)) ||
3377 (Opc == ISD::OR && (Val == 0xffffffff || Val == 0)) ||
3378 (Opc == ISD::XOR && Val == 0);
3379}
3380
3381// Break up 64-bit bit operation of a constant into two 32-bit and/or/xor. This
3382// will typically happen anyway for a VALU 64-bit and. This exposes other 32-bit
3383// integer combine opportunities since most 64-bit operations are decomposed
3384// this way. TODO: We won't want this for SALU especially if it is an inline
3385// immediate.
3386SDValue SITargetLowering::splitBinaryBitConstantOp(
3387 DAGCombinerInfo &DCI,
3388 const SDLoc &SL,
3389 unsigned Opc, SDValue LHS,
3390 const ConstantSDNode *CRHS) const {
3391 uint64_t Val = CRHS->getZExtValue();
3392 uint32_t ValLo = Lo_32(Val);
3393 uint32_t ValHi = Hi_32(Val);
3394 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
3395
3396 if ((bitOpWithConstantIsReducible(Opc, ValLo) ||
3397 bitOpWithConstantIsReducible(Opc, ValHi)) ||
3398 (CRHS->hasOneUse() && !TII->isInlineConstant(CRHS->getAPIntValue()))) {
3399 // If we need to materialize a 64-bit immediate, it will be split up later
3400 // anyway. Avoid creating the harder to understand 64-bit immediate
3401 // materialization.
3402 return splitBinaryBitConstantOpImpl(DCI, SL, Opc, LHS, ValLo, ValHi);
3403 }
3404
3405 return SDValue();
3406}
3407
Matt Arsenaultd0101a22015-01-06 23:00:46 +00003408SDValue SITargetLowering::performAndCombine(SDNode *N,
3409 DAGCombinerInfo &DCI) const {
3410 if (DCI.isBeforeLegalize())
3411 return SDValue();
3412
3413 SelectionDAG &DAG = DCI.DAG;
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003414 EVT VT = N->getValueType(0);
Matt Arsenaultd0101a22015-01-06 23:00:46 +00003415 SDValue LHS = N->getOperand(0);
3416 SDValue RHS = N->getOperand(1);
3417
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003418
3419 if (VT == MVT::i64) {
3420 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
3421 if (CRHS) {
3422 if (SDValue Split
3423 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::AND, LHS, CRHS))
3424 return Split;
3425 }
3426 }
3427
3428 // (and (fcmp ord x, x), (fcmp une (fabs x), inf)) ->
3429 // fp_class x, ~(s_nan | q_nan | n_infinity | p_infinity)
3430 if (LHS.getOpcode() == ISD::SETCC && RHS.getOpcode() == ISD::SETCC) {
Matt Arsenaultd0101a22015-01-06 23:00:46 +00003431 ISD::CondCode LCC = cast<CondCodeSDNode>(LHS.getOperand(2))->get();
3432 ISD::CondCode RCC = cast<CondCodeSDNode>(RHS.getOperand(2))->get();
3433
3434 SDValue X = LHS.getOperand(0);
3435 SDValue Y = RHS.getOperand(0);
3436 if (Y.getOpcode() != ISD::FABS || Y.getOperand(0) != X)
3437 return SDValue();
3438
3439 if (LCC == ISD::SETO) {
3440 if (X != LHS.getOperand(1))
3441 return SDValue();
3442
3443 if (RCC == ISD::SETUNE) {
3444 const ConstantFPSDNode *C1 = dyn_cast<ConstantFPSDNode>(RHS.getOperand(1));
3445 if (!C1 || !C1->isInfinity() || C1->isNegative())
3446 return SDValue();
3447
3448 const uint32_t Mask = SIInstrFlags::N_NORMAL |
3449 SIInstrFlags::N_SUBNORMAL |
3450 SIInstrFlags::N_ZERO |
3451 SIInstrFlags::P_ZERO |
3452 SIInstrFlags::P_SUBNORMAL |
3453 SIInstrFlags::P_NORMAL;
3454
3455 static_assert(((~(SIInstrFlags::S_NAN |
3456 SIInstrFlags::Q_NAN |
3457 SIInstrFlags::N_INFINITY |
3458 SIInstrFlags::P_INFINITY)) & 0x3ff) == Mask,
3459 "mask not equal");
3460
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003461 SDLoc DL(N);
3462 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
3463 X, DAG.getConstant(Mask, DL, MVT::i32));
Matt Arsenaultd0101a22015-01-06 23:00:46 +00003464 }
3465 }
3466 }
3467
3468 return SDValue();
3469}
3470
Matt Arsenaultf2290332015-01-06 23:00:39 +00003471SDValue SITargetLowering::performOrCombine(SDNode *N,
3472 DAGCombinerInfo &DCI) const {
3473 SelectionDAG &DAG = DCI.DAG;
3474 SDValue LHS = N->getOperand(0);
3475 SDValue RHS = N->getOperand(1);
3476
Matt Arsenault3b082382016-04-12 18:24:38 +00003477 EVT VT = N->getValueType(0);
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003478 if (VT == MVT::i1) {
3479 // or (fp_class x, c1), (fp_class x, c2) -> fp_class x, (c1 | c2)
3480 if (LHS.getOpcode() == AMDGPUISD::FP_CLASS &&
3481 RHS.getOpcode() == AMDGPUISD::FP_CLASS) {
3482 SDValue Src = LHS.getOperand(0);
3483 if (Src != RHS.getOperand(0))
3484 return SDValue();
Matt Arsenault3b082382016-04-12 18:24:38 +00003485
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003486 const ConstantSDNode *CLHS = dyn_cast<ConstantSDNode>(LHS.getOperand(1));
3487 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS.getOperand(1));
3488 if (!CLHS || !CRHS)
3489 return SDValue();
Matt Arsenault3b082382016-04-12 18:24:38 +00003490
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003491 // Only 10 bits are used.
3492 static const uint32_t MaxMask = 0x3ff;
Matt Arsenault3b082382016-04-12 18:24:38 +00003493
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003494 uint32_t NewMask = (CLHS->getZExtValue() | CRHS->getZExtValue()) & MaxMask;
3495 SDLoc DL(N);
3496 return DAG.getNode(AMDGPUISD::FP_CLASS, DL, MVT::i1,
3497 Src, DAG.getConstant(NewMask, DL, MVT::i32));
3498 }
Matt Arsenault3b082382016-04-12 18:24:38 +00003499
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003500 return SDValue();
3501 }
3502
3503 if (VT != MVT::i64)
3504 return SDValue();
3505
3506 // TODO: This could be a generic combine with a predicate for extracting the
3507 // high half of an integer being free.
3508
3509 // (or i64:x, (zero_extend i32:y)) ->
3510 // i64 (bitcast (v2i32 build_vector (or i32:y, lo_32(x)), hi_32(x)))
3511 if (LHS.getOpcode() == ISD::ZERO_EXTEND &&
3512 RHS.getOpcode() != ISD::ZERO_EXTEND)
3513 std::swap(LHS, RHS);
3514
3515 if (RHS.getOpcode() == ISD::ZERO_EXTEND) {
3516 SDValue ExtSrc = RHS.getOperand(0);
3517 EVT SrcVT = ExtSrc.getValueType();
3518 if (SrcVT == MVT::i32) {
3519 SDLoc SL(N);
3520 SDValue LowLHS, HiBits;
3521 std::tie(LowLHS, HiBits) = split64BitValue(LHS, DAG);
3522 SDValue LowOr = DAG.getNode(ISD::OR, SL, MVT::i32, LowLHS, ExtSrc);
3523
3524 DCI.AddToWorklist(LowOr.getNode());
3525 DCI.AddToWorklist(HiBits.getNode());
3526
3527 SDValue Vec = DAG.getNode(ISD::BUILD_VECTOR, SL, MVT::v2i32,
3528 LowOr, HiBits);
3529 return DAG.getNode(ISD::BITCAST, SL, MVT::i64, Vec);
Matt Arsenault3b082382016-04-12 18:24:38 +00003530 }
3531 }
3532
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003533 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(N->getOperand(1));
3534 if (CRHS) {
3535 if (SDValue Split
3536 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::OR, LHS, CRHS))
3537 return Split;
3538 }
Matt Arsenaultf2290332015-01-06 23:00:39 +00003539
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003540 return SDValue();
3541}
Matt Arsenaultf2290332015-01-06 23:00:39 +00003542
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003543SDValue SITargetLowering::performXorCombine(SDNode *N,
3544 DAGCombinerInfo &DCI) const {
3545 EVT VT = N->getValueType(0);
3546 if (VT != MVT::i64)
3547 return SDValue();
Matt Arsenaultf2290332015-01-06 23:00:39 +00003548
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003549 SDValue LHS = N->getOperand(0);
3550 SDValue RHS = N->getOperand(1);
3551
3552 const ConstantSDNode *CRHS = dyn_cast<ConstantSDNode>(RHS);
3553 if (CRHS) {
3554 if (SDValue Split
3555 = splitBinaryBitConstantOp(DCI, SDLoc(N), ISD::XOR, LHS, CRHS))
3556 return Split;
Matt Arsenaultf2290332015-01-06 23:00:39 +00003557 }
3558
3559 return SDValue();
3560}
3561
3562SDValue SITargetLowering::performClassCombine(SDNode *N,
3563 DAGCombinerInfo &DCI) const {
3564 SelectionDAG &DAG = DCI.DAG;
3565 SDValue Mask = N->getOperand(1);
3566
3567 // fp_class x, 0 -> false
3568 if (const ConstantSDNode *CMask = dyn_cast<ConstantSDNode>(Mask)) {
3569 if (CMask->isNullValue())
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003570 return DAG.getConstant(0, SDLoc(N), MVT::i1);
Matt Arsenaultf2290332015-01-06 23:00:39 +00003571 }
3572
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00003573 if (N->getOperand(0).isUndef())
3574 return DAG.getUNDEF(MVT::i1);
3575
Matt Arsenaultf2290332015-01-06 23:00:39 +00003576 return SDValue();
3577}
3578
Matt Arsenault9cd90712016-04-14 01:42:16 +00003579// Constant fold canonicalize.
3580SDValue SITargetLowering::performFCanonicalizeCombine(
3581 SDNode *N,
3582 DAGCombinerInfo &DCI) const {
3583 ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(N->getOperand(0));
3584 if (!CFP)
3585 return SDValue();
3586
3587 SelectionDAG &DAG = DCI.DAG;
3588 const APFloat &C = CFP->getValueAPF();
3589
3590 // Flush denormals to 0 if not enabled.
3591 if (C.isDenormal()) {
3592 EVT VT = N->getValueType(0);
3593 if (VT == MVT::f32 && !Subtarget->hasFP32Denormals())
3594 return DAG.getConstantFP(0.0, SDLoc(N), VT);
3595
3596 if (VT == MVT::f64 && !Subtarget->hasFP64Denormals())
3597 return DAG.getConstantFP(0.0, SDLoc(N), VT);
3598 }
3599
3600 if (C.isNaN()) {
3601 EVT VT = N->getValueType(0);
3602 APFloat CanonicalQNaN = APFloat::getQNaN(C.getSemantics());
3603 if (C.isSignaling()) {
3604 // Quiet a signaling NaN.
3605 return DAG.getConstantFP(CanonicalQNaN, SDLoc(N), VT);
3606 }
3607
3608 // Make sure it is the canonical NaN bitpattern.
3609 //
3610 // TODO: Can we use -1 as the canonical NaN value since it's an inline
3611 // immediate?
3612 if (C.bitcastToAPInt() != CanonicalQNaN.bitcastToAPInt())
3613 return DAG.getConstantFP(CanonicalQNaN, SDLoc(N), VT);
3614 }
3615
3616 return SDValue(CFP, 0);
3617}
3618
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003619static unsigned minMaxOpcToMin3Max3Opc(unsigned Opc) {
3620 switch (Opc) {
3621 case ISD::FMAXNUM:
3622 return AMDGPUISD::FMAX3;
Matt Arsenault5881f4e2015-06-09 00:52:37 +00003623 case ISD::SMAX:
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003624 return AMDGPUISD::SMAX3;
Matt Arsenault5881f4e2015-06-09 00:52:37 +00003625 case ISD::UMAX:
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003626 return AMDGPUISD::UMAX3;
3627 case ISD::FMINNUM:
3628 return AMDGPUISD::FMIN3;
Matt Arsenault5881f4e2015-06-09 00:52:37 +00003629 case ISD::SMIN:
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003630 return AMDGPUISD::SMIN3;
Matt Arsenault5881f4e2015-06-09 00:52:37 +00003631 case ISD::UMIN:
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003632 return AMDGPUISD::UMIN3;
3633 default:
3634 llvm_unreachable("Not a min/max opcode");
3635 }
3636}
3637
Benjamin Kramerbdc49562016-06-12 15:39:02 +00003638static SDValue performIntMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
3639 SDValue Op0, SDValue Op1, bool Signed) {
Matt Arsenaultf639c322016-01-28 20:53:42 +00003640 ConstantSDNode *K1 = dyn_cast<ConstantSDNode>(Op1);
3641 if (!K1)
3642 return SDValue();
3643
3644 ConstantSDNode *K0 = dyn_cast<ConstantSDNode>(Op0.getOperand(1));
3645 if (!K0)
3646 return SDValue();
3647
Matt Arsenaultf639c322016-01-28 20:53:42 +00003648 if (Signed) {
3649 if (K0->getAPIntValue().sge(K1->getAPIntValue()))
3650 return SDValue();
3651 } else {
3652 if (K0->getAPIntValue().uge(K1->getAPIntValue()))
3653 return SDValue();
3654 }
3655
3656 EVT VT = K0->getValueType(0);
Tom Stellard115a6152016-11-10 16:02:37 +00003657
3658 MVT NVT = MVT::i32;
3659 unsigned ExtOp = Signed ? ISD::SIGN_EXTEND : ISD::ZERO_EXTEND;
3660
3661 SDValue Tmp1, Tmp2, Tmp3;
3662 Tmp1 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(0));
3663 Tmp2 = DAG.getNode(ExtOp, SL, NVT, Op0->getOperand(1));
3664 Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1);
3665
3666 if (VT == MVT::i16) {
3667 Tmp1 = DAG.getNode(Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3, SL, NVT,
3668 Tmp1, Tmp2, Tmp3);
3669
3670 return DAG.getNode(ISD::TRUNCATE, SL, VT, Tmp1);
3671 } else
3672 return DAG.getNode(Signed ? AMDGPUISD::SMED3 : AMDGPUISD::UMED3, SL, VT,
3673 Op0.getOperand(0), SDValue(K0, 0), SDValue(K1, 0));
Matt Arsenaultf639c322016-01-28 20:53:42 +00003674}
3675
3676static bool isKnownNeverSNan(SelectionDAG &DAG, SDValue Op) {
3677 if (!DAG.getTargetLoweringInfo().hasFloatingPointExceptions())
3678 return true;
3679
3680 return DAG.isKnownNeverNaN(Op);
3681}
3682
Benjamin Kramerbdc49562016-06-12 15:39:02 +00003683static SDValue performFPMed3ImmCombine(SelectionDAG &DAG, const SDLoc &SL,
3684 SDValue Op0, SDValue Op1) {
Matt Arsenaultf639c322016-01-28 20:53:42 +00003685 ConstantFPSDNode *K1 = dyn_cast<ConstantFPSDNode>(Op1);
3686 if (!K1)
3687 return SDValue();
3688
3689 ConstantFPSDNode *K0 = dyn_cast<ConstantFPSDNode>(Op0.getOperand(1));
3690 if (!K0)
3691 return SDValue();
3692
3693 // Ordered >= (although NaN inputs should have folded away by now).
3694 APFloat::cmpResult Cmp = K0->getValueAPF().compare(K1->getValueAPF());
3695 if (Cmp == APFloat::cmpGreaterThan)
3696 return SDValue();
3697
3698 // This isn't safe with signaling NaNs because in IEEE mode, min/max on a
3699 // signaling NaN gives a quiet NaN. The quiet NaN input to the min would then
3700 // give the other result, which is different from med3 with a NaN input.
3701 SDValue Var = Op0.getOperand(0);
3702 if (!isKnownNeverSNan(DAG, Var))
3703 return SDValue();
3704
3705 return DAG.getNode(AMDGPUISD::FMED3, SL, K0->getValueType(0),
3706 Var, SDValue(K0, 0), SDValue(K1, 0));
3707}
3708
3709SDValue SITargetLowering::performMinMaxCombine(SDNode *N,
3710 DAGCombinerInfo &DCI) const {
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003711 SelectionDAG &DAG = DCI.DAG;
3712
3713 unsigned Opc = N->getOpcode();
3714 SDValue Op0 = N->getOperand(0);
3715 SDValue Op1 = N->getOperand(1);
3716
3717 // Only do this if the inner op has one use since this will just increases
3718 // register pressure for no benefit.
3719
Matt Arsenault5b39b342016-01-28 20:53:48 +00003720 if (Opc != AMDGPUISD::FMIN_LEGACY && Opc != AMDGPUISD::FMAX_LEGACY) {
3721 // max(max(a, b), c) -> max3(a, b, c)
3722 // min(min(a, b), c) -> min3(a, b, c)
3723 if (Op0.getOpcode() == Opc && Op0.hasOneUse()) {
3724 SDLoc DL(N);
3725 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
3726 DL,
3727 N->getValueType(0),
3728 Op0.getOperand(0),
3729 Op0.getOperand(1),
3730 Op1);
3731 }
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003732
Matt Arsenault5b39b342016-01-28 20:53:48 +00003733 // Try commuted.
3734 // max(a, max(b, c)) -> max3(a, b, c)
3735 // min(a, min(b, c)) -> min3(a, b, c)
3736 if (Op1.getOpcode() == Opc && Op1.hasOneUse()) {
3737 SDLoc DL(N);
3738 return DAG.getNode(minMaxOpcToMin3Max3Opc(Opc),
3739 DL,
3740 N->getValueType(0),
3741 Op0,
3742 Op1.getOperand(0),
3743 Op1.getOperand(1));
3744 }
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003745 }
3746
Matt Arsenaultf639c322016-01-28 20:53:42 +00003747 // min(max(x, K0), K1), K0 < K1 -> med3(x, K0, K1)
3748 if (Opc == ISD::SMIN && Op0.getOpcode() == ISD::SMAX && Op0.hasOneUse()) {
3749 if (SDValue Med3 = performIntMed3ImmCombine(DAG, SDLoc(N), Op0, Op1, true))
3750 return Med3;
3751 }
3752
3753 if (Opc == ISD::UMIN && Op0.getOpcode() == ISD::UMAX && Op0.hasOneUse()) {
3754 if (SDValue Med3 = performIntMed3ImmCombine(DAG, SDLoc(N), Op0, Op1, false))
3755 return Med3;
3756 }
3757
3758 // fminnum(fmaxnum(x, K0), K1), K0 < K1 && !is_snan(x) -> fmed3(x, K0, K1)
Matt Arsenault5b39b342016-01-28 20:53:48 +00003759 if (((Opc == ISD::FMINNUM && Op0.getOpcode() == ISD::FMAXNUM) ||
3760 (Opc == AMDGPUISD::FMIN_LEGACY &&
3761 Op0.getOpcode() == AMDGPUISD::FMAX_LEGACY)) &&
Matt Arsenaultf639c322016-01-28 20:53:42 +00003762 N->getValueType(0) == MVT::f32 && Op0.hasOneUse()) {
3763 if (SDValue Res = performFPMed3ImmCombine(DAG, SDLoc(N), Op0, Op1))
3764 return Res;
3765 }
3766
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003767 return SDValue();
3768}
3769
Matt Arsenault6f6233d2015-01-06 23:00:41 +00003770SDValue SITargetLowering::performSetCCCombine(SDNode *N,
3771 DAGCombinerInfo &DCI) const {
3772 SelectionDAG &DAG = DCI.DAG;
3773 SDLoc SL(N);
3774
3775 SDValue LHS = N->getOperand(0);
3776 SDValue RHS = N->getOperand(1);
3777 EVT VT = LHS.getValueType();
3778
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +00003779 if (VT != MVT::f32 && VT != MVT::f64 && (Subtarget->has16BitInsts() &&
3780 VT != MVT::f16))
Matt Arsenault6f6233d2015-01-06 23:00:41 +00003781 return SDValue();
3782
3783 // Match isinf pattern
3784 // (fcmp oeq (fabs x), inf) -> (fp_class x, (p_infinity | n_infinity))
3785 ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
3786 if (CC == ISD::SETOEQ && LHS.getOpcode() == ISD::FABS) {
3787 const ConstantFPSDNode *CRHS = dyn_cast<ConstantFPSDNode>(RHS);
3788 if (!CRHS)
3789 return SDValue();
3790
3791 const APFloat &APF = CRHS->getValueAPF();
3792 if (APF.isInfinity() && !APF.isNegative()) {
3793 unsigned Mask = SIInstrFlags::P_INFINITY | SIInstrFlags::N_INFINITY;
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003794 return DAG.getNode(AMDGPUISD::FP_CLASS, SL, MVT::i1, LHS.getOperand(0),
3795 DAG.getConstant(Mask, SL, MVT::i32));
Matt Arsenault6f6233d2015-01-06 23:00:41 +00003796 }
3797 }
3798
3799 return SDValue();
3800}
3801
Tom Stellard75aadc22012-12-11 21:25:42 +00003802SDValue SITargetLowering::PerformDAGCombine(SDNode *N,
3803 DAGCombinerInfo &DCI) const {
3804 SelectionDAG &DAG = DCI.DAG;
Andrew Trickef9de2a2013-05-25 02:42:55 +00003805 SDLoc DL(N);
Tom Stellard75aadc22012-12-11 21:25:42 +00003806
3807 switch (N->getOpcode()) {
Matt Arsenault22b4c252014-12-21 16:48:42 +00003808 default:
3809 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
Matt Arsenault6f6233d2015-01-06 23:00:41 +00003810 case ISD::SETCC:
3811 return performSetCCCombine(N, DCI);
Matt Arsenault5b39b342016-01-28 20:53:48 +00003812 case ISD::FMAXNUM:
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003813 case ISD::FMINNUM:
Matt Arsenault5881f4e2015-06-09 00:52:37 +00003814 case ISD::SMAX:
3815 case ISD::SMIN:
3816 case ISD::UMAX:
Matt Arsenault5b39b342016-01-28 20:53:48 +00003817 case ISD::UMIN:
3818 case AMDGPUISD::FMIN_LEGACY:
3819 case AMDGPUISD::FMAX_LEGACY: {
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003820 if (DCI.getDAGCombineLevel() >= AfterLegalizeDAG &&
Tom Stellard7c840bc2015-03-16 15:53:55 +00003821 N->getValueType(0) != MVT::f64 &&
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003822 getTargetMachine().getOptLevel() > CodeGenOpt::None)
Matt Arsenaultf639c322016-01-28 20:53:42 +00003823 return performMinMaxCombine(N, DCI);
Matt Arsenaultcc3c2b32014-11-14 20:08:52 +00003824 break;
3825 }
Matt Arsenault364a6742014-06-11 17:50:44 +00003826
3827 case AMDGPUISD::CVT_F32_UBYTE0:
3828 case AMDGPUISD::CVT_F32_UBYTE1:
3829 case AMDGPUISD::CVT_F32_UBYTE2:
3830 case AMDGPUISD::CVT_F32_UBYTE3: {
3831 unsigned Offset = N->getOpcode() - AMDGPUISD::CVT_F32_UBYTE0;
Konstantin Zhuravlyovfda33ea2016-10-21 22:10:03 +00003832
Matt Arsenault364a6742014-06-11 17:50:44 +00003833 SDValue Src = N->getOperand(0);
Konstantin Zhuravlyovfda33ea2016-10-21 22:10:03 +00003834 SDValue Srl = N->getOperand(0);
3835 if (Srl.getOpcode() == ISD::ZERO_EXTEND)
3836 Srl = Srl.getOperand(0);
Matt Arsenaulta949dc62016-05-09 16:29:50 +00003837
Matt Arsenault327bb5a2016-07-01 22:47:50 +00003838 // TODO: Handle (or x, (srl y, 8)) pattern when known bits are zero.
Konstantin Zhuravlyovfda33ea2016-10-21 22:10:03 +00003839 if (Srl.getOpcode() == ISD::SRL) {
Matt Arsenaulta949dc62016-05-09 16:29:50 +00003840 // cvt_f32_ubyte0 (srl x, 16) -> cvt_f32_ubyte2 x
3841 // cvt_f32_ubyte1 (srl x, 16) -> cvt_f32_ubyte3 x
3842 // cvt_f32_ubyte0 (srl x, 8) -> cvt_f32_ubyte1 x
3843
Konstantin Zhuravlyovfda33ea2016-10-21 22:10:03 +00003844 if (const ConstantSDNode *C =
3845 dyn_cast<ConstantSDNode>(Srl.getOperand(1))) {
3846 Srl = DAG.getZExtOrTrunc(Srl.getOperand(0), SDLoc(Srl.getOperand(0)),
3847 EVT(MVT::i32));
3848
Matt Arsenaulta949dc62016-05-09 16:29:50 +00003849 unsigned SrcOffset = C->getZExtValue() + 8 * Offset;
3850 if (SrcOffset < 32 && SrcOffset % 8 == 0) {
3851 return DAG.getNode(AMDGPUISD::CVT_F32_UBYTE0 + SrcOffset / 8, DL,
Konstantin Zhuravlyovfda33ea2016-10-21 22:10:03 +00003852 MVT::f32, Srl);
Matt Arsenaulta949dc62016-05-09 16:29:50 +00003853 }
3854 }
3855 }
3856
Matt Arsenault364a6742014-06-11 17:50:44 +00003857 APInt Demanded = APInt::getBitsSet(32, 8 * Offset, 8 * Offset + 8);
3858
3859 APInt KnownZero, KnownOne;
3860 TargetLowering::TargetLoweringOpt TLO(DAG, !DCI.isBeforeLegalize(),
3861 !DCI.isBeforeLegalizeOps());
3862 const TargetLowering &TLI = DAG.getTargetLoweringInfo();
3863 if (TLO.ShrinkDemandedConstant(Src, Demanded) ||
3864 TLI.SimplifyDemandedBits(Src, Demanded, KnownZero, KnownOne, TLO)) {
3865 DCI.CommitTargetLoweringOpt(TLO);
3866 }
3867
3868 break;
3869 }
Konstantin Zhuravlyovfda33ea2016-10-21 22:10:03 +00003870 case ISD::SINT_TO_FP:
Matt Arsenault364a6742014-06-11 17:50:44 +00003871 case ISD::UINT_TO_FP: {
3872 return performUCharToFloatCombine(N, DCI);
Matt Arsenaultde5fbe92016-01-11 17:02:00 +00003873 }
Matt Arsenault02cb0ff2014-09-29 14:59:34 +00003874 case ISD::FADD: {
3875 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3876 break;
3877
3878 EVT VT = N->getValueType(0);
3879 if (VT != MVT::f32)
3880 break;
3881
Matt Arsenault8d630032015-02-20 22:10:41 +00003882 // Only do this if we are not trying to support denormals. v_mad_f32 does
3883 // not support denormals ever.
3884 if (Subtarget->hasFP32Denormals())
3885 break;
3886
Matt Arsenault02cb0ff2014-09-29 14:59:34 +00003887 SDValue LHS = N->getOperand(0);
3888 SDValue RHS = N->getOperand(1);
3889
3890 // These should really be instruction patterns, but writing patterns with
3891 // source modiifiers is a pain.
3892
3893 // fadd (fadd (a, a), b) -> mad 2.0, a, b
3894 if (LHS.getOpcode() == ISD::FADD) {
3895 SDValue A = LHS.getOperand(0);
3896 if (A == LHS.getOperand(1)) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003897 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
Matt Arsenault8d630032015-02-20 22:10:41 +00003898 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, RHS);
Matt Arsenault02cb0ff2014-09-29 14:59:34 +00003899 }
3900 }
3901
3902 // fadd (b, fadd (a, a)) -> mad 2.0, a, b
3903 if (RHS.getOpcode() == ISD::FADD) {
3904 SDValue A = RHS.getOperand(0);
3905 if (A == RHS.getOperand(1)) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003906 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
Matt Arsenault8d630032015-02-20 22:10:41 +00003907 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, LHS);
Matt Arsenault02cb0ff2014-09-29 14:59:34 +00003908 }
3909 }
3910
Matt Arsenault8d630032015-02-20 22:10:41 +00003911 return SDValue();
Matt Arsenault02cb0ff2014-09-29 14:59:34 +00003912 }
Matt Arsenault8675db12014-08-29 16:01:14 +00003913 case ISD::FSUB: {
3914 if (DCI.getDAGCombineLevel() < AfterLegalizeDAG)
3915 break;
3916
3917 EVT VT = N->getValueType(0);
3918
3919 // Try to get the fneg to fold into the source modifier. This undoes generic
3920 // DAG combines and folds them into the mad.
Matt Arsenault8d630032015-02-20 22:10:41 +00003921 //
3922 // Only do this if we are not trying to support denormals. v_mad_f32 does
3923 // not support denormals ever.
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +00003924 if (VT == MVT::f32 && !Subtarget->hasFP32Denormals()) {
Matt Arsenault8675db12014-08-29 16:01:14 +00003925 SDValue LHS = N->getOperand(0);
3926 SDValue RHS = N->getOperand(1);
Matt Arsenault3d4233f2014-09-29 14:59:38 +00003927 if (LHS.getOpcode() == ISD::FADD) {
3928 // (fsub (fadd a, a), c) -> mad 2.0, a, (fneg c)
3929
3930 SDValue A = LHS.getOperand(0);
3931 if (A == LHS.getOperand(1)) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003932 const SDValue Two = DAG.getConstantFP(2.0, DL, MVT::f32);
Matt Arsenault3d4233f2014-09-29 14:59:38 +00003933 SDValue NegRHS = DAG.getNode(ISD::FNEG, DL, VT, RHS);
3934
Matt Arsenault8d630032015-02-20 22:10:41 +00003935 return DAG.getNode(ISD::FMAD, DL, VT, Two, A, NegRHS);
Matt Arsenault3d4233f2014-09-29 14:59:38 +00003936 }
3937 }
3938
3939 if (RHS.getOpcode() == ISD::FADD) {
3940 // (fsub c, (fadd a, a)) -> mad -2.0, a, c
3941
3942 SDValue A = RHS.getOperand(0);
3943 if (A == RHS.getOperand(1)) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00003944 const SDValue NegTwo = DAG.getConstantFP(-2.0, DL, MVT::f32);
Matt Arsenault8d630032015-02-20 22:10:41 +00003945 return DAG.getNode(ISD::FMAD, DL, VT, NegTwo, A, LHS);
Matt Arsenault3d4233f2014-09-29 14:59:38 +00003946 }
3947 }
Matt Arsenault8d630032015-02-20 22:10:41 +00003948
3949 return SDValue();
Matt Arsenault8675db12014-08-29 16:01:14 +00003950 }
3951
3952 break;
3953 }
Matt Arsenaultb2baffa2014-08-15 17:49:05 +00003954 case ISD::LOAD:
3955 case ISD::STORE:
3956 case ISD::ATOMIC_LOAD:
3957 case ISD::ATOMIC_STORE:
3958 case ISD::ATOMIC_CMP_SWAP:
3959 case ISD::ATOMIC_CMP_SWAP_WITH_SUCCESS:
3960 case ISD::ATOMIC_SWAP:
3961 case ISD::ATOMIC_LOAD_ADD:
3962 case ISD::ATOMIC_LOAD_SUB:
3963 case ISD::ATOMIC_LOAD_AND:
3964 case ISD::ATOMIC_LOAD_OR:
3965 case ISD::ATOMIC_LOAD_XOR:
3966 case ISD::ATOMIC_LOAD_NAND:
3967 case ISD::ATOMIC_LOAD_MIN:
3968 case ISD::ATOMIC_LOAD_MAX:
3969 case ISD::ATOMIC_LOAD_UMIN:
Matt Arsenaulta9dbdca2016-04-12 14:05:04 +00003970 case ISD::ATOMIC_LOAD_UMAX:
3971 case AMDGPUISD::ATOMIC_INC:
3972 case AMDGPUISD::ATOMIC_DEC: { // TODO: Target mem intrinsics.
Matt Arsenaultb2baffa2014-08-15 17:49:05 +00003973 if (DCI.isBeforeLegalize())
3974 break;
Matt Arsenault5565f65e2014-05-22 18:09:07 +00003975
Matt Arsenaultb2baffa2014-08-15 17:49:05 +00003976 MemSDNode *MemNode = cast<MemSDNode>(N);
3977 SDValue Ptr = MemNode->getBasePtr();
3978
3979 // TODO: We could also do this for multiplies.
3980 unsigned AS = MemNode->getAddressSpace();
3981 if (Ptr.getOpcode() == ISD::SHL && AS != AMDGPUAS::PRIVATE_ADDRESS) {
3982 SDValue NewPtr = performSHLPtrCombine(Ptr.getNode(), AS, DCI);
3983 if (NewPtr) {
Benjamin Kramer6cd780f2015-02-17 15:29:18 +00003984 SmallVector<SDValue, 8> NewOps(MemNode->op_begin(), MemNode->op_end());
Matt Arsenaultb2baffa2014-08-15 17:49:05 +00003985
3986 NewOps[N->getOpcode() == ISD::STORE ? 2 : 1] = NewPtr;
3987 return SDValue(DAG.UpdateNodeOperands(MemNode, NewOps), 0);
3988 }
3989 }
3990 break;
3991 }
Matt Arsenaultd0101a22015-01-06 23:00:46 +00003992 case ISD::AND:
3993 return performAndCombine(N, DCI);
Matt Arsenaultf2290332015-01-06 23:00:39 +00003994 case ISD::OR:
3995 return performOrCombine(N, DCI);
Matt Arsenaultfa5f7672016-09-14 15:19:03 +00003996 case ISD::XOR:
3997 return performXorCombine(N, DCI);
Matt Arsenaultf2290332015-01-06 23:00:39 +00003998 case AMDGPUISD::FP_CLASS:
3999 return performClassCombine(N, DCI);
Matt Arsenault9cd90712016-04-14 01:42:16 +00004000 case ISD::FCANONICALIZE:
4001 return performFCanonicalizeCombine(N, DCI);
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00004002 case AMDGPUISD::FRACT:
4003 case AMDGPUISD::RCP:
4004 case AMDGPUISD::RSQ:
Matt Arsenault32fc5272016-07-26 16:45:45 +00004005 case AMDGPUISD::RCP_LEGACY:
Matt Arsenaultb6d8c372016-06-20 18:33:56 +00004006 case AMDGPUISD::RSQ_LEGACY:
4007 case AMDGPUISD::RSQ_CLAMP:
4008 case AMDGPUISD::LDEXP: {
4009 SDValue Src = N->getOperand(0);
4010 if (Src.isUndef())
4011 return Src;
4012 break;
4013 }
Matt Arsenaultb2baffa2014-08-15 17:49:05 +00004014 }
Matt Arsenault5565f65e2014-05-22 18:09:07 +00004015 return AMDGPUTargetLowering::PerformDAGCombine(N, DCI);
Tom Stellard75aadc22012-12-11 21:25:42 +00004016}
Christian Konigd910b7d2013-02-26 17:52:16 +00004017
Christian Konig8e06e2a2013-04-10 08:39:08 +00004018/// \brief Helper function for adjustWritemask
Benjamin Kramer635e3682013-05-23 15:43:05 +00004019static unsigned SubIdx2Lane(unsigned Idx) {
Christian Konig8e06e2a2013-04-10 08:39:08 +00004020 switch (Idx) {
4021 default: return 0;
4022 case AMDGPU::sub0: return 0;
4023 case AMDGPU::sub1: return 1;
4024 case AMDGPU::sub2: return 2;
4025 case AMDGPU::sub3: return 3;
4026 }
4027}
4028
4029/// \brief Adjust the writemask of MIMG instructions
4030void SITargetLowering::adjustWritemask(MachineSDNode *&Node,
4031 SelectionDAG &DAG) const {
4032 SDNode *Users[4] = { };
Tom Stellard54774e52013-10-23 02:53:47 +00004033 unsigned Lane = 0;
Nikolay Haustov2f684f12016-02-26 09:51:05 +00004034 unsigned DmaskIdx = (Node->getNumOperands() - Node->getNumValues() == 9) ? 2 : 3;
4035 unsigned OldDmask = Node->getConstantOperandVal(DmaskIdx);
Tom Stellard54774e52013-10-23 02:53:47 +00004036 unsigned NewDmask = 0;
Christian Konig8e06e2a2013-04-10 08:39:08 +00004037
4038 // Try to figure out the used register components
4039 for (SDNode::use_iterator I = Node->use_begin(), E = Node->use_end();
4040 I != E; ++I) {
4041
4042 // Abort if we can't understand the usage
4043 if (!I->isMachineOpcode() ||
4044 I->getMachineOpcode() != TargetOpcode::EXTRACT_SUBREG)
4045 return;
4046
Tom Stellard54774e52013-10-23 02:53:47 +00004047 // Lane means which subreg of %VGPRa_VGPRb_VGPRc_VGPRd is used.
4048 // Note that subregs are packed, i.e. Lane==0 is the first bit set
4049 // in OldDmask, so it can be any of X,Y,Z,W; Lane==1 is the second bit
4050 // set, etc.
Christian Konig8b1ed282013-04-10 08:39:16 +00004051 Lane = SubIdx2Lane(I->getConstantOperandVal(1));
Christian Konig8e06e2a2013-04-10 08:39:08 +00004052
Tom Stellard54774e52013-10-23 02:53:47 +00004053 // Set which texture component corresponds to the lane.
4054 unsigned Comp;
4055 for (unsigned i = 0, Dmask = OldDmask; i <= Lane; i++) {
4056 assert(Dmask);
Tom Stellard03a5c082013-10-23 03:50:25 +00004057 Comp = countTrailingZeros(Dmask);
Tom Stellard54774e52013-10-23 02:53:47 +00004058 Dmask &= ~(1 << Comp);
4059 }
4060
Christian Konig8e06e2a2013-04-10 08:39:08 +00004061 // Abort if we have more than one user per component
4062 if (Users[Lane])
4063 return;
4064
4065 Users[Lane] = *I;
Tom Stellard54774e52013-10-23 02:53:47 +00004066 NewDmask |= 1 << Comp;
Christian Konig8e06e2a2013-04-10 08:39:08 +00004067 }
4068
Tom Stellard54774e52013-10-23 02:53:47 +00004069 // Abort if there's no change
4070 if (NewDmask == OldDmask)
Christian Konig8e06e2a2013-04-10 08:39:08 +00004071 return;
4072
4073 // Adjust the writemask in the node
4074 std::vector<SDValue> Ops;
Nikolay Haustov2f684f12016-02-26 09:51:05 +00004075 Ops.insert(Ops.end(), Node->op_begin(), Node->op_begin() + DmaskIdx);
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00004076 Ops.push_back(DAG.getTargetConstant(NewDmask, SDLoc(Node), MVT::i32));
Nikolay Haustov2f684f12016-02-26 09:51:05 +00004077 Ops.insert(Ops.end(), Node->op_begin() + DmaskIdx + 1, Node->op_end());
Craig Topper8c0b4d02014-04-28 05:57:50 +00004078 Node = (MachineSDNode*)DAG.UpdateNodeOperands(Node, Ops);
Christian Konig8e06e2a2013-04-10 08:39:08 +00004079
Christian Konig8b1ed282013-04-10 08:39:16 +00004080 // If we only got one lane, replace it with a copy
Tom Stellard54774e52013-10-23 02:53:47 +00004081 // (if NewDmask has only one bit set...)
4082 if (NewDmask && (NewDmask & (NewDmask-1)) == 0) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00004083 SDValue RC = DAG.getTargetConstant(AMDGPU::VGPR_32RegClassID, SDLoc(),
4084 MVT::i32);
Christian Konig8b1ed282013-04-10 08:39:16 +00004085 SDNode *Copy = DAG.getMachineNode(TargetOpcode::COPY_TO_REGCLASS,
Andrew Trickef9de2a2013-05-25 02:42:55 +00004086 SDLoc(), Users[Lane]->getValueType(0),
Christian Konig8b1ed282013-04-10 08:39:16 +00004087 SDValue(Node, 0), RC);
4088 DAG.ReplaceAllUsesWith(Users[Lane], Copy);
4089 return;
4090 }
4091
Christian Konig8e06e2a2013-04-10 08:39:08 +00004092 // Update the users of the node with the new indices
4093 for (unsigned i = 0, Idx = AMDGPU::sub0; i < 4; ++i) {
4094
4095 SDNode *User = Users[i];
4096 if (!User)
4097 continue;
4098
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00004099 SDValue Op = DAG.getTargetConstant(Idx, SDLoc(User), MVT::i32);
Christian Konig8e06e2a2013-04-10 08:39:08 +00004100 DAG.UpdateNodeOperands(User, User->getOperand(0), Op);
4101
4102 switch (Idx) {
4103 default: break;
4104 case AMDGPU::sub0: Idx = AMDGPU::sub1; break;
4105 case AMDGPU::sub1: Idx = AMDGPU::sub2; break;
4106 case AMDGPU::sub2: Idx = AMDGPU::sub3; break;
4107 }
4108 }
4109}
4110
Tom Stellardc98ee202015-07-16 19:40:07 +00004111static bool isFrameIndexOp(SDValue Op) {
4112 if (Op.getOpcode() == ISD::AssertZext)
4113 Op = Op.getOperand(0);
4114
4115 return isa<FrameIndexSDNode>(Op);
4116}
4117
Tom Stellard3457a842014-10-09 19:06:00 +00004118/// \brief Legalize target independent instructions (e.g. INSERT_SUBREG)
4119/// with frame index operands.
4120/// LLVM assumes that inputs are to these instructions are registers.
4121void SITargetLowering::legalizeTargetIndependentNode(SDNode *Node,
4122 SelectionDAG &DAG) const {
Tom Stellard8dd392e2014-10-09 18:09:15 +00004123
4124 SmallVector<SDValue, 8> Ops;
Tom Stellard3457a842014-10-09 19:06:00 +00004125 for (unsigned i = 0; i < Node->getNumOperands(); ++i) {
Tom Stellardc98ee202015-07-16 19:40:07 +00004126 if (!isFrameIndexOp(Node->getOperand(i))) {
Tom Stellard3457a842014-10-09 19:06:00 +00004127 Ops.push_back(Node->getOperand(i));
Tom Stellard8dd392e2014-10-09 18:09:15 +00004128 continue;
4129 }
4130
Tom Stellard3457a842014-10-09 19:06:00 +00004131 SDLoc DL(Node);
Tom Stellard8dd392e2014-10-09 18:09:15 +00004132 Ops.push_back(SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL,
Tom Stellard3457a842014-10-09 19:06:00 +00004133 Node->getOperand(i).getValueType(),
4134 Node->getOperand(i)), 0));
Tom Stellard8dd392e2014-10-09 18:09:15 +00004135 }
4136
Tom Stellard3457a842014-10-09 19:06:00 +00004137 DAG.UpdateNodeOperands(Node, Ops);
Tom Stellard8dd392e2014-10-09 18:09:15 +00004138}
4139
Matt Arsenault08d84942014-06-03 23:06:13 +00004140/// \brief Fold the instructions after selecting them.
Christian Konig8e06e2a2013-04-10 08:39:08 +00004141SDNode *SITargetLowering::PostISelFolding(MachineSDNode *Node,
4142 SelectionDAG &DAG) const {
Matt Arsenault43e92fe2016-06-24 06:30:11 +00004143 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
Nicolai Haehnlef2c64db2016-02-18 16:44:18 +00004144 unsigned Opcode = Node->getMachineOpcode();
Christian Konig8e06e2a2013-04-10 08:39:08 +00004145
Nicolai Haehnlec06bfa12016-07-11 21:59:43 +00004146 if (TII->isMIMG(Opcode) && !TII->get(Opcode).mayStore() &&
4147 !TII->isGather4(Opcode))
Christian Konig8e06e2a2013-04-10 08:39:08 +00004148 adjustWritemask(Node, DAG);
4149
Nicolai Haehnlef2c64db2016-02-18 16:44:18 +00004150 if (Opcode == AMDGPU::INSERT_SUBREG ||
4151 Opcode == AMDGPU::REG_SEQUENCE) {
Tom Stellard8dd392e2014-10-09 18:09:15 +00004152 legalizeTargetIndependentNode(Node, DAG);
4153 return Node;
4154 }
Tom Stellard654d6692015-01-08 15:08:17 +00004155 return Node;
Christian Konig8e06e2a2013-04-10 08:39:08 +00004156}
Christian Konig8b1ed282013-04-10 08:39:16 +00004157
4158/// \brief Assign the register class depending on the number of
4159/// bits set in the writemask
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00004160void SITargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
Christian Konig8b1ed282013-04-10 08:39:16 +00004161 SDNode *Node) const {
Matt Arsenault43e92fe2016-06-24 06:30:11 +00004162 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
Matt Arsenault7ac9c4a2014-09-08 15:07:31 +00004163
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00004164 MachineRegisterInfo &MRI = MI.getParent()->getParent()->getRegInfo();
Matt Arsenault6005fcb2015-10-21 21:51:02 +00004165
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00004166 if (TII->isVOP3(MI.getOpcode())) {
Matt Arsenault6005fcb2015-10-21 21:51:02 +00004167 // Make sure constant bus requirements are respected.
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00004168 TII->legalizeOperandsVOP3(MRI, MI);
Matt Arsenault6005fcb2015-10-21 21:51:02 +00004169 return;
4170 }
Matt Arsenaultcb0ac3d2014-09-26 17:54:59 +00004171
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00004172 if (TII->isMIMG(MI)) {
4173 unsigned VReg = MI.getOperand(0).getReg();
Changpeng Fang8236fe12016-11-14 18:33:18 +00004174 const TargetRegisterClass *RC = MRI.getRegClass(VReg);
4175 // TODO: Need mapping tables to handle other cases (register classes).
4176 if (RC != &AMDGPU::VReg_128RegClass)
4177 return;
4178
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00004179 unsigned DmaskIdx = MI.getNumOperands() == 12 ? 3 : 4;
4180 unsigned Writemask = MI.getOperand(DmaskIdx).getImm();
Matt Arsenault7ac9c4a2014-09-08 15:07:31 +00004181 unsigned BitsSet = 0;
4182 for (unsigned i = 0; i < 4; ++i)
4183 BitsSet += Writemask & (1 << i) ? 1 : 0;
Matt Arsenault7ac9c4a2014-09-08 15:07:31 +00004184 switch (BitsSet) {
4185 default: return;
Tom Stellard45c0b3a2015-01-07 20:59:25 +00004186 case 1: RC = &AMDGPU::VGPR_32RegClass; break;
Matt Arsenault7ac9c4a2014-09-08 15:07:31 +00004187 case 2: RC = &AMDGPU::VReg_64RegClass; break;
4188 case 3: RC = &AMDGPU::VReg_96RegClass; break;
4189 }
4190
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00004191 unsigned NewOpcode = TII->getMaskedMIMGOp(MI.getOpcode(), BitsSet);
4192 MI.setDesc(TII->get(NewOpcode));
Matt Arsenault7ac9c4a2014-09-08 15:07:31 +00004193 MRI.setRegClass(VReg, RC);
Christian Konig8b1ed282013-04-10 08:39:16 +00004194 return;
Christian Konig8b1ed282013-04-10 08:39:16 +00004195 }
4196
Matt Arsenault7ac9c4a2014-09-08 15:07:31 +00004197 // Replace unused atomics with the no return version.
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00004198 int NoRetAtomicOp = AMDGPU::getAtomicNoRetOp(MI.getOpcode());
Matt Arsenault7ac9c4a2014-09-08 15:07:31 +00004199 if (NoRetAtomicOp != -1) {
4200 if (!Node->hasAnyUseOfValue(0)) {
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00004201 MI.setDesc(TII->get(NoRetAtomicOp));
4202 MI.RemoveOperand(0);
Tom Stellard354a43c2016-04-01 18:27:37 +00004203 return;
Matt Arsenault7ac9c4a2014-09-08 15:07:31 +00004204 }
4205
Tom Stellard354a43c2016-04-01 18:27:37 +00004206 // For mubuf_atomic_cmpswap, we need to have tablegen use an extract_subreg
4207 // instruction, because the return type of these instructions is a vec2 of
4208 // the memory type, so it can be tied to the input operand.
4209 // This means these instructions always have a use, so we need to add a
4210 // special case to check if the atomic has only one extract_subreg use,
4211 // which itself has no uses.
4212 if ((Node->hasNUsesOfValue(1, 0) &&
Nicolai Haehnle750082d2016-04-15 14:42:36 +00004213 Node->use_begin()->isMachineOpcode() &&
Tom Stellard354a43c2016-04-01 18:27:37 +00004214 Node->use_begin()->getMachineOpcode() == AMDGPU::EXTRACT_SUBREG &&
4215 !Node->use_begin()->hasAnyUseOfValue(0))) {
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00004216 unsigned Def = MI.getOperand(0).getReg();
Tom Stellard354a43c2016-04-01 18:27:37 +00004217
4218 // Change this into a noret atomic.
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00004219 MI.setDesc(TII->get(NoRetAtomicOp));
4220 MI.RemoveOperand(0);
Tom Stellard354a43c2016-04-01 18:27:37 +00004221
4222 // If we only remove the def operand from the atomic instruction, the
4223 // extract_subreg will be left with a use of a vreg without a def.
4224 // So we need to insert an implicit_def to avoid machine verifier
4225 // errors.
Duncan P. N. Exon Smithe4f5e4f2016-06-30 22:52:52 +00004226 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(),
Tom Stellard354a43c2016-04-01 18:27:37 +00004227 TII->get(AMDGPU::IMPLICIT_DEF), Def);
4228 }
Matt Arsenault7ac9c4a2014-09-08 15:07:31 +00004229 return;
4230 }
Christian Konig8b1ed282013-04-10 08:39:16 +00004231}
Tom Stellard0518ff82013-06-03 17:39:58 +00004232
Benjamin Kramerbdc49562016-06-12 15:39:02 +00004233static SDValue buildSMovImm32(SelectionDAG &DAG, const SDLoc &DL,
4234 uint64_t Val) {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00004235 SDValue K = DAG.getTargetConstant(Val, DL, MVT::i32);
Matt Arsenault485defe2014-11-05 19:01:17 +00004236 return SDValue(DAG.getMachineNode(AMDGPU::S_MOV_B32, DL, MVT::i32, K), 0);
4237}
4238
4239MachineSDNode *SITargetLowering::wrapAddr64Rsrc(SelectionDAG &DAG,
Benjamin Kramerbdc49562016-06-12 15:39:02 +00004240 const SDLoc &DL,
Matt Arsenault485defe2014-11-05 19:01:17 +00004241 SDValue Ptr) const {
Matt Arsenault43e92fe2016-06-24 06:30:11 +00004242 const SIInstrInfo *TII = getSubtarget()->getInstrInfo();
Matt Arsenault485defe2014-11-05 19:01:17 +00004243
Matt Arsenault2d6fdb82015-09-25 17:08:42 +00004244 // Build the half of the subregister with the constants before building the
4245 // full 128-bit register. If we are building multiple resource descriptors,
4246 // this will allow CSEing of the 2-component register.
4247 const SDValue Ops0[] = {
4248 DAG.getTargetConstant(AMDGPU::SGPR_64RegClassID, DL, MVT::i32),
4249 buildSMovImm32(DAG, DL, 0),
4250 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
4251 buildSMovImm32(DAG, DL, TII->getDefaultRsrcDataFormat() >> 32),
4252 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32)
4253 };
Matt Arsenault485defe2014-11-05 19:01:17 +00004254
Matt Arsenault2d6fdb82015-09-25 17:08:42 +00004255 SDValue SubRegHi = SDValue(DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL,
4256 MVT::v2i32, Ops0), 0);
Matt Arsenault485defe2014-11-05 19:01:17 +00004257
Matt Arsenault2d6fdb82015-09-25 17:08:42 +00004258 // Combine the constants and the pointer.
4259 const SDValue Ops1[] = {
4260 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
4261 Ptr,
4262 DAG.getTargetConstant(AMDGPU::sub0_sub1, DL, MVT::i32),
4263 SubRegHi,
4264 DAG.getTargetConstant(AMDGPU::sub2_sub3, DL, MVT::i32)
4265 };
Matt Arsenault485defe2014-11-05 19:01:17 +00004266
Matt Arsenault2d6fdb82015-09-25 17:08:42 +00004267 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops1);
Matt Arsenault485defe2014-11-05 19:01:17 +00004268}
4269
Matt Arsenaultf3cd4512014-11-05 19:01:19 +00004270/// \brief Return a resource descriptor with the 'Add TID' bit enabled
Benjamin Kramerdf005cb2015-08-08 18:27:36 +00004271/// The TID (Thread ID) is multiplied by the stride value (bits [61:48]
4272/// of the resource descriptor) to create an offset, which is added to
4273/// the resource pointer.
Benjamin Kramerbdc49562016-06-12 15:39:02 +00004274MachineSDNode *SITargetLowering::buildRSRC(SelectionDAG &DAG, const SDLoc &DL,
4275 SDValue Ptr, uint32_t RsrcDword1,
Matt Arsenaultf3cd4512014-11-05 19:01:19 +00004276 uint64_t RsrcDword2And3) const {
4277 SDValue PtrLo = DAG.getTargetExtractSubreg(AMDGPU::sub0, DL, MVT::i32, Ptr);
4278 SDValue PtrHi = DAG.getTargetExtractSubreg(AMDGPU::sub1, DL, MVT::i32, Ptr);
4279 if (RsrcDword1) {
4280 PtrHi = SDValue(DAG.getMachineNode(AMDGPU::S_OR_B32, DL, MVT::i32, PtrHi,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00004281 DAG.getConstant(RsrcDword1, DL, MVT::i32)),
4282 0);
Matt Arsenaultf3cd4512014-11-05 19:01:19 +00004283 }
4284
4285 SDValue DataLo = buildSMovImm32(DAG, DL,
4286 RsrcDword2And3 & UINT64_C(0xFFFFFFFF));
4287 SDValue DataHi = buildSMovImm32(DAG, DL, RsrcDword2And3 >> 32);
4288
4289 const SDValue Ops[] = {
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00004290 DAG.getTargetConstant(AMDGPU::SReg_128RegClassID, DL, MVT::i32),
Matt Arsenaultf3cd4512014-11-05 19:01:19 +00004291 PtrLo,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00004292 DAG.getTargetConstant(AMDGPU::sub0, DL, MVT::i32),
Matt Arsenaultf3cd4512014-11-05 19:01:19 +00004293 PtrHi,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00004294 DAG.getTargetConstant(AMDGPU::sub1, DL, MVT::i32),
Matt Arsenaultf3cd4512014-11-05 19:01:19 +00004295 DataLo,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00004296 DAG.getTargetConstant(AMDGPU::sub2, DL, MVT::i32),
Matt Arsenaultf3cd4512014-11-05 19:01:19 +00004297 DataHi,
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +00004298 DAG.getTargetConstant(AMDGPU::sub3, DL, MVT::i32)
Matt Arsenaultf3cd4512014-11-05 19:01:19 +00004299 };
4300
4301 return DAG.getMachineNode(AMDGPU::REG_SEQUENCE, DL, MVT::v4i32, Ops);
4302}
4303
Tom Stellard94593ee2013-06-03 17:40:18 +00004304SDValue SITargetLowering::CreateLiveInRegister(SelectionDAG &DAG,
4305 const TargetRegisterClass *RC,
4306 unsigned Reg, EVT VT) const {
4307 SDValue VReg = AMDGPUTargetLowering::CreateLiveInRegister(DAG, RC, Reg, VT);
4308
4309 return DAG.getCopyFromReg(DAG.getEntryNode(), SDLoc(DAG.getEntryNode()),
4310 cast<RegisterSDNode>(VReg)->getReg(), VT);
4311}
Tom Stellardd7e6f132015-04-08 01:09:26 +00004312
4313//===----------------------------------------------------------------------===//
4314// SI Inline Assembly Support
4315//===----------------------------------------------------------------------===//
4316
4317std::pair<unsigned, const TargetRegisterClass *>
4318SITargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
Benjamin Kramer9bfb6272015-07-05 19:29:18 +00004319 StringRef Constraint,
Tom Stellardd7e6f132015-04-08 01:09:26 +00004320 MVT VT) const {
Matt Arsenault742deb22016-11-18 04:42:57 +00004321 if (!isTypeLegal(VT))
4322 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
Tom Stellardb3c3bda2015-12-10 02:12:53 +00004323
4324 if (Constraint.size() == 1) {
4325 switch (Constraint[0]) {
4326 case 's':
4327 case 'r':
4328 switch (VT.getSizeInBits()) {
4329 default:
4330 return std::make_pair(0U, nullptr);
4331 case 32:
Marek Olsak79c05872016-11-25 17:37:09 +00004332 return std::make_pair(0U, &AMDGPU::SReg_32_XM0RegClass);
Tom Stellardb3c3bda2015-12-10 02:12:53 +00004333 case 64:
4334 return std::make_pair(0U, &AMDGPU::SGPR_64RegClass);
4335 case 128:
4336 return std::make_pair(0U, &AMDGPU::SReg_128RegClass);
4337 case 256:
4338 return std::make_pair(0U, &AMDGPU::SReg_256RegClass);
4339 }
4340
4341 case 'v':
4342 switch (VT.getSizeInBits()) {
4343 default:
4344 return std::make_pair(0U, nullptr);
4345 case 32:
4346 return std::make_pair(0U, &AMDGPU::VGPR_32RegClass);
4347 case 64:
4348 return std::make_pair(0U, &AMDGPU::VReg_64RegClass);
4349 case 96:
4350 return std::make_pair(0U, &AMDGPU::VReg_96RegClass);
4351 case 128:
4352 return std::make_pair(0U, &AMDGPU::VReg_128RegClass);
4353 case 256:
4354 return std::make_pair(0U, &AMDGPU::VReg_256RegClass);
4355 case 512:
4356 return std::make_pair(0U, &AMDGPU::VReg_512RegClass);
4357 }
Tom Stellardd7e6f132015-04-08 01:09:26 +00004358 }
4359 }
4360
4361 if (Constraint.size() > 1) {
4362 const TargetRegisterClass *RC = nullptr;
4363 if (Constraint[1] == 'v') {
4364 RC = &AMDGPU::VGPR_32RegClass;
4365 } else if (Constraint[1] == 's') {
4366 RC = &AMDGPU::SGPR_32RegClass;
4367 }
4368
4369 if (RC) {
Matt Arsenault0b554ed2015-06-23 02:05:55 +00004370 uint32_t Idx;
4371 bool Failed = Constraint.substr(2).getAsInteger(10, Idx);
4372 if (!Failed && Idx < RC->getNumRegs())
Tom Stellardd7e6f132015-04-08 01:09:26 +00004373 return std::make_pair(RC->getRegister(Idx), RC);
4374 }
4375 }
4376 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
4377}
Tom Stellardb3c3bda2015-12-10 02:12:53 +00004378
4379SITargetLowering::ConstraintType
4380SITargetLowering::getConstraintType(StringRef Constraint) const {
4381 if (Constraint.size() == 1) {
4382 switch (Constraint[0]) {
4383 default: break;
4384 case 's':
4385 case 'v':
4386 return C_RegisterClass;
4387 }
4388 }
4389 return TargetLowering::getConstraintType(Constraint);
4390}