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Daniel Dunbar71475772009-07-17 20:42:00 +00001//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
Evan Cheng11424442011-07-26 00:24:13 +000010#include "MCTargetDesc/X86BaseInfo.h"
Evgeniy Stepanov49e26252014-03-14 08:58:04 +000011#include "X86AsmInstrumentation.h"
Evgeniy Stepanove3804d42014-02-28 12:28:07 +000012#include "X86AsmParserCommon.h"
13#include "X86Operand.h"
Coby Tayreed8912892017-08-24 08:46:25 +000014#include "InstPrinter/X86IntelInstPrinter.h"
Craig Topper690d8ea2013-07-24 07:33:14 +000015#include "llvm/ADT/STLExtras.h"
Chris Lattner1261b812010-09-22 04:11:10 +000016#include "llvm/ADT/SmallString.h"
17#include "llvm/ADT/SmallVector.h"
Chris Lattner1261b812010-09-22 04:11:10 +000018#include "llvm/ADT/StringSwitch.h"
19#include "llvm/ADT/Twine.h"
Chad Rosier8a244662013-04-02 20:02:33 +000020#include "llvm/MC/MCContext.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000021#include "llvm/MC/MCExpr.h"
22#include "llvm/MC/MCInst.h"
Evgeniy Stepanovf4a36992014-04-24 13:29:34 +000023#include "llvm/MC/MCInstrInfo.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000024#include "llvm/MC/MCParser/MCAsmLexer.h"
25#include "llvm/MC/MCParser/MCAsmParser.h"
26#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
Benjamin Kramerb3e8a6d2016-01-27 10:01:28 +000027#include "llvm/MC/MCParser/MCTargetAsmParser.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000028#include "llvm/MC/MCRegisterInfo.h"
Michael Zuckerman02ecd432015-12-13 17:07:23 +000029#include "llvm/MC/MCSection.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000030#include "llvm/MC/MCStreamer.h"
31#include "llvm/MC/MCSubtargetInfo.h"
32#include "llvm/MC/MCSymbol.h"
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +000033#include "llvm/Support/SourceMgr.h"
Evan Cheng2bb40352011-08-24 18:08:43 +000034#include "llvm/Support/TargetRegistry.h"
Daniel Dunbar7d7b4d12010-08-12 00:55:42 +000035#include "llvm/Support/raw_ostream.h"
Reid Kleckner7b1e1a02014-07-30 22:23:11 +000036#include <algorithm>
Evgeniy Stepanov49e26252014-03-14 08:58:04 +000037#include <memory>
Evan Cheng4d1ca962011-07-08 01:53:10 +000038
Daniel Dunbar71475772009-07-17 20:42:00 +000039using namespace llvm;
40
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +000041static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
42 if (Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
43 ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
44 return true;
45 }
46 return false;
47}
48
Daniel Dunbar71475772009-07-17 20:42:00 +000049namespace {
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +000050
Chad Rosier5362af92013-04-16 18:15:40 +000051static const char OpPrecedence[] = {
Kevin Enderby2e13b1c2014-01-15 19:05:24 +000052 0, // IC_OR
Michael Kupersteine3de07a2015-06-14 12:59:45 +000053 1, // IC_XOR
54 2, // IC_AND
55 3, // IC_LSHIFT
56 3, // IC_RSHIFT
57 4, // IC_PLUS
58 4, // IC_MINUS
59 5, // IC_MULTIPLY
60 5, // IC_DIVIDE
Coby Tayree41a5b552017-06-27 16:58:27 +000061 5, // IC_MOD
62 6, // IC_NOT
63 7, // IC_NEG
64 8, // IC_RPAREN
65 9, // IC_LPAREN
Chad Rosier5362af92013-04-16 18:15:40 +000066 0, // IC_IMM
67 0 // IC_REGISTER
68};
69
Devang Patel4a6e7782012-01-12 18:03:40 +000070class X86AsmParser : public MCTargetAsmParser {
Chad Rosierf0e87202012-10-25 20:41:34 +000071 ParseInstructionInfo *InstInfo;
Evgeniy Stepanov49e26252014-03-14 08:58:04 +000072 std::unique_ptr<X86AsmInstrumentation> Instrumentation;
Nirav Dave6477ce22016-09-26 19:33:36 +000073 bool Code16GCC;
NAKAMURA Takumia9cb5382015-09-22 11:14:39 +000074
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +000075private:
Alp Tokera5b88a52013-12-02 16:06:06 +000076 SMLoc consumeToken() {
Rafael Espindola961d4692014-11-11 05:18:41 +000077 MCAsmParser &Parser = getParser();
Alp Tokera5b88a52013-12-02 16:06:06 +000078 SMLoc Result = Parser.getTok().getLoc();
79 Parser.Lex();
80 return Result;
81 }
82
Nirav Dave6477ce22016-09-26 19:33:36 +000083 unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
84 uint64_t &ErrorInfo, bool matchingInlineAsm,
85 unsigned VariantID = 0) {
86 // In Code16GCC mode, match as 32-bit.
87 if (Code16GCC)
88 SwitchMode(X86::Mode32Bit);
89 unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo,
90 matchingInlineAsm, VariantID);
91 if (Code16GCC)
92 SwitchMode(X86::Mode16Bit);
93 return rv;
94 }
95
Chad Rosier5362af92013-04-16 18:15:40 +000096 enum InfixCalculatorTok {
Kevin Enderby2e13b1c2014-01-15 19:05:24 +000097 IC_OR = 0,
Michael Kupersteine3de07a2015-06-14 12:59:45 +000098 IC_XOR,
Kevin Enderby2e13b1c2014-01-15 19:05:24 +000099 IC_AND,
Kevin Enderbyd6b10712014-02-06 01:21:15 +0000100 IC_LSHIFT,
101 IC_RSHIFT,
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000102 IC_PLUS,
Chad Rosier5362af92013-04-16 18:15:40 +0000103 IC_MINUS,
104 IC_MULTIPLY,
105 IC_DIVIDE,
Coby Tayree41a5b552017-06-27 16:58:27 +0000106 IC_MOD,
107 IC_NOT,
108 IC_NEG,
Chad Rosier5362af92013-04-16 18:15:40 +0000109 IC_RPAREN,
110 IC_LPAREN,
111 IC_IMM,
112 IC_REGISTER
113 };
114
Coby Tayree07a89742017-03-21 19:31:55 +0000115 enum IntelOperatorKind {
116 IOK_INVALID = 0,
117 IOK_LENGTH,
118 IOK_SIZE,
119 IOK_TYPE,
120 IOK_OFFSET
121 };
122
Chad Rosier5362af92013-04-16 18:15:40 +0000123 class InfixCalculator {
124 typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
125 SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
126 SmallVector<ICToken, 4> PostfixStack;
Michael Liao5bf95782014-12-04 05:20:33 +0000127
Coby Tayree41a5b552017-06-27 16:58:27 +0000128 bool isUnaryOperator(const InfixCalculatorTok Op) {
129 return Op == IC_NEG || Op == IC_NOT;
130 }
131
Chad Rosier5362af92013-04-16 18:15:40 +0000132 public:
133 int64_t popOperand() {
134 assert (!PostfixStack.empty() && "Poped an empty stack!");
135 ICToken Op = PostfixStack.pop_back_val();
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000136 if (!(Op.first == IC_IMM || Op.first == IC_REGISTER))
137 return -1; // The invalid Scale value will be caught later by checkScale
Chad Rosier5362af92013-04-16 18:15:40 +0000138 return Op.second;
139 }
140 void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
141 assert ((Op == IC_IMM || Op == IC_REGISTER) &&
142 "Unexpected operand!");
143 PostfixStack.push_back(std::make_pair(Op, Val));
144 }
Michael Liao5bf95782014-12-04 05:20:33 +0000145
Jakub Staszak9c349222013-08-08 15:48:46 +0000146 void popOperator() { InfixOperatorStack.pop_back(); }
Chad Rosier5362af92013-04-16 18:15:40 +0000147 void pushOperator(InfixCalculatorTok Op) {
148 // Push the new operator if the stack is empty.
149 if (InfixOperatorStack.empty()) {
150 InfixOperatorStack.push_back(Op);
151 return;
152 }
Michael Liao5bf95782014-12-04 05:20:33 +0000153
Chad Rosier5362af92013-04-16 18:15:40 +0000154 // Push the new operator if it has a higher precedence than the operator
155 // on the top of the stack or the operator on the top of the stack is a
156 // left parentheses.
157 unsigned Idx = InfixOperatorStack.size() - 1;
158 InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
159 if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
160 InfixOperatorStack.push_back(Op);
161 return;
162 }
Michael Liao5bf95782014-12-04 05:20:33 +0000163
Chad Rosier5362af92013-04-16 18:15:40 +0000164 // The operator on the top of the stack has higher precedence than the
165 // new operator.
166 unsigned ParenCount = 0;
Kirill Bobyrev6afbaf02017-01-18 16:34:25 +0000167 while (1) {
Chad Rosier5362af92013-04-16 18:15:40 +0000168 // Nothing to process.
169 if (InfixOperatorStack.empty())
170 break;
Michael Liao5bf95782014-12-04 05:20:33 +0000171
Chad Rosier5362af92013-04-16 18:15:40 +0000172 Idx = InfixOperatorStack.size() - 1;
173 StackOp = InfixOperatorStack[Idx];
174 if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
175 break;
Michael Liao5bf95782014-12-04 05:20:33 +0000176
Chad Rosier5362af92013-04-16 18:15:40 +0000177 // If we have an even parentheses count and we see a left parentheses,
178 // then stop processing.
179 if (!ParenCount && StackOp == IC_LPAREN)
180 break;
Michael Liao5bf95782014-12-04 05:20:33 +0000181
Chad Rosier5362af92013-04-16 18:15:40 +0000182 if (StackOp == IC_RPAREN) {
183 ++ParenCount;
Jakub Staszak9c349222013-08-08 15:48:46 +0000184 InfixOperatorStack.pop_back();
Chad Rosier5362af92013-04-16 18:15:40 +0000185 } else if (StackOp == IC_LPAREN) {
186 --ParenCount;
Jakub Staszak9c349222013-08-08 15:48:46 +0000187 InfixOperatorStack.pop_back();
Chad Rosier5362af92013-04-16 18:15:40 +0000188 } else {
Jakub Staszak9c349222013-08-08 15:48:46 +0000189 InfixOperatorStack.pop_back();
Chad Rosier5362af92013-04-16 18:15:40 +0000190 PostfixStack.push_back(std::make_pair(StackOp, 0));
191 }
192 }
193 // Push the new operator.
194 InfixOperatorStack.push_back(Op);
195 }
Marina Yatsinaa0e02412015-08-10 11:33:10 +0000196
Chad Rosier5362af92013-04-16 18:15:40 +0000197 int64_t execute() {
198 // Push any remaining operators onto the postfix stack.
199 while (!InfixOperatorStack.empty()) {
200 InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
201 if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
202 PostfixStack.push_back(std::make_pair(StackOp, 0));
203 }
Michael Liao5bf95782014-12-04 05:20:33 +0000204
Chad Rosier5362af92013-04-16 18:15:40 +0000205 if (PostfixStack.empty())
206 return 0;
Michael Liao5bf95782014-12-04 05:20:33 +0000207
Chad Rosier5362af92013-04-16 18:15:40 +0000208 SmallVector<ICToken, 16> OperandStack;
209 for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
210 ICToken Op = PostfixStack[i];
211 if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
212 OperandStack.push_back(Op);
Coby Tayree41a5b552017-06-27 16:58:27 +0000213 } else if (isUnaryOperator(Op.first)) {
214 assert (OperandStack.size() > 0 && "Too few operands.");
215 ICToken Operand = OperandStack.pop_back_val();
216 assert (Operand.first == IC_IMM &&
217 "Unary operation with a register!");
218 switch (Op.first) {
219 default:
220 report_fatal_error("Unexpected operator!");
221 break;
222 case IC_NEG:
223 OperandStack.push_back(std::make_pair(IC_IMM, -Operand.second));
224 break;
225 case IC_NOT:
226 OperandStack.push_back(std::make_pair(IC_IMM, ~Operand.second));
227 break;
228 }
Chad Rosier5362af92013-04-16 18:15:40 +0000229 } else {
230 assert (OperandStack.size() > 1 && "Too few operands.");
231 int64_t Val;
232 ICToken Op2 = OperandStack.pop_back_val();
233 ICToken Op1 = OperandStack.pop_back_val();
234 switch (Op.first) {
235 default:
236 report_fatal_error("Unexpected operator!");
237 break;
238 case IC_PLUS:
239 Val = Op1.second + Op2.second;
240 OperandStack.push_back(std::make_pair(IC_IMM, Val));
241 break;
242 case IC_MINUS:
243 Val = Op1.second - Op2.second;
244 OperandStack.push_back(std::make_pair(IC_IMM, Val));
245 break;
246 case IC_MULTIPLY:
247 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
248 "Multiply operation with an immediate and a register!");
249 Val = Op1.second * Op2.second;
250 OperandStack.push_back(std::make_pair(IC_IMM, Val));
251 break;
252 case IC_DIVIDE:
253 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
254 "Divide operation with an immediate and a register!");
255 assert (Op2.second != 0 && "Division by zero!");
256 Val = Op1.second / Op2.second;
257 OperandStack.push_back(std::make_pair(IC_IMM, Val));
258 break;
Coby Tayree41a5b552017-06-27 16:58:27 +0000259 case IC_MOD:
260 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
261 "Modulo operation with an immediate and a register!");
262 Val = Op1.second % Op2.second;
263 OperandStack.push_back(std::make_pair(IC_IMM, Val));
264 break;
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000265 case IC_OR:
266 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
267 "Or operation with an immediate and a register!");
268 Val = Op1.second | Op2.second;
269 OperandStack.push_back(std::make_pair(IC_IMM, Val));
270 break;
Michael Kupersteine3de07a2015-06-14 12:59:45 +0000271 case IC_XOR:
272 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
273 "Xor operation with an immediate and a register!");
274 Val = Op1.second ^ Op2.second;
275 OperandStack.push_back(std::make_pair(IC_IMM, Val));
276 break;
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000277 case IC_AND:
278 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
279 "And operation with an immediate and a register!");
280 Val = Op1.second & Op2.second;
281 OperandStack.push_back(std::make_pair(IC_IMM, Val));
282 break;
Kevin Enderbyd6b10712014-02-06 01:21:15 +0000283 case IC_LSHIFT:
284 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
285 "Left shift operation with an immediate and a register!");
286 Val = Op1.second << Op2.second;
287 OperandStack.push_back(std::make_pair(IC_IMM, Val));
288 break;
289 case IC_RSHIFT:
290 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
291 "Right shift operation with an immediate and a register!");
292 Val = Op1.second >> Op2.second;
293 OperandStack.push_back(std::make_pair(IC_IMM, Val));
294 break;
Chad Rosier5362af92013-04-16 18:15:40 +0000295 }
296 }
297 }
298 assert (OperandStack.size() == 1 && "Expected a single result.");
299 return OperandStack.pop_back_val().second;
300 }
301 };
302
303 enum IntelExprState {
Coby Tayreed8912892017-08-24 08:46:25 +0000304 IES_INIT,
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000305 IES_OR,
Michael Kupersteine3de07a2015-06-14 12:59:45 +0000306 IES_XOR,
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000307 IES_AND,
Kevin Enderbyd6b10712014-02-06 01:21:15 +0000308 IES_LSHIFT,
309 IES_RSHIFT,
Chad Rosier5362af92013-04-16 18:15:40 +0000310 IES_PLUS,
311 IES_MINUS,
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000312 IES_NOT,
Chad Rosier5362af92013-04-16 18:15:40 +0000313 IES_MULTIPLY,
314 IES_DIVIDE,
Coby Tayree41a5b552017-06-27 16:58:27 +0000315 IES_MOD,
Chad Rosier5362af92013-04-16 18:15:40 +0000316 IES_LBRAC,
317 IES_RBRAC,
318 IES_LPAREN,
319 IES_RPAREN,
320 IES_REGISTER,
Chad Rosier5362af92013-04-16 18:15:40 +0000321 IES_INTEGER,
Chad Rosier5362af92013-04-16 18:15:40 +0000322 IES_IDENTIFIER,
323 IES_ERROR
324 };
325
326 class IntelExprStateMachine {
Chad Rosier31246272013-04-17 21:01:45 +0000327 IntelExprState State, PrevState;
Chad Rosier5362af92013-04-16 18:15:40 +0000328 unsigned BaseReg, IndexReg, TmpReg, Scale;
Chad Rosierbfb70992013-04-17 00:11:46 +0000329 int64_t Imm;
Chad Rosier5362af92013-04-16 18:15:40 +0000330 const MCExpr *Sym;
331 StringRef SymName;
332 InfixCalculator IC;
Chad Rosiercb78f0d2013-04-22 19:42:15 +0000333 InlineAsmIdentifierInfo Info;
Coby Tayreed8912892017-08-24 08:46:25 +0000334 short BracCount;
335 bool MemExpr;
NAKAMURA Takumia9cb5382015-09-22 11:14:39 +0000336
Chad Rosier5362af92013-04-16 18:15:40 +0000337 public:
Coby Tayreed8912892017-08-24 08:46:25 +0000338 IntelExprStateMachine()
339 : State(IES_INIT), PrevState(IES_ERROR), BaseReg(0), IndexReg(0),
340 TmpReg(0), Scale(1), Imm(0), Sym(nullptr), BracCount(0),
Coby Tayreec3d24112017-09-29 07:02:46 +0000341 MemExpr(false) {}
Michael Liao5bf95782014-12-04 05:20:33 +0000342
Coby Tayreed8912892017-08-24 08:46:25 +0000343 void addImm(int64_t imm) { Imm += imm; }
344 short getBracCount() { return BracCount; }
345 bool isMemExpr() { return MemExpr; }
Chad Rosier5362af92013-04-16 18:15:40 +0000346 unsigned getBaseReg() { return BaseReg; }
347 unsigned getIndexReg() { return IndexReg; }
348 unsigned getScale() { return Scale; }
349 const MCExpr *getSym() { return Sym; }
350 StringRef getSymName() { return SymName; }
Chad Rosierbfb70992013-04-17 00:11:46 +0000351 int64_t getImm() { return Imm + IC.execute(); }
Chad Rosieredb1dc82013-05-09 23:48:53 +0000352 bool isValidEndState() {
353 return State == IES_RBRAC || State == IES_INTEGER;
354 }
Chad Rosier31246272013-04-17 21:01:45 +0000355 bool hadError() { return State == IES_ERROR; }
Coby Tayreed8912892017-08-24 08:46:25 +0000356 InlineAsmIdentifierInfo &getIdentifierInfo() { return Info; }
Chad Rosiercb78f0d2013-04-22 19:42:15 +0000357
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000358 void onOr() {
359 IntelExprState CurrState = State;
360 switch (State) {
361 default:
362 State = IES_ERROR;
363 break;
364 case IES_INTEGER:
365 case IES_RPAREN:
366 case IES_REGISTER:
367 State = IES_OR;
368 IC.pushOperator(IC_OR);
369 break;
370 }
371 PrevState = CurrState;
372 }
Michael Kupersteine3de07a2015-06-14 12:59:45 +0000373 void onXor() {
374 IntelExprState CurrState = State;
375 switch (State) {
376 default:
377 State = IES_ERROR;
378 break;
379 case IES_INTEGER:
380 case IES_RPAREN:
381 case IES_REGISTER:
382 State = IES_XOR;
383 IC.pushOperator(IC_XOR);
384 break;
385 }
386 PrevState = CurrState;
387 }
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000388 void onAnd() {
389 IntelExprState CurrState = State;
390 switch (State) {
391 default:
392 State = IES_ERROR;
393 break;
394 case IES_INTEGER:
395 case IES_RPAREN:
396 case IES_REGISTER:
397 State = IES_AND;
398 IC.pushOperator(IC_AND);
399 break;
400 }
401 PrevState = CurrState;
402 }
Kevin Enderbyd6b10712014-02-06 01:21:15 +0000403 void onLShift() {
404 IntelExprState CurrState = State;
405 switch (State) {
406 default:
407 State = IES_ERROR;
408 break;
409 case IES_INTEGER:
410 case IES_RPAREN:
411 case IES_REGISTER:
412 State = IES_LSHIFT;
413 IC.pushOperator(IC_LSHIFT);
414 break;
415 }
416 PrevState = CurrState;
417 }
418 void onRShift() {
419 IntelExprState CurrState = State;
420 switch (State) {
421 default:
422 State = IES_ERROR;
423 break;
424 case IES_INTEGER:
425 case IES_RPAREN:
426 case IES_REGISTER:
427 State = IES_RSHIFT;
428 IC.pushOperator(IC_RSHIFT);
429 break;
430 }
431 PrevState = CurrState;
432 }
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000433 bool onPlus(StringRef &ErrMsg) {
Chad Rosier31246272013-04-17 21:01:45 +0000434 IntelExprState CurrState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000435 switch (State) {
436 default:
437 State = IES_ERROR;
438 break;
439 case IES_INTEGER:
440 case IES_RPAREN:
Chad Rosier5362af92013-04-16 18:15:40 +0000441 case IES_REGISTER:
442 State = IES_PLUS;
Chad Rosier5362af92013-04-16 18:15:40 +0000443 IC.pushOperator(IC_PLUS);
Chad Rosier31246272013-04-17 21:01:45 +0000444 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
445 // If we already have a BaseReg, then assume this is the IndexReg with
446 // a scale of 1.
447 if (!BaseReg) {
448 BaseReg = TmpReg;
449 } else {
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000450 if (IndexReg) {
451 ErrMsg = "BaseReg/IndexReg already set!";
452 return true;
453 }
Chad Rosier31246272013-04-17 21:01:45 +0000454 IndexReg = TmpReg;
455 Scale = 1;
456 }
457 }
Chad Rosier5362af92013-04-16 18:15:40 +0000458 break;
459 }
Chad Rosier31246272013-04-17 21:01:45 +0000460 PrevState = CurrState;
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000461 return false;
Chad Rosier5362af92013-04-16 18:15:40 +0000462 }
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000463 bool onMinus(StringRef &ErrMsg) {
Chad Rosier31246272013-04-17 21:01:45 +0000464 IntelExprState CurrState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000465 switch (State) {
466 default:
467 State = IES_ERROR;
468 break;
Coby Tayree41a5b552017-06-27 16:58:27 +0000469 case IES_OR:
470 case IES_XOR:
471 case IES_AND:
472 case IES_LSHIFT:
473 case IES_RSHIFT:
Chad Rosier5362af92013-04-16 18:15:40 +0000474 case IES_PLUS:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000475 case IES_NOT:
Chad Rosier31246272013-04-17 21:01:45 +0000476 case IES_MULTIPLY:
477 case IES_DIVIDE:
Coby Tayree41a5b552017-06-27 16:58:27 +0000478 case IES_MOD:
Chad Rosier5362af92013-04-16 18:15:40 +0000479 case IES_LPAREN:
Chad Rosier5362af92013-04-16 18:15:40 +0000480 case IES_RPAREN:
Chad Rosier31246272013-04-17 21:01:45 +0000481 case IES_LBRAC:
482 case IES_RBRAC:
483 case IES_INTEGER:
Chad Rosier5362af92013-04-16 18:15:40 +0000484 case IES_REGISTER:
Coby Tayreed8912892017-08-24 08:46:25 +0000485 case IES_INIT:
Chad Rosier5362af92013-04-16 18:15:40 +0000486 State = IES_MINUS;
Coby Tayree41a5b552017-06-27 16:58:27 +0000487 // push minus operator if it is not a negate operator
488 if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
489 CurrState == IES_INTEGER || CurrState == IES_RBRAC)
Chad Rosier31246272013-04-17 21:01:45 +0000490 IC.pushOperator(IC_MINUS);
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000491 else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
492 // We have negate operator for Scale: it's illegal
493 ErrMsg = "Scale can't be negative";
494 return true;
495 } else
Coby Tayree41a5b552017-06-27 16:58:27 +0000496 IC.pushOperator(IC_NEG);
Chad Rosier31246272013-04-17 21:01:45 +0000497 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
498 // If we already have a BaseReg, then assume this is the IndexReg with
499 // a scale of 1.
500 if (!BaseReg) {
501 BaseReg = TmpReg;
502 } else {
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000503 if (IndexReg) {
504 ErrMsg = "BaseReg/IndexReg already set!";
505 return true;
506 }
Chad Rosier31246272013-04-17 21:01:45 +0000507 IndexReg = TmpReg;
508 Scale = 1;
509 }
Chad Rosier5362af92013-04-16 18:15:40 +0000510 }
Chad Rosier5362af92013-04-16 18:15:40 +0000511 break;
512 }
Chad Rosier31246272013-04-17 21:01:45 +0000513 PrevState = CurrState;
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000514 return false;
Chad Rosier5362af92013-04-16 18:15:40 +0000515 }
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000516 void onNot() {
517 IntelExprState CurrState = State;
518 switch (State) {
519 default:
520 State = IES_ERROR;
521 break;
Coby Tayree41a5b552017-06-27 16:58:27 +0000522 case IES_OR:
523 case IES_XOR:
524 case IES_AND:
525 case IES_LSHIFT:
526 case IES_RSHIFT:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000527 case IES_PLUS:
Coby Tayree41a5b552017-06-27 16:58:27 +0000528 case IES_MINUS:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000529 case IES_NOT:
Coby Tayree41a5b552017-06-27 16:58:27 +0000530 case IES_MULTIPLY:
531 case IES_DIVIDE:
532 case IES_MOD:
533 case IES_LPAREN:
534 case IES_LBRAC:
Coby Tayreed8912892017-08-24 08:46:25 +0000535 case IES_INIT:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000536 State = IES_NOT;
Coby Tayree41a5b552017-06-27 16:58:27 +0000537 IC.pushOperator(IC_NOT);
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000538 break;
539 }
540 PrevState = CurrState;
541 }
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000542
543 bool onRegister(unsigned Reg, StringRef &ErrMsg) {
Chad Rosier31246272013-04-17 21:01:45 +0000544 IntelExprState CurrState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000545 switch (State) {
546 default:
547 State = IES_ERROR;
548 break;
549 case IES_PLUS:
550 case IES_LPAREN:
Coby Tayreed8912892017-08-24 08:46:25 +0000551 case IES_LBRAC:
Chad Rosier5362af92013-04-16 18:15:40 +0000552 State = IES_REGISTER;
553 TmpReg = Reg;
554 IC.pushOperand(IC_REGISTER);
555 break;
Chad Rosier31246272013-04-17 21:01:45 +0000556 case IES_MULTIPLY:
557 // Index Register - Scale * Register
558 if (PrevState == IES_INTEGER) {
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000559 if (IndexReg) {
560 ErrMsg = "BaseReg/IndexReg already set!";
561 return true;
562 }
Chad Rosier31246272013-04-17 21:01:45 +0000563 State = IES_REGISTER;
564 IndexReg = Reg;
565 // Get the scale and replace the 'Scale * Register' with '0'.
566 Scale = IC.popOperand();
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000567 if (checkScale(Scale, ErrMsg))
568 return true;
Chad Rosier31246272013-04-17 21:01:45 +0000569 IC.pushOperand(IC_IMM);
570 IC.popOperator();
571 } else {
572 State = IES_ERROR;
573 }
Chad Rosier5362af92013-04-16 18:15:40 +0000574 break;
575 }
Chad Rosier31246272013-04-17 21:01:45 +0000576 PrevState = CurrState;
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000577 return false;
Chad Rosier5362af92013-04-16 18:15:40 +0000578 }
Coby Tayreed8912892017-08-24 08:46:25 +0000579 bool onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName,
Coby Tayreec3d24112017-09-29 07:02:46 +0000580 const InlineAsmIdentifierInfo &IDInfo,
581 bool ParsingInlineAsm, StringRef &ErrMsg) {
582 // InlineAsm: Treat an enum value as an integer
583 if (ParsingInlineAsm)
584 if (IDInfo.isKind(InlineAsmIdentifierInfo::IK_EnumVal))
585 return onInteger(IDInfo.Enum.EnumVal, ErrMsg);
586 // Treat a symbolic constant like an integer
587 if (auto *CE = dyn_cast<MCConstantExpr>(SymRef))
588 return onInteger(CE->getValue(), ErrMsg);
Chad Rosierdb003992013-04-18 16:28:19 +0000589 PrevState = State;
Coby Tayreed8912892017-08-24 08:46:25 +0000590 bool HasSymbol = Sym != nullptr;
Chad Rosier5362af92013-04-16 18:15:40 +0000591 switch (State) {
592 default:
593 State = IES_ERROR;
594 break;
595 case IES_PLUS:
596 case IES_MINUS:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000597 case IES_NOT:
Coby Tayreed8912892017-08-24 08:46:25 +0000598 case IES_INIT:
599 case IES_LBRAC:
Coby Tayreec3d24112017-09-29 07:02:46 +0000600 MemExpr = true;
Chad Rosier5362af92013-04-16 18:15:40 +0000601 State = IES_INTEGER;
602 Sym = SymRef;
603 SymName = SymRefName;
604 IC.pushOperand(IC_IMM);
Coby Tayreec3d24112017-09-29 07:02:46 +0000605 if (ParsingInlineAsm)
606 Info = IDInfo;
Chad Rosier5362af92013-04-16 18:15:40 +0000607 break;
608 }
Coby Tayreed8912892017-08-24 08:46:25 +0000609 if (HasSymbol)
610 ErrMsg = "cannot use more than one symbol in memory operand";
611 return HasSymbol;
Chad Rosier5362af92013-04-16 18:15:40 +0000612 }
Kevin Enderby9d117022014-01-23 21:52:41 +0000613 bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
Chad Rosier31246272013-04-17 21:01:45 +0000614 IntelExprState CurrState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000615 switch (State) {
616 default:
617 State = IES_ERROR;
618 break;
619 case IES_PLUS:
620 case IES_MINUS:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000621 case IES_NOT:
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000622 case IES_OR:
Michael Kupersteine3de07a2015-06-14 12:59:45 +0000623 case IES_XOR:
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000624 case IES_AND:
Kevin Enderbyd6b10712014-02-06 01:21:15 +0000625 case IES_LSHIFT:
626 case IES_RSHIFT:
Chad Rosier5362af92013-04-16 18:15:40 +0000627 case IES_DIVIDE:
Coby Tayree41a5b552017-06-27 16:58:27 +0000628 case IES_MOD:
Chad Rosier31246272013-04-17 21:01:45 +0000629 case IES_MULTIPLY:
Chad Rosier5362af92013-04-16 18:15:40 +0000630 case IES_LPAREN:
Coby Tayreed8912892017-08-24 08:46:25 +0000631 case IES_INIT:
632 case IES_LBRAC:
Chad Rosier5362af92013-04-16 18:15:40 +0000633 State = IES_INTEGER;
Chad Rosier31246272013-04-17 21:01:45 +0000634 if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
635 // Index Register - Register * Scale
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000636 if (IndexReg) {
637 ErrMsg = "BaseReg/IndexReg already set!";
Kevin Enderby9d117022014-01-23 21:52:41 +0000638 return true;
639 }
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000640 IndexReg = TmpReg;
641 Scale = TmpInt;
642 if (checkScale(Scale, ErrMsg))
643 return true;
Chad Rosier31246272013-04-17 21:01:45 +0000644 // Get the scale and replace the 'Register * Scale' with '0'.
645 IC.popOperator();
Chad Rosier31246272013-04-17 21:01:45 +0000646 } else {
647 IC.pushOperand(IC_IMM, TmpInt);
648 }
Chad Rosier5362af92013-04-16 18:15:40 +0000649 break;
650 }
Chad Rosier31246272013-04-17 21:01:45 +0000651 PrevState = CurrState;
Kevin Enderby9d117022014-01-23 21:52:41 +0000652 return false;
Chad Rosier5362af92013-04-16 18:15:40 +0000653 }
654 void onStar() {
Chad Rosierdb003992013-04-18 16:28:19 +0000655 PrevState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000656 switch (State) {
657 default:
658 State = IES_ERROR;
659 break;
660 case IES_INTEGER:
Chad Rosier5362af92013-04-16 18:15:40 +0000661 case IES_REGISTER:
Chad Rosier5362af92013-04-16 18:15:40 +0000662 case IES_RPAREN:
663 State = IES_MULTIPLY;
664 IC.pushOperator(IC_MULTIPLY);
665 break;
666 }
667 }
668 void onDivide() {
Chad Rosierdb003992013-04-18 16:28:19 +0000669 PrevState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000670 switch (State) {
671 default:
672 State = IES_ERROR;
673 break;
674 case IES_INTEGER:
Chad Rosier31246272013-04-17 21:01:45 +0000675 case IES_RPAREN:
Chad Rosier5362af92013-04-16 18:15:40 +0000676 State = IES_DIVIDE;
677 IC.pushOperator(IC_DIVIDE);
678 break;
679 }
680 }
Coby Tayree41a5b552017-06-27 16:58:27 +0000681 void onMod() {
682 PrevState = State;
683 switch (State) {
684 default:
685 State = IES_ERROR;
686 break;
687 case IES_INTEGER:
688 case IES_RPAREN:
689 State = IES_MOD;
690 IC.pushOperator(IC_MOD);
691 break;
692 }
693 }
Coby Tayreed8912892017-08-24 08:46:25 +0000694 bool onLBrac() {
695 if (BracCount)
696 return true;
Chad Rosierdb003992013-04-18 16:28:19 +0000697 PrevState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000698 switch (State) {
699 default:
700 State = IES_ERROR;
701 break;
702 case IES_RBRAC:
Coby Tayreed8912892017-08-24 08:46:25 +0000703 case IES_INTEGER:
704 case IES_RPAREN:
Chad Rosier5362af92013-04-16 18:15:40 +0000705 State = IES_PLUS;
706 IC.pushOperator(IC_PLUS);
707 break;
Coby Tayreed8912892017-08-24 08:46:25 +0000708 case IES_INIT:
709 assert(!BracCount && "BracCount should be zero on parsing's start");
710 State = IES_LBRAC;
711 break;
Chad Rosier5362af92013-04-16 18:15:40 +0000712 }
Coby Tayreed8912892017-08-24 08:46:25 +0000713 MemExpr = true;
714 BracCount++;
715 return false;
Chad Rosier5362af92013-04-16 18:15:40 +0000716 }
Coby Tayreed8912892017-08-24 08:46:25 +0000717 bool onRBrac() {
Chad Rosier31246272013-04-17 21:01:45 +0000718 IntelExprState CurrState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000719 switch (State) {
720 default:
721 State = IES_ERROR;
722 break;
Chad Rosier5362af92013-04-16 18:15:40 +0000723 case IES_INTEGER:
Chad Rosier5362af92013-04-16 18:15:40 +0000724 case IES_REGISTER:
Chad Rosier31246272013-04-17 21:01:45 +0000725 case IES_RPAREN:
Coby Tayreed8912892017-08-24 08:46:25 +0000726 if (BracCount-- != 1)
727 return true;
Chad Rosier5362af92013-04-16 18:15:40 +0000728 State = IES_RBRAC;
Chad Rosier31246272013-04-17 21:01:45 +0000729 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
730 // If we already have a BaseReg, then assume this is the IndexReg with
731 // a scale of 1.
732 if (!BaseReg) {
733 BaseReg = TmpReg;
734 } else {
735 assert (!IndexReg && "BaseReg/IndexReg already set!");
736 IndexReg = TmpReg;
737 Scale = 1;
738 }
Chad Rosier5362af92013-04-16 18:15:40 +0000739 }
740 break;
741 }
Chad Rosier31246272013-04-17 21:01:45 +0000742 PrevState = CurrState;
Coby Tayreed8912892017-08-24 08:46:25 +0000743 return false;
Chad Rosier5362af92013-04-16 18:15:40 +0000744 }
745 void onLParen() {
Chad Rosier31246272013-04-17 21:01:45 +0000746 IntelExprState CurrState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000747 switch (State) {
748 default:
749 State = IES_ERROR;
750 break;
751 case IES_PLUS:
752 case IES_MINUS:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000753 case IES_NOT:
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000754 case IES_OR:
Michael Kupersteine3de07a2015-06-14 12:59:45 +0000755 case IES_XOR:
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000756 case IES_AND:
Kevin Enderbyd6b10712014-02-06 01:21:15 +0000757 case IES_LSHIFT:
758 case IES_RSHIFT:
Chad Rosier5362af92013-04-16 18:15:40 +0000759 case IES_MULTIPLY:
760 case IES_DIVIDE:
Coby Tayree41a5b552017-06-27 16:58:27 +0000761 case IES_MOD:
Chad Rosier5362af92013-04-16 18:15:40 +0000762 case IES_LPAREN:
Coby Tayreed8912892017-08-24 08:46:25 +0000763 case IES_INIT:
764 case IES_LBRAC:
Chad Rosier5362af92013-04-16 18:15:40 +0000765 State = IES_LPAREN;
766 IC.pushOperator(IC_LPAREN);
767 break;
768 }
Chad Rosier31246272013-04-17 21:01:45 +0000769 PrevState = CurrState;
Chad Rosier5362af92013-04-16 18:15:40 +0000770 }
771 void onRParen() {
Chad Rosierdb003992013-04-18 16:28:19 +0000772 PrevState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000773 switch (State) {
774 default:
775 State = IES_ERROR;
776 break;
Chad Rosier5362af92013-04-16 18:15:40 +0000777 case IES_INTEGER:
Chad Rosier31246272013-04-17 21:01:45 +0000778 case IES_REGISTER:
Chad Rosier5362af92013-04-16 18:15:40 +0000779 case IES_RPAREN:
780 State = IES_RPAREN;
781 IC.pushOperator(IC_RPAREN);
782 break;
783 }
784 }
785 };
786
Nirav Dave2364748a2016-09-16 18:30:20 +0000787 bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
Chad Rosier4453e842012-10-12 23:09:25 +0000788 bool MatchingInlineAsm = false) {
Rafael Espindola961d4692014-11-11 05:18:41 +0000789 MCAsmParser &Parser = getParser();
Nirav Dave2364748a2016-09-16 18:30:20 +0000790 if (MatchingInlineAsm) {
791 if (!getLexer().isAtStartOfStatement())
792 Parser.eatToEndOfStatement();
793 return false;
794 }
795 return Parser.Error(L, Msg, Range);
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000796 }
797
David Blaikie960ea3f2014-06-08 16:18:35 +0000798 std::nullptr_t ErrorOperand(SMLoc Loc, StringRef Msg) {
Devang Patel41b9dde2012-01-17 18:00:18 +0000799 Error(Loc, Msg);
Craig Topper062a2ba2014-04-25 05:30:21 +0000800 return nullptr;
Devang Patel41b9dde2012-01-17 18:00:18 +0000801 }
802
David Blaikie960ea3f2014-06-08 16:18:35 +0000803 std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
804 std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);
Marina Yatsinab9f4f622016-01-19 15:37:56 +0000805 bool IsSIReg(unsigned Reg);
806 unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
807 void
808 AddDefaultSrcDestOperands(OperandVector &Operands,
809 std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
810 std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
811 bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
812 OperandVector &FinalOperands);
David Blaikie960ea3f2014-06-08 16:18:35 +0000813 std::unique_ptr<X86Operand> ParseOperand();
814 std::unique_ptr<X86Operand> ParseATTOperand();
815 std::unique_ptr<X86Operand> ParseIntelOperand();
816 std::unique_ptr<X86Operand> ParseIntelOffsetOfOperator();
Coby Tayreed8912892017-08-24 08:46:25 +0000817 bool ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End);
818 unsigned IdentifyIntelInlineAsmOperator(StringRef Name);
819 unsigned ParseIntelInlineAsmOperator(unsigned OpKind);
Elena Demikhovsky18fd4962015-03-02 15:00:34 +0000820 std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start, SMLoc End);
Coby Tayree2cb497a2017-04-04 14:43:23 +0000821 bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM);
Coby Tayreed8912892017-08-24 08:46:25 +0000822 void RewriteIntelExpression(IntelExprStateMachine &SM, SMLoc Start,
823 SMLoc End);
Benjamin Kramer951b15e2013-12-01 11:47:42 +0000824 bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
Coby Tayreed8912892017-08-24 08:46:25 +0000825 bool ParseIntelInlineAsmIdentifier(const MCExpr *&Val, StringRef &Identifier,
826 InlineAsmIdentifierInfo &Info,
827 bool IsUnevaluatedOperand, SMLoc &End);
Chad Rosiercb78f0d2013-04-22 19:42:15 +0000828
David Blaikie960ea3f2014-06-08 16:18:35 +0000829 std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
Kevin Enderbyce4bec82009-09-10 20:51:44 +0000830
Coby Tayreed8912892017-08-24 08:46:25 +0000831 bool ParseIntelMemoryOperandSize(unsigned &Size);
David Blaikie960ea3f2014-06-08 16:18:35 +0000832 std::unique_ptr<X86Operand>
833 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
834 unsigned IndexReg, unsigned Scale, SMLoc Start,
835 SMLoc End, unsigned Size, StringRef Identifier,
Coby Tayreeef66b3b2017-09-10 12:21:24 +0000836 const InlineAsmIdentifierInfo &Info);
Chad Rosier7ca135b2013-03-19 21:11:56 +0000837
Michael Zuckerman02ecd432015-12-13 17:07:23 +0000838 bool parseDirectiveEven(SMLoc L);
Kevin Enderbyce4bec82009-09-10 20:51:44 +0000839 bool ParseDirectiveWord(unsigned Size, SMLoc L);
Evan Cheng481ebb02011-07-27 00:38:12 +0000840 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
Kevin Enderbyce4bec82009-09-10 20:51:44 +0000841
David Blaikie960ea3f2014-06-08 16:18:35 +0000842 bool processInstruction(MCInst &Inst, const OperandVector &Ops);
Devang Patelde47cce2012-01-18 22:42:29 +0000843
Evgeniy Stepanov49e26252014-03-14 08:58:04 +0000844 /// Wrapper around MCStreamer::EmitInstruction(). Possibly adds
845 /// instrumentation around Inst.
David Blaikie960ea3f2014-06-08 16:18:35 +0000846 void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
Evgeniy Stepanov49e26252014-03-14 08:58:04 +0000847
Chad Rosier49963552012-10-13 00:26:04 +0000848 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
David Blaikie960ea3f2014-06-08 16:18:35 +0000849 OperandVector &Operands, MCStreamer &Out,
Tim Northover26bb14e2014-08-18 11:49:42 +0000850 uint64_t &ErrorInfo,
Craig Topper39012cc2014-03-09 18:03:14 +0000851 bool MatchingInlineAsm) override;
Chad Rosier9cb988f2012-08-09 22:04:55 +0000852
Reid Klecknerf6fb7802014-08-26 20:32:34 +0000853 void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
854 MCStreamer &Out, bool MatchingInlineAsm);
855
Ranjeet Singh86ecbb72015-06-30 12:32:53 +0000856 bool ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo,
Reid Klecknerf6fb7802014-08-26 20:32:34 +0000857 bool MatchingInlineAsm);
858
859 bool MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
860 OperandVector &Operands, MCStreamer &Out,
861 uint64_t &ErrorInfo,
862 bool MatchingInlineAsm);
863
864 bool MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
865 OperandVector &Operands, MCStreamer &Out,
866 uint64_t &ErrorInfo,
867 bool MatchingInlineAsm);
868
Craig Topperfd38cbe2014-08-30 16:48:34 +0000869 bool OmitRegisterFromClobberLists(unsigned RegNo) override;
Nico Weber42f79db2014-07-17 20:24:55 +0000870
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000871 /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
872 /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
Michael Zuckerman1bee6342016-10-18 13:52:39 +0000873 /// return false if no parsing errors occurred, true otherwise.
David Blaikie960ea3f2014-06-08 16:18:35 +0000874 bool HandleAVX512Operand(OperandVector &Operands,
875 const MCParsedAsmOperand &Op);
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000876
Michael Zuckerman1bee6342016-10-18 13:52:39 +0000877 bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
878
Evan Chengc5e6d2f2011-07-11 03:57:24 +0000879 bool is64BitMode() const {
Evan Cheng4d1ca962011-07-08 01:53:10 +0000880 // FIXME: Can tablegen auto-generate this?
Akira Hatanakabd9fc282015-11-14 05:20:05 +0000881 return getSTI().getFeatureBits()[X86::Mode64Bit];
Evan Cheng4d1ca962011-07-08 01:53:10 +0000882 }
Craig Topper3c80d622014-01-06 04:55:54 +0000883 bool is32BitMode() const {
884 // FIXME: Can tablegen auto-generate this?
Akira Hatanakabd9fc282015-11-14 05:20:05 +0000885 return getSTI().getFeatureBits()[X86::Mode32Bit];
Craig Topper3c80d622014-01-06 04:55:54 +0000886 }
887 bool is16BitMode() const {
888 // FIXME: Can tablegen auto-generate this?
Akira Hatanakabd9fc282015-11-14 05:20:05 +0000889 return getSTI().getFeatureBits()[X86::Mode16Bit];
Craig Topper3c80d622014-01-06 04:55:54 +0000890 }
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000891 void SwitchMode(unsigned mode) {
Akira Hatanakab11ef082015-11-14 06:35:56 +0000892 MCSubtargetInfo &STI = copySTI();
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000893 FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
894 FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
Ranjeet Singh86ecbb72015-06-30 12:32:53 +0000895 unsigned FB = ComputeAvailableFeatures(
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000896 STI.ToggleFeature(OldMode.flip(mode)));
Evan Cheng481ebb02011-07-27 00:38:12 +0000897 setAvailableFeatures(FB);
NAKAMURA Takumia9cb5382015-09-22 11:14:39 +0000898
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000899 assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
Evan Cheng481ebb02011-07-27 00:38:12 +0000900 }
Evan Cheng4d1ca962011-07-08 01:53:10 +0000901
Reid Kleckner5b37c182014-08-01 20:21:24 +0000902 unsigned getPointerWidth() {
903 if (is16BitMode()) return 16;
904 if (is32BitMode()) return 32;
905 if (is64BitMode()) return 64;
906 llvm_unreachable("invalid mode");
907 }
908
Chad Rosierc2f055d2013-04-18 16:13:18 +0000909 bool isParsingIntelSyntax() {
910 return getParser().getAssemblerDialect();
911 }
912
Daniel Dunbareefe8612010-07-19 05:44:09 +0000913 /// @name Auto-generated Matcher Functions
914 /// {
Michael J. Spencer530ce852010-10-09 11:00:50 +0000915
Chris Lattner3e4582a2010-09-06 19:11:01 +0000916#define GET_ASSEMBLER_HEADER
917#include "X86GenAsmMatcher.inc"
Michael J. Spencer530ce852010-10-09 11:00:50 +0000918
Daniel Dunbar00331992009-07-29 00:02:19 +0000919 /// }
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +0000920
921public:
Coby Tayree07a89742017-03-21 19:31:55 +0000922
Akira Hatanakab11ef082015-11-14 06:35:56 +0000923 X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
Rafael Espindola961d4692014-11-11 05:18:41 +0000924 const MCInstrInfo &mii, const MCTargetOptions &Options)
Oliver Stannard4191b9e2017-10-11 09:17:43 +0000925 : MCTargetAsmParser(Options, sti, mii), InstInfo(nullptr),
Nirav Dave6477ce22016-09-26 19:33:36 +0000926 Code16GCC(false) {
Michael J. Spencer530ce852010-10-09 11:00:50 +0000927
Daniel Dunbareefe8612010-07-19 05:44:09 +0000928 // Initialize the set of available features.
Akira Hatanakabd9fc282015-11-14 05:20:05 +0000929 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
Evgeniy Stepanov0a951b72014-04-23 11:16:03 +0000930 Instrumentation.reset(
931 CreateX86AsmInstrumentation(Options, Parser.getContext(), STI));
Daniel Dunbareefe8612010-07-19 05:44:09 +0000932 }
Evgeniy Stepanov0a951b72014-04-23 11:16:03 +0000933
Craig Topper39012cc2014-03-09 18:03:14 +0000934 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +0000935
Yuri Gorshenin3939dec2014-09-10 09:45:49 +0000936 void SetFrameRegister(unsigned RegNo) override;
937
David Blaikie960ea3f2014-06-08 16:18:35 +0000938 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
939 SMLoc NameLoc, OperandVector &Operands) override;
Kevin Enderbyce4bec82009-09-10 20:51:44 +0000940
Craig Topper39012cc2014-03-09 18:03:14 +0000941 bool ParseDirective(AsmToken DirectiveID) override;
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +0000942};
Chris Lattner4eb9df02009-07-29 06:33:53 +0000943} // end anonymous namespace
944
Sean Callanan86c11812010-01-23 00:40:33 +0000945/// @name Auto-generated Match Functions
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +0000946/// {
Sean Callanan86c11812010-01-23 00:40:33 +0000947
Chris Lattner60db0a62010-02-09 00:34:28 +0000948static unsigned MatchRegisterName(StringRef Name);
Sean Callanan86c11812010-01-23 00:40:33 +0000949
950/// }
Chris Lattner4eb9df02009-07-29 06:33:53 +0000951
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000952static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
953 unsigned Scale, StringRef &ErrMsg) {
Kevin Enderbybc570f22014-01-23 22:34:42 +0000954 // If we have both a base register and an index register make sure they are
955 // both 64-bit or 32-bit registers.
956 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
Douglas Katzman0411e862016-10-05 15:23:35 +0000957
958 if ((BaseReg == X86::RIP && IndexReg != 0) || (IndexReg == X86::RIP)) {
959 ErrMsg = "invalid base+index expression";
960 return true;
961 }
Kevin Enderbybc570f22014-01-23 22:34:42 +0000962 if (BaseReg != 0 && IndexReg != 0) {
963 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
964 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
965 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
966 IndexReg != X86::RIZ) {
967 ErrMsg = "base register is 64-bit, but index register is not";
968 return true;
969 }
970 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
971 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
972 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
973 IndexReg != X86::EIZ){
974 ErrMsg = "base register is 32-bit, but index register is not";
975 return true;
976 }
977 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
978 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
979 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
980 ErrMsg = "base register is 16-bit, but index register is not";
981 return true;
982 }
983 if (((BaseReg == X86::BX || BaseReg == X86::BP) &&
984 IndexReg != X86::SI && IndexReg != X86::DI) ||
985 ((BaseReg == X86::SI || BaseReg == X86::DI) &&
986 IndexReg != X86::BX && IndexReg != X86::BP)) {
987 ErrMsg = "invalid 16-bit base/index register combination";
988 return true;
989 }
990 }
991 }
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000992 return checkScale(Scale, ErrMsg);
Kevin Enderbybc570f22014-01-23 22:34:42 +0000993}
994
Devang Patel4a6e7782012-01-12 18:03:40 +0000995bool X86AsmParser::ParseRegister(unsigned &RegNo,
996 SMLoc &StartLoc, SMLoc &EndLoc) {
Rafael Espindola961d4692014-11-11 05:18:41 +0000997 MCAsmParser &Parser = getParser();
Chris Lattnercc2ad082010-01-15 18:27:19 +0000998 RegNo = 0;
Benjamin Kramere3d658b2012-09-07 14:51:35 +0000999 const AsmToken &PercentTok = Parser.getTok();
1000 StartLoc = PercentTok.getLoc();
1001
1002 // If we encounter a %, ignore it. This code handles registers with and
1003 // without the prefix, unprefixed registers can occur in cfi directives.
1004 if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
Devang Patel41b9dde2012-01-17 18:00:18 +00001005 Parser.Lex(); // Eat percent token.
Kevin Enderby7d912182009-09-03 17:15:07 +00001006
Sean Callanan936b0d32010-01-19 21:44:56 +00001007 const AsmToken &Tok = Parser.getTok();
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001008 EndLoc = Tok.getEndLoc();
1009
Devang Patelce6a2ca2012-01-20 22:32:05 +00001010 if (Tok.isNot(AsmToken::Identifier)) {
Reid Klecknerc990b5d2017-07-24 20:48:15 +00001011 if (isParsingIntelSyntax()) return true;
Benjamin Kramer1930b002011-10-16 12:10:27 +00001012 return Error(StartLoc, "invalid register name",
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001013 SMRange(StartLoc, EndLoc));
Devang Patelce6a2ca2012-01-20 22:32:05 +00001014 }
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00001015
Kevin Enderby7d912182009-09-03 17:15:07 +00001016 RegNo = MatchRegisterName(Tok.getString());
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001017
Chris Lattner1261b812010-09-22 04:11:10 +00001018 // If the match failed, try the register name as lowercase.
1019 if (RegNo == 0)
Benjamin Kramer20baffb2011-11-06 20:37:06 +00001020 RegNo = MatchRegisterName(Tok.getString().lower());
Michael J. Spencer530ce852010-10-09 11:00:50 +00001021
Michael Kupersteincdb076b2015-07-30 10:10:25 +00001022 // The "flags" register cannot be referenced directly.
1023 // Treat it as an identifier instead.
1024 if (isParsingInlineAsm() && isParsingIntelSyntax() && RegNo == X86::EFLAGS)
1025 RegNo = 0;
1026
Evan Chengeda1d4f2011-07-27 23:22:03 +00001027 if (!is64BitMode()) {
Eric Christopherc0a5aae2013-12-20 02:04:49 +00001028 // FIXME: This should be done using Requires<Not64BitMode> and
Evan Chengeda1d4f2011-07-27 23:22:03 +00001029 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
1030 // checked.
1031 // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
1032 // REX prefix.
1033 if (RegNo == X86::RIZ ||
1034 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
1035 X86II::isX86_64NonExtLowByteReg(RegNo) ||
Craig Topper6acca802016-08-27 17:13:37 +00001036 X86II::isX86_64ExtendedReg(RegNo))
Benjamin Kramer1930b002011-10-16 12:10:27 +00001037 return Error(StartLoc, "register %"
1038 + Tok.getString() + " is only available in 64-bit mode",
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001039 SMRange(StartLoc, EndLoc));
Craig Topper29c22732016-02-26 05:29:32 +00001040 } else if (!getSTI().getFeatureBits()[X86::FeatureAVX512]) {
1041 if (X86II::is32ExtendedReg(RegNo))
1042 return Error(StartLoc, "register %"
Craig Topperd50b5f82016-02-26 06:50:24 +00001043 + Tok.getString() + " is only available with AVX512",
Craig Topper29c22732016-02-26 05:29:32 +00001044 SMRange(StartLoc, EndLoc));
Evan Chengeda1d4f2011-07-27 23:22:03 +00001045 }
Bruno Cardoso Lopes306a1f92010-07-24 00:06:39 +00001046
Chris Lattner1261b812010-09-22 04:11:10 +00001047 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1048 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
Chris Lattnerd00faaa2010-02-09 00:49:22 +00001049 RegNo = X86::ST0;
Chris Lattnerd00faaa2010-02-09 00:49:22 +00001050 Parser.Lex(); // Eat 'st'
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001051
Chris Lattnerd00faaa2010-02-09 00:49:22 +00001052 // Check to see if we have '(4)' after %st.
1053 if (getLexer().isNot(AsmToken::LParen))
1054 return false;
1055 // Lex the paren.
1056 getParser().Lex();
1057
1058 const AsmToken &IntTok = Parser.getTok();
1059 if (IntTok.isNot(AsmToken::Integer))
1060 return Error(IntTok.getLoc(), "expected stack index");
1061 switch (IntTok.getIntVal()) {
1062 case 0: RegNo = X86::ST0; break;
1063 case 1: RegNo = X86::ST1; break;
1064 case 2: RegNo = X86::ST2; break;
1065 case 3: RegNo = X86::ST3; break;
1066 case 4: RegNo = X86::ST4; break;
1067 case 5: RegNo = X86::ST5; break;
1068 case 6: RegNo = X86::ST6; break;
1069 case 7: RegNo = X86::ST7; break;
1070 default: return Error(IntTok.getLoc(), "invalid stack index");
1071 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001072
Chris Lattnerd00faaa2010-02-09 00:49:22 +00001073 if (getParser().Lex().isNot(AsmToken::RParen))
1074 return Error(Parser.getTok().getLoc(), "expected ')'");
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001075
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001076 EndLoc = Parser.getTok().getEndLoc();
Chris Lattnerd00faaa2010-02-09 00:49:22 +00001077 Parser.Lex(); // Eat ')'
1078 return false;
1079 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001080
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001081 EndLoc = Parser.getTok().getEndLoc();
1082
Chris Lattner80486622010-06-24 07:29:18 +00001083 // If this is "db[0-7]", match it as an alias
1084 // for dr[0-7].
1085 if (RegNo == 0 && Tok.getString().size() == 3 &&
1086 Tok.getString().startswith("db")) {
1087 switch (Tok.getString()[2]) {
1088 case '0': RegNo = X86::DR0; break;
1089 case '1': RegNo = X86::DR1; break;
1090 case '2': RegNo = X86::DR2; break;
1091 case '3': RegNo = X86::DR3; break;
1092 case '4': RegNo = X86::DR4; break;
1093 case '5': RegNo = X86::DR5; break;
1094 case '6': RegNo = X86::DR6; break;
1095 case '7': RegNo = X86::DR7; break;
1096 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001097
Chris Lattner80486622010-06-24 07:29:18 +00001098 if (RegNo != 0) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001099 EndLoc = Parser.getTok().getEndLoc();
Chris Lattner80486622010-06-24 07:29:18 +00001100 Parser.Lex(); // Eat it.
1101 return false;
1102 }
1103 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001104
Devang Patelce6a2ca2012-01-20 22:32:05 +00001105 if (RegNo == 0) {
Devang Patel9a9bb5c2012-01-30 20:02:42 +00001106 if (isParsingIntelSyntax()) return true;
Benjamin Kramer1930b002011-10-16 12:10:27 +00001107 return Error(StartLoc, "invalid register name",
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001108 SMRange(StartLoc, EndLoc));
Devang Patelce6a2ca2012-01-20 22:32:05 +00001109 }
Daniel Dunbar00331992009-07-29 00:02:19 +00001110
Sean Callanana83fd7d2010-01-19 20:27:46 +00001111 Parser.Lex(); // Eat identifier token.
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00001112 return false;
Daniel Dunbar71475772009-07-17 20:42:00 +00001113}
1114
Yuri Gorshenin3939dec2014-09-10 09:45:49 +00001115void X86AsmParser::SetFrameRegister(unsigned RegNo) {
Yuri Gorshenine8c81fd2014-10-07 11:03:09 +00001116 Instrumentation->SetInitialFrameRegister(RegNo);
Yuri Gorshenin3939dec2014-09-10 09:45:49 +00001117}
1118
David Blaikie960ea3f2014-06-08 16:18:35 +00001119std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
Nirav Dave6477ce22016-09-26 19:33:36 +00001120 bool Parse32 = is32BitMode() || Code16GCC;
1121 unsigned Basereg = is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI);
Jim Grosbach13760bd2015-05-30 01:25:56 +00001122 const MCExpr *Disp = MCConstantExpr::create(0, getContext());
Craig Topper055845f2015-01-02 07:02:25 +00001123 return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
Nirav Dave6477ce22016-09-26 19:33:36 +00001124 /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
Craig Topper055845f2015-01-02 07:02:25 +00001125 Loc, Loc, 0);
David Woodhouse2ef8d9c2014-01-22 15:08:08 +00001126}
1127
David Blaikie960ea3f2014-06-08 16:18:35 +00001128std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
Nirav Dave6477ce22016-09-26 19:33:36 +00001129 bool Parse32 = is32BitMode() || Code16GCC;
1130 unsigned Basereg = is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
Jim Grosbach13760bd2015-05-30 01:25:56 +00001131 const MCExpr *Disp = MCConstantExpr::create(0, getContext());
Craig Topper055845f2015-01-02 07:02:25 +00001132 return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
Nirav Dave6477ce22016-09-26 19:33:36 +00001133 /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
Craig Topper055845f2015-01-02 07:02:25 +00001134 Loc, Loc, 0);
David Woodhouseb33c2ef2014-01-22 15:08:21 +00001135}
1136
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001137bool X86AsmParser::IsSIReg(unsigned Reg) {
1138 switch (Reg) {
Craig Topper4d187632016-02-26 05:29:39 +00001139 default: llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001140 case X86::RSI:
1141 case X86::ESI:
1142 case X86::SI:
1143 return true;
1144 case X86::RDI:
1145 case X86::EDI:
1146 case X86::DI:
1147 return false;
1148 }
1149}
1150
1151unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
1152 bool IsSIReg) {
1153 switch (RegClassID) {
Craig Topper4d187632016-02-26 05:29:39 +00001154 default: llvm_unreachable("Unexpected register class");
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001155 case X86::GR64RegClassID:
1156 return IsSIReg ? X86::RSI : X86::RDI;
1157 case X86::GR32RegClassID:
1158 return IsSIReg ? X86::ESI : X86::EDI;
1159 case X86::GR16RegClassID:
1160 return IsSIReg ? X86::SI : X86::DI;
1161 }
1162}
1163
Michael Kupersteinffcc7662015-07-23 10:23:48 +00001164void X86AsmParser::AddDefaultSrcDestOperands(
1165 OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1166 std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {
1167 if (isParsingIntelSyntax()) {
1168 Operands.push_back(std::move(Dst));
1169 Operands.push_back(std::move(Src));
1170 }
1171 else {
1172 Operands.push_back(std::move(Src));
1173 Operands.push_back(std::move(Dst));
1174 }
1175}
1176
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001177bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
1178 OperandVector &FinalOperands) {
1179
1180 if (OrigOperands.size() > 1) {
Craig Topperd55f4bc2016-02-16 07:45:07 +00001181 // Check if sizes match, OrigOperands also contains the instruction name
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001182 assert(OrigOperands.size() == FinalOperands.size() + 1 &&
Craig Topperd55f4bc2016-02-16 07:45:07 +00001183 "Operand size mismatch");
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001184
Marina Yatsinaff262fa2016-01-21 11:37:06 +00001185 SmallVector<std::pair<SMLoc, std::string>, 2> Warnings;
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001186 // Verify types match
1187 int RegClassID = -1;
1188 for (unsigned int i = 0; i < FinalOperands.size(); ++i) {
1189 X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]);
1190 X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]);
1191
1192 if (FinalOp.isReg() &&
1193 (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg()))
1194 // Return false and let a normal complaint about bogus operands happen
1195 return false;
1196
1197 if (FinalOp.isMem()) {
1198
1199 if (!OrigOp.isMem())
1200 // Return false and let a normal complaint about bogus operands happen
1201 return false;
1202
1203 unsigned OrigReg = OrigOp.Mem.BaseReg;
1204 unsigned FinalReg = FinalOp.Mem.BaseReg;
1205
1206 // If we've already encounterd a register class, make sure all register
1207 // bases are of the same register class
1208 if (RegClassID != -1 &&
1209 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
1210 return Error(OrigOp.getStartLoc(),
1211 "mismatching source and destination index registers");
1212 }
1213
1214 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg))
1215 RegClassID = X86::GR64RegClassID;
1216 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg))
1217 RegClassID = X86::GR32RegClassID;
1218 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
1219 RegClassID = X86::GR16RegClassID;
Marina Yatsina701938d2016-01-20 14:03:47 +00001220 else
Craig Topper5a62f7e2016-02-16 07:28:03 +00001221 // Unexpected register class type
Marina Yatsina701938d2016-01-20 14:03:47 +00001222 // Return false and let a normal complaint about bogus operands happen
1223 return false;
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001224
1225 bool IsSI = IsSIReg(FinalReg);
1226 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI);
1227
1228 if (FinalReg != OrigReg) {
1229 std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI";
Marina Yatsinaff262fa2016-01-21 11:37:06 +00001230 Warnings.push_back(std::make_pair(
1231 OrigOp.getStartLoc(),
1232 "memory operand is only for determining the size, " + RegName +
1233 " will be used for the location"));
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001234 }
1235
1236 FinalOp.Mem.Size = OrigOp.Mem.Size;
1237 FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
1238 FinalOp.Mem.BaseReg = FinalReg;
1239 }
1240 }
1241
Marina Yatsinaff262fa2016-01-21 11:37:06 +00001242 // Produce warnings only if all the operands passed the adjustment - prevent
1243 // legal cases like "movsd (%rax), %xmm0" mistakenly produce warnings
Craig Topper16d7eb22016-02-16 07:45:04 +00001244 for (auto &WarningMsg : Warnings) {
1245 Warning(WarningMsg.first, WarningMsg.second);
Marina Yatsinaff262fa2016-01-21 11:37:06 +00001246 }
1247
1248 // Remove old operands
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001249 for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1250 OrigOperands.pop_back();
1251 }
1252 // OrigOperands.append(FinalOperands.begin(), FinalOperands.end());
1253 for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1254 OrigOperands.push_back(std::move(FinalOperands[i]));
1255
1256 return false;
1257}
1258
David Blaikie960ea3f2014-06-08 16:18:35 +00001259std::unique_ptr<X86Operand> X86AsmParser::ParseOperand() {
Devang Patel9a9bb5c2012-01-30 20:02:42 +00001260 if (isParsingIntelSyntax())
Devang Patel46831de2012-01-12 01:36:43 +00001261 return ParseIntelOperand();
1262 return ParseATTOperand();
1263}
1264
David Blaikie960ea3f2014-06-08 16:18:35 +00001265std::unique_ptr<X86Operand> X86AsmParser::CreateMemForInlineAsm(
1266 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1267 unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier,
Coby Tayreeef66b3b2017-09-10 12:21:24 +00001268 const InlineAsmIdentifierInfo &Info) {
Reid Kleckner5b37c182014-08-01 20:21:24 +00001269 // If we found a decl other than a VarDecl, then assume it is a FuncDecl or
1270 // some other label reference.
Coby Tayreec3d24112017-09-29 07:02:46 +00001271 if (Info.isKind(InlineAsmIdentifierInfo::IK_Label)) {
Reid Kleckner5b37c182014-08-01 20:21:24 +00001272 // Insert an explicit size if the user didn't have one.
1273 if (!Size) {
1274 Size = getPointerWidth();
Craig Topper7d5b2312015-10-10 05:25:02 +00001275 InstInfo->AsmRewrites->emplace_back(AOK_SizeDirective, Start,
1276 /*Len=*/0, Size);
Reid Kleckner5b37c182014-08-01 20:21:24 +00001277 }
Reid Kleckner5b37c182014-08-01 20:21:24 +00001278 // Create an absolute memory reference in order to match against
1279 // instructions taking a PC relative operand.
Craig Topper055845f2015-01-02 07:02:25 +00001280 return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size,
Coby Tayreec3d24112017-09-29 07:02:46 +00001281 Identifier, Info.Label.Decl);
Reid Klecknerd84e70e2014-03-04 00:33:17 +00001282 }
Reid Klecknerd84e70e2014-03-04 00:33:17 +00001283 // We either have a direct symbol reference, or an offset from a symbol. The
1284 // parser always puts the symbol on the LHS, so look there for size
1285 // calculation purposes.
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00001286 unsigned FrontendSize = 0;
Coby Tayreec3d24112017-09-29 07:02:46 +00001287 void *Decl = nullptr;
1288 bool IsGlobalLV = false;
1289 if (Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
1290 // Size is in terms of bits in this context.
1291 FrontendSize = Info.Var.Type * 8;
1292 Decl = Info.Var.Decl;
1293 IsGlobalLV = Info.Var.IsGlobalLV;
1294 }
1295 // It is widely common for MS InlineAsm to use a global variable and one/two
1296 // registers in a mmory expression, and though unaccessible via rip/eip.
1297 if (IsGlobalLV && (BaseReg || IndexReg)) {
1298 return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End);
1299 // Otherwise, we set the base register to a non-zero value
Chad Rosier175d0ae2013-04-12 18:21:18 +00001300 // if we don't know the actual value at this time. This is necessary to
Chad Rosier7ca135b2013-03-19 21:11:56 +00001301 // get the matching correct in some cases.
Coby Tayreec3d24112017-09-29 07:02:46 +00001302 } else {
1303 BaseReg = BaseReg ? BaseReg : 1;
1304 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
1305 IndexReg, Scale, Start, End, Size, Identifier,
1306 Decl, FrontendSize);
1307 }
Chad Rosier7ca135b2013-03-19 21:11:56 +00001308}
1309
Coby Tayree2cb497a2017-04-04 14:43:23 +00001310// Some binary bitwise operators have a named synonymous
1311// Query a candidate string for being such a named operator
1312// and if so - invoke the appropriate handler
1313bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) {
1314 // A named operator should be either lower or upper case, but not a mix
1315 if (Name.compare(Name.lower()) && Name.compare(Name.upper()))
1316 return false;
1317 if (Name.equals_lower("not"))
1318 SM.onNot();
1319 else if (Name.equals_lower("or"))
1320 SM.onOr();
1321 else if (Name.equals_lower("shl"))
1322 SM.onLShift();
1323 else if (Name.equals_lower("shr"))
1324 SM.onRShift();
1325 else if (Name.equals_lower("xor"))
1326 SM.onXor();
1327 else if (Name.equals_lower("and"))
1328 SM.onAnd();
Coby Tayree41a5b552017-06-27 16:58:27 +00001329 else if (Name.equals_lower("mod"))
1330 SM.onMod();
Coby Tayree2cb497a2017-04-04 14:43:23 +00001331 else
1332 return false;
1333 return true;
1334}
1335
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001336bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
Rafael Espindola961d4692014-11-11 05:18:41 +00001337 MCAsmParser &Parser = getParser();
Chad Rosier6844ea02012-10-24 22:13:37 +00001338 const AsmToken &Tok = Parser.getTok();
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +00001339 StringRef ErrMsg;
Chad Rosier51afe632012-06-27 22:34:28 +00001340
Marina Yatsina8dfd5cb2015-12-24 12:09:51 +00001341 AsmToken::TokenKind PrevTK = AsmToken::Error;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001342 bool Done = false;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001343 while (!Done) {
1344 bool UpdateLocLex = true;
Andrew V. Tischenkofdb264e2017-05-26 13:23:34 +00001345 AsmToken::TokenKind TK = getLexer().getKind();
Chad Rosier5c118fd2013-01-14 22:31:35 +00001346
David Majnemer6a5b8122014-06-19 01:25:43 +00001347 switch (TK) {
Coby Tayreed8912892017-08-24 08:46:25 +00001348 default:
1349 if ((Done = SM.isValidEndState()))
Chad Rosier5c118fd2013-01-14 22:31:35 +00001350 break;
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001351 return Error(Tok.getLoc(), "unknown token in expression");
Coby Tayreed8912892017-08-24 08:46:25 +00001352 case AsmToken::EndOfStatement:
Chad Rosierbfb70992013-04-17 00:11:46 +00001353 Done = true;
1354 break;
Coby Tayreed8912892017-08-24 08:46:25 +00001355 case AsmToken::Real:
1356 // DotOperator: [ebx].0
1357 UpdateLocLex = false;
1358 if (ParseIntelDotOperator(SM, End))
1359 return true;
1360 break;
David Majnemer6a5b8122014-06-19 01:25:43 +00001361 case AsmToken::String:
Chad Rosier5c118fd2013-01-14 22:31:35 +00001362 case AsmToken::Identifier: {
Chad Rosier152749c2013-04-12 18:54:20 +00001363 SMLoc IdentLoc = Tok.getLoc();
1364 StringRef Identifier = Tok.getString();
Coby Tayree07a89742017-03-21 19:31:55 +00001365 UpdateLocLex = false;
Coby Tayreec3d24112017-09-29 07:02:46 +00001366 // Register
1367 unsigned Reg;
1368 if (Tok.isNot(AsmToken::String) && !ParseRegister(Reg, IdentLoc, End)) {
1369 if (SM.onRegister(Reg, ErrMsg))
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +00001370 return Error(Tok.getLoc(), ErrMsg);
Coby Tayreec3d24112017-09-29 07:02:46 +00001371 break;
1372 }
1373 // Operator synonymous ("not", "or" etc.)
1374 if ((UpdateLocLex = ParseIntelNamedOperator(Identifier, SM)))
1375 break;
1376 // Symbol reference, when parsing assembly content
1377 InlineAsmIdentifierInfo Info;
1378 const MCExpr *Val;
1379 if (!isParsingInlineAsm()) {
1380 if (getParser().parsePrimaryExpr(Val, End)) {
Coby Tayree07a89742017-03-21 19:31:55 +00001381 return Error(Tok.getLoc(), "Unexpected identifier!");
Coby Tayreec3d24112017-09-29 07:02:46 +00001382 } else if (SM.onIdentifierExpr(Val, Identifier, Info, false, ErrMsg)) {
Coby Tayreed8912892017-08-24 08:46:25 +00001383 return Error(IdentLoc, ErrMsg);
Coby Tayreec3d24112017-09-29 07:02:46 +00001384 } else
1385 break;
1386 }
1387 // MS InlineAsm operators (TYPE/LENGTH/SIZE)
1388 if (unsigned OpKind = IdentifyIntelInlineAsmOperator(Identifier)) {
Coby Tayreed8912892017-08-24 08:46:25 +00001389 if (OpKind == IOK_OFFSET)
Coby Tayree07a89742017-03-21 19:31:55 +00001390 return Error(IdentLoc, "Dealing OFFSET operator as part of"
1391 "a compound immediate expression is yet to be supported");
Coby Tayreec3d24112017-09-29 07:02:46 +00001392 if (int64_t Val = ParseIntelInlineAsmOperator(OpKind)) {
1393 if (SM.onInteger(Val, ErrMsg))
1394 return Error(IdentLoc, ErrMsg);
1395 } else
Coby Tayree07a89742017-03-21 19:31:55 +00001396 return true;
Coby Tayreec3d24112017-09-29 07:02:46 +00001397 break;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001398 }
Coby Tayreec3d24112017-09-29 07:02:46 +00001399 // MS Dot Operator expression
1400 if (Identifier.count('.') && PrevTK == AsmToken::RBrac) {
1401 if (ParseIntelDotOperator(SM, End))
1402 return true;
1403 break;
1404 }
1405 // MS InlineAsm identifier
1406 if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info, false, End))
1407 return true;
1408 else if (SM.onIdentifierExpr(Val, Identifier, Info, true, ErrMsg))
1409 return Error(IdentLoc, ErrMsg);
Coby Tayree07a89742017-03-21 19:31:55 +00001410 break;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001411 }
Kevin Enderby36eba252013-12-19 23:16:14 +00001412 case AsmToken::Integer: {
Kevin Enderby36eba252013-12-19 23:16:14 +00001413 // Look for 'b' or 'f' following an Integer as a directional label
1414 SMLoc Loc = getTok().getLoc();
1415 int64_t IntVal = getTok().getIntVal();
1416 End = consumeToken();
1417 UpdateLocLex = false;
1418 if (getLexer().getKind() == AsmToken::Identifier) {
1419 StringRef IDVal = getTok().getString();
1420 if (IDVal == "f" || IDVal == "b") {
1421 MCSymbol *Sym =
Jim Grosbach6f482002015-05-18 18:43:14 +00001422 getContext().getDirectionalLocalSymbol(IntVal, IDVal == "b");
Kevin Enderby36eba252013-12-19 23:16:14 +00001423 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
Michael Liao5bf95782014-12-04 05:20:33 +00001424 const MCExpr *Val =
NAKAMURA Takumi0a7d0ad2015-09-22 11:15:07 +00001425 MCSymbolRefExpr::create(Sym, Variant, getContext());
Kevin Enderby36eba252013-12-19 23:16:14 +00001426 if (IDVal == "b" && Sym->isUndefined())
1427 return Error(Loc, "invalid reference to undefined symbol");
1428 StringRef Identifier = Sym->getName();
Coby Tayreec3d24112017-09-29 07:02:46 +00001429 InlineAsmIdentifierInfo Info;
1430 if (SM.onIdentifierExpr(Val, Identifier, Info,
1431 isParsingInlineAsm(), ErrMsg))
Coby Tayreed8912892017-08-24 08:46:25 +00001432 return Error(Loc, ErrMsg);
Kevin Enderby36eba252013-12-19 23:16:14 +00001433 End = consumeToken();
1434 } else {
Kevin Enderby9d117022014-01-23 21:52:41 +00001435 if (SM.onInteger(IntVal, ErrMsg))
1436 return Error(Loc, ErrMsg);
Kevin Enderby36eba252013-12-19 23:16:14 +00001437 }
1438 } else {
Kevin Enderby9d117022014-01-23 21:52:41 +00001439 if (SM.onInteger(IntVal, ErrMsg))
1440 return Error(Loc, ErrMsg);
Kevin Enderby36eba252013-12-19 23:16:14 +00001441 }
Chad Rosier5c118fd2013-01-14 22:31:35 +00001442 break;
Kevin Enderby36eba252013-12-19 23:16:14 +00001443 }
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +00001444 case AsmToken::Plus:
1445 if (SM.onPlus(ErrMsg))
1446 return Error(getTok().getLoc(), ErrMsg);
1447 break;
1448 case AsmToken::Minus:
1449 if (SM.onMinus(ErrMsg))
1450 return Error(getTok().getLoc(), ErrMsg);
1451 break;
Ehsan Akhgari4103da62014-07-04 19:13:05 +00001452 case AsmToken::Tilde: SM.onNot(); break;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001453 case AsmToken::Star: SM.onStar(); break;
Chad Rosier4a7005e2013-04-05 16:28:55 +00001454 case AsmToken::Slash: SM.onDivide(); break;
Kevin Enderby2e13b1c2014-01-15 19:05:24 +00001455 case AsmToken::Pipe: SM.onOr(); break;
Michael Kupersteine3de07a2015-06-14 12:59:45 +00001456 case AsmToken::Caret: SM.onXor(); break;
Kevin Enderby2e13b1c2014-01-15 19:05:24 +00001457 case AsmToken::Amp: SM.onAnd(); break;
Kevin Enderbyd6b10712014-02-06 01:21:15 +00001458 case AsmToken::LessLess:
1459 SM.onLShift(); break;
1460 case AsmToken::GreaterGreater:
1461 SM.onRShift(); break;
Coby Tayreed8912892017-08-24 08:46:25 +00001462 case AsmToken::LBrac:
1463 if (SM.onLBrac())
1464 return Error(Tok.getLoc(), "unexpected bracket encountered");
1465 break;
1466 case AsmToken::RBrac:
1467 if (SM.onRBrac())
1468 return Error(Tok.getLoc(), "unexpected bracket encountered");
1469 break;
Chad Rosier4a7005e2013-04-05 16:28:55 +00001470 case AsmToken::LParen: SM.onLParen(); break;
1471 case AsmToken::RParen: SM.onRParen(); break;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001472 }
Chad Rosier31246272013-04-17 21:01:45 +00001473 if (SM.hadError())
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001474 return Error(Tok.getLoc(), "unknown token in expression");
Chad Rosier31246272013-04-17 21:01:45 +00001475
Alp Tokera5b88a52013-12-02 16:06:06 +00001476 if (!Done && UpdateLocLex)
1477 End = consumeToken();
Marina Yatsina8dfd5cb2015-12-24 12:09:51 +00001478
1479 PrevTK = TK;
Devang Patel41b9dde2012-01-17 18:00:18 +00001480 }
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001481 return false;
Chad Rosier5362af92013-04-16 18:15:40 +00001482}
1483
Coby Tayreed8912892017-08-24 08:46:25 +00001484void X86AsmParser::RewriteIntelExpression(IntelExprStateMachine &SM,
1485 SMLoc Start, SMLoc End) {
1486 SMLoc Loc = Start;
1487 unsigned ExprLen = End.getPointer() - Start.getPointer();
1488 // Skip everything before a symbol displacement (if we have one)
1489 if (SM.getSym()) {
1490 StringRef SymName = SM.getSymName();
1491 if (unsigned Len = SymName.data() - Start.getPointer())
1492 InstInfo->AsmRewrites->emplace_back(AOK_Skip, Start, Len);
1493 Loc = SMLoc::getFromPointer(SymName.data() + SymName.size());
1494 ExprLen = End.getPointer() - (SymName.data() + SymName.size());
1495 // If we have only a symbol than there's no need for complex rewrite,
1496 // simply skip everything after it
1497 if (!(SM.getBaseReg() || SM.getIndexReg() || SM.getImm())) {
1498 if (ExprLen)
1499 InstInfo->AsmRewrites->emplace_back(AOK_Skip, Loc, ExprLen);
1500 return;
Nirav Dave8601ac12016-08-02 17:56:03 +00001501 }
1502 }
Coby Tayreed8912892017-08-24 08:46:25 +00001503 // Build an Intel Expression rewrite
1504 StringRef BaseRegStr;
1505 StringRef IndexRegStr;
1506 if (SM.getBaseReg())
1507 BaseRegStr = X86IntelInstPrinter::getRegisterName(SM.getBaseReg());
1508 if (SM.getIndexReg())
1509 IndexRegStr = X86IntelInstPrinter::getRegisterName(SM.getIndexReg());
1510 // Emit it
1511 IntelExpr Expr(BaseRegStr, IndexRegStr, SM.getScale(), SM.getImm(), SM.isMemExpr());
1512 InstInfo->AsmRewrites->emplace_back(Loc, ExprLen, Expr);
Devang Patel41b9dde2012-01-17 18:00:18 +00001513}
1514
Chad Rosier8a244662013-04-02 20:02:33 +00001515// Inline assembly may use variable names with namespace alias qualifiers.
Coby Tayreed8912892017-08-24 08:46:25 +00001516bool X86AsmParser::ParseIntelInlineAsmIdentifier(const MCExpr *&Val,
1517 StringRef &Identifier,
1518 InlineAsmIdentifierInfo &Info,
1519 bool IsUnevaluatedOperand,
1520 SMLoc &End) {
Rafael Espindola961d4692014-11-11 05:18:41 +00001521 MCAsmParser &Parser = getParser();
Reid Klecknerc2b92542015-08-26 21:57:25 +00001522 assert(isParsingInlineAsm() && "Expected to be parsing inline assembly.");
Craig Topper062a2ba2014-04-25 05:30:21 +00001523 Val = nullptr;
Chad Rosier8a244662013-04-02 20:02:33 +00001524
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001525 StringRef LineBuf(Identifier.data());
Coby Tayreec3d24112017-09-29 07:02:46 +00001526 SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001527
Chad Rosier8a244662013-04-02 20:02:33 +00001528 const AsmToken &Tok = Parser.getTok();
Ehsan Akhgaridb0e7062014-09-22 02:21:35 +00001529 SMLoc Loc = Tok.getLoc();
John McCallf73981b2013-05-03 00:15:41 +00001530
1531 // Advance the token stream until the end of the current token is
1532 // after the end of what the frontend claimed.
1533 const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
Reid Klecknerc2b92542015-08-26 21:57:25 +00001534 do {
John McCallf73981b2013-05-03 00:15:41 +00001535 End = Tok.getEndLoc();
1536 getLexer().Lex();
Reid Klecknerc2b92542015-08-26 21:57:25 +00001537 } while (End.getPointer() < EndPtr);
Ehsan Akhgaridb0e7062014-09-22 02:21:35 +00001538 Identifier = LineBuf;
1539
Reid Klecknerc2b92542015-08-26 21:57:25 +00001540 // The frontend should end parsing on an assembler token boundary, unless it
1541 // failed parsing.
Coby Tayreec3d24112017-09-29 07:02:46 +00001542 assert((End.getPointer() == EndPtr ||
1543 Info.isKind(InlineAsmIdentifierInfo::IK_Invalid)) &&
1544 "frontend claimed part of a token?");
Reid Klecknerc2b92542015-08-26 21:57:25 +00001545
Ehsan Akhgaridb0e7062014-09-22 02:21:35 +00001546 // If the identifier lookup was unsuccessful, assume that we are dealing with
1547 // a label.
Coby Tayreec3d24112017-09-29 07:02:46 +00001548 if (Info.isKind(InlineAsmIdentifierInfo::IK_Invalid)) {
Ehsan Akhgaribb6bb072014-09-22 20:40:36 +00001549 StringRef InternalName =
1550 SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(),
1551 Loc, false);
1552 assert(InternalName.size() && "We should have an internal name here.");
1553 // Push a rewrite for replacing the identifier name with the internal name.
Craig Topper7d5b2312015-10-10 05:25:02 +00001554 InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(),
1555 InternalName);
Coby Tayreec3d24112017-09-29 07:02:46 +00001556 } else if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal))
1557 return false;
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001558 // Create the symbol reference.
Jim Grosbach6f482002015-05-18 18:43:14 +00001559 MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
Chad Rosier8a244662013-04-02 20:02:33 +00001560 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
Jim Grosbach13760bd2015-05-30 01:25:56 +00001561 Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext());
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001562 return false;
Chad Rosier8a244662013-04-02 20:02:33 +00001563}
1564
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001565//ParseRoundingModeOp - Parse AVX-512 rounding mode operand
1566std::unique_ptr<X86Operand>
1567X86AsmParser::ParseRoundingModeOp(SMLoc Start, SMLoc End) {
1568 MCAsmParser &Parser = getParser();
1569 const AsmToken &Tok = Parser.getTok();
Elena Demikhovsky29792e92015-05-07 11:24:42 +00001570 // Eat "{" and mark the current place.
1571 const SMLoc consumedToken = consumeToken();
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001572 if (Tok.getIdentifier().startswith("r")){
1573 int rndMode = StringSwitch<int>(Tok.getIdentifier())
1574 .Case("rn", X86::STATIC_ROUNDING::TO_NEAREST_INT)
1575 .Case("rd", X86::STATIC_ROUNDING::TO_NEG_INF)
1576 .Case("ru", X86::STATIC_ROUNDING::TO_POS_INF)
1577 .Case("rz", X86::STATIC_ROUNDING::TO_ZERO)
1578 .Default(-1);
1579 if (-1 == rndMode)
1580 return ErrorOperand(Tok.getLoc(), "Invalid rounding mode.");
1581 Parser.Lex(); // Eat "r*" of r*-sae
1582 if (!getLexer().is(AsmToken::Minus))
1583 return ErrorOperand(Tok.getLoc(), "Expected - at this point");
1584 Parser.Lex(); // Eat "-"
1585 Parser.Lex(); // Eat the sae
1586 if (!getLexer().is(AsmToken::RCurly))
1587 return ErrorOperand(Tok.getLoc(), "Expected } at this point");
1588 Parser.Lex(); // Eat "}"
1589 const MCExpr *RndModeOp =
Jim Grosbach13760bd2015-05-30 01:25:56 +00001590 MCConstantExpr::create(rndMode, Parser.getContext());
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001591 return X86Operand::CreateImm(RndModeOp, Start, End);
1592 }
Elena Demikhovsky29792e92015-05-07 11:24:42 +00001593 if(Tok.getIdentifier().equals("sae")){
1594 Parser.Lex(); // Eat the sae
1595 if (!getLexer().is(AsmToken::RCurly))
1596 return ErrorOperand(Tok.getLoc(), "Expected } at this point");
1597 Parser.Lex(); // Eat "}"
1598 return X86Operand::CreateToken("{sae}", consumedToken);
1599 }
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001600 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1601}
Chad Rosier91c82662012-10-24 17:22:29 +00001602
Chad Rosier5dcb4662012-10-24 22:21:50 +00001603/// Parse the '.' operator.
Coby Tayreed8912892017-08-24 08:46:25 +00001604bool X86AsmParser::ParseIntelDotOperator(IntelExprStateMachine &SM, SMLoc &End) {
1605 const AsmToken &Tok = getTok();
1606 unsigned Offset;
Chad Rosier5dcb4662012-10-24 22:21:50 +00001607
Reid Kleckner94a1c4d2014-03-06 19:19:12 +00001608 // Drop the optional '.'.
1609 StringRef DotDispStr = Tok.getString();
1610 if (DotDispStr.startswith("."))
1611 DotDispStr = DotDispStr.drop_front(1);
Chad Rosier5dcb4662012-10-24 22:21:50 +00001612
Chad Rosier5dcb4662012-10-24 22:21:50 +00001613 // .Imm gets lexed as a real.
1614 if (Tok.is(AsmToken::Real)) {
1615 APInt DotDisp;
1616 DotDispStr.getAsInteger(10, DotDisp);
Coby Tayreed8912892017-08-24 08:46:25 +00001617 Offset = DotDisp.getZExtValue();
Chad Rosiercc541e82013-04-19 15:57:00 +00001618 } else if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
Chad Rosier240b7b92012-10-25 21:51:10 +00001619 std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1620 if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
Coby Tayreed8912892017-08-24 08:46:25 +00001621 Offset))
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001622 return Error(Tok.getLoc(), "Unable to lookup field reference!");
Chad Rosiercc541e82013-04-19 15:57:00 +00001623 } else
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001624 return Error(Tok.getLoc(), "Unexpected token type!");
Chad Rosier911c1f32012-10-25 17:37:43 +00001625
Coby Tayreed8912892017-08-24 08:46:25 +00001626 // Eat the DotExpression and update End
1627 End = SMLoc::getFromPointer(DotDispStr.data());
1628 const char *DotExprEndLoc = DotDispStr.data() + DotDispStr.size();
1629 while (Tok.getLoc().getPointer() < DotExprEndLoc)
1630 Lex();
1631 SM.addImm(Offset);
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001632 return false;
Chad Rosier5dcb4662012-10-24 22:21:50 +00001633}
1634
Chad Rosier91c82662012-10-24 17:22:29 +00001635/// Parse the 'offset' operator. This operator is used to specify the
1636/// location rather then the content of a variable.
David Blaikie960ea3f2014-06-08 16:18:35 +00001637std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOffsetOfOperator() {
Rafael Espindola961d4692014-11-11 05:18:41 +00001638 MCAsmParser &Parser = getParser();
Chad Rosier18785852013-04-09 20:58:48 +00001639 const AsmToken &Tok = Parser.getTok();
Chad Rosier10d1d1c2013-04-09 20:44:09 +00001640 SMLoc OffsetOfLoc = Tok.getLoc();
Chad Rosier91c82662012-10-24 17:22:29 +00001641 Parser.Lex(); // Eat offset.
Chad Rosier91c82662012-10-24 17:22:29 +00001642
Chad Rosier91c82662012-10-24 17:22:29 +00001643 const MCExpr *Val;
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001644 InlineAsmIdentifierInfo Info;
Chad Rosier18785852013-04-09 20:58:48 +00001645 SMLoc Start = Tok.getLoc(), End;
Chad Rosierae7ecd62013-04-11 23:37:34 +00001646 StringRef Identifier = Tok.getString();
Coby Tayreed8912892017-08-24 08:46:25 +00001647 if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
1648 /*Unevaluated=*/false, End))
Craig Topper062a2ba2014-04-25 05:30:21 +00001649 return nullptr;
Chad Rosierae7ecd62013-04-11 23:37:34 +00001650
Coby Tayreec3d24112017-09-29 07:02:46 +00001651 void *Decl = nullptr;
1652 // FIXME: MS evaluates "offset <Constant>" to the underlying integral
1653 if (Info.isKind(InlineAsmIdentifierInfo::IK_EnumVal))
1654 return ErrorOperand(Start, "offset operator cannot yet handle constants");
1655 else if (Info.isKind(InlineAsmIdentifierInfo::IK_Var))
1656 Decl = Info.Var.Decl;
Chad Rosiere2f03772012-10-26 16:09:20 +00001657 // Don't emit the offset operator.
Craig Topper7d5b2312015-10-10 05:25:02 +00001658 InstInfo->AsmRewrites->emplace_back(AOK_Skip, OffsetOfLoc, 7);
Chad Rosiere2f03772012-10-26 16:09:20 +00001659
Chad Rosier91c82662012-10-24 17:22:29 +00001660 // The offset operator will have an 'r' constraint, thus we need to create
1661 // register operand to ensure proper matching. Just pick a GPR based on
1662 // the size of a pointer.
Nirav Dave6477ce22016-09-26 19:33:36 +00001663 bool Parse32 = is32BitMode() || Code16GCC;
1664 unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX : X86::BX);
1665
Chad Rosiera4bc9432013-01-10 22:10:27 +00001666 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
Coby Tayreec3d24112017-09-29 07:02:46 +00001667 OffsetOfLoc, Identifier, Decl);
Devang Patel41b9dde2012-01-17 18:00:18 +00001668}
1669
Coby Tayree07a89742017-03-21 19:31:55 +00001670// Query a candidate string for being an Intel assembly operator
1671// Report back its kind, or IOK_INVALID if does not evaluated as a known one
Coby Tayreed8912892017-08-24 08:46:25 +00001672unsigned X86AsmParser::IdentifyIntelInlineAsmOperator(StringRef Name) {
Coby Tayree07a89742017-03-21 19:31:55 +00001673 return StringSwitch<unsigned>(Name)
1674 .Cases("TYPE","type",IOK_TYPE)
1675 .Cases("SIZE","size",IOK_SIZE)
1676 .Cases("LENGTH","length",IOK_LENGTH)
1677 .Cases("OFFSET","offset",IOK_OFFSET)
1678 .Default(IOK_INVALID);
1679}
Chad Rosierd0ed73a2013-01-17 19:21:48 +00001680
1681/// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1682/// returns the number of elements in an array. It returns the value 1 for
1683/// non-array variables. The SIZE operator returns the size of a C or C++
1684/// variable. A variable's size is the product of its LENGTH and TYPE. The
1685/// TYPE operator returns the size of a C or C++ type or variable. If the
1686/// variable is an array, TYPE returns the size of a single element.
Coby Tayreed8912892017-08-24 08:46:25 +00001687unsigned X86AsmParser::ParseIntelInlineAsmOperator(unsigned OpKind) {
Rafael Espindola961d4692014-11-11 05:18:41 +00001688 MCAsmParser &Parser = getParser();
Chad Rosier18785852013-04-09 20:58:48 +00001689 const AsmToken &Tok = Parser.getTok();
Chad Rosier10d1d1c2013-04-09 20:44:09 +00001690 Parser.Lex(); // Eat operator.
Chad Rosier11c42f22012-10-26 18:04:20 +00001691
Craig Topper062a2ba2014-04-25 05:30:21 +00001692 const MCExpr *Val = nullptr;
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001693 InlineAsmIdentifierInfo Info;
Chad Rosier18785852013-04-09 20:58:48 +00001694 SMLoc Start = Tok.getLoc(), End;
Chad Rosierb67f8052013-04-11 23:57:04 +00001695 StringRef Identifier = Tok.getString();
Coby Tayreed8912892017-08-24 08:46:25 +00001696 if (ParseIntelInlineAsmIdentifier(Val, Identifier, Info,
1697 /*Unevaluated=*/true, End))
Coby Tayree07a89742017-03-21 19:31:55 +00001698 return 0;
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001699
Coby Tayreec3d24112017-09-29 07:02:46 +00001700 if (!Info.isKind(InlineAsmIdentifierInfo::IK_Var)) {
Coby Tayree07a89742017-03-21 19:31:55 +00001701 Error(Start, "unable to lookup expression");
1702 return 0;
1703 }
Coby Tayreed8912892017-08-24 08:46:25 +00001704
Chad Rosierf6675c32013-04-22 17:01:46 +00001705 unsigned CVal = 0;
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001706 switch(OpKind) {
1707 default: llvm_unreachable("Unexpected operand kind!");
Coby Tayreec3d24112017-09-29 07:02:46 +00001708 case IOK_LENGTH: CVal = Info.Var.Length; break;
1709 case IOK_SIZE: CVal = Info.Var.Size; break;
1710 case IOK_TYPE: CVal = Info.Var.Type; break;
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001711 }
Eric Christopheradfe5362017-07-25 19:22:09 +00001712
Coby Tayree07a89742017-03-21 19:31:55 +00001713 return CVal;
Chad Rosier11c42f22012-10-26 18:04:20 +00001714}
1715
Coby Tayreed8912892017-08-24 08:46:25 +00001716bool X86AsmParser::ParseIntelMemoryOperandSize(unsigned &Size) {
1717 Size = StringSwitch<unsigned>(getTok().getString())
1718 .Cases("BYTE", "byte", 8)
1719 .Cases("WORD", "word", 16)
1720 .Cases("DWORD", "dword", 32)
Coby Tayree566348f2017-09-28 11:04:08 +00001721 .Cases("FLOAT", "float", 32)
1722 .Cases("LONG", "long", 32)
Coby Tayreed8912892017-08-24 08:46:25 +00001723 .Cases("FWORD", "fword", 48)
Coby Tayree566348f2017-09-28 11:04:08 +00001724 .Cases("DOUBLE", "double", 64)
Coby Tayreed8912892017-08-24 08:46:25 +00001725 .Cases("QWORD", "qword", 64)
1726 .Cases("MMWORD","mmword", 64)
1727 .Cases("XWORD", "xword", 80)
1728 .Cases("TBYTE", "tbyte", 80)
1729 .Cases("XMMWORD", "xmmword", 128)
1730 .Cases("YMMWORD", "ymmword", 256)
1731 .Cases("ZMMWORD", "zmmword", 512)
1732 .Cases("OPAQUE", "opaque", -1U) // needs to be non-zero, but doesn't matter
1733 .Default(0);
1734 if (Size) {
1735 const AsmToken &Tok = Lex(); // Eat operand size (e.g., byte, word).
1736 if (!(Tok.getString().equals("PTR") || Tok.getString().equals("ptr")))
1737 return Error(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!");
1738 Lex(); // Eat ptr.
1739 }
1740 return false;
1741}
1742
David Blaikie960ea3f2014-06-08 16:18:35 +00001743std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
Rafael Espindola961d4692014-11-11 05:18:41 +00001744 MCAsmParser &Parser = getParser();
Chad Rosier70f47592013-04-10 20:07:47 +00001745 const AsmToken &Tok = Parser.getTok();
David Majnemeraa34d792013-08-27 21:56:17 +00001746 SMLoc Start, End;
Chad Rosier91c82662012-10-24 17:22:29 +00001747
Coby Tayree07a89742017-03-21 19:31:55 +00001748 // FIXME: Offset operator
1749 // Should be handled as part of immediate expression, as other operators
1750 // Currently, only supported as a stand-alone operand
1751 if (isParsingInlineAsm())
Coby Tayreed8912892017-08-24 08:46:25 +00001752 if (IdentifyIntelInlineAsmOperator(Tok.getString()) == IOK_OFFSET)
Chad Rosier10d1d1c2013-04-09 20:44:09 +00001753 return ParseIntelOffsetOfOperator();
Chad Rosier11c42f22012-10-26 18:04:20 +00001754
Coby Tayreed8912892017-08-24 08:46:25 +00001755 // Parse optional Size directive.
1756 unsigned Size;
1757 if (ParseIntelMemoryOperandSize(Size))
1758 return nullptr;
1759 bool PtrInOperand = bool(Size);
Nirav Dave8601ac12016-08-02 17:56:03 +00001760
David Majnemeraa34d792013-08-27 21:56:17 +00001761 Start = Tok.getLoc();
1762
Coby Tayreed8912892017-08-24 08:46:25 +00001763 // Rounding mode operand.
Akira Hatanakabd9fc282015-11-14 05:20:05 +00001764 if (getSTI().getFeatureBits()[X86::FeatureAVX512] &&
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001765 getLexer().is(AsmToken::LCurly))
1766 return ParseRoundingModeOp(Start, End);
1767
Coby Tayreed8912892017-08-24 08:46:25 +00001768 // Register operand.
Devang Patelce6a2ca2012-01-20 22:32:05 +00001769 unsigned RegNo = 0;
Coby Tayreed8912892017-08-24 08:46:25 +00001770 if (Tok.is(AsmToken::Identifier) && !ParseRegister(RegNo, Start, End)) {
Douglas Katzman0411e862016-10-05 15:23:35 +00001771 if (RegNo == X86::RIP)
1772 return ErrorOperand(Start, "rip can only be used as a base register");
Coby Tayreed8912892017-08-24 08:46:25 +00001773 // A Register followed by ':' is considered a segment override
1774 if (Tok.isNot(AsmToken::Colon))
1775 return !PtrInOperand ? X86Operand::CreateReg(RegNo, Start, End) :
1776 ErrorOperand(Start, "expected memory operand after 'ptr', "
1777 "found register operand instead");
1778 // An alleged segment override. check if we have a valid segment register
1779 if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
1780 return ErrorOperand(Start, "invalid segment register");
1781 // Eat ':' and update Start location
1782 Start = Lex().getLoc();
Devang Patel46831de2012-01-12 01:36:43 +00001783 }
1784
Nirav Dave8601ac12016-08-02 17:56:03 +00001785 // Immediates and Memory
Coby Tayreed8912892017-08-24 08:46:25 +00001786 IntelExprStateMachine SM;
Nirav Dave8601ac12016-08-02 17:56:03 +00001787 if (ParseIntelExpression(SM, End))
1788 return nullptr;
1789
Coby Tayreed8912892017-08-24 08:46:25 +00001790 if (isParsingInlineAsm())
1791 RewriteIntelExpression(SM, Start, Tok.getLoc());
1792
Nirav Dave8601ac12016-08-02 17:56:03 +00001793 int64_t Imm = SM.getImm();
Coby Tayreed8912892017-08-24 08:46:25 +00001794 const MCExpr *Disp = SM.getSym();
1795 const MCExpr *ImmDisp = MCConstantExpr::create(Imm, getContext());
1796 if (Disp && Imm)
1797 Disp = MCBinaryExpr::createAdd(Disp, ImmDisp, getContext());
1798 if (!Disp)
1799 Disp = ImmDisp;
Nirav Dave8601ac12016-08-02 17:56:03 +00001800
Coby Tayreed8912892017-08-24 08:46:25 +00001801 // RegNo != 0 specifies a valid segment register,
1802 // and we are parsing a segment override
1803 if (!SM.isMemExpr() && !RegNo)
1804 return X86Operand::CreateImm(Disp, Start, End);
Nirav Dave8601ac12016-08-02 17:56:03 +00001805
Coby Tayreed8912892017-08-24 08:46:25 +00001806 StringRef ErrMsg;
1807 unsigned BaseReg = SM.getBaseReg();
1808 unsigned IndexReg = SM.getIndexReg();
1809 unsigned Scale = SM.getScale();
Nirav Dave8601ac12016-08-02 17:56:03 +00001810
Coby Tayreed8912892017-08-24 08:46:25 +00001811 if ((BaseReg || IndexReg) &&
1812 CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, ErrMsg))
1813 return ErrorOperand(Start, ErrMsg);
1814 if (isParsingInlineAsm())
1815 return CreateMemForInlineAsm(RegNo, Disp, BaseReg, IndexReg,
1816 Scale, Start, End, Size, SM.getSymName(),
1817 SM.getIdentifierInfo());
1818 if (!(BaseReg || IndexReg || RegNo))
1819 return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size);
1820 return X86Operand::CreateMem(getPointerWidth(), RegNo, Disp,
1821 BaseReg, IndexReg, Scale, Start, End, Size);
Devang Patel46831de2012-01-12 01:36:43 +00001822}
1823
David Blaikie960ea3f2014-06-08 16:18:35 +00001824std::unique_ptr<X86Operand> X86AsmParser::ParseATTOperand() {
Rafael Espindola961d4692014-11-11 05:18:41 +00001825 MCAsmParser &Parser = getParser();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00001826 switch (getLexer().getKind()) {
1827 default:
Chris Lattnerb9270732010-04-17 18:56:34 +00001828 // Parse a memory operand with no segment register.
1829 return ParseMemOperand(0, Parser.getTok().getLoc());
Chris Lattnercc2ad082010-01-15 18:27:19 +00001830 case AsmToken::Percent: {
Chris Lattnerb9270732010-04-17 18:56:34 +00001831 // Read the register.
Chris Lattnercc2ad082010-01-15 18:27:19 +00001832 unsigned RegNo;
Chris Lattner0c2538f2010-01-15 18:51:29 +00001833 SMLoc Start, End;
Craig Topper062a2ba2014-04-25 05:30:21 +00001834 if (ParseRegister(RegNo, Start, End)) return nullptr;
Bruno Cardoso Lopes306a1f92010-07-24 00:06:39 +00001835 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
Benjamin Kramer1930b002011-10-16 12:10:27 +00001836 Error(Start, "%eiz and %riz can only be used as index registers",
1837 SMRange(Start, End));
Craig Topper062a2ba2014-04-25 05:30:21 +00001838 return nullptr;
Bruno Cardoso Lopes306a1f92010-07-24 00:06:39 +00001839 }
Douglas Katzman0411e862016-10-05 15:23:35 +00001840 if (RegNo == X86::RIP) {
1841 Error(Start, "%rip can only be used as a base register",
1842 SMRange(Start, End));
1843 return nullptr;
1844 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001845
Chris Lattnerb9270732010-04-17 18:56:34 +00001846 // If this is a segment register followed by a ':', then this is the start
1847 // of a memory reference, otherwise this is a normal register reference.
1848 if (getLexer().isNot(AsmToken::Colon))
1849 return X86Operand::CreateReg(RegNo, Start, End);
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001850
Reid Kleckner0c5da972014-07-31 23:03:22 +00001851 if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
1852 return ErrorOperand(Start, "invalid segment register");
1853
Chris Lattnerb9270732010-04-17 18:56:34 +00001854 getParser().Lex(); // Eat the colon.
1855 return ParseMemOperand(RegNo, Start);
Chris Lattnercc2ad082010-01-15 18:27:19 +00001856 }
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00001857 case AsmToken::Dollar: {
1858 // $42 -> immediate.
Sean Callanan936b0d32010-01-19 21:44:56 +00001859 SMLoc Start = Parser.getTok().getLoc(), End;
Sean Callanana83fd7d2010-01-19 20:27:46 +00001860 Parser.Lex();
Daniel Dunbar73da11e2009-08-31 08:08:38 +00001861 const MCExpr *Val;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00001862 if (getParser().parseExpression(Val, End))
Craig Topper062a2ba2014-04-25 05:30:21 +00001863 return nullptr;
Chris Lattner528d00b2010-01-15 19:28:38 +00001864 return X86Operand::CreateImm(Val, Start, End);
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00001865 }
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001866 case AsmToken::LCurly:{
1867 SMLoc Start = Parser.getTok().getLoc(), End;
Akira Hatanakabd9fc282015-11-14 05:20:05 +00001868 if (getSTI().getFeatureBits()[X86::FeatureAVX512])
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001869 return ParseRoundingModeOp(Start, End);
Nirav Dave8601ac12016-08-02 17:56:03 +00001870 return ErrorOperand(Start, "Unexpected '{' in expression");
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001871 }
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00001872 }
Daniel Dunbar2b11c7d2009-07-20 20:01:54 +00001873}
1874
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001875// true on failure, false otherwise
1876// If no {z} mark was found - Parser doesn't advance
1877bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
1878 const SMLoc &StartLoc) {
1879 MCAsmParser &Parser = getParser();
1880 // Assuming we are just pass the '{' mark, quering the next token
Coby Tayree179ff0e2016-11-20 09:31:11 +00001881 // Searched for {z}, but none was found. Return false, as no parsing error was
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001882 // encountered
1883 if (!(getLexer().is(AsmToken::Identifier) &&
1884 (getLexer().getTok().getIdentifier() == "z")))
1885 return false;
1886 Parser.Lex(); // Eat z
1887 // Query and eat the '}' mark
1888 if (!getLexer().is(AsmToken::RCurly))
1889 return Error(getLexer().getLoc(), "Expected } at this point");
1890 Parser.Lex(); // Eat '}'
1891 // Assign Z with the {z} mark opernad
Benjamin Kramerfc54e352016-11-24 15:17:39 +00001892 Z = X86Operand::CreateToken("{z}", StartLoc);
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001893 return false;
1894}
1895
1896// true on failure, false otherwise
David Blaikie960ea3f2014-06-08 16:18:35 +00001897bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
1898 const MCParsedAsmOperand &Op) {
Rafael Espindola961d4692014-11-11 05:18:41 +00001899 MCAsmParser &Parser = getParser();
Akira Hatanakabd9fc282015-11-14 05:20:05 +00001900 if(getSTI().getFeatureBits()[X86::FeatureAVX512]) {
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001901 if (getLexer().is(AsmToken::LCurly)) {
1902 // Eat "{" and mark the current place.
1903 const SMLoc consumedToken = consumeToken();
1904 // Distinguish {1to<NUM>} from {%k<NUM>}.
1905 if(getLexer().is(AsmToken::Integer)) {
1906 // Parse memory broadcasting ({1to<NUM>}).
1907 if (getLexer().getTok().getIntVal() != 1)
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001908 return TokError("Expected 1to<NUM> at this point");
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001909 Parser.Lex(); // Eat "1" of 1to8
1910 if (!getLexer().is(AsmToken::Identifier) ||
1911 !getLexer().getTok().getIdentifier().startswith("to"))
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001912 return TokError("Expected 1to<NUM> at this point");
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001913 // Recognize only reasonable suffixes.
1914 const char *BroadcastPrimitive =
1915 StringSwitch<const char*>(getLexer().getTok().getIdentifier())
Robert Khasanovbfa01312014-07-21 14:54:21 +00001916 .Case("to2", "{1to2}")
1917 .Case("to4", "{1to4}")
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001918 .Case("to8", "{1to8}")
1919 .Case("to16", "{1to16}")
Craig Topper062a2ba2014-04-25 05:30:21 +00001920 .Default(nullptr);
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001921 if (!BroadcastPrimitive)
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001922 return TokError("Invalid memory broadcast primitive.");
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001923 Parser.Lex(); // Eat "toN" of 1toN
1924 if (!getLexer().is(AsmToken::RCurly))
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001925 return TokError("Expected } at this point");
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001926 Parser.Lex(); // Eat "}"
1927 Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive,
1928 consumedToken));
1929 // No AVX512 specific primitives can pass
1930 // after memory broadcasting, so return.
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001931 return false;
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001932 } else {
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001933 // Parse either {k}{z}, {z}{k}, {k} or {z}
1934 // last one have no meaning, but GCC accepts it
1935 // Currently, we're just pass a '{' mark
1936 std::unique_ptr<X86Operand> Z;
1937 if (ParseZ(Z, consumedToken))
1938 return true;
1939 // Reaching here means that parsing of the allegadly '{z}' mark yielded
1940 // no errors.
1941 // Query for the need of further parsing for a {%k<NUM>} mark
1942 if (!Z || getLexer().is(AsmToken::LCurly)) {
Coby Tayree3bfb3652017-08-09 12:32:05 +00001943 SMLoc StartLoc = Z ? consumeToken() : consumedToken;
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001944 // Parse an op-mask register mark ({%k<NUM>}), which is now to be
1945 // expected
Coby Tayree3bfb3652017-08-09 12:32:05 +00001946 unsigned RegNo;
Coby Tayree799fa2c2017-08-13 12:03:00 +00001947 SMLoc RegLoc;
1948 if (!ParseRegister(RegNo, RegLoc, StartLoc) &&
Coby Tayree3bfb3652017-08-09 12:32:05 +00001949 X86MCRegisterClasses[X86::VK1RegClassID].contains(RegNo)) {
Coby Tayree799fa2c2017-08-13 12:03:00 +00001950 if (RegNo == X86::K0)
1951 return Error(RegLoc, "Register k0 can't be used as write mask");
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001952 if (!getLexer().is(AsmToken::RCurly))
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001953 return Error(getLexer().getLoc(), "Expected } at this point");
1954 Operands.push_back(X86Operand::CreateToken("{", StartLoc));
Haojian Wuc1cae0b2017-08-09 12:49:20 +00001955 Operands.push_back(
1956 X86Operand::CreateReg(RegNo, StartLoc, StartLoc));
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001957 Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
1958 } else
1959 return Error(getLexer().getLoc(),
1960 "Expected an op-mask register at this point");
1961 // {%k<NUM>} mark is found, inquire for {z}
1962 if (getLexer().is(AsmToken::LCurly) && !Z) {
1963 // Have we've found a parsing error, or found no (expected) {z} mark
1964 // - report an error
1965 if (ParseZ(Z, consumeToken()) || !Z)
Coby Tayree3bfb3652017-08-09 12:32:05 +00001966 return Error(getLexer().getLoc(),
1967 "Expected a {z} mark at this point");
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001968
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001969 }
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001970 // '{z}' on its own is meaningless, hence should be ignored.
1971 // on the contrary - have it been accompanied by a K register,
1972 // allow it.
1973 if (Z)
1974 Operands.push_back(std::move(Z));
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001975 }
1976 }
1977 }
1978 }
Michael Zuckerman1bee6342016-10-18 13:52:39 +00001979 return false;
Elena Demikhovskyc9657012014-02-20 06:34:39 +00001980}
1981
Chris Lattnerb9270732010-04-17 18:56:34 +00001982/// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
1983/// has already been parsed if present.
David Blaikie960ea3f2014-06-08 16:18:35 +00001984std::unique_ptr<X86Operand> X86AsmParser::ParseMemOperand(unsigned SegReg,
1985 SMLoc MemStart) {
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001986
Rafael Espindola961d4692014-11-11 05:18:41 +00001987 MCAsmParser &Parser = getParser();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00001988 // We have to disambiguate a parenthesized expression "(4+5)" from the start
1989 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
Chris Lattner807a3bc2010-01-24 01:07:33 +00001990 // only way to do this without lookahead is to eat the '(' and see what is
1991 // after it.
Jim Grosbach13760bd2015-05-30 01:25:56 +00001992 const MCExpr *Disp = MCConstantExpr::create(0, getParser().getContext());
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00001993 if (getLexer().isNot(AsmToken::LParen)) {
Chris Lattnere17df0b2010-01-15 19:39:23 +00001994 SMLoc ExprEnd;
Craig Topper062a2ba2014-04-25 05:30:21 +00001995 if (getParser().parseExpression(Disp, ExprEnd)) return nullptr;
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001996
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00001997 // After parsing the base expression we could either have a parenthesized
1998 // memory address or not. If not, return now. If so, eat the (.
1999 if (getLexer().isNot(AsmToken::LParen)) {
Daniel Dunbara4fc8d92009-07-31 22:22:54 +00002000 // Unless we have a segment register, treat this as an immediate.
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002001 if (SegReg == 0)
Craig Topper055845f2015-01-02 07:02:25 +00002002 return X86Operand::CreateMem(getPointerWidth(), Disp, MemStart, ExprEnd);
2003 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
2004 MemStart, ExprEnd);
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002005 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002006
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002007 // Eat the '('.
Sean Callanana83fd7d2010-01-19 20:27:46 +00002008 Parser.Lex();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002009 } else {
2010 // Okay, we have a '('. We don't know if this is an expression or not, but
2011 // so we have to eat the ( to see beyond it.
Sean Callanan936b0d32010-01-19 21:44:56 +00002012 SMLoc LParenLoc = Parser.getTok().getLoc();
Sean Callanana83fd7d2010-01-19 20:27:46 +00002013 Parser.Lex(); // Eat the '('.
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002014
Kevin Enderby7d912182009-09-03 17:15:07 +00002015 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002016 // Nothing to do here, fall into the code below with the '(' part of the
2017 // memory operand consumed.
2018 } else {
Chris Lattner528d00b2010-01-15 19:28:38 +00002019 SMLoc ExprEnd;
Konstantin Belochapka34777112017-09-22 23:37:48 +00002020 getLexer().UnLex(AsmToken(AsmToken::LParen, "("));
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002021
Konstantin Belochapka34777112017-09-22 23:37:48 +00002022 // It must be either an parenthesized expression, or an expression that
2023 // begins from a parenthesized expression, parse it now. Example: (1+2) or
2024 // (1+2)+3
2025 if (getParser().parseExpression(Disp, ExprEnd))
Craig Topper062a2ba2014-04-25 05:30:21 +00002026 return nullptr;
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002027
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002028 // After parsing the base expression we could either have a parenthesized
2029 // memory address or not. If not, return now. If so, eat the (.
2030 if (getLexer().isNot(AsmToken::LParen)) {
Daniel Dunbara4fc8d92009-07-31 22:22:54 +00002031 // Unless we have a segment register, treat this as an immediate.
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002032 if (SegReg == 0)
Craig Topper055845f2015-01-02 07:02:25 +00002033 return X86Operand::CreateMem(getPointerWidth(), Disp, LParenLoc,
2034 ExprEnd);
2035 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
2036 MemStart, ExprEnd);
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002037 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002038
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002039 // Eat the '('.
Sean Callanana83fd7d2010-01-19 20:27:46 +00002040 Parser.Lex();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002041 }
2042 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002043
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002044 // If we reached here, then we just ate the ( of the memory operand. Process
2045 // the rest of the memory operand.
Daniel Dunbar3ebf8482009-07-31 20:53:16 +00002046 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
David Woodhouse6dbda442014-01-08 12:58:28 +00002047 SMLoc IndexLoc, BaseLoc;
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002048
Chris Lattner0c2538f2010-01-15 18:51:29 +00002049 if (getLexer().is(AsmToken::Percent)) {
Benjamin Kramer1930b002011-10-16 12:10:27 +00002050 SMLoc StartLoc, EndLoc;
David Woodhouse6dbda442014-01-08 12:58:28 +00002051 BaseLoc = Parser.getTok().getLoc();
Craig Topper062a2ba2014-04-25 05:30:21 +00002052 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return nullptr;
Bruno Cardoso Lopes306a1f92010-07-24 00:06:39 +00002053 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
Benjamin Kramer1930b002011-10-16 12:10:27 +00002054 Error(StartLoc, "eiz and riz can only be used as index registers",
2055 SMRange(StartLoc, EndLoc));
Craig Topper062a2ba2014-04-25 05:30:21 +00002056 return nullptr;
Bruno Cardoso Lopes306a1f92010-07-24 00:06:39 +00002057 }
Chris Lattner0c2538f2010-01-15 18:51:29 +00002058 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002059
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002060 if (getLexer().is(AsmToken::Comma)) {
Sean Callanana83fd7d2010-01-19 20:27:46 +00002061 Parser.Lex(); // Eat the comma.
Kevin Enderbyfb3110b2012-03-12 21:32:09 +00002062 IndexLoc = Parser.getTok().getLoc();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002063
2064 // Following the comma we should have either an index register, or a scale
2065 // value. We don't support the later form, but we want to parse it
2066 // correctly.
2067 //
2068 // Not that even though it would be completely consistent to support syntax
Bruno Cardoso Lopes306a1f92010-07-24 00:06:39 +00002069 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
Kevin Enderby7d912182009-09-03 17:15:07 +00002070 if (getLexer().is(AsmToken::Percent)) {
Chris Lattner0c2538f2010-01-15 18:51:29 +00002071 SMLoc L;
Douglas Katzman0411e862016-10-05 15:23:35 +00002072 if (ParseRegister(IndexReg, L, L))
2073 return nullptr;
2074 if (BaseReg == X86::RIP) {
2075 Error(IndexLoc, "%rip as base register can not have an index register");
2076 return nullptr;
2077 }
2078 if (IndexReg == X86::RIP) {
2079 Error(IndexLoc, "%rip is not allowed as an index register");
2080 return nullptr;
2081 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002082
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002083 if (getLexer().isNot(AsmToken::RParen)) {
2084 // Parse the scale amount:
2085 // ::= ',' [scale-expression]
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002086 if (getLexer().isNot(AsmToken::Comma)) {
Sean Callanan936b0d32010-01-19 21:44:56 +00002087 Error(Parser.getTok().getLoc(),
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002088 "expected comma in scale expression");
Craig Topper062a2ba2014-04-25 05:30:21 +00002089 return nullptr;
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002090 }
Sean Callanana83fd7d2010-01-19 20:27:46 +00002091 Parser.Lex(); // Eat the comma.
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002092
2093 if (getLexer().isNot(AsmToken::RParen)) {
Sean Callanan936b0d32010-01-19 21:44:56 +00002094 SMLoc Loc = Parser.getTok().getLoc();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002095
2096 int64_t ScaleVal;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00002097 if (getParser().parseAbsoluteExpression(ScaleVal)){
Kevin Enderbydeed5aa2012-03-09 22:24:10 +00002098 Error(Loc, "expected scale expression");
Craig Topper062a2ba2014-04-25 05:30:21 +00002099 return nullptr;
Craig Topper6bf3ed42012-07-18 04:59:16 +00002100 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002101
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002102 // Validate the scale amount.
NAKAMURA Takumi0a7d0ad2015-09-22 11:15:07 +00002103 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
David Woodhouse6dbda442014-01-08 12:58:28 +00002104 ScaleVal != 1) {
2105 Error(Loc, "scale factor in 16-bit address must be 1");
Craig Topper062a2ba2014-04-25 05:30:21 +00002106 return nullptr;
NAKAMURA Takumi0a7d0ad2015-09-22 11:15:07 +00002107 }
2108 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 &&
2109 ScaleVal != 8) {
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002110 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
Craig Topper062a2ba2014-04-25 05:30:21 +00002111 return nullptr;
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002112 }
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002113 Scale = (unsigned)ScaleVal;
2114 }
2115 }
2116 } else if (getLexer().isNot(AsmToken::RParen)) {
Daniel Dunbar94b84a12010-08-24 19:13:38 +00002117 // A scale amount without an index is ignored.
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002118 // index.
Sean Callanan936b0d32010-01-19 21:44:56 +00002119 SMLoc Loc = Parser.getTok().getLoc();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002120
2121 int64_t Value;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00002122 if (getParser().parseAbsoluteExpression(Value))
Craig Topper062a2ba2014-04-25 05:30:21 +00002123 return nullptr;
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002124
Daniel Dunbar94b84a12010-08-24 19:13:38 +00002125 if (Value != 1)
2126 Warning(Loc, "scale factor without index register is ignored");
2127 Scale = 1;
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002128 }
2129 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002130
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002131 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002132 if (getLexer().isNot(AsmToken::RParen)) {
Sean Callanan936b0d32010-01-19 21:44:56 +00002133 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
Craig Topper062a2ba2014-04-25 05:30:21 +00002134 return nullptr;
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002135 }
Jordan Rosee8f1eae2013-01-07 19:00:49 +00002136 SMLoc MemEnd = Parser.getTok().getEndLoc();
Sean Callanana83fd7d2010-01-19 20:27:46 +00002137 Parser.Lex(); // Eat the ')'.
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002138
David Woodhouse6dbda442014-01-08 12:58:28 +00002139 // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
2140 // and then only in non-64-bit modes. Except for DX, which is a special case
2141 // because an unofficial form of in/out instructions uses it.
2142 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2143 (is64BitMode() || (BaseReg != X86::BX && BaseReg != X86::BP &&
2144 BaseReg != X86::SI && BaseReg != X86::DI)) &&
2145 BaseReg != X86::DX) {
2146 Error(BaseLoc, "invalid 16-bit base register");
Craig Topper062a2ba2014-04-25 05:30:21 +00002147 return nullptr;
David Woodhouse6dbda442014-01-08 12:58:28 +00002148 }
2149 if (BaseReg == 0 &&
2150 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
2151 Error(IndexLoc, "16-bit memory operand may not include only index register");
Craig Topper062a2ba2014-04-25 05:30:21 +00002152 return nullptr;
David Woodhouse6dbda442014-01-08 12:58:28 +00002153 }
Kevin Enderbybc570f22014-01-23 22:34:42 +00002154
2155 StringRef ErrMsg;
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +00002156 if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, ErrMsg)) {
Kevin Enderbybc570f22014-01-23 22:34:42 +00002157 Error(BaseLoc, ErrMsg);
Craig Topper062a2ba2014-04-25 05:30:21 +00002158 return nullptr;
Kevin Enderbyfb3110b2012-03-12 21:32:09 +00002159 }
2160
Reid Klecknerb7e2f602014-07-31 23:26:35 +00002161 if (SegReg || BaseReg || IndexReg)
Craig Topper055845f2015-01-02 07:02:25 +00002162 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
2163 IndexReg, Scale, MemStart, MemEnd);
2164 return X86Operand::CreateMem(getPointerWidth(), Disp, MemStart, MemEnd);
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002165}
2166
David Blaikie960ea3f2014-06-08 16:18:35 +00002167bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
2168 SMLoc NameLoc, OperandVector &Operands) {
Rafael Espindola961d4692014-11-11 05:18:41 +00002169 MCAsmParser &Parser = getParser();
Chad Rosierf0e87202012-10-25 20:41:34 +00002170 InstInfo = &Info;
Chris Lattner2cb092d2010-10-30 19:23:13 +00002171 StringRef PatchedName = Name;
Daniel Dunbar0e767d72010-05-25 19:49:32 +00002172
Coby Tayree48d67cd2017-07-30 11:12:47 +00002173 if ((Name.equals("jmp") || Name.equals("jc") || Name.equals("jz")) &&
2174 isParsingIntelSyntax() && isParsingInlineAsm()) {
Michael Zuckerman174d2e72016-10-14 08:09:40 +00002175 StringRef NextTok = Parser.getTok().getString();
2176 if (NextTok == "short") {
2177 SMLoc NameEndLoc =
2178 NameLoc.getFromPointer(NameLoc.getPointer() + Name.size());
2179 // Eat the short keyword
2180 Parser.Lex();
2181 // MS ignores the short keyword, it determines the jmp type based
2182 // on the distance of the label
2183 InstInfo->AsmRewrites->emplace_back(AOK_Skip, NameEndLoc,
2184 NextTok.size() + 1);
2185 }
2186 }
2187
Chris Lattner7e8a99b2010-11-28 20:23:50 +00002188 // FIXME: Hack to recognize setneb as setne.
2189 if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
2190 PatchedName != "setb" && PatchedName != "setnb")
2191 PatchedName = PatchedName.substr(0, Name.size()-1);
Chad Rosier51afe632012-06-27 22:34:28 +00002192
Daniel Dunbar0e767d72010-05-25 19:49:32 +00002193 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
Bruno Cardoso Lopes3183dd52010-06-23 21:10:57 +00002194 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
Daniel Dunbar0e767d72010-05-25 19:49:32 +00002195 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
2196 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
Craig Toppera0a603e2012-03-29 07:11:23 +00002197 bool IsVCMP = PatchedName[0] == 'v';
Craig Topper78c424d2015-02-15 07:13:48 +00002198 unsigned CCIdx = IsVCMP ? 4 : 3;
2199 unsigned ComparisonCode = StringSwitch<unsigned>(
2200 PatchedName.slice(CCIdx, PatchedName.size() - 2))
Craig Toppera0a603e2012-03-29 07:11:23 +00002201 .Case("eq", 0x00)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002202 .Case("eq_oq", 0x00)
Craig Toppera0a603e2012-03-29 07:11:23 +00002203 .Case("lt", 0x01)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002204 .Case("lt_os", 0x01)
Craig Toppera0a603e2012-03-29 07:11:23 +00002205 .Case("le", 0x02)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002206 .Case("le_os", 0x02)
Craig Toppera0a603e2012-03-29 07:11:23 +00002207 .Case("unord", 0x03)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002208 .Case("unord_q", 0x03)
Craig Toppera0a603e2012-03-29 07:11:23 +00002209 .Case("neq", 0x04)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002210 .Case("neq_uq", 0x04)
Craig Toppera0a603e2012-03-29 07:11:23 +00002211 .Case("nlt", 0x05)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002212 .Case("nlt_us", 0x05)
Craig Toppera0a603e2012-03-29 07:11:23 +00002213 .Case("nle", 0x06)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002214 .Case("nle_us", 0x06)
Craig Toppera0a603e2012-03-29 07:11:23 +00002215 .Case("ord", 0x07)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002216 .Case("ord_q", 0x07)
Craig Toppera0a603e2012-03-29 07:11:23 +00002217 /* AVX only from here */
2218 .Case("eq_uq", 0x08)
2219 .Case("nge", 0x09)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002220 .Case("nge_us", 0x09)
Bruno Cardoso Lopes6c614512010-07-07 22:24:03 +00002221 .Case("ngt", 0x0A)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002222 .Case("ngt_us", 0x0A)
Bruno Cardoso Lopes6c614512010-07-07 22:24:03 +00002223 .Case("false", 0x0B)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002224 .Case("false_oq", 0x0B)
Bruno Cardoso Lopes6c614512010-07-07 22:24:03 +00002225 .Case("neq_oq", 0x0C)
2226 .Case("ge", 0x0D)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002227 .Case("ge_os", 0x0D)
Bruno Cardoso Lopes6c614512010-07-07 22:24:03 +00002228 .Case("gt", 0x0E)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002229 .Case("gt_os", 0x0E)
Bruno Cardoso Lopes6c614512010-07-07 22:24:03 +00002230 .Case("true", 0x0F)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002231 .Case("true_uq", 0x0F)
Bruno Cardoso Lopes6c614512010-07-07 22:24:03 +00002232 .Case("eq_os", 0x10)
2233 .Case("lt_oq", 0x11)
2234 .Case("le_oq", 0x12)
2235 .Case("unord_s", 0x13)
2236 .Case("neq_us", 0x14)
2237 .Case("nlt_uq", 0x15)
2238 .Case("nle_uq", 0x16)
2239 .Case("ord_s", 0x17)
2240 .Case("eq_us", 0x18)
2241 .Case("nge_uq", 0x19)
2242 .Case("ngt_uq", 0x1A)
2243 .Case("false_os", 0x1B)
2244 .Case("neq_os", 0x1C)
2245 .Case("ge_oq", 0x1D)
2246 .Case("gt_oq", 0x1E)
2247 .Case("true_us", 0x1F)
Daniel Dunbar0e767d72010-05-25 19:49:32 +00002248 .Default(~0U);
Craig Topper78c424d2015-02-15 07:13:48 +00002249 if (ComparisonCode != ~0U && (IsVCMP || ComparisonCode < 8)) {
Craig Topper43860832015-02-14 21:54:03 +00002250
Craig Topper78c424d2015-02-15 07:13:48 +00002251 Operands.push_back(X86Operand::CreateToken(PatchedName.slice(0, CCIdx),
Craig Topper43860832015-02-14 21:54:03 +00002252 NameLoc));
2253
Jim Grosbach13760bd2015-05-30 01:25:56 +00002254 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
Craig Topper43860832015-02-14 21:54:03 +00002255 getParser().getContext());
2256 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2257
2258 PatchedName = PatchedName.substr(PatchedName.size() - 2);
Daniel Dunbar0e767d72010-05-25 19:49:32 +00002259 }
2260 }
Bruno Cardoso Lopesea0e05a2010-07-23 18:41:12 +00002261
Craig Topper78c424d2015-02-15 07:13:48 +00002262 // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}.
2263 if (PatchedName.startswith("vpcmp") &&
2264 (PatchedName.endswith("b") || PatchedName.endswith("w") ||
2265 PatchedName.endswith("d") || PatchedName.endswith("q"))) {
2266 unsigned CCIdx = PatchedName.drop_back().back() == 'u' ? 2 : 1;
2267 unsigned ComparisonCode = StringSwitch<unsigned>(
2268 PatchedName.slice(5, PatchedName.size() - CCIdx))
2269 .Case("eq", 0x0) // Only allowed on unsigned. Checked below.
2270 .Case("lt", 0x1)
2271 .Case("le", 0x2)
2272 //.Case("false", 0x3) // Not a documented alias.
2273 .Case("neq", 0x4)
2274 .Case("nlt", 0x5)
2275 .Case("nle", 0x6)
2276 //.Case("true", 0x7) // Not a documented alias.
2277 .Default(~0U);
2278 if (ComparisonCode != ~0U && (ComparisonCode != 0 || CCIdx == 2)) {
2279 Operands.push_back(X86Operand::CreateToken("vpcmp", NameLoc));
2280
Jim Grosbach13760bd2015-05-30 01:25:56 +00002281 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
Craig Topper78c424d2015-02-15 07:13:48 +00002282 getParser().getContext());
2283 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2284
2285 PatchedName = PatchedName.substr(PatchedName.size() - CCIdx);
2286 }
2287 }
2288
Craig Topper916708f2015-02-13 07:42:25 +00002289 // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}.
2290 if (PatchedName.startswith("vpcom") &&
2291 (PatchedName.endswith("b") || PatchedName.endswith("w") ||
2292 PatchedName.endswith("d") || PatchedName.endswith("q"))) {
Craig Topper78c424d2015-02-15 07:13:48 +00002293 unsigned CCIdx = PatchedName.drop_back().back() == 'u' ? 2 : 1;
2294 unsigned ComparisonCode = StringSwitch<unsigned>(
2295 PatchedName.slice(5, PatchedName.size() - CCIdx))
Craig Topper916708f2015-02-13 07:42:25 +00002296 .Case("lt", 0x0)
2297 .Case("le", 0x1)
2298 .Case("gt", 0x2)
2299 .Case("ge", 0x3)
2300 .Case("eq", 0x4)
2301 .Case("neq", 0x5)
2302 .Case("false", 0x6)
2303 .Case("true", 0x7)
2304 .Default(~0U);
Craig Topper78c424d2015-02-15 07:13:48 +00002305 if (ComparisonCode != ~0U) {
Craig Topper916708f2015-02-13 07:42:25 +00002306 Operands.push_back(X86Operand::CreateToken("vpcom", NameLoc));
2307
Jim Grosbach13760bd2015-05-30 01:25:56 +00002308 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
Craig Topper916708f2015-02-13 07:42:25 +00002309 getParser().getContext());
2310 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2311
Craig Topper78c424d2015-02-15 07:13:48 +00002312 PatchedName = PatchedName.substr(PatchedName.size() - CCIdx);
Craig Topper916708f2015-02-13 07:42:25 +00002313 }
2314 }
2315
Daniel Dunbar3e0c9792010-02-10 21:19:28 +00002316 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002317
Chris Lattner086a83a2010-09-08 05:17:37 +00002318 // Determine whether this is an instruction prefix.
Coby Tayreec54c5cb2017-08-21 07:50:15 +00002319 // FIXME:
Craig Topper0768bce2017-09-26 21:35:04 +00002320 // Enhance prefixes integrity robustness. for example, following forms
Coby Tayreec54c5cb2017-08-21 07:50:15 +00002321 // are currently tolerated:
2322 // repz repnz <insn> ; GAS errors for the use of two similar prefixes
2323 // lock addq %rax, %rbx ; Destination operand must be of memory type
2324 // xacquire <insn> ; xacquire must be accompanied by 'lock'
2325 bool isPrefix = StringSwitch<bool>(Name)
2326 .Cases("lock",
2327 "rep", "repe",
2328 "repz", "repne",
2329 "repnz", "rex64",
2330 "data32", "data16", true)
2331 .Cases("xacquire", "xrelease", true)
2332 .Cases("acquire", "release", isParsingIntelSyntax())
2333 .Default(false);
Michael J. Spencer530ce852010-10-09 11:00:50 +00002334
Marina Yatsina5f5de9f2016-03-07 18:11:16 +00002335 bool CurlyAsEndOfStatement = false;
Chris Lattner086a83a2010-09-08 05:17:37 +00002336 // This does the actual operand parsing. Don't parse any more if we have a
2337 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
2338 // just want to parse the "lock" as the first instruction and the "incl" as
2339 // the next one.
2340 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
Daniel Dunbar71527c12009-08-11 05:00:25 +00002341
2342 // Parse '*' modifier.
Alp Tokera5b88a52013-12-02 16:06:06 +00002343 if (getLexer().is(AsmToken::Star))
2344 Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
Daniel Dunbar71527c12009-08-11 05:00:25 +00002345
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002346 // Read the operands.
Kirill Bobyrev6afbaf02017-01-18 16:34:25 +00002347 while(1) {
David Blaikie960ea3f2014-06-08 16:18:35 +00002348 if (std::unique_ptr<X86Operand> Op = ParseOperand()) {
2349 Operands.push_back(std::move(Op));
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002350 if (HandleAVX512Operand(Operands, *Operands.back()))
Elena Demikhovsky89529742013-09-12 08:55:00 +00002351 return true;
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002352 } else {
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002353 return true;
Elena Demikhovsky89529742013-09-12 08:55:00 +00002354 }
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002355 // check for comma and eat it
2356 if (getLexer().is(AsmToken::Comma))
2357 Parser.Lex();
2358 else
2359 break;
2360 }
Elena Demikhovsky89529742013-09-12 08:55:00 +00002361
Hiroshi Inouee9dea6e2017-07-13 06:48:39 +00002362 // In MS inline asm curly braces mark the beginning/end of a block,
2363 // therefore they should be interepreted as end of statement
Marina Yatsina5f5de9f2016-03-07 18:11:16 +00002364 CurlyAsEndOfStatement =
2365 isParsingIntelSyntax() && isParsingInlineAsm() &&
2366 (getLexer().is(AsmToken::LCurly) || getLexer().is(AsmToken::RCurly));
2367 if (getLexer().isNot(AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
Nirav Dave2364748a2016-09-16 18:30:20 +00002368 return TokError("unexpected token in argument list");
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002369 }
Michael J. Spencer530ce852010-10-09 11:00:50 +00002370
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002371 // Consume the EndOfStatement or the prefix separator Slash
Elena Demikhovsky9f09b3e2014-02-20 07:00:10 +00002372 if (getLexer().is(AsmToken::EndOfStatement) ||
2373 (isPrefix && getLexer().is(AsmToken::Slash)))
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002374 Parser.Lex();
Marina Yatsina5f5de9f2016-03-07 18:11:16 +00002375 else if (CurlyAsEndOfStatement)
2376 // Add an actual EndOfStatement before the curly brace
2377 Info.AsmRewrites->emplace_back(AOK_EndOfStatement,
2378 getLexer().getTok().getLoc(), 0);
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002379
Michael Zuckermanfd3fe9e2015-11-12 16:58:51 +00002380 // This is for gas compatibility and cannot be done in td.
2381 // Adding "p" for some floating point with no argument.
2382 // For example: fsub --> fsubp
2383 bool IsFp =
2384 Name == "fsub" || Name == "fdiv" || Name == "fsubr" || Name == "fdivr";
2385 if (IsFp && Operands.size() == 1) {
2386 const char *Repl = StringSwitch<const char *>(Name)
2387 .Case("fsub", "fsubp")
2388 .Case("fdiv", "fdivp")
2389 .Case("fsubr", "fsubrp")
2390 .Case("fdivr", "fdivrp");
2391 static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
2392 }
2393
Nirav Davef45fd2b2016-08-08 18:01:04 +00002394 // Moving a 32 or 16 bit value into a segment register has the same
2395 // behavior. Modify such instructions to always take shorter form.
2396 if ((Name == "mov" || Name == "movw" || Name == "movl") &&
2397 (Operands.size() == 3)) {
2398 X86Operand &Op1 = (X86Operand &)*Operands[1];
2399 X86Operand &Op2 = (X86Operand &)*Operands[2];
2400 SMLoc Loc = Op1.getEndLoc();
2401 if (Op1.isReg() && Op2.isReg() &&
2402 X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(
2403 Op2.getReg()) &&
2404 (X86MCRegisterClasses[X86::GR16RegClassID].contains(Op1.getReg()) ||
2405 X86MCRegisterClasses[X86::GR32RegClassID].contains(Op1.getReg()))) {
2406 // Change instruction name to match new instruction.
2407 if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) {
2408 Name = is16BitMode() ? "movw" : "movl";
2409 Operands[0] = X86Operand::CreateToken(Name, NameLoc);
2410 }
2411 // Select the correct equivalent 16-/32-bit source register.
2412 unsigned Reg =
2413 getX86SubSuperRegisterOrZero(Op1.getReg(), is16BitMode() ? 16 : 32);
2414 Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc);
2415 }
2416 }
2417
Nirav Dave8e103802016-06-29 19:54:27 +00002418 // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
Chris Lattnerb6f8e822010-11-06 19:25:43 +00002419 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
2420 // documented form in various unofficial manuals, so a lot of code uses it.
Nirav Dave8e103802016-06-29 19:54:27 +00002421 if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
2422 Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
Chris Lattnerb6f8e822010-11-06 19:25:43 +00002423 Operands.size() == 3) {
David Blaikie960ea3f2014-06-08 16:18:35 +00002424 X86Operand &Op = (X86Operand &)*Operands.back();
Chris Lattnerb6f8e822010-11-06 19:25:43 +00002425 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2426 isa<MCConstantExpr>(Op.Mem.Disp) &&
2427 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2428 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2429 SMLoc Loc = Op.getEndLoc();
2430 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
Chris Lattnerb6f8e822010-11-06 19:25:43 +00002431 }
2432 }
Nirav Dave8e103802016-06-29 19:54:27 +00002433 // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
2434 if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
2435 Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
Joerg Sonnenbergerb7e635d2011-02-22 20:40:09 +00002436 Operands.size() == 3) {
David Blaikie960ea3f2014-06-08 16:18:35 +00002437 X86Operand &Op = (X86Operand &)*Operands[1];
Joerg Sonnenbergerb7e635d2011-02-22 20:40:09 +00002438 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2439 isa<MCConstantExpr>(Op.Mem.Disp) &&
2440 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2441 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2442 SMLoc Loc = Op.getEndLoc();
David Blaikie960ea3f2014-06-08 16:18:35 +00002443 Operands[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
Joerg Sonnenbergerb7e635d2011-02-22 20:40:09 +00002444 }
2445 }
David Woodhouse4ce66062014-01-22 15:08:55 +00002446
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002447 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 2> TmpOperands;
2448 bool HadVerifyError = false;
2449
David Woodhouse4ce66062014-01-22 15:08:55 +00002450 // Append default arguments to "ins[bwld]"
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002451 if (Name.startswith("ins") &&
2452 (Operands.size() == 1 || Operands.size() == 3) &&
2453 (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
2454 Name == "ins")) {
2455
2456 AddDefaultSrcDestOperands(TmpOperands,
Michael Kupersteinffcc7662015-07-23 10:23:48 +00002457 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
2458 DefaultMemDIOperand(NameLoc));
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002459 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
Joerg Sonnenberger3fbfcc02011-03-18 11:59:40 +00002460 }
2461
David Woodhousec472b812014-01-22 15:08:49 +00002462 // Append default arguments to "outs[bwld]"
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002463 if (Name.startswith("outs") &&
2464 (Operands.size() == 1 || Operands.size() == 3) &&
David Woodhousec472b812014-01-22 15:08:49 +00002465 (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002466 Name == "outsd" || Name == "outs")) {
2467 AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
Michael Kupersteinffcc7662015-07-23 10:23:48 +00002468 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002469 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
Joerg Sonnenberger3fbfcc02011-03-18 11:59:40 +00002470 }
2471
David Woodhouse2ef8d9c2014-01-22 15:08:08 +00002472 // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
2473 // values of $SIREG according to the mode. It would be nice if this
2474 // could be achieved with InstAlias in the tables.
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002475 if (Name.startswith("lods") &&
2476 (Operands.size() == 1 || Operands.size() == 2) &&
Joerg Sonnenberger3fbfcc02011-03-18 11:59:40 +00002477 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002478 Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
2479 TmpOperands.push_back(DefaultMemSIOperand(NameLoc));
2480 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2481 }
David Woodhouse2ef8d9c2014-01-22 15:08:08 +00002482
David Woodhouseb33c2ef2014-01-22 15:08:21 +00002483 // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
2484 // values of $DIREG according to the mode. It would be nice if this
2485 // could be achieved with InstAlias in the tables.
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002486 if (Name.startswith("stos") &&
2487 (Operands.size() == 1 || Operands.size() == 2) &&
Joerg Sonnenberger3fbfcc02011-03-18 11:59:40 +00002488 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002489 Name == "stosl" || Name == "stosd" || Name == "stosq")) {
2490 TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
2491 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2492 }
Joerg Sonnenberger3fbfcc02011-03-18 11:59:40 +00002493
David Woodhouse20fe4802014-01-22 15:08:27 +00002494 // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
2495 // values of $DIREG according to the mode. It would be nice if this
2496 // could be achieved with InstAlias in the tables.
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002497 if (Name.startswith("scas") &&
2498 (Operands.size() == 1 || Operands.size() == 2) &&
David Woodhouse20fe4802014-01-22 15:08:27 +00002499 (Name == "scas" || Name == "scasb" || Name == "scasw" ||
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002500 Name == "scasl" || Name == "scasd" || Name == "scasq")) {
2501 TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
2502 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2503 }
David Woodhouse20fe4802014-01-22 15:08:27 +00002504
David Woodhouse9bbf7ca2014-01-22 15:08:36 +00002505 // Add default SI and DI operands to "cmps[bwlq]".
2506 if (Name.startswith("cmps") &&
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002507 (Operands.size() == 1 || Operands.size() == 3) &&
David Woodhouse9bbf7ca2014-01-22 15:08:36 +00002508 (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
2509 Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002510 AddDefaultSrcDestOperands(TmpOperands, DefaultMemDIOperand(NameLoc),
2511 DefaultMemSIOperand(NameLoc));
2512 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
David Woodhouse9bbf7ca2014-01-22 15:08:36 +00002513 }
2514
David Woodhouse6f417de2014-01-22 15:08:42 +00002515 // Add default SI and DI operands to "movs[bwlq]".
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002516 if (((Name.startswith("movs") &&
2517 (Name == "movs" || Name == "movsb" || Name == "movsw" ||
2518 Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
2519 (Name.startswith("smov") &&
2520 (Name == "smov" || Name == "smovb" || Name == "smovw" ||
2521 Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
2522 (Operands.size() == 1 || Operands.size() == 3)) {
Coby Tayree94ddbb42016-11-21 15:50:56 +00002523 if (Name == "movsd" && Operands.size() == 1 && !isParsingIntelSyntax())
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002524 Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
2525 AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
2526 DefaultMemDIOperand(NameLoc));
2527 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2528 }
2529
2530 // Check if we encountered an error for one the string insturctions
2531 if (HadVerifyError) {
2532 return HadVerifyError;
David Woodhouse6f417de2014-01-22 15:08:42 +00002533 }
2534
Chris Lattner4bd21712010-09-15 04:33:27 +00002535 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
Chris Lattner30561ab2010-09-11 16:32:12 +00002536 // "shift <op>".
Daniel Dunbar18fc3442010-03-13 00:47:29 +00002537 if ((Name.startswith("shr") || Name.startswith("sar") ||
Chris Lattner64f91b92010-11-06 21:23:40 +00002538 Name.startswith("shl") || Name.startswith("sal") ||
2539 Name.startswith("rcl") || Name.startswith("rcr") ||
2540 Name.startswith("rol") || Name.startswith("ror")) &&
Chris Lattner4cfbcdc2010-09-06 18:32:06 +00002541 Operands.size() == 3) {
Devang Patel9a9bb5c2012-01-30 20:02:42 +00002542 if (isParsingIntelSyntax()) {
Devang Patela410ed32012-01-24 21:43:36 +00002543 // Intel syntax
David Blaikie960ea3f2014-06-08 16:18:35 +00002544 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[2]);
2545 if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) &&
2546 cast<MCConstantExpr>(Op1.getImm())->getValue() == 1)
Craig Topper6bf3ed42012-07-18 04:59:16 +00002547 Operands.pop_back();
Devang Patela410ed32012-01-24 21:43:36 +00002548 } else {
David Blaikie960ea3f2014-06-08 16:18:35 +00002549 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2550 if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) &&
2551 cast<MCConstantExpr>(Op1.getImm())->getValue() == 1)
Craig Topper6bf3ed42012-07-18 04:59:16 +00002552 Operands.erase(Operands.begin() + 1);
Chris Lattner4cfbcdc2010-09-06 18:32:06 +00002553 }
Daniel Dunbarfbd12cc2010-03-20 22:36:38 +00002554 }
Chad Rosier51afe632012-06-27 22:34:28 +00002555
Chris Lattnerfc4fe002011-04-09 19:41:05 +00002556 // Transforms "int $3" into "int3" as a size optimization. We can't write an
2557 // instalias with an immediate operand yet.
2558 if (Name == "int" && Operands.size() == 2) {
David Blaikie960ea3f2014-06-08 16:18:35 +00002559 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
Duncan P. N. Exon Smithd5313222015-07-23 19:27:07 +00002560 if (Op1.isImm())
2561 if (auto *CE = dyn_cast<MCConstantExpr>(Op1.getImm()))
2562 if (CE->getValue() == 3) {
2563 Operands.erase(Operands.begin() + 1);
2564 static_cast<X86Operand &>(*Operands[0]).setTokenValue("int3");
2565 }
Chris Lattnerfc4fe002011-04-09 19:41:05 +00002566 }
Michael J. Spencer530ce852010-10-09 11:00:50 +00002567
Marina Yatsinad9658d12016-01-19 16:35:38 +00002568 // Transforms "xlat mem8" into "xlatb"
2569 if ((Name == "xlat" || Name == "xlatb") && Operands.size() == 2) {
2570 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2571 if (Op1.isMem8()) {
2572 Warning(Op1.getStartLoc(), "memory operand is only for determining the "
2573 "size, (R|E)BX will be used for the location");
2574 Operands.pop_back();
2575 static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb");
2576 }
2577 }
2578
Chris Lattnerf29c0b62010-01-14 22:21:20 +00002579 return false;
Daniel Dunbar3c2a8932009-07-20 18:55:04 +00002580}
2581
David Blaikie960ea3f2014-06-08 16:18:35 +00002582bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
Aaron Ballmana81264b2016-05-23 15:52:59 +00002583 return false;
Devang Patelde47cce2012-01-18 22:42:29 +00002584}
2585
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002586static const char *getSubtargetFeatureName(uint64_t Val);
Evgeniy Stepanov49e26252014-03-14 08:58:04 +00002587
David Blaikie960ea3f2014-06-08 16:18:35 +00002588void X86AsmParser::EmitInstruction(MCInst &Inst, OperandVector &Operands,
2589 MCStreamer &Out) {
Evgeniy Stepanov77ad8662014-07-31 09:11:04 +00002590 Instrumentation->InstrumentAndEmitInstruction(Inst, Operands, getContext(),
2591 MII, Out);
Evgeniy Stepanov49e26252014-03-14 08:58:04 +00002592}
2593
David Blaikie960ea3f2014-06-08 16:18:35 +00002594bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2595 OperandVector &Operands,
Tim Northover26bb14e2014-08-18 11:49:42 +00002596 MCStreamer &Out, uint64_t &ErrorInfo,
David Blaikie960ea3f2014-06-08 16:18:35 +00002597 bool MatchingInlineAsm) {
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002598 if (isParsingIntelSyntax())
2599 return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002600 MatchingInlineAsm);
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002601 return MatchAndEmitATTInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002602 MatchingInlineAsm);
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002603}
Daniel Dunbar2ecc3bb2010-08-12 00:55:38 +00002604
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002605void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
2606 OperandVector &Operands, MCStreamer &Out,
2607 bool MatchingInlineAsm) {
Chris Lattnera63292a2010-09-29 01:50:45 +00002608 // FIXME: This should be replaced with a real .td file alias mechanism.
Chad Rosier3b1336c2012-08-28 23:57:47 +00002609 // Also, MatchInstructionImpl should actually *do* the EmitInstruction
Chris Lattner4869d342010-11-06 19:57:21 +00002610 // call.
Reid Klecknerb1f2d2f2014-07-31 00:07:33 +00002611 const char *Repl = StringSwitch<const char *>(Op.getToken())
2612 .Case("finit", "fninit")
2613 .Case("fsave", "fnsave")
2614 .Case("fstcw", "fnstcw")
2615 .Case("fstcww", "fnstcw")
2616 .Case("fstenv", "fnstenv")
2617 .Case("fstsw", "fnstsw")
2618 .Case("fstsww", "fnstsw")
2619 .Case("fclex", "fnclex")
2620 .Default(nullptr);
2621 if (Repl) {
Chris Lattnera63292a2010-09-29 01:50:45 +00002622 MCInst Inst;
2623 Inst.setOpcode(X86::WAIT);
Jim Grosbach8f28dbd2012-01-27 00:51:27 +00002624 Inst.setLoc(IDLoc);
Chad Rosier4453e842012-10-12 23:09:25 +00002625 if (!MatchingInlineAsm)
Evgeniy Stepanov49e26252014-03-14 08:58:04 +00002626 EmitInstruction(Inst, Operands, Out);
Chris Lattneradc0dbe2010-09-30 16:39:29 +00002627 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
Chris Lattnera63292a2010-09-29 01:50:45 +00002628 }
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002629}
2630
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002631bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo,
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002632 bool MatchingInlineAsm) {
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002633 assert(ErrorInfo && "Unknown missing feature!");
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002634 SmallString<126> Msg;
2635 raw_svector_ostream OS(Msg);
2636 OS << "instruction requires:";
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002637 uint64_t Mask = 1;
2638 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2639 if (ErrorInfo & Mask)
2640 OS << ' ' << getSubtargetFeatureName(ErrorInfo & Mask);
2641 Mask <<= 1;
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002642 }
Nirav Dave2364748a2016-09-16 18:30:20 +00002643 return Error(IDLoc, OS.str(), SMRange(), MatchingInlineAsm);
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002644}
2645
2646bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
2647 OperandVector &Operands,
2648 MCStreamer &Out,
2649 uint64_t &ErrorInfo,
2650 bool MatchingInlineAsm) {
2651 assert(!Operands.empty() && "Unexpect empty operand list!");
2652 X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
2653 assert(Op.isToken() && "Leading operand should always be a mnemonic!");
Nirav Dave2364748a2016-09-16 18:30:20 +00002654 SMRange EmptyRange = None;
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002655
2656 // First, handle aliases that expand to multiple instructions.
2657 MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
Michael J. Spencer530ce852010-10-09 11:00:50 +00002658
Chris Lattner628fbec2010-09-06 21:54:15 +00002659 bool WasOriginallyInvalidOperand = false;
Chris Lattnerb44fd242010-09-29 01:42:58 +00002660 MCInst Inst;
Michael J. Spencer530ce852010-10-09 11:00:50 +00002661
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002662 // First, try a direct match.
Nirav Dave6477ce22016-09-26 19:33:36 +00002663 switch (MatchInstruction(Operands, Inst, ErrorInfo, MatchingInlineAsm,
2664 isParsingIntelSyntax())) {
Craig Topper589ceee2015-01-03 08:16:34 +00002665 default: llvm_unreachable("Unexpected match result!");
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002666 case Match_Success:
Devang Patelde47cce2012-01-18 22:42:29 +00002667 // Some instructions need post-processing to, for example, tweak which
2668 // encoding is selected. Loop on it while changes happen so the
Chad Rosier51afe632012-06-27 22:34:28 +00002669 // individual transformations can chain off each other.
Chad Rosier4453e842012-10-12 23:09:25 +00002670 if (!MatchingInlineAsm)
Chad Rosierf4e35dc2012-10-01 23:45:51 +00002671 while (processInstruction(Inst, Operands))
2672 ;
Devang Patelde47cce2012-01-18 22:42:29 +00002673
Jim Grosbach8f28dbd2012-01-27 00:51:27 +00002674 Inst.setLoc(IDLoc);
Chad Rosier4453e842012-10-12 23:09:25 +00002675 if (!MatchingInlineAsm)
Evgeniy Stepanov49e26252014-03-14 08:58:04 +00002676 EmitInstruction(Inst, Operands, Out);
Chad Rosierf4e35dc2012-10-01 23:45:51 +00002677 Opcode = Inst.getOpcode();
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002678 return false;
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002679 case Match_MissingFeature:
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002680 return ErrorMissingFeature(IDLoc, ErrorInfo, MatchingInlineAsm);
Chris Lattner628fbec2010-09-06 21:54:15 +00002681 case Match_InvalidOperand:
2682 WasOriginallyInvalidOperand = true;
2683 break;
2684 case Match_MnemonicFail:
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002685 break;
2686 }
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002687
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002688 // FIXME: Ideally, we would only attempt suffix matches for things which are
2689 // valid prefixes, and we could just infer the right unambiguous
2690 // type. However, that requires substantially more matcher support than the
2691 // following hack.
Michael J. Spencer530ce852010-10-09 11:00:50 +00002692
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002693 // Change the operand to point to a temporary token.
David Blaikie960ea3f2014-06-08 16:18:35 +00002694 StringRef Base = Op.getToken();
Daniel Dunbar2ecc3bb2010-08-12 00:55:38 +00002695 SmallString<16> Tmp;
2696 Tmp += Base;
2697 Tmp += ' ';
Yaron Keren075759a2015-03-30 15:42:36 +00002698 Op.setTokenValue(Tmp);
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002699
Chris Lattnerfab94132010-11-06 18:28:02 +00002700 // If this instruction starts with an 'f', then it is a floating point stack
2701 // instruction. These come in up to three forms for 32-bit, 64-bit, and
2702 // 80-bit floating point, which use the suffixes s,l,t respectively.
2703 //
2704 // Otherwise, we assume that this may be an integer instruction, which comes
2705 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
2706 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
Chad Rosier51afe632012-06-27 22:34:28 +00002707
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002708 // Check for the various suffix matches.
Tim Northover26bb14e2014-08-18 11:49:42 +00002709 uint64_t ErrorInfoIgnore;
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002710 uint64_t ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002711 unsigned Match[4];
Chad Rosier51afe632012-06-27 22:34:28 +00002712
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002713 for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
2714 Tmp.back() = Suffixes[I];
Nirav Dave6477ce22016-09-26 19:33:36 +00002715 Match[I] = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
2716 MatchingInlineAsm, isParsingIntelSyntax());
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002717 // If this returned as a missing feature failure, remember that.
2718 if (Match[I] == Match_MissingFeature)
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002719 ErrorInfoMissingFeature = ErrorInfoIgnore;
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002720 }
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002721
2722 // Restore the old token.
David Blaikie960ea3f2014-06-08 16:18:35 +00002723 Op.setTokenValue(Base);
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002724
2725 // If exactly one matched, then we treat that as a successful match (and the
2726 // instruction will already have been filled in correctly, since the failing
2727 // matches won't have modified it).
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002728 unsigned NumSuccessfulMatches =
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002729 std::count(std::begin(Match), std::end(Match), Match_Success);
Chris Lattnerb44fd242010-09-29 01:42:58 +00002730 if (NumSuccessfulMatches == 1) {
Jim Grosbach8f28dbd2012-01-27 00:51:27 +00002731 Inst.setLoc(IDLoc);
Chad Rosier4453e842012-10-12 23:09:25 +00002732 if (!MatchingInlineAsm)
Evgeniy Stepanov49e26252014-03-14 08:58:04 +00002733 EmitInstruction(Inst, Operands, Out);
Chad Rosierf4e35dc2012-10-01 23:45:51 +00002734 Opcode = Inst.getOpcode();
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002735 return false;
Chris Lattnerb44fd242010-09-29 01:42:58 +00002736 }
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002737
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002738 // Otherwise, the match failed, try to produce a decent error message.
Daniel Dunbar2ecc3bb2010-08-12 00:55:38 +00002739
Daniel Dunbar7d7b4d12010-08-12 00:55:42 +00002740 // If we had multiple suffix matches, then identify this as an ambiguous
2741 // match.
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002742 if (NumSuccessfulMatches > 1) {
Daniel Dunbar7d7b4d12010-08-12 00:55:42 +00002743 char MatchChars[4];
2744 unsigned NumMatches = 0;
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002745 for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I)
2746 if (Match[I] == Match_Success)
2747 MatchChars[NumMatches++] = Suffixes[I];
Daniel Dunbar7d7b4d12010-08-12 00:55:42 +00002748
Alp Tokere69170a2014-06-26 22:52:05 +00002749 SmallString<126> Msg;
2750 raw_svector_ostream OS(Msg);
Daniel Dunbar7d7b4d12010-08-12 00:55:42 +00002751 OS << "ambiguous instructions require an explicit suffix (could be ";
2752 for (unsigned i = 0; i != NumMatches; ++i) {
2753 if (i != 0)
2754 OS << ", ";
2755 if (i + 1 == NumMatches)
2756 OS << "or ";
2757 OS << "'" << Base << MatchChars[i] << "'";
2758 }
2759 OS << ")";
Nirav Dave2364748a2016-09-16 18:30:20 +00002760 Error(IDLoc, OS.str(), EmptyRange, MatchingInlineAsm);
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002761 return true;
Daniel Dunbar7d7b4d12010-08-12 00:55:42 +00002762 }
Michael J. Spencer530ce852010-10-09 11:00:50 +00002763
Chris Lattner628fbec2010-09-06 21:54:15 +00002764 // Okay, we know that none of the variants matched successfully.
Michael J. Spencer530ce852010-10-09 11:00:50 +00002765
Chris Lattner628fbec2010-09-06 21:54:15 +00002766 // If all of the instructions reported an invalid mnemonic, then the original
2767 // mnemonic was invalid.
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002768 if (std::count(std::begin(Match), std::end(Match), Match_MnemonicFail) == 4) {
Chris Lattner339cc7b2010-09-06 22:11:18 +00002769 if (!WasOriginallyInvalidOperand) {
Benjamin Kramerd416bae2011-10-16 11:28:29 +00002770 return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
Nirav Dave2364748a2016-09-16 18:30:20 +00002771 Op.getLocRange(), MatchingInlineAsm);
Chris Lattner339cc7b2010-09-06 22:11:18 +00002772 }
2773
2774 // Recover location info for the operand if we know which was the problem.
Tim Northover26bb14e2014-08-18 11:49:42 +00002775 if (ErrorInfo != ~0ULL) {
Chad Rosier49963552012-10-13 00:26:04 +00002776 if (ErrorInfo >= Operands.size())
Nirav Dave2364748a2016-09-16 18:30:20 +00002777 return Error(IDLoc, "too few operands for instruction", EmptyRange,
2778 MatchingInlineAsm);
Michael J. Spencer530ce852010-10-09 11:00:50 +00002779
David Blaikie960ea3f2014-06-08 16:18:35 +00002780 X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
2781 if (Operand.getStartLoc().isValid()) {
2782 SMRange OperandRange = Operand.getLocRange();
2783 return Error(Operand.getStartLoc(), "invalid operand for instruction",
Chad Rosier4453e842012-10-12 23:09:25 +00002784 OperandRange, MatchingInlineAsm);
Chris Lattnera3a06812011-10-16 04:47:35 +00002785 }
Chris Lattner339cc7b2010-09-06 22:11:18 +00002786 }
2787
Nirav Dave2364748a2016-09-16 18:30:20 +00002788 return Error(IDLoc, "invalid operand for instruction", EmptyRange,
Chad Rosier4453e842012-10-12 23:09:25 +00002789 MatchingInlineAsm);
Chris Lattner628fbec2010-09-06 21:54:15 +00002790 }
Michael J. Spencer530ce852010-10-09 11:00:50 +00002791
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002792 // If one instruction matched with a missing feature, report this as a
2793 // missing feature.
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002794 if (std::count(std::begin(Match), std::end(Match),
2795 Match_MissingFeature) == 1) {
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002796 ErrorInfo = ErrorInfoMissingFeature;
2797 return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature,
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002798 MatchingInlineAsm);
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002799 }
Michael J. Spencer530ce852010-10-09 11:00:50 +00002800
Chris Lattner628fbec2010-09-06 21:54:15 +00002801 // If one instruction matched with an invalid operand, report this as an
2802 // operand failure.
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002803 if (std::count(std::begin(Match), std::end(Match),
2804 Match_InvalidOperand) == 1) {
Nirav Dave2364748a2016-09-16 18:30:20 +00002805 return Error(IDLoc, "invalid operand for instruction", EmptyRange,
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002806 MatchingInlineAsm);
Chris Lattner628fbec2010-09-06 21:54:15 +00002807 }
Michael J. Spencer530ce852010-10-09 11:00:50 +00002808
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002809 // If all of these were an outright failure, report it in a useless way.
Chad Rosier3d4bc622012-08-21 19:36:59 +00002810 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
Nirav Dave2364748a2016-09-16 18:30:20 +00002811 EmptyRange, MatchingInlineAsm);
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002812 return true;
2813}
2814
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002815bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
2816 OperandVector &Operands,
2817 MCStreamer &Out,
2818 uint64_t &ErrorInfo,
2819 bool MatchingInlineAsm) {
2820 assert(!Operands.empty() && "Unexpect empty operand list!");
2821 X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
2822 assert(Op.isToken() && "Leading operand should always be a mnemonic!");
2823 StringRef Mnemonic = Op.getToken();
Nirav Dave2364748a2016-09-16 18:30:20 +00002824 SMRange EmptyRange = None;
Nirav Daveee554e62016-10-06 15:28:08 +00002825 StringRef Base = Op.getToken();
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002826
2827 // First, handle aliases that expand to multiple instructions.
2828 MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
2829
2830 MCInst Inst;
2831
2832 // Find one unsized memory operand, if present.
2833 X86Operand *UnsizedMemOp = nullptr;
2834 for (const auto &Op : Operands) {
2835 X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00002836 if (X86Op->isMemUnsized()) {
2837 UnsizedMemOp = X86Op;
Coby Tayree49b37332016-11-22 09:30:29 +00002838 // Have we found an unqualified memory operand,
2839 // break. IA allows only one memory operand.
2840 break;
2841 }
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002842 }
2843
2844 // Allow some instructions to have implicitly pointer-sized operands. This is
2845 // compatible with gas.
2846 if (UnsizedMemOp) {
2847 static const char *const PtrSizedInstrs[] = {"call", "jmp", "push"};
2848 for (const char *Instr : PtrSizedInstrs) {
2849 if (Mnemonic == Instr) {
Craig Topper055845f2015-01-02 07:02:25 +00002850 UnsizedMemOp->Mem.Size = getPointerWidth();
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002851 break;
2852 }
2853 }
2854 }
2855
Nirav Daveee554e62016-10-06 15:28:08 +00002856 SmallVector<unsigned, 8> Match;
2857 uint64_t ErrorInfoMissingFeature = 0;
2858
2859 // If unsized push has immediate operand we should default the default pointer
2860 // size for the size.
2861 if (Mnemonic == "push" && Operands.size() == 2) {
2862 auto *X86Op = static_cast<X86Operand *>(Operands[1].get());
2863 if (X86Op->isImm()) {
2864 // If it's not a constant fall through and let remainder take care of it.
2865 const auto *CE = dyn_cast<MCConstantExpr>(X86Op->getImm());
2866 unsigned Size = getPointerWidth();
2867 if (CE &&
2868 (isIntN(Size, CE->getValue()) || isUIntN(Size, CE->getValue()))) {
2869 SmallString<16> Tmp;
2870 Tmp += Base;
2871 Tmp += (is64BitMode())
2872 ? "q"
2873 : (is32BitMode()) ? "l" : (is16BitMode()) ? "w" : " ";
2874 Op.setTokenValue(Tmp);
2875 // Do match in ATT mode to allow explicit suffix usage.
2876 Match.push_back(MatchInstruction(Operands, Inst, ErrorInfo,
2877 MatchingInlineAsm,
2878 false /*isParsingIntelSyntax()*/));
2879 Op.setTokenValue(Base);
2880 }
2881 }
2882 }
2883
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002884 // If an unsized memory operand is present, try to match with each memory
2885 // operand size. In Intel assembly, the size is not part of the instruction
2886 // mnemonic.
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002887 if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
Ahmed Bougachad65f7872014-12-03 02:03:26 +00002888 static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002889 for (unsigned Size : MopSizes) {
2890 UnsizedMemOp->Mem.Size = Size;
2891 uint64_t ErrorInfoIgnore;
Reid Kleckner7b7a5992014-08-27 20:10:38 +00002892 unsigned LastOpcode = Inst.getOpcode();
Nirav Dave6477ce22016-09-26 19:33:36 +00002893 unsigned M = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
2894 MatchingInlineAsm, isParsingIntelSyntax());
Reid Kleckner7b7a5992014-08-27 20:10:38 +00002895 if (Match.empty() || LastOpcode != Inst.getOpcode())
2896 Match.push_back(M);
2897
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002898 // If this returned as a missing feature failure, remember that.
2899 if (Match.back() == Match_MissingFeature)
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002900 ErrorInfoMissingFeature = ErrorInfoIgnore;
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002901 }
Reid Kleckner7b7a5992014-08-27 20:10:38 +00002902
2903 // Restore the size of the unsized memory operand if we modified it.
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00002904 UnsizedMemOp->Mem.Size = 0;
Reid Kleckner7b7a5992014-08-27 20:10:38 +00002905 }
2906
2907 // If we haven't matched anything yet, this is not a basic integer or FPU
Saleem Abdulrasoolc3f8ad32015-01-16 20:16:06 +00002908 // operation. There shouldn't be any ambiguity in our mnemonic table, so try
Reid Kleckner7b7a5992014-08-27 20:10:38 +00002909 // matching with the unsized operand.
2910 if (Match.empty()) {
Nirav Dave6477ce22016-09-26 19:33:36 +00002911 Match.push_back(MatchInstruction(
2912 Operands, Inst, ErrorInfo, MatchingInlineAsm, isParsingIntelSyntax()));
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002913 // If this returned as a missing feature failure, remember that.
2914 if (Match.back() == Match_MissingFeature)
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002915 ErrorInfoMissingFeature = ErrorInfo;
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002916 }
2917
2918 // Restore the size of the unsized memory operand if we modified it.
2919 if (UnsizedMemOp)
2920 UnsizedMemOp->Mem.Size = 0;
2921
2922 // If it's a bad mnemonic, all results will be the same.
2923 if (Match.back() == Match_MnemonicFail) {
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002924 return Error(IDLoc, "invalid instruction mnemonic '" + Mnemonic + "'",
Nirav Dave2364748a2016-09-16 18:30:20 +00002925 Op.getLocRange(), MatchingInlineAsm);
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002926 }
2927
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00002928 unsigned NumSuccessfulMatches =
2929 std::count(std::begin(Match), std::end(Match), Match_Success);
2930
2931 // If matching was ambiguous and we had size information from the frontend,
2932 // try again with that. This handles cases like "movxz eax, m8/m16".
2933 if (UnsizedMemOp && NumSuccessfulMatches > 1 &&
2934 UnsizedMemOp->getMemFrontendSize()) {
2935 UnsizedMemOp->Mem.Size = UnsizedMemOp->getMemFrontendSize();
2936 unsigned M = MatchInstruction(
2937 Operands, Inst, ErrorInfo, MatchingInlineAsm, isParsingIntelSyntax());
2938 if (M == Match_Success)
2939 NumSuccessfulMatches = 1;
2940
2941 // Add a rewrite that encodes the size information we used from the
2942 // frontend.
2943 InstInfo->AsmRewrites->emplace_back(
2944 AOK_SizeDirective, UnsizedMemOp->getStartLoc(),
2945 /*Len=*/0, UnsizedMemOp->getMemFrontendSize());
2946 }
2947
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002948 // If exactly one matched, then we treat that as a successful match (and the
2949 // instruction will already have been filled in correctly, since the failing
2950 // matches won't have modified it).
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002951 if (NumSuccessfulMatches == 1) {
2952 // Some instructions need post-processing to, for example, tweak which
2953 // encoding is selected. Loop on it while changes happen so the individual
2954 // transformations can chain off each other.
2955 if (!MatchingInlineAsm)
2956 while (processInstruction(Inst, Operands))
2957 ;
2958 Inst.setLoc(IDLoc);
2959 if (!MatchingInlineAsm)
2960 EmitInstruction(Inst, Operands, Out);
2961 Opcode = Inst.getOpcode();
2962 return false;
2963 } else if (NumSuccessfulMatches > 1) {
2964 assert(UnsizedMemOp &&
2965 "multiple matches only possible with unsized memory operands");
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002966 return Error(UnsizedMemOp->getStartLoc(),
2967 "ambiguous operand size for instruction '" + Mnemonic + "\'",
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00002968 UnsizedMemOp->getLocRange());
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002969 }
2970
2971 // If one instruction matched with a missing feature, report this as a
2972 // missing feature.
2973 if (std::count(std::begin(Match), std::end(Match),
2974 Match_MissingFeature) == 1) {
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002975 ErrorInfo = ErrorInfoMissingFeature;
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002976 return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature,
2977 MatchingInlineAsm);
2978 }
2979
2980 // If one instruction matched with an invalid operand, report this as an
2981 // operand failure.
2982 if (std::count(std::begin(Match), std::end(Match),
2983 Match_InvalidOperand) == 1) {
Nirav Dave2364748a2016-09-16 18:30:20 +00002984 return Error(IDLoc, "invalid operand for instruction", EmptyRange,
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002985 MatchingInlineAsm);
2986 }
2987
2988 // If all of these were an outright failure, report it in a useless way.
Nirav Dave2364748a2016-09-16 18:30:20 +00002989 return Error(IDLoc, "unknown instruction mnemonic", EmptyRange,
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002990 MatchingInlineAsm);
2991}
2992
Nico Weber42f79db2014-07-17 20:24:55 +00002993bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
2994 return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
2995}
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002996
Devang Patel4a6e7782012-01-12 18:03:40 +00002997bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
Rafael Espindola961d4692014-11-11 05:18:41 +00002998 MCAsmParser &Parser = getParser();
Chris Lattner72c0b592010-10-30 17:38:55 +00002999 StringRef IDVal = DirectiveID.getIdentifier();
3000 if (IDVal == ".word")
3001 return ParseDirectiveWord(2, DirectiveID.getLoc());
Evan Cheng481ebb02011-07-27 00:38:12 +00003002 else if (IDVal.startswith(".code"))
3003 return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
Chad Rosier6f8d8b22012-09-10 20:54:39 +00003004 else if (IDVal.startswith(".att_syntax")) {
Andrew V. Tischenkoc3c67232017-04-26 09:56:59 +00003005 getParser().setParsingInlineAsm(false);
Reid Klecknerce63b792014-08-06 23:21:13 +00003006 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3007 if (Parser.getTok().getString() == "prefix")
3008 Parser.Lex();
3009 else if (Parser.getTok().getString() == "noprefix")
3010 return Error(DirectiveID.getLoc(), "'.att_syntax noprefix' is not "
3011 "supported: registers must have a "
3012 "'%' prefix in .att_syntax");
3013 }
Chad Rosier6f8d8b22012-09-10 20:54:39 +00003014 getParser().setAssemblerDialect(0);
3015 return false;
3016 } else if (IDVal.startswith(".intel_syntax")) {
Devang Patela173ee52012-01-31 18:14:05 +00003017 getParser().setAssemblerDialect(1);
Andrew V. Tischenkoc3c67232017-04-26 09:56:59 +00003018 getParser().setParsingInlineAsm(true);
Devang Patel9a9bb5c2012-01-30 20:02:42 +00003019 if (getLexer().isNot(AsmToken::EndOfStatement)) {
Saleem Abdulrasoola6505ca2014-01-13 01:15:39 +00003020 if (Parser.getTok().getString() == "noprefix")
Craig Topper6bf3ed42012-07-18 04:59:16 +00003021 Parser.Lex();
Reid Klecknerce63b792014-08-06 23:21:13 +00003022 else if (Parser.getTok().getString() == "prefix")
3023 return Error(DirectiveID.getLoc(), "'.intel_syntax prefix' is not "
3024 "supported: registers must not have "
3025 "a '%' prefix in .intel_syntax");
Devang Patel9a9bb5c2012-01-30 20:02:42 +00003026 }
3027 return false;
Michael Zuckerman02ecd432015-12-13 17:07:23 +00003028 } else if (IDVal == ".even")
3029 return parseDirectiveEven(DirectiveID.getLoc());
Chris Lattner72c0b592010-10-30 17:38:55 +00003030 return true;
3031}
3032
Michael Zuckerman02ecd432015-12-13 17:07:23 +00003033/// parseDirectiveEven
3034/// ::= .even
3035bool X86AsmParser::parseDirectiveEven(SMLoc L) {
Michael Zuckerman02ecd432015-12-13 17:07:23 +00003036 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3037 TokError("unexpected token in directive");
3038 return false;
3039 }
Eric Christopher445c9522016-10-14 05:47:37 +00003040 const MCSection *Section = getStreamer().getCurrentSectionOnly();
Michael Zuckerman02ecd432015-12-13 17:07:23 +00003041 if (!Section) {
3042 getStreamer().InitSections(false);
Eric Christopher445c9522016-10-14 05:47:37 +00003043 Section = getStreamer().getCurrentSectionOnly();
Michael Zuckerman02ecd432015-12-13 17:07:23 +00003044 }
3045 if (Section->UseCodeAlign())
3046 getStreamer().EmitCodeAlignment(2, 0);
3047 else
3048 getStreamer().EmitValueToAlignment(2, 0, 1, 0);
3049 return false;
3050}
Chris Lattner72c0b592010-10-30 17:38:55 +00003051/// ParseDirectiveWord
3052/// ::= .word [ expression (, expression)* ]
Devang Patel4a6e7782012-01-12 18:03:40 +00003053bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
Rafael Espindola961d4692014-11-11 05:18:41 +00003054 MCAsmParser &Parser = getParser();
Chris Lattner72c0b592010-10-30 17:38:55 +00003055 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3056 for (;;) {
3057 const MCExpr *Value;
David Majnemera375b262015-10-26 02:45:50 +00003058 SMLoc ExprLoc = getLexer().getLoc();
Jim Grosbachd2037eb2013-02-20 22:21:35 +00003059 if (getParser().parseExpression(Value))
Saleem Abdulrasoola6505ca2014-01-13 01:15:39 +00003060 return false;
Chad Rosier51afe632012-06-27 22:34:28 +00003061
David Majnemera375b262015-10-26 02:45:50 +00003062 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
3063 assert(Size <= 8 && "Invalid size");
3064 uint64_t IntValue = MCE->getValue();
3065 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
3066 return Error(ExprLoc, "literal value out of range for directive");
3067 getStreamer().EmitIntValue(IntValue, Size);
3068 } else {
3069 getStreamer().EmitValue(Value, Size, ExprLoc);
3070 }
Chad Rosier51afe632012-06-27 22:34:28 +00003071
Chris Lattner72c0b592010-10-30 17:38:55 +00003072 if (getLexer().is(AsmToken::EndOfStatement))
3073 break;
Chad Rosier51afe632012-06-27 22:34:28 +00003074
Chris Lattner72c0b592010-10-30 17:38:55 +00003075 // FIXME: Improve diagnostic.
Saleem Abdulrasoola6505ca2014-01-13 01:15:39 +00003076 if (getLexer().isNot(AsmToken::Comma)) {
3077 Error(L, "unexpected token in directive");
3078 return false;
3079 }
Chris Lattner72c0b592010-10-30 17:38:55 +00003080 Parser.Lex();
3081 }
3082 }
Chad Rosier51afe632012-06-27 22:34:28 +00003083
Chris Lattner72c0b592010-10-30 17:38:55 +00003084 Parser.Lex();
3085 return false;
3086}
3087
Evan Cheng481ebb02011-07-27 00:38:12 +00003088/// ParseDirectiveCode
Craig Topper3c80d622014-01-06 04:55:54 +00003089/// ::= .code16 | .code32 | .code64
Devang Patel4a6e7782012-01-12 18:03:40 +00003090bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
Rafael Espindola961d4692014-11-11 05:18:41 +00003091 MCAsmParser &Parser = getParser();
Nirav Dave6477ce22016-09-26 19:33:36 +00003092 Code16GCC = false;
Craig Topper3c80d622014-01-06 04:55:54 +00003093 if (IDVal == ".code16") {
Evan Cheng481ebb02011-07-27 00:38:12 +00003094 Parser.Lex();
Craig Topper3c80d622014-01-06 04:55:54 +00003095 if (!is16BitMode()) {
3096 SwitchMode(X86::Mode16Bit);
3097 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3098 }
Nirav Dave6477ce22016-09-26 19:33:36 +00003099 } else if (IDVal == ".code16gcc") {
3100 // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode.
3101 Parser.Lex();
3102 Code16GCC = true;
3103 if (!is16BitMode()) {
3104 SwitchMode(X86::Mode16Bit);
3105 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3106 }
Saleem Abdulrasoola6505ca2014-01-13 01:15:39 +00003107 } else if (IDVal == ".code32") {
Craig Topper3c80d622014-01-06 04:55:54 +00003108 Parser.Lex();
3109 if (!is32BitMode()) {
3110 SwitchMode(X86::Mode32Bit);
Evan Cheng481ebb02011-07-27 00:38:12 +00003111 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3112 }
3113 } else if (IDVal == ".code64") {
3114 Parser.Lex();
3115 if (!is64BitMode()) {
Craig Topper3c80d622014-01-06 04:55:54 +00003116 SwitchMode(X86::Mode64Bit);
Evan Cheng481ebb02011-07-27 00:38:12 +00003117 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
3118 }
3119 } else {
Saleem Abdulrasoola6505ca2014-01-13 01:15:39 +00003120 Error(L, "unknown directive " + IDVal);
3121 return false;
Evan Cheng481ebb02011-07-27 00:38:12 +00003122 }
Chris Lattner72c0b592010-10-30 17:38:55 +00003123
Evan Cheng481ebb02011-07-27 00:38:12 +00003124 return false;
3125}
Chris Lattner72c0b592010-10-30 17:38:55 +00003126
Daniel Dunbar71475772009-07-17 20:42:00 +00003127// Force static initialization.
3128extern "C" void LLVMInitializeX86AsmParser() {
Mehdi Aminif42454b2016-10-09 23:00:34 +00003129 RegisterMCAsmParser<X86AsmParser> X(getTheX86_32Target());
3130 RegisterMCAsmParser<X86AsmParser> Y(getTheX86_64Target());
Daniel Dunbar71475772009-07-17 20:42:00 +00003131}
Daniel Dunbar00331992009-07-29 00:02:19 +00003132
Chris Lattner3e4582a2010-09-06 19:11:01 +00003133#define GET_REGISTER_MATCHER
3134#define GET_MATCHER_IMPLEMENTATION
Jim Grosbach6f1f41b2012-11-14 18:04:47 +00003135#define GET_SUBTARGET_FEATURE_NAME
Daniel Dunbar00331992009-07-29 00:02:19 +00003136#include "X86GenAsmMatcher.inc"