blob: 3e2a64a21852b87901f591364b656a43313943fc [file] [log] [blame]
Daniel Dunbar71475772009-07-17 20:42:00 +00001//===-- X86AsmParser.cpp - Parse X86 assembly to MCInst instructions ------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9
Evan Cheng11424442011-07-26 00:24:13 +000010#include "MCTargetDesc/X86BaseInfo.h"
Evgeniy Stepanov49e26252014-03-14 08:58:04 +000011#include "X86AsmInstrumentation.h"
Evgeniy Stepanove3804d42014-02-28 12:28:07 +000012#include "X86AsmParserCommon.h"
13#include "X86Operand.h"
Craig Topper690d8ea2013-07-24 07:33:14 +000014#include "llvm/ADT/STLExtras.h"
Chris Lattner1261b812010-09-22 04:11:10 +000015#include "llvm/ADT/SmallString.h"
16#include "llvm/ADT/SmallVector.h"
Chris Lattner1261b812010-09-22 04:11:10 +000017#include "llvm/ADT/StringSwitch.h"
18#include "llvm/ADT/Twine.h"
Chad Rosier8a244662013-04-02 20:02:33 +000019#include "llvm/MC/MCContext.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000020#include "llvm/MC/MCExpr.h"
21#include "llvm/MC/MCInst.h"
Evgeniy Stepanovf4a36992014-04-24 13:29:34 +000022#include "llvm/MC/MCInstrInfo.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000023#include "llvm/MC/MCParser/MCAsmLexer.h"
24#include "llvm/MC/MCParser/MCAsmParser.h"
25#include "llvm/MC/MCParser/MCParsedAsmOperand.h"
Benjamin Kramerb3e8a6d2016-01-27 10:01:28 +000026#include "llvm/MC/MCParser/MCTargetAsmParser.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000027#include "llvm/MC/MCRegisterInfo.h"
Michael Zuckerman02ecd432015-12-13 17:07:23 +000028#include "llvm/MC/MCSection.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +000029#include "llvm/MC/MCStreamer.h"
30#include "llvm/MC/MCSubtargetInfo.h"
31#include "llvm/MC/MCSymbol.h"
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +000032#include "llvm/Support/SourceMgr.h"
Evan Cheng2bb40352011-08-24 18:08:43 +000033#include "llvm/Support/TargetRegistry.h"
Daniel Dunbar7d7b4d12010-08-12 00:55:42 +000034#include "llvm/Support/raw_ostream.h"
Reid Kleckner7b1e1a02014-07-30 22:23:11 +000035#include <algorithm>
Evgeniy Stepanov49e26252014-03-14 08:58:04 +000036#include <memory>
Evan Cheng4d1ca962011-07-08 01:53:10 +000037
Daniel Dunbar71475772009-07-17 20:42:00 +000038using namespace llvm;
39
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +000040static bool checkScale(unsigned Scale, StringRef &ErrMsg) {
41 if (Scale != 1 && Scale != 2 && Scale != 4 && Scale != 8) {
42 ErrMsg = "scale factor in address must be 1, 2, 4 or 8";
43 return true;
44 }
45 return false;
46}
47
Daniel Dunbar71475772009-07-17 20:42:00 +000048namespace {
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +000049
Chad Rosier5362af92013-04-16 18:15:40 +000050static const char OpPrecedence[] = {
Kevin Enderby2e13b1c2014-01-15 19:05:24 +000051 0, // IC_OR
Michael Kupersteine3de07a2015-06-14 12:59:45 +000052 1, // IC_XOR
53 2, // IC_AND
54 3, // IC_LSHIFT
55 3, // IC_RSHIFT
56 4, // IC_PLUS
57 4, // IC_MINUS
58 5, // IC_MULTIPLY
59 5, // IC_DIVIDE
Coby Tayree41a5b552017-06-27 16:58:27 +000060 5, // IC_MOD
61 6, // IC_NOT
62 7, // IC_NEG
63 8, // IC_RPAREN
64 9, // IC_LPAREN
Chad Rosier5362af92013-04-16 18:15:40 +000065 0, // IC_IMM
66 0 // IC_REGISTER
67};
68
Devang Patel4a6e7782012-01-12 18:03:40 +000069class X86AsmParser : public MCTargetAsmParser {
Evgeniy Stepanovf4a36992014-04-24 13:29:34 +000070 const MCInstrInfo &MII;
Chad Rosierf0e87202012-10-25 20:41:34 +000071 ParseInstructionInfo *InstInfo;
Evgeniy Stepanov49e26252014-03-14 08:58:04 +000072 std::unique_ptr<X86AsmInstrumentation> Instrumentation;
Nirav Dave6477ce22016-09-26 19:33:36 +000073 bool Code16GCC;
NAKAMURA Takumia9cb5382015-09-22 11:14:39 +000074
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +000075private:
Alp Tokera5b88a52013-12-02 16:06:06 +000076 SMLoc consumeToken() {
Rafael Espindola961d4692014-11-11 05:18:41 +000077 MCAsmParser &Parser = getParser();
Alp Tokera5b88a52013-12-02 16:06:06 +000078 SMLoc Result = Parser.getTok().getLoc();
79 Parser.Lex();
80 return Result;
81 }
82
Nirav Dave6477ce22016-09-26 19:33:36 +000083 unsigned MatchInstruction(const OperandVector &Operands, MCInst &Inst,
84 uint64_t &ErrorInfo, bool matchingInlineAsm,
85 unsigned VariantID = 0) {
86 // In Code16GCC mode, match as 32-bit.
87 if (Code16GCC)
88 SwitchMode(X86::Mode32Bit);
89 unsigned rv = MatchInstructionImpl(Operands, Inst, ErrorInfo,
90 matchingInlineAsm, VariantID);
91 if (Code16GCC)
92 SwitchMode(X86::Mode16Bit);
93 return rv;
94 }
95
Chad Rosier5362af92013-04-16 18:15:40 +000096 enum InfixCalculatorTok {
Kevin Enderby2e13b1c2014-01-15 19:05:24 +000097 IC_OR = 0,
Michael Kupersteine3de07a2015-06-14 12:59:45 +000098 IC_XOR,
Kevin Enderby2e13b1c2014-01-15 19:05:24 +000099 IC_AND,
Kevin Enderbyd6b10712014-02-06 01:21:15 +0000100 IC_LSHIFT,
101 IC_RSHIFT,
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000102 IC_PLUS,
Chad Rosier5362af92013-04-16 18:15:40 +0000103 IC_MINUS,
104 IC_MULTIPLY,
105 IC_DIVIDE,
Coby Tayree41a5b552017-06-27 16:58:27 +0000106 IC_MOD,
107 IC_NOT,
108 IC_NEG,
Chad Rosier5362af92013-04-16 18:15:40 +0000109 IC_RPAREN,
110 IC_LPAREN,
111 IC_IMM,
112 IC_REGISTER
113 };
114
Coby Tayree07a89742017-03-21 19:31:55 +0000115 enum IntelOperatorKind {
116 IOK_INVALID = 0,
117 IOK_LENGTH,
118 IOK_SIZE,
119 IOK_TYPE,
120 IOK_OFFSET
121 };
122
Chad Rosier5362af92013-04-16 18:15:40 +0000123 class InfixCalculator {
124 typedef std::pair< InfixCalculatorTok, int64_t > ICToken;
125 SmallVector<InfixCalculatorTok, 4> InfixOperatorStack;
126 SmallVector<ICToken, 4> PostfixStack;
Michael Liao5bf95782014-12-04 05:20:33 +0000127
Coby Tayree41a5b552017-06-27 16:58:27 +0000128 bool isUnaryOperator(const InfixCalculatorTok Op) {
129 return Op == IC_NEG || Op == IC_NOT;
130 }
131
Chad Rosier5362af92013-04-16 18:15:40 +0000132 public:
133 int64_t popOperand() {
134 assert (!PostfixStack.empty() && "Poped an empty stack!");
135 ICToken Op = PostfixStack.pop_back_val();
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000136 if (!(Op.first == IC_IMM || Op.first == IC_REGISTER))
137 return -1; // The invalid Scale value will be caught later by checkScale
Chad Rosier5362af92013-04-16 18:15:40 +0000138 return Op.second;
139 }
140 void pushOperand(InfixCalculatorTok Op, int64_t Val = 0) {
141 assert ((Op == IC_IMM || Op == IC_REGISTER) &&
142 "Unexpected operand!");
143 PostfixStack.push_back(std::make_pair(Op, Val));
144 }
Michael Liao5bf95782014-12-04 05:20:33 +0000145
Jakub Staszak9c349222013-08-08 15:48:46 +0000146 void popOperator() { InfixOperatorStack.pop_back(); }
Chad Rosier5362af92013-04-16 18:15:40 +0000147 void pushOperator(InfixCalculatorTok Op) {
148 // Push the new operator if the stack is empty.
149 if (InfixOperatorStack.empty()) {
150 InfixOperatorStack.push_back(Op);
151 return;
152 }
Michael Liao5bf95782014-12-04 05:20:33 +0000153
Chad Rosier5362af92013-04-16 18:15:40 +0000154 // Push the new operator if it has a higher precedence than the operator
155 // on the top of the stack or the operator on the top of the stack is a
156 // left parentheses.
157 unsigned Idx = InfixOperatorStack.size() - 1;
158 InfixCalculatorTok StackOp = InfixOperatorStack[Idx];
159 if (OpPrecedence[Op] > OpPrecedence[StackOp] || StackOp == IC_LPAREN) {
160 InfixOperatorStack.push_back(Op);
161 return;
162 }
Michael Liao5bf95782014-12-04 05:20:33 +0000163
Chad Rosier5362af92013-04-16 18:15:40 +0000164 // The operator on the top of the stack has higher precedence than the
165 // new operator.
166 unsigned ParenCount = 0;
Kirill Bobyrev6afbaf02017-01-18 16:34:25 +0000167 while (1) {
Chad Rosier5362af92013-04-16 18:15:40 +0000168 // Nothing to process.
169 if (InfixOperatorStack.empty())
170 break;
Michael Liao5bf95782014-12-04 05:20:33 +0000171
Chad Rosier5362af92013-04-16 18:15:40 +0000172 Idx = InfixOperatorStack.size() - 1;
173 StackOp = InfixOperatorStack[Idx];
174 if (!(OpPrecedence[StackOp] >= OpPrecedence[Op] || ParenCount))
175 break;
Michael Liao5bf95782014-12-04 05:20:33 +0000176
Chad Rosier5362af92013-04-16 18:15:40 +0000177 // If we have an even parentheses count and we see a left parentheses,
178 // then stop processing.
179 if (!ParenCount && StackOp == IC_LPAREN)
180 break;
Michael Liao5bf95782014-12-04 05:20:33 +0000181
Chad Rosier5362af92013-04-16 18:15:40 +0000182 if (StackOp == IC_RPAREN) {
183 ++ParenCount;
Jakub Staszak9c349222013-08-08 15:48:46 +0000184 InfixOperatorStack.pop_back();
Chad Rosier5362af92013-04-16 18:15:40 +0000185 } else if (StackOp == IC_LPAREN) {
186 --ParenCount;
Jakub Staszak9c349222013-08-08 15:48:46 +0000187 InfixOperatorStack.pop_back();
Chad Rosier5362af92013-04-16 18:15:40 +0000188 } else {
Jakub Staszak9c349222013-08-08 15:48:46 +0000189 InfixOperatorStack.pop_back();
Chad Rosier5362af92013-04-16 18:15:40 +0000190 PostfixStack.push_back(std::make_pair(StackOp, 0));
191 }
192 }
193 // Push the new operator.
194 InfixOperatorStack.push_back(Op);
195 }
Marina Yatsinaa0e02412015-08-10 11:33:10 +0000196
Chad Rosier5362af92013-04-16 18:15:40 +0000197 int64_t execute() {
198 // Push any remaining operators onto the postfix stack.
199 while (!InfixOperatorStack.empty()) {
200 InfixCalculatorTok StackOp = InfixOperatorStack.pop_back_val();
201 if (StackOp != IC_LPAREN && StackOp != IC_RPAREN)
202 PostfixStack.push_back(std::make_pair(StackOp, 0));
203 }
Michael Liao5bf95782014-12-04 05:20:33 +0000204
Chad Rosier5362af92013-04-16 18:15:40 +0000205 if (PostfixStack.empty())
206 return 0;
Michael Liao5bf95782014-12-04 05:20:33 +0000207
Chad Rosier5362af92013-04-16 18:15:40 +0000208 SmallVector<ICToken, 16> OperandStack;
209 for (unsigned i = 0, e = PostfixStack.size(); i != e; ++i) {
210 ICToken Op = PostfixStack[i];
211 if (Op.first == IC_IMM || Op.first == IC_REGISTER) {
212 OperandStack.push_back(Op);
Coby Tayree41a5b552017-06-27 16:58:27 +0000213 } else if (isUnaryOperator(Op.first)) {
214 assert (OperandStack.size() > 0 && "Too few operands.");
215 ICToken Operand = OperandStack.pop_back_val();
216 assert (Operand.first == IC_IMM &&
217 "Unary operation with a register!");
218 switch (Op.first) {
219 default:
220 report_fatal_error("Unexpected operator!");
221 break;
222 case IC_NEG:
223 OperandStack.push_back(std::make_pair(IC_IMM, -Operand.second));
224 break;
225 case IC_NOT:
226 OperandStack.push_back(std::make_pair(IC_IMM, ~Operand.second));
227 break;
228 }
Chad Rosier5362af92013-04-16 18:15:40 +0000229 } else {
230 assert (OperandStack.size() > 1 && "Too few operands.");
231 int64_t Val;
232 ICToken Op2 = OperandStack.pop_back_val();
233 ICToken Op1 = OperandStack.pop_back_val();
234 switch (Op.first) {
235 default:
236 report_fatal_error("Unexpected operator!");
237 break;
238 case IC_PLUS:
239 Val = Op1.second + Op2.second;
240 OperandStack.push_back(std::make_pair(IC_IMM, Val));
241 break;
242 case IC_MINUS:
243 Val = Op1.second - Op2.second;
244 OperandStack.push_back(std::make_pair(IC_IMM, Val));
245 break;
246 case IC_MULTIPLY:
247 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
248 "Multiply operation with an immediate and a register!");
249 Val = Op1.second * Op2.second;
250 OperandStack.push_back(std::make_pair(IC_IMM, Val));
251 break;
252 case IC_DIVIDE:
253 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
254 "Divide operation with an immediate and a register!");
255 assert (Op2.second != 0 && "Division by zero!");
256 Val = Op1.second / Op2.second;
257 OperandStack.push_back(std::make_pair(IC_IMM, Val));
258 break;
Coby Tayree41a5b552017-06-27 16:58:27 +0000259 case IC_MOD:
260 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
261 "Modulo operation with an immediate and a register!");
262 Val = Op1.second % Op2.second;
263 OperandStack.push_back(std::make_pair(IC_IMM, Val));
264 break;
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000265 case IC_OR:
266 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
267 "Or operation with an immediate and a register!");
268 Val = Op1.second | Op2.second;
269 OperandStack.push_back(std::make_pair(IC_IMM, Val));
270 break;
Michael Kupersteine3de07a2015-06-14 12:59:45 +0000271 case IC_XOR:
272 assert(Op1.first == IC_IMM && Op2.first == IC_IMM &&
273 "Xor operation with an immediate and a register!");
274 Val = Op1.second ^ Op2.second;
275 OperandStack.push_back(std::make_pair(IC_IMM, Val));
276 break;
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000277 case IC_AND:
278 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
279 "And operation with an immediate and a register!");
280 Val = Op1.second & Op2.second;
281 OperandStack.push_back(std::make_pair(IC_IMM, Val));
282 break;
Kevin Enderbyd6b10712014-02-06 01:21:15 +0000283 case IC_LSHIFT:
284 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
285 "Left shift operation with an immediate and a register!");
286 Val = Op1.second << Op2.second;
287 OperandStack.push_back(std::make_pair(IC_IMM, Val));
288 break;
289 case IC_RSHIFT:
290 assert (Op1.first == IC_IMM && Op2.first == IC_IMM &&
291 "Right shift operation with an immediate and a register!");
292 Val = Op1.second >> Op2.second;
293 OperandStack.push_back(std::make_pair(IC_IMM, Val));
294 break;
Chad Rosier5362af92013-04-16 18:15:40 +0000295 }
296 }
297 }
298 assert (OperandStack.size() == 1 && "Expected a single result.");
299 return OperandStack.pop_back_val().second;
300 }
301 };
302
303 enum IntelExprState {
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000304 IES_OR,
Michael Kupersteine3de07a2015-06-14 12:59:45 +0000305 IES_XOR,
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000306 IES_AND,
Kevin Enderbyd6b10712014-02-06 01:21:15 +0000307 IES_LSHIFT,
308 IES_RSHIFT,
Chad Rosier5362af92013-04-16 18:15:40 +0000309 IES_PLUS,
310 IES_MINUS,
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000311 IES_NOT,
Chad Rosier5362af92013-04-16 18:15:40 +0000312 IES_MULTIPLY,
313 IES_DIVIDE,
Coby Tayree41a5b552017-06-27 16:58:27 +0000314 IES_MOD,
Chad Rosier5362af92013-04-16 18:15:40 +0000315 IES_LBRAC,
316 IES_RBRAC,
317 IES_LPAREN,
318 IES_RPAREN,
319 IES_REGISTER,
Chad Rosier5362af92013-04-16 18:15:40 +0000320 IES_INTEGER,
Chad Rosier5362af92013-04-16 18:15:40 +0000321 IES_IDENTIFIER,
322 IES_ERROR
323 };
324
325 class IntelExprStateMachine {
Chad Rosier31246272013-04-17 21:01:45 +0000326 IntelExprState State, PrevState;
Chad Rosier5362af92013-04-16 18:15:40 +0000327 unsigned BaseReg, IndexReg, TmpReg, Scale;
Chad Rosierbfb70992013-04-17 00:11:46 +0000328 int64_t Imm;
Chad Rosier5362af92013-04-16 18:15:40 +0000329 const MCExpr *Sym;
330 StringRef SymName;
Chad Rosierbfb70992013-04-17 00:11:46 +0000331 bool StopOnLBrac, AddImmPrefix;
Chad Rosier5362af92013-04-16 18:15:40 +0000332 InfixCalculator IC;
Chad Rosiercb78f0d2013-04-22 19:42:15 +0000333 InlineAsmIdentifierInfo Info;
NAKAMURA Takumia9cb5382015-09-22 11:14:39 +0000334
Chad Rosier5362af92013-04-16 18:15:40 +0000335 public:
Chad Rosierbfb70992013-04-17 00:11:46 +0000336 IntelExprStateMachine(int64_t imm, bool stoponlbrac, bool addimmprefix) :
Chad Rosier31246272013-04-17 21:01:45 +0000337 State(IES_PLUS), PrevState(IES_ERROR), BaseReg(0), IndexReg(0), TmpReg(0),
Craig Topper062a2ba2014-04-25 05:30:21 +0000338 Scale(1), Imm(imm), Sym(nullptr), StopOnLBrac(stoponlbrac),
Chad Rosiercb78f0d2013-04-22 19:42:15 +0000339 AddImmPrefix(addimmprefix) { Info.clear(); }
Michael Liao5bf95782014-12-04 05:20:33 +0000340
Chad Rosier5362af92013-04-16 18:15:40 +0000341 unsigned getBaseReg() { return BaseReg; }
342 unsigned getIndexReg() { return IndexReg; }
343 unsigned getScale() { return Scale; }
344 const MCExpr *getSym() { return Sym; }
345 StringRef getSymName() { return SymName; }
Chad Rosierbfb70992013-04-17 00:11:46 +0000346 int64_t getImm() { return Imm + IC.execute(); }
Chad Rosieredb1dc82013-05-09 23:48:53 +0000347 bool isValidEndState() {
348 return State == IES_RBRAC || State == IES_INTEGER;
349 }
Chad Rosierbfb70992013-04-17 00:11:46 +0000350 bool getStopOnLBrac() { return StopOnLBrac; }
351 bool getAddImmPrefix() { return AddImmPrefix; }
Chad Rosier31246272013-04-17 21:01:45 +0000352 bool hadError() { return State == IES_ERROR; }
Chad Rosierbfb70992013-04-17 00:11:46 +0000353
Chad Rosiercb78f0d2013-04-22 19:42:15 +0000354 InlineAsmIdentifierInfo &getIdentifierInfo() {
355 return Info;
356 }
357
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000358 void onOr() {
359 IntelExprState CurrState = State;
360 switch (State) {
361 default:
362 State = IES_ERROR;
363 break;
364 case IES_INTEGER:
365 case IES_RPAREN:
366 case IES_REGISTER:
367 State = IES_OR;
368 IC.pushOperator(IC_OR);
369 break;
370 }
371 PrevState = CurrState;
372 }
Michael Kupersteine3de07a2015-06-14 12:59:45 +0000373 void onXor() {
374 IntelExprState CurrState = State;
375 switch (State) {
376 default:
377 State = IES_ERROR;
378 break;
379 case IES_INTEGER:
380 case IES_RPAREN:
381 case IES_REGISTER:
382 State = IES_XOR;
383 IC.pushOperator(IC_XOR);
384 break;
385 }
386 PrevState = CurrState;
387 }
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000388 void onAnd() {
389 IntelExprState CurrState = State;
390 switch (State) {
391 default:
392 State = IES_ERROR;
393 break;
394 case IES_INTEGER:
395 case IES_RPAREN:
396 case IES_REGISTER:
397 State = IES_AND;
398 IC.pushOperator(IC_AND);
399 break;
400 }
401 PrevState = CurrState;
402 }
Kevin Enderbyd6b10712014-02-06 01:21:15 +0000403 void onLShift() {
404 IntelExprState CurrState = State;
405 switch (State) {
406 default:
407 State = IES_ERROR;
408 break;
409 case IES_INTEGER:
410 case IES_RPAREN:
411 case IES_REGISTER:
412 State = IES_LSHIFT;
413 IC.pushOperator(IC_LSHIFT);
414 break;
415 }
416 PrevState = CurrState;
417 }
418 void onRShift() {
419 IntelExprState CurrState = State;
420 switch (State) {
421 default:
422 State = IES_ERROR;
423 break;
424 case IES_INTEGER:
425 case IES_RPAREN:
426 case IES_REGISTER:
427 State = IES_RSHIFT;
428 IC.pushOperator(IC_RSHIFT);
429 break;
430 }
431 PrevState = CurrState;
432 }
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000433 bool onPlus(StringRef &ErrMsg) {
Chad Rosier31246272013-04-17 21:01:45 +0000434 IntelExprState CurrState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000435 switch (State) {
436 default:
437 State = IES_ERROR;
438 break;
439 case IES_INTEGER:
440 case IES_RPAREN:
Chad Rosier5362af92013-04-16 18:15:40 +0000441 case IES_REGISTER:
442 State = IES_PLUS;
Chad Rosier5362af92013-04-16 18:15:40 +0000443 IC.pushOperator(IC_PLUS);
Chad Rosier31246272013-04-17 21:01:45 +0000444 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
445 // If we already have a BaseReg, then assume this is the IndexReg with
446 // a scale of 1.
447 if (!BaseReg) {
448 BaseReg = TmpReg;
449 } else {
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000450 if (IndexReg) {
451 ErrMsg = "BaseReg/IndexReg already set!";
452 return true;
453 }
Chad Rosier31246272013-04-17 21:01:45 +0000454 IndexReg = TmpReg;
455 Scale = 1;
456 }
457 }
Chad Rosier5362af92013-04-16 18:15:40 +0000458 break;
459 }
Chad Rosier31246272013-04-17 21:01:45 +0000460 PrevState = CurrState;
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000461 return false;
Chad Rosier5362af92013-04-16 18:15:40 +0000462 }
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000463 bool onMinus(StringRef &ErrMsg) {
Chad Rosier31246272013-04-17 21:01:45 +0000464 IntelExprState CurrState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000465 switch (State) {
466 default:
467 State = IES_ERROR;
468 break;
Coby Tayree41a5b552017-06-27 16:58:27 +0000469 case IES_OR:
470 case IES_XOR:
471 case IES_AND:
472 case IES_LSHIFT:
473 case IES_RSHIFT:
Chad Rosier5362af92013-04-16 18:15:40 +0000474 case IES_PLUS:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000475 case IES_NOT:
Chad Rosier31246272013-04-17 21:01:45 +0000476 case IES_MULTIPLY:
477 case IES_DIVIDE:
Coby Tayree41a5b552017-06-27 16:58:27 +0000478 case IES_MOD:
Chad Rosier5362af92013-04-16 18:15:40 +0000479 case IES_LPAREN:
Chad Rosier5362af92013-04-16 18:15:40 +0000480 case IES_RPAREN:
Chad Rosier31246272013-04-17 21:01:45 +0000481 case IES_LBRAC:
482 case IES_RBRAC:
483 case IES_INTEGER:
Chad Rosier5362af92013-04-16 18:15:40 +0000484 case IES_REGISTER:
485 State = IES_MINUS;
Coby Tayree41a5b552017-06-27 16:58:27 +0000486 // push minus operator if it is not a negate operator
487 if (CurrState == IES_REGISTER || CurrState == IES_RPAREN ||
488 CurrState == IES_INTEGER || CurrState == IES_RBRAC)
Chad Rosier31246272013-04-17 21:01:45 +0000489 IC.pushOperator(IC_MINUS);
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000490 else if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
491 // We have negate operator for Scale: it's illegal
492 ErrMsg = "Scale can't be negative";
493 return true;
494 } else
Coby Tayree41a5b552017-06-27 16:58:27 +0000495 IC.pushOperator(IC_NEG);
Chad Rosier31246272013-04-17 21:01:45 +0000496 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
497 // If we already have a BaseReg, then assume this is the IndexReg with
498 // a scale of 1.
499 if (!BaseReg) {
500 BaseReg = TmpReg;
501 } else {
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000502 if (IndexReg) {
503 ErrMsg = "BaseReg/IndexReg already set!";
504 return true;
505 }
Chad Rosier31246272013-04-17 21:01:45 +0000506 IndexReg = TmpReg;
507 Scale = 1;
508 }
Chad Rosier5362af92013-04-16 18:15:40 +0000509 }
Chad Rosier5362af92013-04-16 18:15:40 +0000510 break;
511 }
Chad Rosier31246272013-04-17 21:01:45 +0000512 PrevState = CurrState;
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000513 return false;
Chad Rosier5362af92013-04-16 18:15:40 +0000514 }
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000515 void onNot() {
516 IntelExprState CurrState = State;
517 switch (State) {
518 default:
519 State = IES_ERROR;
520 break;
Coby Tayree41a5b552017-06-27 16:58:27 +0000521 case IES_OR:
522 case IES_XOR:
523 case IES_AND:
524 case IES_LSHIFT:
525 case IES_RSHIFT:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000526 case IES_PLUS:
Coby Tayree41a5b552017-06-27 16:58:27 +0000527 case IES_MINUS:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000528 case IES_NOT:
Coby Tayree41a5b552017-06-27 16:58:27 +0000529 case IES_MULTIPLY:
530 case IES_DIVIDE:
531 case IES_MOD:
532 case IES_LPAREN:
533 case IES_LBRAC:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000534 State = IES_NOT;
Coby Tayree41a5b552017-06-27 16:58:27 +0000535 IC.pushOperator(IC_NOT);
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000536 break;
537 }
538 PrevState = CurrState;
539 }
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000540
541 bool onRegister(unsigned Reg, StringRef &ErrMsg) {
Chad Rosier31246272013-04-17 21:01:45 +0000542 IntelExprState CurrState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000543 switch (State) {
544 default:
545 State = IES_ERROR;
546 break;
547 case IES_PLUS:
548 case IES_LPAREN:
549 State = IES_REGISTER;
550 TmpReg = Reg;
551 IC.pushOperand(IC_REGISTER);
552 break;
Chad Rosier31246272013-04-17 21:01:45 +0000553 case IES_MULTIPLY:
554 // Index Register - Scale * Register
555 if (PrevState == IES_INTEGER) {
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000556 if (IndexReg) {
557 ErrMsg = "BaseReg/IndexReg already set!";
558 return true;
559 }
Chad Rosier31246272013-04-17 21:01:45 +0000560 State = IES_REGISTER;
561 IndexReg = Reg;
562 // Get the scale and replace the 'Scale * Register' with '0'.
563 Scale = IC.popOperand();
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000564 if (checkScale(Scale, ErrMsg))
565 return true;
Chad Rosier31246272013-04-17 21:01:45 +0000566 IC.pushOperand(IC_IMM);
567 IC.popOperator();
568 } else {
569 State = IES_ERROR;
570 }
Chad Rosier5362af92013-04-16 18:15:40 +0000571 break;
572 }
Chad Rosier31246272013-04-17 21:01:45 +0000573 PrevState = CurrState;
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000574 return false;
Chad Rosier5362af92013-04-16 18:15:40 +0000575 }
Chad Rosier95ce8892013-04-19 18:39:50 +0000576 void onIdentifierExpr(const MCExpr *SymRef, StringRef SymRefName) {
Chad Rosierdb003992013-04-18 16:28:19 +0000577 PrevState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000578 switch (State) {
579 default:
580 State = IES_ERROR;
581 break;
582 case IES_PLUS:
583 case IES_MINUS:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000584 case IES_NOT:
Chad Rosier5362af92013-04-16 18:15:40 +0000585 State = IES_INTEGER;
586 Sym = SymRef;
587 SymName = SymRefName;
588 IC.pushOperand(IC_IMM);
589 break;
590 }
591 }
Kevin Enderby9d117022014-01-23 21:52:41 +0000592 bool onInteger(int64_t TmpInt, StringRef &ErrMsg) {
Chad Rosier31246272013-04-17 21:01:45 +0000593 IntelExprState CurrState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000594 switch (State) {
595 default:
596 State = IES_ERROR;
597 break;
598 case IES_PLUS:
599 case IES_MINUS:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000600 case IES_NOT:
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000601 case IES_OR:
Michael Kupersteine3de07a2015-06-14 12:59:45 +0000602 case IES_XOR:
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000603 case IES_AND:
Kevin Enderbyd6b10712014-02-06 01:21:15 +0000604 case IES_LSHIFT:
605 case IES_RSHIFT:
Chad Rosier5362af92013-04-16 18:15:40 +0000606 case IES_DIVIDE:
Coby Tayree41a5b552017-06-27 16:58:27 +0000607 case IES_MOD:
Chad Rosier31246272013-04-17 21:01:45 +0000608 case IES_MULTIPLY:
Chad Rosier5362af92013-04-16 18:15:40 +0000609 case IES_LPAREN:
Chad Rosier5362af92013-04-16 18:15:40 +0000610 State = IES_INTEGER;
Chad Rosier31246272013-04-17 21:01:45 +0000611 if (PrevState == IES_REGISTER && CurrState == IES_MULTIPLY) {
612 // Index Register - Register * Scale
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000613 if (IndexReg) {
614 ErrMsg = "BaseReg/IndexReg already set!";
Kevin Enderby9d117022014-01-23 21:52:41 +0000615 return true;
616 }
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000617 IndexReg = TmpReg;
618 Scale = TmpInt;
619 if (checkScale(Scale, ErrMsg))
620 return true;
Chad Rosier31246272013-04-17 21:01:45 +0000621 // Get the scale and replace the 'Register * Scale' with '0'.
622 IC.popOperator();
Chad Rosier31246272013-04-17 21:01:45 +0000623 } else {
624 IC.pushOperand(IC_IMM, TmpInt);
625 }
Chad Rosier5362af92013-04-16 18:15:40 +0000626 break;
627 }
Chad Rosier31246272013-04-17 21:01:45 +0000628 PrevState = CurrState;
Kevin Enderby9d117022014-01-23 21:52:41 +0000629 return false;
Chad Rosier5362af92013-04-16 18:15:40 +0000630 }
631 void onStar() {
Chad Rosierdb003992013-04-18 16:28:19 +0000632 PrevState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000633 switch (State) {
634 default:
635 State = IES_ERROR;
636 break;
637 case IES_INTEGER:
Chad Rosier5362af92013-04-16 18:15:40 +0000638 case IES_REGISTER:
Chad Rosier5362af92013-04-16 18:15:40 +0000639 case IES_RPAREN:
640 State = IES_MULTIPLY;
641 IC.pushOperator(IC_MULTIPLY);
642 break;
643 }
644 }
645 void onDivide() {
Chad Rosierdb003992013-04-18 16:28:19 +0000646 PrevState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000647 switch (State) {
648 default:
649 State = IES_ERROR;
650 break;
651 case IES_INTEGER:
Chad Rosier31246272013-04-17 21:01:45 +0000652 case IES_RPAREN:
Chad Rosier5362af92013-04-16 18:15:40 +0000653 State = IES_DIVIDE;
654 IC.pushOperator(IC_DIVIDE);
655 break;
656 }
657 }
Coby Tayree41a5b552017-06-27 16:58:27 +0000658 void onMod() {
659 PrevState = State;
660 switch (State) {
661 default:
662 State = IES_ERROR;
663 break;
664 case IES_INTEGER:
665 case IES_RPAREN:
666 State = IES_MOD;
667 IC.pushOperator(IC_MOD);
668 break;
669 }
670 }
Chad Rosier5362af92013-04-16 18:15:40 +0000671 void onLBrac() {
Chad Rosierdb003992013-04-18 16:28:19 +0000672 PrevState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000673 switch (State) {
674 default:
675 State = IES_ERROR;
676 break;
677 case IES_RBRAC:
678 State = IES_PLUS;
679 IC.pushOperator(IC_PLUS);
680 break;
681 }
682 }
683 void onRBrac() {
Chad Rosier31246272013-04-17 21:01:45 +0000684 IntelExprState CurrState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000685 switch (State) {
686 default:
687 State = IES_ERROR;
688 break;
Chad Rosier5362af92013-04-16 18:15:40 +0000689 case IES_INTEGER:
Chad Rosier5362af92013-04-16 18:15:40 +0000690 case IES_REGISTER:
Chad Rosier31246272013-04-17 21:01:45 +0000691 case IES_RPAREN:
Chad Rosier5362af92013-04-16 18:15:40 +0000692 State = IES_RBRAC;
Chad Rosier31246272013-04-17 21:01:45 +0000693 if (CurrState == IES_REGISTER && PrevState != IES_MULTIPLY) {
694 // If we already have a BaseReg, then assume this is the IndexReg with
695 // a scale of 1.
696 if (!BaseReg) {
697 BaseReg = TmpReg;
698 } else {
699 assert (!IndexReg && "BaseReg/IndexReg already set!");
700 IndexReg = TmpReg;
701 Scale = 1;
702 }
Chad Rosier5362af92013-04-16 18:15:40 +0000703 }
704 break;
705 }
Chad Rosier31246272013-04-17 21:01:45 +0000706 PrevState = CurrState;
Chad Rosier5362af92013-04-16 18:15:40 +0000707 }
708 void onLParen() {
Chad Rosier31246272013-04-17 21:01:45 +0000709 IntelExprState CurrState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000710 switch (State) {
711 default:
712 State = IES_ERROR;
713 break;
714 case IES_PLUS:
715 case IES_MINUS:
Ehsan Akhgari4103da62014-07-04 19:13:05 +0000716 case IES_NOT:
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000717 case IES_OR:
Michael Kupersteine3de07a2015-06-14 12:59:45 +0000718 case IES_XOR:
Kevin Enderby2e13b1c2014-01-15 19:05:24 +0000719 case IES_AND:
Kevin Enderbyd6b10712014-02-06 01:21:15 +0000720 case IES_LSHIFT:
721 case IES_RSHIFT:
Chad Rosier5362af92013-04-16 18:15:40 +0000722 case IES_MULTIPLY:
723 case IES_DIVIDE:
Coby Tayree41a5b552017-06-27 16:58:27 +0000724 case IES_MOD:
Chad Rosier5362af92013-04-16 18:15:40 +0000725 case IES_LPAREN:
726 State = IES_LPAREN;
727 IC.pushOperator(IC_LPAREN);
728 break;
729 }
Chad Rosier31246272013-04-17 21:01:45 +0000730 PrevState = CurrState;
Chad Rosier5362af92013-04-16 18:15:40 +0000731 }
732 void onRParen() {
Chad Rosierdb003992013-04-18 16:28:19 +0000733 PrevState = State;
Chad Rosier5362af92013-04-16 18:15:40 +0000734 switch (State) {
735 default:
736 State = IES_ERROR;
737 break;
Chad Rosier5362af92013-04-16 18:15:40 +0000738 case IES_INTEGER:
Chad Rosier31246272013-04-17 21:01:45 +0000739 case IES_REGISTER:
Chad Rosier5362af92013-04-16 18:15:40 +0000740 case IES_RPAREN:
741 State = IES_RPAREN;
742 IC.pushOperator(IC_RPAREN);
743 break;
744 }
745 }
746 };
747
Nirav Dave2364748a2016-09-16 18:30:20 +0000748 bool Error(SMLoc L, const Twine &Msg, SMRange Range = None,
Chad Rosier4453e842012-10-12 23:09:25 +0000749 bool MatchingInlineAsm = false) {
Rafael Espindola961d4692014-11-11 05:18:41 +0000750 MCAsmParser &Parser = getParser();
Nirav Dave2364748a2016-09-16 18:30:20 +0000751 if (MatchingInlineAsm) {
752 if (!getLexer().isAtStartOfStatement())
753 Parser.eatToEndOfStatement();
754 return false;
755 }
756 return Parser.Error(L, Msg, Range);
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000757 }
758
David Blaikie960ea3f2014-06-08 16:18:35 +0000759 std::nullptr_t ErrorOperand(SMLoc Loc, StringRef Msg) {
Devang Patel41b9dde2012-01-17 18:00:18 +0000760 Error(Loc, Msg);
Craig Topper062a2ba2014-04-25 05:30:21 +0000761 return nullptr;
Devang Patel41b9dde2012-01-17 18:00:18 +0000762 }
763
David Blaikie960ea3f2014-06-08 16:18:35 +0000764 std::unique_ptr<X86Operand> DefaultMemSIOperand(SMLoc Loc);
765 std::unique_ptr<X86Operand> DefaultMemDIOperand(SMLoc Loc);
Marina Yatsinab9f4f622016-01-19 15:37:56 +0000766 bool IsSIReg(unsigned Reg);
767 unsigned GetSIDIForRegClass(unsigned RegClassID, unsigned Reg, bool IsSIReg);
768 void
769 AddDefaultSrcDestOperands(OperandVector &Operands,
770 std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
771 std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst);
772 bool VerifyAndAdjustOperands(OperandVector &OrigOperands,
773 OperandVector &FinalOperands);
David Blaikie960ea3f2014-06-08 16:18:35 +0000774 std::unique_ptr<X86Operand> ParseOperand();
775 std::unique_ptr<X86Operand> ParseATTOperand();
776 std::unique_ptr<X86Operand> ParseIntelOperand();
777 std::unique_ptr<X86Operand> ParseIntelOffsetOfOperator();
Benjamin Kramer951b15e2013-12-01 11:47:42 +0000778 bool ParseIntelDotOperator(const MCExpr *Disp, const MCExpr *&NewDisp);
Coby Tayree07a89742017-03-21 19:31:55 +0000779 unsigned IdentifyIntelOperator(StringRef Name);
Eric Christopheradfe5362017-07-25 19:22:09 +0000780 unsigned ParseIntelOperator(unsigned OpKind);
David Blaikie960ea3f2014-06-08 16:18:35 +0000781 std::unique_ptr<X86Operand>
782 ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start, unsigned Size);
Elena Demikhovsky18fd4962015-03-02 15:00:34 +0000783 std::unique_ptr<X86Operand> ParseRoundingModeOp(SMLoc Start, SMLoc End);
Coby Tayree2cb497a2017-04-04 14:43:23 +0000784 bool ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM);
Benjamin Kramer951b15e2013-12-01 11:47:42 +0000785 bool ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End);
Nirav Dave8601ac12016-08-02 17:56:03 +0000786 std::unique_ptr<X86Operand>
787 ParseIntelBracExpression(unsigned SegReg, SMLoc Start, int64_t ImmDisp,
788 bool isSymbol, unsigned Size);
Benjamin Kramer951b15e2013-12-01 11:47:42 +0000789 bool ParseIntelIdentifier(const MCExpr *&Val, StringRef &Identifier,
790 InlineAsmIdentifierInfo &Info,
791 bool IsUnevaluatedOperand, SMLoc &End);
Chad Rosiercb78f0d2013-04-22 19:42:15 +0000792
David Blaikie960ea3f2014-06-08 16:18:35 +0000793 std::unique_ptr<X86Operand> ParseMemOperand(unsigned SegReg, SMLoc StartLoc);
Kevin Enderbyce4bec82009-09-10 20:51:44 +0000794
David Blaikie960ea3f2014-06-08 16:18:35 +0000795 std::unique_ptr<X86Operand>
796 CreateMemForInlineAsm(unsigned SegReg, const MCExpr *Disp, unsigned BaseReg,
797 unsigned IndexReg, unsigned Scale, SMLoc Start,
798 SMLoc End, unsigned Size, StringRef Identifier,
Coby Tayree49b37332016-11-22 09:30:29 +0000799 InlineAsmIdentifierInfo &Info,
800 bool AllowBetterSizeMatch = false);
Chad Rosier7ca135b2013-03-19 21:11:56 +0000801
Michael Zuckerman02ecd432015-12-13 17:07:23 +0000802 bool parseDirectiveEven(SMLoc L);
Kevin Enderbyce4bec82009-09-10 20:51:44 +0000803 bool ParseDirectiveWord(unsigned Size, SMLoc L);
Evan Cheng481ebb02011-07-27 00:38:12 +0000804 bool ParseDirectiveCode(StringRef IDVal, SMLoc L);
Kevin Enderbyce4bec82009-09-10 20:51:44 +0000805
David Blaikie960ea3f2014-06-08 16:18:35 +0000806 bool processInstruction(MCInst &Inst, const OperandVector &Ops);
Devang Patelde47cce2012-01-18 22:42:29 +0000807
Evgeniy Stepanov49e26252014-03-14 08:58:04 +0000808 /// Wrapper around MCStreamer::EmitInstruction(). Possibly adds
809 /// instrumentation around Inst.
David Blaikie960ea3f2014-06-08 16:18:35 +0000810 void EmitInstruction(MCInst &Inst, OperandVector &Operands, MCStreamer &Out);
Evgeniy Stepanov49e26252014-03-14 08:58:04 +0000811
Chad Rosier49963552012-10-13 00:26:04 +0000812 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
David Blaikie960ea3f2014-06-08 16:18:35 +0000813 OperandVector &Operands, MCStreamer &Out,
Tim Northover26bb14e2014-08-18 11:49:42 +0000814 uint64_t &ErrorInfo,
Craig Topper39012cc2014-03-09 18:03:14 +0000815 bool MatchingInlineAsm) override;
Chad Rosier9cb988f2012-08-09 22:04:55 +0000816
Reid Klecknerf6fb7802014-08-26 20:32:34 +0000817 void MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op, OperandVector &Operands,
818 MCStreamer &Out, bool MatchingInlineAsm);
819
Ranjeet Singh86ecbb72015-06-30 12:32:53 +0000820 bool ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo,
Reid Klecknerf6fb7802014-08-26 20:32:34 +0000821 bool MatchingInlineAsm);
822
823 bool MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
824 OperandVector &Operands, MCStreamer &Out,
825 uint64_t &ErrorInfo,
826 bool MatchingInlineAsm);
827
828 bool MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
829 OperandVector &Operands, MCStreamer &Out,
830 uint64_t &ErrorInfo,
831 bool MatchingInlineAsm);
832
Craig Topperfd38cbe2014-08-30 16:48:34 +0000833 bool OmitRegisterFromClobberLists(unsigned RegNo) override;
Nico Weber42f79db2014-07-17 20:24:55 +0000834
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000835 /// Parses AVX512 specific operand primitives: masked registers ({%k<NUM>}, {z})
836 /// and memory broadcasting ({1to<NUM>}) primitives, updating Operands vector if required.
Michael Zuckerman1bee6342016-10-18 13:52:39 +0000837 /// return false if no parsing errors occurred, true otherwise.
David Blaikie960ea3f2014-06-08 16:18:35 +0000838 bool HandleAVX512Operand(OperandVector &Operands,
839 const MCParsedAsmOperand &Op);
Elena Demikhovskyc9657012014-02-20 06:34:39 +0000840
Michael Zuckerman1bee6342016-10-18 13:52:39 +0000841 bool ParseZ(std::unique_ptr<X86Operand> &Z, const SMLoc &StartLoc);
842
Evan Chengc5e6d2f2011-07-11 03:57:24 +0000843 bool is64BitMode() const {
Evan Cheng4d1ca962011-07-08 01:53:10 +0000844 // FIXME: Can tablegen auto-generate this?
Akira Hatanakabd9fc282015-11-14 05:20:05 +0000845 return getSTI().getFeatureBits()[X86::Mode64Bit];
Evan Cheng4d1ca962011-07-08 01:53:10 +0000846 }
Craig Topper3c80d622014-01-06 04:55:54 +0000847 bool is32BitMode() const {
848 // FIXME: Can tablegen auto-generate this?
Akira Hatanakabd9fc282015-11-14 05:20:05 +0000849 return getSTI().getFeatureBits()[X86::Mode32Bit];
Craig Topper3c80d622014-01-06 04:55:54 +0000850 }
851 bool is16BitMode() const {
852 // FIXME: Can tablegen auto-generate this?
Akira Hatanakabd9fc282015-11-14 05:20:05 +0000853 return getSTI().getFeatureBits()[X86::Mode16Bit];
Craig Topper3c80d622014-01-06 04:55:54 +0000854 }
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000855 void SwitchMode(unsigned mode) {
Akira Hatanakab11ef082015-11-14 06:35:56 +0000856 MCSubtargetInfo &STI = copySTI();
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000857 FeatureBitset AllModes({X86::Mode64Bit, X86::Mode32Bit, X86::Mode16Bit});
858 FeatureBitset OldMode = STI.getFeatureBits() & AllModes;
Ranjeet Singh86ecbb72015-06-30 12:32:53 +0000859 unsigned FB = ComputeAvailableFeatures(
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000860 STI.ToggleFeature(OldMode.flip(mode)));
Evan Cheng481ebb02011-07-27 00:38:12 +0000861 setAvailableFeatures(FB);
NAKAMURA Takumia9cb5382015-09-22 11:14:39 +0000862
Michael Kupersteindb0712f2015-05-26 10:47:10 +0000863 assert(FeatureBitset({mode}) == (STI.getFeatureBits() & AllModes));
Evan Cheng481ebb02011-07-27 00:38:12 +0000864 }
Evan Cheng4d1ca962011-07-08 01:53:10 +0000865
Reid Kleckner5b37c182014-08-01 20:21:24 +0000866 unsigned getPointerWidth() {
867 if (is16BitMode()) return 16;
868 if (is32BitMode()) return 32;
869 if (is64BitMode()) return 64;
870 llvm_unreachable("invalid mode");
871 }
872
Chad Rosierc2f055d2013-04-18 16:13:18 +0000873 bool isParsingIntelSyntax() {
874 return getParser().getAssemblerDialect();
875 }
876
Daniel Dunbareefe8612010-07-19 05:44:09 +0000877 /// @name Auto-generated Matcher Functions
878 /// {
Michael J. Spencer530ce852010-10-09 11:00:50 +0000879
Chris Lattner3e4582a2010-09-06 19:11:01 +0000880#define GET_ASSEMBLER_HEADER
881#include "X86GenAsmMatcher.inc"
Michael J. Spencer530ce852010-10-09 11:00:50 +0000882
Daniel Dunbar00331992009-07-29 00:02:19 +0000883 /// }
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +0000884
885public:
Coby Tayree07a89742017-03-21 19:31:55 +0000886
Akira Hatanakab11ef082015-11-14 06:35:56 +0000887 X86AsmParser(const MCSubtargetInfo &sti, MCAsmParser &Parser,
Rafael Espindola961d4692014-11-11 05:18:41 +0000888 const MCInstrInfo &mii, const MCTargetOptions &Options)
Nirav Dave6477ce22016-09-26 19:33:36 +0000889 : MCTargetAsmParser(Options, sti), MII(mii), InstInfo(nullptr),
890 Code16GCC(false) {
Michael J. Spencer530ce852010-10-09 11:00:50 +0000891
Daniel Dunbareefe8612010-07-19 05:44:09 +0000892 // Initialize the set of available features.
Akira Hatanakabd9fc282015-11-14 05:20:05 +0000893 setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
Evgeniy Stepanov0a951b72014-04-23 11:16:03 +0000894 Instrumentation.reset(
895 CreateX86AsmInstrumentation(Options, Parser.getContext(), STI));
Daniel Dunbareefe8612010-07-19 05:44:09 +0000896 }
Evgeniy Stepanov0a951b72014-04-23 11:16:03 +0000897
Craig Topper39012cc2014-03-09 18:03:14 +0000898 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +0000899
Yuri Gorshenin3939dec2014-09-10 09:45:49 +0000900 void SetFrameRegister(unsigned RegNo) override;
901
David Blaikie960ea3f2014-06-08 16:18:35 +0000902 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
903 SMLoc NameLoc, OperandVector &Operands) override;
Kevin Enderbyce4bec82009-09-10 20:51:44 +0000904
Craig Topper39012cc2014-03-09 18:03:14 +0000905 bool ParseDirective(AsmToken DirectiveID) override;
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +0000906};
Chris Lattner4eb9df02009-07-29 06:33:53 +0000907} // end anonymous namespace
908
Sean Callanan86c11812010-01-23 00:40:33 +0000909/// @name Auto-generated Match Functions
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +0000910/// {
Sean Callanan86c11812010-01-23 00:40:33 +0000911
Chris Lattner60db0a62010-02-09 00:34:28 +0000912static unsigned MatchRegisterName(StringRef Name);
Sean Callanan86c11812010-01-23 00:40:33 +0000913
914/// }
Chris Lattner4eb9df02009-07-29 06:33:53 +0000915
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000916static bool CheckBaseRegAndIndexRegAndScale(unsigned BaseReg, unsigned IndexReg,
917 unsigned Scale, StringRef &ErrMsg) {
Kevin Enderbybc570f22014-01-23 22:34:42 +0000918 // If we have both a base register and an index register make sure they are
919 // both 64-bit or 32-bit registers.
920 // To support VSIB, IndexReg can be 128-bit or 256-bit registers.
Douglas Katzman0411e862016-10-05 15:23:35 +0000921
922 if ((BaseReg == X86::RIP && IndexReg != 0) || (IndexReg == X86::RIP)) {
923 ErrMsg = "invalid base+index expression";
924 return true;
925 }
Kevin Enderbybc570f22014-01-23 22:34:42 +0000926 if (BaseReg != 0 && IndexReg != 0) {
927 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(BaseReg) &&
928 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
929 X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg)) &&
930 IndexReg != X86::RIZ) {
931 ErrMsg = "base register is 64-bit, but index register is not";
932 return true;
933 }
934 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(BaseReg) &&
935 (X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg) ||
936 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) &&
937 IndexReg != X86::EIZ){
938 ErrMsg = "base register is 32-bit, but index register is not";
939 return true;
940 }
941 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg)) {
942 if (X86MCRegisterClasses[X86::GR32RegClassID].contains(IndexReg) ||
943 X86MCRegisterClasses[X86::GR64RegClassID].contains(IndexReg)) {
944 ErrMsg = "base register is 16-bit, but index register is not";
945 return true;
946 }
947 if (((BaseReg == X86::BX || BaseReg == X86::BP) &&
948 IndexReg != X86::SI && IndexReg != X86::DI) ||
949 ((BaseReg == X86::SI || BaseReg == X86::DI) &&
950 IndexReg != X86::BX && IndexReg != X86::BP)) {
951 ErrMsg = "invalid 16-bit base/index register combination";
952 return true;
953 }
954 }
955 }
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +0000956 return checkScale(Scale, ErrMsg);
Kevin Enderbybc570f22014-01-23 22:34:42 +0000957}
958
Devang Patel4a6e7782012-01-12 18:03:40 +0000959bool X86AsmParser::ParseRegister(unsigned &RegNo,
960 SMLoc &StartLoc, SMLoc &EndLoc) {
Rafael Espindola961d4692014-11-11 05:18:41 +0000961 MCAsmParser &Parser = getParser();
Chris Lattnercc2ad082010-01-15 18:27:19 +0000962 RegNo = 0;
Benjamin Kramere3d658b2012-09-07 14:51:35 +0000963 const AsmToken &PercentTok = Parser.getTok();
964 StartLoc = PercentTok.getLoc();
965
966 // If we encounter a %, ignore it. This code handles registers with and
967 // without the prefix, unprefixed registers can occur in cfi directives.
968 if (!isParsingIntelSyntax() && PercentTok.is(AsmToken::Percent))
Devang Patel41b9dde2012-01-17 18:00:18 +0000969 Parser.Lex(); // Eat percent token.
Kevin Enderby7d912182009-09-03 17:15:07 +0000970
Sean Callanan936b0d32010-01-19 21:44:56 +0000971 const AsmToken &Tok = Parser.getTok();
Jordan Rosee8f1eae2013-01-07 19:00:49 +0000972 EndLoc = Tok.getEndLoc();
973
Devang Patelce6a2ca2012-01-20 22:32:05 +0000974 if (Tok.isNot(AsmToken::Identifier)) {
Reid Klecknerc990b5d2017-07-24 20:48:15 +0000975 if (isParsingIntelSyntax()) return true;
Benjamin Kramer1930b002011-10-16 12:10:27 +0000976 return Error(StartLoc, "invalid register name",
Jordan Rosee8f1eae2013-01-07 19:00:49 +0000977 SMRange(StartLoc, EndLoc));
Devang Patelce6a2ca2012-01-20 22:32:05 +0000978 }
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +0000979
Kevin Enderby7d912182009-09-03 17:15:07 +0000980 RegNo = MatchRegisterName(Tok.getString());
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +0000981
Chris Lattner1261b812010-09-22 04:11:10 +0000982 // If the match failed, try the register name as lowercase.
983 if (RegNo == 0)
Benjamin Kramer20baffb2011-11-06 20:37:06 +0000984 RegNo = MatchRegisterName(Tok.getString().lower());
Michael J. Spencer530ce852010-10-09 11:00:50 +0000985
Michael Kupersteincdb076b2015-07-30 10:10:25 +0000986 // The "flags" register cannot be referenced directly.
987 // Treat it as an identifier instead.
988 if (isParsingInlineAsm() && isParsingIntelSyntax() && RegNo == X86::EFLAGS)
989 RegNo = 0;
990
Evan Chengeda1d4f2011-07-27 23:22:03 +0000991 if (!is64BitMode()) {
Eric Christopherc0a5aae2013-12-20 02:04:49 +0000992 // FIXME: This should be done using Requires<Not64BitMode> and
Evan Chengeda1d4f2011-07-27 23:22:03 +0000993 // Requires<In64BitMode> so "eiz" usage in 64-bit instructions can be also
994 // checked.
995 // FIXME: Check AH, CH, DH, BH cannot be used in an instruction requiring a
996 // REX prefix.
997 if (RegNo == X86::RIZ ||
998 X86MCRegisterClasses[X86::GR64RegClassID].contains(RegNo) ||
999 X86II::isX86_64NonExtLowByteReg(RegNo) ||
Craig Topper6acca802016-08-27 17:13:37 +00001000 X86II::isX86_64ExtendedReg(RegNo))
Benjamin Kramer1930b002011-10-16 12:10:27 +00001001 return Error(StartLoc, "register %"
1002 + Tok.getString() + " is only available in 64-bit mode",
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001003 SMRange(StartLoc, EndLoc));
Craig Topper29c22732016-02-26 05:29:32 +00001004 } else if (!getSTI().getFeatureBits()[X86::FeatureAVX512]) {
1005 if (X86II::is32ExtendedReg(RegNo))
1006 return Error(StartLoc, "register %"
Craig Topperd50b5f82016-02-26 06:50:24 +00001007 + Tok.getString() + " is only available with AVX512",
Craig Topper29c22732016-02-26 05:29:32 +00001008 SMRange(StartLoc, EndLoc));
Evan Chengeda1d4f2011-07-27 23:22:03 +00001009 }
Bruno Cardoso Lopes306a1f92010-07-24 00:06:39 +00001010
Chris Lattner1261b812010-09-22 04:11:10 +00001011 // Parse "%st" as "%st(0)" and "%st(1)", which is multiple tokens.
1012 if (RegNo == 0 && (Tok.getString() == "st" || Tok.getString() == "ST")) {
Chris Lattnerd00faaa2010-02-09 00:49:22 +00001013 RegNo = X86::ST0;
Chris Lattnerd00faaa2010-02-09 00:49:22 +00001014 Parser.Lex(); // Eat 'st'
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001015
Chris Lattnerd00faaa2010-02-09 00:49:22 +00001016 // Check to see if we have '(4)' after %st.
1017 if (getLexer().isNot(AsmToken::LParen))
1018 return false;
1019 // Lex the paren.
1020 getParser().Lex();
1021
1022 const AsmToken &IntTok = Parser.getTok();
1023 if (IntTok.isNot(AsmToken::Integer))
1024 return Error(IntTok.getLoc(), "expected stack index");
1025 switch (IntTok.getIntVal()) {
1026 case 0: RegNo = X86::ST0; break;
1027 case 1: RegNo = X86::ST1; break;
1028 case 2: RegNo = X86::ST2; break;
1029 case 3: RegNo = X86::ST3; break;
1030 case 4: RegNo = X86::ST4; break;
1031 case 5: RegNo = X86::ST5; break;
1032 case 6: RegNo = X86::ST6; break;
1033 case 7: RegNo = X86::ST7; break;
1034 default: return Error(IntTok.getLoc(), "invalid stack index");
1035 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001036
Chris Lattnerd00faaa2010-02-09 00:49:22 +00001037 if (getParser().Lex().isNot(AsmToken::RParen))
1038 return Error(Parser.getTok().getLoc(), "expected ')'");
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001039
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001040 EndLoc = Parser.getTok().getEndLoc();
Chris Lattnerd00faaa2010-02-09 00:49:22 +00001041 Parser.Lex(); // Eat ')'
1042 return false;
1043 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001044
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001045 EndLoc = Parser.getTok().getEndLoc();
1046
Chris Lattner80486622010-06-24 07:29:18 +00001047 // If this is "db[0-7]", match it as an alias
1048 // for dr[0-7].
1049 if (RegNo == 0 && Tok.getString().size() == 3 &&
1050 Tok.getString().startswith("db")) {
1051 switch (Tok.getString()[2]) {
1052 case '0': RegNo = X86::DR0; break;
1053 case '1': RegNo = X86::DR1; break;
1054 case '2': RegNo = X86::DR2; break;
1055 case '3': RegNo = X86::DR3; break;
1056 case '4': RegNo = X86::DR4; break;
1057 case '5': RegNo = X86::DR5; break;
1058 case '6': RegNo = X86::DR6; break;
1059 case '7': RegNo = X86::DR7; break;
1060 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001061
Chris Lattner80486622010-06-24 07:29:18 +00001062 if (RegNo != 0) {
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001063 EndLoc = Parser.getTok().getEndLoc();
Chris Lattner80486622010-06-24 07:29:18 +00001064 Parser.Lex(); // Eat it.
1065 return false;
1066 }
1067 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001068
Devang Patelce6a2ca2012-01-20 22:32:05 +00001069 if (RegNo == 0) {
Devang Patel9a9bb5c2012-01-30 20:02:42 +00001070 if (isParsingIntelSyntax()) return true;
Benjamin Kramer1930b002011-10-16 12:10:27 +00001071 return Error(StartLoc, "invalid register name",
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001072 SMRange(StartLoc, EndLoc));
Devang Patelce6a2ca2012-01-20 22:32:05 +00001073 }
Daniel Dunbar00331992009-07-29 00:02:19 +00001074
Sean Callanana83fd7d2010-01-19 20:27:46 +00001075 Parser.Lex(); // Eat identifier token.
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00001076 return false;
Daniel Dunbar71475772009-07-17 20:42:00 +00001077}
1078
Yuri Gorshenin3939dec2014-09-10 09:45:49 +00001079void X86AsmParser::SetFrameRegister(unsigned RegNo) {
Yuri Gorshenine8c81fd2014-10-07 11:03:09 +00001080 Instrumentation->SetInitialFrameRegister(RegNo);
Yuri Gorshenin3939dec2014-09-10 09:45:49 +00001081}
1082
David Blaikie960ea3f2014-06-08 16:18:35 +00001083std::unique_ptr<X86Operand> X86AsmParser::DefaultMemSIOperand(SMLoc Loc) {
Nirav Dave6477ce22016-09-26 19:33:36 +00001084 bool Parse32 = is32BitMode() || Code16GCC;
1085 unsigned Basereg = is64BitMode() ? X86::RSI : (Parse32 ? X86::ESI : X86::SI);
Jim Grosbach13760bd2015-05-30 01:25:56 +00001086 const MCExpr *Disp = MCConstantExpr::create(0, getContext());
Craig Topper055845f2015-01-02 07:02:25 +00001087 return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
Nirav Dave6477ce22016-09-26 19:33:36 +00001088 /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
Craig Topper055845f2015-01-02 07:02:25 +00001089 Loc, Loc, 0);
David Woodhouse2ef8d9c2014-01-22 15:08:08 +00001090}
1091
David Blaikie960ea3f2014-06-08 16:18:35 +00001092std::unique_ptr<X86Operand> X86AsmParser::DefaultMemDIOperand(SMLoc Loc) {
Nirav Dave6477ce22016-09-26 19:33:36 +00001093 bool Parse32 = is32BitMode() || Code16GCC;
1094 unsigned Basereg = is64BitMode() ? X86::RDI : (Parse32 ? X86::EDI : X86::DI);
Jim Grosbach13760bd2015-05-30 01:25:56 +00001095 const MCExpr *Disp = MCConstantExpr::create(0, getContext());
Craig Topper055845f2015-01-02 07:02:25 +00001096 return X86Operand::CreateMem(getPointerWidth(), /*SegReg=*/0, Disp,
Nirav Dave6477ce22016-09-26 19:33:36 +00001097 /*BaseReg=*/Basereg, /*IndexReg=*/0, /*Scale=*/1,
Craig Topper055845f2015-01-02 07:02:25 +00001098 Loc, Loc, 0);
David Woodhouseb33c2ef2014-01-22 15:08:21 +00001099}
1100
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001101bool X86AsmParser::IsSIReg(unsigned Reg) {
1102 switch (Reg) {
Craig Topper4d187632016-02-26 05:29:39 +00001103 default: llvm_unreachable("Only (R|E)SI and (R|E)DI are expected!");
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001104 case X86::RSI:
1105 case X86::ESI:
1106 case X86::SI:
1107 return true;
1108 case X86::RDI:
1109 case X86::EDI:
1110 case X86::DI:
1111 return false;
1112 }
1113}
1114
1115unsigned X86AsmParser::GetSIDIForRegClass(unsigned RegClassID, unsigned Reg,
1116 bool IsSIReg) {
1117 switch (RegClassID) {
Craig Topper4d187632016-02-26 05:29:39 +00001118 default: llvm_unreachable("Unexpected register class");
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001119 case X86::GR64RegClassID:
1120 return IsSIReg ? X86::RSI : X86::RDI;
1121 case X86::GR32RegClassID:
1122 return IsSIReg ? X86::ESI : X86::EDI;
1123 case X86::GR16RegClassID:
1124 return IsSIReg ? X86::SI : X86::DI;
1125 }
1126}
1127
Michael Kupersteinffcc7662015-07-23 10:23:48 +00001128void X86AsmParser::AddDefaultSrcDestOperands(
1129 OperandVector& Operands, std::unique_ptr<llvm::MCParsedAsmOperand> &&Src,
1130 std::unique_ptr<llvm::MCParsedAsmOperand> &&Dst) {
1131 if (isParsingIntelSyntax()) {
1132 Operands.push_back(std::move(Dst));
1133 Operands.push_back(std::move(Src));
1134 }
1135 else {
1136 Operands.push_back(std::move(Src));
1137 Operands.push_back(std::move(Dst));
1138 }
1139}
1140
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001141bool X86AsmParser::VerifyAndAdjustOperands(OperandVector &OrigOperands,
1142 OperandVector &FinalOperands) {
1143
1144 if (OrigOperands.size() > 1) {
Craig Topperd55f4bc2016-02-16 07:45:07 +00001145 // Check if sizes match, OrigOperands also contains the instruction name
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001146 assert(OrigOperands.size() == FinalOperands.size() + 1 &&
Craig Topperd55f4bc2016-02-16 07:45:07 +00001147 "Operand size mismatch");
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001148
Marina Yatsinaff262fa2016-01-21 11:37:06 +00001149 SmallVector<std::pair<SMLoc, std::string>, 2> Warnings;
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001150 // Verify types match
1151 int RegClassID = -1;
1152 for (unsigned int i = 0; i < FinalOperands.size(); ++i) {
1153 X86Operand &OrigOp = static_cast<X86Operand &>(*OrigOperands[i + 1]);
1154 X86Operand &FinalOp = static_cast<X86Operand &>(*FinalOperands[i]);
1155
1156 if (FinalOp.isReg() &&
1157 (!OrigOp.isReg() || FinalOp.getReg() != OrigOp.getReg()))
1158 // Return false and let a normal complaint about bogus operands happen
1159 return false;
1160
1161 if (FinalOp.isMem()) {
1162
1163 if (!OrigOp.isMem())
1164 // Return false and let a normal complaint about bogus operands happen
1165 return false;
1166
1167 unsigned OrigReg = OrigOp.Mem.BaseReg;
1168 unsigned FinalReg = FinalOp.Mem.BaseReg;
1169
1170 // If we've already encounterd a register class, make sure all register
1171 // bases are of the same register class
1172 if (RegClassID != -1 &&
1173 !X86MCRegisterClasses[RegClassID].contains(OrigReg)) {
1174 return Error(OrigOp.getStartLoc(),
1175 "mismatching source and destination index registers");
1176 }
1177
1178 if (X86MCRegisterClasses[X86::GR64RegClassID].contains(OrigReg))
1179 RegClassID = X86::GR64RegClassID;
1180 else if (X86MCRegisterClasses[X86::GR32RegClassID].contains(OrigReg))
1181 RegClassID = X86::GR32RegClassID;
1182 else if (X86MCRegisterClasses[X86::GR16RegClassID].contains(OrigReg))
1183 RegClassID = X86::GR16RegClassID;
Marina Yatsina701938d2016-01-20 14:03:47 +00001184 else
Craig Topper5a62f7e2016-02-16 07:28:03 +00001185 // Unexpected register class type
Marina Yatsina701938d2016-01-20 14:03:47 +00001186 // Return false and let a normal complaint about bogus operands happen
1187 return false;
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001188
1189 bool IsSI = IsSIReg(FinalReg);
1190 FinalReg = GetSIDIForRegClass(RegClassID, FinalReg, IsSI);
1191
1192 if (FinalReg != OrigReg) {
1193 std::string RegName = IsSI ? "ES:(R|E)SI" : "ES:(R|E)DI";
Marina Yatsinaff262fa2016-01-21 11:37:06 +00001194 Warnings.push_back(std::make_pair(
1195 OrigOp.getStartLoc(),
1196 "memory operand is only for determining the size, " + RegName +
1197 " will be used for the location"));
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001198 }
1199
1200 FinalOp.Mem.Size = OrigOp.Mem.Size;
1201 FinalOp.Mem.SegReg = OrigOp.Mem.SegReg;
1202 FinalOp.Mem.BaseReg = FinalReg;
1203 }
1204 }
1205
Marina Yatsinaff262fa2016-01-21 11:37:06 +00001206 // Produce warnings only if all the operands passed the adjustment - prevent
1207 // legal cases like "movsd (%rax), %xmm0" mistakenly produce warnings
Craig Topper16d7eb22016-02-16 07:45:04 +00001208 for (auto &WarningMsg : Warnings) {
1209 Warning(WarningMsg.first, WarningMsg.second);
Marina Yatsinaff262fa2016-01-21 11:37:06 +00001210 }
1211
1212 // Remove old operands
Marina Yatsinab9f4f622016-01-19 15:37:56 +00001213 for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1214 OrigOperands.pop_back();
1215 }
1216 // OrigOperands.append(FinalOperands.begin(), FinalOperands.end());
1217 for (unsigned int i = 0; i < FinalOperands.size(); ++i)
1218 OrigOperands.push_back(std::move(FinalOperands[i]));
1219
1220 return false;
1221}
1222
David Blaikie960ea3f2014-06-08 16:18:35 +00001223std::unique_ptr<X86Operand> X86AsmParser::ParseOperand() {
Devang Patel9a9bb5c2012-01-30 20:02:42 +00001224 if (isParsingIntelSyntax())
Devang Patel46831de2012-01-12 01:36:43 +00001225 return ParseIntelOperand();
1226 return ParseATTOperand();
1227}
1228
Devang Patel41b9dde2012-01-17 18:00:18 +00001229/// getIntelMemOperandSize - Return intel memory operand size.
1230static unsigned getIntelMemOperandSize(StringRef OpStr) {
Chad Rosierb6b8e962012-09-11 21:10:25 +00001231 unsigned Size = StringSwitch<unsigned>(OpStr)
Chad Rosierab53b4f2012-09-12 18:24:26 +00001232 .Cases("BYTE", "byte", 8)
1233 .Cases("WORD", "word", 16)
1234 .Cases("DWORD", "dword", 32)
Marina Yatsina497d44a2015-12-07 13:09:20 +00001235 .Cases("FWORD", "fword", 48)
Chad Rosierab53b4f2012-09-12 18:24:26 +00001236 .Cases("QWORD", "qword", 64)
Michael Zuckerman9beca2e2015-08-24 10:26:54 +00001237 .Cases("MMWORD","mmword", 64)
Chad Rosierab53b4f2012-09-12 18:24:26 +00001238 .Cases("XWORD", "xword", 80)
Michael Kuperstein69e40a42015-07-19 11:03:08 +00001239 .Cases("TBYTE", "tbyte", 80)
Chad Rosierab53b4f2012-09-12 18:24:26 +00001240 .Cases("XMMWORD", "xmmword", 128)
1241 .Cases("YMMWORD", "ymmword", 256)
Craig Topper9ac290a2014-01-17 07:37:39 +00001242 .Cases("ZMMWORD", "zmmword", 512)
Craig Topper2d4b3c92014-01-17 07:44:10 +00001243 .Cases("OPAQUE", "opaque", -1U) // needs to be non-zero, but doesn't matter
Chad Rosierb6b8e962012-09-11 21:10:25 +00001244 .Default(0);
1245 return Size;
Devang Patel46831de2012-01-12 01:36:43 +00001246}
1247
David Blaikie960ea3f2014-06-08 16:18:35 +00001248std::unique_ptr<X86Operand> X86AsmParser::CreateMemForInlineAsm(
1249 unsigned SegReg, const MCExpr *Disp, unsigned BaseReg, unsigned IndexReg,
1250 unsigned Scale, SMLoc Start, SMLoc End, unsigned Size, StringRef Identifier,
Coby Tayree49b37332016-11-22 09:30:29 +00001251 InlineAsmIdentifierInfo &Info, bool AllowBetterSizeMatch) {
Reid Kleckner5b37c182014-08-01 20:21:24 +00001252 // If we found a decl other than a VarDecl, then assume it is a FuncDecl or
1253 // some other label reference.
Eric Christopheradfe5362017-07-25 19:22:09 +00001254 if (isa<MCSymbolRefExpr>(Disp) && Info.OpDecl && !Info.IsVarDecl) {
Reid Kleckner5b37c182014-08-01 20:21:24 +00001255 // Insert an explicit size if the user didn't have one.
1256 if (!Size) {
1257 Size = getPointerWidth();
Craig Topper7d5b2312015-10-10 05:25:02 +00001258 InstInfo->AsmRewrites->emplace_back(AOK_SizeDirective, Start,
1259 /*Len=*/0, Size);
Reid Kleckner5b37c182014-08-01 20:21:24 +00001260 }
1261
1262 // Create an absolute memory reference in order to match against
1263 // instructions taking a PC relative operand.
Craig Topper055845f2015-01-02 07:02:25 +00001264 return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size,
1265 Identifier, Info.OpDecl);
Reid Klecknerd84e70e2014-03-04 00:33:17 +00001266 }
1267
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00001268
Reid Klecknerd84e70e2014-03-04 00:33:17 +00001269 // We either have a direct symbol reference, or an offset from a symbol. The
1270 // parser always puts the symbol on the LHS, so look there for size
1271 // calculation purposes.
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00001272 unsigned FrontendSize = 0;
Reid Klecknerd84e70e2014-03-04 00:33:17 +00001273 const MCBinaryExpr *BinOp = dyn_cast<MCBinaryExpr>(Disp);
1274 bool IsSymRef =
1275 isa<MCSymbolRefExpr>(BinOp ? BinOp->getLHS() : Disp);
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00001276 if (IsSymRef && !Size && Info.Type)
1277 FrontendSize = Info.Type * 8; // Size is in terms of bits in this context.
Chad Rosier7ca135b2013-03-19 21:11:56 +00001278
Chad Rosier7ca135b2013-03-19 21:11:56 +00001279 // When parsing inline assembly we set the base register to a non-zero value
Chad Rosier175d0ae2013-04-12 18:21:18 +00001280 // if we don't know the actual value at this time. This is necessary to
Chad Rosier7ca135b2013-03-19 21:11:56 +00001281 // get the matching correct in some cases.
Chad Rosier175d0ae2013-04-12 18:21:18 +00001282 BaseReg = BaseReg ? BaseReg : 1;
Craig Topper055845f2015-01-02 07:02:25 +00001283 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
1284 IndexReg, Scale, Start, End, Size, Identifier,
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00001285 Info.OpDecl, FrontendSize);
Chad Rosier7ca135b2013-03-19 21:11:56 +00001286}
1287
Chad Rosierd383db52013-04-12 20:20:54 +00001288static void
Craig Topper7143d802015-10-10 05:25:06 +00001289RewriteIntelBracExpression(SmallVectorImpl<AsmRewrite> &AsmRewrites,
Chad Rosierd383db52013-04-12 20:20:54 +00001290 StringRef SymName, int64_t ImmDisp,
1291 int64_t FinalImmDisp, SMLoc &BracLoc,
1292 SMLoc &StartInBrac, SMLoc &End) {
1293 // Remove the '[' and ']' from the IR string.
Craig Topper7143d802015-10-10 05:25:06 +00001294 AsmRewrites.emplace_back(AOK_Skip, BracLoc, 1);
1295 AsmRewrites.emplace_back(AOK_Skip, End, 1);
Chad Rosierd383db52013-04-12 20:20:54 +00001296
1297 // If ImmDisp is non-zero, then we parsed a displacement before the
1298 // bracketed expression (i.e., ImmDisp [ BaseReg + Scale*IndexReg + Disp])
1299 // If ImmDisp doesn't match the displacement computed by the state machine
1300 // then we have an additional displacement in the bracketed expression.
1301 if (ImmDisp != FinalImmDisp) {
1302 if (ImmDisp) {
1303 // We have an immediate displacement before the bracketed expression.
1304 // Adjust this to match the final immediate displacement.
1305 bool Found = false;
Craig Topper7143d802015-10-10 05:25:06 +00001306 for (AsmRewrite &AR : AsmRewrites) {
1307 if (AR.Loc.getPointer() > BracLoc.getPointer())
Chad Rosierd383db52013-04-12 20:20:54 +00001308 continue;
Craig Topper7143d802015-10-10 05:25:06 +00001309 if (AR.Kind == AOK_ImmPrefix || AR.Kind == AOK_Imm) {
Chad Rosierbfb70992013-04-17 00:11:46 +00001310 assert (!Found && "ImmDisp already rewritten.");
Craig Topper7143d802015-10-10 05:25:06 +00001311 AR.Kind = AOK_Imm;
1312 AR.Len = BracLoc.getPointer() - AR.Loc.getPointer();
1313 AR.Val = FinalImmDisp;
Chad Rosierd383db52013-04-12 20:20:54 +00001314 Found = true;
1315 break;
1316 }
1317 }
1318 assert (Found && "Unable to rewrite ImmDisp.");
Duncan Sands0480b9b2013-05-13 07:50:47 +00001319 (void)Found;
Chad Rosierd383db52013-04-12 20:20:54 +00001320 } else {
1321 // We have a symbolic and an immediate displacement, but no displacement
Chad Rosierbfb70992013-04-17 00:11:46 +00001322 // before the bracketed expression. Put the immediate displacement
Chad Rosierd383db52013-04-12 20:20:54 +00001323 // before the bracketed expression.
Craig Topper7143d802015-10-10 05:25:06 +00001324 AsmRewrites.emplace_back(AOK_Imm, BracLoc, 0, FinalImmDisp);
Chad Rosierd383db52013-04-12 20:20:54 +00001325 }
1326 }
1327 // Remove all the ImmPrefix rewrites within the brackets.
Coby Tayree07a89742017-03-21 19:31:55 +00001328 // We may have some Imm rewrties as a result of an operator applying,
1329 // remove them as well
Craig Topper7143d802015-10-10 05:25:06 +00001330 for (AsmRewrite &AR : AsmRewrites) {
1331 if (AR.Loc.getPointer() < StartInBrac.getPointer())
Chad Rosierd383db52013-04-12 20:20:54 +00001332 continue;
Coby Tayree07a89742017-03-21 19:31:55 +00001333 if (AR.Kind == AOK_ImmPrefix || AR.Kind == AOK_Imm)
Craig Topper7143d802015-10-10 05:25:06 +00001334 AR.Kind = AOK_Delete;
Chad Rosierd383db52013-04-12 20:20:54 +00001335 }
1336 const char *SymLocPtr = SymName.data();
Michael Liao5bf95782014-12-04 05:20:33 +00001337 // Skip everything before the symbol.
Chad Rosierd383db52013-04-12 20:20:54 +00001338 if (unsigned Len = SymLocPtr - StartInBrac.getPointer()) {
1339 assert(Len > 0 && "Expected a non-negative length.");
Craig Topper7d5b2312015-10-10 05:25:02 +00001340 AsmRewrites.emplace_back(AOK_Skip, StartInBrac, Len);
Chad Rosierd383db52013-04-12 20:20:54 +00001341 }
1342 // Skip everything after the symbol.
1343 if (unsigned Len = End.getPointer() - (SymLocPtr + SymName.size())) {
1344 SMLoc Loc = SMLoc::getFromPointer(SymLocPtr + SymName.size());
1345 assert(Len > 0 && "Expected a non-negative length.");
Craig Topper7d5b2312015-10-10 05:25:02 +00001346 AsmRewrites.emplace_back(AOK_Skip, Loc, Len);
Chad Rosierd383db52013-04-12 20:20:54 +00001347 }
1348}
1349
Coby Tayree2cb497a2017-04-04 14:43:23 +00001350// Some binary bitwise operators have a named synonymous
1351// Query a candidate string for being such a named operator
1352// and if so - invoke the appropriate handler
1353bool X86AsmParser::ParseIntelNamedOperator(StringRef Name, IntelExprStateMachine &SM) {
1354 // A named operator should be either lower or upper case, but not a mix
1355 if (Name.compare(Name.lower()) && Name.compare(Name.upper()))
1356 return false;
1357 if (Name.equals_lower("not"))
1358 SM.onNot();
1359 else if (Name.equals_lower("or"))
1360 SM.onOr();
1361 else if (Name.equals_lower("shl"))
1362 SM.onLShift();
1363 else if (Name.equals_lower("shr"))
1364 SM.onRShift();
1365 else if (Name.equals_lower("xor"))
1366 SM.onXor();
1367 else if (Name.equals_lower("and"))
1368 SM.onAnd();
Coby Tayree41a5b552017-06-27 16:58:27 +00001369 else if (Name.equals_lower("mod"))
1370 SM.onMod();
Coby Tayree2cb497a2017-04-04 14:43:23 +00001371 else
1372 return false;
1373 return true;
1374}
1375
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001376bool X86AsmParser::ParseIntelExpression(IntelExprStateMachine &SM, SMLoc &End) {
Rafael Espindola961d4692014-11-11 05:18:41 +00001377 MCAsmParser &Parser = getParser();
Chad Rosier6844ea02012-10-24 22:13:37 +00001378 const AsmToken &Tok = Parser.getTok();
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +00001379 StringRef ErrMsg;
Chad Rosier51afe632012-06-27 22:34:28 +00001380
Marina Yatsina8dfd5cb2015-12-24 12:09:51 +00001381 AsmToken::TokenKind PrevTK = AsmToken::Error;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001382 bool Done = false;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001383 while (!Done) {
1384 bool UpdateLocLex = true;
1385
Andrew V. Tischenkofdb264e2017-05-26 13:23:34 +00001386 AsmToken::TokenKind TK = getLexer().getKind();
Chad Rosier5c118fd2013-01-14 22:31:35 +00001387 // The period in the dot operator (e.g., [ebx].foo.bar) is parsed as an
1388 // identifier. Don't try an parse it as a register.
Andrew V. Tischenkofdb264e2017-05-26 13:23:34 +00001389 if (PrevTK != AsmToken::Error && Tok.getString().startswith(".") &&
1390 TK != AsmToken::Identifier)
Chad Rosier5c118fd2013-01-14 22:31:35 +00001391 break;
Michael Liao5bf95782014-12-04 05:20:33 +00001392
Chad Rosierbfb70992013-04-17 00:11:46 +00001393 // If we're parsing an immediate expression, we don't expect a '['.
1394 if (SM.getStopOnLBrac() && getLexer().getKind() == AsmToken::LBrac)
1395 break;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001396
David Majnemer6a5b8122014-06-19 01:25:43 +00001397 switch (TK) {
Chad Rosier5c118fd2013-01-14 22:31:35 +00001398 default: {
1399 if (SM.isValidEndState()) {
1400 Done = true;
1401 break;
1402 }
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001403 return Error(Tok.getLoc(), "unknown token in expression");
Chad Rosier5c118fd2013-01-14 22:31:35 +00001404 }
Chad Rosierbfb70992013-04-17 00:11:46 +00001405 case AsmToken::EndOfStatement: {
1406 Done = true;
1407 break;
1408 }
David Majnemer6a5b8122014-06-19 01:25:43 +00001409 case AsmToken::String:
Chad Rosier5c118fd2013-01-14 22:31:35 +00001410 case AsmToken::Identifier: {
Chad Rosier175d0ae2013-04-12 18:21:18 +00001411 // This could be a register or a symbolic displacement.
1412 unsigned TmpReg;
Chad Rosier95ce8892013-04-19 18:39:50 +00001413 const MCExpr *Val;
Chad Rosier152749c2013-04-12 18:54:20 +00001414 SMLoc IdentLoc = Tok.getLoc();
1415 StringRef Identifier = Tok.getString();
Coby Tayree07a89742017-03-21 19:31:55 +00001416 UpdateLocLex = false;
David Majnemer6a5b8122014-06-19 01:25:43 +00001417 if (TK != AsmToken::String && !ParseRegister(TmpReg, IdentLoc, End)) {
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +00001418 if (SM.onRegister(TmpReg, ErrMsg))
1419 return Error(Tok.getLoc(), ErrMsg);
Coby Tayree2cb497a2017-04-04 14:43:23 +00001420 } else if (ParseIntelNamedOperator(Identifier, SM)) {
1421 UpdateLocLex = true;
Coby Tayree07a89742017-03-21 19:31:55 +00001422 } else if (!isParsingInlineAsm()) {
1423 if (getParser().parsePrimaryExpr(Val, End))
1424 return Error(Tok.getLoc(), "Unexpected identifier!");
Chad Rosier95ce8892013-04-19 18:39:50 +00001425 SM.onIdentifierExpr(Val, Identifier);
Coby Tayree07a89742017-03-21 19:31:55 +00001426 } else if (unsigned OpKind = IdentifyIntelOperator(Identifier)) {
1427 if (OpKind == IOK_OFFSET)
1428 return Error(IdentLoc, "Dealing OFFSET operator as part of"
1429 "a compound immediate expression is yet to be supported");
Eric Christopheradfe5362017-07-25 19:22:09 +00001430 int64_t Val = ParseIntelOperator(OpKind);
Coby Tayree07a89742017-03-21 19:31:55 +00001431 if (!Val)
1432 return true;
Coby Tayree07a89742017-03-21 19:31:55 +00001433 if (SM.onInteger(Val, ErrMsg))
1434 return Error(IdentLoc, ErrMsg);
1435 } else if (Identifier.find('.') != StringRef::npos &&
1436 PrevTK == AsmToken::RBrac) {
1437 return false;
1438 } else {
Eric Christopheradfe5362017-07-25 19:22:09 +00001439 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
1440 if (ParseIntelIdentifier(Val, Identifier, Info,
Coby Tayree07a89742017-03-21 19:31:55 +00001441 /*Unevaluated=*/false, End))
Eric Christopheradfe5362017-07-25 19:22:09 +00001442 return true;
1443 SM.onIdentifierExpr(Val, Identifier);
Chad Rosier5c118fd2013-01-14 22:31:35 +00001444 }
Coby Tayree07a89742017-03-21 19:31:55 +00001445 break;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001446 }
Kevin Enderby36eba252013-12-19 23:16:14 +00001447 case AsmToken::Integer: {
Chad Rosierbfb70992013-04-17 00:11:46 +00001448 if (isParsingInlineAsm() && SM.getAddImmPrefix())
Craig Topper7d5b2312015-10-10 05:25:02 +00001449 InstInfo->AsmRewrites->emplace_back(AOK_ImmPrefix, Tok.getLoc());
Kevin Enderby36eba252013-12-19 23:16:14 +00001450 // Look for 'b' or 'f' following an Integer as a directional label
1451 SMLoc Loc = getTok().getLoc();
1452 int64_t IntVal = getTok().getIntVal();
1453 End = consumeToken();
1454 UpdateLocLex = false;
1455 if (getLexer().getKind() == AsmToken::Identifier) {
1456 StringRef IDVal = getTok().getString();
1457 if (IDVal == "f" || IDVal == "b") {
1458 MCSymbol *Sym =
Jim Grosbach6f482002015-05-18 18:43:14 +00001459 getContext().getDirectionalLocalSymbol(IntVal, IDVal == "b");
Kevin Enderby36eba252013-12-19 23:16:14 +00001460 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
Michael Liao5bf95782014-12-04 05:20:33 +00001461 const MCExpr *Val =
NAKAMURA Takumi0a7d0ad2015-09-22 11:15:07 +00001462 MCSymbolRefExpr::create(Sym, Variant, getContext());
Kevin Enderby36eba252013-12-19 23:16:14 +00001463 if (IDVal == "b" && Sym->isUndefined())
1464 return Error(Loc, "invalid reference to undefined symbol");
1465 StringRef Identifier = Sym->getName();
1466 SM.onIdentifierExpr(Val, Identifier);
1467 End = consumeToken();
1468 } else {
Kevin Enderby9d117022014-01-23 21:52:41 +00001469 if (SM.onInteger(IntVal, ErrMsg))
1470 return Error(Loc, ErrMsg);
Kevin Enderby36eba252013-12-19 23:16:14 +00001471 }
1472 } else {
Kevin Enderby9d117022014-01-23 21:52:41 +00001473 if (SM.onInteger(IntVal, ErrMsg))
1474 return Error(Loc, ErrMsg);
Kevin Enderby36eba252013-12-19 23:16:14 +00001475 }
Chad Rosier5c118fd2013-01-14 22:31:35 +00001476 break;
Kevin Enderby36eba252013-12-19 23:16:14 +00001477 }
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +00001478 case AsmToken::Plus:
1479 if (SM.onPlus(ErrMsg))
1480 return Error(getTok().getLoc(), ErrMsg);
1481 break;
1482 case AsmToken::Minus:
1483 if (SM.onMinus(ErrMsg))
1484 return Error(getTok().getLoc(), ErrMsg);
1485 break;
Ehsan Akhgari4103da62014-07-04 19:13:05 +00001486 case AsmToken::Tilde: SM.onNot(); break;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001487 case AsmToken::Star: SM.onStar(); break;
Chad Rosier4a7005e2013-04-05 16:28:55 +00001488 case AsmToken::Slash: SM.onDivide(); break;
Kevin Enderby2e13b1c2014-01-15 19:05:24 +00001489 case AsmToken::Pipe: SM.onOr(); break;
Michael Kupersteine3de07a2015-06-14 12:59:45 +00001490 case AsmToken::Caret: SM.onXor(); break;
Kevin Enderby2e13b1c2014-01-15 19:05:24 +00001491 case AsmToken::Amp: SM.onAnd(); break;
Kevin Enderbyd6b10712014-02-06 01:21:15 +00001492 case AsmToken::LessLess:
1493 SM.onLShift(); break;
1494 case AsmToken::GreaterGreater:
1495 SM.onRShift(); break;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001496 case AsmToken::LBrac: SM.onLBrac(); break;
1497 case AsmToken::RBrac: SM.onRBrac(); break;
Chad Rosier4a7005e2013-04-05 16:28:55 +00001498 case AsmToken::LParen: SM.onLParen(); break;
1499 case AsmToken::RParen: SM.onRParen(); break;
Chad Rosier5c118fd2013-01-14 22:31:35 +00001500 }
Chad Rosier31246272013-04-17 21:01:45 +00001501 if (SM.hadError())
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001502 return Error(Tok.getLoc(), "unknown token in expression");
Chad Rosier31246272013-04-17 21:01:45 +00001503
Alp Tokera5b88a52013-12-02 16:06:06 +00001504 if (!Done && UpdateLocLex)
1505 End = consumeToken();
Marina Yatsina8dfd5cb2015-12-24 12:09:51 +00001506
1507 PrevTK = TK;
Devang Patel41b9dde2012-01-17 18:00:18 +00001508 }
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001509 return false;
Chad Rosier5362af92013-04-16 18:15:40 +00001510}
1511
David Blaikie960ea3f2014-06-08 16:18:35 +00001512std::unique_ptr<X86Operand>
1513X86AsmParser::ParseIntelBracExpression(unsigned SegReg, SMLoc Start,
Nirav Dave8601ac12016-08-02 17:56:03 +00001514 int64_t ImmDisp, bool isSymbol,
1515 unsigned Size) {
Rafael Espindola961d4692014-11-11 05:18:41 +00001516 MCAsmParser &Parser = getParser();
Chad Rosier5362af92013-04-16 18:15:40 +00001517 const AsmToken &Tok = Parser.getTok();
1518 SMLoc BracLoc = Tok.getLoc(), End = Tok.getEndLoc();
1519 if (getLexer().isNot(AsmToken::LBrac))
1520 return ErrorOperand(BracLoc, "Expected '[' token!");
1521 Parser.Lex(); // Eat '['
1522
Nirav Davea6c75952016-07-14 17:37:05 +00001523 SMLoc StartInBrac = Parser.getTok().getLoc();
Chad Rosier5362af92013-04-16 18:15:40 +00001524 // Parse [ Symbol + ImmDisp ] and [ BaseReg + Scale*IndexReg + ImmDisp ]. We
1525 // may have already parsed an immediate displacement before the bracketed
1526 // expression.
Chad Rosierbfb70992013-04-17 00:11:46 +00001527 IntelExprStateMachine SM(ImmDisp, /*StopOnLBrac=*/false, /*AddImmPrefix=*/true);
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001528 if (ParseIntelExpression(SM, End))
Craig Topper062a2ba2014-04-25 05:30:21 +00001529 return nullptr;
Devang Patel41b9dde2012-01-17 18:00:18 +00001530
Craig Topper062a2ba2014-04-25 05:30:21 +00001531 const MCExpr *Disp = nullptr;
Chad Rosier175d0ae2013-04-12 18:21:18 +00001532 if (const MCExpr *Sym = SM.getSym()) {
Chad Rosierd383db52013-04-12 20:20:54 +00001533 // A symbolic displacement.
Chad Rosier175d0ae2013-04-12 18:21:18 +00001534 Disp = Sym;
Chad Rosierd383db52013-04-12 20:20:54 +00001535 if (isParsingInlineAsm())
Craig Topper7143d802015-10-10 05:25:06 +00001536 RewriteIntelBracExpression(*InstInfo->AsmRewrites, SM.getSymName(),
Chad Rosier5362af92013-04-16 18:15:40 +00001537 ImmDisp, SM.getImm(), BracLoc, StartInBrac,
Chad Rosierd383db52013-04-12 20:20:54 +00001538 End);
Reid Klecknerd84e70e2014-03-04 00:33:17 +00001539 }
1540
1541 if (SM.getImm() || !Disp) {
Jim Grosbach13760bd2015-05-30 01:25:56 +00001542 const MCExpr *Imm = MCConstantExpr::create(SM.getImm(), getContext());
Reid Klecknerd84e70e2014-03-04 00:33:17 +00001543 if (Disp)
Jim Grosbach13760bd2015-05-30 01:25:56 +00001544 Disp = MCBinaryExpr::createAdd(Disp, Imm, getContext());
Reid Klecknerd84e70e2014-03-04 00:33:17 +00001545 else
1546 Disp = Imm; // An immediate displacement only.
Chad Rosier175d0ae2013-04-12 18:21:18 +00001547 }
Devang Pateld0930ff2012-01-20 21:21:01 +00001548
Reid Kleckner94a1c4d2014-03-06 19:19:12 +00001549 // Parse struct field access. Intel requires a dot, but MSVC doesn't. MSVC
1550 // will in fact do global lookup the field name inside all global typedefs,
1551 // but we don't emulate that.
Nirav Davea6c75952016-07-14 17:37:05 +00001552 if ((Parser.getTok().getKind() == AsmToken::Identifier ||
1553 Parser.getTok().getKind() == AsmToken::Dot ||
1554 Parser.getTok().getKind() == AsmToken::Real) &&
1555 Parser.getTok().getString().find('.') != StringRef::npos) {
Chad Rosier911c1f32012-10-25 17:37:43 +00001556 const MCExpr *NewDisp;
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001557 if (ParseIntelDotOperator(Disp, NewDisp))
Craig Topper062a2ba2014-04-25 05:30:21 +00001558 return nullptr;
Michael Liao5bf95782014-12-04 05:20:33 +00001559
Chad Rosier70f47592013-04-10 20:07:47 +00001560 End = Tok.getEndLoc();
Chad Rosier911c1f32012-10-25 17:37:43 +00001561 Parser.Lex(); // Eat the field.
1562 Disp = NewDisp;
1563 }
Chad Rosier5dcb4662012-10-24 22:21:50 +00001564
Nirav Dave8601ac12016-08-02 17:56:03 +00001565 if (isSymbol) {
1566 if (SM.getSym()) {
1567 Error(Start, "cannot use more than one symbol in memory operand");
1568 return nullptr;
1569 }
1570 if (SM.getBaseReg()) {
1571 Error(Start, "cannot use base register with variable reference");
1572 return nullptr;
1573 }
1574 if (SM.getIndexReg()) {
1575 Error(Start, "cannot use index register with variable reference");
1576 return nullptr;
1577 }
1578 }
1579
Chad Rosier5c118fd2013-01-14 22:31:35 +00001580 int BaseReg = SM.getBaseReg();
1581 int IndexReg = SM.getIndexReg();
Chad Rosier175d0ae2013-04-12 18:21:18 +00001582 int Scale = SM.getScale();
Chad Rosiere8f9bfd2013-04-19 19:29:50 +00001583 if (!isParsingInlineAsm()) {
1584 // handle [-42]
1585 if (!BaseReg && !IndexReg) {
1586 if (!SegReg)
Craig Topper055845f2015-01-02 07:02:25 +00001587 return X86Operand::CreateMem(getPointerWidth(), Disp, Start, End, Size);
1588 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
1589 Start, End, Size);
Chad Rosiere8f9bfd2013-04-19 19:29:50 +00001590 }
Kevin Enderbybc570f22014-01-23 22:34:42 +00001591 StringRef ErrMsg;
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +00001592 if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, ErrMsg)) {
Kevin Enderbybc570f22014-01-23 22:34:42 +00001593 Error(StartInBrac, ErrMsg);
Craig Topper062a2ba2014-04-25 05:30:21 +00001594 return nullptr;
Kevin Enderbybc570f22014-01-23 22:34:42 +00001595 }
Craig Topper055845f2015-01-02 07:02:25 +00001596 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
1597 IndexReg, Scale, Start, End, Size);
Chad Rosier5c118fd2013-01-14 22:31:35 +00001598 }
Chad Rosiere8f9bfd2013-04-19 19:29:50 +00001599
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001600 InlineAsmIdentifierInfo &Info = SM.getIdentifierInfo();
Chad Rosiere8f9bfd2013-04-19 19:29:50 +00001601 return CreateMemForInlineAsm(SegReg, Disp, BaseReg, IndexReg, Scale, Start,
Coby Tayree49b37332016-11-22 09:30:29 +00001602 End, Size, SM.getSymName(), Info,
1603 isParsingInlineAsm());
Devang Patel41b9dde2012-01-17 18:00:18 +00001604}
1605
Chad Rosier8a244662013-04-02 20:02:33 +00001606// Inline assembly may use variable names with namespace alias qualifiers.
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001607bool X86AsmParser::ParseIntelIdentifier(const MCExpr *&Val,
1608 StringRef &Identifier,
1609 InlineAsmIdentifierInfo &Info,
1610 bool IsUnevaluatedOperand, SMLoc &End) {
Rafael Espindola961d4692014-11-11 05:18:41 +00001611 MCAsmParser &Parser = getParser();
Reid Klecknerc2b92542015-08-26 21:57:25 +00001612 assert(isParsingInlineAsm() && "Expected to be parsing inline assembly.");
Craig Topper062a2ba2014-04-25 05:30:21 +00001613 Val = nullptr;
Chad Rosier8a244662013-04-02 20:02:33 +00001614
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001615 StringRef LineBuf(Identifier.data());
Ehsan Akhgaridb0e7062014-09-22 02:21:35 +00001616 void *Result =
1617 SemaCallback->LookupInlineAsmIdentifier(LineBuf, Info, IsUnevaluatedOperand);
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001618
Chad Rosier8a244662013-04-02 20:02:33 +00001619 const AsmToken &Tok = Parser.getTok();
Ehsan Akhgaridb0e7062014-09-22 02:21:35 +00001620 SMLoc Loc = Tok.getLoc();
John McCallf73981b2013-05-03 00:15:41 +00001621
1622 // Advance the token stream until the end of the current token is
1623 // after the end of what the frontend claimed.
1624 const char *EndPtr = Tok.getLoc().getPointer() + LineBuf.size();
Reid Klecknerc2b92542015-08-26 21:57:25 +00001625 do {
John McCallf73981b2013-05-03 00:15:41 +00001626 End = Tok.getEndLoc();
1627 getLexer().Lex();
Reid Klecknerc2b92542015-08-26 21:57:25 +00001628 } while (End.getPointer() < EndPtr);
Ehsan Akhgaridb0e7062014-09-22 02:21:35 +00001629 Identifier = LineBuf;
1630
Reid Klecknerc2b92542015-08-26 21:57:25 +00001631 // The frontend should end parsing on an assembler token boundary, unless it
1632 // failed parsing.
1633 assert((End.getPointer() == EndPtr || !Result) &&
1634 "frontend claimed part of a token?");
1635
Ehsan Akhgaridb0e7062014-09-22 02:21:35 +00001636 // If the identifier lookup was unsuccessful, assume that we are dealing with
1637 // a label.
1638 if (!Result) {
Ehsan Akhgaribb6bb072014-09-22 20:40:36 +00001639 StringRef InternalName =
1640 SemaCallback->LookupInlineAsmLabel(Identifier, getSourceManager(),
1641 Loc, false);
1642 assert(InternalName.size() && "We should have an internal name here.");
1643 // Push a rewrite for replacing the identifier name with the internal name.
Craig Topper7d5b2312015-10-10 05:25:02 +00001644 InstInfo->AsmRewrites->emplace_back(AOK_Label, Loc, Identifier.size(),
1645 InternalName);
Ehsan Akhgaridb0e7062014-09-22 02:21:35 +00001646 }
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001647
1648 // Create the symbol reference.
Jim Grosbach6f482002015-05-18 18:43:14 +00001649 MCSymbol *Sym = getContext().getOrCreateSymbol(Identifier);
Chad Rosier8a244662013-04-02 20:02:33 +00001650 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
Jim Grosbach13760bd2015-05-30 01:25:56 +00001651 Val = MCSymbolRefExpr::create(Sym, Variant, getParser().getContext());
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001652 return false;
Chad Rosier8a244662013-04-02 20:02:33 +00001653}
1654
David Majnemeraa34d792013-08-27 21:56:17 +00001655/// \brief Parse intel style segment override.
David Blaikie960ea3f2014-06-08 16:18:35 +00001656std::unique_ptr<X86Operand>
1657X86AsmParser::ParseIntelSegmentOverride(unsigned SegReg, SMLoc Start,
1658 unsigned Size) {
Rafael Espindola961d4692014-11-11 05:18:41 +00001659 MCAsmParser &Parser = getParser();
David Majnemeraa34d792013-08-27 21:56:17 +00001660 assert(SegReg != 0 && "Tried to parse a segment override without a segment!");
1661 const AsmToken &Tok = Parser.getTok(); // Eat colon.
1662 if (Tok.isNot(AsmToken::Colon))
1663 return ErrorOperand(Tok.getLoc(), "Expected ':' token!");
1664 Parser.Lex(); // Eat ':'
Devang Patel41b9dde2012-01-17 18:00:18 +00001665
David Majnemeraa34d792013-08-27 21:56:17 +00001666 int64_t ImmDisp = 0;
Chad Rosier1530ba52013-03-27 21:49:56 +00001667 if (getLexer().is(AsmToken::Integer)) {
David Majnemeraa34d792013-08-27 21:56:17 +00001668 ImmDisp = Tok.getIntVal();
1669 AsmToken ImmDispToken = Parser.Lex(); // Eat the integer.
1670
Chad Rosier1530ba52013-03-27 21:49:56 +00001671 if (isParsingInlineAsm())
Craig Topper7d5b2312015-10-10 05:25:02 +00001672 InstInfo->AsmRewrites->emplace_back(AOK_ImmPrefix, ImmDispToken.getLoc());
David Majnemeraa34d792013-08-27 21:56:17 +00001673
1674 if (getLexer().isNot(AsmToken::LBrac)) {
1675 // An immediate following a 'segment register', 'colon' token sequence can
1676 // be followed by a bracketed expression. If it isn't we know we have our
1677 // final segment override.
Jim Grosbach13760bd2015-05-30 01:25:56 +00001678 const MCExpr *Disp = MCConstantExpr::create(ImmDisp, getContext());
Craig Topper055845f2015-01-02 07:02:25 +00001679 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp,
1680 /*BaseReg=*/0, /*IndexReg=*/0, /*Scale=*/1,
1681 Start, ImmDispToken.getEndLoc(), Size);
David Majnemeraa34d792013-08-27 21:56:17 +00001682 }
Chad Rosier1530ba52013-03-27 21:49:56 +00001683 }
1684
Chad Rosier91c82662012-10-24 17:22:29 +00001685 if (getLexer().is(AsmToken::LBrac))
Nirav Dave8601ac12016-08-02 17:56:03 +00001686 return ParseIntelBracExpression(SegReg, Start, ImmDisp, false, Size);
Devang Patel880bc162012-01-23 18:31:58 +00001687
David Majnemeraa34d792013-08-27 21:56:17 +00001688 const MCExpr *Val;
1689 SMLoc End;
1690 if (!isParsingInlineAsm()) {
1691 if (getParser().parsePrimaryExpr(Val, End))
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001692 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
David Majnemeraa34d792013-08-27 21:56:17 +00001693
Craig Topper055845f2015-01-02 07:02:25 +00001694 return X86Operand::CreateMem(getPointerWidth(), Val, Start, End, Size);
Devang Patel880bc162012-01-23 18:31:58 +00001695 }
Devang Patel41b9dde2012-01-17 18:00:18 +00001696
David Majnemeraa34d792013-08-27 21:56:17 +00001697 InlineAsmIdentifierInfo Info;
1698 StringRef Identifier = Tok.getString();
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001699 if (ParseIntelIdentifier(Val, Identifier, Info,
1700 /*Unevaluated=*/false, End))
Craig Topper062a2ba2014-04-25 05:30:21 +00001701 return nullptr;
David Majnemeraa34d792013-08-27 21:56:17 +00001702 return CreateMemForInlineAsm(/*SegReg=*/0, Val, /*BaseReg=*/0,/*IndexReg=*/0,
1703 /*Scale=*/1, Start, End, Size, Identifier, Info);
1704}
1705
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001706//ParseRoundingModeOp - Parse AVX-512 rounding mode operand
1707std::unique_ptr<X86Operand>
1708X86AsmParser::ParseRoundingModeOp(SMLoc Start, SMLoc End) {
1709 MCAsmParser &Parser = getParser();
1710 const AsmToken &Tok = Parser.getTok();
Elena Demikhovsky29792e92015-05-07 11:24:42 +00001711 // Eat "{" and mark the current place.
1712 const SMLoc consumedToken = consumeToken();
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001713 if (Tok.getIdentifier().startswith("r")){
1714 int rndMode = StringSwitch<int>(Tok.getIdentifier())
1715 .Case("rn", X86::STATIC_ROUNDING::TO_NEAREST_INT)
1716 .Case("rd", X86::STATIC_ROUNDING::TO_NEG_INF)
1717 .Case("ru", X86::STATIC_ROUNDING::TO_POS_INF)
1718 .Case("rz", X86::STATIC_ROUNDING::TO_ZERO)
1719 .Default(-1);
1720 if (-1 == rndMode)
1721 return ErrorOperand(Tok.getLoc(), "Invalid rounding mode.");
1722 Parser.Lex(); // Eat "r*" of r*-sae
1723 if (!getLexer().is(AsmToken::Minus))
1724 return ErrorOperand(Tok.getLoc(), "Expected - at this point");
1725 Parser.Lex(); // Eat "-"
1726 Parser.Lex(); // Eat the sae
1727 if (!getLexer().is(AsmToken::RCurly))
1728 return ErrorOperand(Tok.getLoc(), "Expected } at this point");
1729 Parser.Lex(); // Eat "}"
1730 const MCExpr *RndModeOp =
Jim Grosbach13760bd2015-05-30 01:25:56 +00001731 MCConstantExpr::create(rndMode, Parser.getContext());
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001732 return X86Operand::CreateImm(RndModeOp, Start, End);
1733 }
Elena Demikhovsky29792e92015-05-07 11:24:42 +00001734 if(Tok.getIdentifier().equals("sae")){
1735 Parser.Lex(); // Eat the sae
1736 if (!getLexer().is(AsmToken::RCurly))
1737 return ErrorOperand(Tok.getLoc(), "Expected } at this point");
1738 Parser.Lex(); // Eat "}"
1739 return X86Operand::CreateToken("{sae}", consumedToken);
1740 }
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001741 return ErrorOperand(Tok.getLoc(), "unknown token in expression");
1742}
Chad Rosier91c82662012-10-24 17:22:29 +00001743
Chad Rosier5dcb4662012-10-24 22:21:50 +00001744/// Parse the '.' operator.
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001745bool X86AsmParser::ParseIntelDotOperator(const MCExpr *Disp,
Chad Rosiercc541e82013-04-19 15:57:00 +00001746 const MCExpr *&NewDisp) {
Rafael Espindola961d4692014-11-11 05:18:41 +00001747 MCAsmParser &Parser = getParser();
Chad Rosier70f47592013-04-10 20:07:47 +00001748 const AsmToken &Tok = Parser.getTok();
Chad Rosier6241c1a2013-04-17 21:14:38 +00001749 int64_t OrigDispVal, DotDispVal;
Chad Rosier911c1f32012-10-25 17:37:43 +00001750
1751 // FIXME: Handle non-constant expressions.
Chad Rosiercc541e82013-04-19 15:57:00 +00001752 if (const MCConstantExpr *OrigDisp = dyn_cast<MCConstantExpr>(Disp))
Chad Rosier911c1f32012-10-25 17:37:43 +00001753 OrigDispVal = OrigDisp->getValue();
Chad Rosiercc541e82013-04-19 15:57:00 +00001754 else
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001755 return Error(Tok.getLoc(), "Non-constant offsets are not supported!");
Chad Rosier5dcb4662012-10-24 22:21:50 +00001756
Reid Kleckner94a1c4d2014-03-06 19:19:12 +00001757 // Drop the optional '.'.
1758 StringRef DotDispStr = Tok.getString();
1759 if (DotDispStr.startswith("."))
1760 DotDispStr = DotDispStr.drop_front(1);
Chad Rosier5dcb4662012-10-24 22:21:50 +00001761
Chad Rosier5dcb4662012-10-24 22:21:50 +00001762 // .Imm gets lexed as a real.
1763 if (Tok.is(AsmToken::Real)) {
1764 APInt DotDisp;
1765 DotDispStr.getAsInteger(10, DotDisp);
Chad Rosier911c1f32012-10-25 17:37:43 +00001766 DotDispVal = DotDisp.getZExtValue();
Chad Rosiercc541e82013-04-19 15:57:00 +00001767 } else if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
Chad Rosier240b7b92012-10-25 21:51:10 +00001768 unsigned DotDisp;
1769 std::pair<StringRef, StringRef> BaseMember = DotDispStr.split('.');
1770 if (SemaCallback->LookupInlineAsmField(BaseMember.first, BaseMember.second,
Chad Rosiercc541e82013-04-19 15:57:00 +00001771 DotDisp))
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001772 return Error(Tok.getLoc(), "Unable to lookup field reference!");
Chad Rosier240b7b92012-10-25 21:51:10 +00001773 DotDispVal = DotDisp;
Chad Rosiercc541e82013-04-19 15:57:00 +00001774 } else
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001775 return Error(Tok.getLoc(), "Unexpected token type!");
Chad Rosier911c1f32012-10-25 17:37:43 +00001776
Chad Rosier240b7b92012-10-25 21:51:10 +00001777 if (isParsingInlineAsm() && Tok.is(AsmToken::Identifier)) {
1778 SMLoc Loc = SMLoc::getFromPointer(DotDispStr.data());
1779 unsigned Len = DotDispStr.size();
Marina Yatsinaf58dcb82017-06-26 16:03:42 +00001780 InstInfo->AsmRewrites->emplace_back(AOK_DotOperator, Loc, Len, DotDispVal);
Chad Rosier911c1f32012-10-25 17:37:43 +00001781 }
1782
Jim Grosbach13760bd2015-05-30 01:25:56 +00001783 NewDisp = MCConstantExpr::create(OrigDispVal + DotDispVal, getContext());
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001784 return false;
Chad Rosier5dcb4662012-10-24 22:21:50 +00001785}
1786
Chad Rosier91c82662012-10-24 17:22:29 +00001787/// Parse the 'offset' operator. This operator is used to specify the
1788/// location rather then the content of a variable.
David Blaikie960ea3f2014-06-08 16:18:35 +00001789std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOffsetOfOperator() {
Rafael Espindola961d4692014-11-11 05:18:41 +00001790 MCAsmParser &Parser = getParser();
Chad Rosier18785852013-04-09 20:58:48 +00001791 const AsmToken &Tok = Parser.getTok();
Chad Rosier10d1d1c2013-04-09 20:44:09 +00001792 SMLoc OffsetOfLoc = Tok.getLoc();
Chad Rosier91c82662012-10-24 17:22:29 +00001793 Parser.Lex(); // Eat offset.
Chad Rosier91c82662012-10-24 17:22:29 +00001794
Chad Rosier91c82662012-10-24 17:22:29 +00001795 const MCExpr *Val;
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001796 InlineAsmIdentifierInfo Info;
Chad Rosier18785852013-04-09 20:58:48 +00001797 SMLoc Start = Tok.getLoc(), End;
Chad Rosierae7ecd62013-04-11 23:37:34 +00001798 StringRef Identifier = Tok.getString();
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001799 if (ParseIntelIdentifier(Val, Identifier, Info,
1800 /*Unevaluated=*/false, End))
Craig Topper062a2ba2014-04-25 05:30:21 +00001801 return nullptr;
Chad Rosierae7ecd62013-04-11 23:37:34 +00001802
Chad Rosiere2f03772012-10-26 16:09:20 +00001803 // Don't emit the offset operator.
Craig Topper7d5b2312015-10-10 05:25:02 +00001804 InstInfo->AsmRewrites->emplace_back(AOK_Skip, OffsetOfLoc, 7);
Chad Rosiere2f03772012-10-26 16:09:20 +00001805
Chad Rosier91c82662012-10-24 17:22:29 +00001806 // The offset operator will have an 'r' constraint, thus we need to create
1807 // register operand to ensure proper matching. Just pick a GPR based on
1808 // the size of a pointer.
Nirav Dave6477ce22016-09-26 19:33:36 +00001809 bool Parse32 = is32BitMode() || Code16GCC;
1810 unsigned RegNo = is64BitMode() ? X86::RBX : (Parse32 ? X86::EBX : X86::BX);
1811
Chad Rosiera4bc9432013-01-10 22:10:27 +00001812 return X86Operand::CreateReg(RegNo, Start, End, /*GetAddress=*/true,
Peter Collingbourne0da86302016-10-10 22:49:37 +00001813 OffsetOfLoc, Identifier, Info.OpDecl);
Devang Patel41b9dde2012-01-17 18:00:18 +00001814}
1815
Coby Tayree07a89742017-03-21 19:31:55 +00001816// Query a candidate string for being an Intel assembly operator
1817// Report back its kind, or IOK_INVALID if does not evaluated as a known one
1818unsigned X86AsmParser::IdentifyIntelOperator(StringRef Name) {
1819 return StringSwitch<unsigned>(Name)
1820 .Cases("TYPE","type",IOK_TYPE)
1821 .Cases("SIZE","size",IOK_SIZE)
1822 .Cases("LENGTH","length",IOK_LENGTH)
1823 .Cases("OFFSET","offset",IOK_OFFSET)
1824 .Default(IOK_INVALID);
1825}
Chad Rosierd0ed73a2013-01-17 19:21:48 +00001826
1827/// Parse the 'LENGTH', 'TYPE' and 'SIZE' operators. The LENGTH operator
1828/// returns the number of elements in an array. It returns the value 1 for
1829/// non-array variables. The SIZE operator returns the size of a C or C++
1830/// variable. A variable's size is the product of its LENGTH and TYPE. The
1831/// TYPE operator returns the size of a C or C++ type or variable. If the
1832/// variable is an array, TYPE returns the size of a single element.
Eric Christopheradfe5362017-07-25 19:22:09 +00001833unsigned X86AsmParser::ParseIntelOperator(unsigned OpKind) {
Rafael Espindola961d4692014-11-11 05:18:41 +00001834 MCAsmParser &Parser = getParser();
Chad Rosier18785852013-04-09 20:58:48 +00001835 const AsmToken &Tok = Parser.getTok();
Chad Rosier10d1d1c2013-04-09 20:44:09 +00001836 SMLoc TypeLoc = Tok.getLoc();
1837 Parser.Lex(); // Eat operator.
Chad Rosier11c42f22012-10-26 18:04:20 +00001838
Craig Topper062a2ba2014-04-25 05:30:21 +00001839 const MCExpr *Val = nullptr;
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001840 InlineAsmIdentifierInfo Info;
Chad Rosier18785852013-04-09 20:58:48 +00001841 SMLoc Start = Tok.getLoc(), End;
Chad Rosierb67f8052013-04-11 23:57:04 +00001842 StringRef Identifier = Tok.getString();
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001843 if (ParseIntelIdentifier(Val, Identifier, Info,
1844 /*Unevaluated=*/true, End))
Coby Tayree07a89742017-03-21 19:31:55 +00001845 return 0;
Benjamin Kramer951b15e2013-12-01 11:47:42 +00001846
Coby Tayree07a89742017-03-21 19:31:55 +00001847 if (!Info.OpDecl) {
1848 Error(Start, "unable to lookup expression");
1849 return 0;
1850 }
1851
Chad Rosierf6675c32013-04-22 17:01:46 +00001852 unsigned CVal = 0;
Chad Rosiercb78f0d2013-04-22 19:42:15 +00001853 switch(OpKind) {
1854 default: llvm_unreachable("Unexpected operand kind!");
1855 case IOK_LENGTH: CVal = Info.Length; break;
1856 case IOK_SIZE: CVal = Info.Size; break;
1857 case IOK_TYPE: CVal = Info.Type; break;
1858 }
Eric Christopheradfe5362017-07-25 19:22:09 +00001859
1860 // Rewrite the type operator and the C or C++ type or variable in terms of an
1861 // immediate. E.g. TYPE foo -> $$4
1862 unsigned Len = End.getPointer() - TypeLoc.getPointer();
1863 InstInfo->AsmRewrites->emplace_back(AOK_Imm, TypeLoc, Len, CVal);
1864
Coby Tayree07a89742017-03-21 19:31:55 +00001865 return CVal;
Chad Rosier11c42f22012-10-26 18:04:20 +00001866}
1867
David Blaikie960ea3f2014-06-08 16:18:35 +00001868std::unique_ptr<X86Operand> X86AsmParser::ParseIntelOperand() {
Rafael Espindola961d4692014-11-11 05:18:41 +00001869 MCAsmParser &Parser = getParser();
Chad Rosier70f47592013-04-10 20:07:47 +00001870 const AsmToken &Tok = Parser.getTok();
David Majnemeraa34d792013-08-27 21:56:17 +00001871 SMLoc Start, End;
Chad Rosier91c82662012-10-24 17:22:29 +00001872
Coby Tayree07a89742017-03-21 19:31:55 +00001873 // FIXME: Offset operator
1874 // Should be handled as part of immediate expression, as other operators
1875 // Currently, only supported as a stand-alone operand
1876 if (isParsingInlineAsm())
1877 if (IdentifyIntelOperator(Tok.getString()) == IOK_OFFSET)
Chad Rosier10d1d1c2013-04-09 20:44:09 +00001878 return ParseIntelOffsetOfOperator();
Chad Rosier11c42f22012-10-26 18:04:20 +00001879
Marina Yatsina4b1aea02015-12-03 12:17:03 +00001880 bool PtrInOperand = false;
David Majnemeraa34d792013-08-27 21:56:17 +00001881 unsigned Size = getIntelMemOperandSize(Tok.getString());
1882 if (Size) {
1883 Parser.Lex(); // Eat operand size (e.g., byte, word).
1884 if (Tok.getString() != "PTR" && Tok.getString() != "ptr")
Reid Kleckner71ff3f22014-08-01 00:59:22 +00001885 return ErrorOperand(Tok.getLoc(), "Expected 'PTR' or 'ptr' token!");
David Majnemeraa34d792013-08-27 21:56:17 +00001886 Parser.Lex(); // Eat ptr.
Marina Yatsina4b1aea02015-12-03 12:17:03 +00001887 PtrInOperand = true;
David Majnemeraa34d792013-08-27 21:56:17 +00001888 }
Nirav Dave8601ac12016-08-02 17:56:03 +00001889
David Majnemeraa34d792013-08-27 21:56:17 +00001890 Start = Tok.getLoc();
1891
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001892 // rounding mode token
Akira Hatanakabd9fc282015-11-14 05:20:05 +00001893 if (getSTI().getFeatureBits()[X86::FeatureAVX512] &&
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00001894 getLexer().is(AsmToken::LCurly))
1895 return ParseRoundingModeOp(Start, End);
1896
Chad Rosierd0ed73a2013-01-17 19:21:48 +00001897 // Register.
Devang Patelce6a2ca2012-01-20 22:32:05 +00001898 unsigned RegNo = 0;
Nirav Dave8601ac12016-08-02 17:56:03 +00001899 if (getLexer().is(AsmToken::Identifier) &&
1900 !ParseRegister(RegNo, Start, End)) {
Chad Rosier0397edd2012-10-04 23:59:38 +00001901 // If this is a segment register followed by a ':', then this is the start
David Majnemeraa34d792013-08-27 21:56:17 +00001902 // of a segment override, otherwise this is a normal register reference.
Douglas Katzman0411e862016-10-05 15:23:35 +00001903 // In case it is a normal register and there is ptr in the operand this
Marina Yatsina4b1aea02015-12-03 12:17:03 +00001904 // is an error
Douglas Katzman0411e862016-10-05 15:23:35 +00001905 if (RegNo == X86::RIP)
1906 return ErrorOperand(Start, "rip can only be used as a base register");
1907 if (getLexer().isNot(AsmToken::Colon)) {
1908 if (PtrInOperand) {
Marina Yatsina4b1aea02015-12-03 12:17:03 +00001909 return ErrorOperand(Start, "expected memory operand after "
1910 "'ptr', found register operand instead");
1911 }
Jordan Rosee8f1eae2013-01-07 19:00:49 +00001912 return X86Operand::CreateReg(RegNo, Start, End);
Marina Yatsina4b1aea02015-12-03 12:17:03 +00001913 }
David Majnemeraa34d792013-08-27 21:56:17 +00001914 return ParseIntelSegmentOverride(/*SegReg=*/RegNo, Start, Size);
Devang Patel46831de2012-01-12 01:36:43 +00001915 }
1916
Nirav Dave8601ac12016-08-02 17:56:03 +00001917 // Immediates and Memory
1918
1919 // Parse [ BaseReg + Scale*IndexReg + Disp ].
1920 if (getLexer().is(AsmToken::LBrac))
1921 return ParseIntelBracExpression(/*SegReg=*/0, Start, /*ImmDisp=*/0, false,
1922 Size);
1923
Kirill Bobyrev6afbaf02017-01-18 16:34:25 +00001924 AsmToken StartTok = Tok;
Nirav Dave8601ac12016-08-02 17:56:03 +00001925 IntelExprStateMachine SM(/*Imm=*/0, /*StopOnLBrac=*/true,
1926 /*AddImmPrefix=*/false);
1927 if (ParseIntelExpression(SM, End))
1928 return nullptr;
1929
1930 bool isSymbol = SM.getSym() && SM.getSym()->getKind() != MCExpr::Constant;
1931 int64_t Imm = SM.getImm();
1932 if (SM.getSym() && SM.getSym()->getKind() == MCExpr::Constant)
1933 SM.getSym()->evaluateAsAbsolute(Imm);
1934
Eric Christopheradfe5362017-07-25 19:22:09 +00001935 if (StartTok.isNot(AsmToken::Identifier) &&
1936 StartTok.isNot(AsmToken::String) && isParsingInlineAsm()) {
Nirav Dave8601ac12016-08-02 17:56:03 +00001937 unsigned Len = Tok.getLoc().getPointer() - Start.getPointer();
Eric Christopheradfe5362017-07-25 19:22:09 +00001938 if (StartTok.getString().size() == Len)
1939 // Just add a prefix if this wasn't a complex immediate expression.
1940 InstInfo->AsmRewrites->emplace_back(AOK_ImmPrefix, Start);
1941 else
1942 // Otherwise, rewrite the complex expression as a single immediate.
Nirav Dave8601ac12016-08-02 17:56:03 +00001943 InstInfo->AsmRewrites->emplace_back(AOK_Imm, Start, Len, Imm);
1944 }
1945
1946 if (getLexer().isNot(AsmToken::LBrac)) {
1947 // If a directional label (ie. 1f or 2b) was parsed above from
1948 // ParseIntelExpression() then SM.getSym() was set to a pointer to
1949 // to the MCExpr with the directional local symbol and this is a
1950 // memory operand not an immediate operand.
1951 if (isSymbol) {
1952 if (isParsingInlineAsm())
1953 return CreateMemForInlineAsm(/*SegReg=*/0, SM.getSym(), /*BaseReg=*/0,
1954 /*IndexReg=*/0,
1955 /*Scale=*/1, Start, End, Size,
1956 SM.getSymName(), SM.getIdentifierInfo());
1957 return X86Operand::CreateMem(getPointerWidth(), SM.getSym(), Start, End,
1958 Size);
1959 }
1960
1961 const MCExpr *ImmExpr = MCConstantExpr::create(Imm, getContext());
1962 return X86Operand::CreateImm(ImmExpr, Start, End);
1963 }
1964
1965 // Only positive immediates are valid.
1966 if (Imm < 0)
1967 return ErrorOperand(Start, "expected a positive immediate displacement "
1968 "before bracketed expr.");
1969
1970 return ParseIntelBracExpression(/*SegReg=*/0, Start, Imm, isSymbol, Size);
Devang Patel46831de2012-01-12 01:36:43 +00001971}
1972
David Blaikie960ea3f2014-06-08 16:18:35 +00001973std::unique_ptr<X86Operand> X86AsmParser::ParseATTOperand() {
Rafael Espindola961d4692014-11-11 05:18:41 +00001974 MCAsmParser &Parser = getParser();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00001975 switch (getLexer().getKind()) {
1976 default:
Chris Lattnerb9270732010-04-17 18:56:34 +00001977 // Parse a memory operand with no segment register.
1978 return ParseMemOperand(0, Parser.getTok().getLoc());
Chris Lattnercc2ad082010-01-15 18:27:19 +00001979 case AsmToken::Percent: {
Chris Lattnerb9270732010-04-17 18:56:34 +00001980 // Read the register.
Chris Lattnercc2ad082010-01-15 18:27:19 +00001981 unsigned RegNo;
Chris Lattner0c2538f2010-01-15 18:51:29 +00001982 SMLoc Start, End;
Craig Topper062a2ba2014-04-25 05:30:21 +00001983 if (ParseRegister(RegNo, Start, End)) return nullptr;
Bruno Cardoso Lopes306a1f92010-07-24 00:06:39 +00001984 if (RegNo == X86::EIZ || RegNo == X86::RIZ) {
Benjamin Kramer1930b002011-10-16 12:10:27 +00001985 Error(Start, "%eiz and %riz can only be used as index registers",
1986 SMRange(Start, End));
Craig Topper062a2ba2014-04-25 05:30:21 +00001987 return nullptr;
Bruno Cardoso Lopes306a1f92010-07-24 00:06:39 +00001988 }
Douglas Katzman0411e862016-10-05 15:23:35 +00001989 if (RegNo == X86::RIP) {
1990 Error(Start, "%rip can only be used as a base register",
1991 SMRange(Start, End));
1992 return nullptr;
1993 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001994
Chris Lattnerb9270732010-04-17 18:56:34 +00001995 // If this is a segment register followed by a ':', then this is the start
1996 // of a memory reference, otherwise this is a normal register reference.
1997 if (getLexer().isNot(AsmToken::Colon))
1998 return X86Operand::CreateReg(RegNo, Start, End);
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00001999
Reid Kleckner0c5da972014-07-31 23:03:22 +00002000 if (!X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo))
2001 return ErrorOperand(Start, "invalid segment register");
2002
Chris Lattnerb9270732010-04-17 18:56:34 +00002003 getParser().Lex(); // Eat the colon.
2004 return ParseMemOperand(RegNo, Start);
Chris Lattnercc2ad082010-01-15 18:27:19 +00002005 }
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002006 case AsmToken::Dollar: {
2007 // $42 -> immediate.
Sean Callanan936b0d32010-01-19 21:44:56 +00002008 SMLoc Start = Parser.getTok().getLoc(), End;
Sean Callanana83fd7d2010-01-19 20:27:46 +00002009 Parser.Lex();
Daniel Dunbar73da11e2009-08-31 08:08:38 +00002010 const MCExpr *Val;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00002011 if (getParser().parseExpression(Val, End))
Craig Topper062a2ba2014-04-25 05:30:21 +00002012 return nullptr;
Chris Lattner528d00b2010-01-15 19:28:38 +00002013 return X86Operand::CreateImm(Val, Start, End);
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002014 }
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00002015 case AsmToken::LCurly:{
2016 SMLoc Start = Parser.getTok().getLoc(), End;
Akira Hatanakabd9fc282015-11-14 05:20:05 +00002017 if (getSTI().getFeatureBits()[X86::FeatureAVX512])
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00002018 return ParseRoundingModeOp(Start, End);
Nirav Dave8601ac12016-08-02 17:56:03 +00002019 return ErrorOperand(Start, "Unexpected '{' in expression");
Elena Demikhovsky18fd4962015-03-02 15:00:34 +00002020 }
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002021 }
Daniel Dunbar2b11c7d2009-07-20 20:01:54 +00002022}
2023
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002024// true on failure, false otherwise
2025// If no {z} mark was found - Parser doesn't advance
2026bool X86AsmParser::ParseZ(std::unique_ptr<X86Operand> &Z,
2027 const SMLoc &StartLoc) {
2028 MCAsmParser &Parser = getParser();
2029 // Assuming we are just pass the '{' mark, quering the next token
Coby Tayree179ff0e2016-11-20 09:31:11 +00002030 // Searched for {z}, but none was found. Return false, as no parsing error was
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002031 // encountered
2032 if (!(getLexer().is(AsmToken::Identifier) &&
2033 (getLexer().getTok().getIdentifier() == "z")))
2034 return false;
2035 Parser.Lex(); // Eat z
2036 // Query and eat the '}' mark
2037 if (!getLexer().is(AsmToken::RCurly))
2038 return Error(getLexer().getLoc(), "Expected } at this point");
2039 Parser.Lex(); // Eat '}'
2040 // Assign Z with the {z} mark opernad
Benjamin Kramerfc54e352016-11-24 15:17:39 +00002041 Z = X86Operand::CreateToken("{z}", StartLoc);
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002042 return false;
2043}
2044
2045// true on failure, false otherwise
David Blaikie960ea3f2014-06-08 16:18:35 +00002046bool X86AsmParser::HandleAVX512Operand(OperandVector &Operands,
2047 const MCParsedAsmOperand &Op) {
Rafael Espindola961d4692014-11-11 05:18:41 +00002048 MCAsmParser &Parser = getParser();
Akira Hatanakabd9fc282015-11-14 05:20:05 +00002049 if(getSTI().getFeatureBits()[X86::FeatureAVX512]) {
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002050 if (getLexer().is(AsmToken::LCurly)) {
2051 // Eat "{" and mark the current place.
2052 const SMLoc consumedToken = consumeToken();
2053 // Distinguish {1to<NUM>} from {%k<NUM>}.
2054 if(getLexer().is(AsmToken::Integer)) {
2055 // Parse memory broadcasting ({1to<NUM>}).
2056 if (getLexer().getTok().getIntVal() != 1)
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002057 return TokError("Expected 1to<NUM> at this point");
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002058 Parser.Lex(); // Eat "1" of 1to8
2059 if (!getLexer().is(AsmToken::Identifier) ||
2060 !getLexer().getTok().getIdentifier().startswith("to"))
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002061 return TokError("Expected 1to<NUM> at this point");
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002062 // Recognize only reasonable suffixes.
2063 const char *BroadcastPrimitive =
2064 StringSwitch<const char*>(getLexer().getTok().getIdentifier())
Robert Khasanovbfa01312014-07-21 14:54:21 +00002065 .Case("to2", "{1to2}")
2066 .Case("to4", "{1to4}")
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002067 .Case("to8", "{1to8}")
2068 .Case("to16", "{1to16}")
Craig Topper062a2ba2014-04-25 05:30:21 +00002069 .Default(nullptr);
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002070 if (!BroadcastPrimitive)
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002071 return TokError("Invalid memory broadcast primitive.");
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002072 Parser.Lex(); // Eat "toN" of 1toN
2073 if (!getLexer().is(AsmToken::RCurly))
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002074 return TokError("Expected } at this point");
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002075 Parser.Lex(); // Eat "}"
2076 Operands.push_back(X86Operand::CreateToken(BroadcastPrimitive,
2077 consumedToken));
2078 // No AVX512 specific primitives can pass
2079 // after memory broadcasting, so return.
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002080 return false;
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002081 } else {
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002082 // Parse either {k}{z}, {z}{k}, {k} or {z}
2083 // last one have no meaning, but GCC accepts it
2084 // Currently, we're just pass a '{' mark
2085 std::unique_ptr<X86Operand> Z;
2086 if (ParseZ(Z, consumedToken))
2087 return true;
2088 // Reaching here means that parsing of the allegadly '{z}' mark yielded
2089 // no errors.
2090 // Query for the need of further parsing for a {%k<NUM>} mark
2091 if (!Z || getLexer().is(AsmToken::LCurly)) {
2092 const SMLoc StartLoc = Z ? consumeToken() : consumedToken;
2093 // Parse an op-mask register mark ({%k<NUM>}), which is now to be
2094 // expected
2095 if (std::unique_ptr<X86Operand> Op = ParseOperand()) {
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002096 if (!getLexer().is(AsmToken::RCurly))
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002097 return Error(getLexer().getLoc(), "Expected } at this point");
2098 Operands.push_back(X86Operand::CreateToken("{", StartLoc));
2099 Operands.push_back(std::move(Op));
2100 Operands.push_back(X86Operand::CreateToken("}", consumeToken()));
2101 } else
2102 return Error(getLexer().getLoc(),
2103 "Expected an op-mask register at this point");
2104 // {%k<NUM>} mark is found, inquire for {z}
2105 if (getLexer().is(AsmToken::LCurly) && !Z) {
2106 // Have we've found a parsing error, or found no (expected) {z} mark
2107 // - report an error
2108 if (ParseZ(Z, consumeToken()) || !Z)
2109 return true;
2110
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002111 }
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002112 // '{z}' on its own is meaningless, hence should be ignored.
2113 // on the contrary - have it been accompanied by a K register,
2114 // allow it.
2115 if (Z)
2116 Operands.push_back(std::move(Z));
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002117 }
2118 }
2119 }
2120 }
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002121 return false;
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002122}
2123
Chris Lattnerb9270732010-04-17 18:56:34 +00002124/// ParseMemOperand: segment: disp(basereg, indexreg, scale). The '%ds:' prefix
2125/// has already been parsed if present.
David Blaikie960ea3f2014-06-08 16:18:35 +00002126std::unique_ptr<X86Operand> X86AsmParser::ParseMemOperand(unsigned SegReg,
2127 SMLoc MemStart) {
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002128
Rafael Espindola961d4692014-11-11 05:18:41 +00002129 MCAsmParser &Parser = getParser();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002130 // We have to disambiguate a parenthesized expression "(4+5)" from the start
2131 // of a memory operand with a missing displacement "(%ebx)" or "(,%eax)". The
Chris Lattner807a3bc2010-01-24 01:07:33 +00002132 // only way to do this without lookahead is to eat the '(' and see what is
2133 // after it.
Jim Grosbach13760bd2015-05-30 01:25:56 +00002134 const MCExpr *Disp = MCConstantExpr::create(0, getParser().getContext());
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002135 if (getLexer().isNot(AsmToken::LParen)) {
Chris Lattnere17df0b2010-01-15 19:39:23 +00002136 SMLoc ExprEnd;
Craig Topper062a2ba2014-04-25 05:30:21 +00002137 if (getParser().parseExpression(Disp, ExprEnd)) return nullptr;
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002138
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002139 // After parsing the base expression we could either have a parenthesized
2140 // memory address or not. If not, return now. If so, eat the (.
2141 if (getLexer().isNot(AsmToken::LParen)) {
Daniel Dunbara4fc8d92009-07-31 22:22:54 +00002142 // Unless we have a segment register, treat this as an immediate.
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002143 if (SegReg == 0)
Craig Topper055845f2015-01-02 07:02:25 +00002144 return X86Operand::CreateMem(getPointerWidth(), Disp, MemStart, ExprEnd);
2145 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
2146 MemStart, ExprEnd);
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002147 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002148
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002149 // Eat the '('.
Sean Callanana83fd7d2010-01-19 20:27:46 +00002150 Parser.Lex();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002151 } else {
2152 // Okay, we have a '('. We don't know if this is an expression or not, but
2153 // so we have to eat the ( to see beyond it.
Sean Callanan936b0d32010-01-19 21:44:56 +00002154 SMLoc LParenLoc = Parser.getTok().getLoc();
Sean Callanana83fd7d2010-01-19 20:27:46 +00002155 Parser.Lex(); // Eat the '('.
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002156
Kevin Enderby7d912182009-09-03 17:15:07 +00002157 if (getLexer().is(AsmToken::Percent) || getLexer().is(AsmToken::Comma)) {
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002158 // Nothing to do here, fall into the code below with the '(' part of the
2159 // memory operand consumed.
2160 } else {
Chris Lattner528d00b2010-01-15 19:28:38 +00002161 SMLoc ExprEnd;
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002162
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002163 // It must be an parenthesized expression, parse it now.
Jim Grosbachd2037eb2013-02-20 22:21:35 +00002164 if (getParser().parseParenExpression(Disp, ExprEnd))
Craig Topper062a2ba2014-04-25 05:30:21 +00002165 return nullptr;
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002166
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002167 // After parsing the base expression we could either have a parenthesized
2168 // memory address or not. If not, return now. If so, eat the (.
2169 if (getLexer().isNot(AsmToken::LParen)) {
Daniel Dunbara4fc8d92009-07-31 22:22:54 +00002170 // Unless we have a segment register, treat this as an immediate.
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002171 if (SegReg == 0)
Craig Topper055845f2015-01-02 07:02:25 +00002172 return X86Operand::CreateMem(getPointerWidth(), Disp, LParenLoc,
2173 ExprEnd);
2174 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, 0, 0, 1,
2175 MemStart, ExprEnd);
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002176 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002177
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002178 // Eat the '('.
Sean Callanana83fd7d2010-01-19 20:27:46 +00002179 Parser.Lex();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002180 }
2181 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002182
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002183 // If we reached here, then we just ate the ( of the memory operand. Process
2184 // the rest of the memory operand.
Daniel Dunbar3ebf8482009-07-31 20:53:16 +00002185 unsigned BaseReg = 0, IndexReg = 0, Scale = 1;
David Woodhouse6dbda442014-01-08 12:58:28 +00002186 SMLoc IndexLoc, BaseLoc;
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002187
Chris Lattner0c2538f2010-01-15 18:51:29 +00002188 if (getLexer().is(AsmToken::Percent)) {
Benjamin Kramer1930b002011-10-16 12:10:27 +00002189 SMLoc StartLoc, EndLoc;
David Woodhouse6dbda442014-01-08 12:58:28 +00002190 BaseLoc = Parser.getTok().getLoc();
Craig Topper062a2ba2014-04-25 05:30:21 +00002191 if (ParseRegister(BaseReg, StartLoc, EndLoc)) return nullptr;
Bruno Cardoso Lopes306a1f92010-07-24 00:06:39 +00002192 if (BaseReg == X86::EIZ || BaseReg == X86::RIZ) {
Benjamin Kramer1930b002011-10-16 12:10:27 +00002193 Error(StartLoc, "eiz and riz can only be used as index registers",
2194 SMRange(StartLoc, EndLoc));
Craig Topper062a2ba2014-04-25 05:30:21 +00002195 return nullptr;
Bruno Cardoso Lopes306a1f92010-07-24 00:06:39 +00002196 }
Chris Lattner0c2538f2010-01-15 18:51:29 +00002197 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002198
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002199 if (getLexer().is(AsmToken::Comma)) {
Sean Callanana83fd7d2010-01-19 20:27:46 +00002200 Parser.Lex(); // Eat the comma.
Kevin Enderbyfb3110b2012-03-12 21:32:09 +00002201 IndexLoc = Parser.getTok().getLoc();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002202
2203 // Following the comma we should have either an index register, or a scale
2204 // value. We don't support the later form, but we want to parse it
2205 // correctly.
2206 //
2207 // Not that even though it would be completely consistent to support syntax
Bruno Cardoso Lopes306a1f92010-07-24 00:06:39 +00002208 // like "1(%eax,,1)", the assembler doesn't. Use "eiz" or "riz" for this.
Kevin Enderby7d912182009-09-03 17:15:07 +00002209 if (getLexer().is(AsmToken::Percent)) {
Chris Lattner0c2538f2010-01-15 18:51:29 +00002210 SMLoc L;
Douglas Katzman0411e862016-10-05 15:23:35 +00002211 if (ParseRegister(IndexReg, L, L))
2212 return nullptr;
2213 if (BaseReg == X86::RIP) {
2214 Error(IndexLoc, "%rip as base register can not have an index register");
2215 return nullptr;
2216 }
2217 if (IndexReg == X86::RIP) {
2218 Error(IndexLoc, "%rip is not allowed as an index register");
2219 return nullptr;
2220 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002221
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002222 if (getLexer().isNot(AsmToken::RParen)) {
2223 // Parse the scale amount:
2224 // ::= ',' [scale-expression]
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002225 if (getLexer().isNot(AsmToken::Comma)) {
Sean Callanan936b0d32010-01-19 21:44:56 +00002226 Error(Parser.getTok().getLoc(),
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002227 "expected comma in scale expression");
Craig Topper062a2ba2014-04-25 05:30:21 +00002228 return nullptr;
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002229 }
Sean Callanana83fd7d2010-01-19 20:27:46 +00002230 Parser.Lex(); // Eat the comma.
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002231
2232 if (getLexer().isNot(AsmToken::RParen)) {
Sean Callanan936b0d32010-01-19 21:44:56 +00002233 SMLoc Loc = Parser.getTok().getLoc();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002234
2235 int64_t ScaleVal;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00002236 if (getParser().parseAbsoluteExpression(ScaleVal)){
Kevin Enderbydeed5aa2012-03-09 22:24:10 +00002237 Error(Loc, "expected scale expression");
Craig Topper062a2ba2014-04-25 05:30:21 +00002238 return nullptr;
Craig Topper6bf3ed42012-07-18 04:59:16 +00002239 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002240
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002241 // Validate the scale amount.
NAKAMURA Takumi0a7d0ad2015-09-22 11:15:07 +00002242 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
David Woodhouse6dbda442014-01-08 12:58:28 +00002243 ScaleVal != 1) {
2244 Error(Loc, "scale factor in 16-bit address must be 1");
Craig Topper062a2ba2014-04-25 05:30:21 +00002245 return nullptr;
NAKAMURA Takumi0a7d0ad2015-09-22 11:15:07 +00002246 }
2247 if (ScaleVal != 1 && ScaleVal != 2 && ScaleVal != 4 &&
2248 ScaleVal != 8) {
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002249 Error(Loc, "scale factor in address must be 1, 2, 4 or 8");
Craig Topper062a2ba2014-04-25 05:30:21 +00002250 return nullptr;
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002251 }
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002252 Scale = (unsigned)ScaleVal;
2253 }
2254 }
2255 } else if (getLexer().isNot(AsmToken::RParen)) {
Daniel Dunbar94b84a12010-08-24 19:13:38 +00002256 // A scale amount without an index is ignored.
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002257 // index.
Sean Callanan936b0d32010-01-19 21:44:56 +00002258 SMLoc Loc = Parser.getTok().getLoc();
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002259
2260 int64_t Value;
Jim Grosbachd2037eb2013-02-20 22:21:35 +00002261 if (getParser().parseAbsoluteExpression(Value))
Craig Topper062a2ba2014-04-25 05:30:21 +00002262 return nullptr;
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002263
Daniel Dunbar94b84a12010-08-24 19:13:38 +00002264 if (Value != 1)
2265 Warning(Loc, "scale factor without index register is ignored");
2266 Scale = 1;
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002267 }
2268 }
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002269
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002270 // Ok, we've eaten the memory operand, verify we have a ')' and eat it too.
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002271 if (getLexer().isNot(AsmToken::RParen)) {
Sean Callanan936b0d32010-01-19 21:44:56 +00002272 Error(Parser.getTok().getLoc(), "unexpected token in memory operand");
Craig Topper062a2ba2014-04-25 05:30:21 +00002273 return nullptr;
Chris Lattnera2bbb7c2010-01-15 18:44:13 +00002274 }
Jordan Rosee8f1eae2013-01-07 19:00:49 +00002275 SMLoc MemEnd = Parser.getTok().getEndLoc();
Sean Callanana83fd7d2010-01-19 20:27:46 +00002276 Parser.Lex(); // Eat the ')'.
Bruno Cardoso Lopesd65cd1d2010-07-23 22:15:26 +00002277
David Woodhouse6dbda442014-01-08 12:58:28 +00002278 // Check for use of invalid 16-bit registers. Only BX/BP/SI/DI are allowed,
2279 // and then only in non-64-bit modes. Except for DX, which is a special case
2280 // because an unofficial form of in/out instructions uses it.
2281 if (X86MCRegisterClasses[X86::GR16RegClassID].contains(BaseReg) &&
2282 (is64BitMode() || (BaseReg != X86::BX && BaseReg != X86::BP &&
2283 BaseReg != X86::SI && BaseReg != X86::DI)) &&
2284 BaseReg != X86::DX) {
2285 Error(BaseLoc, "invalid 16-bit base register");
Craig Topper062a2ba2014-04-25 05:30:21 +00002286 return nullptr;
David Woodhouse6dbda442014-01-08 12:58:28 +00002287 }
2288 if (BaseReg == 0 &&
2289 X86MCRegisterClasses[X86::GR16RegClassID].contains(IndexReg)) {
2290 Error(IndexLoc, "16-bit memory operand may not include only index register");
Craig Topper062a2ba2014-04-25 05:30:21 +00002291 return nullptr;
David Woodhouse6dbda442014-01-08 12:58:28 +00002292 }
Kevin Enderbybc570f22014-01-23 22:34:42 +00002293
2294 StringRef ErrMsg;
Andrew V. Tischenko32e9b1a2017-07-25 13:05:12 +00002295 if (CheckBaseRegAndIndexRegAndScale(BaseReg, IndexReg, Scale, ErrMsg)) {
Kevin Enderbybc570f22014-01-23 22:34:42 +00002296 Error(BaseLoc, ErrMsg);
Craig Topper062a2ba2014-04-25 05:30:21 +00002297 return nullptr;
Kevin Enderbyfb3110b2012-03-12 21:32:09 +00002298 }
2299
Reid Klecknerb7e2f602014-07-31 23:26:35 +00002300 if (SegReg || BaseReg || IndexReg)
Craig Topper055845f2015-01-02 07:02:25 +00002301 return X86Operand::CreateMem(getPointerWidth(), SegReg, Disp, BaseReg,
2302 IndexReg, Scale, MemStart, MemEnd);
2303 return X86Operand::CreateMem(getPointerWidth(), Disp, MemStart, MemEnd);
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002304}
2305
David Blaikie960ea3f2014-06-08 16:18:35 +00002306bool X86AsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
2307 SMLoc NameLoc, OperandVector &Operands) {
Rafael Espindola961d4692014-11-11 05:18:41 +00002308 MCAsmParser &Parser = getParser();
Chad Rosierf0e87202012-10-25 20:41:34 +00002309 InstInfo = &Info;
Chris Lattner2cb092d2010-10-30 19:23:13 +00002310 StringRef PatchedName = Name;
Daniel Dunbar0e767d72010-05-25 19:49:32 +00002311
Michael Zuckerman174d2e72016-10-14 08:09:40 +00002312 if (Name == "jmp" && isParsingIntelSyntax() && isParsingInlineAsm()) {
2313 StringRef NextTok = Parser.getTok().getString();
2314 if (NextTok == "short") {
2315 SMLoc NameEndLoc =
2316 NameLoc.getFromPointer(NameLoc.getPointer() + Name.size());
2317 // Eat the short keyword
2318 Parser.Lex();
2319 // MS ignores the short keyword, it determines the jmp type based
2320 // on the distance of the label
2321 InstInfo->AsmRewrites->emplace_back(AOK_Skip, NameEndLoc,
2322 NextTok.size() + 1);
2323 }
2324 }
2325
Chris Lattner7e8a99b2010-11-28 20:23:50 +00002326 // FIXME: Hack to recognize setneb as setne.
2327 if (PatchedName.startswith("set") && PatchedName.endswith("b") &&
2328 PatchedName != "setb" && PatchedName != "setnb")
2329 PatchedName = PatchedName.substr(0, Name.size()-1);
Chad Rosier51afe632012-06-27 22:34:28 +00002330
Daniel Dunbar0e767d72010-05-25 19:49:32 +00002331 // FIXME: Hack to recognize cmp<comparison code>{ss,sd,ps,pd}.
Bruno Cardoso Lopes3183dd52010-06-23 21:10:57 +00002332 if ((PatchedName.startswith("cmp") || PatchedName.startswith("vcmp")) &&
Daniel Dunbar0e767d72010-05-25 19:49:32 +00002333 (PatchedName.endswith("ss") || PatchedName.endswith("sd") ||
2334 PatchedName.endswith("ps") || PatchedName.endswith("pd"))) {
Craig Toppera0a603e2012-03-29 07:11:23 +00002335 bool IsVCMP = PatchedName[0] == 'v';
Craig Topper78c424d2015-02-15 07:13:48 +00002336 unsigned CCIdx = IsVCMP ? 4 : 3;
2337 unsigned ComparisonCode = StringSwitch<unsigned>(
2338 PatchedName.slice(CCIdx, PatchedName.size() - 2))
Craig Toppera0a603e2012-03-29 07:11:23 +00002339 .Case("eq", 0x00)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002340 .Case("eq_oq", 0x00)
Craig Toppera0a603e2012-03-29 07:11:23 +00002341 .Case("lt", 0x01)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002342 .Case("lt_os", 0x01)
Craig Toppera0a603e2012-03-29 07:11:23 +00002343 .Case("le", 0x02)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002344 .Case("le_os", 0x02)
Craig Toppera0a603e2012-03-29 07:11:23 +00002345 .Case("unord", 0x03)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002346 .Case("unord_q", 0x03)
Craig Toppera0a603e2012-03-29 07:11:23 +00002347 .Case("neq", 0x04)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002348 .Case("neq_uq", 0x04)
Craig Toppera0a603e2012-03-29 07:11:23 +00002349 .Case("nlt", 0x05)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002350 .Case("nlt_us", 0x05)
Craig Toppera0a603e2012-03-29 07:11:23 +00002351 .Case("nle", 0x06)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002352 .Case("nle_us", 0x06)
Craig Toppera0a603e2012-03-29 07:11:23 +00002353 .Case("ord", 0x07)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002354 .Case("ord_q", 0x07)
Craig Toppera0a603e2012-03-29 07:11:23 +00002355 /* AVX only from here */
2356 .Case("eq_uq", 0x08)
2357 .Case("nge", 0x09)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002358 .Case("nge_us", 0x09)
Bruno Cardoso Lopes6c614512010-07-07 22:24:03 +00002359 .Case("ngt", 0x0A)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002360 .Case("ngt_us", 0x0A)
Bruno Cardoso Lopes6c614512010-07-07 22:24:03 +00002361 .Case("false", 0x0B)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002362 .Case("false_oq", 0x0B)
Bruno Cardoso Lopes6c614512010-07-07 22:24:03 +00002363 .Case("neq_oq", 0x0C)
2364 .Case("ge", 0x0D)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002365 .Case("ge_os", 0x0D)
Bruno Cardoso Lopes6c614512010-07-07 22:24:03 +00002366 .Case("gt", 0x0E)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002367 .Case("gt_os", 0x0E)
Bruno Cardoso Lopes6c614512010-07-07 22:24:03 +00002368 .Case("true", 0x0F)
Michael Zuckerman72b72232016-01-25 08:43:26 +00002369 .Case("true_uq", 0x0F)
Bruno Cardoso Lopes6c614512010-07-07 22:24:03 +00002370 .Case("eq_os", 0x10)
2371 .Case("lt_oq", 0x11)
2372 .Case("le_oq", 0x12)
2373 .Case("unord_s", 0x13)
2374 .Case("neq_us", 0x14)
2375 .Case("nlt_uq", 0x15)
2376 .Case("nle_uq", 0x16)
2377 .Case("ord_s", 0x17)
2378 .Case("eq_us", 0x18)
2379 .Case("nge_uq", 0x19)
2380 .Case("ngt_uq", 0x1A)
2381 .Case("false_os", 0x1B)
2382 .Case("neq_os", 0x1C)
2383 .Case("ge_oq", 0x1D)
2384 .Case("gt_oq", 0x1E)
2385 .Case("true_us", 0x1F)
Daniel Dunbar0e767d72010-05-25 19:49:32 +00002386 .Default(~0U);
Craig Topper78c424d2015-02-15 07:13:48 +00002387 if (ComparisonCode != ~0U && (IsVCMP || ComparisonCode < 8)) {
Craig Topper43860832015-02-14 21:54:03 +00002388
Craig Topper78c424d2015-02-15 07:13:48 +00002389 Operands.push_back(X86Operand::CreateToken(PatchedName.slice(0, CCIdx),
Craig Topper43860832015-02-14 21:54:03 +00002390 NameLoc));
2391
Jim Grosbach13760bd2015-05-30 01:25:56 +00002392 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
Craig Topper43860832015-02-14 21:54:03 +00002393 getParser().getContext());
2394 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2395
2396 PatchedName = PatchedName.substr(PatchedName.size() - 2);
Daniel Dunbar0e767d72010-05-25 19:49:32 +00002397 }
2398 }
Bruno Cardoso Lopesea0e05a2010-07-23 18:41:12 +00002399
Craig Topper78c424d2015-02-15 07:13:48 +00002400 // FIXME: Hack to recognize vpcmp<comparison code>{ub,uw,ud,uq,b,w,d,q}.
2401 if (PatchedName.startswith("vpcmp") &&
2402 (PatchedName.endswith("b") || PatchedName.endswith("w") ||
2403 PatchedName.endswith("d") || PatchedName.endswith("q"))) {
2404 unsigned CCIdx = PatchedName.drop_back().back() == 'u' ? 2 : 1;
2405 unsigned ComparisonCode = StringSwitch<unsigned>(
2406 PatchedName.slice(5, PatchedName.size() - CCIdx))
2407 .Case("eq", 0x0) // Only allowed on unsigned. Checked below.
2408 .Case("lt", 0x1)
2409 .Case("le", 0x2)
2410 //.Case("false", 0x3) // Not a documented alias.
2411 .Case("neq", 0x4)
2412 .Case("nlt", 0x5)
2413 .Case("nle", 0x6)
2414 //.Case("true", 0x7) // Not a documented alias.
2415 .Default(~0U);
2416 if (ComparisonCode != ~0U && (ComparisonCode != 0 || CCIdx == 2)) {
2417 Operands.push_back(X86Operand::CreateToken("vpcmp", NameLoc));
2418
Jim Grosbach13760bd2015-05-30 01:25:56 +00002419 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
Craig Topper78c424d2015-02-15 07:13:48 +00002420 getParser().getContext());
2421 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2422
2423 PatchedName = PatchedName.substr(PatchedName.size() - CCIdx);
2424 }
2425 }
2426
Craig Topper916708f2015-02-13 07:42:25 +00002427 // FIXME: Hack to recognize vpcom<comparison code>{ub,uw,ud,uq,b,w,d,q}.
2428 if (PatchedName.startswith("vpcom") &&
2429 (PatchedName.endswith("b") || PatchedName.endswith("w") ||
2430 PatchedName.endswith("d") || PatchedName.endswith("q"))) {
Craig Topper78c424d2015-02-15 07:13:48 +00002431 unsigned CCIdx = PatchedName.drop_back().back() == 'u' ? 2 : 1;
2432 unsigned ComparisonCode = StringSwitch<unsigned>(
2433 PatchedName.slice(5, PatchedName.size() - CCIdx))
Craig Topper916708f2015-02-13 07:42:25 +00002434 .Case("lt", 0x0)
2435 .Case("le", 0x1)
2436 .Case("gt", 0x2)
2437 .Case("ge", 0x3)
2438 .Case("eq", 0x4)
2439 .Case("neq", 0x5)
2440 .Case("false", 0x6)
2441 .Case("true", 0x7)
2442 .Default(~0U);
Craig Topper78c424d2015-02-15 07:13:48 +00002443 if (ComparisonCode != ~0U) {
Craig Topper916708f2015-02-13 07:42:25 +00002444 Operands.push_back(X86Operand::CreateToken("vpcom", NameLoc));
2445
Jim Grosbach13760bd2015-05-30 01:25:56 +00002446 const MCExpr *ImmOp = MCConstantExpr::create(ComparisonCode,
Craig Topper916708f2015-02-13 07:42:25 +00002447 getParser().getContext());
2448 Operands.push_back(X86Operand::CreateImm(ImmOp, NameLoc, NameLoc));
2449
Craig Topper78c424d2015-02-15 07:13:48 +00002450 PatchedName = PatchedName.substr(PatchedName.size() - CCIdx);
Craig Topper916708f2015-02-13 07:42:25 +00002451 }
2452 }
2453
Daniel Dunbar3e0c9792010-02-10 21:19:28 +00002454 Operands.push_back(X86Operand::CreateToken(PatchedName, NameLoc));
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002455
Chris Lattner086a83a2010-09-08 05:17:37 +00002456 // Determine whether this is an instruction prefix.
2457 bool isPrefix =
Chris Lattner2cb092d2010-10-30 19:23:13 +00002458 Name == "lock" || Name == "rep" ||
2459 Name == "repe" || Name == "repz" ||
Rafael Espindolaf6c05b12010-11-23 11:23:24 +00002460 Name == "repne" || Name == "repnz" ||
Marina Yatsina197db002017-01-18 08:07:51 +00002461 Name == "rex64" || Name == "data16" || Name == "data32";
Michael J. Spencer530ce852010-10-09 11:00:50 +00002462
Marina Yatsina5f5de9f2016-03-07 18:11:16 +00002463 bool CurlyAsEndOfStatement = false;
Chris Lattner086a83a2010-09-08 05:17:37 +00002464 // This does the actual operand parsing. Don't parse any more if we have a
2465 // prefix juxtaposed with an operation like "lock incl 4(%rax)", because we
2466 // just want to parse the "lock" as the first instruction and the "incl" as
2467 // the next one.
2468 if (getLexer().isNot(AsmToken::EndOfStatement) && !isPrefix) {
Daniel Dunbar71527c12009-08-11 05:00:25 +00002469
2470 // Parse '*' modifier.
Alp Tokera5b88a52013-12-02 16:06:06 +00002471 if (getLexer().is(AsmToken::Star))
2472 Operands.push_back(X86Operand::CreateToken("*", consumeToken()));
Daniel Dunbar71527c12009-08-11 05:00:25 +00002473
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002474 // Read the operands.
Kirill Bobyrev6afbaf02017-01-18 16:34:25 +00002475 while(1) {
David Blaikie960ea3f2014-06-08 16:18:35 +00002476 if (std::unique_ptr<X86Operand> Op = ParseOperand()) {
2477 Operands.push_back(std::move(Op));
Michael Zuckerman1bee6342016-10-18 13:52:39 +00002478 if (HandleAVX512Operand(Operands, *Operands.back()))
Elena Demikhovsky89529742013-09-12 08:55:00 +00002479 return true;
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002480 } else {
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002481 return true;
Elena Demikhovsky89529742013-09-12 08:55:00 +00002482 }
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002483 // check for comma and eat it
2484 if (getLexer().is(AsmToken::Comma))
2485 Parser.Lex();
2486 else
2487 break;
2488 }
Elena Demikhovsky89529742013-09-12 08:55:00 +00002489
Hiroshi Inouee9dea6e2017-07-13 06:48:39 +00002490 // In MS inline asm curly braces mark the beginning/end of a block,
2491 // therefore they should be interepreted as end of statement
Marina Yatsina5f5de9f2016-03-07 18:11:16 +00002492 CurlyAsEndOfStatement =
2493 isParsingIntelSyntax() && isParsingInlineAsm() &&
2494 (getLexer().is(AsmToken::LCurly) || getLexer().is(AsmToken::RCurly));
2495 if (getLexer().isNot(AsmToken::EndOfStatement) && !CurlyAsEndOfStatement)
Nirav Dave2364748a2016-09-16 18:30:20 +00002496 return TokError("unexpected token in argument list");
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002497 }
Michael J. Spencer530ce852010-10-09 11:00:50 +00002498
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002499 // Consume the EndOfStatement or the prefix separator Slash
Elena Demikhovsky9f09b3e2014-02-20 07:00:10 +00002500 if (getLexer().is(AsmToken::EndOfStatement) ||
2501 (isPrefix && getLexer().is(AsmToken::Slash)))
Elena Demikhovskyc9657012014-02-20 06:34:39 +00002502 Parser.Lex();
Marina Yatsina5f5de9f2016-03-07 18:11:16 +00002503 else if (CurlyAsEndOfStatement)
2504 // Add an actual EndOfStatement before the curly brace
2505 Info.AsmRewrites->emplace_back(AOK_EndOfStatement,
2506 getLexer().getTok().getLoc(), 0);
Daniel Dunbare1fdb0e2009-07-28 22:40:46 +00002507
Michael Zuckermanfd3fe9e2015-11-12 16:58:51 +00002508 // This is for gas compatibility and cannot be done in td.
2509 // Adding "p" for some floating point with no argument.
2510 // For example: fsub --> fsubp
2511 bool IsFp =
2512 Name == "fsub" || Name == "fdiv" || Name == "fsubr" || Name == "fdivr";
2513 if (IsFp && Operands.size() == 1) {
2514 const char *Repl = StringSwitch<const char *>(Name)
2515 .Case("fsub", "fsubp")
2516 .Case("fdiv", "fdivp")
2517 .Case("fsubr", "fsubrp")
2518 .Case("fdivr", "fdivrp");
2519 static_cast<X86Operand &>(*Operands[0]).setTokenValue(Repl);
2520 }
2521
Nirav Davef45fd2b2016-08-08 18:01:04 +00002522 // Moving a 32 or 16 bit value into a segment register has the same
2523 // behavior. Modify such instructions to always take shorter form.
2524 if ((Name == "mov" || Name == "movw" || Name == "movl") &&
2525 (Operands.size() == 3)) {
2526 X86Operand &Op1 = (X86Operand &)*Operands[1];
2527 X86Operand &Op2 = (X86Operand &)*Operands[2];
2528 SMLoc Loc = Op1.getEndLoc();
2529 if (Op1.isReg() && Op2.isReg() &&
2530 X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(
2531 Op2.getReg()) &&
2532 (X86MCRegisterClasses[X86::GR16RegClassID].contains(Op1.getReg()) ||
2533 X86MCRegisterClasses[X86::GR32RegClassID].contains(Op1.getReg()))) {
2534 // Change instruction name to match new instruction.
2535 if (Name != "mov" && Name[3] == (is16BitMode() ? 'l' : 'w')) {
2536 Name = is16BitMode() ? "movw" : "movl";
2537 Operands[0] = X86Operand::CreateToken(Name, NameLoc);
2538 }
2539 // Select the correct equivalent 16-/32-bit source register.
2540 unsigned Reg =
2541 getX86SubSuperRegisterOrZero(Op1.getReg(), is16BitMode() ? 16 : 32);
2542 Operands[1] = X86Operand::CreateReg(Reg, Loc, Loc);
2543 }
2544 }
2545
Nirav Dave8e103802016-06-29 19:54:27 +00002546 // This is a terrible hack to handle "out[s]?[bwl]? %al, (%dx)" ->
Chris Lattnerb6f8e822010-11-06 19:25:43 +00002547 // "outb %al, %dx". Out doesn't take a memory form, but this is a widely
2548 // documented form in various unofficial manuals, so a lot of code uses it.
Nirav Dave8e103802016-06-29 19:54:27 +00002549 if ((Name == "outb" || Name == "outsb" || Name == "outw" || Name == "outsw" ||
2550 Name == "outl" || Name == "outsl" || Name == "out" || Name == "outs") &&
Chris Lattnerb6f8e822010-11-06 19:25:43 +00002551 Operands.size() == 3) {
David Blaikie960ea3f2014-06-08 16:18:35 +00002552 X86Operand &Op = (X86Operand &)*Operands.back();
Chris Lattnerb6f8e822010-11-06 19:25:43 +00002553 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2554 isa<MCConstantExpr>(Op.Mem.Disp) &&
2555 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2556 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2557 SMLoc Loc = Op.getEndLoc();
2558 Operands.back() = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
Chris Lattnerb6f8e822010-11-06 19:25:43 +00002559 }
2560 }
Nirav Dave8e103802016-06-29 19:54:27 +00002561 // Same hack for "in[s]?[bwl]? (%dx), %al" -> "inb %dx, %al".
2562 if ((Name == "inb" || Name == "insb" || Name == "inw" || Name == "insw" ||
2563 Name == "inl" || Name == "insl" || Name == "in" || Name == "ins") &&
Joerg Sonnenbergerb7e635d2011-02-22 20:40:09 +00002564 Operands.size() == 3) {
David Blaikie960ea3f2014-06-08 16:18:35 +00002565 X86Operand &Op = (X86Operand &)*Operands[1];
Joerg Sonnenbergerb7e635d2011-02-22 20:40:09 +00002566 if (Op.isMem() && Op.Mem.SegReg == 0 &&
2567 isa<MCConstantExpr>(Op.Mem.Disp) &&
2568 cast<MCConstantExpr>(Op.Mem.Disp)->getValue() == 0 &&
2569 Op.Mem.BaseReg == MatchRegisterName("dx") && Op.Mem.IndexReg == 0) {
2570 SMLoc Loc = Op.getEndLoc();
David Blaikie960ea3f2014-06-08 16:18:35 +00002571 Operands[1] = X86Operand::CreateReg(Op.Mem.BaseReg, Loc, Loc);
Joerg Sonnenbergerb7e635d2011-02-22 20:40:09 +00002572 }
2573 }
David Woodhouse4ce66062014-01-22 15:08:55 +00002574
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002575 SmallVector<std::unique_ptr<MCParsedAsmOperand>, 2> TmpOperands;
2576 bool HadVerifyError = false;
2577
David Woodhouse4ce66062014-01-22 15:08:55 +00002578 // Append default arguments to "ins[bwld]"
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002579 if (Name.startswith("ins") &&
2580 (Operands.size() == 1 || Operands.size() == 3) &&
2581 (Name == "insb" || Name == "insw" || Name == "insl" || Name == "insd" ||
2582 Name == "ins")) {
2583
2584 AddDefaultSrcDestOperands(TmpOperands,
Michael Kupersteinffcc7662015-07-23 10:23:48 +00002585 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc),
2586 DefaultMemDIOperand(NameLoc));
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002587 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
Joerg Sonnenberger3fbfcc02011-03-18 11:59:40 +00002588 }
2589
David Woodhousec472b812014-01-22 15:08:49 +00002590 // Append default arguments to "outs[bwld]"
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002591 if (Name.startswith("outs") &&
2592 (Operands.size() == 1 || Operands.size() == 3) &&
David Woodhousec472b812014-01-22 15:08:49 +00002593 (Name == "outsb" || Name == "outsw" || Name == "outsl" ||
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002594 Name == "outsd" || Name == "outs")) {
2595 AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
Michael Kupersteinffcc7662015-07-23 10:23:48 +00002596 X86Operand::CreateReg(X86::DX, NameLoc, NameLoc));
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002597 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
Joerg Sonnenberger3fbfcc02011-03-18 11:59:40 +00002598 }
2599
David Woodhouse2ef8d9c2014-01-22 15:08:08 +00002600 // Transform "lods[bwlq]" into "lods[bwlq] ($SIREG)" for appropriate
2601 // values of $SIREG according to the mode. It would be nice if this
2602 // could be achieved with InstAlias in the tables.
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002603 if (Name.startswith("lods") &&
2604 (Operands.size() == 1 || Operands.size() == 2) &&
Joerg Sonnenberger3fbfcc02011-03-18 11:59:40 +00002605 (Name == "lods" || Name == "lodsb" || Name == "lodsw" ||
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002606 Name == "lodsl" || Name == "lodsd" || Name == "lodsq")) {
2607 TmpOperands.push_back(DefaultMemSIOperand(NameLoc));
2608 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2609 }
David Woodhouse2ef8d9c2014-01-22 15:08:08 +00002610
David Woodhouseb33c2ef2014-01-22 15:08:21 +00002611 // Transform "stos[bwlq]" into "stos[bwlq] ($DIREG)" for appropriate
2612 // values of $DIREG according to the mode. It would be nice if this
2613 // could be achieved with InstAlias in the tables.
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002614 if (Name.startswith("stos") &&
2615 (Operands.size() == 1 || Operands.size() == 2) &&
Joerg Sonnenberger3fbfcc02011-03-18 11:59:40 +00002616 (Name == "stos" || Name == "stosb" || Name == "stosw" ||
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002617 Name == "stosl" || Name == "stosd" || Name == "stosq")) {
2618 TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
2619 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2620 }
Joerg Sonnenberger3fbfcc02011-03-18 11:59:40 +00002621
David Woodhouse20fe4802014-01-22 15:08:27 +00002622 // Transform "scas[bwlq]" into "scas[bwlq] ($DIREG)" for appropriate
2623 // values of $DIREG according to the mode. It would be nice if this
2624 // could be achieved with InstAlias in the tables.
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002625 if (Name.startswith("scas") &&
2626 (Operands.size() == 1 || Operands.size() == 2) &&
David Woodhouse20fe4802014-01-22 15:08:27 +00002627 (Name == "scas" || Name == "scasb" || Name == "scasw" ||
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002628 Name == "scasl" || Name == "scasd" || Name == "scasq")) {
2629 TmpOperands.push_back(DefaultMemDIOperand(NameLoc));
2630 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2631 }
David Woodhouse20fe4802014-01-22 15:08:27 +00002632
David Woodhouse9bbf7ca2014-01-22 15:08:36 +00002633 // Add default SI and DI operands to "cmps[bwlq]".
2634 if (Name.startswith("cmps") &&
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002635 (Operands.size() == 1 || Operands.size() == 3) &&
David Woodhouse9bbf7ca2014-01-22 15:08:36 +00002636 (Name == "cmps" || Name == "cmpsb" || Name == "cmpsw" ||
2637 Name == "cmpsl" || Name == "cmpsd" || Name == "cmpsq")) {
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002638 AddDefaultSrcDestOperands(TmpOperands, DefaultMemDIOperand(NameLoc),
2639 DefaultMemSIOperand(NameLoc));
2640 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
David Woodhouse9bbf7ca2014-01-22 15:08:36 +00002641 }
2642
David Woodhouse6f417de2014-01-22 15:08:42 +00002643 // Add default SI and DI operands to "movs[bwlq]".
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002644 if (((Name.startswith("movs") &&
2645 (Name == "movs" || Name == "movsb" || Name == "movsw" ||
2646 Name == "movsl" || Name == "movsd" || Name == "movsq")) ||
2647 (Name.startswith("smov") &&
2648 (Name == "smov" || Name == "smovb" || Name == "smovw" ||
2649 Name == "smovl" || Name == "smovd" || Name == "smovq"))) &&
2650 (Operands.size() == 1 || Operands.size() == 3)) {
Coby Tayree94ddbb42016-11-21 15:50:56 +00002651 if (Name == "movsd" && Operands.size() == 1 && !isParsingIntelSyntax())
Marina Yatsinab9f4f622016-01-19 15:37:56 +00002652 Operands.back() = X86Operand::CreateToken("movsl", NameLoc);
2653 AddDefaultSrcDestOperands(TmpOperands, DefaultMemSIOperand(NameLoc),
2654 DefaultMemDIOperand(NameLoc));
2655 HadVerifyError = VerifyAndAdjustOperands(Operands, TmpOperands);
2656 }
2657
2658 // Check if we encountered an error for one the string insturctions
2659 if (HadVerifyError) {
2660 return HadVerifyError;
David Woodhouse6f417de2014-01-22 15:08:42 +00002661 }
2662
Chris Lattner4bd21712010-09-15 04:33:27 +00002663 // FIXME: Hack to handle recognize s{hr,ar,hl} $1, <op>. Canonicalize to
Chris Lattner30561ab2010-09-11 16:32:12 +00002664 // "shift <op>".
Daniel Dunbar18fc3442010-03-13 00:47:29 +00002665 if ((Name.startswith("shr") || Name.startswith("sar") ||
Chris Lattner64f91b92010-11-06 21:23:40 +00002666 Name.startswith("shl") || Name.startswith("sal") ||
2667 Name.startswith("rcl") || Name.startswith("rcr") ||
2668 Name.startswith("rol") || Name.startswith("ror")) &&
Chris Lattner4cfbcdc2010-09-06 18:32:06 +00002669 Operands.size() == 3) {
Devang Patel9a9bb5c2012-01-30 20:02:42 +00002670 if (isParsingIntelSyntax()) {
Devang Patela410ed32012-01-24 21:43:36 +00002671 // Intel syntax
David Blaikie960ea3f2014-06-08 16:18:35 +00002672 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[2]);
2673 if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) &&
2674 cast<MCConstantExpr>(Op1.getImm())->getValue() == 1)
Craig Topper6bf3ed42012-07-18 04:59:16 +00002675 Operands.pop_back();
Devang Patela410ed32012-01-24 21:43:36 +00002676 } else {
David Blaikie960ea3f2014-06-08 16:18:35 +00002677 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2678 if (Op1.isImm() && isa<MCConstantExpr>(Op1.getImm()) &&
2679 cast<MCConstantExpr>(Op1.getImm())->getValue() == 1)
Craig Topper6bf3ed42012-07-18 04:59:16 +00002680 Operands.erase(Operands.begin() + 1);
Chris Lattner4cfbcdc2010-09-06 18:32:06 +00002681 }
Daniel Dunbarfbd12cc2010-03-20 22:36:38 +00002682 }
Chad Rosier51afe632012-06-27 22:34:28 +00002683
Chris Lattnerfc4fe002011-04-09 19:41:05 +00002684 // Transforms "int $3" into "int3" as a size optimization. We can't write an
2685 // instalias with an immediate operand yet.
2686 if (Name == "int" && Operands.size() == 2) {
David Blaikie960ea3f2014-06-08 16:18:35 +00002687 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
Duncan P. N. Exon Smithd5313222015-07-23 19:27:07 +00002688 if (Op1.isImm())
2689 if (auto *CE = dyn_cast<MCConstantExpr>(Op1.getImm()))
2690 if (CE->getValue() == 3) {
2691 Operands.erase(Operands.begin() + 1);
2692 static_cast<X86Operand &>(*Operands[0]).setTokenValue("int3");
2693 }
Chris Lattnerfc4fe002011-04-09 19:41:05 +00002694 }
Michael J. Spencer530ce852010-10-09 11:00:50 +00002695
Marina Yatsinad9658d12016-01-19 16:35:38 +00002696 // Transforms "xlat mem8" into "xlatb"
2697 if ((Name == "xlat" || Name == "xlatb") && Operands.size() == 2) {
2698 X86Operand &Op1 = static_cast<X86Operand &>(*Operands[1]);
2699 if (Op1.isMem8()) {
2700 Warning(Op1.getStartLoc(), "memory operand is only for determining the "
2701 "size, (R|E)BX will be used for the location");
2702 Operands.pop_back();
2703 static_cast<X86Operand &>(*Operands[0]).setTokenValue("xlatb");
2704 }
2705 }
2706
Chris Lattnerf29c0b62010-01-14 22:21:20 +00002707 return false;
Daniel Dunbar3c2a8932009-07-20 18:55:04 +00002708}
2709
David Blaikie960ea3f2014-06-08 16:18:35 +00002710bool X86AsmParser::processInstruction(MCInst &Inst, const OperandVector &Ops) {
Aaron Ballmana81264b2016-05-23 15:52:59 +00002711 return false;
Devang Patelde47cce2012-01-18 22:42:29 +00002712}
2713
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002714static const char *getSubtargetFeatureName(uint64_t Val);
Evgeniy Stepanov49e26252014-03-14 08:58:04 +00002715
David Blaikie960ea3f2014-06-08 16:18:35 +00002716void X86AsmParser::EmitInstruction(MCInst &Inst, OperandVector &Operands,
2717 MCStreamer &Out) {
Evgeniy Stepanov77ad8662014-07-31 09:11:04 +00002718 Instrumentation->InstrumentAndEmitInstruction(Inst, Operands, getContext(),
2719 MII, Out);
Evgeniy Stepanov49e26252014-03-14 08:58:04 +00002720}
2721
David Blaikie960ea3f2014-06-08 16:18:35 +00002722bool X86AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
2723 OperandVector &Operands,
Tim Northover26bb14e2014-08-18 11:49:42 +00002724 MCStreamer &Out, uint64_t &ErrorInfo,
David Blaikie960ea3f2014-06-08 16:18:35 +00002725 bool MatchingInlineAsm) {
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002726 if (isParsingIntelSyntax())
2727 return MatchAndEmitIntelInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002728 MatchingInlineAsm);
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002729 return MatchAndEmitATTInstruction(IDLoc, Opcode, Operands, Out, ErrorInfo,
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002730 MatchingInlineAsm);
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002731}
Daniel Dunbar2ecc3bb2010-08-12 00:55:38 +00002732
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002733void X86AsmParser::MatchFPUWaitAlias(SMLoc IDLoc, X86Operand &Op,
2734 OperandVector &Operands, MCStreamer &Out,
2735 bool MatchingInlineAsm) {
Chris Lattnera63292a2010-09-29 01:50:45 +00002736 // FIXME: This should be replaced with a real .td file alias mechanism.
Chad Rosier3b1336c2012-08-28 23:57:47 +00002737 // Also, MatchInstructionImpl should actually *do* the EmitInstruction
Chris Lattner4869d342010-11-06 19:57:21 +00002738 // call.
Reid Klecknerb1f2d2f2014-07-31 00:07:33 +00002739 const char *Repl = StringSwitch<const char *>(Op.getToken())
2740 .Case("finit", "fninit")
2741 .Case("fsave", "fnsave")
2742 .Case("fstcw", "fnstcw")
2743 .Case("fstcww", "fnstcw")
2744 .Case("fstenv", "fnstenv")
2745 .Case("fstsw", "fnstsw")
2746 .Case("fstsww", "fnstsw")
2747 .Case("fclex", "fnclex")
2748 .Default(nullptr);
2749 if (Repl) {
Chris Lattnera63292a2010-09-29 01:50:45 +00002750 MCInst Inst;
2751 Inst.setOpcode(X86::WAIT);
Jim Grosbach8f28dbd2012-01-27 00:51:27 +00002752 Inst.setLoc(IDLoc);
Chad Rosier4453e842012-10-12 23:09:25 +00002753 if (!MatchingInlineAsm)
Evgeniy Stepanov49e26252014-03-14 08:58:04 +00002754 EmitInstruction(Inst, Operands, Out);
Chris Lattneradc0dbe2010-09-30 16:39:29 +00002755 Operands[0] = X86Operand::CreateToken(Repl, IDLoc);
Chris Lattnera63292a2010-09-29 01:50:45 +00002756 }
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002757}
2758
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002759bool X86AsmParser::ErrorMissingFeature(SMLoc IDLoc, uint64_t ErrorInfo,
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002760 bool MatchingInlineAsm) {
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002761 assert(ErrorInfo && "Unknown missing feature!");
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002762 SmallString<126> Msg;
2763 raw_svector_ostream OS(Msg);
2764 OS << "instruction requires:";
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002765 uint64_t Mask = 1;
2766 for (unsigned i = 0; i < (sizeof(ErrorInfo)*8-1); ++i) {
2767 if (ErrorInfo & Mask)
2768 OS << ' ' << getSubtargetFeatureName(ErrorInfo & Mask);
2769 Mask <<= 1;
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002770 }
Nirav Dave2364748a2016-09-16 18:30:20 +00002771 return Error(IDLoc, OS.str(), SMRange(), MatchingInlineAsm);
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002772}
2773
2774bool X86AsmParser::MatchAndEmitATTInstruction(SMLoc IDLoc, unsigned &Opcode,
2775 OperandVector &Operands,
2776 MCStreamer &Out,
2777 uint64_t &ErrorInfo,
2778 bool MatchingInlineAsm) {
2779 assert(!Operands.empty() && "Unexpect empty operand list!");
2780 X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
2781 assert(Op.isToken() && "Leading operand should always be a mnemonic!");
Nirav Dave2364748a2016-09-16 18:30:20 +00002782 SMRange EmptyRange = None;
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002783
2784 // First, handle aliases that expand to multiple instructions.
2785 MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
Michael J. Spencer530ce852010-10-09 11:00:50 +00002786
Chris Lattner628fbec2010-09-06 21:54:15 +00002787 bool WasOriginallyInvalidOperand = false;
Chris Lattnerb44fd242010-09-29 01:42:58 +00002788 MCInst Inst;
Michael J. Spencer530ce852010-10-09 11:00:50 +00002789
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002790 // First, try a direct match.
Nirav Dave6477ce22016-09-26 19:33:36 +00002791 switch (MatchInstruction(Operands, Inst, ErrorInfo, MatchingInlineAsm,
2792 isParsingIntelSyntax())) {
Craig Topper589ceee2015-01-03 08:16:34 +00002793 default: llvm_unreachable("Unexpected match result!");
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002794 case Match_Success:
Devang Patelde47cce2012-01-18 22:42:29 +00002795 // Some instructions need post-processing to, for example, tweak which
2796 // encoding is selected. Loop on it while changes happen so the
Chad Rosier51afe632012-06-27 22:34:28 +00002797 // individual transformations can chain off each other.
Chad Rosier4453e842012-10-12 23:09:25 +00002798 if (!MatchingInlineAsm)
Chad Rosierf4e35dc2012-10-01 23:45:51 +00002799 while (processInstruction(Inst, Operands))
2800 ;
Devang Patelde47cce2012-01-18 22:42:29 +00002801
Jim Grosbach8f28dbd2012-01-27 00:51:27 +00002802 Inst.setLoc(IDLoc);
Chad Rosier4453e842012-10-12 23:09:25 +00002803 if (!MatchingInlineAsm)
Evgeniy Stepanov49e26252014-03-14 08:58:04 +00002804 EmitInstruction(Inst, Operands, Out);
Chad Rosierf4e35dc2012-10-01 23:45:51 +00002805 Opcode = Inst.getOpcode();
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002806 return false;
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002807 case Match_MissingFeature:
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002808 return ErrorMissingFeature(IDLoc, ErrorInfo, MatchingInlineAsm);
Chris Lattner628fbec2010-09-06 21:54:15 +00002809 case Match_InvalidOperand:
2810 WasOriginallyInvalidOperand = true;
2811 break;
2812 case Match_MnemonicFail:
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002813 break;
2814 }
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002815
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002816 // FIXME: Ideally, we would only attempt suffix matches for things which are
2817 // valid prefixes, and we could just infer the right unambiguous
2818 // type. However, that requires substantially more matcher support than the
2819 // following hack.
Michael J. Spencer530ce852010-10-09 11:00:50 +00002820
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002821 // Change the operand to point to a temporary token.
David Blaikie960ea3f2014-06-08 16:18:35 +00002822 StringRef Base = Op.getToken();
Daniel Dunbar2ecc3bb2010-08-12 00:55:38 +00002823 SmallString<16> Tmp;
2824 Tmp += Base;
2825 Tmp += ' ';
Yaron Keren075759a2015-03-30 15:42:36 +00002826 Op.setTokenValue(Tmp);
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002827
Chris Lattnerfab94132010-11-06 18:28:02 +00002828 // If this instruction starts with an 'f', then it is a floating point stack
2829 // instruction. These come in up to three forms for 32-bit, 64-bit, and
2830 // 80-bit floating point, which use the suffixes s,l,t respectively.
2831 //
2832 // Otherwise, we assume that this may be an integer instruction, which comes
2833 // in 8/16/32/64-bit forms using the b,w,l,q suffixes respectively.
2834 const char *Suffixes = Base[0] != 'f' ? "bwlq" : "slt\0";
Chad Rosier51afe632012-06-27 22:34:28 +00002835
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002836 // Check for the various suffix matches.
Tim Northover26bb14e2014-08-18 11:49:42 +00002837 uint64_t ErrorInfoIgnore;
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002838 uint64_t ErrorInfoMissingFeature = 0; // Init suppresses compiler warnings.
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002839 unsigned Match[4];
Chad Rosier51afe632012-06-27 22:34:28 +00002840
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002841 for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I) {
2842 Tmp.back() = Suffixes[I];
Nirav Dave6477ce22016-09-26 19:33:36 +00002843 Match[I] = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
2844 MatchingInlineAsm, isParsingIntelSyntax());
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002845 // If this returned as a missing feature failure, remember that.
2846 if (Match[I] == Match_MissingFeature)
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002847 ErrorInfoMissingFeature = ErrorInfoIgnore;
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002848 }
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002849
2850 // Restore the old token.
David Blaikie960ea3f2014-06-08 16:18:35 +00002851 Op.setTokenValue(Base);
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002852
2853 // If exactly one matched, then we treat that as a successful match (and the
2854 // instruction will already have been filled in correctly, since the failing
2855 // matches won't have modified it).
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002856 unsigned NumSuccessfulMatches =
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002857 std::count(std::begin(Match), std::end(Match), Match_Success);
Chris Lattnerb44fd242010-09-29 01:42:58 +00002858 if (NumSuccessfulMatches == 1) {
Jim Grosbach8f28dbd2012-01-27 00:51:27 +00002859 Inst.setLoc(IDLoc);
Chad Rosier4453e842012-10-12 23:09:25 +00002860 if (!MatchingInlineAsm)
Evgeniy Stepanov49e26252014-03-14 08:58:04 +00002861 EmitInstruction(Inst, Operands, Out);
Chad Rosierf4e35dc2012-10-01 23:45:51 +00002862 Opcode = Inst.getOpcode();
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002863 return false;
Chris Lattnerb44fd242010-09-29 01:42:58 +00002864 }
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002865
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002866 // Otherwise, the match failed, try to produce a decent error message.
Daniel Dunbar2ecc3bb2010-08-12 00:55:38 +00002867
Daniel Dunbar7d7b4d12010-08-12 00:55:42 +00002868 // If we had multiple suffix matches, then identify this as an ambiguous
2869 // match.
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002870 if (NumSuccessfulMatches > 1) {
Daniel Dunbar7d7b4d12010-08-12 00:55:42 +00002871 char MatchChars[4];
2872 unsigned NumMatches = 0;
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002873 for (unsigned I = 0, E = array_lengthof(Match); I != E; ++I)
2874 if (Match[I] == Match_Success)
2875 MatchChars[NumMatches++] = Suffixes[I];
Daniel Dunbar7d7b4d12010-08-12 00:55:42 +00002876
Alp Tokere69170a2014-06-26 22:52:05 +00002877 SmallString<126> Msg;
2878 raw_svector_ostream OS(Msg);
Daniel Dunbar7d7b4d12010-08-12 00:55:42 +00002879 OS << "ambiguous instructions require an explicit suffix (could be ";
2880 for (unsigned i = 0; i != NumMatches; ++i) {
2881 if (i != 0)
2882 OS << ", ";
2883 if (i + 1 == NumMatches)
2884 OS << "or ";
2885 OS << "'" << Base << MatchChars[i] << "'";
2886 }
2887 OS << ")";
Nirav Dave2364748a2016-09-16 18:30:20 +00002888 Error(IDLoc, OS.str(), EmptyRange, MatchingInlineAsm);
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002889 return true;
Daniel Dunbar7d7b4d12010-08-12 00:55:42 +00002890 }
Michael J. Spencer530ce852010-10-09 11:00:50 +00002891
Chris Lattner628fbec2010-09-06 21:54:15 +00002892 // Okay, we know that none of the variants matched successfully.
Michael J. Spencer530ce852010-10-09 11:00:50 +00002893
Chris Lattner628fbec2010-09-06 21:54:15 +00002894 // If all of the instructions reported an invalid mnemonic, then the original
2895 // mnemonic was invalid.
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002896 if (std::count(std::begin(Match), std::end(Match), Match_MnemonicFail) == 4) {
Chris Lattner339cc7b2010-09-06 22:11:18 +00002897 if (!WasOriginallyInvalidOperand) {
Benjamin Kramerd416bae2011-10-16 11:28:29 +00002898 return Error(IDLoc, "invalid instruction mnemonic '" + Base + "'",
Nirav Dave2364748a2016-09-16 18:30:20 +00002899 Op.getLocRange(), MatchingInlineAsm);
Chris Lattner339cc7b2010-09-06 22:11:18 +00002900 }
2901
2902 // Recover location info for the operand if we know which was the problem.
Tim Northover26bb14e2014-08-18 11:49:42 +00002903 if (ErrorInfo != ~0ULL) {
Chad Rosier49963552012-10-13 00:26:04 +00002904 if (ErrorInfo >= Operands.size())
Nirav Dave2364748a2016-09-16 18:30:20 +00002905 return Error(IDLoc, "too few operands for instruction", EmptyRange,
2906 MatchingInlineAsm);
Michael J. Spencer530ce852010-10-09 11:00:50 +00002907
David Blaikie960ea3f2014-06-08 16:18:35 +00002908 X86Operand &Operand = (X86Operand &)*Operands[ErrorInfo];
2909 if (Operand.getStartLoc().isValid()) {
2910 SMRange OperandRange = Operand.getLocRange();
2911 return Error(Operand.getStartLoc(), "invalid operand for instruction",
Chad Rosier4453e842012-10-12 23:09:25 +00002912 OperandRange, MatchingInlineAsm);
Chris Lattnera3a06812011-10-16 04:47:35 +00002913 }
Chris Lattner339cc7b2010-09-06 22:11:18 +00002914 }
2915
Nirav Dave2364748a2016-09-16 18:30:20 +00002916 return Error(IDLoc, "invalid operand for instruction", EmptyRange,
Chad Rosier4453e842012-10-12 23:09:25 +00002917 MatchingInlineAsm);
Chris Lattner628fbec2010-09-06 21:54:15 +00002918 }
Michael J. Spencer530ce852010-10-09 11:00:50 +00002919
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002920 // If one instruction matched with a missing feature, report this as a
2921 // missing feature.
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002922 if (std::count(std::begin(Match), std::end(Match),
2923 Match_MissingFeature) == 1) {
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00002924 ErrorInfo = ErrorInfoMissingFeature;
2925 return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature,
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002926 MatchingInlineAsm);
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002927 }
Michael J. Spencer530ce852010-10-09 11:00:50 +00002928
Chris Lattner628fbec2010-09-06 21:54:15 +00002929 // If one instruction matched with an invalid operand, report this as an
2930 // operand failure.
Reid Kleckner7b1e1a02014-07-30 22:23:11 +00002931 if (std::count(std::begin(Match), std::end(Match),
2932 Match_InvalidOperand) == 1) {
Nirav Dave2364748a2016-09-16 18:30:20 +00002933 return Error(IDLoc, "invalid operand for instruction", EmptyRange,
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002934 MatchingInlineAsm);
Chris Lattner628fbec2010-09-06 21:54:15 +00002935 }
Michael J. Spencer530ce852010-10-09 11:00:50 +00002936
Chris Lattnerb4be28f2010-09-06 20:08:02 +00002937 // If all of these were an outright failure, report it in a useless way.
Chad Rosier3d4bc622012-08-21 19:36:59 +00002938 Error(IDLoc, "unknown use of instruction mnemonic without a size suffix",
Nirav Dave2364748a2016-09-16 18:30:20 +00002939 EmptyRange, MatchingInlineAsm);
Daniel Dunbar9b816a12010-05-04 16:12:42 +00002940 return true;
2941}
2942
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002943bool X86AsmParser::MatchAndEmitIntelInstruction(SMLoc IDLoc, unsigned &Opcode,
2944 OperandVector &Operands,
2945 MCStreamer &Out,
2946 uint64_t &ErrorInfo,
2947 bool MatchingInlineAsm) {
2948 assert(!Operands.empty() && "Unexpect empty operand list!");
2949 X86Operand &Op = static_cast<X86Operand &>(*Operands[0]);
2950 assert(Op.isToken() && "Leading operand should always be a mnemonic!");
2951 StringRef Mnemonic = Op.getToken();
Nirav Dave2364748a2016-09-16 18:30:20 +00002952 SMRange EmptyRange = None;
Nirav Daveee554e62016-10-06 15:28:08 +00002953 StringRef Base = Op.getToken();
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002954
2955 // First, handle aliases that expand to multiple instructions.
2956 MatchFPUWaitAlias(IDLoc, Op, Operands, Out, MatchingInlineAsm);
2957
2958 MCInst Inst;
2959
2960 // Find one unsized memory operand, if present.
2961 X86Operand *UnsizedMemOp = nullptr;
2962 for (const auto &Op : Operands) {
2963 X86Operand *X86Op = static_cast<X86Operand *>(Op.get());
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00002964 if (X86Op->isMemUnsized()) {
2965 UnsizedMemOp = X86Op;
Coby Tayree49b37332016-11-22 09:30:29 +00002966 // Have we found an unqualified memory operand,
2967 // break. IA allows only one memory operand.
2968 break;
2969 }
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002970 }
2971
2972 // Allow some instructions to have implicitly pointer-sized operands. This is
2973 // compatible with gas.
2974 if (UnsizedMemOp) {
2975 static const char *const PtrSizedInstrs[] = {"call", "jmp", "push"};
2976 for (const char *Instr : PtrSizedInstrs) {
2977 if (Mnemonic == Instr) {
Craig Topper055845f2015-01-02 07:02:25 +00002978 UnsizedMemOp->Mem.Size = getPointerWidth();
Reid Klecknerf6fb7802014-08-26 20:32:34 +00002979 break;
2980 }
2981 }
2982 }
2983
Nirav Daveee554e62016-10-06 15:28:08 +00002984 SmallVector<unsigned, 8> Match;
2985 uint64_t ErrorInfoMissingFeature = 0;
2986
2987 // If unsized push has immediate operand we should default the default pointer
2988 // size for the size.
2989 if (Mnemonic == "push" && Operands.size() == 2) {
2990 auto *X86Op = static_cast<X86Operand *>(Operands[1].get());
2991 if (X86Op->isImm()) {
2992 // If it's not a constant fall through and let remainder take care of it.
2993 const auto *CE = dyn_cast<MCConstantExpr>(X86Op->getImm());
2994 unsigned Size = getPointerWidth();
2995 if (CE &&
2996 (isIntN(Size, CE->getValue()) || isUIntN(Size, CE->getValue()))) {
2997 SmallString<16> Tmp;
2998 Tmp += Base;
2999 Tmp += (is64BitMode())
3000 ? "q"
3001 : (is32BitMode()) ? "l" : (is16BitMode()) ? "w" : " ";
3002 Op.setTokenValue(Tmp);
3003 // Do match in ATT mode to allow explicit suffix usage.
3004 Match.push_back(MatchInstruction(Operands, Inst, ErrorInfo,
3005 MatchingInlineAsm,
3006 false /*isParsingIntelSyntax()*/));
3007 Op.setTokenValue(Base);
3008 }
3009 }
3010 }
3011
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003012 // If an unsized memory operand is present, try to match with each memory
3013 // operand size. In Intel assembly, the size is not part of the instruction
3014 // mnemonic.
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003015 if (UnsizedMemOp && UnsizedMemOp->isMemUnsized()) {
Ahmed Bougachad65f7872014-12-03 02:03:26 +00003016 static const unsigned MopSizes[] = {8, 16, 32, 64, 80, 128, 256, 512};
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003017 for (unsigned Size : MopSizes) {
3018 UnsizedMemOp->Mem.Size = Size;
3019 uint64_t ErrorInfoIgnore;
Reid Kleckner7b7a5992014-08-27 20:10:38 +00003020 unsigned LastOpcode = Inst.getOpcode();
Nirav Dave6477ce22016-09-26 19:33:36 +00003021 unsigned M = MatchInstruction(Operands, Inst, ErrorInfoIgnore,
3022 MatchingInlineAsm, isParsingIntelSyntax());
Reid Kleckner7b7a5992014-08-27 20:10:38 +00003023 if (Match.empty() || LastOpcode != Inst.getOpcode())
3024 Match.push_back(M);
3025
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003026 // If this returned as a missing feature failure, remember that.
3027 if (Match.back() == Match_MissingFeature)
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00003028 ErrorInfoMissingFeature = ErrorInfoIgnore;
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003029 }
Reid Kleckner7b7a5992014-08-27 20:10:38 +00003030
3031 // Restore the size of the unsized memory operand if we modified it.
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00003032 UnsizedMemOp->Mem.Size = 0;
Reid Kleckner7b7a5992014-08-27 20:10:38 +00003033 }
3034
3035 // If we haven't matched anything yet, this is not a basic integer or FPU
Saleem Abdulrasoolc3f8ad32015-01-16 20:16:06 +00003036 // operation. There shouldn't be any ambiguity in our mnemonic table, so try
Reid Kleckner7b7a5992014-08-27 20:10:38 +00003037 // matching with the unsized operand.
3038 if (Match.empty()) {
Nirav Dave6477ce22016-09-26 19:33:36 +00003039 Match.push_back(MatchInstruction(
3040 Operands, Inst, ErrorInfo, MatchingInlineAsm, isParsingIntelSyntax()));
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003041 // If this returned as a missing feature failure, remember that.
3042 if (Match.back() == Match_MissingFeature)
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00003043 ErrorInfoMissingFeature = ErrorInfo;
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003044 }
3045
3046 // Restore the size of the unsized memory operand if we modified it.
3047 if (UnsizedMemOp)
3048 UnsizedMemOp->Mem.Size = 0;
3049
3050 // If it's a bad mnemonic, all results will be the same.
3051 if (Match.back() == Match_MnemonicFail) {
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003052 return Error(IDLoc, "invalid instruction mnemonic '" + Mnemonic + "'",
Nirav Dave2364748a2016-09-16 18:30:20 +00003053 Op.getLocRange(), MatchingInlineAsm);
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003054 }
3055
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00003056 unsigned NumSuccessfulMatches =
3057 std::count(std::begin(Match), std::end(Match), Match_Success);
3058
3059 // If matching was ambiguous and we had size information from the frontend,
3060 // try again with that. This handles cases like "movxz eax, m8/m16".
3061 if (UnsizedMemOp && NumSuccessfulMatches > 1 &&
3062 UnsizedMemOp->getMemFrontendSize()) {
3063 UnsizedMemOp->Mem.Size = UnsizedMemOp->getMemFrontendSize();
3064 unsigned M = MatchInstruction(
3065 Operands, Inst, ErrorInfo, MatchingInlineAsm, isParsingIntelSyntax());
3066 if (M == Match_Success)
3067 NumSuccessfulMatches = 1;
3068
3069 // Add a rewrite that encodes the size information we used from the
3070 // frontend.
3071 InstInfo->AsmRewrites->emplace_back(
3072 AOK_SizeDirective, UnsizedMemOp->getStartLoc(),
3073 /*Len=*/0, UnsizedMemOp->getMemFrontendSize());
3074 }
3075
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003076 // If exactly one matched, then we treat that as a successful match (and the
3077 // instruction will already have been filled in correctly, since the failing
3078 // matches won't have modified it).
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003079 if (NumSuccessfulMatches == 1) {
3080 // Some instructions need post-processing to, for example, tweak which
3081 // encoding is selected. Loop on it while changes happen so the individual
3082 // transformations can chain off each other.
3083 if (!MatchingInlineAsm)
3084 while (processInstruction(Inst, Operands))
3085 ;
3086 Inst.setLoc(IDLoc);
3087 if (!MatchingInlineAsm)
3088 EmitInstruction(Inst, Operands, Out);
3089 Opcode = Inst.getOpcode();
3090 return false;
3091 } else if (NumSuccessfulMatches > 1) {
3092 assert(UnsizedMemOp &&
3093 "multiple matches only possible with unsized memory operands");
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003094 return Error(UnsizedMemOp->getStartLoc(),
3095 "ambiguous operand size for instruction '" + Mnemonic + "\'",
Reid Kleckner6d2ea6e2017-05-04 18:19:52 +00003096 UnsizedMemOp->getLocRange());
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003097 }
3098
3099 // If one instruction matched with a missing feature, report this as a
3100 // missing feature.
3101 if (std::count(std::begin(Match), std::end(Match),
3102 Match_MissingFeature) == 1) {
Ranjeet Singh86ecbb72015-06-30 12:32:53 +00003103 ErrorInfo = ErrorInfoMissingFeature;
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003104 return ErrorMissingFeature(IDLoc, ErrorInfoMissingFeature,
3105 MatchingInlineAsm);
3106 }
3107
3108 // If one instruction matched with an invalid operand, report this as an
3109 // operand failure.
3110 if (std::count(std::begin(Match), std::end(Match),
3111 Match_InvalidOperand) == 1) {
Nirav Dave2364748a2016-09-16 18:30:20 +00003112 return Error(IDLoc, "invalid operand for instruction", EmptyRange,
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003113 MatchingInlineAsm);
3114 }
3115
3116 // If all of these were an outright failure, report it in a useless way.
Nirav Dave2364748a2016-09-16 18:30:20 +00003117 return Error(IDLoc, "unknown instruction mnemonic", EmptyRange,
Reid Klecknerf6fb7802014-08-26 20:32:34 +00003118 MatchingInlineAsm);
3119}
3120
Nico Weber42f79db2014-07-17 20:24:55 +00003121bool X86AsmParser::OmitRegisterFromClobberLists(unsigned RegNo) {
3122 return X86MCRegisterClasses[X86::SEGMENT_REGRegClassID].contains(RegNo);
3123}
Daniel Dunbar9b816a12010-05-04 16:12:42 +00003124
Devang Patel4a6e7782012-01-12 18:03:40 +00003125bool X86AsmParser::ParseDirective(AsmToken DirectiveID) {
Rafael Espindola961d4692014-11-11 05:18:41 +00003126 MCAsmParser &Parser = getParser();
Chris Lattner72c0b592010-10-30 17:38:55 +00003127 StringRef IDVal = DirectiveID.getIdentifier();
3128 if (IDVal == ".word")
3129 return ParseDirectiveWord(2, DirectiveID.getLoc());
Evan Cheng481ebb02011-07-27 00:38:12 +00003130 else if (IDVal.startswith(".code"))
3131 return ParseDirectiveCode(IDVal, DirectiveID.getLoc());
Chad Rosier6f8d8b22012-09-10 20:54:39 +00003132 else if (IDVal.startswith(".att_syntax")) {
Andrew V. Tischenkoc3c67232017-04-26 09:56:59 +00003133 getParser().setParsingInlineAsm(false);
Reid Klecknerce63b792014-08-06 23:21:13 +00003134 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3135 if (Parser.getTok().getString() == "prefix")
3136 Parser.Lex();
3137 else if (Parser.getTok().getString() == "noprefix")
3138 return Error(DirectiveID.getLoc(), "'.att_syntax noprefix' is not "
3139 "supported: registers must have a "
3140 "'%' prefix in .att_syntax");
3141 }
Chad Rosier6f8d8b22012-09-10 20:54:39 +00003142 getParser().setAssemblerDialect(0);
3143 return false;
3144 } else if (IDVal.startswith(".intel_syntax")) {
Devang Patela173ee52012-01-31 18:14:05 +00003145 getParser().setAssemblerDialect(1);
Andrew V. Tischenkoc3c67232017-04-26 09:56:59 +00003146 getParser().setParsingInlineAsm(true);
Devang Patel9a9bb5c2012-01-30 20:02:42 +00003147 if (getLexer().isNot(AsmToken::EndOfStatement)) {
Saleem Abdulrasoola6505ca2014-01-13 01:15:39 +00003148 if (Parser.getTok().getString() == "noprefix")
Craig Topper6bf3ed42012-07-18 04:59:16 +00003149 Parser.Lex();
Reid Klecknerce63b792014-08-06 23:21:13 +00003150 else if (Parser.getTok().getString() == "prefix")
3151 return Error(DirectiveID.getLoc(), "'.intel_syntax prefix' is not "
3152 "supported: registers must not have "
3153 "a '%' prefix in .intel_syntax");
Devang Patel9a9bb5c2012-01-30 20:02:42 +00003154 }
3155 return false;
Michael Zuckerman02ecd432015-12-13 17:07:23 +00003156 } else if (IDVal == ".even")
3157 return parseDirectiveEven(DirectiveID.getLoc());
Chris Lattner72c0b592010-10-30 17:38:55 +00003158 return true;
3159}
3160
Michael Zuckerman02ecd432015-12-13 17:07:23 +00003161/// parseDirectiveEven
3162/// ::= .even
3163bool X86AsmParser::parseDirectiveEven(SMLoc L) {
Michael Zuckerman02ecd432015-12-13 17:07:23 +00003164 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3165 TokError("unexpected token in directive");
3166 return false;
3167 }
Eric Christopher445c9522016-10-14 05:47:37 +00003168 const MCSection *Section = getStreamer().getCurrentSectionOnly();
Michael Zuckerman02ecd432015-12-13 17:07:23 +00003169 if (!Section) {
3170 getStreamer().InitSections(false);
Eric Christopher445c9522016-10-14 05:47:37 +00003171 Section = getStreamer().getCurrentSectionOnly();
Michael Zuckerman02ecd432015-12-13 17:07:23 +00003172 }
3173 if (Section->UseCodeAlign())
3174 getStreamer().EmitCodeAlignment(2, 0);
3175 else
3176 getStreamer().EmitValueToAlignment(2, 0, 1, 0);
3177 return false;
3178}
Chris Lattner72c0b592010-10-30 17:38:55 +00003179/// ParseDirectiveWord
3180/// ::= .word [ expression (, expression)* ]
Devang Patel4a6e7782012-01-12 18:03:40 +00003181bool X86AsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
Rafael Espindola961d4692014-11-11 05:18:41 +00003182 MCAsmParser &Parser = getParser();
Chris Lattner72c0b592010-10-30 17:38:55 +00003183 if (getLexer().isNot(AsmToken::EndOfStatement)) {
3184 for (;;) {
3185 const MCExpr *Value;
David Majnemera375b262015-10-26 02:45:50 +00003186 SMLoc ExprLoc = getLexer().getLoc();
Jim Grosbachd2037eb2013-02-20 22:21:35 +00003187 if (getParser().parseExpression(Value))
Saleem Abdulrasoola6505ca2014-01-13 01:15:39 +00003188 return false;
Chad Rosier51afe632012-06-27 22:34:28 +00003189
David Majnemera375b262015-10-26 02:45:50 +00003190 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
3191 assert(Size <= 8 && "Invalid size");
3192 uint64_t IntValue = MCE->getValue();
3193 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
3194 return Error(ExprLoc, "literal value out of range for directive");
3195 getStreamer().EmitIntValue(IntValue, Size);
3196 } else {
3197 getStreamer().EmitValue(Value, Size, ExprLoc);
3198 }
Chad Rosier51afe632012-06-27 22:34:28 +00003199
Chris Lattner72c0b592010-10-30 17:38:55 +00003200 if (getLexer().is(AsmToken::EndOfStatement))
3201 break;
Chad Rosier51afe632012-06-27 22:34:28 +00003202
Chris Lattner72c0b592010-10-30 17:38:55 +00003203 // FIXME: Improve diagnostic.
Saleem Abdulrasoola6505ca2014-01-13 01:15:39 +00003204 if (getLexer().isNot(AsmToken::Comma)) {
3205 Error(L, "unexpected token in directive");
3206 return false;
3207 }
Chris Lattner72c0b592010-10-30 17:38:55 +00003208 Parser.Lex();
3209 }
3210 }
Chad Rosier51afe632012-06-27 22:34:28 +00003211
Chris Lattner72c0b592010-10-30 17:38:55 +00003212 Parser.Lex();
3213 return false;
3214}
3215
Evan Cheng481ebb02011-07-27 00:38:12 +00003216/// ParseDirectiveCode
Craig Topper3c80d622014-01-06 04:55:54 +00003217/// ::= .code16 | .code32 | .code64
Devang Patel4a6e7782012-01-12 18:03:40 +00003218bool X86AsmParser::ParseDirectiveCode(StringRef IDVal, SMLoc L) {
Rafael Espindola961d4692014-11-11 05:18:41 +00003219 MCAsmParser &Parser = getParser();
Nirav Dave6477ce22016-09-26 19:33:36 +00003220 Code16GCC = false;
Craig Topper3c80d622014-01-06 04:55:54 +00003221 if (IDVal == ".code16") {
Evan Cheng481ebb02011-07-27 00:38:12 +00003222 Parser.Lex();
Craig Topper3c80d622014-01-06 04:55:54 +00003223 if (!is16BitMode()) {
3224 SwitchMode(X86::Mode16Bit);
3225 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3226 }
Nirav Dave6477ce22016-09-26 19:33:36 +00003227 } else if (IDVal == ".code16gcc") {
3228 // .code16gcc parses as if in 32-bit mode, but emits code in 16-bit mode.
3229 Parser.Lex();
3230 Code16GCC = true;
3231 if (!is16BitMode()) {
3232 SwitchMode(X86::Mode16Bit);
3233 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code16);
3234 }
Saleem Abdulrasoola6505ca2014-01-13 01:15:39 +00003235 } else if (IDVal == ".code32") {
Craig Topper3c80d622014-01-06 04:55:54 +00003236 Parser.Lex();
3237 if (!is32BitMode()) {
3238 SwitchMode(X86::Mode32Bit);
Evan Cheng481ebb02011-07-27 00:38:12 +00003239 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code32);
3240 }
3241 } else if (IDVal == ".code64") {
3242 Parser.Lex();
3243 if (!is64BitMode()) {
Craig Topper3c80d622014-01-06 04:55:54 +00003244 SwitchMode(X86::Mode64Bit);
Evan Cheng481ebb02011-07-27 00:38:12 +00003245 getParser().getStreamer().EmitAssemblerFlag(MCAF_Code64);
3246 }
3247 } else {
Saleem Abdulrasoola6505ca2014-01-13 01:15:39 +00003248 Error(L, "unknown directive " + IDVal);
3249 return false;
Evan Cheng481ebb02011-07-27 00:38:12 +00003250 }
Chris Lattner72c0b592010-10-30 17:38:55 +00003251
Evan Cheng481ebb02011-07-27 00:38:12 +00003252 return false;
3253}
Chris Lattner72c0b592010-10-30 17:38:55 +00003254
Daniel Dunbar71475772009-07-17 20:42:00 +00003255// Force static initialization.
3256extern "C" void LLVMInitializeX86AsmParser() {
Mehdi Aminif42454b2016-10-09 23:00:34 +00003257 RegisterMCAsmParser<X86AsmParser> X(getTheX86_32Target());
3258 RegisterMCAsmParser<X86AsmParser> Y(getTheX86_64Target());
Daniel Dunbar71475772009-07-17 20:42:00 +00003259}
Daniel Dunbar00331992009-07-29 00:02:19 +00003260
Chris Lattner3e4582a2010-09-06 19:11:01 +00003261#define GET_REGISTER_MATCHER
3262#define GET_MATCHER_IMPLEMENTATION
Jim Grosbach6f1f41b2012-11-14 18:04:47 +00003263#define GET_SUBTARGET_FEATURE_NAME
Daniel Dunbar00331992009-07-29 00:02:19 +00003264#include "X86GenAsmMatcher.inc"