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Matt Arsenault0c90e952015-11-06 18:17:45 +00001//=====-- AMDGPUSubtarget.h - Define Subtarget for AMDGPU ------*- C++ -*-====//
Tom Stellard75aadc22012-12-11 21:25:42 +00002//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9//
10/// \file
Adrian Prantl5f8f34e42018-05-01 15:54:18 +000011/// AMDGPU specific subclass of TargetSubtarget.
Tom Stellard75aadc22012-12-11 21:25:42 +000012//
13//===----------------------------------------------------------------------===//
14
Matt Arsenault0c90e952015-11-06 18:17:45 +000015#ifndef LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
16#define LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H
Matt Arsenaultf59e5382015-11-06 18:23:00 +000017
Tom Stellarda6c6e1b2013-06-07 20:37:48 +000018#include "AMDGPU.h"
Quentin Colombet61d71a12017-08-15 22:31:51 +000019#include "AMDGPUCallLowering.h"
Matt Arsenault43e92fe2016-06-24 06:30:11 +000020#include "R600FrameLowering.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000021#include "R600ISelLowering.h"
22#include "R600InstrInfo.h"
Matt Arsenault43e92fe2016-06-24 06:30:11 +000023#include "SIFrameLowering.h"
Chandler Carruth6bda14b2017-06-06 11:49:48 +000024#include "SIISelLowering.h"
25#include "SIInstrInfo.h"
Tom Stellard347ac792015-06-26 21:15:07 +000026#include "Utils/AMDGPUBaseInfo.h"
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000027#include "llvm/ADT/Triple.h"
Quentin Colombet61d71a12017-08-15 22:31:51 +000028#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
29#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
30#include "llvm/CodeGen/GlobalISel/RegisterBankInfo.h"
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000031#include "llvm/CodeGen/MachineFunction.h"
Matt Arsenault56684d42016-08-11 17:31:42 +000032#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
Eugene Zelenko2bc2f332016-12-09 22:06:55 +000033#include "llvm/MC/MCInstrItineraries.h"
34#include "llvm/Support/MathExtras.h"
35#include <cassert>
36#include <cstdint>
37#include <memory>
38#include <utility>
Tom Stellard75aadc22012-12-11 21:25:42 +000039
40#define GET_SUBTARGETINFO_HEADER
41#include "AMDGPUGenSubtargetInfo.inc"
Tom Stellardc5a154d2018-06-28 23:47:12 +000042#define GET_SUBTARGETINFO_HEADER
43#include "R600GenSubtargetInfo.inc"
Tom Stellard75aadc22012-12-11 21:25:42 +000044
Tom Stellard75aadc22012-12-11 21:25:42 +000045namespace llvm {
46
Matt Arsenault43e92fe2016-06-24 06:30:11 +000047class StringRef;
Tom Stellarde99fb652015-01-20 19:33:04 +000048
Tom Stellard5bfbae52018-07-11 20:59:01 +000049class AMDGPUSubtarget {
50public:
51 enum Generation {
52 R600 = 0,
53 R700 = 1,
Matt Arsenault4bec7d42018-07-20 09:05:08 +000054 EVERGREEN = 2,
Tom Stellard5bfbae52018-07-11 20:59:01 +000055 NORTHERN_ISLANDS = 3,
56 SOUTHERN_ISLANDS = 4,
57 SEA_ISLANDS = 5,
58 VOLCANIC_ISLANDS = 6,
59 GFX9 = 7
60 };
61
Tom Stellardc5a154d2018-06-28 23:47:12 +000062private:
63 Triple TargetTriple;
64
65protected:
Tom Stellardc5a154d2018-06-28 23:47:12 +000066 bool Has16BitInsts;
67 bool HasMadMixInsts;
68 bool FP32Denormals;
69 bool FPExceptions;
70 bool HasSDWA;
71 bool HasVOP3PInsts;
72 bool HasMulI24;
73 bool HasMulU24;
Matt Arsenault6c7ba822018-08-15 21:03:55 +000074 bool HasInv2PiInlineImm;
Tom Stellardc5a154d2018-06-28 23:47:12 +000075 bool HasFminFmaxLegacy;
76 bool EnablePromoteAlloca;
David Stuttard20de3e92018-09-14 10:27:19 +000077 bool HasTrigReducedRange;
Tom Stellardc5a154d2018-06-28 23:47:12 +000078 int LocalMemorySize;
79 unsigned WavefrontSize;
80
81public:
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +000082 AMDGPUSubtarget(const Triple &TT);
Tom Stellardc5a154d2018-06-28 23:47:12 +000083
Tom Stellard5bfbae52018-07-11 20:59:01 +000084 static const AMDGPUSubtarget &get(const MachineFunction &MF);
85 static const AMDGPUSubtarget &get(const TargetMachine &TM,
Matt Arsenault4bec7d42018-07-20 09:05:08 +000086 const Function &F);
Tom Stellardc5a154d2018-06-28 23:47:12 +000087
88 /// \returns Default range flat work group size for a calling convention.
89 std::pair<unsigned, unsigned> getDefaultFlatWorkGroupSize(CallingConv::ID CC) const;
90
91 /// \returns Subtarget's default pair of minimum/maximum flat work group sizes
92 /// for function \p F, or minimum/maximum flat work group sizes explicitly
93 /// requested using "amdgpu-flat-work-group-size" attribute attached to
94 /// function \p F.
95 ///
96 /// \returns Subtarget's default values if explicitly requested values cannot
97 /// be converted to integer, or violate subtarget's specifications.
98 std::pair<unsigned, unsigned> getFlatWorkGroupSizes(const Function &F) const;
99
100 /// \returns Subtarget's default pair of minimum/maximum number of waves per
101 /// execution unit for function \p F, or minimum/maximum number of waves per
102 /// execution unit explicitly requested using "amdgpu-waves-per-eu" attribute
103 /// attached to function \p F.
104 ///
105 /// \returns Subtarget's default values if explicitly requested values cannot
106 /// be converted to integer, violate subtarget's specifications, or are not
107 /// compatible with minimum/maximum number of waves limited by flat work group
108 /// size, register usage, and/or lds usage.
109 std::pair<unsigned, unsigned> getWavesPerEU(const Function &F) const;
110
111 /// Return the amount of LDS that can be used that will not restrict the
112 /// occupancy lower than WaveCount.
113 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
114 const Function &) const;
115
116 /// Inverse of getMaxLocalMemWithWaveCount. Return the maximum wavecount if
117 /// the given LDS memory size is the only constraint.
118 unsigned getOccupancyWithLocalMemSize(uint32_t Bytes, const Function &) const;
119
120 unsigned getOccupancyWithLocalMemSize(const MachineFunction &MF) const;
121
122 bool isAmdHsaOS() const {
123 return TargetTriple.getOS() == Triple::AMDHSA;
124 }
125
126 bool isAmdPalOS() const {
127 return TargetTriple.getOS() == Triple::AMDPAL;
128 }
129
Tom Stellardec4feae2018-07-06 17:16:17 +0000130 bool isMesa3DOS() const {
131 return TargetTriple.getOS() == Triple::Mesa3D;
132 }
133
134 bool isMesaKernel(const Function &F) const {
135 return isMesa3DOS() && !AMDGPU::isShader(F.getCallingConv());
136 }
137
Konstantin Zhuravlyovaa067cb2018-10-04 21:02:16 +0000138 bool isAmdHsaOrMesa(const Function &F) const {
Tom Stellardec4feae2018-07-06 17:16:17 +0000139 return isAmdHsaOS() || isMesaKernel(F);
140 }
141
Tom Stellardc5a154d2018-06-28 23:47:12 +0000142 bool has16BitInsts() const {
143 return Has16BitInsts;
144 }
145
146 bool hasMadMixInsts() const {
147 return HasMadMixInsts;
148 }
149
150 bool hasFP32Denormals() const {
151 return FP32Denormals;
152 }
153
154 bool hasFPExceptions() const {
155 return FPExceptions;
156 }
157
158 bool hasSDWA() const {
159 return HasSDWA;
160 }
161
162 bool hasVOP3PInsts() const {
163 return HasVOP3PInsts;
164 }
165
166 bool hasMulI24() const {
167 return HasMulI24;
168 }
169
170 bool hasMulU24() const {
171 return HasMulU24;
172 }
173
Matt Arsenault6c7ba822018-08-15 21:03:55 +0000174 bool hasInv2PiInlineImm() const {
175 return HasInv2PiInlineImm;
176 }
177
Tom Stellardc5a154d2018-06-28 23:47:12 +0000178 bool hasFminFmaxLegacy() const {
179 return HasFminFmaxLegacy;
180 }
181
David Stuttard20de3e92018-09-14 10:27:19 +0000182 bool hasTrigReducedRange() const {
183 return HasTrigReducedRange;
184 }
185
Tom Stellardc5a154d2018-06-28 23:47:12 +0000186 bool isPromoteAllocaEnabled() const {
187 return EnablePromoteAlloca;
188 }
189
190 unsigned getWavefrontSize() const {
191 return WavefrontSize;
192 }
193
194 int getLocalMemorySize() const {
195 return LocalMemorySize;
196 }
197
198 unsigned getAlignmentForImplicitArgPtr() const {
199 return isAmdHsaOS() ? 8 : 4;
200 }
201
Tom Stellardec4feae2018-07-06 17:16:17 +0000202 /// Returns the offset in bytes from the start of the input buffer
203 /// of the first explicit kernel argument.
204 unsigned getExplicitKernelArgOffset(const Function &F) const {
Konstantin Zhuravlyovaa067cb2018-10-04 21:02:16 +0000205 return isAmdHsaOrMesa(F) ? 0 : 36;
Tom Stellardec4feae2018-07-06 17:16:17 +0000206 }
207
Tom Stellardc5a154d2018-06-28 23:47:12 +0000208 /// \returns Maximum number of work groups per compute unit supported by the
209 /// subtarget and limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000210 virtual unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const = 0;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000211
212 /// \returns Minimum flat work group size supported by the subtarget.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000213 virtual unsigned getMinFlatWorkGroupSize() const = 0;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000214
215 /// \returns Maximum flat work group size supported by the subtarget.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000216 virtual unsigned getMaxFlatWorkGroupSize() const = 0;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000217
218 /// \returns Maximum number of waves per execution unit supported by the
219 /// subtarget and limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000220 virtual unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const = 0;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000221
222 /// \returns Minimum number of waves per execution unit supported by the
223 /// subtarget.
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000224 virtual unsigned getMinWavesPerEU() const = 0;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000225
226 unsigned getMaxWavesPerEU() const { return 10; }
227
228 /// Creates value range metadata on an workitemid.* inrinsic call or load.
229 bool makeLIDRangeMetadata(Instruction *I) const;
230
Matt Arsenault4bec7d42018-07-20 09:05:08 +0000231 /// \returns Number of bytes of arguments that are passed to a shader or
232 /// kernel in addition to the explicit ones declared for the function.
233 unsigned getImplicitArgNumBytes(const Function &F) const {
234 if (isMesaKernel(F))
235 return 16;
236 return AMDGPU::getIntegerAttribute(F, "amdgpu-implicitarg-num-bytes", 0);
237 }
238 uint64_t getExplicitKernArgSize(const Function &F,
239 unsigned &MaxAlign) const;
240 unsigned getKernArgSegmentSize(const Function &F,
241 unsigned &MaxAlign) const;
242
Tom Stellard5bfbae52018-07-11 20:59:01 +0000243 virtual ~AMDGPUSubtarget() {}
Tom Stellardc5a154d2018-06-28 23:47:12 +0000244};
245
Tom Stellard5bfbae52018-07-11 20:59:01 +0000246class GCNSubtarget : public AMDGPUGenSubtargetInfo,
247 public AMDGPUSubtarget {
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000248public:
Marek Olsak4d00dd22015-03-09 15:48:09 +0000249 enum {
Tom Stellard347ac792015-06-26 21:15:07 +0000250 ISAVersion0_0_0,
Wei Ding7c3e5112017-06-10 03:53:19 +0000251 ISAVersion6_0_0,
252 ISAVersion6_0_1,
Tom Stellard347ac792015-06-26 21:15:07 +0000253 ISAVersion7_0_0,
254 ISAVersion7_0_1,
Yaxun Liu94add852016-10-26 16:37:56 +0000255 ISAVersion7_0_2,
Wei Ding7c3e5112017-06-10 03:53:19 +0000256 ISAVersion7_0_3,
Konstantin Zhuravlyovc40d9f22017-12-08 20:52:28 +0000257 ISAVersion7_0_4,
Changpeng Fangc16be002016-01-13 20:39:25 +0000258 ISAVersion8_0_1,
Changpeng Fang98317d22016-10-11 16:00:47 +0000259 ISAVersion8_0_2,
Yaxun Liu94add852016-10-26 16:37:56 +0000260 ISAVersion8_0_3,
Yaxun Liu94add852016-10-26 16:37:56 +0000261 ISAVersion8_1_0,
Matt Arsenaulte823d922017-02-18 18:29:53 +0000262 ISAVersion9_0_0,
Matt Arsenault0084adc2018-04-30 19:08:16 +0000263 ISAVersion9_0_2,
264 ISAVersion9_0_4,
Konstantin Zhuravlyov1501af42018-05-01 18:47:48 +0000265 ISAVersion9_0_6,
Tim Renouf2a1b1d92018-10-24 08:14:07 +0000266 ISAVersion9_0_9,
Tom Stellard347ac792015-06-26 21:15:07 +0000267 };
268
Wei Ding205bfdb2017-02-10 02:15:29 +0000269 enum TrapHandlerAbi {
270 TrapHandlerAbiNone = 0,
271 TrapHandlerAbiHsa = 1
272 };
273
Wei Dingf2cce022017-02-22 23:22:19 +0000274 enum TrapID {
275 TrapIDHardwareReserved = 0,
276 TrapIDHSADebugTrap = 1,
277 TrapIDLLVMTrap = 2,
278 TrapIDLLVMDebugTrap = 3,
279 TrapIDDebugBreakpoint = 7,
280 TrapIDDebugReserved8 = 8,
281 TrapIDDebugReservedFE = 0xfe,
282 TrapIDDebugReservedFF = 0xff
Wei Ding205bfdb2017-02-10 02:15:29 +0000283 };
284
285 enum TrapRegValues {
Wei Dingf2cce022017-02-22 23:22:19 +0000286 LLVMTrapHandlerRegValue = 1
Wei Ding205bfdb2017-02-10 02:15:29 +0000287 };
288
Tom Stellardc5a154d2018-06-28 23:47:12 +0000289private:
Tom Stellardc5a154d2018-06-28 23:47:12 +0000290 /// GlobalISel related APIs.
291 std::unique_ptr<AMDGPUCallLowering> CallLoweringInfo;
292 std::unique_ptr<InstructionSelector> InstSelector;
293 std::unique_ptr<LegalizerInfo> Legalizer;
294 std::unique_ptr<RegisterBankInfo> RegBankInfo;
295
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000296protected:
297 // Basic subtarget description.
298 Triple TargetTriple;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000299 unsigned Gen;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000300 unsigned IsaVersion;
Stanislav Mekhanoshin06d3b412018-09-17 16:04:32 +0000301 InstrItineraryData InstrItins;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000302 int LDSBankCount;
303 unsigned MaxPrivateElementSize;
304
305 // Possibly statically set by tablegen, but may want to be overridden.
Matt Arsenaultb035a572015-01-29 19:34:25 +0000306 bool FastFMAF32;
Matt Arsenaulte83690c2016-01-18 21:13:50 +0000307 bool HalfRate64Ops;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000308
309 // Dynamially set bits that enable features.
Matt Arsenaulta6867fd2017-01-23 22:31:03 +0000310 bool FP64FP16Denormals;
Matt Arsenault2fdf2a12017-02-21 23:35:48 +0000311 bool DX10Clamp;
Changpeng Fangb41574a2015-12-22 20:55:23 +0000312 bool FlatForGlobal;
Konstantin Zhuravlyovbe6c0ca2017-06-02 17:40:26 +0000313 bool AutoWaitcntBeforeBarrier;
Konstantin Zhuravlyoveda425e2017-10-14 15:59:07 +0000314 bool CodeObjectV3;
Tom Stellard64a9d082016-10-14 18:10:39 +0000315 bool UnalignedScratchAccess;
Matt Arsenault7f681ac2016-07-01 23:03:44 +0000316 bool UnalignedBufferAccess;
Matt Arsenaulte823d922017-02-18 18:29:53 +0000317 bool HasApertureRegs;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000318 bool EnableXNACK;
Wei Ding205bfdb2017-02-10 02:15:29 +0000319 bool TrapHandler;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000320 bool DebuggerInsertNops;
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +0000321 bool DebuggerEmitPrologue;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000322
323 // Used as options.
Matt Arsenault45b98182017-11-15 00:45:43 +0000324 bool EnableHugePrivateBuffer;
Matt Arsenault41033282014-10-10 22:01:59 +0000325 bool EnableLoadStoreOpt;
Matt Arsenault706f9302015-07-06 16:01:58 +0000326 bool EnableUnsafeDSOffsetFolding;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000327 bool EnableSIScheduler;
Marek Olsaka9a58fa2018-04-10 22:48:23 +0000328 bool EnableDS128;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000329 bool DumpCode;
330
331 // Subtarget statically properties set by tablegen
332 bool FP64;
Jan Vesely39aeab42017-12-04 23:07:28 +0000333 bool FMA;
Dmitry Preobrazhenskye3271ae2018-02-05 12:45:43 +0000334 bool MIMG_R128;
Tom Stellardd7e6f132015-04-08 01:09:26 +0000335 bool IsGCN;
Tom Stellardd7e6f132015-04-08 01:09:26 +0000336 bool GCN3Encoding;
Tom Stellardd1f0f022015-04-23 19:33:54 +0000337 bool CIInsts;
Matt Arsenault96b67842018-08-07 07:28:46 +0000338 bool VIInsts;
Matt Arsenault2021f082017-02-18 19:12:26 +0000339 bool GFX9Insts;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000340 bool SGPRInitBug;
Matt Arsenault9d82ee72016-02-27 08:53:55 +0000341 bool HasSMemRealTime;
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000342 bool HasIntClamp;
Matt Arsenault0084adc2018-04-30 19:08:16 +0000343 bool HasFmaMixInsts;
Matt Arsenaultcc88ce32016-10-12 18:00:51 +0000344 bool HasMovrel;
345 bool HasVGPRIndexMode;
Matt Arsenault7b647552016-10-28 21:55:15 +0000346 bool HasScalarStores;
Dmitry Preobrazhensky6bad04e2018-04-02 16:10:25 +0000347 bool HasScalarAtomics;
Sam Kolton3c4933f2017-06-22 06:26:41 +0000348 bool HasSDWAOmod;
349 bool HasSDWAScalar;
350 bool HasSDWASdst;
351 bool HasSDWAMac;
Sam Koltona179d252017-06-27 15:02:23 +0000352 bool HasSDWAOutModsVOPC;
Sam Kolton07dbde22017-01-20 10:01:25 +0000353 bool HasDPP;
Ryan Taylor1f334d02018-08-28 15:07:30 +0000354 bool HasR128A16;
Matt Arsenault0084adc2018-04-30 19:08:16 +0000355 bool HasDLInsts;
Konstantin Zhuravlyov108927b2018-11-05 22:44:19 +0000356 bool EnableSRAMECC;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000357 bool FlatAddressSpace;
Matt Arsenaultacdc7652017-05-10 21:19:05 +0000358 bool FlatInstOffsets;
359 bool FlatGlobalInsts;
360 bool FlatScratchInsts;
Matt Arsenaultc37fe662017-07-20 17:42:47 +0000361 bool AddNoCarryInsts;
Changpeng Fang44dfa1d2018-01-12 21:12:19 +0000362 bool HasUnpackedD16VMem;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000363 bool R600ALUInst;
364 bool CaymanISA;
365 bool CFALUBug;
366 bool HasVertexCache;
367 short TexVTXClauseSize;
Alexander Timofeev18009562016-12-08 17:28:47 +0000368 bool ScalarizeGlobal;
Tom Stellard75aadc22012-12-11 21:25:42 +0000369
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000370 // Dummy feature to use for assembler in tablegen.
371 bool FeatureDisable;
372
Matt Arsenault56684d42016-08-11 17:31:42 +0000373 SelectionDAGTargetInfo TSInfo;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000374private:
Tom Stellard5bfbae52018-07-11 20:59:01 +0000375 SIInstrInfo InstrInfo;
Tom Stellard752ddbd2018-07-11 22:15:15 +0000376 SITargetLowering TLInfo;
Tom Stellard5bfbae52018-07-11 20:59:01 +0000377 SIFrameLowering FrameLowering;
Tom Stellard75aadc22012-12-11 21:25:42 +0000378
379public:
Tom Stellard5bfbae52018-07-11 20:59:01 +0000380 GCNSubtarget(const Triple &TT, StringRef GPU, StringRef FS,
381 const GCNTargetMachine &TM);
382 ~GCNSubtarget() override;
Eugene Zelenko2bc2f332016-12-09 22:06:55 +0000383
Tom Stellard5bfbae52018-07-11 20:59:01 +0000384 GCNSubtarget &initializeSubtargetDependencies(const Triple &TT,
Daniel Sandersa73f1fd2015-06-10 12:11:26 +0000385 StringRef GPU, StringRef FS);
Tom Stellard75aadc22012-12-11 21:25:42 +0000386
Tom Stellard5bfbae52018-07-11 20:59:01 +0000387 const SIInstrInfo *getInstrInfo() const override {
388 return &InstrInfo;
389 }
Tom Stellard000c5af2016-04-14 19:09:28 +0000390
Tom Stellardc5a154d2018-06-28 23:47:12 +0000391 const SIFrameLowering *getFrameLowering() const override {
392 return &FrameLowering;
393 }
394
Tom Stellard5bfbae52018-07-11 20:59:01 +0000395 const SITargetLowering *getTargetLowering() const override {
396 return &TLInfo;
397 }
Tom Stellardc5a154d2018-06-28 23:47:12 +0000398
Tom Stellard5bfbae52018-07-11 20:59:01 +0000399 const SIRegisterInfo *getRegisterInfo() const override {
400 return &InstrInfo.getRegisterInfo();
401 }
Tom Stellardc5a154d2018-06-28 23:47:12 +0000402
403 const CallLowering *getCallLowering() const override {
404 return CallLoweringInfo.get();
405 }
406
407 const InstructionSelector *getInstructionSelector() const override {
408 return InstSelector.get();
409 }
410
411 const LegalizerInfo *getLegalizerInfo() const override {
412 return Legalizer.get();
413 }
414
415 const RegisterBankInfo *getRegBankInfo() const override {
416 return RegBankInfo.get();
Eric Christopherd9134482014-08-04 21:25:23 +0000417 }
Matt Arsenaultd782d052014-06-27 17:57:00 +0000418
Matt Arsenault56684d42016-08-11 17:31:42 +0000419 // Nothing implemented, just prevent crashes on use.
420 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
421 return &TSInfo;
422 }
423
Stanislav Mekhanoshin06d3b412018-09-17 16:04:32 +0000424 const InstrItineraryData *getInstrItineraryData() const override {
425 return &InstrItins;
426 }
427
Craig Topperee7b0f32014-04-30 05:53:27 +0000428 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
Tom Stellard75aadc22012-12-11 21:25:42 +0000429
Matt Arsenaultd782d052014-06-27 17:57:00 +0000430 Generation getGeneration() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000431 return (Generation)Gen;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000432 }
433
Matt Arsenault4eea3f32017-11-13 22:55:05 +0000434 unsigned getWavefrontSizeLog2() const {
435 return Log2_32(WavefrontSize);
436 }
437
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000438 int getLDSBankCount() const {
439 return LDSBankCount;
440 }
441
442 unsigned getMaxPrivateElementSize() const {
443 return MaxPrivateElementSize;
444 }
445
Dmitry Preobrazhenskyff64aa52017-08-16 13:51:56 +0000446 bool hasIntClamp() const {
447 return HasIntClamp;
448 }
449
Jan Veselyd1c9b612017-12-04 22:57:29 +0000450 bool hasFP64() const {
Matt Arsenaultd782d052014-06-27 17:57:00 +0000451 return FP64;
452 }
453
Dmitry Preobrazhenskye3271ae2018-02-05 12:45:43 +0000454 bool hasMIMG_R128() const {
455 return MIMG_R128;
456 }
457
Tom Stellardc5a154d2018-06-28 23:47:12 +0000458 bool hasHWFP64() const {
459 return FP64;
460 }
461
Matt Arsenaultb035a572015-01-29 19:34:25 +0000462 bool hasFastFMAF32() const {
463 return FastFMAF32;
464 }
465
Matt Arsenaulte83690c2016-01-18 21:13:50 +0000466 bool hasHalfRate64Ops() const {
467 return HalfRate64Ops;
468 }
469
Matt Arsenault88701812016-06-09 23:42:48 +0000470 bool hasAddr64() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000471 return (getGeneration() < AMDGPUSubtarget::VOLCANIC_ISLANDS);
Matt Arsenault88701812016-06-09 23:42:48 +0000472 }
473
Matt Arsenaultfae02982014-03-17 18:58:11 +0000474 bool hasBFE() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000475 return true;
Matt Arsenaultfae02982014-03-17 18:58:11 +0000476 }
477
Matt Arsenault6e439652014-06-10 19:00:20 +0000478 bool hasBFI() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000479 return true;
Matt Arsenault6e439652014-06-10 19:00:20 +0000480 }
481
Matt Arsenaultfae02982014-03-17 18:58:11 +0000482 bool hasBFM() const {
483 return hasBFE();
484 }
485
Matt Arsenault60425062014-06-10 19:18:28 +0000486 bool hasBCNT(unsigned Size) const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000487 return true;
Tom Stellard50122a52014-04-07 19:45:41 +0000488 }
489
Jan Vesely6ddb8dd2014-07-15 15:51:09 +0000490 bool hasFFBL() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000491 return true;
Jan Vesely6ddb8dd2014-07-15 15:51:09 +0000492 }
493
494 bool hasFFBH() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000495 return true;
Jan Vesely6ddb8dd2014-07-15 15:51:09 +0000496 }
497
Matt Arsenault10268f92017-02-27 22:40:39 +0000498 bool hasMed3_16() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000499 return getGeneration() >= AMDGPUSubtarget::GFX9;
Matt Arsenault10268f92017-02-27 22:40:39 +0000500 }
501
Matt Arsenaultee324ff2017-05-17 19:25:06 +0000502 bool hasMin3Max3_16() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000503 return getGeneration() >= AMDGPUSubtarget::GFX9;
Matt Arsenaultd7e23032017-09-07 18:05:07 +0000504 }
505
Matt Arsenault0084adc2018-04-30 19:08:16 +0000506 bool hasFmaMixInsts() const {
507 return HasFmaMixInsts;
508 }
509
Jan Vesely808fff52015-04-30 17:15:56 +0000510 bool hasCARRY() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000511 return true;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000512 }
513
Jan Vesely39aeab42017-12-04 23:07:28 +0000514 bool hasFMA() const {
515 return FMA;
516 }
517
Stanislav Mekhanoshin79080ec2018-10-29 17:26:01 +0000518 bool hasSwap() const {
519 return GFX9Insts;
520 }
521
Wei Ding205bfdb2017-02-10 02:15:29 +0000522 TrapHandlerAbi getTrapHandlerAbi() const {
523 return isAmdHsaOS() ? TrapHandlerAbiHsa : TrapHandlerAbiNone;
524 }
525
Matt Arsenault45b98182017-11-15 00:45:43 +0000526 bool enableHugePrivateBuffer() const {
527 return EnableHugePrivateBuffer;
528 }
529
Matt Arsenault706f9302015-07-06 16:01:58 +0000530 bool unsafeDSOffsetFoldingEnabled() const {
531 return EnableUnsafeDSOffsetFolding;
532 }
533
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000534 bool dumpCode() const {
535 return DumpCode;
Matt Arsenaultd782d052014-06-27 17:57:00 +0000536 }
537
Matt Arsenault8a028bf2016-05-16 21:19:59 +0000538 /// Return the amount of LDS that can be used that will not restrict the
539 /// occupancy lower than WaveCount.
Stanislav Mekhanoshin2b913b12017-02-01 22:59:50 +0000540 unsigned getMaxLocalMemSizeWithWaveCount(unsigned WaveCount,
541 const Function &) const;
Matt Arsenault8a028bf2016-05-16 21:19:59 +0000542
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000543 bool hasFP16Denormals() const {
Matt Arsenaulta6867fd2017-01-23 22:31:03 +0000544 return FP64FP16Denormals;
Konstantin Zhuravlyovf86e4b72016-11-13 07:01:11 +0000545 }
Matt Arsenault8a028bf2016-05-16 21:19:59 +0000546
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000547 bool hasFP64Denormals() const {
Matt Arsenaulta6867fd2017-01-23 22:31:03 +0000548 return FP64FP16Denormals;
Matt Arsenault24ee0782016-02-12 02:40:47 +0000549 }
550
Stanislav Mekhanoshindc2890a2017-07-13 23:59:15 +0000551 bool supportsMinMaxDenormModes() const {
552 return getGeneration() >= AMDGPUSubtarget::GFX9;
553 }
554
Matt Arsenault2fdf2a12017-02-21 23:35:48 +0000555 bool enableDX10Clamp() const {
556 return DX10Clamp;
557 }
558
559 bool enableIEEEBit(const MachineFunction &MF) const {
Matthias Braunf1caa282017-12-15 22:22:58 +0000560 return AMDGPU::isCompute(MF.getFunction().getCallingConv());
Matt Arsenault2fdf2a12017-02-21 23:35:48 +0000561 }
562
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000563 bool useFlatForGlobal() const {
564 return FlatForGlobal;
Tom Stellardec87f842015-05-25 16:15:54 +0000565 }
566
Farhana Aleena7cb3112018-03-09 17:41:39 +0000567 /// \returns If target supports ds_read/write_b128 and user enables generation
568 /// of ds_read/write_b128.
Marek Olsaka9a58fa2018-04-10 22:48:23 +0000569 bool useDS128() const {
570 return CIInsts && EnableDS128;
Farhana Aleena7cb3112018-03-09 17:41:39 +0000571 }
572
Matt Arsenaultcaf0ed42017-11-30 00:52:40 +0000573 /// \returns If MUBUF instructions always perform range checking, even for
574 /// buffer resources used for private memory access.
575 bool privateMemoryResourceIsRangeChecked() const {
576 return getGeneration() < AMDGPUSubtarget::GFX9;
577 }
578
Konstantin Zhuravlyovbe6c0ca2017-06-02 17:40:26 +0000579 bool hasAutoWaitcntBeforeBarrier() const {
580 return AutoWaitcntBeforeBarrier;
581 }
582
Konstantin Zhuravlyoveda425e2017-10-14 15:59:07 +0000583 bool hasCodeObjectV3() const {
Konstantin Zhuravlyova25e0522018-11-15 02:32:43 +0000584 // FIXME: Need to add code object v3 support for mesa and pal.
585 return isAmdHsaOS() ? CodeObjectV3 : false;
Konstantin Zhuravlyoveda425e2017-10-14 15:59:07 +0000586 }
587
Matt Arsenault7f681ac2016-07-01 23:03:44 +0000588 bool hasUnalignedBufferAccess() const {
589 return UnalignedBufferAccess;
590 }
591
Tom Stellard64a9d082016-10-14 18:10:39 +0000592 bool hasUnalignedScratchAccess() const {
593 return UnalignedScratchAccess;
594 }
595
Matt Arsenaulte823d922017-02-18 18:29:53 +0000596 bool hasApertureRegs() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000597 return HasApertureRegs;
Matt Arsenaulte823d922017-02-18 18:29:53 +0000598 }
599
Wei Ding205bfdb2017-02-10 02:15:29 +0000600 bool isTrapHandlerEnabled() const {
601 return TrapHandler;
602 }
603
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000604 bool isXNACKEnabled() const {
605 return EnableXNACK;
606 }
Tom Stellardb8fd6ef2014-12-02 22:00:07 +0000607
Matt Arsenaultb6491cc2017-01-31 01:20:54 +0000608 bool hasFlatAddressSpace() const {
609 return FlatAddressSpace;
610 }
611
Matt Arsenaultacdc7652017-05-10 21:19:05 +0000612 bool hasFlatInstOffsets() const {
613 return FlatInstOffsets;
614 }
615
616 bool hasFlatGlobalInsts() const {
617 return FlatGlobalInsts;
618 }
619
620 bool hasFlatScratchInsts() const {
621 return FlatScratchInsts;
622 }
623
Mark Searlesf0b93f12018-06-04 16:51:59 +0000624 bool hasFlatLgkmVMemCountInOrder() const {
625 return getGeneration() > GFX9;
626 }
627
Matt Arsenaulted6e8f02017-09-01 18:36:06 +0000628 bool hasD16LoadStore() const {
629 return getGeneration() >= GFX9;
630 }
631
Matt Arsenault3f71c0e2017-11-29 00:55:57 +0000632 /// Return if most LDS instructions have an m0 use that require m0 to be
633 /// iniitalized.
634 bool ldsRequiresM0Init() const {
635 return getGeneration() < GFX9;
636 }
637
Matt Arsenaultc37fe662017-07-20 17:42:47 +0000638 bool hasAddNoCarry() const {
639 return AddNoCarryInsts;
640 }
641
Changpeng Fang44dfa1d2018-01-12 21:12:19 +0000642 bool hasUnpackedD16VMem() const {
643 return HasUnpackedD16VMem;
644 }
645
Tom Stellard2f3f9852017-01-25 01:25:13 +0000646 // Covers VS/PS/CS graphics shaders
Matt Arsenaultceafc552018-05-29 17:42:50 +0000647 bool isMesaGfxShader(const Function &F) const {
648 return isMesa3DOS() && AMDGPU::isShader(F.getCallingConv());
Tom Stellard2f3f9852017-01-25 01:25:13 +0000649 }
650
Matt Arsenault4f6318f2017-11-06 17:04:37 +0000651 bool hasMad64_32() const {
652 return getGeneration() >= SEA_ISLANDS;
653 }
654
Sam Kolton3c4933f2017-06-22 06:26:41 +0000655 bool hasSDWAOmod() const {
656 return HasSDWAOmod;
657 }
658
659 bool hasSDWAScalar() const {
660 return HasSDWAScalar;
661 }
662
663 bool hasSDWASdst() const {
664 return HasSDWASdst;
665 }
666
667 bool hasSDWAMac() const {
668 return HasSDWAMac;
669 }
670
Sam Koltona179d252017-06-27 15:02:23 +0000671 bool hasSDWAOutModsVOPC() const {
672 return HasSDWAOutModsVOPC;
Sam Kolton3c4933f2017-06-22 06:26:41 +0000673 }
674
Mark Searles2a19af62018-04-26 16:11:19 +0000675 bool vmemWriteNeedsExpWaitcnt() const {
676 return getGeneration() < SEA_ISLANDS;
677 }
678
Matt Arsenault0084adc2018-04-30 19:08:16 +0000679 bool hasDLInsts() const {
680 return HasDLInsts;
681 }
682
Konstantin Zhuravlyov108927b2018-11-05 22:44:19 +0000683 bool isSRAMECCEnabled() const {
684 return EnableSRAMECC;
Konstantin Zhuravlyovc2c2eb72018-05-04 20:06:57 +0000685 }
686
Matt Arsenault869fec22017-04-17 19:48:24 +0000687 // Scratch is allocated in 256 dword per wave blocks for the entire
688 // wavefront. When viewed from the perspecive of an arbitrary workitem, this
689 // is 4-byte aligned.
Matt Arsenaultffb132e2018-03-29 20:22:04 +0000690 //
691 // Only 4-byte alignment is really needed to access anything. Transformations
692 // on the pointer value itself may rely on the alignment / known low bits of
693 // the pointer. Set this to something above the minimum to avoid needing
694 // dynamic realignment in common cases.
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000695 unsigned getStackAlignment() const {
Matt Arsenaultffb132e2018-03-29 20:22:04 +0000696 return 16;
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000697 }
Tom Stellard347ac792015-06-26 21:15:07 +0000698
Craig Topper5656db42014-04-29 07:57:24 +0000699 bool enableMachineScheduler() const override {
Tom Stellard83f0bce2015-01-29 16:55:25 +0000700 return true;
Andrew Trick978674b2013-09-20 05:14:41 +0000701 }
702
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000703 bool enableSubRegLiveness() const override {
704 return true;
705 }
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000706
Tom Stellardc5a154d2018-06-28 23:47:12 +0000707 void setScalarizeGlobalBehavior(bool b) { ScalarizeGlobal = b; }
708 bool getScalarizeGlobalBehavior() const { return ScalarizeGlobal; }
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000709
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000710 /// \returns Number of execution units per compute unit supported by the
711 /// subtarget.
712 unsigned getEUsPerCU() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000713 return AMDGPU::IsaInfo::getEUsPerCU(this);
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000714 }
715
716 /// \returns Maximum number of waves per compute unit supported by the
717 /// subtarget without any kind of limitation.
718 unsigned getMaxWavesPerCU() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000719 return AMDGPU::IsaInfo::getMaxWavesPerCU(this);
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000720 }
721
722 /// \returns Maximum number of waves per compute unit supported by the
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000723 /// subtarget and limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000724 unsigned getMaxWavesPerCU(unsigned FlatWorkGroupSize) const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000725 return AMDGPU::IsaInfo::getMaxWavesPerCU(this, FlatWorkGroupSize);
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000726 }
727
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000728 /// \returns Maximum number of waves per execution unit supported by the
729 /// subtarget without any kind of limitation.
730 unsigned getMaxWavesPerEU() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000731 return AMDGPU::IsaInfo::getMaxWavesPerEU();
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000732 }
733
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000734 /// \returns Number of waves per work group supported by the subtarget and
735 /// limited by given \p FlatWorkGroupSize.
Konstantin Zhuravlyov1d650262016-09-06 20:22:28 +0000736 unsigned getWavesPerWorkGroup(unsigned FlatWorkGroupSize) const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000737 return AMDGPU::IsaInfo::getWavesPerWorkGroup(this, FlatWorkGroupSize);
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000738 }
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000739
Tom Stellardc5a154d2018-06-28 23:47:12 +0000740 // static wrappers
741 static bool hasHalfRate64Ops(const TargetSubtargetInfo &STI);
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000742
Matt Arsenault9f5e0ef2017-01-25 04:25:02 +0000743 // XXX - Why is this here if it isn't in the default pass set?
744 bool enableEarlyIfConversion() const override {
745 return true;
746 }
747
Tom Stellard83f0bce2015-01-29 16:55:25 +0000748 void overrideSchedPolicy(MachineSchedPolicy &Policy,
Tom Stellard83f0bce2015-01-29 16:55:25 +0000749 unsigned NumRegionInstrs) const override;
750
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000751 unsigned getMaxNumUserSGPRs() const {
752 return 16;
753 }
754
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000755 bool hasSMemRealTime() const {
756 return HasSMemRealTime;
757 }
758
Matt Arsenaultcc88ce32016-10-12 18:00:51 +0000759 bool hasMovrel() const {
760 return HasMovrel;
761 }
762
763 bool hasVGPRIndexMode() const {
764 return HasVGPRIndexMode;
765 }
766
Marek Olsake22fdb92017-03-21 17:00:32 +0000767 bool useVGPRIndexMode(bool UserEnable) const {
768 return !hasMovrel() || (UserEnable && hasVGPRIndexMode());
769 }
770
Matt Arsenault7b1dc2c2016-09-17 02:02:19 +0000771 bool hasScalarCompareEq64() const {
772 return getGeneration() >= VOLCANIC_ISLANDS;
773 }
774
Matt Arsenault7b647552016-10-28 21:55:15 +0000775 bool hasScalarStores() const {
776 return HasScalarStores;
777 }
778
Dmitry Preobrazhensky6bad04e2018-04-02 16:10:25 +0000779 bool hasScalarAtomics() const {
780 return HasScalarAtomics;
781 }
782
Matt Arsenaultc88ba362016-10-29 04:05:06 +0000783
Sam Kolton07dbde22017-01-20 10:01:25 +0000784 bool hasDPP() const {
785 return HasDPP;
786 }
787
Ryan Taylor1f334d02018-08-28 15:07:30 +0000788 bool hasR128A16() const {
789 return HasR128A16;
790 }
791
Tom Stellardde008d32016-01-21 04:28:34 +0000792 bool enableSIScheduler() const {
793 return EnableSIScheduler;
794 }
795
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +0000796 bool debuggerSupported() const {
Konstantin Zhuravlyove004b3d2018-06-21 20:28:19 +0000797 return debuggerInsertNops() && debuggerEmitPrologue();
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +0000798 }
799
Konstantin Zhuravlyov8c273ad2016-04-18 16:28:23 +0000800 bool debuggerInsertNops() const {
801 return DebuggerInsertNops;
802 }
803
Konstantin Zhuravlyovf2f3d142016-06-25 03:11:28 +0000804 bool debuggerEmitPrologue() const {
805 return DebuggerEmitPrologue;
806 }
807
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000808 bool loadStoreOptEnabled() const {
809 return EnableLoadStoreOpt;
Nicolai Haehnle5b504972016-01-04 23:35:53 +0000810 }
811
Matt Arsenault43e92fe2016-06-24 06:30:11 +0000812 bool hasSGPRInitBug() const {
813 return SGPRInitBug;
Matt Arsenault41003af2015-11-30 21:16:07 +0000814 }
Tom Stellard0d23ebe2016-08-29 19:42:52 +0000815
Tom Stellardb133fbb2016-10-27 23:05:31 +0000816 bool has12DWordStoreHazard() const {
817 return getGeneration() != AMDGPUSubtarget::SOUTHERN_ISLANDS;
818 }
819
Matt Arsenaulte823d922017-02-18 18:29:53 +0000820 bool hasSMovFedHazard() const {
821 return getGeneration() >= AMDGPUSubtarget::GFX9;
822 }
823
Matt Arsenaulta41351e2017-11-17 21:35:32 +0000824 bool hasReadM0MovRelInterpHazard() const {
Matt Arsenaulte823d922017-02-18 18:29:53 +0000825 return getGeneration() >= AMDGPUSubtarget::GFX9;
826 }
827
Matt Arsenaulta41351e2017-11-17 21:35:32 +0000828 bool hasReadM0SendMsgHazard() const {
829 return getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS;
830 }
831
Tom Stellardc5a154d2018-06-28 23:47:12 +0000832 /// Return the maximum number of waves per SIMD for kernels using \p SGPRs
833 /// SGPRs
Tom Stellard0d23ebe2016-08-29 19:42:52 +0000834 unsigned getOccupancyWithNumSGPRs(unsigned SGPRs) const;
835
Tom Stellardc5a154d2018-06-28 23:47:12 +0000836 /// Return the maximum number of waves per SIMD for kernels using \p VGPRs
837 /// VGPRs
Tom Stellard0d23ebe2016-08-29 19:42:52 +0000838 unsigned getOccupancyWithNumVGPRs(unsigned VGPRs) const;
Konstantin Zhuravlyovd7bdf242016-09-30 16:50:36 +0000839
Matt Arsenaulte823d922017-02-18 18:29:53 +0000840 /// \returns true if the flat_scratch register should be initialized with the
841 /// pointer to the wave's scratch memory rather than a size and offset.
842 bool flatScratchIsPointer() const {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000843 return getGeneration() >= AMDGPUSubtarget::GFX9;
Konstantin Zhuravlyovd7bdf242016-09-30 16:50:36 +0000844 }
Matt Arsenault4eae3012016-10-28 20:31:47 +0000845
Tim Renouf832f90f2018-02-26 14:46:43 +0000846 /// \returns true if the machine has merged shaders in which s0-s7 are
847 /// reserved by the hardware and user SGPRs start at s8
848 bool hasMergedShaders() const {
849 return getGeneration() >= GFX9;
850 }
851
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000852 /// \returns SGPR allocation granularity supported by the subtarget.
853 unsigned getSGPRAllocGranule() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000854 return AMDGPU::IsaInfo::getSGPRAllocGranule(this);
Konstantin Zhuravlyove22fbcb2017-02-08 13:18:40 +0000855 }
856
857 /// \returns SGPR encoding granularity supported by the subtarget.
858 unsigned getSGPREncodingGranule() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000859 return AMDGPU::IsaInfo::getSGPREncodingGranule(this);
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000860 }
861
862 /// \returns Total number of SGPRs supported by the subtarget.
863 unsigned getTotalNumSGPRs() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000864 return AMDGPU::IsaInfo::getTotalNumSGPRs(this);
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000865 }
866
867 /// \returns Addressable number of SGPRs supported by the subtarget.
868 unsigned getAddressableNumSGPRs() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000869 return AMDGPU::IsaInfo::getAddressableNumSGPRs(this);
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000870 }
871
872 /// \returns Minimum number of SGPRs that meets the given number of waves per
873 /// execution unit requirement supported by the subtarget.
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000874 unsigned getMinNumSGPRs(unsigned WavesPerEU) const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000875 return AMDGPU::IsaInfo::getMinNumSGPRs(this, WavesPerEU);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000876 }
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000877
878 /// \returns Maximum number of SGPRs that meets the given number of waves per
879 /// execution unit requirement supported by the subtarget.
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000880 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000881 return AMDGPU::IsaInfo::getMaxNumSGPRs(this, WavesPerEU, Addressable);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000882 }
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000883
884 /// \returns Reserved number of SGPRs for given function \p MF.
885 unsigned getReservedNumSGPRs(const MachineFunction &MF) const;
886
887 /// \returns Maximum number of SGPRs that meets number of waves per execution
888 /// unit requirement for function \p MF, or number of SGPRs explicitly
889 /// requested using "amdgpu-num-sgpr" attribute attached to function \p MF.
890 ///
891 /// \returns Value that meets number of waves per execution unit requirement
892 /// if explicitly requested value cannot be converted to integer, violates
893 /// subtarget's specifications, or does not meet number of waves per execution
894 /// unit requirement.
895 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
896
897 /// \returns VGPR allocation granularity supported by the subtarget.
898 unsigned getVGPRAllocGranule() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000899 return AMDGPU::IsaInfo::getVGPRAllocGranule(this);
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000900 }
901
Konstantin Zhuravlyove22fbcb2017-02-08 13:18:40 +0000902 /// \returns VGPR encoding granularity supported by the subtarget.
903 unsigned getVGPREncodingGranule() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000904 return AMDGPU::IsaInfo::getVGPREncodingGranule(this);
Konstantin Zhuravlyove22fbcb2017-02-08 13:18:40 +0000905 }
906
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000907 /// \returns Total number of VGPRs supported by the subtarget.
908 unsigned getTotalNumVGPRs() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000909 return AMDGPU::IsaInfo::getTotalNumVGPRs(this);
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000910 }
911
912 /// \returns Addressable number of VGPRs supported by the subtarget.
913 unsigned getAddressableNumVGPRs() const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000914 return AMDGPU::IsaInfo::getAddressableNumVGPRs(this);
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000915 }
916
917 /// \returns Minimum number of VGPRs that meets given number of waves per
918 /// execution unit requirement supported by the subtarget.
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000919 unsigned getMinNumVGPRs(unsigned WavesPerEU) const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000920 return AMDGPU::IsaInfo::getMinNumVGPRs(this, WavesPerEU);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000921 }
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000922
923 /// \returns Maximum number of VGPRs that meets given number of waves per
924 /// execution unit requirement supported by the subtarget.
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000925 unsigned getMaxNumVGPRs(unsigned WavesPerEU) const {
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000926 return AMDGPU::IsaInfo::getMaxNumVGPRs(this, WavesPerEU);
Konstantin Zhuravlyov9f89ede2017-02-08 14:05:23 +0000927 }
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000928
Konstantin Zhuravlyove03b1d72017-02-08 13:02:33 +0000929 /// \returns Maximum number of VGPRs that meets number of waves per execution
930 /// unit requirement for function \p MF, or number of VGPRs explicitly
931 /// requested using "amdgpu-num-vgpr" attribute attached to function \p MF.
932 ///
933 /// \returns Value that meets number of waves per execution unit requirement
934 /// if explicitly requested value cannot be converted to integer, violates
935 /// subtarget's specifications, or does not meet number of waves per execution
936 /// unit requirement.
937 unsigned getMaxNumVGPRs(const MachineFunction &MF) const;
Stanislav Mekhanoshind4ae4702017-09-19 20:54:38 +0000938
939 void getPostRAMutations(
940 std::vector<std::unique_ptr<ScheduleDAGMutation>> &Mutations)
941 const override;
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +0000942
943 /// \returns Maximum number of work groups per compute unit supported by the
944 /// subtarget and limited by given \p FlatWorkGroupSize.
945 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
946 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);
947 }
948
949 /// \returns Minimum flat work group size supported by the subtarget.
950 unsigned getMinFlatWorkGroupSize() const override {
951 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(this);
952 }
953
954 /// \returns Maximum flat work group size supported by the subtarget.
955 unsigned getMaxFlatWorkGroupSize() const override {
956 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(this);
957 }
958
959 /// \returns Maximum number of waves per execution unit supported by the
960 /// subtarget and limited by given \p FlatWorkGroupSize.
961 unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const override {
962 return AMDGPU::IsaInfo::getMaxWavesPerEU(this, FlatWorkGroupSize);
963 }
964
965 /// \returns Minimum number of waves per execution unit supported by the
966 /// subtarget.
967 unsigned getMinWavesPerEU() const override {
968 return AMDGPU::IsaInfo::getMinWavesPerEU(this);
969 }
Tom Stellard75aadc22012-12-11 21:25:42 +0000970};
971
Tom Stellardc5a154d2018-06-28 23:47:12 +0000972class R600Subtarget final : public R600GenSubtargetInfo,
Tom Stellard5bfbae52018-07-11 20:59:01 +0000973 public AMDGPUSubtarget {
Tom Stellardc5a154d2018-06-28 23:47:12 +0000974private:
975 R600InstrInfo InstrInfo;
976 R600FrameLowering FrameLowering;
977 bool FMA;
978 bool CaymanISA;
979 bool CFALUBug;
980 bool DX10Clamp;
981 bool HasVertexCache;
982 bool R600ALUInst;
983 bool FP64;
984 short TexVTXClauseSize;
985 Generation Gen;
986 R600TargetLowering TLInfo;
987 InstrItineraryData InstrItins;
988 SelectionDAGTargetInfo TSInfo;
Tom Stellardc5a154d2018-06-28 23:47:12 +0000989
990public:
991 R600Subtarget(const Triple &TT, StringRef CPU, StringRef FS,
992 const TargetMachine &TM);
993
994 const R600InstrInfo *getInstrInfo() const override { return &InstrInfo; }
995
996 const R600FrameLowering *getFrameLowering() const override {
997 return &FrameLowering;
998 }
999
1000 const R600TargetLowering *getTargetLowering() const override {
1001 return &TLInfo;
1002 }
1003
1004 const R600RegisterInfo *getRegisterInfo() const override {
1005 return &InstrInfo.getRegisterInfo();
1006 }
1007
1008 const InstrItineraryData *getInstrItineraryData() const override {
1009 return &InstrItins;
1010 }
1011
1012 // Nothing implemented, just prevent crashes on use.
1013 const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
1014 return &TSInfo;
1015 }
1016
1017 void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
1018
1019 Generation getGeneration() const {
1020 return Gen;
1021 }
1022
1023 unsigned getStackAlignment() const {
1024 return 4;
1025 }
1026
1027 R600Subtarget &initializeSubtargetDependencies(const Triple &TT,
1028 StringRef GPU, StringRef FS);
1029
1030 bool hasBFE() const {
1031 return (getGeneration() >= EVERGREEN);
1032 }
1033
1034 bool hasBFI() const {
1035 return (getGeneration() >= EVERGREEN);
1036 }
1037
1038 bool hasBCNT(unsigned Size) const {
1039 if (Size == 32)
1040 return (getGeneration() >= EVERGREEN);
1041
1042 return false;
1043 }
1044
1045 bool hasBORROW() const {
1046 return (getGeneration() >= EVERGREEN);
1047 }
1048
1049 bool hasCARRY() const {
1050 return (getGeneration() >= EVERGREEN);
1051 }
1052
1053 bool hasCaymanISA() const {
1054 return CaymanISA;
1055 }
1056
1057 bool hasFFBL() const {
1058 return (getGeneration() >= EVERGREEN);
1059 }
1060
1061 bool hasFFBH() const {
1062 return (getGeneration() >= EVERGREEN);
1063 }
1064
1065 bool hasFMA() const { return FMA; }
1066
Tom Stellardc5a154d2018-06-28 23:47:12 +00001067 bool hasCFAluBug() const { return CFALUBug; }
1068
1069 bool hasVertexCache() const { return HasVertexCache; }
1070
1071 short getTexVTXClauseSize() const { return TexVTXClauseSize; }
1072
Tom Stellardc5a154d2018-06-28 23:47:12 +00001073 bool enableMachineScheduler() const override {
1074 return true;
1075 }
1076
1077 bool enableSubRegLiveness() const override {
1078 return true;
1079 }
Konstantin Zhuravlyov71e43ee2018-09-12 18:50:47 +00001080
1081 /// \returns Maximum number of work groups per compute unit supported by the
1082 /// subtarget and limited by given \p FlatWorkGroupSize.
1083 unsigned getMaxWorkGroupsPerCU(unsigned FlatWorkGroupSize) const override {
1084 return AMDGPU::IsaInfo::getMaxWorkGroupsPerCU(this, FlatWorkGroupSize);
1085 }
1086
1087 /// \returns Minimum flat work group size supported by the subtarget.
1088 unsigned getMinFlatWorkGroupSize() const override {
1089 return AMDGPU::IsaInfo::getMinFlatWorkGroupSize(this);
1090 }
1091
1092 /// \returns Maximum flat work group size supported by the subtarget.
1093 unsigned getMaxFlatWorkGroupSize() const override {
1094 return AMDGPU::IsaInfo::getMaxFlatWorkGroupSize(this);
1095 }
1096
1097 /// \returns Maximum number of waves per execution unit supported by the
1098 /// subtarget and limited by given \p FlatWorkGroupSize.
1099 unsigned getMaxWavesPerEU(unsigned FlatWorkGroupSize) const override {
1100 return AMDGPU::IsaInfo::getMaxWavesPerEU(this, FlatWorkGroupSize);
1101 }
1102
1103 /// \returns Minimum number of waves per execution unit supported by the
1104 /// subtarget.
1105 unsigned getMinWavesPerEU() const override {
1106 return AMDGPU::IsaInfo::getMinWavesPerEU(this);
1107 }
Tom Stellardc5a154d2018-06-28 23:47:12 +00001108};
1109
Eugene Zelenko2bc2f332016-12-09 22:06:55 +00001110} // end namespace llvm
Tom Stellard75aadc22012-12-11 21:25:42 +00001111
Eugene Zelenko2bc2f332016-12-09 22:06:55 +00001112#endif // LLVM_LIB_TARGET_AMDGPU_AMDGPUSUBTARGET_H