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gerrit-public.fairphone.software / toolchain / llvm-project / d1f0f0268c349cf52e5bcf01fa1a672bcece2add / . / llvm / lib / Target / R600 / AMDGPU.td
blob: 2e0e30a0fbca05b06dd420e8abfaa6ad338f916e [file] [log] [blame]
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]1//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//==-----------------------------------------------------------------------===//
9
Tom Stellardbc5b5372014-06-13 16:38:59 +0000[diff] [blame]10include "llvm/Target/Target.td"
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]11
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]12//===----------------------------------------------------------------------===//
13// Subtarget Features
14//===----------------------------------------------------------------------===//
15
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]16// Debugging Features
17
18def FeatureDumpCode : SubtargetFeature <"DumpCode",
19 "DumpCode",
20 "true",
21 "Dump MachineInstrs in the CodeEmitter">;
22
Tom Stellard66df8a22013-11-18 19:43:44 +0000[diff] [blame]23def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
Tom Stellarded0ceec2013-10-10 17:11:12 +0000[diff] [blame]24 "EnableIRStructurizer",
Tom Stellard66df8a22013-11-18 19:43:44 +0000[diff] [blame]25 "false",
26 "Disable IR Structurizer">;
Tom Stellarded0ceec2013-10-10 17:11:12 +0000[diff] [blame]27
Matt Arsenaultd9a23ab2014-07-13 02:08:26 +0000[diff] [blame]28def FeaturePromoteAlloca : SubtargetFeature <"promote-alloca",
29 "EnablePromoteAlloca",
30 "true",
31 "Enable promote alloca pass">;
32
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]33// Target features
34
Tom Stellard783893a2013-11-18 19:43:33 +0000[diff] [blame]35def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
36 "EnableIfCvt",
37 "false",
38 "Disable the if conversion pass">;
39
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]40def FeatureFP64 : SubtargetFeature<"fp64",
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]41 "FP64",
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]42 "true",
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]43 "Enable double precision operations">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]44
Matt Arsenaultf171cf22014-07-14 23:40:49 +0000[diff] [blame]45def FeatureFP64Denormals : SubtargetFeature<"fp64-denormals",
46 "FP64Denormals",
47 "true",
48 "Enable double precision denormal handling",
49 [FeatureFP64]>;
50
Matt Arsenaultb035a572015-01-29 19:34:25 +0000[diff] [blame]51def FeatureFastFMAF32 : SubtargetFeature<"fast-fmaf",
52 "FastFMAF32",
53 "true",
54 "Assuming f32 fma is at least as fast as mul + add",
55 []>;
56
Matt Arsenaultf171cf22014-07-14 23:40:49 +0000[diff] [blame]57// Some instructions do not support denormals despite this flag. Using
58// fp32 denormals also causes instructions to run at the double
59// precision rate for the device.
60def FeatureFP32Denormals : SubtargetFeature<"fp32-denormals",
61 "FP32Denormals",
62 "true",
63 "Enable single precision denormal handling">;
64
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]65def Feature64BitPtr : SubtargetFeature<"64BitPtr",
66 "Is64bit",
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]67 "true",
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]68 "Specify if 64-bit addressing should be used">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]69
70def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
71 "R600ALUInst",
72 "false",
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]73 "Older version of ALU instructions encoding">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]74
75def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
76 "HasVertexCache",
77 "true",
Matt Arsenaultf5e29972014-06-20 06:50:05 +0000[diff] [blame]78 "Specify use of dedicated vertex cache">;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]79
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]80def FeatureCaymanISA : SubtargetFeature<"caymanISA",
81 "CaymanISA",
82 "true",
83 "Use Cayman ISA">;
84
Tom Stellard348273d2014-01-23 16:18:02 +0000[diff] [blame]85def FeatureCFALUBug : SubtargetFeature<"cfalubug",
86 "CFALUBug",
87 "true",
88 "GPU has CF_ALU bug">;
89
Matt Arsenault41033282014-10-10 22:01:59 +0000[diff] [blame]90// XXX - This should probably be removed once enabled by default
91def FeatureEnableLoadStoreOpt : SubtargetFeature <"load-store-opt",
92 "EnableLoadStoreOpt",
93 "true",
94 "Enable SI load/store optimizer pass">;
95
Matt Arsenault3f981402014-09-15 15:41:53 +0000[diff] [blame]96def FeatureFlatAddressSpace : SubtargetFeature<"flat-address-space",
97 "FlatAddressSpace",
98 "true",
99 "Support flat address space">;
100
Tom Stellarde99fb652015-01-20 19:33:04 +0000[diff] [blame]101def FeatureVGPRSpilling : SubtargetFeature<"vgpr-spilling",
102 "EnableVGPRSpilling",
103 "true",
104 "Enable spilling of VGPRs to scratch memory">;
105
Marek Olsak4d00dd22015-03-09 15:48:09 +0000[diff] [blame]106def FeatureSGPRInitBug : SubtargetFeature<"sgpr-init-bug",
107 "SGPRInitBug",
108 "true",
109 "VI SGPR initilization bug requiring a fixed SGPR allocation size">;
110
Tom Stellard3498e4f2013-06-07 20:28:55 +0000[diff] [blame]111class SubtargetFeatureFetchLimit <string Value> :
112 SubtargetFeature <"fetch"#Value,
113 "TexVTXClauseSize",
114 Value,
115 "Limit the maximum number of fetches in a clause to "#Value>;
Tom Stellard99792772013-06-07 20:28:49 +0000[diff] [blame]116
Tom Stellard3498e4f2013-06-07 20:28:55 +0000[diff] [blame]117def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
118def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
119
Tom Stellard8c347b02014-01-22 21:55:40 +0000[diff] [blame]120class SubtargetFeatureWavefrontSize <int Value> : SubtargetFeature<
121 "wavefrontsize"#Value,
122 "WavefrontSize",
123 !cast<string>(Value),
124 "The number of threads per wavefront">;
125
126def FeatureWavefrontSize16 : SubtargetFeatureWavefrontSize<16>;
127def FeatureWavefrontSize32 : SubtargetFeatureWavefrontSize<32>;
128def FeatureWavefrontSize64 : SubtargetFeatureWavefrontSize<64>;
129
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]130class SubtargetFeatureLocalMemorySize <int Value> : SubtargetFeature<
131 "localmemorysize"#Value,
132 "LocalMemorySize",
133 !cast<string>(Value),
134 "The size of local memory in bytes">;
135
Tom Stellardd7e6f132015-04-08 01:09:26 +0000[diff] [blame]136def FeatureGCN : SubtargetFeature<"gcn",
137 "IsGCN",
138 "true",
139 "GCN or newer GPU">;
140
141def FeatureGCN1Encoding : SubtargetFeature<"gcn1-encoding",
142 "GCN1Encoding",
143 "true",
144 "Encoding format for SI and CI">;
145
146def FeatureGCN3Encoding : SubtargetFeature<"gcn3-encoding",
147 "GCN3Encoding",
148 "true",
149 "Encoding format for VI">;
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame^]150
151def FeatureCIInsts : SubtargetFeature<"ci-insts",
152 "CIInsts",
153 "true",
154 "Additional intstructions for CI+">;
155
156// Dummy feature used to disable assembler instructions.
157def FeatureDisable : SubtargetFeature<"",
158 "FeatureDisable","true",
159 "Dummy feature to disable assembler"
160 " instructions">;
161
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]162class SubtargetFeatureGeneration <string Value,
163 list<SubtargetFeature> Implies> :
164 SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
165 Value#" GPU generation", Implies>;
166
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]167def FeatureLocalMemorySize0 : SubtargetFeatureLocalMemorySize<0>;
168def FeatureLocalMemorySize32768 : SubtargetFeatureLocalMemorySize<32768>;
169def FeatureLocalMemorySize65536 : SubtargetFeatureLocalMemorySize<65536>;
170
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]171def FeatureR600 : SubtargetFeatureGeneration<"R600",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]172 [FeatureR600ALUInst, FeatureFetchLimit8, FeatureLocalMemorySize0]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]173
174def FeatureR700 : SubtargetFeatureGeneration<"R700",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]175 [FeatureFetchLimit16, FeatureLocalMemorySize0]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]176
177def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]178 [FeatureFetchLimit16, FeatureLocalMemorySize32768]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]179
180def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
Tom Stellard880a80a2014-06-17 16:53:14 +0000[diff] [blame]181 [FeatureFetchLimit16, FeatureWavefrontSize64,
182 FeatureLocalMemorySize32768]
183>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]184
185def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
Tom Stellard42639a52014-07-21 15:44:58 +0000[diff] [blame]186 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize32768,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000[diff] [blame]187 FeatureWavefrontSize64, FeatureGCN, FeatureGCN1Encoding]>;
Tom Stellarda6c6e1b2013-06-07 20:37:48 +0000[diff] [blame]188
Tom Stellard6e1ee472013-10-29 16:37:28 +0000[diff] [blame]189def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
Tom Stellard42639a52014-07-21 15:44:58 +0000[diff] [blame]190 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000[diff] [blame]191 FeatureWavefrontSize64, FeatureGCN, FeatureFlatAddressSpace,
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame^]192 FeatureGCN1Encoding, FeatureCIInsts]>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]193
194def FeatureVolcanicIslands : SubtargetFeatureGeneration<"VOLCANIC_ISLANDS",
195 [Feature64BitPtr, FeatureFP64, FeatureLocalMemorySize65536,
Tom Stellardd7e6f132015-04-08 01:09:26 +0000[diff] [blame]196 FeatureWavefrontSize64, FeatureFlatAddressSpace, FeatureGCN,
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame^]197 FeatureGCN3Encoding, FeatureCIInsts]>;
Marek Olsak5df00d62014-12-07 12:18:57 +0000[diff] [blame]198
Tom Stellard3498e4f2013-06-07 20:28:55 +0000[diff] [blame]199//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]200
201def AMDGPUInstrInfo : InstrInfo {
202 let guessInstructionProperties = 1;
Matt Arsenault1ecac062015-02-18 02:15:32 +0000[diff] [blame]203 let noNamedPositionallyEncodedOperands = 1;
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]204}
205
Tom Stellard9d7ddd52014-11-14 14:08:00 +0000[diff] [blame]206def AMDGPUAsmParser : AsmParser {
207 // Some of the R600 registers have the same name, so this crashes.
208 // For example T0_XYZW and T0_XY both have the asm name T0.
209 let ShouldEmitMatchRegisterName = 0;
210}
211
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]212def AMDGPU : Target {
213 // Pull in Instruction Info:
214 let InstructionSet = AMDGPUInstrInfo;
Tom Stellard9d7ddd52014-11-14 14:08:00 +0000[diff] [blame]215 let AssemblyParsers = [AMDGPUAsmParser];
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]216}
217
Tom Stellardbc5b5372014-06-13 16:38:59 +0000[diff] [blame]218// Dummy Instruction itineraries for pseudo instructions
219def ALU_NULL : FuncUnit;
220def NullALU : InstrItinClass;
221
Tom Stellard0e70de52014-05-16 20:56:45 +0000[diff] [blame]222//===----------------------------------------------------------------------===//
223// Predicate helper class
224//===----------------------------------------------------------------------===//
225
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame^]226def TruePredicate : Predicate<"true">;
227def isSICI : Predicate<
228 "Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||"
229 "Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS"
230>, AssemblerPredicate<"FeatureGCN1Encoding">;
231
Tom Stellard0e70de52014-05-16 20:56:45 +0000[diff] [blame]232class PredicateControl {
233 Predicate SubtargetPredicate;
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame^]234 Predicate SIAssemblerPredicate = isSICI;
Tom Stellardd7e6f132015-04-08 01:09:26 +0000[diff] [blame]235 list<Predicate> AssemblerPredicates = [];
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame^]236 Predicate AssemblerPredicate = TruePredicate;
Tom Stellard0e70de52014-05-16 20:56:45 +0000[diff] [blame]237 list<Predicate> OtherPredicates = [];
Tom Stellardd1f0f022015-04-23 19:33:54 +0000[diff] [blame^]238 list<Predicate> Predicates = !listconcat([SubtargetPredicate, AssemblerPredicate],
Tom Stellardd7e6f132015-04-08 01:09:26 +0000[diff] [blame]239 AssemblerPredicates,
Tom Stellard0e70de52014-05-16 20:56:45 +0000[diff] [blame]240 OtherPredicates);
241}
242
Tom Stellard75aadc22012-12-11 21:25:42 +0000[diff] [blame]243// Include AMDGPU TD files
244include "R600Schedule.td"
245include "SISchedule.td"
246include "Processors.td"
247include "AMDGPUInstrInfo.td"
248include "AMDGPUIntrinsics.td"
249include "AMDGPURegisterInfo.td"
250include "AMDGPUInstructions.td"
Christian Konig2c8f6d52013-03-07 09:03:52 +0000[diff] [blame]251include "AMDGPUCallingConv.td"