Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-4.19 / 3405421344b808534d7a4c483354ea67e6edf491 / . / arch / arm / boot / dts / am33xx.dtsi
blob: 3b605411ba057085b5f58480f11ccaa6c7b72029 [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 };
39
40 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]41 #address-cells = <1>;
42 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]43 cpu@0 {
44 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]45 device_type = "cpu";
46 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]47
48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
61 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]62 };
63 };
64
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]65 pmu {
66 compatible = "arm,cortex-a8-pmu";
67 interrupts = <3>;
68 };
69
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]70 /*
71 * The soc node represents the soc top level view. It is uses for IPs
72 * that are not memory mapped in the MPU view or for the MPU itself.
73 */
74 soc {
75 compatible = "ti,omap-infra";
76 mpu {
77 compatible = "ti,omap3-mpu";
78 ti,hwmods = "mpu";
79 };
80 };
81
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]82 am33xx_pinmux: pinmux@44e10800 {
83 compatible = "pinctrl-single";
84 reg = <0x44e10800 0x0238>;
85 #address-cells = <1>;
86 #size-cells = <0>;
87 pinctrl-single,register-width = <32>;
88 pinctrl-single,function-mask = <0x7f>;
89 };
90
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]91 /*
92 * XXX: Use a flat representation of the AM33XX interconnect.
93 * The real AM33XX interconnect network is quite complex.Since
94 * that will not bring real advantage to represent that in DT
95 * for the moment, just use a fake OCP bus entry to represent
96 * the whole bus hierarchy.
97 */
98 ocp {
99 compatible = "simple-bus";
100 #address-cells = <1>;
101 #size-cells = <1>;
102 ranges;
103 ti,hwmods = "l3_main";
104
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]105 prcm: prcm@44e00000 {
106 compatible = "ti,am3-prcm";
107 reg = <0x44e00000 0x4000>;
108
109 prcm_clocks: clocks {
110 #address-cells = <1>;
111 #size-cells = <0>;
112 };
113
114 prcm_clockdomains: clockdomains {
115 };
116 };
117
118 scrm: scrm@44e10000 {
119 compatible = "ti,am3-scrm";
120 reg = <0x44e10000 0x2000>;
121
122 scrm_clocks: clocks {
123 #address-cells = <1>;
124 #size-cells = <0>;
125 };
126
127 scrm_clockdomains: clockdomains {
128 };
129 };
130
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]131 intc: interrupt-controller@48200000 {
132 compatible = "ti,omap2-intc";
133 interrupt-controller;
134 #interrupt-cells = <1>;
135 ti,intc-size = <128>;
136 reg = <0x48200000 0x1000>;
137 };
138
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]139 edma: edma@49000000 {
140 compatible = "ti,edma3";
141 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
142 reg = <0x49000000 0x10000>,
143 <0x44e10f90 0x10>;
144 interrupts = <12 13 14>;
145 #dma-cells = <1>;
146 dma-channels = <64>;
147 ti,edma-regions = <4>;
148 ti,edma-slots = <256>;
149 };
150
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]151 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]152 compatible = "ti,omap4-gpio";
153 ti,hwmods = "gpio1";
154 gpio-controller;
155 #gpio-cells = <2>;
156 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]157 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]158 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]159 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]160 };
161
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]162 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]163 compatible = "ti,omap4-gpio";
164 ti,hwmods = "gpio2";
165 gpio-controller;
166 #gpio-cells = <2>;
167 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]168 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]169 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]170 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]171 };
172
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]173 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]174 compatible = "ti,omap4-gpio";
175 ti,hwmods = "gpio3";
176 gpio-controller;
177 #gpio-cells = <2>;
178 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]179 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]180 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]181 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]182 };
183
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]184 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]185 compatible = "ti,omap4-gpio";
186 ti,hwmods = "gpio4";
187 gpio-controller;
188 #gpio-cells = <2>;
189 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]190 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]191 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]192 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]193 };
194
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]195 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]196 compatible = "ti,omap3-uart";
197 ti,hwmods = "uart1";
198 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]199 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]200 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]201 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]202 };
203
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]204 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]205 compatible = "ti,omap3-uart";
206 ti,hwmods = "uart2";
207 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]208 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]209 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]210 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]211 };
212
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]213 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]214 compatible = "ti,omap3-uart";
215 ti,hwmods = "uart3";
216 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]217 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]218 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]219 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]220 };
221
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]222 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]223 compatible = "ti,omap3-uart";
224 ti,hwmods = "uart4";
225 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]226 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]227 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]228 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]229 };
230
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]231 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]232 compatible = "ti,omap3-uart";
233 ti,hwmods = "uart5";
234 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]235 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]236 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]237 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]238 };
239
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]240 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]241 compatible = "ti,omap3-uart";
242 ti,hwmods = "uart6";
243 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]244 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]245 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]246 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]247 };
248
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]249 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]250 compatible = "ti,omap4-i2c";
251 #address-cells = <1>;
252 #size-cells = <0>;
253 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]254 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]255 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]256 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]257 };
258
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]259 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]260 compatible = "ti,omap4-i2c";
261 #address-cells = <1>;
262 #size-cells = <0>;
263 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]264 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]265 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]266 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]267 };
268
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]269 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]270 compatible = "ti,omap4-i2c";
271 #address-cells = <1>;
272 #size-cells = <0>;
273 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]274 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]275 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]276 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]277 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]278
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]279 mmc1: mmc@48060000 {
280 compatible = "ti,omap4-hsmmc";
281 ti,hwmods = "mmc1";
282 ti,dual-volt;
283 ti,needs-special-reset;
284 ti,needs-special-hs-handling;
285 dmas = <&edma 24
286 &edma 25>;
287 dma-names = "tx", "rx";
288 interrupts = <64>;
289 interrupt-parent = <&intc>;
290 reg = <0x48060000 0x1000>;
291 status = "disabled";
292 };
293
294 mmc2: mmc@481d8000 {
295 compatible = "ti,omap4-hsmmc";
296 ti,hwmods = "mmc2";
297 ti,needs-special-reset;
298 dmas = <&edma 2
299 &edma 3>;
300 dma-names = "tx", "rx";
301 interrupts = <28>;
302 interrupt-parent = <&intc>;
303 reg = <0x481d8000 0x1000>;
304 status = "disabled";
305 };
306
307 mmc3: mmc@47810000 {
308 compatible = "ti,omap4-hsmmc";
309 ti,hwmods = "mmc3";
310 ti,needs-special-reset;
311 interrupts = <29>;
312 interrupt-parent = <&intc>;
313 reg = <0x47810000 0x1000>;
314 status = "disabled";
315 };
316
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]317 hwspinlock: spinlock@480ca000 {
318 compatible = "ti,omap4-hwspinlock";
319 reg = <0x480ca000 0x1000>;
320 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame^]321 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]322 };
323
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]324 wdt2: wdt@44e35000 {
325 compatible = "ti,omap3-wdt";
326 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]327 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]328 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]329 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]330
331 dcan0: d_can@481cc000 {
332 compatible = "bosch,d_can";
333 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]334 reg = <0x481cc000 0x2000
335 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]336 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]337 status = "disabled";
338 };
339
340 dcan1: d_can@481d0000 {
341 compatible = "bosch,d_can";
342 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]343 reg = <0x481d0000 0x2000
344 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]345 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]346 status = "disabled";
347 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]348
349 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]350 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]351 reg = <0x44e31000 0x400>;
352 interrupts = <67>;
353 ti,hwmods = "timer1";
354 ti,timer-alwon;
355 };
356
357 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]358 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]359 reg = <0x48040000 0x400>;
360 interrupts = <68>;
361 ti,hwmods = "timer2";
362 };
363
364 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]365 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]366 reg = <0x48042000 0x400>;
367 interrupts = <69>;
368 ti,hwmods = "timer3";
369 };
370
371 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]372 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]373 reg = <0x48044000 0x400>;
374 interrupts = <92>;
375 ti,hwmods = "timer4";
376 ti,timer-pwm;
377 };
378
379 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]380 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]381 reg = <0x48046000 0x400>;
382 interrupts = <93>;
383 ti,hwmods = "timer5";
384 ti,timer-pwm;
385 };
386
387 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]388 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]389 reg = <0x48048000 0x400>;
390 interrupts = <94>;
391 ti,hwmods = "timer6";
392 ti,timer-pwm;
393 };
394
395 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]396 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]397 reg = <0x4804a000 0x400>;
398 interrupts = <95>;
399 ti,hwmods = "timer7";
400 ti,timer-pwm;
401 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]402
403 rtc@44e3e000 {
404 compatible = "ti,da830-rtc";
405 reg = <0x44e3e000 0x1000>;
406 interrupts = <75
407 76>;
408 ti,hwmods = "rtc";
409 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]410
411 spi0: spi@48030000 {
412 compatible = "ti,omap4-mcspi";
413 #address-cells = <1>;
414 #size-cells = <0>;
415 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]416 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]417 ti,spi-num-cs = <2>;
418 ti,hwmods = "spi0";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]419 dmas = <&edma 16
420 &edma 17
421 &edma 18
422 &edma 19>;
423 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]424 status = "disabled";
425 };
426
427 spi1: spi@481a0000 {
428 compatible = "ti,omap4-mcspi";
429 #address-cells = <1>;
430 #size-cells = <0>;
431 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]432 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]433 ti,spi-num-cs = <2>;
434 ti,hwmods = "spi1";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]435 dmas = <&edma 42
436 &edma 43
437 &edma 44
438 &edma 45>;
439 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]440 status = "disabled";
441 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]442
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]443 usb: usb@47400000 {
444 compatible = "ti,am33xx-usb";
445 reg = <0x47400000 0x1000>;
446 ranges;
447 #address-cells = <1>;
448 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]449 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]450 status = "disabled";
451
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]452 usb_ctrl_mod: control@44e10000 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]453 compatible = "ti,am335x-usb-ctrl-module";
454 reg = <0x44e10620 0x10
455 0x44e10648 0x4>;
456 reg-names = "phy_ctrl", "wakeup";
457 status = "disabled";
458 };
459
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]460 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]461 compatible = "ti,am335x-usb-phy";
462 reg = <0x47401300 0x100>;
463 reg-names = "phy";
464 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]465 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]466 };
467
468 usb0: usb@47401000 {
469 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]470 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]471 reg = <0x47401400 0x400
472 0x47401000 0x200>;
473 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]474
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]475 interrupts = <18>;
476 interrupt-names = "mc";
477 dr_mode = "otg";
478 mentor,multipoint = <1>;
479 mentor,num-eps = <16>;
480 mentor,ram-bits = <12>;
481 mentor,power = <500>;
482 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]483
484 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
485 &cppi41dma 2 0 &cppi41dma 3 0
486 &cppi41dma 4 0 &cppi41dma 5 0
487 &cppi41dma 6 0 &cppi41dma 7 0
488 &cppi41dma 8 0 &cppi41dma 9 0
489 &cppi41dma 10 0 &cppi41dma 11 0
490 &cppi41dma 12 0 &cppi41dma 13 0
491 &cppi41dma 14 0 &cppi41dma 0 1
492 &cppi41dma 1 1 &cppi41dma 2 1
493 &cppi41dma 3 1 &cppi41dma 4 1
494 &cppi41dma 5 1 &cppi41dma 6 1
495 &cppi41dma 7 1 &cppi41dma 8 1
496 &cppi41dma 9 1 &cppi41dma 10 1
497 &cppi41dma 11 1 &cppi41dma 12 1
498 &cppi41dma 13 1 &cppi41dma 14 1>;
499 dma-names =
500 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
501 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
502 "rx14", "rx15",
503 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
504 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
505 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]506 };
507
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]508 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]509 compatible = "ti,am335x-usb-phy";
510 reg = <0x47401b00 0x100>;
511 reg-names = "phy";
512 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]513 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]514 };
515
516 usb1: usb@47401800 {
517 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]518 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]519 reg = <0x47401c00 0x400
520 0x47401800 0x200>;
521 reg-names = "mc", "control";
522 interrupts = <19>;
523 interrupt-names = "mc";
524 dr_mode = "otg";
525 mentor,multipoint = <1>;
526 mentor,num-eps = <16>;
527 mentor,ram-bits = <12>;
528 mentor,power = <500>;
529 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]530
531 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
532 &cppi41dma 17 0 &cppi41dma 18 0
533 &cppi41dma 19 0 &cppi41dma 20 0
534 &cppi41dma 21 0 &cppi41dma 22 0
535 &cppi41dma 23 0 &cppi41dma 24 0
536 &cppi41dma 25 0 &cppi41dma 26 0
537 &cppi41dma 27 0 &cppi41dma 28 0
538 &cppi41dma 29 0 &cppi41dma 15 1
539 &cppi41dma 16 1 &cppi41dma 17 1
540 &cppi41dma 18 1 &cppi41dma 19 1
541 &cppi41dma 20 1 &cppi41dma 21 1
542 &cppi41dma 22 1 &cppi41dma 23 1
543 &cppi41dma 24 1 &cppi41dma 25 1
544 &cppi41dma 26 1 &cppi41dma 27 1
545 &cppi41dma 28 1 &cppi41dma 29 1>;
546 dma-names =
547 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
548 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
549 "rx14", "rx15",
550 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
551 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
552 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]553 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]554
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]555 cppi41dma: dma-controller@07402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]556 compatible = "ti,am3359-cppi41";
557 reg = <0x47400000 0x1000
558 0x47402000 0x1000
559 0x47403000 0x1000
560 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]561 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]562 interrupts = <17>;
563 interrupt-names = "glue";
564 #dma-cells = <2>;
565 #dma-channels = <30>;
566 #dma-requests = <256>;
567 status = "disabled";
568 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]569 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]570
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]571 epwmss0: epwmss@48300000 {
572 compatible = "ti,am33xx-pwmss";
573 reg = <0x48300000 0x10>;
574 ti,hwmods = "epwmss0";
575 #address-cells = <1>;
576 #size-cells = <1>;
577 status = "disabled";
578 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
579 0x48300180 0x48300180 0x80 /* EQEP */
580 0x48300200 0x48300200 0x80>; /* EHRPWM */
581
582 ecap0: ecap@48300100 {
583 compatible = "ti,am33xx-ecap";
584 #pwm-cells = <3>;
585 reg = <0x48300100 0x80>;
586 ti,hwmods = "ecap0";
587 status = "disabled";
588 };
589
590 ehrpwm0: ehrpwm@48300200 {
591 compatible = "ti,am33xx-ehrpwm";
592 #pwm-cells = <3>;
593 reg = <0x48300200 0x80>;
594 ti,hwmods = "ehrpwm0";
595 status = "disabled";
596 };
597 };
598
599 epwmss1: epwmss@48302000 {
600 compatible = "ti,am33xx-pwmss";
601 reg = <0x48302000 0x10>;
602 ti,hwmods = "epwmss1";
603 #address-cells = <1>;
604 #size-cells = <1>;
605 status = "disabled";
606 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
607 0x48302180 0x48302180 0x80 /* EQEP */
608 0x48302200 0x48302200 0x80>; /* EHRPWM */
609
610 ecap1: ecap@48302100 {
611 compatible = "ti,am33xx-ecap";
612 #pwm-cells = <3>;
613 reg = <0x48302100 0x80>;
614 ti,hwmods = "ecap1";
615 status = "disabled";
616 };
617
618 ehrpwm1: ehrpwm@48302200 {
619 compatible = "ti,am33xx-ehrpwm";
620 #pwm-cells = <3>;
621 reg = <0x48302200 0x80>;
622 ti,hwmods = "ehrpwm1";
623 status = "disabled";
624 };
625 };
626
627 epwmss2: epwmss@48304000 {
628 compatible = "ti,am33xx-pwmss";
629 reg = <0x48304000 0x10>;
630 ti,hwmods = "epwmss2";
631 #address-cells = <1>;
632 #size-cells = <1>;
633 status = "disabled";
634 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
635 0x48304180 0x48304180 0x80 /* EQEP */
636 0x48304200 0x48304200 0x80>; /* EHRPWM */
637
638 ecap2: ecap@48304100 {
639 compatible = "ti,am33xx-ecap";
640 #pwm-cells = <3>;
641 reg = <0x48304100 0x80>;
642 ti,hwmods = "ecap2";
643 status = "disabled";
644 };
645
646 ehrpwm2: ehrpwm@48304200 {
647 compatible = "ti,am33xx-ehrpwm";
648 #pwm-cells = <3>;
649 reg = <0x48304200 0x80>;
650 ti,hwmods = "ehrpwm2";
651 status = "disabled";
652 };
653 };
654
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]655 mac: ethernet@4a100000 {
656 compatible = "ti,cpsw";
657 ti,hwmods = "cpgmac0";
658 cpdma_channels = <8>;
659 ale_entries = <1024>;
660 bd_ram_size = <0x2000>;
661 no_bd_ram = <0>;
662 rx_descs = <64>;
663 mac_control = <0x20>;
664 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]665 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]666 cpts_clock_mult = <0x80000000>;
667 cpts_clock_shift = <29>;
668 reg = <0x4a100000 0x800
669 0x4a101200 0x100>;
670 #address-cells = <1>;
671 #size-cells = <1>;
672 interrupt-parent = <&intc>;
673 /*
674 * c0_rx_thresh_pend
675 * c0_rx_pend
676 * c0_tx_pend
677 * c0_misc_pend
678 */
679 interrupts = <40 41 42 43>;
680 ranges;
681
682 davinci_mdio: mdio@4a101000 {
683 compatible = "ti,davinci_mdio";
684 #address-cells = <1>;
685 #size-cells = <0>;
686 ti,hwmods = "davinci_mdio";
687 bus_freq = <1000000>;
688 reg = <0x4a101000 0x100>;
689 };
690
691 cpsw_emac0: slave@4a100200 {
692 /* Filled in by U-Boot */
693 mac-address = [ 00 00 00 00 00 00 ];
694 };
695
696 cpsw_emac1: slave@4a100300 {
697 /* Filled in by U-Boot */
698 mac-address = [ 00 00 00 00 00 00 ];
699 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]700
701 phy_sel: cpsw-phy-sel@44e10650 {
702 compatible = "ti,am3352-cpsw-phy-sel";
703 reg= <0x44e10650 0x4>;
704 reg-names = "gmii-sel";
705 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]706 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]707
708 ocmcram: ocmcram@40300000 {
709 compatible = "ti,am3352-ocmcram";
710 reg = <0x40300000 0x10000>;
711 ti,hwmods = "ocmcram";
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]712 };
713
714 wkup_m3: wkup_m3@44d00000 {
715 compatible = "ti,am3353-wkup-m3";
716 reg = <0x44d00000 0x4000 /* M3 UMEM */
717 0x44d80000 0x2000>; /* M3 DMEM */
718 ti,hwmods = "wkup_m3";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]719 ti,no-reset-on-init;
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]720 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]721
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]722 elm: elm@48080000 {
723 compatible = "ti,am3352-elm";
724 reg = <0x48080000 0x2000>;
725 interrupts = <4>;
726 ti,hwmods = "elm";
727 status = "disabled";
728 };
729
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]730 lcdc: lcdc@4830e000 {
731 compatible = "ti,am33xx-tilcdc";
732 reg = <0x4830e000 0x1000>;
733 interrupt-parent = <&intc>;
734 interrupts = <36>;
735 ti,hwmods = "lcdc";
736 status = "disabled";
737 };
738
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]739 tscadc: tscadc@44e0d000 {
740 compatible = "ti,am3359-tscadc";
741 reg = <0x44e0d000 0x1000>;
742 interrupt-parent = <&intc>;
743 interrupts = <16>;
744 ti,hwmods = "adc_tsc";
745 status = "disabled";
746
747 tsc {
748 compatible = "ti,am3359-tsc";
749 };
750 am335x_adc: adc {
751 #io-channel-cells = <1>;
752 compatible = "ti,am3359-adc";
753 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]754 };
755
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]756 gpmc: gpmc@50000000 {
757 compatible = "ti,am3352-gpmc";
758 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]759 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]760 reg = <0x50000000 0x2000>;
761 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]762 gpmc,num-cs = <7>;
763 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]764 #address-cells = <2>;
765 #size-cells = <1>;
766 status = "disabled";
767 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]768
769 sham: sham@53100000 {
770 compatible = "ti,omap4-sham";
771 ti,hwmods = "sham";
772 reg = <0x53100000 0x200>;
773 interrupts = <109>;
774 dmas = <&edma 36>;
775 dma-names = "rx";
776 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]777
778 aes: aes@53500000 {
779 compatible = "ti,omap4-aes";
780 ti,hwmods = "aes";
781 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]782 interrupts = <103>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]783 dmas = <&edma 6>,
784 <&edma 5>;
785 dma-names = "tx", "rx";
786 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]787
788 mcasp0: mcasp@48038000 {
789 compatible = "ti,am33xx-mcasp-audio";
790 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]791 reg = <0x48038000 0x2000>,
792 <0x46000000 0x400000>;
793 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]794 interrupts = <80>, <81>;
795 interrupts-names = "tx", "rx";
796 status = "disabled";
797 dmas = <&edma 8>,
798 <&edma 9>;
799 dma-names = "tx", "rx";
800 };
801
802 mcasp1: mcasp@4803C000 {
803 compatible = "ti,am33xx-mcasp-audio";
804 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]805 reg = <0x4803C000 0x2000>,
806 <0x46400000 0x400000>;
807 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]808 interrupts = <82>, <83>;
809 interrupts-names = "tx", "rx";
810 status = "disabled";
811 dmas = <&edma 10>,
812 <&edma 11>;
813 dma-names = "tx", "rx";
814 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]815
816 rng: rng@48310000 {
817 compatible = "ti,omap4-rng";
818 ti,hwmods = "rng";
819 reg = <0x48310000 0x2000>;
820 interrupts = <111>;
821 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]822 };
823};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]824
825/include/ "am33xx-clocks.dtsi"