Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2012 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> |
| 25 | * |
| 26 | */ |
| 27 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 28 | #include <linux/cpufreq.h> |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 29 | #include "i915_drv.h" |
| 30 | #include "intel_drv.h" |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 31 | #include "../../../platform/x86/intel_ips.h" |
| 32 | #include <linux/module.h> |
Paulo Zanoni | f9dcb0d | 2013-12-11 18:50:10 -0200 | [diff] [blame] | 33 | #include <linux/vgaarb.h> |
Damien Lespiau | f4db932 | 2013-06-24 22:59:50 +0100 | [diff] [blame] | 34 | #include <drm/i915_powerwell.h> |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 36 | |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 37 | /** |
| 38 | * RC6 is a special power stage which allows the GPU to enter an very |
| 39 | * low-voltage mode when idle, using down to 0V while at this stage. This |
| 40 | * stage is entered automatically when the GPU is idle when RC6 support is |
| 41 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. |
| 42 | * |
| 43 | * There are different RC6 modes available in Intel GPU, which differentiate |
| 44 | * among each other with the latency required to enter and leave RC6 and |
| 45 | * voltage consumed by the GPU in different states. |
| 46 | * |
| 47 | * The combination of the following flags define which states GPU is allowed |
| 48 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and |
| 49 | * RC6pp is deepest RC6. Their support by hardware varies according to the |
| 50 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one |
| 51 | * which brings the most power savings; deeper states save more power, but |
| 52 | * require higher latency to switch to and wake up. |
| 53 | */ |
| 54 | #define INTEL_RC6_ENABLE (1<<0) |
| 55 | #define INTEL_RC6p_ENABLE (1<<1) |
| 56 | #define INTEL_RC6pp_ENABLE (1<<2) |
| 57 | |
Eugeni Dodonov | f6750b3 | 2012-04-18 11:51:14 -0300 | [diff] [blame] | 58 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
| 59 | * framebuffer contents in-memory, aiming at reducing the required bandwidth |
| 60 | * during in-memory transfers and, therefore, reduce the power packet. |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 61 | * |
Eugeni Dodonov | f6750b3 | 2012-04-18 11:51:14 -0300 | [diff] [blame] | 62 | * The benefits of FBC are mostly visible with solid backgrounds and |
| 63 | * variation-less patterns. |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 64 | * |
Eugeni Dodonov | f6750b3 | 2012-04-18 11:51:14 -0300 | [diff] [blame] | 65 | * FBC-related functionality can be enabled by the means of the |
| 66 | * i915.i915_enable_fbc parameter |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 67 | */ |
| 68 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 69 | static void i8xx_disable_fbc(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 70 | { |
| 71 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 72 | u32 fbc_ctl; |
| 73 | |
| 74 | /* Disable compression */ |
| 75 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 76 | if ((fbc_ctl & FBC_CTL_EN) == 0) |
| 77 | return; |
| 78 | |
| 79 | fbc_ctl &= ~FBC_CTL_EN; |
| 80 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 81 | |
| 82 | /* Wait for compressing bit to clear */ |
| 83 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { |
| 84 | DRM_DEBUG_KMS("FBC idle timed out\n"); |
| 85 | return; |
| 86 | } |
| 87 | |
| 88 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 89 | } |
| 90 | |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 91 | static void i8xx_enable_fbc(struct drm_crtc *crtc) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 92 | { |
| 93 | struct drm_device *dev = crtc->dev; |
| 94 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 95 | struct drm_framebuffer *fb = crtc->primary->fb; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 96 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 97 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 98 | int cfb_pitch; |
Ville Syrjälä | 7f2cf22 | 2014-01-23 16:49:11 +0200 | [diff] [blame] | 99 | int i; |
Ville Syrjälä | 159f987 | 2013-11-28 17:29:57 +0200 | [diff] [blame] | 100 | u32 fbc_ctl; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 101 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 102 | cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 103 | if (fb->pitches[0] < cfb_pitch) |
| 104 | cfb_pitch = fb->pitches[0]; |
| 105 | |
Ville Syrjälä | 42a430f | 2013-11-28 17:29:56 +0200 | [diff] [blame] | 106 | /* FBC_CTL wants 32B or 64B units */ |
| 107 | if (IS_GEN2(dev)) |
| 108 | cfb_pitch = (cfb_pitch / 32) - 1; |
| 109 | else |
| 110 | cfb_pitch = (cfb_pitch / 64) - 1; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 111 | |
| 112 | /* Clear old tags */ |
| 113 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) |
| 114 | I915_WRITE(FBC_TAG + (i * 4), 0); |
| 115 | |
Ville Syrjälä | 159f987 | 2013-11-28 17:29:57 +0200 | [diff] [blame] | 116 | if (IS_GEN4(dev)) { |
| 117 | u32 fbc_ctl2; |
| 118 | |
| 119 | /* Set it up... */ |
| 120 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; |
Ville Syrjälä | 7f2cf22 | 2014-01-23 16:49:11 +0200 | [diff] [blame] | 121 | fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); |
Ville Syrjälä | 159f987 | 2013-11-28 17:29:57 +0200 | [diff] [blame] | 122 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
| 123 | I915_WRITE(FBC_FENCE_OFF, crtc->y); |
| 124 | } |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 125 | |
| 126 | /* enable it... */ |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 127 | fbc_ctl = I915_READ(FBC_CONTROL); |
| 128 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; |
| 129 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 130 | if (IS_I945GM(dev)) |
| 131 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ |
| 132 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 133 | fbc_ctl |= obj->fence_reg; |
| 134 | I915_WRITE(FBC_CONTROL, fbc_ctl); |
| 135 | |
Ville Syrjälä | 5cd5410 | 2014-01-23 16:49:16 +0200 | [diff] [blame] | 136 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 137 | cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 138 | } |
| 139 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 140 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 141 | { |
| 142 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 143 | |
| 144 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; |
| 145 | } |
| 146 | |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 147 | static void g4x_enable_fbc(struct drm_crtc *crtc) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 148 | { |
| 149 | struct drm_device *dev = crtc->dev; |
| 150 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 151 | struct drm_framebuffer *fb = crtc->primary->fb; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 152 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 153 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 154 | u32 dpfc_ctl; |
| 155 | |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 156 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; |
| 157 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
| 158 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
| 159 | else |
| 160 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 161 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 162 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 163 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
| 164 | |
| 165 | /* enable it... */ |
Ville Syrjälä | fe74c1a | 2014-01-23 16:49:13 +0200 | [diff] [blame] | 166 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 167 | |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 168 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 169 | } |
| 170 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 171 | static void g4x_disable_fbc(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 172 | { |
| 173 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 174 | u32 dpfc_ctl; |
| 175 | |
| 176 | /* Disable compression */ |
| 177 | dpfc_ctl = I915_READ(DPFC_CONTROL); |
| 178 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 179 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 180 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); |
| 181 | |
| 182 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 183 | } |
| 184 | } |
| 185 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 186 | static bool g4x_fbc_enabled(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 187 | { |
| 188 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 189 | |
| 190 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; |
| 191 | } |
| 192 | |
| 193 | static void sandybridge_blit_fbc_update(struct drm_device *dev) |
| 194 | { |
| 195 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 196 | u32 blt_ecoskpd; |
| 197 | |
| 198 | /* Make sure blitter notifies FBC of writes */ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 199 | |
| 200 | /* Blitter is part of Media powerwell on VLV. No impact of |
| 201 | * his param in other platforms for now */ |
| 202 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA); |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 203 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 204 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
| 205 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << |
| 206 | GEN6_BLITTER_LOCK_SHIFT; |
| 207 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 208 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; |
| 209 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 210 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << |
| 211 | GEN6_BLITTER_LOCK_SHIFT); |
| 212 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); |
| 213 | POSTING_READ(GEN6_BLITTER_ECOSKPD); |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 214 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 215 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 216 | } |
| 217 | |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 218 | static void ironlake_enable_fbc(struct drm_crtc *crtc) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 219 | { |
| 220 | struct drm_device *dev = crtc->dev; |
| 221 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 222 | struct drm_framebuffer *fb = crtc->primary->fb; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 223 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 224 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 225 | u32 dpfc_ctl; |
| 226 | |
Ville Syrjälä | 46f3dab | 2014-01-23 16:49:14 +0200 | [diff] [blame] | 227 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 228 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
Ben Widawsky | 5e59f71 | 2014-06-30 10:41:24 -0700 | [diff] [blame] | 229 | dev_priv->fbc.threshold++; |
| 230 | |
| 231 | switch (dev_priv->fbc.threshold) { |
| 232 | case 4: |
| 233 | case 3: |
| 234 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; |
| 235 | break; |
| 236 | case 2: |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 237 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
Ben Widawsky | 5e59f71 | 2014-06-30 10:41:24 -0700 | [diff] [blame] | 238 | break; |
| 239 | case 1: |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 240 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
Ben Widawsky | 5e59f71 | 2014-06-30 10:41:24 -0700 | [diff] [blame] | 241 | break; |
| 242 | } |
Ville Syrjälä | d629336 | 2013-11-21 21:29:45 +0200 | [diff] [blame] | 243 | dpfc_ctl |= DPFC_CTL_FENCE_EN; |
| 244 | if (IS_GEN5(dev)) |
| 245 | dpfc_ctl |= obj->fence_reg; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 246 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 247 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 248 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 249 | /* enable it... */ |
| 250 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
| 251 | |
| 252 | if (IS_GEN6(dev)) { |
| 253 | I915_WRITE(SNB_DPFC_CTL_SA, |
| 254 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
| 255 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
| 256 | sandybridge_blit_fbc_update(dev); |
| 257 | } |
| 258 | |
Ville Syrjälä | 84f44ce | 2013-04-17 17:48:49 +0300 | [diff] [blame] | 259 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 260 | } |
| 261 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 262 | static void ironlake_disable_fbc(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 263 | { |
| 264 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 265 | u32 dpfc_ctl; |
| 266 | |
| 267 | /* Disable compression */ |
| 268 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); |
| 269 | if (dpfc_ctl & DPFC_CTL_EN) { |
| 270 | dpfc_ctl &= ~DPFC_CTL_EN; |
| 271 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); |
| 272 | |
| 273 | DRM_DEBUG_KMS("disabled FBC\n"); |
| 274 | } |
| 275 | } |
| 276 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 277 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 278 | { |
| 279 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 280 | |
| 281 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; |
| 282 | } |
| 283 | |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 284 | static void gen7_enable_fbc(struct drm_crtc *crtc) |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 285 | { |
| 286 | struct drm_device *dev = crtc->dev; |
| 287 | struct drm_i915_private *dev_priv = dev->dev_private; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 288 | struct drm_framebuffer *fb = crtc->primary->fb; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 289 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 290 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 291 | u32 dpfc_ctl; |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 292 | |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 293 | dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane); |
| 294 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
Ben Widawsky | 5e59f71 | 2014-06-30 10:41:24 -0700 | [diff] [blame] | 295 | dev_priv->fbc.threshold++; |
| 296 | |
| 297 | switch (dev_priv->fbc.threshold) { |
| 298 | case 4: |
| 299 | case 3: |
| 300 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; |
| 301 | break; |
| 302 | case 2: |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 303 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
Ben Widawsky | 5e59f71 | 2014-06-30 10:41:24 -0700 | [diff] [blame] | 304 | break; |
| 305 | case 1: |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 306 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
Ben Widawsky | 5e59f71 | 2014-06-30 10:41:24 -0700 | [diff] [blame] | 307 | break; |
| 308 | } |
| 309 | |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 310 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; |
| 311 | |
Rodrigo Vivi | da46f93 | 2014-08-01 02:04:45 -0700 | [diff] [blame] | 312 | if (dev_priv->fbc.false_color) |
| 313 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; |
| 314 | |
Ville Syrjälä | 3fa2e0e | 2014-01-23 16:49:12 +0200 | [diff] [blame] | 315 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 316 | |
Rodrigo Vivi | 891348b | 2013-05-06 19:37:36 -0300 | [diff] [blame] | 317 | if (IS_IVYBRIDGE(dev)) { |
Damien Lespiau | 7dd23ba | 2013-05-10 14:33:17 +0100 | [diff] [blame] | 318 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
Ville Syrjälä | 2adb6db | 2014-03-05 13:05:46 +0200 | [diff] [blame] | 319 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 320 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 321 | ILK_FBCQ_DIS); |
Rodrigo Vivi | 2855416 | 2013-05-06 19:37:37 -0300 | [diff] [blame] | 322 | } else { |
Ville Syrjälä | 2adb6db | 2014-03-05 13:05:46 +0200 | [diff] [blame] | 323 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
Ville Syrjälä | 8f670bb | 2014-03-05 13:05:47 +0200 | [diff] [blame] | 324 | I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), |
| 325 | I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | |
| 326 | HSW_FBCQ_DIS); |
Rodrigo Vivi | 891348b | 2013-05-06 19:37:36 -0300 | [diff] [blame] | 327 | } |
Rodrigo Vivi | b74ea10 | 2013-05-09 14:08:38 -0300 | [diff] [blame] | 328 | |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 329 | I915_WRITE(SNB_DPFC_CTL_SA, |
| 330 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); |
| 331 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); |
| 332 | |
| 333 | sandybridge_blit_fbc_update(dev); |
| 334 | |
Ville Syrjälä | b19870e | 2013-11-06 23:02:25 +0200 | [diff] [blame] | 335 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
Rodrigo Vivi | abe959c | 2013-05-06 19:37:33 -0300 | [diff] [blame] | 336 | } |
| 337 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 338 | bool intel_fbc_enabled(struct drm_device *dev) |
| 339 | { |
| 340 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 341 | |
| 342 | if (!dev_priv->display.fbc_enabled) |
| 343 | return false; |
| 344 | |
| 345 | return dev_priv->display.fbc_enabled(dev); |
| 346 | } |
| 347 | |
| 348 | static void intel_fbc_work_fn(struct work_struct *__work) |
| 349 | { |
| 350 | struct intel_fbc_work *work = |
| 351 | container_of(to_delayed_work(__work), |
| 352 | struct intel_fbc_work, work); |
| 353 | struct drm_device *dev = work->crtc->dev; |
| 354 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 355 | |
| 356 | mutex_lock(&dev->struct_mutex); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 357 | if (work == dev_priv->fbc.fbc_work) { |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 358 | /* Double check that we haven't switched fb without cancelling |
| 359 | * the prior work. |
| 360 | */ |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 361 | if (work->crtc->primary->fb == work->fb) { |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 362 | dev_priv->display.enable_fbc(work->crtc); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 363 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 364 | dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 365 | dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 366 | dev_priv->fbc.y = work->crtc->y; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 367 | } |
| 368 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 369 | dev_priv->fbc.fbc_work = NULL; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 370 | } |
| 371 | mutex_unlock(&dev->struct_mutex); |
| 372 | |
| 373 | kfree(work); |
| 374 | } |
| 375 | |
| 376 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) |
| 377 | { |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 378 | if (dev_priv->fbc.fbc_work == NULL) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 379 | return; |
| 380 | |
| 381 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); |
| 382 | |
| 383 | /* Synchronisation is provided by struct_mutex and checking of |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 384 | * dev_priv->fbc.fbc_work, so we can perform the cancellation |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 385 | * entirely asynchronously. |
| 386 | */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 387 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 388 | /* tasklet was killed before being run, clean up */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 389 | kfree(dev_priv->fbc.fbc_work); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 390 | |
| 391 | /* Mark the work as no longer wanted so that if it does |
| 392 | * wake-up (because the work was already running and waiting |
| 393 | * for our mutex), it will discover that is no longer |
| 394 | * necessary to run. |
| 395 | */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 396 | dev_priv->fbc.fbc_work = NULL; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 397 | } |
| 398 | |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 399 | static void intel_enable_fbc(struct drm_crtc *crtc) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 400 | { |
| 401 | struct intel_fbc_work *work; |
| 402 | struct drm_device *dev = crtc->dev; |
| 403 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 404 | |
| 405 | if (!dev_priv->display.enable_fbc) |
| 406 | return; |
| 407 | |
| 408 | intel_cancel_fbc_work(dev_priv); |
| 409 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 410 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 411 | if (work == NULL) { |
Paulo Zanoni | 6cdcb5e | 2013-06-12 17:27:29 -0300 | [diff] [blame] | 412 | DRM_ERROR("Failed to allocate FBC work structure\n"); |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 413 | dev_priv->display.enable_fbc(crtc); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 414 | return; |
| 415 | } |
| 416 | |
| 417 | work->crtc = crtc; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 418 | work->fb = crtc->primary->fb; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 419 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
| 420 | |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 421 | dev_priv->fbc.fbc_work = work; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 422 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 423 | /* Delay the actual enabling to let pageflipping cease and the |
| 424 | * display to settle before starting the compression. Note that |
| 425 | * this delay also serves a second purpose: it allows for a |
| 426 | * vblank to pass after disabling the FBC before we attempt |
| 427 | * to modify the control registers. |
| 428 | * |
| 429 | * A more complicated solution would involve tracking vblanks |
| 430 | * following the termination of the page-flipping sequence |
| 431 | * and indeed performing the enable as a co-routine and not |
| 432 | * waiting synchronously upon the vblank. |
Damien Lespiau | 7457d61 | 2013-06-07 17:41:07 +0100 | [diff] [blame] | 433 | * |
| 434 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 435 | */ |
| 436 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); |
| 437 | } |
| 438 | |
| 439 | void intel_disable_fbc(struct drm_device *dev) |
| 440 | { |
| 441 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 442 | |
| 443 | intel_cancel_fbc_work(dev_priv); |
| 444 | |
| 445 | if (!dev_priv->display.disable_fbc) |
| 446 | return; |
| 447 | |
| 448 | dev_priv->display.disable_fbc(dev); |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 449 | dev_priv->fbc.plane = -1; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 450 | } |
| 451 | |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 452 | static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, |
| 453 | enum no_fbc_reason reason) |
| 454 | { |
| 455 | if (dev_priv->fbc.no_fbc_reason == reason) |
| 456 | return false; |
| 457 | |
| 458 | dev_priv->fbc.no_fbc_reason = reason; |
| 459 | return true; |
| 460 | } |
| 461 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 462 | /** |
| 463 | * intel_update_fbc - enable/disable FBC as needed |
| 464 | * @dev: the drm_device |
| 465 | * |
| 466 | * Set up the framebuffer compression hardware at mode set time. We |
| 467 | * enable it if possible: |
| 468 | * - plane A only (on pre-965) |
| 469 | * - no pixel mulitply/line duplication |
| 470 | * - no alpha buffer discard |
| 471 | * - no dual wide |
Paulo Zanoni | f85da86 | 2013-06-04 16:53:39 -0300 | [diff] [blame] | 472 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 473 | * |
| 474 | * We can't assume that any compression will take place (worst case), |
| 475 | * so the compressed buffer has to be the same size as the uncompressed |
| 476 | * one. It also must reside (along with the line length buffer) in |
| 477 | * stolen memory. |
| 478 | * |
| 479 | * We need to enable/disable FBC on a global basis. |
| 480 | */ |
| 481 | void intel_update_fbc(struct drm_device *dev) |
| 482 | { |
| 483 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 484 | struct drm_crtc *crtc = NULL, *tmp_crtc; |
| 485 | struct intel_crtc *intel_crtc; |
| 486 | struct drm_framebuffer *fb; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 487 | struct drm_i915_gem_object *obj; |
Ville Syrjälä | ef644fd | 2013-09-04 18:25:21 +0300 | [diff] [blame] | 488 | const struct drm_display_mode *adjusted_mode; |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 489 | unsigned int max_width, max_height; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 490 | |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 491 | if (!HAS_FBC(dev)) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 492 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 493 | return; |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 494 | } |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 495 | |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 496 | if (!i915.powersave) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 497 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
| 498 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 499 | return; |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 500 | } |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 501 | |
| 502 | /* |
| 503 | * If FBC is already on, we just have to verify that we can |
| 504 | * keep it that way... |
| 505 | * Need to disable if: |
| 506 | * - more than one pipe is active |
| 507 | * - changing FBC params (stride, fence, mode) |
| 508 | * - new fb is too large to fit in compressed buffer |
| 509 | * - going to an unsupported config (interlace, pixel multiply, etc.) |
| 510 | */ |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 511 | for_each_crtc(dev, tmp_crtc) { |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 512 | if (intel_crtc_active(tmp_crtc) && |
Ville Syrjälä | 4c445e0 | 2013-10-09 17:24:58 +0300 | [diff] [blame] | 513 | to_intel_crtc(tmp_crtc)->primary_enabled) { |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 514 | if (crtc) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 515 | if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) |
| 516 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 517 | goto out_disable; |
| 518 | } |
| 519 | crtc = tmp_crtc; |
| 520 | } |
| 521 | } |
| 522 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 523 | if (!crtc || crtc->primary->fb == NULL) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 524 | if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT)) |
| 525 | DRM_DEBUG_KMS("no output, disabling\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 526 | goto out_disable; |
| 527 | } |
| 528 | |
| 529 | intel_crtc = to_intel_crtc(crtc); |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 530 | fb = crtc->primary->fb; |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 531 | obj = intel_fb_obj(fb); |
Ville Syrjälä | ef644fd | 2013-09-04 18:25:21 +0300 | [diff] [blame] | 532 | adjusted_mode = &intel_crtc->config.adjusted_mode; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 533 | |
Chris Wilson | 0368920 | 2014-06-06 10:37:11 +0100 | [diff] [blame] | 534 | if (i915.enable_fbc < 0) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 535 | if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) |
| 536 | DRM_DEBUG_KMS("disabled per chip default\n"); |
Damien Lespiau | 8a5729a | 2013-06-24 16:22:02 +0100 | [diff] [blame] | 537 | goto out_disable; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 538 | } |
Jani Nikula | d330a95 | 2014-01-21 11:24:25 +0200 | [diff] [blame] | 539 | if (!i915.enable_fbc) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 540 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
| 541 | DRM_DEBUG_KMS("fbc disabled per module param\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 542 | goto out_disable; |
| 543 | } |
Ville Syrjälä | ef644fd | 2013-09-04 18:25:21 +0300 | [diff] [blame] | 544 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
| 545 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 546 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) |
| 547 | DRM_DEBUG_KMS("mode incompatible with compression, " |
| 548 | "disabling\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 549 | goto out_disable; |
| 550 | } |
Paulo Zanoni | f85da86 | 2013-06-04 16:53:39 -0300 | [diff] [blame] | 551 | |
Daisy Sun | 032843a | 2014-06-16 15:48:18 -0700 | [diff] [blame] | 552 | if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) { |
| 553 | max_width = 4096; |
| 554 | max_height = 4096; |
| 555 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 556 | max_width = 4096; |
| 557 | max_height = 2048; |
Paulo Zanoni | f85da86 | 2013-06-04 16:53:39 -0300 | [diff] [blame] | 558 | } else { |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 559 | max_width = 2048; |
| 560 | max_height = 1536; |
Paulo Zanoni | f85da86 | 2013-06-04 16:53:39 -0300 | [diff] [blame] | 561 | } |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 562 | if (intel_crtc->config.pipe_src_w > max_width || |
| 563 | intel_crtc->config.pipe_src_h > max_height) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 564 | if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) |
| 565 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 566 | goto out_disable; |
| 567 | } |
Ben Widawsky | 8f94d24 | 2014-02-20 16:01:20 -0800 | [diff] [blame] | 568 | if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && |
Ville Syrjälä | c5a44aa | 2013-11-28 17:29:58 +0200 | [diff] [blame] | 569 | intel_crtc->plane != PLANE_A) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 570 | if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) |
Ville Syrjälä | c5a44aa | 2013-11-28 17:29:58 +0200 | [diff] [blame] | 571 | DRM_DEBUG_KMS("plane not A, disabling compression\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 572 | goto out_disable; |
| 573 | } |
| 574 | |
| 575 | /* The use of a CPU fence is mandatory in order to detect writes |
| 576 | * by the CPU to the scanout and trigger updates to the FBC. |
| 577 | */ |
| 578 | if (obj->tiling_mode != I915_TILING_X || |
| 579 | obj->fence_reg == I915_FENCE_REG_NONE) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 580 | if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED)) |
| 581 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 582 | goto out_disable; |
| 583 | } |
| 584 | |
| 585 | /* If the kernel debugger is active, always disable compression */ |
| 586 | if (in_dbg_master()) |
| 587 | goto out_disable; |
| 588 | |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 589 | if (i915_gem_stolen_setup_compression(dev, obj->base.size, |
Ben Widawsky | 5e59f71 | 2014-06-30 10:41:24 -0700 | [diff] [blame] | 590 | drm_format_plane_cpp(fb->pixel_format, 0))) { |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 591 | if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL)) |
| 592 | DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 593 | goto out_disable; |
| 594 | } |
| 595 | |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 596 | /* If the scanout has not changed, don't modify the FBC settings. |
| 597 | * Note that we make the fundamental assumption that the fb->obj |
| 598 | * cannot be unpinned (and have its GTT offset and fence revoked) |
| 599 | * without first being decoupled from the scanout and FBC disabled. |
| 600 | */ |
Ben Widawsky | 5c3fe8b | 2013-06-27 16:30:21 -0700 | [diff] [blame] | 601 | if (dev_priv->fbc.plane == intel_crtc->plane && |
| 602 | dev_priv->fbc.fb_id == fb->base.id && |
| 603 | dev_priv->fbc.y == crtc->y) |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 604 | return; |
| 605 | |
| 606 | if (intel_fbc_enabled(dev)) { |
| 607 | /* We update FBC along two paths, after changing fb/crtc |
| 608 | * configuration (modeswitching) and after page-flipping |
| 609 | * finishes. For the latter, we know that not only did |
| 610 | * we disable the FBC at the start of the page-flip |
| 611 | * sequence, but also more than one vblank has passed. |
| 612 | * |
| 613 | * For the former case of modeswitching, it is possible |
| 614 | * to switch between two FBC valid configurations |
| 615 | * instantaneously so we do need to disable the FBC |
| 616 | * before we can modify its control registers. We also |
| 617 | * have to wait for the next vblank for that to take |
| 618 | * effect. However, since we delay enabling FBC we can |
| 619 | * assume that a vblank has passed since disabling and |
| 620 | * that we can safely alter the registers in the deferred |
| 621 | * callback. |
| 622 | * |
| 623 | * In the scenario that we go from a valid to invalid |
| 624 | * and then back to valid FBC configuration we have |
| 625 | * no strict enforcement that a vblank occurred since |
| 626 | * disabling the FBC. However, along all current pipe |
| 627 | * disabling paths we do need to wait for a vblank at |
| 628 | * some point. And we wait before enabling FBC anyway. |
| 629 | */ |
| 630 | DRM_DEBUG_KMS("disabling active FBC for update\n"); |
| 631 | intel_disable_fbc(dev); |
| 632 | } |
| 633 | |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 634 | intel_enable_fbc(crtc); |
Chris Wilson | 29ebf90 | 2013-07-27 17:23:55 +0100 | [diff] [blame] | 635 | dev_priv->fbc.no_fbc_reason = FBC_OK; |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 636 | return; |
| 637 | |
| 638 | out_disable: |
| 639 | /* Multiple disables should be harmless */ |
| 640 | if (intel_fbc_enabled(dev)) { |
| 641 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); |
| 642 | intel_disable_fbc(dev); |
| 643 | } |
Chris Wilson | 11be49e | 2012-11-15 11:32:20 +0000 | [diff] [blame] | 644 | i915_gem_stolen_cleanup_compression(dev); |
Eugeni Dodonov | 85208be | 2012-04-16 22:20:34 -0300 | [diff] [blame] | 645 | } |
| 646 | |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 647 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
| 648 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 649 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 650 | u32 tmp; |
| 651 | |
| 652 | tmp = I915_READ(CLKCFG); |
| 653 | |
| 654 | switch (tmp & CLKCFG_FSB_MASK) { |
| 655 | case CLKCFG_FSB_533: |
| 656 | dev_priv->fsb_freq = 533; /* 133*4 */ |
| 657 | break; |
| 658 | case CLKCFG_FSB_800: |
| 659 | dev_priv->fsb_freq = 800; /* 200*4 */ |
| 660 | break; |
| 661 | case CLKCFG_FSB_667: |
| 662 | dev_priv->fsb_freq = 667; /* 167*4 */ |
| 663 | break; |
| 664 | case CLKCFG_FSB_400: |
| 665 | dev_priv->fsb_freq = 400; /* 100*4 */ |
| 666 | break; |
| 667 | } |
| 668 | |
| 669 | switch (tmp & CLKCFG_MEM_MASK) { |
| 670 | case CLKCFG_MEM_533: |
| 671 | dev_priv->mem_freq = 533; |
| 672 | break; |
| 673 | case CLKCFG_MEM_667: |
| 674 | dev_priv->mem_freq = 667; |
| 675 | break; |
| 676 | case CLKCFG_MEM_800: |
| 677 | dev_priv->mem_freq = 800; |
| 678 | break; |
| 679 | } |
| 680 | |
| 681 | /* detect pineview DDR3 setting */ |
| 682 | tmp = I915_READ(CSHRDDR3CTL); |
| 683 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; |
| 684 | } |
| 685 | |
| 686 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) |
| 687 | { |
Jani Nikula | 50227e1 | 2014-03-31 14:27:21 +0300 | [diff] [blame] | 688 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 689 | u16 ddrpll, csipll; |
| 690 | |
| 691 | ddrpll = I915_READ16(DDRMPLL1); |
| 692 | csipll = I915_READ16(CSIPLL0); |
| 693 | |
| 694 | switch (ddrpll & 0xff) { |
| 695 | case 0xc: |
| 696 | dev_priv->mem_freq = 800; |
| 697 | break; |
| 698 | case 0x10: |
| 699 | dev_priv->mem_freq = 1066; |
| 700 | break; |
| 701 | case 0x14: |
| 702 | dev_priv->mem_freq = 1333; |
| 703 | break; |
| 704 | case 0x18: |
| 705 | dev_priv->mem_freq = 1600; |
| 706 | break; |
| 707 | default: |
| 708 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", |
| 709 | ddrpll & 0xff); |
| 710 | dev_priv->mem_freq = 0; |
| 711 | break; |
| 712 | } |
| 713 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 714 | dev_priv->ips.r_t = dev_priv->mem_freq; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 715 | |
| 716 | switch (csipll & 0x3ff) { |
| 717 | case 0x00c: |
| 718 | dev_priv->fsb_freq = 3200; |
| 719 | break; |
| 720 | case 0x00e: |
| 721 | dev_priv->fsb_freq = 3733; |
| 722 | break; |
| 723 | case 0x010: |
| 724 | dev_priv->fsb_freq = 4266; |
| 725 | break; |
| 726 | case 0x012: |
| 727 | dev_priv->fsb_freq = 4800; |
| 728 | break; |
| 729 | case 0x014: |
| 730 | dev_priv->fsb_freq = 5333; |
| 731 | break; |
| 732 | case 0x016: |
| 733 | dev_priv->fsb_freq = 5866; |
| 734 | break; |
| 735 | case 0x018: |
| 736 | dev_priv->fsb_freq = 6400; |
| 737 | break; |
| 738 | default: |
| 739 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", |
| 740 | csipll & 0x3ff); |
| 741 | dev_priv->fsb_freq = 0; |
| 742 | break; |
| 743 | } |
| 744 | |
| 745 | if (dev_priv->fsb_freq == 3200) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 746 | dev_priv->ips.c_m = 0; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 747 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 748 | dev_priv->ips.c_m = 1; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 749 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 750 | dev_priv->ips.c_m = 2; |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 751 | } |
| 752 | } |
| 753 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 754 | static const struct cxsr_latency cxsr_latency_table[] = { |
| 755 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ |
| 756 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ |
| 757 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ |
| 758 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ |
| 759 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ |
| 760 | |
| 761 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ |
| 762 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ |
| 763 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ |
| 764 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ |
| 765 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ |
| 766 | |
| 767 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ |
| 768 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ |
| 769 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ |
| 770 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ |
| 771 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ |
| 772 | |
| 773 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ |
| 774 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ |
| 775 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ |
| 776 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ |
| 777 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ |
| 778 | |
| 779 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ |
| 780 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ |
| 781 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ |
| 782 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ |
| 783 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ |
| 784 | |
| 785 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ |
| 786 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ |
| 787 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ |
| 788 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ |
| 789 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ |
| 790 | }; |
| 791 | |
Daniel Vetter | 63c6227 | 2012-04-21 23:17:55 +0200 | [diff] [blame] | 792 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 793 | int is_ddr3, |
| 794 | int fsb, |
| 795 | int mem) |
| 796 | { |
| 797 | const struct cxsr_latency *latency; |
| 798 | int i; |
| 799 | |
| 800 | if (fsb == 0 || mem == 0) |
| 801 | return NULL; |
| 802 | |
| 803 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { |
| 804 | latency = &cxsr_latency_table[i]; |
| 805 | if (is_desktop == latency->is_desktop && |
| 806 | is_ddr3 == latency->is_ddr3 && |
| 807 | fsb == latency->fsb_freq && mem == latency->mem_freq) |
| 808 | return latency; |
| 809 | } |
| 810 | |
| 811 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
| 812 | |
| 813 | return NULL; |
| 814 | } |
| 815 | |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 816 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 817 | { |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 818 | struct drm_device *dev = dev_priv->dev; |
| 819 | u32 val; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 820 | |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 821 | if (IS_VALLEYVIEW(dev)) { |
| 822 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); |
| 823 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { |
| 824 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); |
| 825 | } else if (IS_PINEVIEW(dev)) { |
| 826 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; |
| 827 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; |
| 828 | I915_WRITE(DSPFW3, val); |
| 829 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { |
| 830 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : |
| 831 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); |
| 832 | I915_WRITE(FW_BLC_SELF, val); |
| 833 | } else if (IS_I915GM(dev)) { |
| 834 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : |
| 835 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); |
| 836 | I915_WRITE(INSTPM, val); |
| 837 | } else { |
| 838 | return; |
| 839 | } |
| 840 | |
| 841 | DRM_DEBUG_KMS("memory self-refresh is %s\n", |
| 842 | enable ? "enabled" : "disabled"); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 843 | } |
| 844 | |
| 845 | /* |
| 846 | * Latency for FIFO fetches is dependent on several factors: |
| 847 | * - memory configuration (speed, channels) |
| 848 | * - chipset |
| 849 | * - current MCH state |
| 850 | * It can be fairly high in some situations, so here we assume a fairly |
| 851 | * pessimal value. It's a tradeoff between extra memory fetches (if we |
| 852 | * set this value too high, the FIFO will fetch frequently to stay full) |
| 853 | * and power consumption (set it too low to save power and we might see |
| 854 | * FIFO underruns and display "flicker"). |
| 855 | * |
| 856 | * A value of 5us seems to be a good balance; safe for very low end |
| 857 | * platforms but not overly aggressive on lower latency configs. |
| 858 | */ |
| 859 | static const int latency_ns = 5000; |
| 860 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 861 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 862 | { |
| 863 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 864 | uint32_t dsparb = I915_READ(DSPARB); |
| 865 | int size; |
| 866 | |
| 867 | size = dsparb & 0x7f; |
| 868 | if (plane) |
| 869 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; |
| 870 | |
| 871 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 872 | plane ? "B" : "A", size); |
| 873 | |
| 874 | return size; |
| 875 | } |
| 876 | |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 877 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 878 | { |
| 879 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 880 | uint32_t dsparb = I915_READ(DSPARB); |
| 881 | int size; |
| 882 | |
| 883 | size = dsparb & 0x1ff; |
| 884 | if (plane) |
| 885 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; |
| 886 | size >>= 1; /* Convert to cachelines */ |
| 887 | |
| 888 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 889 | plane ? "B" : "A", size); |
| 890 | |
| 891 | return size; |
| 892 | } |
| 893 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 894 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 895 | { |
| 896 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 897 | uint32_t dsparb = I915_READ(DSPARB); |
| 898 | int size; |
| 899 | |
| 900 | size = dsparb & 0x7f; |
| 901 | size >>= 2; /* Convert to cachelines */ |
| 902 | |
| 903 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, |
| 904 | plane ? "B" : "A", |
| 905 | size); |
| 906 | |
| 907 | return size; |
| 908 | } |
| 909 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 910 | /* Pineview has different values for various configs */ |
| 911 | static const struct intel_watermark_params pineview_display_wm = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 912 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
| 913 | .max_wm = PINEVIEW_MAX_WM, |
| 914 | .default_wm = PINEVIEW_DFT_WM, |
| 915 | .guard_size = PINEVIEW_GUARD_WM, |
| 916 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 917 | }; |
| 918 | static const struct intel_watermark_params pineview_display_hplloff_wm = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 919 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
| 920 | .max_wm = PINEVIEW_MAX_WM, |
| 921 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, |
| 922 | .guard_size = PINEVIEW_GUARD_WM, |
| 923 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 924 | }; |
| 925 | static const struct intel_watermark_params pineview_cursor_wm = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 926 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
| 927 | .max_wm = PINEVIEW_CURSOR_MAX_WM, |
| 928 | .default_wm = PINEVIEW_CURSOR_DFT_WM, |
| 929 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, |
| 930 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 931 | }; |
| 932 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 933 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
| 934 | .max_wm = PINEVIEW_CURSOR_MAX_WM, |
| 935 | .default_wm = PINEVIEW_CURSOR_DFT_WM, |
| 936 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, |
| 937 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 938 | }; |
| 939 | static const struct intel_watermark_params g4x_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 940 | .fifo_size = G4X_FIFO_SIZE, |
| 941 | .max_wm = G4X_MAX_WM, |
| 942 | .default_wm = G4X_MAX_WM, |
| 943 | .guard_size = 2, |
| 944 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 945 | }; |
| 946 | static const struct intel_watermark_params g4x_cursor_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 947 | .fifo_size = I965_CURSOR_FIFO, |
| 948 | .max_wm = I965_CURSOR_MAX_WM, |
| 949 | .default_wm = I965_CURSOR_DFT_WM, |
| 950 | .guard_size = 2, |
| 951 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 952 | }; |
| 953 | static const struct intel_watermark_params valleyview_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 954 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
| 955 | .max_wm = VALLEYVIEW_MAX_WM, |
| 956 | .default_wm = VALLEYVIEW_MAX_WM, |
| 957 | .guard_size = 2, |
| 958 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 959 | }; |
| 960 | static const struct intel_watermark_params valleyview_cursor_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 961 | .fifo_size = I965_CURSOR_FIFO, |
| 962 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, |
| 963 | .default_wm = I965_CURSOR_DFT_WM, |
| 964 | .guard_size = 2, |
| 965 | .cacheline_size = G4X_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 966 | }; |
| 967 | static const struct intel_watermark_params i965_cursor_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 968 | .fifo_size = I965_CURSOR_FIFO, |
| 969 | .max_wm = I965_CURSOR_MAX_WM, |
| 970 | .default_wm = I965_CURSOR_DFT_WM, |
| 971 | .guard_size = 2, |
| 972 | .cacheline_size = I915_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 973 | }; |
| 974 | static const struct intel_watermark_params i945_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 975 | .fifo_size = I945_FIFO_SIZE, |
| 976 | .max_wm = I915_MAX_WM, |
| 977 | .default_wm = 1, |
| 978 | .guard_size = 2, |
| 979 | .cacheline_size = I915_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 980 | }; |
| 981 | static const struct intel_watermark_params i915_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 982 | .fifo_size = I915_FIFO_SIZE, |
| 983 | .max_wm = I915_MAX_WM, |
| 984 | .default_wm = 1, |
| 985 | .guard_size = 2, |
| 986 | .cacheline_size = I915_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 987 | }; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 988 | static const struct intel_watermark_params i830_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 989 | .fifo_size = I855GM_FIFO_SIZE, |
| 990 | .max_wm = I915_MAX_WM, |
| 991 | .default_wm = 1, |
| 992 | .guard_size = 2, |
| 993 | .cacheline_size = I830_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 994 | }; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 995 | static const struct intel_watermark_params i845_wm_info = { |
Ville Syrjälä | e0f0273 | 2014-06-05 19:15:50 +0300 | [diff] [blame] | 996 | .fifo_size = I830_FIFO_SIZE, |
| 997 | .max_wm = I915_MAX_WM, |
| 998 | .default_wm = 1, |
| 999 | .guard_size = 2, |
| 1000 | .cacheline_size = I830_FIFO_LINE_SIZE, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1001 | }; |
| 1002 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1003 | /** |
| 1004 | * intel_calculate_wm - calculate watermark level |
| 1005 | * @clock_in_khz: pixel clock |
| 1006 | * @wm: chip FIFO params |
| 1007 | * @pixel_size: display pixel size |
| 1008 | * @latency_ns: memory latency for the platform |
| 1009 | * |
| 1010 | * Calculate the watermark level (the level at which the display plane will |
| 1011 | * start fetching from memory again). Each chip has a different display |
| 1012 | * FIFO size and allocation, so the caller needs to figure that out and pass |
| 1013 | * in the correct intel_watermark_params structure. |
| 1014 | * |
| 1015 | * As the pixel clock runs, the FIFO will be drained at a rate that depends |
| 1016 | * on the pixel size. When it reaches the watermark level, it'll start |
| 1017 | * fetching FIFO line sized based chunks from memory until the FIFO fills |
| 1018 | * past the watermark point. If the FIFO drains completely, a FIFO underrun |
| 1019 | * will occur, and a display engine hang could result. |
| 1020 | */ |
| 1021 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, |
| 1022 | const struct intel_watermark_params *wm, |
| 1023 | int fifo_size, |
| 1024 | int pixel_size, |
| 1025 | unsigned long latency_ns) |
| 1026 | { |
| 1027 | long entries_required, wm_size; |
| 1028 | |
| 1029 | /* |
| 1030 | * Note: we need to make sure we don't overflow for various clock & |
| 1031 | * latency values. |
| 1032 | * clocks go from a few thousand to several hundred thousand. |
| 1033 | * latency is usually a few thousand |
| 1034 | */ |
| 1035 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / |
| 1036 | 1000; |
| 1037 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); |
| 1038 | |
| 1039 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); |
| 1040 | |
| 1041 | wm_size = fifo_size - (entries_required + wm->guard_size); |
| 1042 | |
| 1043 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); |
| 1044 | |
| 1045 | /* Don't promote wm_size to unsigned... */ |
| 1046 | if (wm_size > (long)wm->max_wm) |
| 1047 | wm_size = wm->max_wm; |
| 1048 | if (wm_size <= 0) |
| 1049 | wm_size = wm->default_wm; |
| 1050 | return wm_size; |
| 1051 | } |
| 1052 | |
| 1053 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) |
| 1054 | { |
| 1055 | struct drm_crtc *crtc, *enabled = NULL; |
| 1056 | |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 1057 | for_each_crtc(dev, crtc) { |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1058 | if (intel_crtc_active(crtc)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1059 | if (enabled) |
| 1060 | return NULL; |
| 1061 | enabled = crtc; |
| 1062 | } |
| 1063 | } |
| 1064 | |
| 1065 | return enabled; |
| 1066 | } |
| 1067 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1068 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1069 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1070 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1071 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1072 | struct drm_crtc *crtc; |
| 1073 | const struct cxsr_latency *latency; |
| 1074 | u32 reg; |
| 1075 | unsigned long wm; |
| 1076 | |
| 1077 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, |
| 1078 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 1079 | if (!latency) { |
| 1080 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1081 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1082 | return; |
| 1083 | } |
| 1084 | |
| 1085 | crtc = single_enabled_crtc(dev); |
| 1086 | if (crtc) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1087 | const struct drm_display_mode *adjusted_mode; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1088 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1089 | int clock; |
| 1090 | |
| 1091 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
| 1092 | clock = adjusted_mode->crtc_clock; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1093 | |
| 1094 | /* Display SR */ |
| 1095 | wm = intel_calculate_wm(clock, &pineview_display_wm, |
| 1096 | pineview_display_wm.fifo_size, |
| 1097 | pixel_size, latency->display_sr); |
| 1098 | reg = I915_READ(DSPFW1); |
| 1099 | reg &= ~DSPFW_SR_MASK; |
| 1100 | reg |= wm << DSPFW_SR_SHIFT; |
| 1101 | I915_WRITE(DSPFW1, reg); |
| 1102 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); |
| 1103 | |
| 1104 | /* cursor SR */ |
| 1105 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, |
| 1106 | pineview_display_wm.fifo_size, |
| 1107 | pixel_size, latency->cursor_sr); |
| 1108 | reg = I915_READ(DSPFW3); |
| 1109 | reg &= ~DSPFW_CURSOR_SR_MASK; |
| 1110 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; |
| 1111 | I915_WRITE(DSPFW3, reg); |
| 1112 | |
| 1113 | /* Display HPLL off SR */ |
| 1114 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, |
| 1115 | pineview_display_hplloff_wm.fifo_size, |
| 1116 | pixel_size, latency->display_hpll_disable); |
| 1117 | reg = I915_READ(DSPFW3); |
| 1118 | reg &= ~DSPFW_HPLL_SR_MASK; |
| 1119 | reg |= wm & DSPFW_HPLL_SR_MASK; |
| 1120 | I915_WRITE(DSPFW3, reg); |
| 1121 | |
| 1122 | /* cursor HPLL off SR */ |
| 1123 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, |
| 1124 | pineview_display_hplloff_wm.fifo_size, |
| 1125 | pixel_size, latency->cursor_hpll_disable); |
| 1126 | reg = I915_READ(DSPFW3); |
| 1127 | reg &= ~DSPFW_HPLL_CURSOR_MASK; |
| 1128 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; |
| 1129 | I915_WRITE(DSPFW3, reg); |
| 1130 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); |
| 1131 | |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1132 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1133 | } else { |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1134 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1135 | } |
| 1136 | } |
| 1137 | |
| 1138 | static bool g4x_compute_wm0(struct drm_device *dev, |
| 1139 | int plane, |
| 1140 | const struct intel_watermark_params *display, |
| 1141 | int display_latency_ns, |
| 1142 | const struct intel_watermark_params *cursor, |
| 1143 | int cursor_latency_ns, |
| 1144 | int *plane_wm, |
| 1145 | int *cursor_wm) |
| 1146 | { |
| 1147 | struct drm_crtc *crtc; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1148 | const struct drm_display_mode *adjusted_mode; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1149 | int htotal, hdisplay, clock, pixel_size; |
| 1150 | int line_time_us, line_count; |
| 1151 | int entries, tlb_miss; |
| 1152 | |
| 1153 | crtc = intel_get_crtc_for_plane(dev, plane); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1154 | if (!intel_crtc_active(crtc)) { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1155 | *cursor_wm = cursor->guard_size; |
| 1156 | *plane_wm = display->guard_size; |
| 1157 | return false; |
| 1158 | } |
| 1159 | |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1160 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1161 | clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1162 | htotal = adjusted_mode->crtc_htotal; |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 1163 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1164 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1165 | |
| 1166 | /* Use the small buffer method to calculate plane watermark */ |
| 1167 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; |
| 1168 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; |
| 1169 | if (tlb_miss > 0) |
| 1170 | entries += tlb_miss; |
| 1171 | entries = DIV_ROUND_UP(entries, display->cacheline_size); |
| 1172 | *plane_wm = entries + display->guard_size; |
| 1173 | if (*plane_wm > (int)display->max_wm) |
| 1174 | *plane_wm = display->max_wm; |
| 1175 | |
| 1176 | /* Use the large buffer method to calculate cursor watermark */ |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 1177 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1178 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
Chris Wilson | 7bb836d | 2014-03-26 12:38:14 +0000 | [diff] [blame] | 1179 | entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1180 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
| 1181 | if (tlb_miss > 0) |
| 1182 | entries += tlb_miss; |
| 1183 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 1184 | *cursor_wm = entries + cursor->guard_size; |
| 1185 | if (*cursor_wm > (int)cursor->max_wm) |
| 1186 | *cursor_wm = (int)cursor->max_wm; |
| 1187 | |
| 1188 | return true; |
| 1189 | } |
| 1190 | |
| 1191 | /* |
| 1192 | * Check the wm result. |
| 1193 | * |
| 1194 | * If any calculated watermark values is larger than the maximum value that |
| 1195 | * can be programmed into the associated watermark register, that watermark |
| 1196 | * must be disabled. |
| 1197 | */ |
| 1198 | static bool g4x_check_srwm(struct drm_device *dev, |
| 1199 | int display_wm, int cursor_wm, |
| 1200 | const struct intel_watermark_params *display, |
| 1201 | const struct intel_watermark_params *cursor) |
| 1202 | { |
| 1203 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", |
| 1204 | display_wm, cursor_wm); |
| 1205 | |
| 1206 | if (display_wm > display->max_wm) { |
| 1207 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", |
| 1208 | display_wm, display->max_wm); |
| 1209 | return false; |
| 1210 | } |
| 1211 | |
| 1212 | if (cursor_wm > cursor->max_wm) { |
| 1213 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", |
| 1214 | cursor_wm, cursor->max_wm); |
| 1215 | return false; |
| 1216 | } |
| 1217 | |
| 1218 | if (!(display_wm || cursor_wm)) { |
| 1219 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); |
| 1220 | return false; |
| 1221 | } |
| 1222 | |
| 1223 | return true; |
| 1224 | } |
| 1225 | |
| 1226 | static bool g4x_compute_srwm(struct drm_device *dev, |
| 1227 | int plane, |
| 1228 | int latency_ns, |
| 1229 | const struct intel_watermark_params *display, |
| 1230 | const struct intel_watermark_params *cursor, |
| 1231 | int *display_wm, int *cursor_wm) |
| 1232 | { |
| 1233 | struct drm_crtc *crtc; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1234 | const struct drm_display_mode *adjusted_mode; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1235 | int hdisplay, htotal, pixel_size, clock; |
| 1236 | unsigned long line_time_us; |
| 1237 | int line_count, line_size; |
| 1238 | int small, large; |
| 1239 | int entries; |
| 1240 | |
| 1241 | if (!latency_ns) { |
| 1242 | *display_wm = *cursor_wm = 0; |
| 1243 | return false; |
| 1244 | } |
| 1245 | |
| 1246 | crtc = intel_get_crtc_for_plane(dev, plane); |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1247 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1248 | clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1249 | htotal = adjusted_mode->crtc_htotal; |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 1250 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1251 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1252 | |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 1253 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1254 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
| 1255 | line_size = hdisplay * pixel_size; |
| 1256 | |
| 1257 | /* Use the minimum of the small and large buffer method for primary */ |
| 1258 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; |
| 1259 | large = line_count * line_size; |
| 1260 | |
| 1261 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); |
| 1262 | *display_wm = entries + display->guard_size; |
| 1263 | |
| 1264 | /* calculate the self-refresh watermark for display cursor */ |
Chris Wilson | 7bb836d | 2014-03-26 12:38:14 +0000 | [diff] [blame] | 1265 | entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1266 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
| 1267 | *cursor_wm = entries + cursor->guard_size; |
| 1268 | |
| 1269 | return g4x_check_srwm(dev, |
| 1270 | *display_wm, *cursor_wm, |
| 1271 | display, cursor); |
| 1272 | } |
| 1273 | |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 1274 | static bool vlv_compute_drain_latency(struct drm_crtc *crtc, |
| 1275 | int pixel_size, |
| 1276 | int *prec_mult, |
| 1277 | int *drain_latency) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1278 | { |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1279 | int entries; |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 1280 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1281 | |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 1282 | if (WARN(clock == 0, "Pixel clock is zero!\n")) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1283 | return false; |
| 1284 | |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 1285 | if (WARN(pixel_size == 0, "Pixel size is zero!\n")) |
| 1286 | return false; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1287 | |
Gajanan Bhat | a398e9c | 2014-08-05 23:15:54 +0530 | [diff] [blame] | 1288 | entries = DIV_ROUND_UP(clock, 1000) * pixel_size; |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 1289 | *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 : |
| 1290 | DRAIN_LATENCY_PRECISION_32; |
| 1291 | *drain_latency = (64 * (*prec_mult) * 4) / entries; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1292 | |
Gajanan Bhat | a398e9c | 2014-08-05 23:15:54 +0530 | [diff] [blame] | 1293 | if (*drain_latency > DRAIN_LATENCY_MASK) |
| 1294 | *drain_latency = DRAIN_LATENCY_MASK; |
| 1295 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1296 | return true; |
| 1297 | } |
| 1298 | |
| 1299 | /* |
| 1300 | * Update drain latency registers of memory arbiter |
| 1301 | * |
| 1302 | * Valleyview SoC has a new memory arbiter and needs drain latency registers |
| 1303 | * to be programmed. Each plane has a drain latency multiplier and a drain |
| 1304 | * latency value. |
| 1305 | */ |
| 1306 | |
Gajanan Bhat | 41aad81 | 2014-07-16 18:24:03 +0530 | [diff] [blame] | 1307 | static void vlv_update_drain_latency(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1308 | { |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 1309 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
| 1310 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 1311 | int pixel_size; |
| 1312 | int drain_latency; |
| 1313 | enum pipe pipe = intel_crtc->pipe; |
| 1314 | int plane_prec, prec_mult, plane_dl; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1315 | |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 1316 | plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_64 | |
| 1317 | DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_64 | |
| 1318 | (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1319 | |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 1320 | if (!intel_crtc_active(crtc)) { |
| 1321 | I915_WRITE(VLV_DDL(pipe), plane_dl); |
| 1322 | return; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1323 | } |
Gajanan Bhat | 0948c26 | 2014-08-07 01:58:24 +0530 | [diff] [blame] | 1324 | |
| 1325 | /* Primary plane Drain Latency */ |
| 1326 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */ |
| 1327 | if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) { |
| 1328 | plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ? |
| 1329 | DDL_PLANE_PRECISION_64 : |
| 1330 | DDL_PLANE_PRECISION_32; |
| 1331 | plane_dl |= plane_prec | drain_latency; |
| 1332 | } |
| 1333 | |
| 1334 | /* Cursor Drain Latency |
| 1335 | * BPP is always 4 for cursor |
| 1336 | */ |
| 1337 | pixel_size = 4; |
| 1338 | |
| 1339 | /* Program cursor DL only if it is enabled */ |
| 1340 | if (intel_crtc->cursor_base && |
| 1341 | vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) { |
| 1342 | plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ? |
| 1343 | DDL_CURSOR_PRECISION_64 : |
| 1344 | DDL_CURSOR_PRECISION_32; |
| 1345 | plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT); |
| 1346 | } |
| 1347 | |
| 1348 | I915_WRITE(VLV_DDL(pipe), plane_dl); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1349 | } |
| 1350 | |
| 1351 | #define single_plane_enabled(mask) is_power_of_2(mask) |
| 1352 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1353 | static void valleyview_update_wm(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1354 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1355 | struct drm_device *dev = crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1356 | static const int sr_latency_ns = 12000; |
| 1357 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1358 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
| 1359 | int plane_sr, cursor_sr; |
Chris Wilson | af6c457 | 2012-12-11 12:01:43 +0000 | [diff] [blame] | 1360 | int ignore_plane_sr, ignore_cursor_sr; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1361 | unsigned int enabled = 0; |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1362 | bool cxsr_enabled; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1363 | |
Gajanan Bhat | 41aad81 | 2014-07-16 18:24:03 +0530 | [diff] [blame] | 1364 | vlv_update_drain_latency(crtc); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1365 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1366 | if (g4x_compute_wm0(dev, PIPE_A, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1367 | &valleyview_wm_info, latency_ns, |
| 1368 | &valleyview_cursor_wm_info, latency_ns, |
| 1369 | &planea_wm, &cursora_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1370 | enabled |= 1 << PIPE_A; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1371 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1372 | if (g4x_compute_wm0(dev, PIPE_B, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1373 | &valleyview_wm_info, latency_ns, |
| 1374 | &valleyview_cursor_wm_info, latency_ns, |
| 1375 | &planeb_wm, &cursorb_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1376 | enabled |= 1 << PIPE_B; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1377 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1378 | if (single_plane_enabled(enabled) && |
| 1379 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1380 | sr_latency_ns, |
| 1381 | &valleyview_wm_info, |
| 1382 | &valleyview_cursor_wm_info, |
Chris Wilson | af6c457 | 2012-12-11 12:01:43 +0000 | [diff] [blame] | 1383 | &plane_sr, &ignore_cursor_sr) && |
| 1384 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1385 | 2*sr_latency_ns, |
| 1386 | &valleyview_wm_info, |
| 1387 | &valleyview_cursor_wm_info, |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1388 | &ignore_plane_sr, &cursor_sr)) { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1389 | cxsr_enabled = true; |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1390 | } else { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1391 | cxsr_enabled = false; |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1392 | intel_set_memory_cxsr(dev_priv, false); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1393 | plane_sr = cursor_sr = 0; |
| 1394 | } |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1395 | |
Ville Syrjälä | a504345 | 2014-06-28 02:04:18 +0300 | [diff] [blame] | 1396 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
| 1397 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1398 | planea_wm, cursora_wm, |
| 1399 | planeb_wm, cursorb_wm, |
| 1400 | plane_sr, cursor_sr); |
| 1401 | |
| 1402 | I915_WRITE(DSPFW1, |
| 1403 | (plane_sr << DSPFW_SR_SHIFT) | |
| 1404 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 1405 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 1406 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1407 | I915_WRITE(DSPFW2, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1408 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1409 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 1410 | I915_WRITE(DSPFW3, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1411 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
| 1412 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1413 | |
| 1414 | if (cxsr_enabled) |
| 1415 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1416 | } |
| 1417 | |
Ville Syrjälä | 3c2777f | 2014-06-26 17:03:06 +0300 | [diff] [blame] | 1418 | static void cherryview_update_wm(struct drm_crtc *crtc) |
| 1419 | { |
| 1420 | struct drm_device *dev = crtc->dev; |
| 1421 | static const int sr_latency_ns = 12000; |
| 1422 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1423 | int planea_wm, planeb_wm, planec_wm; |
| 1424 | int cursora_wm, cursorb_wm, cursorc_wm; |
| 1425 | int plane_sr, cursor_sr; |
| 1426 | int ignore_plane_sr, ignore_cursor_sr; |
| 1427 | unsigned int enabled = 0; |
| 1428 | bool cxsr_enabled; |
| 1429 | |
| 1430 | vlv_update_drain_latency(crtc); |
| 1431 | |
| 1432 | if (g4x_compute_wm0(dev, PIPE_A, |
| 1433 | &valleyview_wm_info, latency_ns, |
| 1434 | &valleyview_cursor_wm_info, latency_ns, |
| 1435 | &planea_wm, &cursora_wm)) |
| 1436 | enabled |= 1 << PIPE_A; |
| 1437 | |
| 1438 | if (g4x_compute_wm0(dev, PIPE_B, |
| 1439 | &valleyview_wm_info, latency_ns, |
| 1440 | &valleyview_cursor_wm_info, latency_ns, |
| 1441 | &planeb_wm, &cursorb_wm)) |
| 1442 | enabled |= 1 << PIPE_B; |
| 1443 | |
| 1444 | if (g4x_compute_wm0(dev, PIPE_C, |
| 1445 | &valleyview_wm_info, latency_ns, |
| 1446 | &valleyview_cursor_wm_info, latency_ns, |
| 1447 | &planec_wm, &cursorc_wm)) |
| 1448 | enabled |= 1 << PIPE_C; |
| 1449 | |
| 1450 | if (single_plane_enabled(enabled) && |
| 1451 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1452 | sr_latency_ns, |
| 1453 | &valleyview_wm_info, |
| 1454 | &valleyview_cursor_wm_info, |
| 1455 | &plane_sr, &ignore_cursor_sr) && |
| 1456 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1457 | 2*sr_latency_ns, |
| 1458 | &valleyview_wm_info, |
| 1459 | &valleyview_cursor_wm_info, |
| 1460 | &ignore_plane_sr, &cursor_sr)) { |
| 1461 | cxsr_enabled = true; |
| 1462 | } else { |
| 1463 | cxsr_enabled = false; |
| 1464 | intel_set_memory_cxsr(dev_priv, false); |
| 1465 | plane_sr = cursor_sr = 0; |
| 1466 | } |
| 1467 | |
| 1468 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
| 1469 | "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, " |
| 1470 | "SR: plane=%d, cursor=%d\n", |
| 1471 | planea_wm, cursora_wm, |
| 1472 | planeb_wm, cursorb_wm, |
| 1473 | planec_wm, cursorc_wm, |
| 1474 | plane_sr, cursor_sr); |
| 1475 | |
| 1476 | I915_WRITE(DSPFW1, |
| 1477 | (plane_sr << DSPFW_SR_SHIFT) | |
| 1478 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 1479 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
| 1480 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
| 1481 | I915_WRITE(DSPFW2, |
| 1482 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
| 1483 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 1484 | I915_WRITE(DSPFW3, |
| 1485 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
| 1486 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
| 1487 | I915_WRITE(DSPFW9_CHV, |
| 1488 | (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK | |
| 1489 | DSPFW_CURSORC_MASK)) | |
| 1490 | (planec_wm << DSPFW_PLANEC_SHIFT) | |
| 1491 | (cursorc_wm << DSPFW_CURSORC_SHIFT)); |
| 1492 | |
| 1493 | if (cxsr_enabled) |
| 1494 | intel_set_memory_cxsr(dev_priv, true); |
| 1495 | } |
| 1496 | |
Gajanan Bhat | 01e184c | 2014-08-07 17:03:30 +0530 | [diff] [blame^] | 1497 | static void valleyview_update_sprite_wm(struct drm_plane *plane, |
| 1498 | struct drm_crtc *crtc, |
| 1499 | uint32_t sprite_width, |
| 1500 | uint32_t sprite_height, |
| 1501 | int pixel_size, |
| 1502 | bool enabled, bool scaled) |
| 1503 | { |
| 1504 | struct drm_device *dev = crtc->dev; |
| 1505 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1506 | int pipe = to_intel_plane(plane)->pipe; |
| 1507 | int sprite = to_intel_plane(plane)->plane; |
| 1508 | int drain_latency; |
| 1509 | int plane_prec; |
| 1510 | int sprite_dl; |
| 1511 | int prec_mult; |
| 1512 | |
| 1513 | sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_64(sprite) | |
| 1514 | (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite))); |
| 1515 | |
| 1516 | if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, |
| 1517 | &drain_latency)) { |
| 1518 | plane_prec = (prec_mult == DRAIN_LATENCY_PRECISION_64) ? |
| 1519 | DDL_SPRITE_PRECISION_64(sprite) : |
| 1520 | DDL_SPRITE_PRECISION_32(sprite); |
| 1521 | sprite_dl |= plane_prec | |
| 1522 | (drain_latency << DDL_SPRITE_SHIFT(sprite)); |
| 1523 | } |
| 1524 | |
| 1525 | I915_WRITE(VLV_DDL(pipe), sprite_dl); |
| 1526 | } |
| 1527 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1528 | static void g4x_update_wm(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1529 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1530 | struct drm_device *dev = crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1531 | static const int sr_latency_ns = 12000; |
| 1532 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1533 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; |
| 1534 | int plane_sr, cursor_sr; |
| 1535 | unsigned int enabled = 0; |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1536 | bool cxsr_enabled; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1537 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1538 | if (g4x_compute_wm0(dev, PIPE_A, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1539 | &g4x_wm_info, latency_ns, |
| 1540 | &g4x_cursor_wm_info, latency_ns, |
| 1541 | &planea_wm, &cursora_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1542 | enabled |= 1 << PIPE_A; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1543 | |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1544 | if (g4x_compute_wm0(dev, PIPE_B, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1545 | &g4x_wm_info, latency_ns, |
| 1546 | &g4x_cursor_wm_info, latency_ns, |
| 1547 | &planeb_wm, &cursorb_wm)) |
Ville Syrjälä | 51cea1f | 2013-03-21 13:10:44 +0200 | [diff] [blame] | 1548 | enabled |= 1 << PIPE_B; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1549 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1550 | if (single_plane_enabled(enabled) && |
| 1551 | g4x_compute_srwm(dev, ffs(enabled) - 1, |
| 1552 | sr_latency_ns, |
| 1553 | &g4x_wm_info, |
| 1554 | &g4x_cursor_wm_info, |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1555 | &plane_sr, &cursor_sr)) { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1556 | cxsr_enabled = true; |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1557 | } else { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1558 | cxsr_enabled = false; |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1559 | intel_set_memory_cxsr(dev_priv, false); |
Chris Wilson | 52bd02d | 2012-12-07 10:43:24 +0000 | [diff] [blame] | 1560 | plane_sr = cursor_sr = 0; |
| 1561 | } |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1562 | |
Ville Syrjälä | a504345 | 2014-06-28 02:04:18 +0300 | [diff] [blame] | 1563 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
| 1564 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1565 | planea_wm, cursora_wm, |
| 1566 | planeb_wm, cursorb_wm, |
| 1567 | plane_sr, cursor_sr); |
| 1568 | |
| 1569 | I915_WRITE(DSPFW1, |
| 1570 | (plane_sr << DSPFW_SR_SHIFT) | |
| 1571 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | |
| 1572 | (planeb_wm << DSPFW_PLANEB_SHIFT) | |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 1573 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1574 | I915_WRITE(DSPFW2, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1575 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1576 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
| 1577 | /* HPLL off in SR has some issues on G4x... disable it */ |
| 1578 | I915_WRITE(DSPFW3, |
Chris Wilson | 8c919b2 | 2012-12-04 16:33:19 +0000 | [diff] [blame] | 1579 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1580 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1581 | |
| 1582 | if (cxsr_enabled) |
| 1583 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1584 | } |
| 1585 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1586 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1587 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1588 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1589 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1590 | struct drm_crtc *crtc; |
| 1591 | int srwm = 1; |
| 1592 | int cursor_sr = 16; |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1593 | bool cxsr_enabled; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1594 | |
| 1595 | /* Calc sr entries for one plane configs */ |
| 1596 | crtc = single_enabled_crtc(dev); |
| 1597 | if (crtc) { |
| 1598 | /* self-refresh has much higher latency */ |
| 1599 | static const int sr_latency_ns = 12000; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1600 | const struct drm_display_mode *adjusted_mode = |
| 1601 | &to_intel_crtc(crtc)->config.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1602 | int clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1603 | int htotal = adjusted_mode->crtc_htotal; |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 1604 | int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1605 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1606 | unsigned long line_time_us; |
| 1607 | int entries; |
| 1608 | |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 1609 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1610 | |
| 1611 | /* Use ns/us then divide to preserve precision */ |
| 1612 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1613 | pixel_size * hdisplay; |
| 1614 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
| 1615 | srwm = I965_FIFO_SIZE - entries; |
| 1616 | if (srwm < 0) |
| 1617 | srwm = 1; |
| 1618 | srwm &= 0x1ff; |
| 1619 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", |
| 1620 | entries, srwm); |
| 1621 | |
| 1622 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
Chris Wilson | 7bb836d | 2014-03-26 12:38:14 +0000 | [diff] [blame] | 1623 | pixel_size * to_intel_crtc(crtc)->cursor_width; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1624 | entries = DIV_ROUND_UP(entries, |
| 1625 | i965_cursor_wm_info.cacheline_size); |
| 1626 | cursor_sr = i965_cursor_wm_info.fifo_size - |
| 1627 | (entries + i965_cursor_wm_info.guard_size); |
| 1628 | |
| 1629 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
| 1630 | cursor_sr = i965_cursor_wm_info.max_wm; |
| 1631 | |
| 1632 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " |
| 1633 | "cursor %d\n", srwm, cursor_sr); |
| 1634 | |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1635 | cxsr_enabled = true; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1636 | } else { |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1637 | cxsr_enabled = false; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1638 | /* Turn off self refresh if both pipes are enabled */ |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1639 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1640 | } |
| 1641 | |
| 1642 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", |
| 1643 | srwm); |
| 1644 | |
| 1645 | /* 965 has limitations... */ |
| 1646 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | |
Ville Syrjälä | 0a56067 | 2014-06-11 16:51:18 +0300 | [diff] [blame] | 1647 | (8 << DSPFW_CURSORB_SHIFT) | |
| 1648 | (8 << DSPFW_PLANEB_SHIFT) | |
| 1649 | (8 << DSPFW_PLANEA_SHIFT)); |
| 1650 | I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) | |
| 1651 | (8 << DSPFW_PLANEC_SHIFT_OLD)); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1652 | /* update cursor SR watermark */ |
| 1653 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
Imre Deak | 9858425 | 2014-06-13 14:54:20 +0300 | [diff] [blame] | 1654 | |
| 1655 | if (cxsr_enabled) |
| 1656 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1657 | } |
| 1658 | |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1659 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1660 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1661 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1662 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1663 | const struct intel_watermark_params *wm_info; |
| 1664 | uint32_t fwater_lo; |
| 1665 | uint32_t fwater_hi; |
| 1666 | int cwm, srwm = 1; |
| 1667 | int fifo_size; |
| 1668 | int planea_wm, planeb_wm; |
| 1669 | struct drm_crtc *crtc, *enabled = NULL; |
| 1670 | |
| 1671 | if (IS_I945GM(dev)) |
| 1672 | wm_info = &i945_wm_info; |
| 1673 | else if (!IS_GEN2(dev)) |
| 1674 | wm_info = &i915_wm_info; |
| 1675 | else |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 1676 | wm_info = &i830_wm_info; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1677 | |
| 1678 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); |
| 1679 | crtc = intel_get_crtc_for_plane(dev, 0); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1680 | if (intel_crtc_active(crtc)) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1681 | const struct drm_display_mode *adjusted_mode; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1682 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1683 | if (IS_GEN2(dev)) |
| 1684 | cpp = 4; |
| 1685 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1686 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
| 1687 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1688 | wm_info, fifo_size, cpp, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1689 | latency_ns); |
| 1690 | enabled = crtc; |
| 1691 | } else |
| 1692 | planea_wm = fifo_size - wm_info->guard_size; |
| 1693 | |
| 1694 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); |
| 1695 | crtc = intel_get_crtc_for_plane(dev, 1); |
Chris Wilson | 3490ea5 | 2013-01-07 10:11:40 +0000 | [diff] [blame] | 1696 | if (intel_crtc_active(crtc)) { |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1697 | const struct drm_display_mode *adjusted_mode; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1698 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1699 | if (IS_GEN2(dev)) |
| 1700 | cpp = 4; |
| 1701 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1702 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
| 1703 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1704 | wm_info, fifo_size, cpp, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1705 | latency_ns); |
| 1706 | if (enabled == NULL) |
| 1707 | enabled = crtc; |
| 1708 | else |
| 1709 | enabled = NULL; |
| 1710 | } else |
| 1711 | planeb_wm = fifo_size - wm_info->guard_size; |
| 1712 | |
| 1713 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); |
| 1714 | |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1715 | if (IS_I915GM(dev) && enabled) { |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 1716 | struct drm_i915_gem_object *obj; |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1717 | |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 1718 | obj = intel_fb_obj(enabled->primary->fb); |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1719 | |
| 1720 | /* self-refresh seems busted with untiled */ |
Matt Roper | 2ff8fde | 2014-07-08 07:50:07 -0700 | [diff] [blame] | 1721 | if (obj->tiling_mode == I915_TILING_NONE) |
Daniel Vetter | 2ab1bc9 | 2014-04-07 08:54:21 +0200 | [diff] [blame] | 1722 | enabled = NULL; |
| 1723 | } |
| 1724 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1725 | /* |
| 1726 | * Overlay gets an aggressive default since video jitter is bad. |
| 1727 | */ |
| 1728 | cwm = 2; |
| 1729 | |
| 1730 | /* Play safe and disable self-refresh before adjusting watermarks. */ |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1731 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1732 | |
| 1733 | /* Calc sr entries for one plane configs */ |
| 1734 | if (HAS_FW_BLC(dev) && enabled) { |
| 1735 | /* self-refresh has much higher latency */ |
| 1736 | static const int sr_latency_ns = 6000; |
Ville Syrjälä | 4fe8590 | 2013-09-04 18:25:22 +0300 | [diff] [blame] | 1737 | const struct drm_display_mode *adjusted_mode = |
| 1738 | &to_intel_crtc(enabled)->config.adjusted_mode; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1739 | int clock = adjusted_mode->crtc_clock; |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 1740 | int htotal = adjusted_mode->crtc_htotal; |
Daniel Vetter | f727b49 | 2013-11-20 15:02:10 +0100 | [diff] [blame] | 1741 | int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 1742 | int pixel_size = enabled->primary->fb->bits_per_pixel / 8; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1743 | unsigned long line_time_us; |
| 1744 | int entries; |
| 1745 | |
Ville Syrjälä | 922044c | 2014-02-14 14:18:57 +0200 | [diff] [blame] | 1746 | line_time_us = max(htotal * 1000 / clock, 1); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1747 | |
| 1748 | /* Use ns/us then divide to preserve precision */ |
| 1749 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * |
| 1750 | pixel_size * hdisplay; |
| 1751 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
| 1752 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); |
| 1753 | srwm = wm_info->fifo_size - entries; |
| 1754 | if (srwm < 0) |
| 1755 | srwm = 1; |
| 1756 | |
| 1757 | if (IS_I945G(dev) || IS_I945GM(dev)) |
| 1758 | I915_WRITE(FW_BLC_SELF, |
| 1759 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); |
| 1760 | else if (IS_I915GM(dev)) |
| 1761 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
| 1762 | } |
| 1763 | |
| 1764 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", |
| 1765 | planea_wm, planeb_wm, cwm, srwm); |
| 1766 | |
| 1767 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); |
| 1768 | fwater_hi = (cwm & 0x1f); |
| 1769 | |
| 1770 | /* Set request length to 8 cachelines per fetch */ |
| 1771 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); |
| 1772 | fwater_hi = fwater_hi | (1 << 8); |
| 1773 | |
| 1774 | I915_WRITE(FW_BLC, fwater_lo); |
| 1775 | I915_WRITE(FW_BLC2, fwater_hi); |
| 1776 | |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 1777 | if (enabled) |
| 1778 | intel_set_memory_cxsr(dev_priv, true); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1779 | } |
| 1780 | |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 1781 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1782 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 1783 | struct drm_device *dev = unused_crtc->dev; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1784 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1785 | struct drm_crtc *crtc; |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1786 | const struct drm_display_mode *adjusted_mode; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1787 | uint32_t fwater_lo; |
| 1788 | int planea_wm; |
| 1789 | |
| 1790 | crtc = single_enabled_crtc(dev); |
| 1791 | if (crtc == NULL) |
| 1792 | return; |
| 1793 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1794 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
| 1795 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 1796 | &i845_wm_info, |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1797 | dev_priv->display.get_fifo_size(dev, 0), |
Chris Wilson | b9e0bda | 2012-10-22 12:32:15 +0100 | [diff] [blame] | 1798 | 4, latency_ns); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 1799 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
| 1800 | fwater_lo |= (3<<8) | planea_wm; |
| 1801 | |
| 1802 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); |
| 1803 | |
| 1804 | I915_WRITE(FW_BLC, fwater_lo); |
| 1805 | } |
| 1806 | |
Ville Syrjälä | 3658729 | 2013-07-05 11:57:16 +0300 | [diff] [blame] | 1807 | static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, |
| 1808 | struct drm_crtc *crtc) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1809 | { |
| 1810 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 1811 | uint32_t pixel_rate; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1812 | |
Damien Lespiau | 241bfc3 | 2013-09-25 16:45:37 +0100 | [diff] [blame] | 1813 | pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1814 | |
| 1815 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to |
| 1816 | * adjust the pixel_rate here. */ |
| 1817 | |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 1818 | if (intel_crtc->config.pch_pfit.enabled) { |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1819 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
Chris Wilson | fd4daa9 | 2013-08-27 17:04:17 +0100 | [diff] [blame] | 1820 | uint32_t pfit_size = intel_crtc->config.pch_pfit.size; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1821 | |
Ville Syrjälä | 37327ab | 2013-09-04 18:25:28 +0300 | [diff] [blame] | 1822 | pipe_w = intel_crtc->config.pipe_src_w; |
| 1823 | pipe_h = intel_crtc->config.pipe_src_h; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1824 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
| 1825 | pfit_h = pfit_size & 0xFFFF; |
| 1826 | if (pipe_w < pfit_w) |
| 1827 | pipe_w = pfit_w; |
| 1828 | if (pipe_h < pfit_h) |
| 1829 | pipe_h = pfit_h; |
| 1830 | |
| 1831 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, |
| 1832 | pfit_w * pfit_h); |
| 1833 | } |
| 1834 | |
| 1835 | return pixel_rate; |
| 1836 | } |
| 1837 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1838 | /* latency must be in 0.1us units. */ |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1839 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1840 | uint32_t latency) |
| 1841 | { |
| 1842 | uint64_t ret; |
| 1843 | |
Ville Syrjälä | 3312ba6 | 2013-08-01 16:18:53 +0300 | [diff] [blame] | 1844 | if (WARN(latency == 0, "Latency value missing\n")) |
| 1845 | return UINT_MAX; |
| 1846 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1847 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
| 1848 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; |
| 1849 | |
| 1850 | return ret; |
| 1851 | } |
| 1852 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1853 | /* latency must be in 0.1us units. */ |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1854 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1855 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
| 1856 | uint32_t latency) |
| 1857 | { |
| 1858 | uint32_t ret; |
| 1859 | |
Ville Syrjälä | 3312ba6 | 2013-08-01 16:18:53 +0300 | [diff] [blame] | 1860 | if (WARN(latency == 0, "Latency value missing\n")) |
| 1861 | return UINT_MAX; |
| 1862 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1863 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
| 1864 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; |
| 1865 | ret = DIV_ROUND_UP(ret, 64) + 2; |
| 1866 | return ret; |
| 1867 | } |
| 1868 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1869 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1870 | uint8_t bytes_per_pixel) |
| 1871 | { |
| 1872 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; |
| 1873 | } |
| 1874 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1875 | struct ilk_pipe_wm_parameters { |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1876 | bool active; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1877 | uint32_t pipe_htotal; |
| 1878 | uint32_t pixel_rate; |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1879 | struct intel_plane_wm_parameters pri; |
| 1880 | struct intel_plane_wm_parameters spr; |
| 1881 | struct intel_plane_wm_parameters cur; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1882 | }; |
| 1883 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1884 | struct ilk_wm_maximums { |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1885 | uint16_t pri; |
| 1886 | uint16_t spr; |
| 1887 | uint16_t cur; |
| 1888 | uint16_t fbc; |
| 1889 | }; |
| 1890 | |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1891 | /* used in computing the new watermarks state */ |
| 1892 | struct intel_wm_config { |
| 1893 | unsigned int num_pipes_active; |
| 1894 | bool sprites_enabled; |
| 1895 | bool sprites_scaled; |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 1896 | }; |
| 1897 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1898 | /* |
| 1899 | * For both WM_PIPE and WM_LP. |
| 1900 | * mem_value must be in 0.1us units. |
| 1901 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1902 | static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1903 | uint32_t mem_value, |
| 1904 | bool is_lp) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1905 | { |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1906 | uint32_t method1, method2; |
| 1907 | |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1908 | if (!params->active || !params->pri.enabled) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1909 | return 0; |
| 1910 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1911 | method1 = ilk_wm_method1(params->pixel_rate, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1912 | params->pri.bytes_per_pixel, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1913 | mem_value); |
| 1914 | |
| 1915 | if (!is_lp) |
| 1916 | return method1; |
| 1917 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1918 | method2 = ilk_wm_method2(params->pixel_rate, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1919 | params->pipe_htotal, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1920 | params->pri.horiz_pixels, |
| 1921 | params->pri.bytes_per_pixel, |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1922 | mem_value); |
| 1923 | |
| 1924 | return min(method1, method2); |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1925 | } |
| 1926 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1927 | /* |
| 1928 | * For both WM_PIPE and WM_LP. |
| 1929 | * mem_value must be in 0.1us units. |
| 1930 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1931 | static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1932 | uint32_t mem_value) |
| 1933 | { |
| 1934 | uint32_t method1, method2; |
| 1935 | |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1936 | if (!params->active || !params->spr.enabled) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1937 | return 0; |
| 1938 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1939 | method1 = ilk_wm_method1(params->pixel_rate, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1940 | params->spr.bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1941 | mem_value); |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1942 | method2 = ilk_wm_method2(params->pixel_rate, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1943 | params->pipe_htotal, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1944 | params->spr.horiz_pixels, |
| 1945 | params->spr.bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1946 | mem_value); |
| 1947 | return min(method1, method2); |
| 1948 | } |
| 1949 | |
Ville Syrjälä | 3712646 | 2013-08-01 16:18:55 +0300 | [diff] [blame] | 1950 | /* |
| 1951 | * For both WM_PIPE and WM_LP. |
| 1952 | * mem_value must be in 0.1us units. |
| 1953 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1954 | static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1955 | uint32_t mem_value) |
| 1956 | { |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1957 | if (!params->active || !params->cur.enabled) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1958 | return 0; |
| 1959 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1960 | return ilk_wm_method2(params->pixel_rate, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1961 | params->pipe_htotal, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1962 | params->cur.horiz_pixels, |
| 1963 | params->cur.bytes_per_pixel, |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 1964 | mem_value); |
| 1965 | } |
| 1966 | |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1967 | /* Only for WM_LP. */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 1968 | static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, |
Ville Syrjälä | 1fda988 | 2013-07-05 11:57:19 +0300 | [diff] [blame] | 1969 | uint32_t pri_val) |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1970 | { |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1971 | if (!params->active || !params->pri.enabled) |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1972 | return 0; |
| 1973 | |
Ville Syrjälä | 2329704 | 2013-07-05 11:57:17 +0300 | [diff] [blame] | 1974 | return ilk_wm_fbc(pri_val, |
Ville Syrjälä | c35426d | 2013-08-07 13:29:50 +0300 | [diff] [blame] | 1975 | params->pri.horiz_pixels, |
| 1976 | params->pri.bytes_per_pixel); |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 1977 | } |
| 1978 | |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1979 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
| 1980 | { |
Ville Syrjälä | 416f472 | 2013-11-02 21:07:46 -0700 | [diff] [blame] | 1981 | if (INTEL_INFO(dev)->gen >= 8) |
| 1982 | return 3072; |
| 1983 | else if (INTEL_INFO(dev)->gen >= 7) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 1984 | return 768; |
| 1985 | else |
| 1986 | return 512; |
| 1987 | } |
| 1988 | |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 1989 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
| 1990 | int level, bool is_sprite) |
| 1991 | { |
| 1992 | if (INTEL_INFO(dev)->gen >= 8) |
| 1993 | /* BDW primary/sprite plane watermarks */ |
| 1994 | return level == 0 ? 255 : 2047; |
| 1995 | else if (INTEL_INFO(dev)->gen >= 7) |
| 1996 | /* IVB/HSW primary/sprite plane watermarks */ |
| 1997 | return level == 0 ? 127 : 1023; |
| 1998 | else if (!is_sprite) |
| 1999 | /* ILK/SNB primary plane watermarks */ |
| 2000 | return level == 0 ? 127 : 511; |
| 2001 | else |
| 2002 | /* ILK/SNB sprite plane watermarks */ |
| 2003 | return level == 0 ? 63 : 255; |
| 2004 | } |
| 2005 | |
| 2006 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, |
| 2007 | int level) |
| 2008 | { |
| 2009 | if (INTEL_INFO(dev)->gen >= 7) |
| 2010 | return level == 0 ? 63 : 255; |
| 2011 | else |
| 2012 | return level == 0 ? 31 : 63; |
| 2013 | } |
| 2014 | |
| 2015 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) |
| 2016 | { |
| 2017 | if (INTEL_INFO(dev)->gen >= 8) |
| 2018 | return 31; |
| 2019 | else |
| 2020 | return 15; |
| 2021 | } |
| 2022 | |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 2023 | /* Calculate the maximum primary/sprite plane watermark */ |
| 2024 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, |
| 2025 | int level, |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 2026 | const struct intel_wm_config *config, |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 2027 | enum intel_ddb_partitioning ddb_partitioning, |
| 2028 | bool is_sprite) |
| 2029 | { |
| 2030 | unsigned int fifo_size = ilk_display_fifo_size(dev); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 2031 | |
| 2032 | /* if sprites aren't enabled, sprites get nothing */ |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 2033 | if (is_sprite && !config->sprites_enabled) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 2034 | return 0; |
| 2035 | |
| 2036 | /* HSW allows LP1+ watermarks even with multiple pipes */ |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 2037 | if (level == 0 || config->num_pipes_active > 1) { |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 2038 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
| 2039 | |
| 2040 | /* |
| 2041 | * For some reason the non self refresh |
| 2042 | * FIFO size is only half of the self |
| 2043 | * refresh FIFO size on ILK/SNB. |
| 2044 | */ |
| 2045 | if (INTEL_INFO(dev)->gen <= 6) |
| 2046 | fifo_size /= 2; |
| 2047 | } |
| 2048 | |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 2049 | if (config->sprites_enabled) { |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 2050 | /* level 0 is always calculated with 1:1 split */ |
| 2051 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { |
| 2052 | if (is_sprite) |
| 2053 | fifo_size *= 5; |
| 2054 | fifo_size /= 6; |
| 2055 | } else { |
| 2056 | fifo_size /= 2; |
| 2057 | } |
| 2058 | } |
| 2059 | |
| 2060 | /* clamp to max that the registers can hold */ |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 2061 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 2062 | } |
| 2063 | |
| 2064 | /* Calculate the maximum cursor plane watermark */ |
| 2065 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 2066 | int level, |
| 2067 | const struct intel_wm_config *config) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 2068 | { |
| 2069 | /* HSW LP1+ watermarks w/ multiple pipes */ |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 2070 | if (level > 0 && config->num_pipes_active > 1) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 2071 | return 64; |
| 2072 | |
| 2073 | /* otherwise just report max that registers can hold */ |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 2074 | return ilk_cursor_wm_reg_max(dev, level); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 2075 | } |
| 2076 | |
Damien Lespiau | d34ff9c | 2014-01-06 19:17:23 +0000 | [diff] [blame] | 2077 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
Ville Syrjälä | 34982fe | 2013-10-09 19:18:09 +0300 | [diff] [blame] | 2078 | int level, |
| 2079 | const struct intel_wm_config *config, |
| 2080 | enum intel_ddb_partitioning ddb_partitioning, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2081 | struct ilk_wm_maximums *max) |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 2082 | { |
Ville Syrjälä | 240264f | 2013-08-07 13:29:12 +0300 | [diff] [blame] | 2083 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
| 2084 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); |
| 2085 | max->cur = ilk_cursor_wm_max(dev, level, config); |
Ville Syrjälä | 4e97508 | 2014-03-07 18:32:11 +0200 | [diff] [blame] | 2086 | max->fbc = ilk_fbc_wm_reg_max(dev); |
Ville Syrjälä | 158ae64 | 2013-08-07 13:28:19 +0300 | [diff] [blame] | 2087 | } |
| 2088 | |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 2089 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
| 2090 | int level, |
| 2091 | struct ilk_wm_maximums *max) |
| 2092 | { |
| 2093 | max->pri = ilk_plane_wm_reg_max(dev, level, false); |
| 2094 | max->spr = ilk_plane_wm_reg_max(dev, level, true); |
| 2095 | max->cur = ilk_cursor_wm_reg_max(dev, level); |
| 2096 | max->fbc = ilk_fbc_wm_reg_max(dev); |
| 2097 | } |
| 2098 | |
Ville Syrjälä | d939565 | 2013-10-09 19:18:10 +0300 | [diff] [blame] | 2099 | static bool ilk_validate_wm_level(int level, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2100 | const struct ilk_wm_maximums *max, |
Ville Syrjälä | d939565 | 2013-10-09 19:18:10 +0300 | [diff] [blame] | 2101 | struct intel_wm_level *result) |
Ville Syrjälä | a9786a1 | 2013-08-07 13:24:47 +0300 | [diff] [blame] | 2102 | { |
| 2103 | bool ret; |
| 2104 | |
| 2105 | /* already determined to be invalid? */ |
| 2106 | if (!result->enable) |
| 2107 | return false; |
| 2108 | |
| 2109 | result->enable = result->pri_val <= max->pri && |
| 2110 | result->spr_val <= max->spr && |
| 2111 | result->cur_val <= max->cur; |
| 2112 | |
| 2113 | ret = result->enable; |
| 2114 | |
| 2115 | /* |
| 2116 | * HACK until we can pre-compute everything, |
| 2117 | * and thus fail gracefully if LP0 watermarks |
| 2118 | * are exceeded... |
| 2119 | */ |
| 2120 | if (level == 0 && !result->enable) { |
| 2121 | if (result->pri_val > max->pri) |
| 2122 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", |
| 2123 | level, result->pri_val, max->pri); |
| 2124 | if (result->spr_val > max->spr) |
| 2125 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", |
| 2126 | level, result->spr_val, max->spr); |
| 2127 | if (result->cur_val > max->cur) |
| 2128 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", |
| 2129 | level, result->cur_val, max->cur); |
| 2130 | |
| 2131 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); |
| 2132 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); |
| 2133 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); |
| 2134 | result->enable = true; |
| 2135 | } |
| 2136 | |
Ville Syrjälä | a9786a1 | 2013-08-07 13:24:47 +0300 | [diff] [blame] | 2137 | return ret; |
| 2138 | } |
| 2139 | |
Damien Lespiau | d34ff9c | 2014-01-06 19:17:23 +0000 | [diff] [blame] | 2140 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
Ville Syrjälä | 6f5ddd1 | 2013-08-06 22:24:02 +0300 | [diff] [blame] | 2141 | int level, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2142 | const struct ilk_pipe_wm_parameters *p, |
Ville Syrjälä | 1fd527c | 2013-08-06 22:24:05 +0300 | [diff] [blame] | 2143 | struct intel_wm_level *result) |
Ville Syrjälä | 6f5ddd1 | 2013-08-06 22:24:02 +0300 | [diff] [blame] | 2144 | { |
| 2145 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; |
| 2146 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; |
| 2147 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; |
| 2148 | |
| 2149 | /* WM1+ latency values stored in 0.5us units */ |
| 2150 | if (level > 0) { |
| 2151 | pri_latency *= 5; |
| 2152 | spr_latency *= 5; |
| 2153 | cur_latency *= 5; |
| 2154 | } |
| 2155 | |
| 2156 | result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); |
| 2157 | result->spr_val = ilk_compute_spr_wm(p, spr_latency); |
| 2158 | result->cur_val = ilk_compute_cur_wm(p, cur_latency); |
| 2159 | result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); |
| 2160 | result->enable = true; |
| 2161 | } |
| 2162 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2163 | static uint32_t |
| 2164 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2165 | { |
| 2166 | struct drm_i915_private *dev_priv = dev->dev_private; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2167 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2168 | struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; |
Paulo Zanoni | 85a02de | 2013-05-03 17:23:43 -0300 | [diff] [blame] | 2169 | u32 linetime, ips_linetime; |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2170 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2171 | if (!intel_crtc_active(crtc)) |
| 2172 | return 0; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2173 | |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2174 | /* The WM are computed with base on how long it takes to fill a single |
| 2175 | * row at the given clock rate, multiplied by 8. |
| 2176 | * */ |
Jesse Barnes | fec8cba | 2013-11-27 11:10:26 -0800 | [diff] [blame] | 2177 | linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
| 2178 | mode->crtc_clock); |
| 2179 | ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
Paulo Zanoni | 85a02de | 2013-05-03 17:23:43 -0300 | [diff] [blame] | 2180 | intel_ddi_get_cdclk_freq(dev_priv)); |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2181 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2182 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
| 2183 | PIPE_WM_LINETIME_TIME(linetime); |
Eugeni Dodonov | 1f8eeab | 2012-05-09 15:37:24 -0300 | [diff] [blame] | 2184 | } |
| 2185 | |
Ville Syrjälä | 12b134d | 2013-07-05 11:57:21 +0300 | [diff] [blame] | 2186 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
| 2187 | { |
| 2188 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2189 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2190 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Ville Syrjälä | 12b134d | 2013-07-05 11:57:21 +0300 | [diff] [blame] | 2191 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
| 2192 | |
| 2193 | wm[0] = (sskpd >> 56) & 0xFF; |
| 2194 | if (wm[0] == 0) |
| 2195 | wm[0] = sskpd & 0xF; |
Ville Syrjälä | e5d5019 | 2013-07-05 11:57:22 +0300 | [diff] [blame] | 2196 | wm[1] = (sskpd >> 4) & 0xFF; |
| 2197 | wm[2] = (sskpd >> 12) & 0xFF; |
| 2198 | wm[3] = (sskpd >> 20) & 0x1FF; |
| 2199 | wm[4] = (sskpd >> 32) & 0x1FF; |
Ville Syrjälä | 63cf9a1 | 2013-07-05 11:57:23 +0300 | [diff] [blame] | 2200 | } else if (INTEL_INFO(dev)->gen >= 6) { |
| 2201 | uint32_t sskpd = I915_READ(MCH_SSKPD); |
| 2202 | |
| 2203 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; |
| 2204 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; |
| 2205 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; |
| 2206 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; |
Ville Syrjälä | 3a88d0a | 2013-08-01 16:18:49 +0300 | [diff] [blame] | 2207 | } else if (INTEL_INFO(dev)->gen >= 5) { |
| 2208 | uint32_t mltr = I915_READ(MLTR_ILK); |
| 2209 | |
| 2210 | /* ILK primary LP0 latency is 700 ns */ |
| 2211 | wm[0] = 7; |
| 2212 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; |
| 2213 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; |
Ville Syrjälä | 12b134d | 2013-07-05 11:57:21 +0300 | [diff] [blame] | 2214 | } |
| 2215 | } |
| 2216 | |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 2217 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
| 2218 | { |
| 2219 | /* ILK sprite LP0 latency is 1300 ns */ |
| 2220 | if (INTEL_INFO(dev)->gen == 5) |
| 2221 | wm[0] = 13; |
| 2222 | } |
| 2223 | |
| 2224 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
| 2225 | { |
| 2226 | /* ILK cursor LP0 latency is 1300 ns */ |
| 2227 | if (INTEL_INFO(dev)->gen == 5) |
| 2228 | wm[0] = 13; |
| 2229 | |
| 2230 | /* WaDoubleCursorLP3Latency:ivb */ |
| 2231 | if (IS_IVYBRIDGE(dev)) |
| 2232 | wm[3] *= 2; |
| 2233 | } |
| 2234 | |
Damien Lespiau | 546c81f | 2014-05-13 15:30:26 +0100 | [diff] [blame] | 2235 | int ilk_wm_max_level(const struct drm_device *dev) |
Ville Syrjälä | ad0d6dc | 2013-08-30 14:30:25 +0300 | [diff] [blame] | 2236 | { |
| 2237 | /* how many WM levels are we expecting */ |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2238 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ad0d6dc | 2013-08-30 14:30:25 +0300 | [diff] [blame] | 2239 | return 4; |
| 2240 | else if (INTEL_INFO(dev)->gen >= 6) |
| 2241 | return 3; |
| 2242 | else |
| 2243 | return 2; |
| 2244 | } |
| 2245 | |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 2246 | static void intel_print_wm_latency(struct drm_device *dev, |
| 2247 | const char *name, |
| 2248 | const uint16_t wm[5]) |
| 2249 | { |
Ville Syrjälä | ad0d6dc | 2013-08-30 14:30:25 +0300 | [diff] [blame] | 2250 | int level, max_level = ilk_wm_max_level(dev); |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 2251 | |
| 2252 | for (level = 0; level <= max_level; level++) { |
| 2253 | unsigned int latency = wm[level]; |
| 2254 | |
| 2255 | if (latency == 0) { |
| 2256 | DRM_ERROR("%s WM%d latency not provided\n", |
| 2257 | name, level); |
| 2258 | continue; |
| 2259 | } |
| 2260 | |
| 2261 | /* WM1+ latency values in 0.5us units */ |
| 2262 | if (level > 0) |
| 2263 | latency *= 5; |
| 2264 | |
| 2265 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", |
| 2266 | name, level, wm[level], |
| 2267 | latency / 10, latency % 10); |
| 2268 | } |
| 2269 | } |
| 2270 | |
Ville Syrjälä | e95a2f7 | 2014-05-08 15:09:19 +0300 | [diff] [blame] | 2271 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
| 2272 | uint16_t wm[5], uint16_t min) |
| 2273 | { |
| 2274 | int level, max_level = ilk_wm_max_level(dev_priv->dev); |
| 2275 | |
| 2276 | if (wm[0] >= min) |
| 2277 | return false; |
| 2278 | |
| 2279 | wm[0] = max(wm[0], min); |
| 2280 | for (level = 1; level <= max_level; level++) |
| 2281 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); |
| 2282 | |
| 2283 | return true; |
| 2284 | } |
| 2285 | |
| 2286 | static void snb_wm_latency_quirk(struct drm_device *dev) |
| 2287 | { |
| 2288 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2289 | bool changed; |
| 2290 | |
| 2291 | /* |
| 2292 | * The BIOS provided WM memory latency values are often |
| 2293 | * inadequate for high resolution displays. Adjust them. |
| 2294 | */ |
| 2295 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | |
| 2296 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | |
| 2297 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); |
| 2298 | |
| 2299 | if (!changed) |
| 2300 | return; |
| 2301 | |
| 2302 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); |
| 2303 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); |
| 2304 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); |
| 2305 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); |
| 2306 | } |
| 2307 | |
Damien Lespiau | fa50ad6 | 2014-03-17 18:01:16 +0000 | [diff] [blame] | 2308 | static void ilk_setup_wm_latency(struct drm_device *dev) |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 2309 | { |
| 2310 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2311 | |
| 2312 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); |
| 2313 | |
| 2314 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, |
| 2315 | sizeof(dev_priv->wm.pri_latency)); |
| 2316 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, |
| 2317 | sizeof(dev_priv->wm.pri_latency)); |
| 2318 | |
| 2319 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); |
| 2320 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); |
Ville Syrjälä | 26ec971 | 2013-08-01 16:18:52 +0300 | [diff] [blame] | 2321 | |
| 2322 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); |
| 2323 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); |
| 2324 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); |
Ville Syrjälä | e95a2f7 | 2014-05-08 15:09:19 +0300 | [diff] [blame] | 2325 | |
| 2326 | if (IS_GEN6(dev)) |
| 2327 | snb_wm_latency_quirk(dev); |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 2328 | } |
| 2329 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2330 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2331 | struct ilk_pipe_wm_parameters *p) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2332 | { |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2333 | struct drm_device *dev = crtc->dev; |
| 2334 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2335 | enum pipe pipe = intel_crtc->pipe; |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2336 | struct drm_plane *plane; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2337 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2338 | if (!intel_crtc_active(crtc)) |
| 2339 | return; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2340 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2341 | p->active = true; |
| 2342 | p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; |
| 2343 | p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); |
| 2344 | p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; |
| 2345 | p->cur.bytes_per_pixel = 4; |
| 2346 | p->pri.horiz_pixels = intel_crtc->config.pipe_src_w; |
| 2347 | p->cur.horiz_pixels = intel_crtc->cursor_width; |
| 2348 | /* TODO: for now, assume primary and cursor planes are always enabled. */ |
| 2349 | p->pri.enabled = true; |
| 2350 | p->cur.enabled = true; |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2351 | |
Matt Roper | af2b653 | 2014-04-01 15:22:32 -0700 | [diff] [blame] | 2352 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2353 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2354 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2355 | if (intel_plane->pipe == pipe) { |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2356 | p->spr = intel_plane->wm; |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2357 | break; |
| 2358 | } |
| 2359 | } |
| 2360 | } |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2361 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2362 | static void ilk_compute_wm_config(struct drm_device *dev, |
| 2363 | struct intel_wm_config *config) |
| 2364 | { |
| 2365 | struct intel_crtc *intel_crtc; |
| 2366 | |
| 2367 | /* Compute the currently _active_ config */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 2368 | for_each_intel_crtc(dev, intel_crtc) { |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2369 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; |
| 2370 | |
| 2371 | if (!wm->pipe_enabled) |
| 2372 | continue; |
| 2373 | |
| 2374 | config->sprites_enabled |= wm->sprites_enabled; |
| 2375 | config->sprites_scaled |= wm->sprites_scaled; |
| 2376 | config->num_pipes_active++; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2377 | } |
| 2378 | } |
| 2379 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2380 | /* Compute new watermarks for the pipe */ |
| 2381 | static bool intel_compute_pipe_wm(struct drm_crtc *crtc, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2382 | const struct ilk_pipe_wm_parameters *params, |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2383 | struct intel_pipe_wm *pipe_wm) |
| 2384 | { |
| 2385 | struct drm_device *dev = crtc->dev; |
Damien Lespiau | d34ff9c | 2014-01-06 19:17:23 +0000 | [diff] [blame] | 2386 | const struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2387 | int level, max_level = ilk_wm_max_level(dev); |
| 2388 | /* LP0 watermark maximums depend on this pipe alone */ |
| 2389 | struct intel_wm_config config = { |
| 2390 | .num_pipes_active = 1, |
| 2391 | .sprites_enabled = params->spr.enabled, |
| 2392 | .sprites_scaled = params->spr.scaled, |
| 2393 | }; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2394 | struct ilk_wm_maximums max; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2395 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2396 | pipe_wm->pipe_enabled = params->active; |
| 2397 | pipe_wm->sprites_enabled = params->spr.enabled; |
| 2398 | pipe_wm->sprites_scaled = params->spr.scaled; |
| 2399 | |
Ville Syrjälä | 7b39a0b | 2013-12-05 15:51:30 +0200 | [diff] [blame] | 2400 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
| 2401 | if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) |
| 2402 | max_level = 1; |
| 2403 | |
| 2404 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ |
| 2405 | if (params->spr.scaled) |
| 2406 | max_level = 0; |
| 2407 | |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 2408 | ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]); |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2409 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2410 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ce0e071 | 2013-12-05 15:51:36 +0200 | [diff] [blame] | 2411 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2412 | |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 2413 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
| 2414 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); |
| 2415 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2416 | /* At least LP0 must be valid */ |
Ville Syrjälä | a3cb404 | 2014-04-28 15:44:56 +0300 | [diff] [blame] | 2417 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
| 2418 | return false; |
| 2419 | |
| 2420 | ilk_compute_wm_reg_maximums(dev, 1, &max); |
| 2421 | |
| 2422 | for (level = 1; level <= max_level; level++) { |
| 2423 | struct intel_wm_level wm = {}; |
| 2424 | |
| 2425 | ilk_compute_wm_level(dev_priv, level, params, &wm); |
| 2426 | |
| 2427 | /* |
| 2428 | * Disable any watermark level that exceeds the |
| 2429 | * register maximums since such watermarks are |
| 2430 | * always invalid. |
| 2431 | */ |
| 2432 | if (!ilk_validate_wm_level(level, &max, &wm)) |
| 2433 | break; |
| 2434 | |
| 2435 | pipe_wm->wm[level] = wm; |
| 2436 | } |
| 2437 | |
| 2438 | return true; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2439 | } |
| 2440 | |
| 2441 | /* |
| 2442 | * Merge the watermarks from all active pipes for a specific level. |
| 2443 | */ |
| 2444 | static void ilk_merge_wm_level(struct drm_device *dev, |
| 2445 | int level, |
| 2446 | struct intel_wm_level *ret_wm) |
| 2447 | { |
| 2448 | const struct intel_crtc *intel_crtc; |
| 2449 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2450 | ret_wm->enable = true; |
| 2451 | |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 2452 | for_each_intel_crtc(dev, intel_crtc) { |
Ville Syrjälä | fe392ef | 2014-03-07 18:32:10 +0200 | [diff] [blame] | 2453 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; |
| 2454 | const struct intel_wm_level *wm = &active->wm[level]; |
| 2455 | |
| 2456 | if (!active->pipe_enabled) |
| 2457 | continue; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2458 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2459 | /* |
| 2460 | * The watermark values may have been used in the past, |
| 2461 | * so we must maintain them in the registers for some |
| 2462 | * time even if the level is now disabled. |
| 2463 | */ |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2464 | if (!wm->enable) |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2465 | ret_wm->enable = false; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2466 | |
| 2467 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); |
| 2468 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); |
| 2469 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); |
| 2470 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); |
| 2471 | } |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2472 | } |
| 2473 | |
| 2474 | /* |
| 2475 | * Merge all low power watermarks for all active pipes. |
| 2476 | */ |
| 2477 | static void ilk_wm_merge(struct drm_device *dev, |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 2478 | const struct intel_wm_config *config, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2479 | const struct ilk_wm_maximums *max, |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2480 | struct intel_pipe_wm *merged) |
| 2481 | { |
| 2482 | int level, max_level = ilk_wm_max_level(dev); |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2483 | int last_enabled_level = max_level; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2484 | |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 2485 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
| 2486 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && |
| 2487 | config->num_pipes_active > 1) |
| 2488 | return; |
| 2489 | |
Ville Syrjälä | 6c8b6c2 | 2013-12-05 15:51:35 +0200 | [diff] [blame] | 2490 | /* ILK: FBC WM must be disabled always */ |
| 2491 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2492 | |
| 2493 | /* merge each WM1+ level */ |
| 2494 | for (level = 1; level <= max_level; level++) { |
| 2495 | struct intel_wm_level *wm = &merged->wm[level]; |
| 2496 | |
| 2497 | ilk_merge_wm_level(dev, level, wm); |
| 2498 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2499 | if (level > last_enabled_level) |
| 2500 | wm->enable = false; |
| 2501 | else if (!ilk_validate_wm_level(level, max, wm)) |
| 2502 | /* make sure all following levels get disabled */ |
| 2503 | last_enabled_level = level - 1; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2504 | |
| 2505 | /* |
| 2506 | * The spec says it is preferred to disable |
| 2507 | * FBC WMs instead of disabling a WM level. |
| 2508 | */ |
| 2509 | if (wm->fbc_val > max->fbc) { |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2510 | if (wm->enable) |
| 2511 | merged->fbc_wm_enabled = false; |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2512 | wm->fbc_val = 0; |
| 2513 | } |
| 2514 | } |
Ville Syrjälä | 6c8b6c2 | 2013-12-05 15:51:35 +0200 | [diff] [blame] | 2515 | |
| 2516 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ |
| 2517 | /* |
| 2518 | * FIXME this is racy. FBC might get enabled later. |
| 2519 | * What we should check here is whether FBC can be |
| 2520 | * enabled sometime later. |
| 2521 | */ |
| 2522 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { |
| 2523 | for (level = 2; level <= max_level; level++) { |
| 2524 | struct intel_wm_level *wm = &merged->wm[level]; |
| 2525 | |
| 2526 | wm->enable = false; |
| 2527 | } |
| 2528 | } |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2529 | } |
| 2530 | |
Ville Syrjälä | b380ca3 | 2013-10-09 19:18:01 +0300 | [diff] [blame] | 2531 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
| 2532 | { |
| 2533 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ |
| 2534 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); |
| 2535 | } |
| 2536 | |
Ville Syrjälä | a68d68e | 2013-12-05 15:51:29 +0200 | [diff] [blame] | 2537 | /* The value we need to program into the WM_LPx latency field */ |
| 2538 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) |
| 2539 | { |
| 2540 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2541 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2542 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | a68d68e | 2013-12-05 15:51:29 +0200 | [diff] [blame] | 2543 | return 2 * level; |
| 2544 | else |
| 2545 | return dev_priv->wm.pri_latency[level]; |
| 2546 | } |
| 2547 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2548 | static void ilk_compute_wm_results(struct drm_device *dev, |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2549 | const struct intel_pipe_wm *merged, |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2550 | enum intel_ddb_partitioning partitioning, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2551 | struct ilk_wm_values *results) |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2552 | { |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2553 | struct intel_crtc *intel_crtc; |
| 2554 | int level, wm_lp; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2555 | |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2556 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2557 | results->partitioning = partitioning; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2558 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2559 | /* LP1+ register values */ |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2560 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
Ville Syrjälä | 1fd527c | 2013-08-06 22:24:05 +0300 | [diff] [blame] | 2561 | const struct intel_wm_level *r; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2562 | |
Ville Syrjälä | b380ca3 | 2013-10-09 19:18:01 +0300 | [diff] [blame] | 2563 | level = ilk_wm_lp_to_level(wm_lp, merged); |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2564 | |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2565 | r = &merged->wm[level]; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2566 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2567 | /* |
| 2568 | * Maintain the watermark values even if the level is |
| 2569 | * disabled. Doing otherwise could cause underruns. |
| 2570 | */ |
| 2571 | results->wm_lp[wm_lp - 1] = |
Ville Syrjälä | a68d68e | 2013-12-05 15:51:29 +0200 | [diff] [blame] | 2572 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
Ville Syrjälä | 416f472 | 2013-11-02 21:07:46 -0700 | [diff] [blame] | 2573 | (r->pri_val << WM1_LP_SR_SHIFT) | |
| 2574 | r->cur_val; |
| 2575 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2576 | if (r->enable) |
| 2577 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; |
| 2578 | |
Ville Syrjälä | 416f472 | 2013-11-02 21:07:46 -0700 | [diff] [blame] | 2579 | if (INTEL_INFO(dev)->gen >= 8) |
| 2580 | results->wm_lp[wm_lp - 1] |= |
| 2581 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; |
| 2582 | else |
| 2583 | results->wm_lp[wm_lp - 1] |= |
| 2584 | r->fbc_val << WM1_LP_FBC_SHIFT; |
| 2585 | |
Ville Syrjälä | d52fea5 | 2014-04-28 15:44:57 +0300 | [diff] [blame] | 2586 | /* |
| 2587 | * Always set WM1S_LP_EN when spr_val != 0, even if the |
| 2588 | * level is disabled. Doing otherwise could cause underruns. |
| 2589 | */ |
Ville Syrjälä | 6cef2b8a | 2013-12-05 15:51:32 +0200 | [diff] [blame] | 2590 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
| 2591 | WARN_ON(wm_lp != 1); |
| 2592 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; |
| 2593 | } else |
| 2594 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2595 | } |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2596 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2597 | /* LP0 register values */ |
Damien Lespiau | d3fcc80 | 2014-05-13 23:32:22 +0100 | [diff] [blame] | 2598 | for_each_intel_crtc(dev, intel_crtc) { |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2599 | enum pipe pipe = intel_crtc->pipe; |
| 2600 | const struct intel_wm_level *r = |
| 2601 | &intel_crtc->wm.active.wm[0]; |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2602 | |
Ville Syrjälä | 0b2ae6d | 2013-10-09 19:17:55 +0300 | [diff] [blame] | 2603 | if (WARN_ON(!r->enable)) |
| 2604 | continue; |
| 2605 | |
| 2606 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; |
| 2607 | |
| 2608 | results->wm_pipe[pipe] = |
| 2609 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | |
| 2610 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | |
| 2611 | r->cur_val; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2612 | } |
| 2613 | } |
| 2614 | |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2615 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
| 2616 | * case both are at the same level. Prefer r1 in case they're the same. */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2617 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2618 | struct intel_pipe_wm *r1, |
| 2619 | struct intel_pipe_wm *r2) |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2620 | { |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2621 | int level, max_level = ilk_wm_max_level(dev); |
| 2622 | int level1 = 0, level2 = 0; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2623 | |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2624 | for (level = 1; level <= max_level; level++) { |
| 2625 | if (r1->wm[level].enable) |
| 2626 | level1 = level; |
| 2627 | if (r2->wm[level].enable) |
| 2628 | level2 = level; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2629 | } |
| 2630 | |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2631 | if (level1 == level2) { |
| 2632 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2633 | return r2; |
| 2634 | else |
| 2635 | return r1; |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2636 | } else if (level1 > level2) { |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2637 | return r1; |
| 2638 | } else { |
| 2639 | return r2; |
| 2640 | } |
| 2641 | } |
| 2642 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2643 | /* dirty bits used to track which watermarks need changes */ |
| 2644 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) |
| 2645 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) |
| 2646 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) |
| 2647 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) |
| 2648 | #define WM_DIRTY_FBC (1 << 24) |
| 2649 | #define WM_DIRTY_DDB (1 << 25) |
| 2650 | |
| 2651 | static unsigned int ilk_compute_wm_dirty(struct drm_device *dev, |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2652 | const struct ilk_wm_values *old, |
| 2653 | const struct ilk_wm_values *new) |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2654 | { |
| 2655 | unsigned int dirty = 0; |
| 2656 | enum pipe pipe; |
| 2657 | int wm_lp; |
| 2658 | |
| 2659 | for_each_pipe(pipe) { |
| 2660 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
| 2661 | dirty |= WM_DIRTY_LINETIME(pipe); |
| 2662 | /* Must disable LP1+ watermarks too */ |
| 2663 | dirty |= WM_DIRTY_LP_ALL; |
| 2664 | } |
| 2665 | |
| 2666 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { |
| 2667 | dirty |= WM_DIRTY_PIPE(pipe); |
| 2668 | /* Must disable LP1+ watermarks too */ |
| 2669 | dirty |= WM_DIRTY_LP_ALL; |
| 2670 | } |
| 2671 | } |
| 2672 | |
| 2673 | if (old->enable_fbc_wm != new->enable_fbc_wm) { |
| 2674 | dirty |= WM_DIRTY_FBC; |
| 2675 | /* Must disable LP1+ watermarks too */ |
| 2676 | dirty |= WM_DIRTY_LP_ALL; |
| 2677 | } |
| 2678 | |
| 2679 | if (old->partitioning != new->partitioning) { |
| 2680 | dirty |= WM_DIRTY_DDB; |
| 2681 | /* Must disable LP1+ watermarks too */ |
| 2682 | dirty |= WM_DIRTY_LP_ALL; |
| 2683 | } |
| 2684 | |
| 2685 | /* LP1+ watermarks already deemed dirty, no need to continue */ |
| 2686 | if (dirty & WM_DIRTY_LP_ALL) |
| 2687 | return dirty; |
| 2688 | |
| 2689 | /* Find the lowest numbered LP1+ watermark in need of an update... */ |
| 2690 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
| 2691 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || |
| 2692 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) |
| 2693 | break; |
| 2694 | } |
| 2695 | |
| 2696 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ |
| 2697 | for (; wm_lp <= 3; wm_lp++) |
| 2698 | dirty |= WM_DIRTY_LP(wm_lp); |
| 2699 | |
| 2700 | return dirty; |
| 2701 | } |
| 2702 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2703 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
| 2704 | unsigned int dirty) |
| 2705 | { |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2706 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2707 | bool changed = false; |
| 2708 | |
| 2709 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
| 2710 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; |
| 2711 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); |
| 2712 | changed = true; |
| 2713 | } |
| 2714 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { |
| 2715 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; |
| 2716 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); |
| 2717 | changed = true; |
| 2718 | } |
| 2719 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { |
| 2720 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; |
| 2721 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); |
| 2722 | changed = true; |
| 2723 | } |
| 2724 | |
| 2725 | /* |
| 2726 | * Don't touch WM1S_LP_EN here. |
| 2727 | * Doing so could cause underruns. |
| 2728 | */ |
| 2729 | |
| 2730 | return changed; |
| 2731 | } |
| 2732 | |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2733 | /* |
| 2734 | * The spec says we shouldn't write when we don't need, because every write |
| 2735 | * causes WMs to be re-evaluated, expending some power. |
| 2736 | */ |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2737 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
| 2738 | struct ilk_wm_values *results) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2739 | { |
Ville Syrjälä | ac9545f | 2013-12-05 15:51:28 +0200 | [diff] [blame] | 2740 | struct drm_device *dev = dev_priv->dev; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2741 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2742 | unsigned int dirty; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2743 | uint32_t val; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2744 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2745 | dirty = ilk_compute_wm_dirty(dev, previous, results); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2746 | if (!dirty) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2747 | return; |
| 2748 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2749 | _ilk_disable_lp_wm(dev_priv, dirty); |
Ville Syrjälä | 6cef2b8a | 2013-12-05 15:51:32 +0200 | [diff] [blame] | 2750 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2751 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2752 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2753 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2754 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2755 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2756 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
| 2757 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2758 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2759 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2760 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2761 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2762 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2763 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
| 2764 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2765 | if (dirty & WM_DIRTY_DDB) { |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2766 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
Ville Syrjälä | ac9545f | 2013-12-05 15:51:28 +0200 | [diff] [blame] | 2767 | val = I915_READ(WM_MISC); |
| 2768 | if (results->partitioning == INTEL_DDB_PART_1_2) |
| 2769 | val &= ~WM_MISC_DATA_PARTITION_5_6; |
| 2770 | else |
| 2771 | val |= WM_MISC_DATA_PARTITION_5_6; |
| 2772 | I915_WRITE(WM_MISC, val); |
| 2773 | } else { |
| 2774 | val = I915_READ(DISP_ARB_CTL2); |
| 2775 | if (results->partitioning == INTEL_DDB_PART_1_2) |
| 2776 | val &= ~DISP_DATA_PARTITION_5_6; |
| 2777 | else |
| 2778 | val |= DISP_DATA_PARTITION_5_6; |
| 2779 | I915_WRITE(DISP_ARB_CTL2, val); |
| 2780 | } |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2781 | } |
| 2782 | |
Ville Syrjälä | 49a687c | 2013-10-11 19:39:52 +0300 | [diff] [blame] | 2783 | if (dirty & WM_DIRTY_FBC) { |
Paulo Zanoni | cca32e9 | 2013-05-31 11:45:06 -0300 | [diff] [blame] | 2784 | val = I915_READ(DISP_ARB_CTL); |
| 2785 | if (results->enable_fbc_wm) |
| 2786 | val &= ~DISP_FBC_WM_DIS; |
| 2787 | else |
| 2788 | val |= DISP_FBC_WM_DIS; |
| 2789 | I915_WRITE(DISP_ARB_CTL, val); |
| 2790 | } |
| 2791 | |
Imre Deak | 954911e | 2013-12-17 14:46:34 +0200 | [diff] [blame] | 2792 | if (dirty & WM_DIRTY_LP(1) && |
| 2793 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) |
| 2794 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); |
| 2795 | |
| 2796 | if (INTEL_INFO(dev)->gen >= 7) { |
Ville Syrjälä | 6cef2b8a | 2013-12-05 15:51:32 +0200 | [diff] [blame] | 2797 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
| 2798 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); |
| 2799 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) |
| 2800 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); |
| 2801 | } |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2802 | |
Ville Syrjälä | facd619 | 2013-12-05 15:51:33 +0200 | [diff] [blame] | 2803 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2804 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
Ville Syrjälä | facd619 | 2013-12-05 15:51:33 +0200 | [diff] [blame] | 2805 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2806 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
Ville Syrjälä | facd619 | 2013-12-05 15:51:33 +0200 | [diff] [blame] | 2807 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2808 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2809 | |
| 2810 | dev_priv->wm.hw = *results; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2811 | } |
| 2812 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2813 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
| 2814 | { |
| 2815 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2816 | |
| 2817 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); |
| 2818 | } |
| 2819 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2820 | static void ilk_update_wm(struct drm_crtc *crtc) |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2821 | { |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2822 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 2823 | struct drm_device *dev = crtc->dev; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2824 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2825 | struct ilk_wm_maximums max; |
| 2826 | struct ilk_pipe_wm_parameters params = {}; |
| 2827 | struct ilk_wm_values results = {}; |
Ville Syrjälä | 77c122b | 2013-08-06 22:24:04 +0300 | [diff] [blame] | 2828 | enum intel_ddb_partitioning partitioning; |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2829 | struct intel_pipe_wm pipe_wm = {}; |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2830 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
Ville Syrjälä | a485bfb | 2013-10-09 19:17:59 +0300 | [diff] [blame] | 2831 | struct intel_wm_config config = {}; |
Paulo Zanoni | 801bcff | 2013-05-31 10:08:35 -0300 | [diff] [blame] | 2832 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2833 | ilk_compute_wm_parameters(crtc, ¶ms); |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2834 | |
Ville Syrjälä | 7c4a395 | 2013-10-09 19:17:56 +0300 | [diff] [blame] | 2835 | intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); |
| 2836 | |
| 2837 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) |
| 2838 | return; |
| 2839 | |
| 2840 | intel_crtc->wm.active = pipe_wm; |
| 2841 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2842 | ilk_compute_wm_config(dev, &config); |
| 2843 | |
Ville Syrjälä | 34982fe | 2013-10-09 19:18:09 +0300 | [diff] [blame] | 2844 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 2845 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
Ville Syrjälä | 0362c78 | 2013-10-09 19:17:57 +0300 | [diff] [blame] | 2846 | |
Ville Syrjälä | a485bfb | 2013-10-09 19:17:59 +0300 | [diff] [blame] | 2847 | /* 5/6 split only in single pipe config on IVB+ */ |
Ville Syrjälä | ec98c8d | 2013-10-11 15:26:26 +0300 | [diff] [blame] | 2848 | if (INTEL_INFO(dev)->gen >= 7 && |
| 2849 | config.num_pipes_active == 1 && config.sprites_enabled) { |
Ville Syrjälä | 34982fe | 2013-10-09 19:18:09 +0300 | [diff] [blame] | 2850 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
Ville Syrjälä | 0ba22e2 | 2013-12-05 15:51:34 +0200 | [diff] [blame] | 2851 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
Ville Syrjälä | a485bfb | 2013-10-09 19:17:59 +0300 | [diff] [blame] | 2852 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2853 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2854 | } else { |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2855 | best_lp_wm = &lp_wm_1_2; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2856 | } |
| 2857 | |
Ville Syrjälä | 198a1e9 | 2013-10-09 19:17:58 +0300 | [diff] [blame] | 2858 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
Ville Syrjälä | 77c122b | 2013-08-06 22:24:04 +0300 | [diff] [blame] | 2859 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
Paulo Zanoni | 861f338 | 2013-05-31 10:19:21 -0300 | [diff] [blame] | 2860 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2861 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
Ville Syrjälä | 609cede | 2013-10-09 19:18:03 +0300 | [diff] [blame] | 2862 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2863 | ilk_write_wm_values(dev_priv, &results); |
Paulo Zanoni | 1011d8c | 2013-05-09 16:55:50 -0300 | [diff] [blame] | 2864 | } |
| 2865 | |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 2866 | static void |
| 2867 | ilk_update_sprite_wm(struct drm_plane *plane, |
| 2868 | struct drm_crtc *crtc, |
| 2869 | uint32_t sprite_width, uint32_t sprite_height, |
| 2870 | int pixel_size, bool enabled, bool scaled) |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 2871 | { |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2872 | struct drm_device *dev = plane->dev; |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 2873 | struct intel_plane *intel_plane = to_intel_plane(plane); |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 2874 | |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 2875 | intel_plane->wm.enabled = enabled; |
| 2876 | intel_plane->wm.scaled = scaled; |
| 2877 | intel_plane->wm.horiz_pixels = sprite_width; |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 2878 | intel_plane->wm.vert_pixels = sprite_width; |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 2879 | intel_plane->wm.bytes_per_pixel = pixel_size; |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 2880 | |
Ville Syrjälä | 8553c18 | 2013-12-05 15:51:39 +0200 | [diff] [blame] | 2881 | /* |
| 2882 | * IVB workaround: must disable low power watermarks for at least |
| 2883 | * one frame before enabling scaling. LP watermarks can be re-enabled |
| 2884 | * when scaling is disabled. |
| 2885 | * |
| 2886 | * WaCxSRDisabledForSpriteScaling:ivb |
| 2887 | */ |
| 2888 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) |
| 2889 | intel_wait_for_vblank(dev, intel_plane->pipe); |
| 2890 | |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2891 | ilk_update_wm(crtc); |
Paulo Zanoni | 526682e | 2013-05-24 11:59:18 -0300 | [diff] [blame] | 2892 | } |
| 2893 | |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2894 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
| 2895 | { |
| 2896 | struct drm_device *dev = crtc->dev; |
| 2897 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2898 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2899 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 2900 | struct intel_pipe_wm *active = &intel_crtc->wm.active; |
| 2901 | enum pipe pipe = intel_crtc->pipe; |
| 2902 | static const unsigned int wm0_pipe_reg[] = { |
| 2903 | [PIPE_A] = WM0_PIPEA_ILK, |
| 2904 | [PIPE_B] = WM0_PIPEB_ILK, |
| 2905 | [PIPE_C] = WM0_PIPEC_IVB, |
| 2906 | }; |
| 2907 | |
| 2908 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2909 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ce0e071 | 2013-12-05 15:51:36 +0200 | [diff] [blame] | 2910 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2911 | |
Ville Syrjälä | 2a44b76 | 2014-03-07 18:32:09 +0200 | [diff] [blame] | 2912 | active->pipe_enabled = intel_crtc_active(crtc); |
| 2913 | |
| 2914 | if (active->pipe_enabled) { |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2915 | u32 tmp = hw->wm_pipe[pipe]; |
| 2916 | |
| 2917 | /* |
| 2918 | * For active pipes LP0 watermark is marked as |
| 2919 | * enabled, and LP1+ watermaks as disabled since |
| 2920 | * we can't really reverse compute them in case |
| 2921 | * multiple pipes are active. |
| 2922 | */ |
| 2923 | active->wm[0].enable = true; |
| 2924 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; |
| 2925 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; |
| 2926 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; |
| 2927 | active->linetime = hw->wm_linetime[pipe]; |
| 2928 | } else { |
| 2929 | int level, max_level = ilk_wm_max_level(dev); |
| 2930 | |
| 2931 | /* |
| 2932 | * For inactive pipes, all watermark levels |
| 2933 | * should be marked as enabled but zeroed, |
| 2934 | * which is what we'd compute them to. |
| 2935 | */ |
| 2936 | for (level = 0; level <= max_level; level++) |
| 2937 | active->wm[level].enable = true; |
| 2938 | } |
| 2939 | } |
| 2940 | |
| 2941 | void ilk_wm_get_hw_state(struct drm_device *dev) |
| 2942 | { |
| 2943 | struct drm_i915_private *dev_priv = dev->dev_private; |
Imre Deak | 820c198 | 2013-12-17 14:46:36 +0200 | [diff] [blame] | 2944 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2945 | struct drm_crtc *crtc; |
| 2946 | |
Damien Lespiau | 70e1e0e | 2014-05-13 23:32:24 +0100 | [diff] [blame] | 2947 | for_each_crtc(dev, crtc) |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2948 | ilk_pipe_wm_get_hw_state(crtc); |
| 2949 | |
| 2950 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); |
| 2951 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); |
| 2952 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); |
| 2953 | |
| 2954 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); |
Ville Syrjälä | cfa7698 | 2014-03-07 18:32:08 +0200 | [diff] [blame] | 2955 | if (INTEL_INFO(dev)->gen >= 7) { |
| 2956 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); |
| 2957 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); |
| 2958 | } |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2959 | |
Ville Syrjälä | a42a571 | 2014-01-07 16:14:08 +0200 | [diff] [blame] | 2960 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Ville Syrjälä | ac9545f | 2013-12-05 15:51:28 +0200 | [diff] [blame] | 2961 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
| 2962 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; |
| 2963 | else if (IS_IVYBRIDGE(dev)) |
| 2964 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? |
| 2965 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; |
Ville Syrjälä | 243e6a4 | 2013-10-14 14:55:24 +0300 | [diff] [blame] | 2966 | |
| 2967 | hw->enable_fbc_wm = |
| 2968 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); |
| 2969 | } |
| 2970 | |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 2971 | /** |
| 2972 | * intel_update_watermarks - update FIFO watermark values based on current modes |
| 2973 | * |
| 2974 | * Calculate watermark values for the various WM regs based on current mode |
| 2975 | * and plane configuration. |
| 2976 | * |
| 2977 | * There are several cases to deal with here: |
| 2978 | * - normal (i.e. non-self-refresh) |
| 2979 | * - self-refresh (SR) mode |
| 2980 | * - lines are large relative to FIFO size (buffer can hold up to 2) |
| 2981 | * - lines are small relative to FIFO size (buffer can hold more than 2 |
| 2982 | * lines), so need to account for TLB latency |
| 2983 | * |
| 2984 | * The normal calculation is: |
| 2985 | * watermark = dotclock * bytes per pixel * latency |
| 2986 | * where latency is platform & configuration dependent (we assume pessimal |
| 2987 | * values here). |
| 2988 | * |
| 2989 | * The SR calculation is: |
| 2990 | * watermark = (trunc(latency/line time)+1) * surface width * |
| 2991 | * bytes per pixel |
| 2992 | * where |
| 2993 | * line time = htotal / dotclock |
| 2994 | * surface width = hdisplay for normal plane and 64 for cursor |
| 2995 | * and latency is assumed to be high, as above. |
| 2996 | * |
| 2997 | * The final value programmed to the register should always be rounded up, |
| 2998 | * and include an extra 2 entries to account for clock crossings. |
| 2999 | * |
| 3000 | * We don't use the sprite, so we can ignore that. And on Crestline we have |
| 3001 | * to set the non-SR watermarks to 8. |
| 3002 | */ |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 3003 | void intel_update_watermarks(struct drm_crtc *crtc) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3004 | { |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 3005 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3006 | |
| 3007 | if (dev_priv->display.update_wm) |
Ville Syrjälä | 46ba614 | 2013-09-10 11:40:40 +0300 | [diff] [blame] | 3008 | dev_priv->display.update_wm(crtc); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3009 | } |
| 3010 | |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 3011 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
| 3012 | struct drm_crtc *crtc, |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 3013 | uint32_t sprite_width, |
| 3014 | uint32_t sprite_height, |
| 3015 | int pixel_size, |
Ville Syrjälä | 39db4a4 | 2013-08-06 22:24:00 +0300 | [diff] [blame] | 3016 | bool enabled, bool scaled) |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3017 | { |
Ville Syrjälä | adf3d35 | 2013-08-06 22:24:11 +0300 | [diff] [blame] | 3018 | struct drm_i915_private *dev_priv = plane->dev->dev_private; |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3019 | |
| 3020 | if (dev_priv->display.update_sprite_wm) |
Damien Lespiau | ed57cb8 | 2014-07-15 09:21:24 +0200 | [diff] [blame] | 3021 | dev_priv->display.update_sprite_wm(plane, crtc, |
| 3022 | sprite_width, sprite_height, |
Ville Syrjälä | 39db4a4 | 2013-08-06 22:24:00 +0300 | [diff] [blame] | 3023 | pixel_size, enabled, scaled); |
Eugeni Dodonov | b445e3b | 2012-04-16 22:20:35 -0300 | [diff] [blame] | 3024 | } |
| 3025 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3026 | static struct drm_i915_gem_object * |
| 3027 | intel_alloc_context_page(struct drm_device *dev) |
| 3028 | { |
| 3029 | struct drm_i915_gem_object *ctx; |
| 3030 | int ret; |
| 3031 | |
| 3032 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 3033 | |
| 3034 | ctx = i915_gem_alloc_object(dev, 4096); |
| 3035 | if (!ctx) { |
| 3036 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); |
| 3037 | return NULL; |
| 3038 | } |
| 3039 | |
Daniel Vetter | c69766f | 2014-02-14 14:01:17 +0100 | [diff] [blame] | 3040 | ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3041 | if (ret) { |
| 3042 | DRM_ERROR("failed to pin power context: %d\n", ret); |
| 3043 | goto err_unref; |
| 3044 | } |
| 3045 | |
| 3046 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); |
| 3047 | if (ret) { |
| 3048 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); |
| 3049 | goto err_unpin; |
| 3050 | } |
| 3051 | |
| 3052 | return ctx; |
| 3053 | |
| 3054 | err_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 3055 | i915_gem_object_ggtt_unpin(ctx); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3056 | err_unref: |
| 3057 | drm_gem_object_unreference(&ctx->base); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3058 | return NULL; |
| 3059 | } |
| 3060 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3061 | /** |
| 3062 | * Lock protecting IPS related data structures |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3063 | */ |
| 3064 | DEFINE_SPINLOCK(mchdev_lock); |
| 3065 | |
| 3066 | /* Global for IPS driver to get at the current i915 device. Protected by |
| 3067 | * mchdev_lock. */ |
| 3068 | static struct drm_i915_private *i915_mch_dev; |
| 3069 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3070 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
| 3071 | { |
| 3072 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3073 | u16 rgvswctl; |
| 3074 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3075 | assert_spin_locked(&mchdev_lock); |
| 3076 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3077 | rgvswctl = I915_READ16(MEMSWCTL); |
| 3078 | if (rgvswctl & MEMCTL_CMD_STS) { |
| 3079 | DRM_DEBUG("gpu busy, RCS change rejected\n"); |
| 3080 | return false; /* still busy with another command */ |
| 3081 | } |
| 3082 | |
| 3083 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | |
| 3084 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; |
| 3085 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 3086 | POSTING_READ16(MEMSWCTL); |
| 3087 | |
| 3088 | rgvswctl |= MEMCTL_CMD_STS; |
| 3089 | I915_WRITE16(MEMSWCTL, rgvswctl); |
| 3090 | |
| 3091 | return true; |
| 3092 | } |
| 3093 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 3094 | static void ironlake_enable_drps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3095 | { |
| 3096 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3097 | u32 rgvmodectl = I915_READ(MEMMODECTL); |
| 3098 | u8 fmax, fmin, fstart, vstart; |
| 3099 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3100 | spin_lock_irq(&mchdev_lock); |
| 3101 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3102 | /* Enable temp reporting */ |
| 3103 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); |
| 3104 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); |
| 3105 | |
| 3106 | /* 100ms RC evaluation intervals */ |
| 3107 | I915_WRITE(RCUPEI, 100000); |
| 3108 | I915_WRITE(RCDNEI, 100000); |
| 3109 | |
| 3110 | /* Set max/min thresholds to 90ms and 80ms respectively */ |
| 3111 | I915_WRITE(RCBMAXAVG, 90000); |
| 3112 | I915_WRITE(RCBMINAVG, 80000); |
| 3113 | |
| 3114 | I915_WRITE(MEMIHYST, 1); |
| 3115 | |
| 3116 | /* Set up min, max, and cur for interrupt handling */ |
| 3117 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; |
| 3118 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); |
| 3119 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> |
| 3120 | MEMMODE_FSTART_SHIFT; |
| 3121 | |
| 3122 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> |
| 3123 | PXVFREQ_PX_SHIFT; |
| 3124 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3125 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
| 3126 | dev_priv->ips.fstart = fstart; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3127 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3128 | dev_priv->ips.max_delay = fstart; |
| 3129 | dev_priv->ips.min_delay = fmin; |
| 3130 | dev_priv->ips.cur_delay = fstart; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3131 | |
| 3132 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", |
| 3133 | fmax, fmin, fstart); |
| 3134 | |
| 3135 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); |
| 3136 | |
| 3137 | /* |
| 3138 | * Interrupts will be enabled in ironlake_irq_postinstall |
| 3139 | */ |
| 3140 | |
| 3141 | I915_WRITE(VIDSTART, vstart); |
| 3142 | POSTING_READ(VIDSTART); |
| 3143 | |
| 3144 | rgvmodectl |= MEMMODE_SWMODE_EN; |
| 3145 | I915_WRITE(MEMMODECTL, rgvmodectl); |
| 3146 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3147 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3148 | DRM_ERROR("stuck trying to change perf mode\n"); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3149 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3150 | |
| 3151 | ironlake_set_drps(dev, fstart); |
| 3152 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3153 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3154 | I915_READ(0x112e0); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3155 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
| 3156 | dev_priv->ips.last_count2 = I915_READ(0x112f4); |
| 3157 | getrawmonotonic(&dev_priv->ips.last_time2); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3158 | |
| 3159 | spin_unlock_irq(&mchdev_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3160 | } |
| 3161 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 3162 | static void ironlake_disable_drps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3163 | { |
| 3164 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3165 | u16 rgvswctl; |
| 3166 | |
| 3167 | spin_lock_irq(&mchdev_lock); |
| 3168 | |
| 3169 | rgvswctl = I915_READ16(MEMSWCTL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3170 | |
| 3171 | /* Ack interrupts, disable EFC interrupt */ |
| 3172 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); |
| 3173 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); |
| 3174 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); |
| 3175 | I915_WRITE(DEIIR, DE_PCU_EVENT); |
| 3176 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); |
| 3177 | |
| 3178 | /* Go back to the starting frequency */ |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 3179 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3180 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3181 | rgvswctl |= MEMCTL_CMD_STS; |
| 3182 | I915_WRITE(MEMSWCTL, rgvswctl); |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3183 | mdelay(1); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3184 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 3185 | spin_unlock_irq(&mchdev_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3186 | } |
| 3187 | |
Daniel Vetter | acbe947 | 2012-07-26 11:50:05 +0200 | [diff] [blame] | 3188 | /* There's a funny hw issue where the hw returns all 0 when reading from |
| 3189 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value |
| 3190 | * ourselves, instead of doing a rmw cycle (which might result in us clearing |
| 3191 | * all limits and the gpu stuck at whatever frequency it is at atm). |
| 3192 | */ |
Chris Wilson | 6917c7b | 2013-11-06 13:56:26 -0200 | [diff] [blame] | 3193 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3194 | { |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3195 | u32 limits; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3196 | |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 3197 | /* Only set the down limit when we've reached the lowest level to avoid |
| 3198 | * getting more interrupts, otherwise leave this clear. This prevents a |
| 3199 | * race in the hw when coming out of rc6: There's a tiny window where |
| 3200 | * the hw runs at the minimal clock before selecting the desired |
| 3201 | * frequency, if the down threshold expires in that window we will not |
| 3202 | * receive a down interrupt. */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3203 | limits = dev_priv->rps.max_freq_softlimit << 24; |
| 3204 | if (val <= dev_priv->rps.min_freq_softlimit) |
| 3205 | limits |= dev_priv->rps.min_freq_softlimit << 16; |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 3206 | |
| 3207 | return limits; |
| 3208 | } |
| 3209 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3210 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
| 3211 | { |
| 3212 | int new_power; |
| 3213 | |
| 3214 | new_power = dev_priv->rps.power; |
| 3215 | switch (dev_priv->rps.power) { |
| 3216 | case LOW_POWER: |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3217 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3218 | new_power = BETWEEN; |
| 3219 | break; |
| 3220 | |
| 3221 | case BETWEEN: |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3222 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3223 | new_power = LOW_POWER; |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3224 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3225 | new_power = HIGH_POWER; |
| 3226 | break; |
| 3227 | |
| 3228 | case HIGH_POWER: |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3229 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3230 | new_power = BETWEEN; |
| 3231 | break; |
| 3232 | } |
| 3233 | /* Max/min bins are special */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3234 | if (val == dev_priv->rps.min_freq_softlimit) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3235 | new_power = LOW_POWER; |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3236 | if (val == dev_priv->rps.max_freq_softlimit) |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3237 | new_power = HIGH_POWER; |
| 3238 | if (new_power == dev_priv->rps.power) |
| 3239 | return; |
| 3240 | |
| 3241 | /* Note the units here are not exactly 1us, but 1280ns. */ |
| 3242 | switch (new_power) { |
| 3243 | case LOW_POWER: |
| 3244 | /* Upclock if more than 95% busy over 16ms */ |
| 3245 | I915_WRITE(GEN6_RP_UP_EI, 12500); |
| 3246 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800); |
| 3247 | |
| 3248 | /* Downclock if less than 85% busy over 32ms */ |
| 3249 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); |
| 3250 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250); |
| 3251 | |
| 3252 | I915_WRITE(GEN6_RP_CONTROL, |
| 3253 | GEN6_RP_MEDIA_TURBO | |
| 3254 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 3255 | GEN6_RP_MEDIA_IS_GFX | |
| 3256 | GEN6_RP_ENABLE | |
| 3257 | GEN6_RP_UP_BUSY_AVG | |
| 3258 | GEN6_RP_DOWN_IDLE_AVG); |
| 3259 | break; |
| 3260 | |
| 3261 | case BETWEEN: |
| 3262 | /* Upclock if more than 90% busy over 13ms */ |
| 3263 | I915_WRITE(GEN6_RP_UP_EI, 10250); |
| 3264 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225); |
| 3265 | |
| 3266 | /* Downclock if less than 75% busy over 32ms */ |
| 3267 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); |
| 3268 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750); |
| 3269 | |
| 3270 | I915_WRITE(GEN6_RP_CONTROL, |
| 3271 | GEN6_RP_MEDIA_TURBO | |
| 3272 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 3273 | GEN6_RP_MEDIA_IS_GFX | |
| 3274 | GEN6_RP_ENABLE | |
| 3275 | GEN6_RP_UP_BUSY_AVG | |
| 3276 | GEN6_RP_DOWN_IDLE_AVG); |
| 3277 | break; |
| 3278 | |
| 3279 | case HIGH_POWER: |
| 3280 | /* Upclock if more than 85% busy over 10ms */ |
| 3281 | I915_WRITE(GEN6_RP_UP_EI, 8000); |
| 3282 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800); |
| 3283 | |
| 3284 | /* Downclock if less than 60% busy over 32ms */ |
| 3285 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); |
| 3286 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000); |
| 3287 | |
| 3288 | I915_WRITE(GEN6_RP_CONTROL, |
| 3289 | GEN6_RP_MEDIA_TURBO | |
| 3290 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 3291 | GEN6_RP_MEDIA_IS_GFX | |
| 3292 | GEN6_RP_ENABLE | |
| 3293 | GEN6_RP_UP_BUSY_AVG | |
| 3294 | GEN6_RP_DOWN_IDLE_AVG); |
| 3295 | break; |
| 3296 | } |
| 3297 | |
| 3298 | dev_priv->rps.power = new_power; |
| 3299 | dev_priv->rps.last_adj = 0; |
| 3300 | } |
| 3301 | |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3302 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
| 3303 | { |
| 3304 | u32 mask = 0; |
| 3305 | |
| 3306 | if (val > dev_priv->rps.min_freq_softlimit) |
| 3307 | mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
| 3308 | if (val < dev_priv->rps.max_freq_softlimit) |
| 3309 | mask |= GEN6_PM_RP_UP_THRESHOLD; |
| 3310 | |
Chris Wilson | 7b3c29f | 2014-07-10 20:31:19 +0100 | [diff] [blame] | 3311 | mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED); |
| 3312 | mask &= dev_priv->pm_rps_events; |
| 3313 | |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3314 | /* IVB and SNB hard hangs on looping batchbuffer |
| 3315 | * if GEN6_PM_UP_EI_EXPIRED is masked. |
| 3316 | */ |
| 3317 | if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev)) |
| 3318 | mask |= GEN6_PM_RP_UP_EI_EXPIRED; |
| 3319 | |
Deepak S | baccd45 | 2014-05-15 20:58:09 +0300 | [diff] [blame] | 3320 | if (IS_GEN8(dev_priv->dev)) |
| 3321 | mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP; |
| 3322 | |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3323 | return ~mask; |
| 3324 | } |
| 3325 | |
Jeff McGee | b8a5ff8 | 2014-02-04 11:37:01 -0600 | [diff] [blame] | 3326 | /* gen6_set_rps is called to update the frequency request, but should also be |
| 3327 | * called when the range (min_delay and max_delay) is modified so that we can |
| 3328 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ |
Daniel Vetter | 20b46e5 | 2012-07-26 11:16:14 +0200 | [diff] [blame] | 3329 | void gen6_set_rps(struct drm_device *dev, u8 val) |
| 3330 | { |
| 3331 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3332 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3333 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3334 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
| 3335 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); |
Daniel Vetter | 004777c | 2012-08-09 15:07:01 +0200 | [diff] [blame] | 3336 | |
Chris Wilson | eb64cad | 2014-03-27 08:24:20 +0000 | [diff] [blame] | 3337 | /* min/max delay may still have been modified so be sure to |
| 3338 | * write the limits value. |
| 3339 | */ |
| 3340 | if (val != dev_priv->rps.cur_freq) { |
| 3341 | gen6_set_rps_thresholds(dev_priv, val); |
Jeff McGee | b8a5ff8 | 2014-02-04 11:37:01 -0600 | [diff] [blame] | 3342 | |
Ben Widawsky | 50e6a2a | 2014-03-31 17:16:43 -0700 | [diff] [blame] | 3343 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
Chris Wilson | eb64cad | 2014-03-27 08:24:20 +0000 | [diff] [blame] | 3344 | I915_WRITE(GEN6_RPNSWREQ, |
| 3345 | HSW_FREQUENCY(val)); |
| 3346 | else |
| 3347 | I915_WRITE(GEN6_RPNSWREQ, |
| 3348 | GEN6_FREQUENCY(val) | |
| 3349 | GEN6_OFFSET(0) | |
| 3350 | GEN6_AGGRESSIVE_TURBO); |
Jeff McGee | b8a5ff8 | 2014-02-04 11:37:01 -0600 | [diff] [blame] | 3351 | } |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3352 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3353 | /* Make sure we continue to get interrupts |
| 3354 | * until we hit the minimum or maximum frequencies. |
| 3355 | */ |
Chris Wilson | eb64cad | 2014-03-27 08:24:20 +0000 | [diff] [blame] | 3356 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val)); |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3357 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3358 | |
Ben Widawsky | d5570a7 | 2012-09-07 19:43:41 -0700 | [diff] [blame] | 3359 | POSTING_READ(GEN6_RPNSWREQ); |
| 3360 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3361 | dev_priv->rps.cur_freq = val; |
Daniel Vetter | be2cde9 | 2012-08-30 13:26:48 +0200 | [diff] [blame] | 3362 | trace_intel_gpu_freq_change(val * 50); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3363 | } |
| 3364 | |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3365 | /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down |
| 3366 | * |
| 3367 | * * If Gfx is Idle, then |
| 3368 | * 1. Mask Turbo interrupts |
| 3369 | * 2. Bring up Gfx clock |
| 3370 | * 3. Change the freq to Rpn and wait till P-Unit updates freq |
| 3371 | * 4. Clear the Force GFX CLK ON bit so that Gfx can down |
| 3372 | * 5. Unmask Turbo interrupts |
| 3373 | */ |
| 3374 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) |
| 3375 | { |
Deepak S | 5549d25 | 2014-06-28 11:26:11 +0530 | [diff] [blame] | 3376 | struct drm_device *dev = dev_priv->dev; |
| 3377 | |
| 3378 | /* Latest VLV doesn't need to force the gfx clock */ |
| 3379 | if (dev->pdev->revision >= 0xd) { |
| 3380 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
| 3381 | return; |
| 3382 | } |
| 3383 | |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3384 | /* |
| 3385 | * When we are idle. Drop to min voltage state. |
| 3386 | */ |
| 3387 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3388 | if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit) |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3389 | return; |
| 3390 | |
| 3391 | /* Mask turbo interrupt so that they will not come in between */ |
| 3392 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
| 3393 | |
Imre Deak | 650ad97 | 2014-04-18 16:35:02 +0300 | [diff] [blame] | 3394 | vlv_force_gfx_clock(dev_priv, true); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3395 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3396 | dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit; |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3397 | |
| 3398 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3399 | dev_priv->rps.min_freq_softlimit); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3400 | |
| 3401 | if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) |
| 3402 | & GENFREQSTATUS) == 0, 5)) |
| 3403 | DRM_ERROR("timed out waiting for Punit\n"); |
| 3404 | |
Imre Deak | 650ad97 | 2014-04-18 16:35:02 +0300 | [diff] [blame] | 3405 | vlv_force_gfx_clock(dev_priv, false); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3406 | |
Chris Wilson | 7b3c29f | 2014-07-10 20:31:19 +0100 | [diff] [blame] | 3407 | I915_WRITE(GEN6_PMINTRMSK, |
| 3408 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3409 | } |
| 3410 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3411 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
| 3412 | { |
Damien Lespiau | 691bb71 | 2013-12-12 14:36:36 +0000 | [diff] [blame] | 3413 | struct drm_device *dev = dev_priv->dev; |
| 3414 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3415 | mutex_lock(&dev_priv->rps.hw_lock); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3416 | if (dev_priv->rps.enabled) { |
Deepak S | 3463811 | 2014-06-28 11:26:26 +0530 | [diff] [blame] | 3417 | if (IS_CHERRYVIEW(dev)) |
| 3418 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
| 3419 | else if (IS_VALLEYVIEW(dev)) |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 3420 | vlv_set_rps_idle(dev_priv); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3421 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3422 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3423 | dev_priv->rps.last_adj = 0; |
| 3424 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3425 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3426 | } |
| 3427 | |
| 3428 | void gen6_rps_boost(struct drm_i915_private *dev_priv) |
| 3429 | { |
Damien Lespiau | 691bb71 | 2013-12-12 14:36:36 +0000 | [diff] [blame] | 3430 | struct drm_device *dev = dev_priv->dev; |
| 3431 | |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3432 | mutex_lock(&dev_priv->rps.hw_lock); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3433 | if (dev_priv->rps.enabled) { |
Damien Lespiau | 691bb71 | 2013-12-12 14:36:36 +0000 | [diff] [blame] | 3434 | if (IS_VALLEYVIEW(dev)) |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3435 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3436 | else |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3437 | gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 3438 | dev_priv->rps.last_adj = 0; |
| 3439 | } |
Chris Wilson | b29c19b | 2013-09-25 17:34:56 +0100 | [diff] [blame] | 3440 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3441 | } |
| 3442 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3443 | void valleyview_set_rps(struct drm_device *dev, u8 val) |
| 3444 | { |
| 3445 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ville Syrjälä | 7a67092 | 2013-06-25 19:21:06 +0300 | [diff] [blame] | 3446 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3447 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3448 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
| 3449 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3450 | |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 3451 | DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3452 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
| 3453 | dev_priv->rps.cur_freq, |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 3454 | vlv_gpu_freq(dev_priv, val), val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3455 | |
Chris Wilson | 2876ce7 | 2014-03-28 08:03:34 +0000 | [diff] [blame] | 3456 | if (val != dev_priv->rps.cur_freq) |
| 3457 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3458 | |
Imre Deak | 09c87db | 2014-04-03 20:02:42 +0300 | [diff] [blame] | 3459 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3460 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3461 | dev_priv->rps.cur_freq = val; |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 3462 | trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3463 | } |
| 3464 | |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 3465 | static void gen8_disable_rps_interrupts(struct drm_device *dev) |
| 3466 | { |
| 3467 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3468 | |
Mika Kuoppala | 992f191 | 2014-05-16 13:44:12 +0300 | [diff] [blame] | 3469 | I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP); |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 3470 | I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) & |
| 3471 | ~dev_priv->pm_rps_events); |
| 3472 | /* Complete PM interrupt masking here doesn't race with the rps work |
| 3473 | * item again unmasking PM interrupts because that is using a different |
| 3474 | * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in |
| 3475 | * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which |
| 3476 | * gen8_enable_rps will clean up. */ |
| 3477 | |
| 3478 | spin_lock_irq(&dev_priv->irq_lock); |
| 3479 | dev_priv->rps.pm_iir = 0; |
| 3480 | spin_unlock_irq(&dev_priv->irq_lock); |
| 3481 | |
| 3482 | I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events); |
| 3483 | } |
| 3484 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3485 | static void gen6_disable_rps_interrupts(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3486 | { |
| 3487 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3488 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3489 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 3490 | I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & |
| 3491 | ~dev_priv->pm_rps_events); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3492 | /* Complete PM interrupt masking here doesn't race with the rps work |
| 3493 | * item again unmasking PM interrupts because that is using a different |
| 3494 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving |
| 3495 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ |
| 3496 | |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 3497 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | c6a828d | 2012-08-08 23:35:35 +0200 | [diff] [blame] | 3498 | dev_priv->rps.pm_iir = 0; |
Daniel Vetter | 59cdb63 | 2013-07-04 23:35:28 +0200 | [diff] [blame] | 3499 | spin_unlock_irq(&dev_priv->irq_lock); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3500 | |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 3501 | I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3502 | } |
| 3503 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3504 | static void gen6_disable_rps(struct drm_device *dev) |
| 3505 | { |
| 3506 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3507 | |
| 3508 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 3509 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
| 3510 | |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 3511 | if (IS_BROADWELL(dev)) |
| 3512 | gen8_disable_rps_interrupts(dev); |
| 3513 | else |
| 3514 | gen6_disable_rps_interrupts(dev); |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3515 | } |
| 3516 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 3517 | static void cherryview_disable_rps(struct drm_device *dev) |
| 3518 | { |
| 3519 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3520 | |
| 3521 | I915_WRITE(GEN6_RC_CONTROL, 0); |
Deepak S | 3497a56 | 2014-07-10 13:16:26 +0530 | [diff] [blame] | 3522 | |
| 3523 | gen8_disable_rps_interrupts(dev); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 3524 | } |
| 3525 | |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3526 | static void valleyview_disable_rps(struct drm_device *dev) |
| 3527 | { |
| 3528 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3529 | |
| 3530 | I915_WRITE(GEN6_RC_CONTROL, 0); |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3531 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3532 | gen6_disable_rps_interrupts(dev); |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 3533 | } |
| 3534 | |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 3535 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
| 3536 | { |
Imre Deak | 91ca689 | 2014-04-14 20:24:25 +0300 | [diff] [blame] | 3537 | if (IS_VALLEYVIEW(dev)) { |
| 3538 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) |
| 3539 | mode = GEN6_RC_CTL_RC6_ENABLE; |
| 3540 | else |
| 3541 | mode = 0; |
| 3542 | } |
Daniel Vetter | 8dfd1f0 | 2014-08-04 11:15:56 +0200 | [diff] [blame] | 3543 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n", |
| 3544 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", |
| 3545 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", |
| 3546 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 3547 | } |
| 3548 | |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3549 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3550 | { |
Damien Lespiau | eb4926e | 2013-06-07 17:41:14 +0100 | [diff] [blame] | 3551 | /* No RC6 before Ironlake */ |
| 3552 | if (INTEL_INFO(dev)->gen < 5) |
| 3553 | return 0; |
| 3554 | |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3555 | /* RC6 is only on Ironlake mobile not on desktop */ |
| 3556 | if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev)) |
| 3557 | return 0; |
| 3558 | |
Daniel Vetter | 456470e | 2012-08-08 23:35:40 +0200 | [diff] [blame] | 3559 | /* Respect the kernel parameter if it is set */ |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3560 | if (enable_rc6 >= 0) { |
| 3561 | int mask; |
| 3562 | |
| 3563 | if (INTEL_INFO(dev)->gen == 6 || IS_IVYBRIDGE(dev)) |
| 3564 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
| 3565 | INTEL_RC6pp_ENABLE; |
| 3566 | else |
| 3567 | mask = INTEL_RC6_ENABLE; |
| 3568 | |
| 3569 | if ((enable_rc6 & mask) != enable_rc6) |
Daniel Vetter | 8dfd1f0 | 2014-08-04 11:15:56 +0200 | [diff] [blame] | 3570 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
| 3571 | enable_rc6 & mask, enable_rc6, mask); |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3572 | |
| 3573 | return enable_rc6 & mask; |
| 3574 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3575 | |
Chris Wilson | 6567d74 | 2012-11-10 10:00:06 +0000 | [diff] [blame] | 3576 | /* Disable RC6 on Ironlake */ |
| 3577 | if (INTEL_INFO(dev)->gen == 5) |
| 3578 | return 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3579 | |
Ben Widawsky | 8bade1a | 2014-01-28 20:25:39 -0800 | [diff] [blame] | 3580 | if (IS_IVYBRIDGE(dev)) |
Ben Widawsky | cca84a1 | 2014-01-28 20:25:38 -0800 | [diff] [blame] | 3581 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
Ben Widawsky | 8bade1a | 2014-01-28 20:25:39 -0800 | [diff] [blame] | 3582 | |
| 3583 | return INTEL_RC6_ENABLE; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3584 | } |
| 3585 | |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 3586 | int intel_enable_rc6(const struct drm_device *dev) |
| 3587 | { |
| 3588 | return i915.enable_rc6; |
| 3589 | } |
| 3590 | |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 3591 | static void gen8_enable_rps_interrupts(struct drm_device *dev) |
| 3592 | { |
| 3593 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3594 | |
| 3595 | spin_lock_irq(&dev_priv->irq_lock); |
| 3596 | WARN_ON(dev_priv->rps.pm_iir); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 3597 | gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 3598 | I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events); |
| 3599 | spin_unlock_irq(&dev_priv->irq_lock); |
| 3600 | } |
| 3601 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3602 | static void gen6_enable_rps_interrupts(struct drm_device *dev) |
| 3603 | { |
| 3604 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3605 | |
| 3606 | spin_lock_irq(&dev_priv->irq_lock); |
Daniel Vetter | a0b3335 | 2013-07-04 23:35:34 +0200 | [diff] [blame] | 3607 | WARN_ON(dev_priv->rps.pm_iir); |
Daniel Vetter | 480c803 | 2014-07-16 09:49:40 +0200 | [diff] [blame] | 3608 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
Deepak S | a6706b4 | 2014-03-15 20:23:22 +0530 | [diff] [blame] | 3609 | I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3610 | spin_unlock_irq(&dev_priv->irq_lock); |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3611 | } |
| 3612 | |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 3613 | static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap) |
| 3614 | { |
| 3615 | /* All of these values are in units of 50MHz */ |
| 3616 | dev_priv->rps.cur_freq = 0; |
| 3617 | /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */ |
| 3618 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; |
| 3619 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; |
| 3620 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; |
| 3621 | /* XXX: only BYT has a special efficient freq */ |
| 3622 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
| 3623 | /* hw_max = RP0 until we check for overclocking */ |
| 3624 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; |
| 3625 | |
| 3626 | /* Preserve min/max settings in case of re-init */ |
| 3627 | if (dev_priv->rps.max_freq_softlimit == 0) |
| 3628 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
| 3629 | |
| 3630 | if (dev_priv->rps.min_freq_softlimit == 0) |
| 3631 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
| 3632 | } |
| 3633 | |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3634 | static void gen8_enable_rps(struct drm_device *dev) |
| 3635 | { |
| 3636 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3637 | struct intel_engine_cs *ring; |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3638 | uint32_t rc6_mask = 0, rp_state_cap; |
| 3639 | int unused; |
| 3640 | |
| 3641 | /* 1a: Software RC state - RC0 */ |
| 3642 | I915_WRITE(GEN6_RC_STATE, 0); |
| 3643 | |
| 3644 | /* 1c & 1d: Get forcewake during program sequence. Although the driver |
| 3645 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3646 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3647 | |
| 3648 | /* 2a: Disable RC states. */ |
| 3649 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 3650 | |
| 3651 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 3652 | parse_rp_state_cap(dev_priv, rp_state_cap); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3653 | |
| 3654 | /* 2b: Program RC6 thresholds.*/ |
| 3655 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); |
| 3656 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
| 3657 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
| 3658 | for_each_ring(ring, dev_priv, unused) |
| 3659 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 3660 | I915_WRITE(GEN6_RC_SLEEP, 0); |
Tom O'Rourke | 0d68b25 | 2014-04-09 11:44:06 -0700 | [diff] [blame] | 3661 | if (IS_BROADWELL(dev)) |
| 3662 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ |
| 3663 | else |
| 3664 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3665 | |
| 3666 | /* 3: Enable RC6 */ |
| 3667 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
| 3668 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
Ben Widawsky | abbf9d2 | 2014-01-28 20:25:41 -0800 | [diff] [blame] | 3669 | intel_print_rc6_info(dev, rc6_mask); |
Tom O'Rourke | 0d68b25 | 2014-04-09 11:44:06 -0700 | [diff] [blame] | 3670 | if (IS_BROADWELL(dev)) |
| 3671 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
| 3672 | GEN7_RC_CTL_TO_MODE | |
| 3673 | rc6_mask); |
| 3674 | else |
| 3675 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
| 3676 | GEN6_RC_CTL_EI_MODE(1) | |
| 3677 | rc6_mask); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3678 | |
| 3679 | /* 4 Program defaults and thresholds for RPS*/ |
Ben Widawsky | f9bdc58 | 2014-03-31 17:16:41 -0700 | [diff] [blame] | 3680 | I915_WRITE(GEN6_RPNSWREQ, |
| 3681 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); |
| 3682 | I915_WRITE(GEN6_RC_VIDEO_FREQ, |
| 3683 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3684 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
| 3685 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ |
| 3686 | |
| 3687 | /* Docs recommend 900MHz, and 300 MHz respectively */ |
| 3688 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3689 | dev_priv->rps.max_freq_softlimit << 24 | |
| 3690 | dev_priv->rps.min_freq_softlimit << 16); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3691 | |
| 3692 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ |
| 3693 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ |
| 3694 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ |
| 3695 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ |
| 3696 | |
| 3697 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
| 3698 | |
| 3699 | /* 5: Enable RPS */ |
| 3700 | I915_WRITE(GEN6_RP_CONTROL, |
| 3701 | GEN6_RP_MEDIA_TURBO | |
| 3702 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
Tom O'Rourke | 7405f42 | 2014-06-10 16:26:34 -0700 | [diff] [blame] | 3703 | GEN6_RP_MEDIA_IS_GFX | |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3704 | GEN6_RP_ENABLE | |
| 3705 | GEN6_RP_UP_BUSY_AVG | |
| 3706 | GEN6_RP_DOWN_IDLE_AVG); |
| 3707 | |
| 3708 | /* 6: Ring frequency + overclocking (our driver does this later */ |
| 3709 | |
| 3710 | gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); |
| 3711 | |
Ben Widawsky | 0961021 | 2014-05-15 20:58:08 +0300 | [diff] [blame] | 3712 | gen8_enable_rps_interrupts(dev); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3713 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3714 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 3715 | } |
| 3716 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3717 | static void gen6_enable_rps(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3718 | { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3719 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 3720 | struct intel_engine_cs *ring; |
Ben Widawsky | 2a5913a | 2014-03-19 18:31:13 -0700 | [diff] [blame] | 3721 | u32 rp_state_cap; |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3722 | u32 gt_perf_status; |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 3723 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3724 | u32 gtfifodbg; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3725 | int rc6_mode; |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3726 | int i, ret; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3727 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3728 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3729 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3730 | /* Here begins a magic sequence of register writes to enable |
| 3731 | * auto-downclocking. |
| 3732 | * |
| 3733 | * Perhaps there might be some value in exposing these to |
| 3734 | * userspace... |
| 3735 | */ |
| 3736 | I915_WRITE(GEN6_RC_STATE, 0); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3737 | |
| 3738 | /* Clear the DBG now so we don't confuse earlier errors */ |
| 3739 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
| 3740 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
| 3741 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 3742 | } |
| 3743 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3744 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3745 | |
Chris Wilson | 7b9e0ae | 2012-04-28 08:56:39 +0100 | [diff] [blame] | 3746 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
| 3747 | gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS); |
| 3748 | |
Ben Widawsky | 3280e8b | 2014-03-31 17:16:42 -0700 | [diff] [blame] | 3749 | parse_rp_state_cap(dev_priv, rp_state_cap); |
Jeff McGee | dd0a1aa | 2014-02-04 11:32:31 -0600 | [diff] [blame] | 3750 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3751 | /* disable the counters and set deterministic thresholds */ |
| 3752 | I915_WRITE(GEN6_RC_CONTROL, 0); |
| 3753 | |
| 3754 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); |
| 3755 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); |
| 3756 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); |
| 3757 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
| 3758 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
| 3759 | |
Chris Wilson | b451951 | 2012-05-11 14:29:30 +0100 | [diff] [blame] | 3760 | for_each_ring(ring, dev_priv, i) |
| 3761 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3762 | |
| 3763 | I915_WRITE(GEN6_RC_SLEEP, 0); |
| 3764 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); |
Daniel Vetter | 29c78f6 | 2013-11-16 16:04:26 +0100 | [diff] [blame] | 3765 | if (IS_IVYBRIDGE(dev)) |
Stéphane Marchesin | 351aa56 | 2013-08-13 11:55:17 -0700 | [diff] [blame] | 3766 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
| 3767 | else |
| 3768 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); |
Stéphane Marchesin | 0920a48 | 2013-01-29 19:41:59 -0800 | [diff] [blame] | 3769 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3770 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
| 3771 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3772 | /* Check if we are enabling RC6 */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3773 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
| 3774 | if (rc6_mode & INTEL_RC6_ENABLE) |
| 3775 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; |
| 3776 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3777 | /* We don't use those on Haswell */ |
| 3778 | if (!IS_HASWELL(dev)) { |
| 3779 | if (rc6_mode & INTEL_RC6p_ENABLE) |
| 3780 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3781 | |
Eugeni Dodonov | 5a7dc92 | 2012-07-02 11:51:05 -0300 | [diff] [blame] | 3782 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
| 3783 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; |
| 3784 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3785 | |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 3786 | intel_print_rc6_info(dev, rc6_mask); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3787 | |
| 3788 | I915_WRITE(GEN6_RC_CONTROL, |
| 3789 | rc6_mask | |
| 3790 | GEN6_RC_CTL_EI_MODE(1) | |
| 3791 | GEN6_RC_CTL_HW_ENABLE); |
| 3792 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3793 | /* Power down if completely idle for over 50ms */ |
| 3794 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3795 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3796 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3797 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 3798 | if (ret) |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3799 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 3800 | |
| 3801 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); |
| 3802 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ |
| 3803 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3804 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
Ben Widawsky | d060c16 | 2014-03-19 18:31:08 -0700 | [diff] [blame] | 3805 | (pcu_mbox & 0xff) * 50); |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3806 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3807 | } |
| 3808 | |
Chris Wilson | dd75fdc | 2013-09-25 17:34:57 +0100 | [diff] [blame] | 3809 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3810 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3811 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 3812 | gen6_enable_rps_interrupts(dev); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3813 | |
Ben Widawsky | 31643d5 | 2012-09-26 10:34:01 -0700 | [diff] [blame] | 3814 | rc6vids = 0; |
| 3815 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); |
| 3816 | if (IS_GEN6(dev) && ret) { |
| 3817 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
| 3818 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
| 3819 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
| 3820 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); |
| 3821 | rc6vids &= 0xffff00; |
| 3822 | rc6vids |= GEN6_ENCODE_RC6_VID(450); |
| 3823 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); |
| 3824 | if (ret) |
| 3825 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); |
| 3826 | } |
| 3827 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 3828 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3829 | } |
| 3830 | |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 3831 | static void __gen6_update_ring_freq(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3832 | { |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3833 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3834 | int min_freq = 15; |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3835 | unsigned int gpu_freq; |
| 3836 | unsigned int max_ia_freq, min_ring_freq; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3837 | int scaling_factor = 180; |
Ben Widawsky | eda7964 | 2013-10-07 17:15:48 -0300 | [diff] [blame] | 3838 | struct cpufreq_policy *policy; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3839 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 3840 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 3841 | |
Ben Widawsky | eda7964 | 2013-10-07 17:15:48 -0300 | [diff] [blame] | 3842 | policy = cpufreq_cpu_get(0); |
| 3843 | if (policy) { |
| 3844 | max_ia_freq = policy->cpuinfo.max_freq; |
| 3845 | cpufreq_cpu_put(policy); |
| 3846 | } else { |
| 3847 | /* |
| 3848 | * Default to measured freq if none found, PCU will ensure we |
| 3849 | * don't go over |
| 3850 | */ |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3851 | max_ia_freq = tsc_khz; |
Ben Widawsky | eda7964 | 2013-10-07 17:15:48 -0300 | [diff] [blame] | 3852 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3853 | |
| 3854 | /* Convert from kHz to MHz */ |
| 3855 | max_ia_freq /= 1000; |
| 3856 | |
Ben Widawsky | 153b4b95 | 2013-10-22 22:05:09 -0700 | [diff] [blame] | 3857 | min_ring_freq = I915_READ(DCLK) & 0xf; |
Ben Widawsky | f6aca45 | 2013-10-02 09:25:02 -0700 | [diff] [blame] | 3858 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
| 3859 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3860 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3861 | /* |
| 3862 | * For each potential GPU frequency, load a ring frequency we'd like |
| 3863 | * to use for memory access. We do this by specifying the IA frequency |
| 3864 | * the PCU should use as a reference to determine the ring frequency. |
| 3865 | */ |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3866 | for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3867 | gpu_freq--) { |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 3868 | int diff = dev_priv->rps.max_freq_softlimit - gpu_freq; |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3869 | unsigned int ia_freq = 0, ring_freq = 0; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3870 | |
Ben Widawsky | 46c764d | 2013-11-02 21:07:49 -0700 | [diff] [blame] | 3871 | if (INTEL_INFO(dev)->gen >= 8) { |
| 3872 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ |
| 3873 | ring_freq = max(min_ring_freq, gpu_freq); |
| 3874 | } else if (IS_HASWELL(dev)) { |
Ben Widawsky | f6aca45 | 2013-10-02 09:25:02 -0700 | [diff] [blame] | 3875 | ring_freq = mult_frac(gpu_freq, 5, 4); |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3876 | ring_freq = max(min_ring_freq, ring_freq); |
| 3877 | /* leave ia_freq as the default, chosen by cpufreq */ |
| 3878 | } else { |
| 3879 | /* On older processors, there is no separate ring |
| 3880 | * clock domain, so in order to boost the bandwidth |
| 3881 | * of the ring, we need to upclock the CPU (ia_freq). |
| 3882 | * |
| 3883 | * For GPU frequencies less than 750MHz, |
| 3884 | * just use the lowest ring freq. |
| 3885 | */ |
| 3886 | if (gpu_freq < min_freq) |
| 3887 | ia_freq = 800; |
| 3888 | else |
| 3889 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); |
| 3890 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); |
| 3891 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3892 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 3893 | sandybridge_pcode_write(dev_priv, |
| 3894 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, |
Chris Wilson | 3ebecd0 | 2013-04-12 19:10:13 +0100 | [diff] [blame] | 3895 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
| 3896 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | |
| 3897 | gpu_freq); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3898 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 3899 | } |
| 3900 | |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 3901 | void gen6_update_ring_freq(struct drm_device *dev) |
| 3902 | { |
| 3903 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 3904 | |
| 3905 | if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev)) |
| 3906 | return; |
| 3907 | |
| 3908 | mutex_lock(&dev_priv->rps.hw_lock); |
| 3909 | __gen6_update_ring_freq(dev); |
| 3910 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 3911 | } |
| 3912 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 3913 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 3914 | { |
| 3915 | u32 val, rp0; |
| 3916 | |
| 3917 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); |
| 3918 | rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK; |
| 3919 | |
| 3920 | return rp0; |
| 3921 | } |
| 3922 | |
| 3923 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) |
| 3924 | { |
| 3925 | u32 val, rpe; |
| 3926 | |
| 3927 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); |
| 3928 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; |
| 3929 | |
| 3930 | return rpe; |
| 3931 | } |
| 3932 | |
Deepak S | 7707df4 | 2014-07-12 18:46:14 +0530 | [diff] [blame] | 3933 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
| 3934 | { |
| 3935 | u32 val, rp1; |
| 3936 | |
| 3937 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
| 3938 | rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK; |
| 3939 | |
| 3940 | return rp1; |
| 3941 | } |
| 3942 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 3943 | static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 3944 | { |
| 3945 | u32 val, rpn; |
| 3946 | |
| 3947 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); |
| 3948 | rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK; |
| 3949 | return rpn; |
| 3950 | } |
| 3951 | |
Deepak S | f8f2b00 | 2014-07-10 13:16:21 +0530 | [diff] [blame] | 3952 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
| 3953 | { |
| 3954 | u32 val, rp1; |
| 3955 | |
| 3956 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
| 3957 | |
| 3958 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; |
| 3959 | |
| 3960 | return rp1; |
| 3961 | } |
| 3962 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 3963 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3964 | { |
| 3965 | u32 val, rp0; |
| 3966 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3967 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3968 | |
| 3969 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; |
| 3970 | /* Clamp to max */ |
| 3971 | rp0 = min_t(u32, rp0, 0xea); |
| 3972 | |
| 3973 | return rp0; |
| 3974 | } |
| 3975 | |
| 3976 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) |
| 3977 | { |
| 3978 | u32 val, rpe; |
| 3979 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3980 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3981 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3982 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3983 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
| 3984 | |
| 3985 | return rpe; |
| 3986 | } |
| 3987 | |
Ville Syrjälä | 03af204 | 2014-06-28 02:03:53 +0300 | [diff] [blame] | 3988 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3989 | { |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 3990 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 3991 | } |
| 3992 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 3993 | /* Check that the pctx buffer wasn't move under us. */ |
| 3994 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) |
| 3995 | { |
| 3996 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; |
| 3997 | |
| 3998 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + |
| 3999 | dev_priv->vlv_pctx->stolen->start); |
| 4000 | } |
| 4001 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4002 | |
| 4003 | /* Check that the pcbr address is not empty. */ |
| 4004 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) |
| 4005 | { |
| 4006 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; |
| 4007 | |
| 4008 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); |
| 4009 | } |
| 4010 | |
| 4011 | static void cherryview_setup_pctx(struct drm_device *dev) |
| 4012 | { |
| 4013 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4014 | unsigned long pctx_paddr, paddr; |
| 4015 | struct i915_gtt *gtt = &dev_priv->gtt; |
| 4016 | u32 pcbr; |
| 4017 | int pctx_size = 32*1024; |
| 4018 | |
| 4019 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 4020 | |
| 4021 | pcbr = I915_READ(VLV_PCBR); |
| 4022 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { |
| 4023 | paddr = (dev_priv->mm.stolen_base + |
| 4024 | (gtt->stolen_size - pctx_size)); |
| 4025 | |
| 4026 | pctx_paddr = (paddr & (~4095)); |
| 4027 | I915_WRITE(VLV_PCBR, pctx_paddr); |
| 4028 | } |
| 4029 | } |
| 4030 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 4031 | static void valleyview_setup_pctx(struct drm_device *dev) |
| 4032 | { |
| 4033 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4034 | struct drm_i915_gem_object *pctx; |
| 4035 | unsigned long pctx_paddr; |
| 4036 | u32 pcbr; |
| 4037 | int pctx_size = 24*1024; |
| 4038 | |
Imre Deak | 17b0c1f | 2014-02-11 21:39:06 +0200 | [diff] [blame] | 4039 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 4040 | |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 4041 | pcbr = I915_READ(VLV_PCBR); |
| 4042 | if (pcbr) { |
| 4043 | /* BIOS set it up already, grab the pre-alloc'd space */ |
| 4044 | int pcbr_offset; |
| 4045 | |
| 4046 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; |
| 4047 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, |
| 4048 | pcbr_offset, |
Daniel Vetter | 190d6cd | 2013-07-04 13:06:28 +0200 | [diff] [blame] | 4049 | I915_GTT_OFFSET_NONE, |
Jesse Barnes | c9cddff | 2013-05-08 10:45:13 -0700 | [diff] [blame] | 4050 | pctx_size); |
| 4051 | goto out; |
| 4052 | } |
| 4053 | |
| 4054 | /* |
| 4055 | * From the Gunit register HAS: |
| 4056 | * The Gfx driver is expected to program this register and ensure |
| 4057 | * proper allocation within Gfx stolen memory. For example, this |
| 4058 | * register should be programmed such than the PCBR range does not |
| 4059 | * overlap with other ranges, such as the frame buffer, protected |
| 4060 | * memory, or any other relevant ranges. |
| 4061 | */ |
| 4062 | pctx = i915_gem_object_create_stolen(dev, pctx_size); |
| 4063 | if (!pctx) { |
| 4064 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); |
| 4065 | return; |
| 4066 | } |
| 4067 | |
| 4068 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; |
| 4069 | I915_WRITE(VLV_PCBR, pctx_paddr); |
| 4070 | |
| 4071 | out: |
| 4072 | dev_priv->vlv_pctx = pctx; |
| 4073 | } |
| 4074 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 4075 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
| 4076 | { |
| 4077 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4078 | |
| 4079 | if (WARN_ON(!dev_priv->vlv_pctx)) |
| 4080 | return; |
| 4081 | |
| 4082 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); |
| 4083 | dev_priv->vlv_pctx = NULL; |
| 4084 | } |
| 4085 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4086 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
| 4087 | { |
| 4088 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4089 | |
| 4090 | valleyview_setup_pctx(dev); |
| 4091 | |
| 4092 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4093 | |
| 4094 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
| 4095 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; |
| 4096 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
| 4097 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
| 4098 | dev_priv->rps.max_freq); |
| 4099 | |
| 4100 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); |
| 4101 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
| 4102 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
| 4103 | dev_priv->rps.efficient_freq); |
| 4104 | |
Deepak S | f8f2b00 | 2014-07-10 13:16:21 +0530 | [diff] [blame] | 4105 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
| 4106 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", |
| 4107 | vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
| 4108 | dev_priv->rps.rp1_freq); |
| 4109 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4110 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
| 4111 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
| 4112 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
| 4113 | dev_priv->rps.min_freq); |
| 4114 | |
| 4115 | /* Preserve min/max settings in case of re-init */ |
| 4116 | if (dev_priv->rps.max_freq_softlimit == 0) |
| 4117 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
| 4118 | |
| 4119 | if (dev_priv->rps.min_freq_softlimit == 0) |
| 4120 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
| 4121 | |
| 4122 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 4123 | } |
| 4124 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4125 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
| 4126 | { |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4127 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4128 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4129 | cherryview_setup_pctx(dev); |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4130 | |
| 4131 | mutex_lock(&dev_priv->rps.hw_lock); |
| 4132 | |
| 4133 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
| 4134 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; |
| 4135 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", |
| 4136 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
| 4137 | dev_priv->rps.max_freq); |
| 4138 | |
| 4139 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); |
| 4140 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", |
| 4141 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
| 4142 | dev_priv->rps.efficient_freq); |
| 4143 | |
Deepak S | 7707df4 | 2014-07-12 18:46:14 +0530 | [diff] [blame] | 4144 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
| 4145 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", |
| 4146 | vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
| 4147 | dev_priv->rps.rp1_freq); |
| 4148 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4149 | dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); |
| 4150 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
| 4151 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
| 4152 | dev_priv->rps.min_freq); |
| 4153 | |
| 4154 | /* Preserve min/max settings in case of re-init */ |
| 4155 | if (dev_priv->rps.max_freq_softlimit == 0) |
| 4156 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; |
| 4157 | |
| 4158 | if (dev_priv->rps.min_freq_softlimit == 0) |
| 4159 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; |
| 4160 | |
| 4161 | mutex_unlock(&dev_priv->rps.hw_lock); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4162 | } |
| 4163 | |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 4164 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
| 4165 | { |
| 4166 | valleyview_cleanup_pctx(dev); |
| 4167 | } |
| 4168 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4169 | static void cherryview_enable_rps(struct drm_device *dev) |
| 4170 | { |
| 4171 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4172 | struct intel_engine_cs *ring; |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4173 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4174 | int i; |
| 4175 | |
| 4176 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 4177 | |
| 4178 | gtfifodbg = I915_READ(GTFIFODBG); |
| 4179 | if (gtfifodbg) { |
| 4180 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
| 4181 | gtfifodbg); |
| 4182 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 4183 | } |
| 4184 | |
| 4185 | cherryview_check_pctx(dev_priv); |
| 4186 | |
| 4187 | /* 1a & 1b: Get forcewake during program sequence. Although the driver |
| 4188 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ |
| 4189 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
| 4190 | |
| 4191 | /* 2a: Program RC6 thresholds.*/ |
| 4192 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); |
| 4193 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
| 4194 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ |
| 4195 | |
| 4196 | for_each_ring(ring, dev_priv, i) |
| 4197 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 4198 | I915_WRITE(GEN6_RC_SLEEP, 0); |
| 4199 | |
| 4200 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ |
| 4201 | |
| 4202 | /* allows RC6 residency counter to work */ |
| 4203 | I915_WRITE(VLV_COUNTER_CONTROL, |
| 4204 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | |
| 4205 | VLV_MEDIA_RC6_COUNT_EN | |
| 4206 | VLV_RENDER_RC6_COUNT_EN)); |
| 4207 | |
| 4208 | /* For now we assume BIOS is allocating and populating the PCBR */ |
| 4209 | pcbr = I915_READ(VLV_PCBR); |
| 4210 | |
| 4211 | DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr); |
| 4212 | |
| 4213 | /* 3: Enable RC6 */ |
| 4214 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && |
| 4215 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) |
| 4216 | rc6_mode = GEN6_RC_CTL_EI_MODE(1); |
| 4217 | |
| 4218 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
| 4219 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4220 | /* 4 Program defaults and thresholds for RPS*/ |
| 4221 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
| 4222 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
| 4223 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
| 4224 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
| 4225 | |
| 4226 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
| 4227 | |
Tom O'Rourke | 7405f42 | 2014-06-10 16:26:34 -0700 | [diff] [blame] | 4228 | /* WaDisablePwrmtrEvent:chv (pre-production hw) */ |
| 4229 | I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff); |
| 4230 | I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00); |
| 4231 | |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4232 | /* 5: Enable RPS */ |
| 4233 | I915_WRITE(GEN6_RP_CONTROL, |
| 4234 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
Tom O'Rourke | 7405f42 | 2014-06-10 16:26:34 -0700 | [diff] [blame] | 4235 | GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ |
Deepak S | 2b6b3a0 | 2014-05-27 15:59:30 +0530 | [diff] [blame] | 4236 | GEN6_RP_ENABLE | |
| 4237 | GEN6_RP_UP_BUSY_AVG | |
| 4238 | GEN6_RP_DOWN_IDLE_AVG); |
| 4239 | |
| 4240 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
| 4241 | |
| 4242 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); |
| 4243 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
| 4244 | |
| 4245 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
| 4246 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
| 4247 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
| 4248 | dev_priv->rps.cur_freq); |
| 4249 | |
| 4250 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
| 4251 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
| 4252 | dev_priv->rps.efficient_freq); |
| 4253 | |
| 4254 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
| 4255 | |
Deepak S | 3497a56 | 2014-07-10 13:16:26 +0530 | [diff] [blame] | 4256 | gen8_enable_rps_interrupts(dev); |
| 4257 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 4258 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
| 4259 | } |
| 4260 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4261 | static void valleyview_enable_rps(struct drm_device *dev) |
| 4262 | { |
| 4263 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4264 | struct intel_engine_cs *ring; |
Ben Widawsky | 2a5913a | 2014-03-19 18:31:13 -0700 | [diff] [blame] | 4265 | u32 gtfifodbg, val, rc6_mode = 0; |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4266 | int i; |
| 4267 | |
| 4268 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
| 4269 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 4270 | valleyview_check_pctx(dev_priv); |
| 4271 | |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4272 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
Jesse Barnes | f7d85c1 | 2013-09-27 10:40:54 -0700 | [diff] [blame] | 4273 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
| 4274 | gtfifodbg); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4275 | I915_WRITE(GTFIFODBG, gtfifodbg); |
| 4276 | } |
| 4277 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 4278 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
| 4279 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4280 | |
| 4281 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
| 4282 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); |
| 4283 | I915_WRITE(GEN6_RP_UP_EI, 66000); |
| 4284 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); |
| 4285 | |
| 4286 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 4287 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4288 | |
| 4289 | I915_WRITE(GEN6_RP_CONTROL, |
| 4290 | GEN6_RP_MEDIA_TURBO | |
| 4291 | GEN6_RP_MEDIA_HW_NORMAL_MODE | |
| 4292 | GEN6_RP_MEDIA_IS_GFX | |
| 4293 | GEN6_RP_ENABLE | |
| 4294 | GEN6_RP_UP_BUSY_AVG | |
| 4295 | GEN6_RP_DOWN_IDLE_CONT); |
| 4296 | |
| 4297 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); |
| 4298 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); |
| 4299 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); |
| 4300 | |
| 4301 | for_each_ring(ring, dev_priv, i) |
| 4302 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); |
| 4303 | |
Jesse Barnes | 2f0aa304 | 2013-11-15 09:32:11 -0800 | [diff] [blame] | 4304 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4305 | |
| 4306 | /* allows RC6 residency counter to work */ |
Jesse Barnes | 49798eb | 2013-09-26 17:55:57 -0700 | [diff] [blame] | 4307 | I915_WRITE(VLV_COUNTER_CONTROL, |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 4308 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
| 4309 | VLV_RENDER_RC0_COUNT_EN | |
Jesse Barnes | 49798eb | 2013-09-26 17:55:57 -0700 | [diff] [blame] | 4310 | VLV_MEDIA_RC6_COUNT_EN | |
| 4311 | VLV_RENDER_RC6_COUNT_EN)); |
Deepak S | 31685c2 | 2014-07-03 17:33:01 -0400 | [diff] [blame] | 4312 | |
Jesse Barnes | a2b23fe | 2013-09-19 09:33:13 -0700 | [diff] [blame] | 4313 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
Jesse Barnes | 6b88f29 | 2013-11-15 09:32:12 -0800 | [diff] [blame] | 4314 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 4315 | |
| 4316 | intel_print_rc6_info(dev, rc6_mode); |
| 4317 | |
Jesse Barnes | a2b23fe | 2013-09-19 09:33:13 -0700 | [diff] [blame] | 4318 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4319 | |
Jani Nikula | 6493625 | 2013-05-22 15:36:20 +0300 | [diff] [blame] | 4320 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4321 | |
| 4322 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); |
| 4323 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
| 4324 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4325 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 4326 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4327 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
| 4328 | dev_priv->rps.cur_freq); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4329 | |
Ville Syrjälä | 73008b9 | 2013-06-25 19:21:01 +0300 | [diff] [blame] | 4330 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4331 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
| 4332 | dev_priv->rps.efficient_freq); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4333 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4334 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4335 | |
Daniel Vetter | 44fc7d5 | 2013-07-12 22:43:27 +0200 | [diff] [blame] | 4336 | gen6_enable_rps_interrupts(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4337 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 4338 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 4339 | } |
| 4340 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 4341 | void ironlake_teardown_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4342 | { |
| 4343 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4344 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 4345 | if (dev_priv->ips.renderctx) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4346 | i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 4347 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
| 4348 | dev_priv->ips.renderctx = NULL; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4349 | } |
| 4350 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 4351 | if (dev_priv->ips.pwrctx) { |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 4352 | i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx); |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 4353 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
| 4354 | dev_priv->ips.pwrctx = NULL; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4355 | } |
| 4356 | } |
| 4357 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 4358 | static void ironlake_disable_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4359 | { |
| 4360 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4361 | |
| 4362 | if (I915_READ(PWRCTXA)) { |
| 4363 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ |
| 4364 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); |
| 4365 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), |
| 4366 | 50); |
| 4367 | |
| 4368 | I915_WRITE(PWRCTXA, 0); |
| 4369 | POSTING_READ(PWRCTXA); |
| 4370 | |
| 4371 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
| 4372 | POSTING_READ(RSTDBYCTL); |
| 4373 | } |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4374 | } |
| 4375 | |
| 4376 | static int ironlake_setup_rc6(struct drm_device *dev) |
| 4377 | { |
| 4378 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 4379 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 4380 | if (dev_priv->ips.renderctx == NULL) |
| 4381 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); |
| 4382 | if (!dev_priv->ips.renderctx) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4383 | return -ENOMEM; |
| 4384 | |
Daniel Vetter | 3e37394 | 2012-11-02 19:55:04 +0100 | [diff] [blame] | 4385 | if (dev_priv->ips.pwrctx == NULL) |
| 4386 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); |
| 4387 | if (!dev_priv->ips.pwrctx) { |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4388 | ironlake_teardown_rc6(dev); |
| 4389 | return -ENOMEM; |
| 4390 | } |
| 4391 | |
| 4392 | return 0; |
| 4393 | } |
| 4394 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 4395 | static void ironlake_enable_rc6(struct drm_device *dev) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4396 | { |
| 4397 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4398 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 4399 | bool was_interruptible; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4400 | int ret; |
| 4401 | |
| 4402 | /* rc6 disabled by default due to repeated reports of hanging during |
| 4403 | * boot and resume. |
| 4404 | */ |
| 4405 | if (!intel_enable_rc6(dev)) |
| 4406 | return; |
| 4407 | |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4408 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
| 4409 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4410 | ret = ironlake_setup_rc6(dev); |
Daniel Vetter | 79f5b2c | 2012-06-24 16:42:33 +0200 | [diff] [blame] | 4411 | if (ret) |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4412 | return; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4413 | |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 4414 | was_interruptible = dev_priv->mm.interruptible; |
| 4415 | dev_priv->mm.interruptible = false; |
| 4416 | |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4417 | /* |
| 4418 | * GPU can automatically power down the render unit if given a page |
| 4419 | * to save state. |
| 4420 | */ |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 4421 | ret = intel_ring_begin(ring, 6); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4422 | if (ret) { |
| 4423 | ironlake_teardown_rc6(dev); |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 4424 | dev_priv->mm.interruptible = was_interruptible; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4425 | return; |
| 4426 | } |
| 4427 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 4428 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
| 4429 | intel_ring_emit(ring, MI_SET_CONTEXT); |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 4430 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 4431 | MI_MM_SPACE_GTT | |
| 4432 | MI_SAVE_EXT_STATE_EN | |
| 4433 | MI_RESTORE_EXT_STATE_EN | |
| 4434 | MI_RESTORE_INHIBIT); |
| 4435 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); |
| 4436 | intel_ring_emit(ring, MI_NOOP); |
| 4437 | intel_ring_emit(ring, MI_FLUSH); |
| 4438 | intel_ring_advance(ring); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4439 | |
| 4440 | /* |
| 4441 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW |
| 4442 | * does an implicit flush, combined with MI_FLUSH above, it should be |
| 4443 | * safe to assume that renderctx is valid |
| 4444 | */ |
Chris Wilson | 3e96050 | 2012-11-27 16:22:54 +0000 | [diff] [blame] | 4445 | ret = intel_ring_idle(ring); |
| 4446 | dev_priv->mm.interruptible = was_interruptible; |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4447 | if (ret) { |
Jani Nikula | def27a5 | 2013-03-12 10:49:19 +0200 | [diff] [blame] | 4448 | DRM_ERROR("failed to enable ironlake power savings\n"); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4449 | ironlake_teardown_rc6(dev); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4450 | return; |
| 4451 | } |
| 4452 | |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 4453 | I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4454 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
Ben Widawsky | dc39fff | 2013-10-18 12:32:07 -0700 | [diff] [blame] | 4455 | |
Imre Deak | 91ca689 | 2014-04-14 20:24:25 +0300 | [diff] [blame] | 4456 | intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE); |
Eugeni Dodonov | 2b4e57b | 2012-04-18 15:29:23 -0300 | [diff] [blame] | 4457 | } |
| 4458 | |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 4459 | static unsigned long intel_pxfreq(u32 vidfreq) |
| 4460 | { |
| 4461 | unsigned long freq; |
| 4462 | int div = (vidfreq & 0x3f0000) >> 16; |
| 4463 | int post = (vidfreq & 0x3000) >> 12; |
| 4464 | int pre = (vidfreq & 0x7); |
| 4465 | |
| 4466 | if (!pre) |
| 4467 | return 0; |
| 4468 | |
| 4469 | freq = ((div * 133333) / ((1<<post) * pre)); |
| 4470 | |
| 4471 | return freq; |
| 4472 | } |
| 4473 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4474 | static const struct cparams { |
| 4475 | u16 i; |
| 4476 | u16 t; |
| 4477 | u16 m; |
| 4478 | u16 c; |
| 4479 | } cparams[] = { |
| 4480 | { 1, 1333, 301, 28664 }, |
| 4481 | { 1, 1066, 294, 24460 }, |
| 4482 | { 1, 800, 294, 25192 }, |
| 4483 | { 0, 1333, 276, 27605 }, |
| 4484 | { 0, 1066, 276, 27605 }, |
| 4485 | { 0, 800, 231, 23784 }, |
| 4486 | }; |
| 4487 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4488 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4489 | { |
| 4490 | u64 total_count, diff, ret; |
| 4491 | u32 count1, count2, count3, m = 0, c = 0; |
| 4492 | unsigned long now = jiffies_to_msecs(jiffies), diff1; |
| 4493 | int i; |
| 4494 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4495 | assert_spin_locked(&mchdev_lock); |
| 4496 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4497 | diff1 = now - dev_priv->ips.last_time1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4498 | |
| 4499 | /* Prevent division-by-zero if we are asking too fast. |
| 4500 | * Also, we don't get interesting results if we are polling |
| 4501 | * faster than once in 10ms, so just return the saved value |
| 4502 | * in such cases. |
| 4503 | */ |
| 4504 | if (diff1 <= 10) |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4505 | return dev_priv->ips.chipset_power; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4506 | |
| 4507 | count1 = I915_READ(DMIEC); |
| 4508 | count2 = I915_READ(DDREC); |
| 4509 | count3 = I915_READ(CSIEC); |
| 4510 | |
| 4511 | total_count = count1 + count2 + count3; |
| 4512 | |
| 4513 | /* FIXME: handle per-counter overflow */ |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4514 | if (total_count < dev_priv->ips.last_count1) { |
| 4515 | diff = ~0UL - dev_priv->ips.last_count1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4516 | diff += total_count; |
| 4517 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4518 | diff = total_count - dev_priv->ips.last_count1; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4519 | } |
| 4520 | |
| 4521 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4522 | if (cparams[i].i == dev_priv->ips.c_m && |
| 4523 | cparams[i].t == dev_priv->ips.r_t) { |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4524 | m = cparams[i].m; |
| 4525 | c = cparams[i].c; |
| 4526 | break; |
| 4527 | } |
| 4528 | } |
| 4529 | |
| 4530 | diff = div_u64(diff, diff1); |
| 4531 | ret = ((m * diff) + c); |
| 4532 | ret = div_u64(ret, 10); |
| 4533 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4534 | dev_priv->ips.last_count1 = total_count; |
| 4535 | dev_priv->ips.last_time1 = now; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4536 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4537 | dev_priv->ips.chipset_power = ret; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4538 | |
| 4539 | return ret; |
| 4540 | } |
| 4541 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4542 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
| 4543 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4544 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4545 | unsigned long val; |
| 4546 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4547 | if (INTEL_INFO(dev)->gen != 5) |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4548 | return 0; |
| 4549 | |
| 4550 | spin_lock_irq(&mchdev_lock); |
| 4551 | |
| 4552 | val = __i915_chipset_val(dev_priv); |
| 4553 | |
| 4554 | spin_unlock_irq(&mchdev_lock); |
| 4555 | |
| 4556 | return val; |
| 4557 | } |
| 4558 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4559 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
| 4560 | { |
| 4561 | unsigned long m, x, b; |
| 4562 | u32 tsfs; |
| 4563 | |
| 4564 | tsfs = I915_READ(TSFS); |
| 4565 | |
| 4566 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); |
| 4567 | x = I915_READ8(TR1); |
| 4568 | |
| 4569 | b = tsfs & TSFS_INTR_MASK; |
| 4570 | |
| 4571 | return ((m * x) / 127) - b; |
| 4572 | } |
| 4573 | |
| 4574 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) |
| 4575 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4576 | struct drm_device *dev = dev_priv->dev; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4577 | static const struct v_table { |
| 4578 | u16 vd; /* in .1 mil */ |
| 4579 | u16 vm; /* in .1 mil */ |
| 4580 | } v_table[] = { |
| 4581 | { 0, 0, }, |
| 4582 | { 375, 0, }, |
| 4583 | { 500, 0, }, |
| 4584 | { 625, 0, }, |
| 4585 | { 750, 0, }, |
| 4586 | { 875, 0, }, |
| 4587 | { 1000, 0, }, |
| 4588 | { 1125, 0, }, |
| 4589 | { 4125, 3000, }, |
| 4590 | { 4125, 3000, }, |
| 4591 | { 4125, 3000, }, |
| 4592 | { 4125, 3000, }, |
| 4593 | { 4125, 3000, }, |
| 4594 | { 4125, 3000, }, |
| 4595 | { 4125, 3000, }, |
| 4596 | { 4125, 3000, }, |
| 4597 | { 4125, 3000, }, |
| 4598 | { 4125, 3000, }, |
| 4599 | { 4125, 3000, }, |
| 4600 | { 4125, 3000, }, |
| 4601 | { 4125, 3000, }, |
| 4602 | { 4125, 3000, }, |
| 4603 | { 4125, 3000, }, |
| 4604 | { 4125, 3000, }, |
| 4605 | { 4125, 3000, }, |
| 4606 | { 4125, 3000, }, |
| 4607 | { 4125, 3000, }, |
| 4608 | { 4125, 3000, }, |
| 4609 | { 4125, 3000, }, |
| 4610 | { 4125, 3000, }, |
| 4611 | { 4125, 3000, }, |
| 4612 | { 4125, 3000, }, |
| 4613 | { 4250, 3125, }, |
| 4614 | { 4375, 3250, }, |
| 4615 | { 4500, 3375, }, |
| 4616 | { 4625, 3500, }, |
| 4617 | { 4750, 3625, }, |
| 4618 | { 4875, 3750, }, |
| 4619 | { 5000, 3875, }, |
| 4620 | { 5125, 4000, }, |
| 4621 | { 5250, 4125, }, |
| 4622 | { 5375, 4250, }, |
| 4623 | { 5500, 4375, }, |
| 4624 | { 5625, 4500, }, |
| 4625 | { 5750, 4625, }, |
| 4626 | { 5875, 4750, }, |
| 4627 | { 6000, 4875, }, |
| 4628 | { 6125, 5000, }, |
| 4629 | { 6250, 5125, }, |
| 4630 | { 6375, 5250, }, |
| 4631 | { 6500, 5375, }, |
| 4632 | { 6625, 5500, }, |
| 4633 | { 6750, 5625, }, |
| 4634 | { 6875, 5750, }, |
| 4635 | { 7000, 5875, }, |
| 4636 | { 7125, 6000, }, |
| 4637 | { 7250, 6125, }, |
| 4638 | { 7375, 6250, }, |
| 4639 | { 7500, 6375, }, |
| 4640 | { 7625, 6500, }, |
| 4641 | { 7750, 6625, }, |
| 4642 | { 7875, 6750, }, |
| 4643 | { 8000, 6875, }, |
| 4644 | { 8125, 7000, }, |
| 4645 | { 8250, 7125, }, |
| 4646 | { 8375, 7250, }, |
| 4647 | { 8500, 7375, }, |
| 4648 | { 8625, 7500, }, |
| 4649 | { 8750, 7625, }, |
| 4650 | { 8875, 7750, }, |
| 4651 | { 9000, 7875, }, |
| 4652 | { 9125, 8000, }, |
| 4653 | { 9250, 8125, }, |
| 4654 | { 9375, 8250, }, |
| 4655 | { 9500, 8375, }, |
| 4656 | { 9625, 8500, }, |
| 4657 | { 9750, 8625, }, |
| 4658 | { 9875, 8750, }, |
| 4659 | { 10000, 8875, }, |
| 4660 | { 10125, 9000, }, |
| 4661 | { 10250, 9125, }, |
| 4662 | { 10375, 9250, }, |
| 4663 | { 10500, 9375, }, |
| 4664 | { 10625, 9500, }, |
| 4665 | { 10750, 9625, }, |
| 4666 | { 10875, 9750, }, |
| 4667 | { 11000, 9875, }, |
| 4668 | { 11125, 10000, }, |
| 4669 | { 11250, 10125, }, |
| 4670 | { 11375, 10250, }, |
| 4671 | { 11500, 10375, }, |
| 4672 | { 11625, 10500, }, |
| 4673 | { 11750, 10625, }, |
| 4674 | { 11875, 10750, }, |
| 4675 | { 12000, 10875, }, |
| 4676 | { 12125, 11000, }, |
| 4677 | { 12250, 11125, }, |
| 4678 | { 12375, 11250, }, |
| 4679 | { 12500, 11375, }, |
| 4680 | { 12625, 11500, }, |
| 4681 | { 12750, 11625, }, |
| 4682 | { 12875, 11750, }, |
| 4683 | { 13000, 11875, }, |
| 4684 | { 13125, 12000, }, |
| 4685 | { 13250, 12125, }, |
| 4686 | { 13375, 12250, }, |
| 4687 | { 13500, 12375, }, |
| 4688 | { 13625, 12500, }, |
| 4689 | { 13750, 12625, }, |
| 4690 | { 13875, 12750, }, |
| 4691 | { 14000, 12875, }, |
| 4692 | { 14125, 13000, }, |
| 4693 | { 14250, 13125, }, |
| 4694 | { 14375, 13250, }, |
| 4695 | { 14500, 13375, }, |
| 4696 | { 14625, 13500, }, |
| 4697 | { 14750, 13625, }, |
| 4698 | { 14875, 13750, }, |
| 4699 | { 15000, 13875, }, |
| 4700 | { 15125, 14000, }, |
| 4701 | { 15250, 14125, }, |
| 4702 | { 15375, 14250, }, |
| 4703 | { 15500, 14375, }, |
| 4704 | { 15625, 14500, }, |
| 4705 | { 15750, 14625, }, |
| 4706 | { 15875, 14750, }, |
| 4707 | { 16000, 14875, }, |
| 4708 | { 16125, 15000, }, |
| 4709 | }; |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4710 | if (INTEL_INFO(dev)->is_mobile) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4711 | return v_table[pxvid].vm; |
| 4712 | else |
| 4713 | return v_table[pxvid].vd; |
| 4714 | } |
| 4715 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4716 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4717 | { |
| 4718 | struct timespec now, diff1; |
| 4719 | u64 diff; |
| 4720 | unsigned long diffms; |
| 4721 | u32 count; |
| 4722 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4723 | assert_spin_locked(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4724 | |
| 4725 | getrawmonotonic(&now); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4726 | diff1 = timespec_sub(now, dev_priv->ips.last_time2); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4727 | |
| 4728 | /* Don't divide by 0 */ |
| 4729 | diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000; |
| 4730 | if (!diffms) |
| 4731 | return; |
| 4732 | |
| 4733 | count = I915_READ(GFXEC); |
| 4734 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4735 | if (count < dev_priv->ips.last_count2) { |
| 4736 | diff = ~0UL - dev_priv->ips.last_count2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4737 | diff += count; |
| 4738 | } else { |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4739 | diff = count - dev_priv->ips.last_count2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4740 | } |
| 4741 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4742 | dev_priv->ips.last_count2 = count; |
| 4743 | dev_priv->ips.last_time2 = now; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4744 | |
| 4745 | /* More magic constants... */ |
| 4746 | diff = diff * 1181; |
| 4747 | diff = div_u64(diff, diffms * 10); |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4748 | dev_priv->ips.gfx_power = diff; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4749 | } |
| 4750 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4751 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
| 4752 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4753 | struct drm_device *dev = dev_priv->dev; |
| 4754 | |
| 4755 | if (INTEL_INFO(dev)->gen != 5) |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4756 | return; |
| 4757 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4758 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4759 | |
| 4760 | __i915_update_gfx_val(dev_priv); |
| 4761 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4762 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4763 | } |
| 4764 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4765 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4766 | { |
| 4767 | unsigned long t, corr, state1, corr2, state2; |
| 4768 | u32 pxvid, ext_v; |
| 4769 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4770 | assert_spin_locked(&mchdev_lock); |
| 4771 | |
Ben Widawsky | b39fb29 | 2014-03-19 18:31:11 -0700 | [diff] [blame] | 4772 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4773 | pxvid = (pxvid >> 24) & 0x7f; |
| 4774 | ext_v = pvid_to_extvid(dev_priv, pxvid); |
| 4775 | |
| 4776 | state1 = ext_v; |
| 4777 | |
| 4778 | t = i915_mch_val(dev_priv); |
| 4779 | |
| 4780 | /* Revel in the empirically derived constants */ |
| 4781 | |
| 4782 | /* Correction factor in 1/100000 units */ |
| 4783 | if (t > 80) |
| 4784 | corr = ((t * 2349) + 135940); |
| 4785 | else if (t >= 50) |
| 4786 | corr = ((t * 964) + 29317); |
| 4787 | else /* < 50 */ |
| 4788 | corr = ((t * 301) + 1004); |
| 4789 | |
| 4790 | corr = corr * ((150142 * state1) / 10000 - 78642); |
| 4791 | corr /= 100000; |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4792 | corr2 = (corr * dev_priv->ips.corr); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4793 | |
| 4794 | state2 = (corr2 * state1) / 10000; |
| 4795 | state2 /= 100; /* convert to mW */ |
| 4796 | |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4797 | __i915_update_gfx_val(dev_priv); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4798 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4799 | return dev_priv->ips.gfx_power + state2; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4800 | } |
| 4801 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4802 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
| 4803 | { |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4804 | struct drm_device *dev = dev_priv->dev; |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4805 | unsigned long val; |
| 4806 | |
Damien Lespiau | 3d13ef2 | 2014-02-07 19:12:47 +0000 | [diff] [blame] | 4807 | if (INTEL_INFO(dev)->gen != 5) |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4808 | return 0; |
| 4809 | |
| 4810 | spin_lock_irq(&mchdev_lock); |
| 4811 | |
| 4812 | val = __i915_gfx_val(dev_priv); |
| 4813 | |
| 4814 | spin_unlock_irq(&mchdev_lock); |
| 4815 | |
| 4816 | return val; |
| 4817 | } |
| 4818 | |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4819 | /** |
| 4820 | * i915_read_mch_val - return value for IPS use |
| 4821 | * |
| 4822 | * Calculate and return a value for the IPS driver to use when deciding whether |
| 4823 | * we have thermal and power headroom to increase CPU or GPU power budget. |
| 4824 | */ |
| 4825 | unsigned long i915_read_mch_val(void) |
| 4826 | { |
| 4827 | struct drm_i915_private *dev_priv; |
| 4828 | unsigned long chipset_val, graphics_val, ret = 0; |
| 4829 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4830 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4831 | if (!i915_mch_dev) |
| 4832 | goto out_unlock; |
| 4833 | dev_priv = i915_mch_dev; |
| 4834 | |
Chris Wilson | f531dcb | 2012-09-25 10:16:12 +0100 | [diff] [blame] | 4835 | chipset_val = __i915_chipset_val(dev_priv); |
| 4836 | graphics_val = __i915_gfx_val(dev_priv); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4837 | |
| 4838 | ret = chipset_val + graphics_val; |
| 4839 | |
| 4840 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4841 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4842 | |
| 4843 | return ret; |
| 4844 | } |
| 4845 | EXPORT_SYMBOL_GPL(i915_read_mch_val); |
| 4846 | |
| 4847 | /** |
| 4848 | * i915_gpu_raise - raise GPU frequency limit |
| 4849 | * |
| 4850 | * Raise the limit; IPS indicates we have thermal headroom. |
| 4851 | */ |
| 4852 | bool i915_gpu_raise(void) |
| 4853 | { |
| 4854 | struct drm_i915_private *dev_priv; |
| 4855 | bool ret = true; |
| 4856 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4857 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4858 | if (!i915_mch_dev) { |
| 4859 | ret = false; |
| 4860 | goto out_unlock; |
| 4861 | } |
| 4862 | dev_priv = i915_mch_dev; |
| 4863 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4864 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
| 4865 | dev_priv->ips.max_delay--; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4866 | |
| 4867 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4868 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4869 | |
| 4870 | return ret; |
| 4871 | } |
| 4872 | EXPORT_SYMBOL_GPL(i915_gpu_raise); |
| 4873 | |
| 4874 | /** |
| 4875 | * i915_gpu_lower - lower GPU frequency limit |
| 4876 | * |
| 4877 | * IPS indicates we're close to a thermal limit, so throttle back the GPU |
| 4878 | * frequency maximum. |
| 4879 | */ |
| 4880 | bool i915_gpu_lower(void) |
| 4881 | { |
| 4882 | struct drm_i915_private *dev_priv; |
| 4883 | bool ret = true; |
| 4884 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4885 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4886 | if (!i915_mch_dev) { |
| 4887 | ret = false; |
| 4888 | goto out_unlock; |
| 4889 | } |
| 4890 | dev_priv = i915_mch_dev; |
| 4891 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4892 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
| 4893 | dev_priv->ips.max_delay++; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4894 | |
| 4895 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4896 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4897 | |
| 4898 | return ret; |
| 4899 | } |
| 4900 | EXPORT_SYMBOL_GPL(i915_gpu_lower); |
| 4901 | |
| 4902 | /** |
| 4903 | * i915_gpu_busy - indicate GPU business to IPS |
| 4904 | * |
| 4905 | * Tell the IPS driver whether or not the GPU is busy. |
| 4906 | */ |
| 4907 | bool i915_gpu_busy(void) |
| 4908 | { |
| 4909 | struct drm_i915_private *dev_priv; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 4910 | struct intel_engine_cs *ring; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4911 | bool ret = false; |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 4912 | int i; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4913 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4914 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4915 | if (!i915_mch_dev) |
| 4916 | goto out_unlock; |
| 4917 | dev_priv = i915_mch_dev; |
| 4918 | |
Chris Wilson | f047e39 | 2012-07-21 12:31:41 +0100 | [diff] [blame] | 4919 | for_each_ring(ring, dev_priv, i) |
| 4920 | ret |= !list_empty(&ring->request_list); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4921 | |
| 4922 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4923 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4924 | |
| 4925 | return ret; |
| 4926 | } |
| 4927 | EXPORT_SYMBOL_GPL(i915_gpu_busy); |
| 4928 | |
| 4929 | /** |
| 4930 | * i915_gpu_turbo_disable - disable graphics turbo |
| 4931 | * |
| 4932 | * Disable graphics turbo by resetting the max frequency and setting the |
| 4933 | * current frequency to the default. |
| 4934 | */ |
| 4935 | bool i915_gpu_turbo_disable(void) |
| 4936 | { |
| 4937 | struct drm_i915_private *dev_priv; |
| 4938 | bool ret = true; |
| 4939 | |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4940 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4941 | if (!i915_mch_dev) { |
| 4942 | ret = false; |
| 4943 | goto out_unlock; |
| 4944 | } |
| 4945 | dev_priv = i915_mch_dev; |
| 4946 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4947 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4948 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 4949 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4950 | ret = false; |
| 4951 | |
| 4952 | out_unlock: |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4953 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4954 | |
| 4955 | return ret; |
| 4956 | } |
| 4957 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); |
| 4958 | |
| 4959 | /** |
| 4960 | * Tells the intel_ips driver that the i915 driver is now loaded, if |
| 4961 | * IPS got loaded first. |
| 4962 | * |
| 4963 | * This awkward dance is so that neither module has to depend on the |
| 4964 | * other in order for IPS to do the appropriate communication of |
| 4965 | * GPU turbo limits to i915. |
| 4966 | */ |
| 4967 | static void |
| 4968 | ips_ping_for_i915_load(void) |
| 4969 | { |
| 4970 | void (*link)(void); |
| 4971 | |
| 4972 | link = symbol_get(ips_link_to_i915_driver); |
| 4973 | if (link) { |
| 4974 | link(); |
| 4975 | symbol_put(ips_link_to_i915_driver); |
| 4976 | } |
| 4977 | } |
| 4978 | |
| 4979 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) |
| 4980 | { |
Daniel Vetter | 02d7195 | 2012-08-09 16:44:54 +0200 | [diff] [blame] | 4981 | /* We only register the i915 ips part with intel-ips once everything is |
| 4982 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4983 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4984 | i915_mch_dev = dev_priv; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4985 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4986 | |
| 4987 | ips_ping_for_i915_load(); |
| 4988 | } |
| 4989 | |
| 4990 | void intel_gpu_ips_teardown(void) |
| 4991 | { |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4992 | spin_lock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4993 | i915_mch_dev = NULL; |
Daniel Vetter | 9270388 | 2012-08-09 16:46:01 +0200 | [diff] [blame] | 4994 | spin_unlock_irq(&mchdev_lock); |
Daniel Vetter | eb48eb0 | 2012-04-26 23:28:12 +0200 | [diff] [blame] | 4995 | } |
Deepak S | 76c3552f | 2014-01-30 23:08:16 +0530 | [diff] [blame] | 4996 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 4997 | static void intel_init_emon(struct drm_device *dev) |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 4998 | { |
| 4999 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5000 | u32 lcfuse; |
| 5001 | u8 pxw[16]; |
| 5002 | int i; |
| 5003 | |
| 5004 | /* Disable to program */ |
| 5005 | I915_WRITE(ECR, 0); |
| 5006 | POSTING_READ(ECR); |
| 5007 | |
| 5008 | /* Program energy weights for various events */ |
| 5009 | I915_WRITE(SDEW, 0x15040d00); |
| 5010 | I915_WRITE(CSIEW0, 0x007f0000); |
| 5011 | I915_WRITE(CSIEW1, 0x1e220004); |
| 5012 | I915_WRITE(CSIEW2, 0x04000004); |
| 5013 | |
| 5014 | for (i = 0; i < 5; i++) |
| 5015 | I915_WRITE(PEW + (i * 4), 0); |
| 5016 | for (i = 0; i < 3; i++) |
| 5017 | I915_WRITE(DEW + (i * 4), 0); |
| 5018 | |
| 5019 | /* Program P-state weights to account for frequency power adjustment */ |
| 5020 | for (i = 0; i < 16; i++) { |
| 5021 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); |
| 5022 | unsigned long freq = intel_pxfreq(pxvidfreq); |
| 5023 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> |
| 5024 | PXVFREQ_PX_SHIFT; |
| 5025 | unsigned long val; |
| 5026 | |
| 5027 | val = vid * vid; |
| 5028 | val *= (freq / 1000); |
| 5029 | val *= 255; |
| 5030 | val /= (127*127*900); |
| 5031 | if (val > 0xff) |
| 5032 | DRM_ERROR("bad pxval: %ld\n", val); |
| 5033 | pxw[i] = val; |
| 5034 | } |
| 5035 | /* Render standby states get 0 weight */ |
| 5036 | pxw[14] = 0; |
| 5037 | pxw[15] = 0; |
| 5038 | |
| 5039 | for (i = 0; i < 4; i++) { |
| 5040 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | |
| 5041 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); |
| 5042 | I915_WRITE(PXW + (i * 4), val); |
| 5043 | } |
| 5044 | |
| 5045 | /* Adjust magic regs to magic values (more experimental results) */ |
| 5046 | I915_WRITE(OGW0, 0); |
| 5047 | I915_WRITE(OGW1, 0); |
| 5048 | I915_WRITE(EG0, 0x00007f00); |
| 5049 | I915_WRITE(EG1, 0x0000000e); |
| 5050 | I915_WRITE(EG2, 0x000e0000); |
| 5051 | I915_WRITE(EG3, 0x68000300); |
| 5052 | I915_WRITE(EG4, 0x42000000); |
| 5053 | I915_WRITE(EG5, 0x00140031); |
| 5054 | I915_WRITE(EG6, 0); |
| 5055 | I915_WRITE(EG7, 0); |
| 5056 | |
| 5057 | for (i = 0; i < 8; i++) |
| 5058 | I915_WRITE(PXWL + (i * 4), 0); |
| 5059 | |
| 5060 | /* Enable PMON + select events */ |
| 5061 | I915_WRITE(ECR, 0x80000019); |
| 5062 | |
| 5063 | lcfuse = I915_READ(LCFUSE02); |
| 5064 | |
Daniel Vetter | 20e4d40 | 2012-08-08 23:35:39 +0200 | [diff] [blame] | 5065 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
Eugeni Dodonov | dde1888 | 2012-04-18 15:29:24 -0300 | [diff] [blame] | 5066 | } |
| 5067 | |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 5068 | void intel_init_gt_powersave(struct drm_device *dev) |
| 5069 | { |
Imre Deak | e6069ca | 2014-04-18 16:01:02 +0300 | [diff] [blame] | 5070 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
| 5071 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5072 | if (IS_CHERRYVIEW(dev)) |
| 5073 | cherryview_init_gt_powersave(dev); |
| 5074 | else if (IS_VALLEYVIEW(dev)) |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5075 | valleyview_init_gt_powersave(dev); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 5076 | } |
| 5077 | |
| 5078 | void intel_cleanup_gt_powersave(struct drm_device *dev) |
| 5079 | { |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5080 | if (IS_CHERRYVIEW(dev)) |
| 5081 | return; |
| 5082 | else if (IS_VALLEYVIEW(dev)) |
Imre Deak | 4e80519 | 2014-04-14 20:24:41 +0300 | [diff] [blame] | 5083 | valleyview_cleanup_gt_powersave(dev); |
Imre Deak | ae48434 | 2014-03-31 15:10:44 +0300 | [diff] [blame] | 5084 | } |
| 5085 | |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 5086 | /** |
| 5087 | * intel_suspend_gt_powersave - suspend PM work and helper threads |
| 5088 | * @dev: drm device |
| 5089 | * |
| 5090 | * We don't want to disable RC6 or other features here, we just want |
| 5091 | * to make sure any work we've queued has finished and won't bother |
| 5092 | * us while we're suspended. |
| 5093 | */ |
| 5094 | void intel_suspend_gt_powersave(struct drm_device *dev) |
| 5095 | { |
| 5096 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5097 | |
| 5098 | /* Interrupts should be disabled already to avoid re-arming. */ |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 5099 | WARN_ON(intel_irqs_enabled(dev_priv)); |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 5100 | |
| 5101 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); |
| 5102 | |
| 5103 | cancel_work_sync(&dev_priv->rps.work); |
Deepak S | b47adc1 | 2014-06-20 20:03:02 +0530 | [diff] [blame] | 5104 | |
| 5105 | /* Force GPU to min freq during suspend */ |
| 5106 | gen6_rps_idle(dev_priv); |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 5107 | } |
| 5108 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5109 | void intel_disable_gt_powersave(struct drm_device *dev) |
| 5110 | { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 5111 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5112 | |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 5113 | /* Interrupts should be disabled already to avoid re-arming. */ |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 5114 | WARN_ON(intel_irqs_enabled(dev_priv)); |
Daniel Vetter | fd0c064 | 2013-04-24 11:13:35 +0200 | [diff] [blame] | 5115 | |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 5116 | if (IS_IRONLAKE_M(dev)) { |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5117 | ironlake_disable_drps(dev); |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 5118 | ironlake_disable_rc6(dev); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5119 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | 10d8d36 | 2014-06-12 17:48:52 +0200 | [diff] [blame] | 5120 | intel_suspend_gt_powersave(dev); |
Imre Deak | e494837 | 2014-05-12 18:35:04 +0300 | [diff] [blame] | 5121 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5122 | mutex_lock(&dev_priv->rps.hw_lock); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5123 | if (IS_CHERRYVIEW(dev)) |
| 5124 | cherryview_disable_rps(dev); |
| 5125 | else if (IS_VALLEYVIEW(dev)) |
Jesse Barnes | d20d4f0 | 2013-04-23 10:09:28 -0700 | [diff] [blame] | 5126 | valleyview_disable_rps(dev); |
| 5127 | else |
| 5128 | gen6_disable_rps(dev); |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 5129 | dev_priv->rps.enabled = false; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5130 | mutex_unlock(&dev_priv->rps.hw_lock); |
Daniel Vetter | 930ebb4 | 2012-06-29 23:32:16 +0200 | [diff] [blame] | 5131 | } |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5132 | } |
| 5133 | |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 5134 | static void intel_gen6_powersave_work(struct work_struct *work) |
| 5135 | { |
| 5136 | struct drm_i915_private *dev_priv = |
| 5137 | container_of(work, struct drm_i915_private, |
| 5138 | rps.delayed_resume_work.work); |
| 5139 | struct drm_device *dev = dev_priv->dev; |
| 5140 | |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5141 | mutex_lock(&dev_priv->rps.hw_lock); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5142 | |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5143 | if (IS_CHERRYVIEW(dev)) { |
| 5144 | cherryview_enable_rps(dev); |
| 5145 | } else if (IS_VALLEYVIEW(dev)) { |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5146 | valleyview_enable_rps(dev); |
Ben Widawsky | 6edee7f | 2013-11-02 21:07:52 -0700 | [diff] [blame] | 5147 | } else if (IS_BROADWELL(dev)) { |
| 5148 | gen8_enable_rps(dev); |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 5149 | __gen6_update_ring_freq(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5150 | } else { |
| 5151 | gen6_enable_rps(dev); |
Imre Deak | c2bc2fc | 2014-04-18 16:16:23 +0300 | [diff] [blame] | 5152 | __gen6_update_ring_freq(dev); |
Jesse Barnes | 0a073b8 | 2013-04-17 15:54:58 -0700 | [diff] [blame] | 5153 | } |
Chris Wilson | c0951f0 | 2013-10-10 21:58:50 +0100 | [diff] [blame] | 5154 | dev_priv->rps.enabled = true; |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 5155 | mutex_unlock(&dev_priv->rps.hw_lock); |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 5156 | |
| 5157 | intel_runtime_pm_put(dev_priv); |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 5158 | } |
| 5159 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5160 | void intel_enable_gt_powersave(struct drm_device *dev) |
| 5161 | { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 5162 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5163 | |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5164 | if (IS_IRONLAKE_M(dev)) { |
Imre Deak | dc1d013 | 2014-04-14 20:24:28 +0300 | [diff] [blame] | 5165 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5166 | ironlake_enable_drps(dev); |
| 5167 | ironlake_enable_rc6(dev); |
| 5168 | intel_init_emon(dev); |
Imre Deak | dc1d013 | 2014-04-14 20:24:28 +0300 | [diff] [blame] | 5169 | mutex_unlock(&dev->struct_mutex); |
Deepak S | 3880774 | 2014-05-23 21:00:15 +0530 | [diff] [blame] | 5170 | } else if (INTEL_INFO(dev)->gen >= 6) { |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 5171 | /* |
| 5172 | * PCU communication is slow and this doesn't need to be |
| 5173 | * done at any specific time, so do this out of our fast path |
| 5174 | * to make resume and init faster. |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 5175 | * |
| 5176 | * We depend on the HW RC6 power context save/restore |
| 5177 | * mechanism when entering D3 through runtime PM suspend. So |
| 5178 | * disable RPM until RPS/RC6 is properly setup. We can only |
| 5179 | * get here via the driver load/system resume/runtime resume |
| 5180 | * paths, so the _noresume version is enough (and in case of |
| 5181 | * runtime resume it's necessary). |
Jesse Barnes | 1a01ab3 | 2012-11-02 11:14:00 -0700 | [diff] [blame] | 5182 | */ |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 5183 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
| 5184 | round_jiffies_up_relative(HZ))) |
| 5185 | intel_runtime_pm_get_noresume(dev_priv); |
Daniel Vetter | 8090c6b | 2012-06-24 16:42:32 +0200 | [diff] [blame] | 5186 | } |
| 5187 | } |
| 5188 | |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 5189 | void intel_reset_gt_powersave(struct drm_device *dev) |
| 5190 | { |
| 5191 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5192 | |
| 5193 | dev_priv->rps.enabled = false; |
| 5194 | intel_enable_gt_powersave(dev); |
| 5195 | } |
| 5196 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5197 | static void ibx_init_clock_gating(struct drm_device *dev) |
| 5198 | { |
| 5199 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5200 | |
| 5201 | /* |
| 5202 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 5203 | * gating for the panel power sequencer or it will fail to |
| 5204 | * start up when no ports are active. |
| 5205 | */ |
| 5206 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); |
| 5207 | } |
| 5208 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5209 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
| 5210 | { |
| 5211 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5212 | int pipe; |
| 5213 | |
| 5214 | for_each_pipe(pipe) { |
| 5215 | I915_WRITE(DSPCNTR(pipe), |
| 5216 | I915_READ(DSPCNTR(pipe)) | |
| 5217 | DISPPLANE_TRICKLE_FEED_DISABLE); |
Ville Syrjälä | 1dba99f | 2013-10-01 18:02:18 +0300 | [diff] [blame] | 5218 | intel_flush_primary_plane(dev_priv, pipe); |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5219 | } |
| 5220 | } |
| 5221 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 5222 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
| 5223 | { |
| 5224 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5225 | |
| 5226 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); |
| 5227 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); |
| 5228 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); |
| 5229 | |
| 5230 | /* |
| 5231 | * Don't touch WM1S_LP_EN here. |
| 5232 | * Doing so could cause underruns. |
| 5233 | */ |
| 5234 | } |
| 5235 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5236 | static void ironlake_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5237 | { |
| 5238 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 5239 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5240 | |
Damien Lespiau | f1e8fa5 | 2013-06-07 17:41:09 +0100 | [diff] [blame] | 5241 | /* |
| 5242 | * Required for FBC |
| 5243 | * WaFbcDisableDpfcClockGating:ilk |
| 5244 | */ |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 5245 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
| 5246 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | |
| 5247 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5248 | |
| 5249 | I915_WRITE(PCH_3DCGDIS0, |
| 5250 | MARIUNIT_CLOCK_GATE_DISABLE | |
| 5251 | SVSMUNIT_CLOCK_GATE_DISABLE); |
| 5252 | I915_WRITE(PCH_3DCGDIS1, |
| 5253 | VFMUNIT_CLOCK_GATE_DISABLE); |
| 5254 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5255 | /* |
| 5256 | * According to the spec the following bits should be set in |
| 5257 | * order to enable memory self-refresh |
| 5258 | * The bit 22/21 of 0x42004 |
| 5259 | * The bit 5 of 0x42020 |
| 5260 | * The bit 15 of 0x45000 |
| 5261 | */ |
| 5262 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5263 | (I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5264 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 5265 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5266 | I915_WRITE(DISP_ARB_CTL, |
| 5267 | (I915_READ(DISP_ARB_CTL) | |
| 5268 | DISP_FBC_WM_DIS)); |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 5269 | |
| 5270 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5271 | |
| 5272 | /* |
| 5273 | * Based on the document from hardware guys the following bits |
| 5274 | * should be set unconditionally in order to enable FBC. |
| 5275 | * The bit 22 of 0x42000 |
| 5276 | * The bit 22 of 0x42004 |
| 5277 | * The bit 7,8,9 of 0x42020. |
| 5278 | */ |
| 5279 | if (IS_IRONLAKE_M(dev)) { |
Damien Lespiau | 4bb3533 | 2013-06-14 15:23:24 +0100 | [diff] [blame] | 5280 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5281 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 5282 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 5283 | ILK_FBCQ_DIS); |
| 5284 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5285 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5286 | ILK_DPARB_GATE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5287 | } |
| 5288 | |
Damien Lespiau | 4d47e4f | 2012-10-19 17:55:42 +0100 | [diff] [blame] | 5289 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
| 5290 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5291 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5292 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5293 | ILK_ELPIN_409_SELECT); |
| 5294 | I915_WRITE(_3D_CHICKEN2, |
| 5295 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | |
| 5296 | _3D_CHICKEN2_WM_READ_PIPELINED); |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 5297 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5298 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 5299 | I915_WRITE(CACHE_MODE_0, |
| 5300 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5301 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5302 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
| 5303 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 5304 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5305 | g4x_disable_trickle_feed(dev); |
Ville Syrjälä | bdad2b2 | 2013-06-07 10:47:03 +0300 | [diff] [blame] | 5306 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5307 | ibx_init_clock_gating(dev); |
| 5308 | } |
| 5309 | |
| 5310 | static void cpt_init_clock_gating(struct drm_device *dev) |
| 5311 | { |
| 5312 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5313 | int pipe; |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 5314 | uint32_t val; |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5315 | |
| 5316 | /* |
| 5317 | * On Ibex Peak and Cougar Point, we need to disable clock |
| 5318 | * gating for the panel power sequencer or it will fail to |
| 5319 | * start up when no ports are active. |
| 5320 | */ |
Jesse Barnes | cd66407 | 2013-10-02 10:34:19 -0700 | [diff] [blame] | 5321 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
| 5322 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | |
| 5323 | PCH_CPUNIT_CLOCK_GATE_DISABLE); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5324 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
| 5325 | DPLS_EDP_PPS_FIX_DIS); |
Takashi Iwai | 335c07b | 2012-12-11 11:46:29 +0100 | [diff] [blame] | 5326 | /* The below fixes the weird display corruption, a few pixels shifted |
| 5327 | * downward, on (only) LVDS of some HP laptops with IVY. |
| 5328 | */ |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 5329 | for_each_pipe(pipe) { |
Paulo Zanoni | dc4bd2d | 2013-04-08 15:48:08 -0300 | [diff] [blame] | 5330 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
| 5331 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; |
| 5332 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
Rodrigo Vivi | 41aa344 | 2013-05-09 20:03:18 -0300 | [diff] [blame] | 5333 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 5334 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
Paulo Zanoni | dc4bd2d | 2013-04-08 15:48:08 -0300 | [diff] [blame] | 5335 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
| 5336 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; |
| 5337 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; |
Paulo Zanoni | 3f704fa | 2013-04-08 15:48:07 -0300 | [diff] [blame] | 5338 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
| 5339 | } |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5340 | /* WADP0ClockGatingDisable */ |
| 5341 | for_each_pipe(pipe) { |
| 5342 | I915_WRITE(TRANS_CHICKEN1(pipe), |
| 5343 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
| 5344 | } |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5345 | } |
| 5346 | |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 5347 | static void gen6_check_mch_setup(struct drm_device *dev) |
| 5348 | { |
| 5349 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5350 | uint32_t tmp; |
| 5351 | |
| 5352 | tmp = I915_READ(MCH_SSKPD); |
Daniel Vetter | df662a2 | 2014-08-04 11:17:25 +0200 | [diff] [blame] | 5353 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
| 5354 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", |
| 5355 | tmp); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 5356 | } |
| 5357 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5358 | static void gen6_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5359 | { |
| 5360 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 5361 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5362 | |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 5363 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5364 | |
| 5365 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5366 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5367 | ILK_ELPIN_409_SELECT); |
| 5368 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5369 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
Daniel Vetter | 4283908 | 2012-12-14 23:38:28 +0100 | [diff] [blame] | 5370 | I915_WRITE(_3D_CHICKEN, |
| 5371 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); |
| 5372 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5373 | /* WaSetupGtModeTdRowDispatch:snb */ |
Daniel Vetter | 6547fbd | 2012-12-14 23:38:29 +0100 | [diff] [blame] | 5374 | if (IS_SNB_GT1(dev)) |
| 5375 | I915_WRITE(GEN6_GT_MODE, |
| 5376 | _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); |
| 5377 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5378 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
| 5379 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 5380 | |
Ville Syrjälä | 8d85d27 | 2014-02-04 21:59:15 +0200 | [diff] [blame] | 5381 | /* |
| 5382 | * BSpec recoomends 8x4 when MSAA is used, |
| 5383 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 5384 | * |
| 5385 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 5386 | * disable bit, which we don't touch here, but it's good |
| 5387 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | 8d85d27 | 2014-02-04 21:59:15 +0200 | [diff] [blame] | 5388 | */ |
| 5389 | I915_WRITE(GEN6_GT_MODE, |
| 5390 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); |
| 5391 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 5392 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5393 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5394 | I915_WRITE(CACHE_MODE_0, |
Daniel Vetter | 5074329 | 2012-04-26 22:02:54 +0200 | [diff] [blame] | 5395 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5396 | |
| 5397 | I915_WRITE(GEN6_UCGCTL1, |
| 5398 | I915_READ(GEN6_UCGCTL1) | |
| 5399 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | |
| 5400 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
| 5401 | |
| 5402 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock |
| 5403 | * gating disable must be set. Failure to set it results in |
| 5404 | * flickering pixels due to Z write ordering failures after |
| 5405 | * some amount of runtime in the Mesa "fire" demo, and Unigine |
| 5406 | * Sanctuary and Tropics, and apparently anything else with |
| 5407 | * alpha test or pixel discard. |
| 5408 | * |
| 5409 | * According to the spec, bit 11 (RCCUNIT) must also be set, |
| 5410 | * but we didn't debug actual testcases to find it out. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5411 | * |
Ville Syrjälä | ef59318 | 2014-01-22 21:32:47 +0200 | [diff] [blame] | 5412 | * WaDisableRCCUnitClockGating:snb |
| 5413 | * WaDisableRCPBUnitClockGating:snb |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5414 | */ |
| 5415 | I915_WRITE(GEN6_UCGCTL2, |
| 5416 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | |
| 5417 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); |
| 5418 | |
Ville Syrjälä | 5eb146d | 2014-02-04 21:59:16 +0200 | [diff] [blame] | 5419 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
Ville Syrjälä | 743b57d | 2014-02-04 21:59:17 +0200 | [diff] [blame] | 5420 | I915_WRITE(_3D_CHICKEN3, |
| 5421 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5422 | |
| 5423 | /* |
Ville Syrjälä | e927ecd | 2014-02-04 21:59:18 +0200 | [diff] [blame] | 5424 | * Bspec says: |
| 5425 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and |
| 5426 | * 3DSTATE_SF number of SF output attributes is more than 16." |
| 5427 | */ |
| 5428 | I915_WRITE(_3D_CHICKEN3, |
| 5429 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); |
| 5430 | |
| 5431 | /* |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5432 | * According to the spec the following bits should be |
| 5433 | * set in order to enable memory self-refresh and fbc: |
| 5434 | * The bit21 and bit22 of 0x42000 |
| 5435 | * The bit21 and bit22 of 0x42004 |
| 5436 | * The bit5 and bit7 of 0x42020 |
| 5437 | * The bit14 of 0x70180 |
| 5438 | * The bit14 of 0x71180 |
Damien Lespiau | 4bb3533 | 2013-06-14 15:23:24 +0100 | [diff] [blame] | 5439 | * |
| 5440 | * WaFbcAsynchFlipDisableFbcQueue:snb |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5441 | */ |
| 5442 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
| 5443 | I915_READ(ILK_DISPLAY_CHICKEN1) | |
| 5444 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); |
| 5445 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
| 5446 | I915_READ(ILK_DISPLAY_CHICKEN2) | |
| 5447 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 5448 | I915_WRITE(ILK_DSPCLK_GATE_D, |
| 5449 | I915_READ(ILK_DSPCLK_GATE_D) | |
| 5450 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | |
| 5451 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5452 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5453 | g4x_disable_trickle_feed(dev); |
Ben Widawsky | f8f2ac9 | 2012-10-03 19:34:24 -0700 | [diff] [blame] | 5454 | |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5455 | cpt_init_clock_gating(dev); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 5456 | |
| 5457 | gen6_check_mch_setup(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5458 | } |
| 5459 | |
| 5460 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) |
| 5461 | { |
| 5462 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); |
| 5463 | |
Ville Syrjälä | 3aad905 | 2014-01-22 21:32:59 +0200 | [diff] [blame] | 5464 | /* |
Ville Syrjälä | 46680e0 | 2014-01-22 21:33:01 +0200 | [diff] [blame] | 5465 | * WaVSThreadDispatchOverride:ivb,vlv |
Ville Syrjälä | 3aad905 | 2014-01-22 21:32:59 +0200 | [diff] [blame] | 5466 | * |
| 5467 | * This actually overrides the dispatch |
| 5468 | * mode for all thread types. |
| 5469 | */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5470 | reg &= ~GEN7_FF_SCHED_MASK; |
| 5471 | reg |= GEN7_FF_TS_SCHED_HW; |
| 5472 | reg |= GEN7_FF_VS_SCHED_HW; |
| 5473 | reg |= GEN7_FF_DS_SCHED_HW; |
| 5474 | |
| 5475 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); |
| 5476 | } |
| 5477 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 5478 | static void lpt_init_clock_gating(struct drm_device *dev) |
| 5479 | { |
| 5480 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5481 | |
| 5482 | /* |
| 5483 | * TODO: this bit should only be enabled when really needed, then |
| 5484 | * disabled when not needed anymore in order to save power. |
| 5485 | */ |
| 5486 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) |
| 5487 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
| 5488 | I915_READ(SOUTH_DSPCLK_GATE_D) | |
| 5489 | PCH_LP_PARTITION_LEVEL_DISABLE); |
Paulo Zanoni | 0a790cd | 2013-04-17 18:15:49 -0300 | [diff] [blame] | 5490 | |
| 5491 | /* WADPOClockGatingDisable:hsw */ |
| 5492 | I915_WRITE(_TRANSA_CHICKEN1, |
| 5493 | I915_READ(_TRANSA_CHICKEN1) | |
| 5494 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 5495 | } |
| 5496 | |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 5497 | static void lpt_suspend_hw(struct drm_device *dev) |
| 5498 | { |
| 5499 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5500 | |
| 5501 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { |
| 5502 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
| 5503 | |
| 5504 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; |
| 5505 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); |
| 5506 | } |
| 5507 | } |
| 5508 | |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 5509 | static void gen8_init_clock_gating(struct drm_device *dev) |
| 5510 | { |
| 5511 | struct drm_i915_private *dev_priv = dev->dev_private; |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 5512 | enum pipe pipe; |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 5513 | |
| 5514 | I915_WRITE(WM3_LP_ILK, 0); |
| 5515 | I915_WRITE(WM2_LP_ILK, 0); |
| 5516 | I915_WRITE(WM1_LP_ILK, 0); |
Ben Widawsky | 50ed5fb | 2013-11-02 21:07:40 -0700 | [diff] [blame] | 5517 | |
| 5518 | /* FIXME(BDW): Check all the w/a, some might only apply to |
| 5519 | * pre-production hw. */ |
| 5520 | |
Kenneth Graunke | c8966e1 | 2014-02-26 23:59:30 -0800 | [diff] [blame] | 5521 | /* WaDisablePartialInstShootdown:bdw */ |
| 5522 | I915_WRITE(GEN8_ROW_CHICKEN, |
| 5523 | _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); |
| 5524 | |
Kenneth Graunke | 1411e6a | 2014-02-26 23:59:31 -0800 | [diff] [blame] | 5525 | /* WaDisableThreadStallDopClockGating:bdw */ |
| 5526 | /* FIXME: Unclear whether we really need this on production bdw. */ |
| 5527 | I915_WRITE(GEN8_ROW_CHICKEN, |
| 5528 | _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); |
| 5529 | |
Damien Lespiau | 4167e32 | 2014-01-16 16:51:35 +0000 | [diff] [blame] | 5530 | /* |
| 5531 | * This GEN8_CENTROID_PIXEL_OPT_DIS W/A is only needed for |
| 5532 | * pre-production hardware |
| 5533 | */ |
Ben Widawsky | fd392b6 | 2013-11-04 22:52:39 -0800 | [diff] [blame] | 5534 | I915_WRITE(HALF_SLICE_CHICKEN3, |
| 5535 | _MASKED_BIT_ENABLE(GEN8_CENTROID_PIXEL_OPT_DIS)); |
Ben Widawsky | bf66347 | 2013-11-02 21:07:57 -0700 | [diff] [blame] | 5536 | I915_WRITE(HALF_SLICE_CHICKEN3, |
| 5537 | _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); |
Ben Widawsky | 4afe8d3 | 2013-11-02 21:07:55 -0700 | [diff] [blame] | 5538 | I915_WRITE(GAMTARBMODE, _MASKED_BIT_ENABLE(ARB_MODE_BWGTLB_DISABLE)); |
| 5539 | |
Ben Widawsky | 7f88da0 | 2013-11-02 21:07:58 -0700 | [diff] [blame] | 5540 | I915_WRITE(_3D_CHICKEN3, |
Michel Thierry | b3f9ad9 | 2014-07-07 12:40:17 +0100 | [diff] [blame] | 5541 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SDE_LIMIT_FIFO_POLY_DEPTH(2))); |
Ben Widawsky | 7f88da0 | 2013-11-02 21:07:58 -0700 | [diff] [blame] | 5542 | |
Ben Widawsky | a75f362 | 2013-11-02 21:07:59 -0700 | [diff] [blame] | 5543 | I915_WRITE(COMMON_SLICE_CHICKEN2, |
| 5544 | _MASKED_BIT_ENABLE(GEN8_CSC2_SBE_VUE_CACHE_CONSERVATIVE)); |
| 5545 | |
Ben Widawsky | 4c2e7a5 | 2013-11-02 21:08:00 -0700 | [diff] [blame] | 5546 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
| 5547 | _MASKED_BIT_ENABLE(GEN7_SINGLE_SUBSCAN_DISPATCH_ENABLE)); |
| 5548 | |
Ben Widawsky | 242a401 | 2014-04-18 18:04:29 -0300 | [diff] [blame] | 5549 | /* WaDisableDopClockGating:bdw May not be needed for production */ |
| 5550 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 5551 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
| 5552 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 5553 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
Ben Widawsky | 50ed5fb | 2013-11-02 21:07:40 -0700 | [diff] [blame] | 5554 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 5555 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 5556 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 5557 | I915_WRITE(CHICKEN_PAR1_1, |
| 5558 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); |
| 5559 | |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 5560 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
Damien Lespiau | 07d27e2 | 2014-03-03 17:31:46 +0000 | [diff] [blame] | 5561 | for_each_pipe(pipe) { |
| 5562 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
Ville Syrjälä | c7c6562 | 2014-03-05 13:05:45 +0200 | [diff] [blame] | 5563 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
Ville Syrjälä | 8f670bb | 2014-03-05 13:05:47 +0200 | [diff] [blame] | 5564 | BDW_DPRS_MASK_VBLANK_SRD); |
Ben Widawsky | fe4ab3c | 2013-11-02 21:07:54 -0700 | [diff] [blame] | 5565 | } |
Ben Widawsky | 63801f2 | 2013-12-12 17:26:03 -0800 | [diff] [blame] | 5566 | |
| 5567 | /* Use Force Non-Coherent whenever executing a 3D context. This is a |
| 5568 | * workaround for for a possible hang in the unlikely event a TLB |
| 5569 | * invalidation occurs during a PSD flush. |
| 5570 | */ |
| 5571 | I915_WRITE(HDC_CHICKEN0, |
| 5572 | I915_READ(HDC_CHICKEN0) | |
| 5573 | _MASKED_BIT_ENABLE(HDC_FORCE_NON_COHERENT)); |
Ben Widawsky | ab57fff | 2013-12-12 15:28:04 -0800 | [diff] [blame] | 5574 | |
| 5575 | /* WaVSRefCountFullforceMissDisable:bdw */ |
| 5576 | /* WaDSRefCountFullforceMissDisable:bdw */ |
| 5577 | I915_WRITE(GEN7_FF_THREAD_MODE, |
| 5578 | I915_READ(GEN7_FF_THREAD_MODE) & |
| 5579 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); |
Ville Syrjälä | 36075a4 | 2014-02-04 21:59:21 +0200 | [diff] [blame] | 5580 | |
| 5581 | /* |
| 5582 | * BSpec recommends 8x4 when MSAA is used, |
| 5583 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 5584 | * |
| 5585 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 5586 | * disable bit, which we don't touch here, but it's good |
| 5587 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | 36075a4 | 2014-02-04 21:59:21 +0200 | [diff] [blame] | 5588 | */ |
| 5589 | I915_WRITE(GEN7_GT_MODE, |
| 5590 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); |
Ville Syrjälä | 295e8bb | 2014-02-27 21:59:01 +0200 | [diff] [blame] | 5591 | |
| 5592 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
| 5593 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); |
Ville Syrjälä | 4f1ca9e | 2014-02-27 21:59:02 +0200 | [diff] [blame] | 5594 | |
| 5595 | /* WaDisableSDEUnitClockGating:bdw */ |
| 5596 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
| 5597 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
Damien Lespiau | 5d70868 | 2014-03-26 18:41:51 +0000 | [diff] [blame] | 5598 | |
| 5599 | /* Wa4x4STCOptimizationDisable:bdw */ |
| 5600 | I915_WRITE(CACHE_MODE_1, |
| 5601 | _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 5602 | } |
| 5603 | |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5604 | static void haswell_init_clock_gating(struct drm_device *dev) |
| 5605 | { |
| 5606 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5607 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 5608 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5609 | |
Francisco Jerez | f3fc488 | 2013-10-02 15:53:16 -0700 | [diff] [blame] | 5610 | /* L3 caching of data atomics doesn't work -- disable it. */ |
| 5611 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); |
| 5612 | I915_WRITE(HSW_ROW_CHICKEN3, |
| 5613 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); |
| 5614 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5615 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5616 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 5617 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 5618 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 5619 | |
Ville Syrjälä | e36ea7f | 2014-01-22 21:33:00 +0200 | [diff] [blame] | 5620 | /* WaVSRefCountFullforceMissDisable:hsw */ |
| 5621 | I915_WRITE(GEN7_FF_THREAD_MODE, |
| 5622 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5623 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5624 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
| 5625 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 5626 | |
Chia-I Wu | fe27c60 | 2014-01-28 13:29:33 +0800 | [diff] [blame] | 5627 | /* enable HiZ Raw Stall Optimization */ |
| 5628 | I915_WRITE(CACHE_MODE_0_GEN7, |
| 5629 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); |
| 5630 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5631 | /* WaDisable4x2SubspanOptimization:hsw */ |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5632 | I915_WRITE(CACHE_MODE_1, |
| 5633 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Eugeni Dodonov | 1544d9d | 2012-07-02 11:51:10 -0300 | [diff] [blame] | 5634 | |
Ville Syrjälä | a12c496 | 2014-02-04 21:59:20 +0200 | [diff] [blame] | 5635 | /* |
| 5636 | * BSpec recommends 8x4 when MSAA is used, |
| 5637 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 5638 | * |
| 5639 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 5640 | * disable bit, which we don't touch here, but it's good |
| 5641 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | a12c496 | 2014-02-04 21:59:20 +0200 | [diff] [blame] | 5642 | */ |
| 5643 | I915_WRITE(GEN7_GT_MODE, |
| 5644 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); |
| 5645 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5646 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
Ben Widawsky | e3dff58 | 2013-03-20 14:49:14 -0700 | [diff] [blame] | 5647 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
| 5648 | |
Paulo Zanoni | 90a8864 | 2013-05-03 17:23:45 -0300 | [diff] [blame] | 5649 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
| 5650 | I915_WRITE(CHICKEN_PAR1_1, |
| 5651 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); |
Eugeni Dodonov | 1544d9d | 2012-07-02 11:51:10 -0300 | [diff] [blame] | 5652 | |
Paulo Zanoni | 17a303e | 2012-11-20 15:12:07 -0200 | [diff] [blame] | 5653 | lpt_init_clock_gating(dev); |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 5654 | } |
| 5655 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5656 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5657 | { |
| 5658 | struct drm_i915_private *dev_priv = dev->dev_private; |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 5659 | uint32_t snpcr; |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5660 | |
Ville Syrjälä | 017636c | 2013-12-05 15:51:37 +0200 | [diff] [blame] | 5661 | ilk_init_lp_watermarks(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5662 | |
Damien Lespiau | 231e54f | 2012-10-19 17:55:41 +0100 | [diff] [blame] | 5663 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5664 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5665 | /* WaDisableEarlyCull:ivb */ |
Jesse Barnes | 87f8020 | 2012-10-02 17:43:41 -0500 | [diff] [blame] | 5666 | I915_WRITE(_3D_CHICKEN3, |
| 5667 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
| 5668 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5669 | /* WaDisableBackToBackFlipFix:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5670 | I915_WRITE(IVB_CHICKEN3, |
| 5671 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 5672 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 5673 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5674 | /* WaDisablePSDDualDispatchEnable:ivb */ |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 5675 | if (IS_IVB_GT1(dev)) |
| 5676 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
| 5677 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 5678 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5679 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
| 5680 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 5681 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5682 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5683 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
| 5684 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); |
| 5685 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5686 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5687 | I915_WRITE(GEN7_L3CNTLREG1, |
| 5688 | GEN7_WA_FOR_GEN7_L3_CONTROL); |
| 5689 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 5690 | GEN7_WA_L3_CHICKEN_MODE); |
| 5691 | if (IS_IVB_GT1(dev)) |
| 5692 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 5693 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
Ville Syrjälä | 412236c | 2014-01-22 21:32:44 +0200 | [diff] [blame] | 5694 | else { |
| 5695 | /* must write both registers */ |
| 5696 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 5697 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 5698 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
| 5699 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
Ville Syrjälä | 412236c | 2014-01-22 21:32:44 +0200 | [diff] [blame] | 5700 | } |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5701 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5702 | /* WaForceL3Serialization:ivb */ |
Jesse Barnes | 61939d9 | 2012-10-02 17:43:38 -0500 | [diff] [blame] | 5703 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
| 5704 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
| 5705 | |
Ville Syrjälä | 1b80a19a | 2014-01-22 21:32:53 +0200 | [diff] [blame] | 5706 | /* |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5707 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5708 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5709 | */ |
| 5710 | I915_WRITE(GEN6_UCGCTL2, |
Ville Syrjälä | 28acf3b | 2014-01-22 21:32:48 +0200 | [diff] [blame] | 5711 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5712 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5713 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5714 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 5715 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 5716 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 5717 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5718 | g4x_disable_trickle_feed(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5719 | |
| 5720 | gen7_setup_fixed_func_scheduler(dev_priv); |
Daniel Vetter | 97e1930 | 2012-04-24 16:00:21 +0200 | [diff] [blame] | 5721 | |
Chris Wilson | 2272134 | 2014-03-04 09:41:43 +0000 | [diff] [blame] | 5722 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
| 5723 | /* enable HiZ Raw Stall Optimization */ |
| 5724 | I915_WRITE(CACHE_MODE_0_GEN7, |
| 5725 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); |
| 5726 | } |
Chia-I Wu | 116f2b6 | 2014-01-28 13:29:34 +0800 | [diff] [blame] | 5727 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5728 | /* WaDisable4x2SubspanOptimization:ivb */ |
Daniel Vetter | 97e1930 | 2012-04-24 16:00:21 +0200 | [diff] [blame] | 5729 | I915_WRITE(CACHE_MODE_1, |
| 5730 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 5731 | |
Ville Syrjälä | a607c1a | 2014-02-04 21:59:19 +0200 | [diff] [blame] | 5732 | /* |
| 5733 | * BSpec recommends 8x4 when MSAA is used, |
| 5734 | * however in practice 16x4 seems fastest. |
Ville Syrjälä | c5c98a5 | 2014-02-05 12:43:47 +0200 | [diff] [blame] | 5735 | * |
| 5736 | * Note that PS/WM thread counts depend on the WIZ hashing |
| 5737 | * disable bit, which we don't touch here, but it's good |
| 5738 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). |
Ville Syrjälä | a607c1a | 2014-02-04 21:59:19 +0200 | [diff] [blame] | 5739 | */ |
| 5740 | I915_WRITE(GEN7_GT_MODE, |
| 5741 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); |
| 5742 | |
Ben Widawsky | 2084822 | 2012-05-04 18:58:59 -0700 | [diff] [blame] | 5743 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
| 5744 | snpcr &= ~GEN6_MBC_SNPCR_MASK; |
| 5745 | snpcr |= GEN6_MBC_SNPCR_MED; |
| 5746 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); |
Daniel Vetter | 3107bd4 | 2012-10-31 22:52:31 +0100 | [diff] [blame] | 5747 | |
Ben Widawsky | ab5c608 | 2013-04-05 13:12:41 -0700 | [diff] [blame] | 5748 | if (!HAS_PCH_NOP(dev)) |
| 5749 | cpt_init_clock_gating(dev); |
Daniel Vetter | 1d7aaa0 | 2013-02-09 21:03:42 +0100 | [diff] [blame] | 5750 | |
| 5751 | gen6_check_mch_setup(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5752 | } |
| 5753 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5754 | static void valleyview_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5755 | { |
| 5756 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | 85b1d7b | 2013-11-04 11:52:45 -0800 | [diff] [blame] | 5757 | u32 val; |
| 5758 | |
| 5759 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5760 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
| 5761 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5762 | switch ((val >> 6) & 3) { |
| 5763 | case 0: |
Deepak S | f6d5194 | 2014-04-03 21:01:28 +0530 | [diff] [blame] | 5764 | case 1: |
Jesse Barnes | 85b1d7b | 2013-11-04 11:52:45 -0800 | [diff] [blame] | 5765 | dev_priv->mem_freq = 800; |
| 5766 | break; |
Jesse Barnes | f64a28a | 2013-11-04 16:07:00 -0800 | [diff] [blame] | 5767 | case 2: |
Deepak S | f6d5194 | 2014-04-03 21:01:28 +0530 | [diff] [blame] | 5768 | dev_priv->mem_freq = 1066; |
Jesse Barnes | 85b1d7b | 2013-11-04 11:52:45 -0800 | [diff] [blame] | 5769 | break; |
Jesse Barnes | f64a28a | 2013-11-04 16:07:00 -0800 | [diff] [blame] | 5770 | case 3: |
Chon Ming Lee | 2325991 | 2013-11-07 15:23:26 +0800 | [diff] [blame] | 5771 | dev_priv->mem_freq = 1333; |
Jesse Barnes | f64a28a | 2013-11-04 16:07:00 -0800 | [diff] [blame] | 5772 | break; |
Jesse Barnes | 85b1d7b | 2013-11-04 11:52:45 -0800 | [diff] [blame] | 5773 | } |
| 5774 | DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5775 | |
Ville Syrjälä | d7fe0cc | 2013-05-21 18:01:50 +0300 | [diff] [blame] | 5776 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5777 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5778 | /* WaDisableEarlyCull:vlv */ |
Jesse Barnes | 87f8020 | 2012-10-02 17:43:41 -0500 | [diff] [blame] | 5779 | I915_WRITE(_3D_CHICKEN3, |
| 5780 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); |
| 5781 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5782 | /* WaDisableBackToBackFlipFix:vlv */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5783 | I915_WRITE(IVB_CHICKEN3, |
| 5784 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | |
| 5785 | CHICKEN3_DGMG_DONE_FIX_DISABLE); |
| 5786 | |
Ville Syrjälä | fad7d36 | 2014-01-22 21:32:39 +0200 | [diff] [blame] | 5787 | /* WaPsdDispatchEnable:vlv */ |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5788 | /* WaDisablePSDDualDispatchEnable:vlv */ |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 5789 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
Jesse Barnes | d3bc030 | 2013-03-08 10:45:51 -0800 | [diff] [blame] | 5790 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
| 5791 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); |
Jesse Barnes | 12f3382 | 2012-10-25 12:15:45 -0700 | [diff] [blame] | 5792 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5793 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
| 5794 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 5795 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5796 | /* WaForceL3Serialization:vlv */ |
Jesse Barnes | 61939d9 | 2012-10-02 17:43:38 -0500 | [diff] [blame] | 5797 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
| 5798 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); |
| 5799 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5800 | /* WaDisableDopClockGating:vlv */ |
Jesse Barnes | 8ab4397 | 2012-10-25 12:15:42 -0700 | [diff] [blame] | 5801 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 5802 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
| 5803 | |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5804 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5805 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
| 5806 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | |
| 5807 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); |
| 5808 | |
Ville Syrjälä | 46680e0 | 2014-01-22 21:33:01 +0200 | [diff] [blame] | 5809 | gen7_setup_fixed_func_scheduler(dev_priv); |
| 5810 | |
Ville Syrjälä | 3c0edae | 2014-01-22 21:32:56 +0200 | [diff] [blame] | 5811 | /* |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5812 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5813 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5814 | */ |
| 5815 | I915_WRITE(GEN6_UCGCTL2, |
Ville Syrjälä | 3c0edae | 2014-01-22 21:32:56 +0200 | [diff] [blame] | 5816 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
Jesse Barnes | 0f846f8 | 2012-06-14 11:04:47 -0700 | [diff] [blame] | 5817 | |
Akash Goel | c98f506 | 2014-03-24 23:00:07 +0530 | [diff] [blame] | 5818 | /* WaDisableL3Bank2xClockGate:vlv |
| 5819 | * Disabling L3 clock gating- MMIO 940c[25] = 1 |
| 5820 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ |
| 5821 | I915_WRITE(GEN7_UCGCTL4, |
| 5822 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); |
Jesse Barnes | e3f33d4 | 2012-06-14 11:04:50 -0700 | [diff] [blame] | 5823 | |
Ville Syrjälä | e0d8d59 | 2013-06-12 22:11:18 +0300 | [diff] [blame] | 5824 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5825 | |
Ville Syrjälä | afd58e7 | 2014-01-22 21:33:03 +0200 | [diff] [blame] | 5826 | /* |
| 5827 | * BSpec says this must be set, even though |
| 5828 | * WaDisable4x2SubspanOptimization isn't listed for VLV. |
| 5829 | */ |
Daniel Vetter | 6b26c86 | 2012-04-24 14:04:12 +0200 | [diff] [blame] | 5830 | I915_WRITE(CACHE_MODE_1, |
| 5831 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); |
Jesse Barnes | 7983117 | 2012-06-20 10:53:12 -0700 | [diff] [blame] | 5832 | |
| 5833 | /* |
Ville Syrjälä | 031994e | 2014-01-22 21:32:46 +0200 | [diff] [blame] | 5834 | * WaIncreaseL3CreditsForVLVB0:vlv |
| 5835 | * This is the hardware default actually. |
| 5836 | */ |
| 5837 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); |
| 5838 | |
| 5839 | /* |
Damien Lespiau | ecdb4eb7 | 2013-05-03 18:48:10 +0100 | [diff] [blame] | 5840 | * WaDisableVLVClockGating_VBIIssue:vlv |
Jesse Barnes | 2d80957 | 2012-10-25 12:15:44 -0700 | [diff] [blame] | 5841 | * Disable clock gating on th GCFG unit to prevent a delay |
| 5842 | * in the reporting of vblank events. |
| 5843 | */ |
Ville Syrjälä | 7a0d1ee | 2014-01-22 21:33:04 +0200 | [diff] [blame] | 5844 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5845 | } |
| 5846 | |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 5847 | static void cherryview_init_clock_gating(struct drm_device *dev) |
| 5848 | { |
| 5849 | struct drm_i915_private *dev_priv = dev->dev_private; |
Deepak S | 67c3bf6 | 2014-07-10 13:16:24 +0530 | [diff] [blame] | 5850 | u32 val; |
| 5851 | |
| 5852 | mutex_lock(&dev_priv->rps.hw_lock); |
| 5853 | val = vlv_punit_read(dev_priv, CCK_FUSE_REG); |
| 5854 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 5855 | switch ((val >> 2) & 0x7) { |
| 5856 | case 0: |
| 5857 | case 1: |
| 5858 | dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_200; |
| 5859 | dev_priv->mem_freq = 1600; |
| 5860 | break; |
| 5861 | case 2: |
| 5862 | dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_267; |
| 5863 | dev_priv->mem_freq = 1600; |
| 5864 | break; |
| 5865 | case 3: |
| 5866 | dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_333; |
| 5867 | dev_priv->mem_freq = 2000; |
| 5868 | break; |
| 5869 | case 4: |
| 5870 | dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_320; |
| 5871 | dev_priv->mem_freq = 1600; |
| 5872 | break; |
| 5873 | case 5: |
| 5874 | dev_priv->rps.cz_freq = CHV_CZ_CLOCK_FREQ_MODE_400; |
| 5875 | dev_priv->mem_freq = 1600; |
| 5876 | break; |
| 5877 | } |
| 5878 | DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 5879 | |
| 5880 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
| 5881 | |
| 5882 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
Ville Syrjälä | dd811e7 | 2014-04-09 13:28:33 +0300 | [diff] [blame] | 5883 | |
| 5884 | /* WaDisablePartialInstShootdown:chv */ |
| 5885 | I915_WRITE(GEN8_ROW_CHICKEN, |
| 5886 | _MASKED_BIT_ENABLE(PARTIAL_INSTRUCTION_SHOOTDOWN_DISABLE)); |
Ville Syrjälä | a706802 | 2014-04-09 13:28:34 +0300 | [diff] [blame] | 5887 | |
| 5888 | /* WaDisableThreadStallDopClockGating:chv */ |
| 5889 | I915_WRITE(GEN8_ROW_CHICKEN, |
| 5890 | _MASKED_BIT_ENABLE(STALL_DOP_GATING_DISABLE)); |
Ville Syrjälä | 232ce33 | 2014-04-09 13:28:35 +0300 | [diff] [blame] | 5891 | |
| 5892 | /* WaVSRefCountFullforceMissDisable:chv */ |
| 5893 | /* WaDSRefCountFullforceMissDisable:chv */ |
| 5894 | I915_WRITE(GEN7_FF_THREAD_MODE, |
| 5895 | I915_READ(GEN7_FF_THREAD_MODE) & |
| 5896 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); |
Ville Syrjälä | acea6f9 | 2014-04-09 13:28:36 +0300 | [diff] [blame] | 5897 | |
| 5898 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ |
| 5899 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
| 5900 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); |
Ville Syrjälä | 0846697 | 2014-04-09 13:28:37 +0300 | [diff] [blame] | 5901 | |
| 5902 | /* WaDisableCSUnitClockGating:chv */ |
| 5903 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | |
| 5904 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); |
Ville Syrjälä | c631780 | 2014-04-09 13:28:38 +0300 | [diff] [blame] | 5905 | |
| 5906 | /* WaDisableSDEUnitClockGating:chv */ |
| 5907 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
| 5908 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
Rafael Barbalho | e0d34ce | 2014-04-09 13:28:40 +0300 | [diff] [blame] | 5909 | |
| 5910 | /* WaDisableSamplerPowerBypass:chv (pre-production hw) */ |
| 5911 | I915_WRITE(HALF_SLICE_CHICKEN3, |
| 5912 | _MASKED_BIT_ENABLE(GEN8_SAMPLER_POWER_BYPASS_DIS)); |
Ville Syrjälä | e4443e4 | 2014-04-09 13:28:41 +0300 | [diff] [blame] | 5913 | |
| 5914 | /* WaDisableGunitClockGating:chv (pre-production hw) */ |
| 5915 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) | |
| 5916 | GINT_DIS); |
| 5917 | |
| 5918 | /* WaDisableFfDopClockGating:chv (pre-production hw) */ |
| 5919 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
| 5920 | _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE)); |
| 5921 | |
| 5922 | /* WaDisableDopClockGating:chv (pre-production hw) */ |
| 5923 | I915_WRITE(GEN7_ROW_CHICKEN2, |
| 5924 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); |
| 5925 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | |
| 5926 | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 5927 | } |
| 5928 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5929 | static void g4x_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5930 | { |
| 5931 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5932 | uint32_t dspclk_gate; |
| 5933 | |
| 5934 | I915_WRITE(RENCLK_GATE_D1, 0); |
| 5935 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | |
| 5936 | GS_UNIT_CLOCK_GATE_DISABLE | |
| 5937 | CL_UNIT_CLOCK_GATE_DISABLE); |
| 5938 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 5939 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | |
| 5940 | OVRUNIT_CLOCK_GATE_DISABLE | |
| 5941 | OVCUNIT_CLOCK_GATE_DISABLE; |
| 5942 | if (IS_GM45(dev)) |
| 5943 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
| 5944 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); |
Daniel Vetter | 4358a37 | 2012-10-18 11:49:51 +0200 | [diff] [blame] | 5945 | |
| 5946 | /* WaDisableRenderCachePipelinedFlush */ |
| 5947 | I915_WRITE(CACHE_MODE_0, |
| 5948 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); |
Ville Syrjälä | de1aa62 | 2013-06-07 10:47:01 +0300 | [diff] [blame] | 5949 | |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5950 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
| 5951 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
| 5952 | |
Ville Syrjälä | 0e088b8 | 2013-06-07 10:47:04 +0300 | [diff] [blame] | 5953 | g4x_disable_trickle_feed(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5954 | } |
| 5955 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5956 | static void crestline_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5957 | { |
| 5958 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5959 | |
| 5960 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
| 5961 | I915_WRITE(RENCLK_GATE_D2, 0); |
| 5962 | I915_WRITE(DSPCLK_GATE_D, 0); |
| 5963 | I915_WRITE(RAMCLK_GATE_D, 0); |
| 5964 | I915_WRITE16(DEUC, 0); |
Ville Syrjälä | 20f9496 | 2013-06-07 10:47:02 +0300 | [diff] [blame] | 5965 | I915_WRITE(MI_ARB_STATE, |
| 5966 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5967 | |
| 5968 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ |
| 5969 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5970 | } |
| 5971 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5972 | static void broadwater_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5973 | { |
| 5974 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5975 | |
| 5976 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
| 5977 | I965_RCC_CLOCK_GATE_DISABLE | |
| 5978 | I965_RCPB_CLOCK_GATE_DISABLE | |
| 5979 | I965_ISC_CLOCK_GATE_DISABLE | |
| 5980 | I965_FBC_CLOCK_GATE_DISABLE); |
| 5981 | I915_WRITE(RENCLK_GATE_D2, 0); |
Ville Syrjälä | 20f9496 | 2013-06-07 10:47:02 +0300 | [diff] [blame] | 5982 | I915_WRITE(MI_ARB_STATE, |
| 5983 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); |
Akash Goel | 4e04632 | 2014-04-04 17:14:38 +0530 | [diff] [blame] | 5984 | |
| 5985 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ |
| 5986 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5987 | } |
| 5988 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 5989 | static void gen3_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 5990 | { |
| 5991 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 5992 | u32 dstate = I915_READ(D_STATE); |
| 5993 | |
| 5994 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | |
| 5995 | DSTATE_DOT_CLOCK_GATING; |
| 5996 | I915_WRITE(D_STATE, dstate); |
Chris Wilson | 13a86b8 | 2012-04-24 14:51:43 +0100 | [diff] [blame] | 5997 | |
| 5998 | if (IS_PINEVIEW(dev)) |
| 5999 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
Daniel Vetter | 974a3b0 | 2012-09-09 11:54:16 +0200 | [diff] [blame] | 6000 | |
| 6001 | /* IIR "flip pending" means done if this bit is set */ |
| 6002 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); |
Ville Syrjälä | 12fabbcb9 | 2014-02-25 15:13:38 +0200 | [diff] [blame] | 6003 | |
| 6004 | /* interrupts should cause a wake up from C3 */ |
Ville Syrjälä | 3299254 | 2014-02-25 15:13:39 +0200 | [diff] [blame] | 6005 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
Ville Syrjälä | dbb4274 | 2014-02-25 15:13:41 +0200 | [diff] [blame] | 6006 | |
| 6007 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 6008 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6009 | } |
| 6010 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6011 | static void i85x_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6012 | { |
| 6013 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6014 | |
| 6015 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
Ville Syrjälä | 54e472a | 2014-02-25 15:13:40 +0200 | [diff] [blame] | 6016 | |
| 6017 | /* interrupts should cause a wake up from C3 */ |
| 6018 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | |
| 6019 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6020 | } |
| 6021 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 6022 | static void i830_init_clock_gating(struct drm_device *dev) |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6023 | { |
| 6024 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6025 | |
| 6026 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); |
| 6027 | } |
| 6028 | |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6029 | void intel_init_clock_gating(struct drm_device *dev) |
| 6030 | { |
| 6031 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 6032 | |
| 6033 | dev_priv->display.init_clock_gating(dev); |
Eugeni Dodonov | 6f1d69b | 2012-04-18 15:29:25 -0300 | [diff] [blame] | 6034 | } |
| 6035 | |
Imre Deak | 7d708ee | 2013-04-17 14:04:50 +0300 | [diff] [blame] | 6036 | void intel_suspend_hw(struct drm_device *dev) |
| 6037 | { |
| 6038 | if (HAS_PCH_LPT(dev)) |
| 6039 | lpt_suspend_hw(dev); |
| 6040 | } |
| 6041 | |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6042 | #define for_each_power_well(i, power_well, domain_mask, power_domains) \ |
| 6043 | for (i = 0; \ |
| 6044 | i < (power_domains)->power_well_count && \ |
| 6045 | ((power_well) = &(power_domains)->power_wells[i]); \ |
| 6046 | i++) \ |
| 6047 | if ((power_well)->domains & (domain_mask)) |
| 6048 | |
| 6049 | #define for_each_power_well_rev(i, power_well, domain_mask, power_domains) \ |
| 6050 | for (i = (power_domains)->power_well_count - 1; \ |
| 6051 | i >= 0 && ((power_well) = &(power_domains)->power_wells[i]);\ |
| 6052 | i--) \ |
| 6053 | if ((power_well)->domains & (domain_mask)) |
| 6054 | |
Paulo Zanoni | 15d199e | 2013-03-22 14:14:13 -0300 | [diff] [blame] | 6055 | /** |
| 6056 | * We should only use the power well if we explicitly asked the hardware to |
| 6057 | * enable it, so check if it's enabled and also check if we've requested it to |
| 6058 | * be enabled. |
| 6059 | */ |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6060 | static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv, |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6061 | struct i915_power_well *power_well) |
| 6062 | { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6063 | return I915_READ(HSW_PWR_WELL_DRIVER) == |
| 6064 | (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED); |
| 6065 | } |
| 6066 | |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 6067 | bool intel_display_power_enabled_unlocked(struct drm_i915_private *dev_priv, |
| 6068 | enum intel_display_power_domain domain) |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 6069 | { |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 6070 | struct i915_power_domains *power_domains; |
Imre Deak | b8c000d | 2014-06-02 14:21:10 +0300 | [diff] [blame] | 6071 | struct i915_power_well *power_well; |
| 6072 | bool is_enabled; |
| 6073 | int i; |
| 6074 | |
| 6075 | if (dev_priv->pm.suspended) |
| 6076 | return false; |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 6077 | |
| 6078 | power_domains = &dev_priv->power_domains; |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 6079 | |
Imre Deak | b8c000d | 2014-06-02 14:21:10 +0300 | [diff] [blame] | 6080 | is_enabled = true; |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 6081 | |
Imre Deak | b8c000d | 2014-06-02 14:21:10 +0300 | [diff] [blame] | 6082 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
| 6083 | if (power_well->always_on) |
| 6084 | continue; |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 6085 | |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 6086 | if (!power_well->hw_enabled) { |
Imre Deak | b8c000d | 2014-06-02 14:21:10 +0300 | [diff] [blame] | 6087 | is_enabled = false; |
| 6088 | break; |
| 6089 | } |
| 6090 | } |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 6091 | |
Imre Deak | b8c000d | 2014-06-02 14:21:10 +0300 | [diff] [blame] | 6092 | return is_enabled; |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 6093 | } |
| 6094 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6095 | bool intel_display_power_enabled(struct drm_i915_private *dev_priv, |
Paulo Zanoni | b97186f | 2013-05-03 12:15:36 -0300 | [diff] [blame] | 6096 | enum intel_display_power_domain domain) |
Paulo Zanoni | 15d199e | 2013-03-22 14:14:13 -0300 | [diff] [blame] | 6097 | { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6098 | struct i915_power_domains *power_domains; |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 6099 | bool ret; |
Paulo Zanoni | 882244a | 2014-04-01 14:55:12 -0300 | [diff] [blame] | 6100 | |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6101 | power_domains = &dev_priv->power_domains; |
| 6102 | |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6103 | mutex_lock(&power_domains->lock); |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 6104 | ret = intel_display_power_enabled_unlocked(dev_priv, domain); |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6105 | mutex_unlock(&power_domains->lock); |
| 6106 | |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 6107 | return ret; |
Paulo Zanoni | 15d199e | 2013-03-22 14:14:13 -0300 | [diff] [blame] | 6108 | } |
| 6109 | |
Imre Deak | 93c73e8 | 2014-02-18 00:02:19 +0200 | [diff] [blame] | 6110 | /* |
| 6111 | * Starting with Haswell, we have a "Power Down Well" that can be turned off |
| 6112 | * when not needed anymore. We have 4 registers that can request the power well |
| 6113 | * to be enabled, and it will only be disabled if none of the registers is |
| 6114 | * requesting it to be enabled. |
| 6115 | */ |
Paulo Zanoni | d5e8fdc | 2013-12-11 18:50:09 -0200 | [diff] [blame] | 6116 | static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv) |
| 6117 | { |
| 6118 | struct drm_device *dev = dev_priv->dev; |
Paulo Zanoni | d5e8fdc | 2013-12-11 18:50:09 -0200 | [diff] [blame] | 6119 | |
Paulo Zanoni | f9dcb0d | 2013-12-11 18:50:10 -0200 | [diff] [blame] | 6120 | /* |
| 6121 | * After we re-enable the power well, if we touch VGA register 0x3d5 |
| 6122 | * we'll get unclaimed register interrupts. This stops after we write |
| 6123 | * anything to the VGA MSR register. The vgacon module uses this |
| 6124 | * register all the time, so if we unbind our driver and, as a |
| 6125 | * consequence, bind vgacon, we'll get stuck in an infinite loop at |
| 6126 | * console_unlock(). So make here we touch the VGA MSR register, making |
| 6127 | * sure vgacon can keep working normally without triggering interrupts |
| 6128 | * and error messages. |
| 6129 | */ |
| 6130 | vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 6131 | outb(inb(VGA_MSR_READ), VGA_MSR_WRITE); |
| 6132 | vga_put(dev->pdev, VGA_RSRC_LEGACY_IO); |
| 6133 | |
Paulo Zanoni | d49bdb0 | 2014-07-04 11:50:31 -0300 | [diff] [blame] | 6134 | if (IS_BROADWELL(dev)) |
| 6135 | gen8_irq_power_well_post_enable(dev_priv); |
Paulo Zanoni | d5e8fdc | 2013-12-11 18:50:09 -0200 | [diff] [blame] | 6136 | } |
| 6137 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6138 | static void hsw_set_power_well(struct drm_i915_private *dev_priv, |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6139 | struct i915_power_well *power_well, bool enable) |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 6140 | { |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 6141 | bool is_enabled, enable_requested; |
| 6142 | uint32_t tmp; |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 6143 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 6144 | tmp = I915_READ(HSW_PWR_WELL_DRIVER); |
Paulo Zanoni | 6aedd1f | 2013-08-02 16:22:25 -0300 | [diff] [blame] | 6145 | is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED; |
| 6146 | enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST; |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 6147 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 6148 | if (enable) { |
| 6149 | if (!enable_requested) |
Paulo Zanoni | 6aedd1f | 2013-08-02 16:22:25 -0300 | [diff] [blame] | 6150 | I915_WRITE(HSW_PWR_WELL_DRIVER, |
| 6151 | HSW_PWR_WELL_ENABLE_REQUEST); |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 6152 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 6153 | if (!is_enabled) { |
| 6154 | DRM_DEBUG_KMS("Enabling power well\n"); |
| 6155 | if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) & |
Paulo Zanoni | 6aedd1f | 2013-08-02 16:22:25 -0300 | [diff] [blame] | 6156 | HSW_PWR_WELL_STATE_ENABLED), 20)) |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 6157 | DRM_ERROR("Timeout enabling power well\n"); |
| 6158 | } |
Ben Widawsky | 596cc11 | 2013-11-11 14:46:28 -0800 | [diff] [blame] | 6159 | |
Paulo Zanoni | d5e8fdc | 2013-12-11 18:50:09 -0200 | [diff] [blame] | 6160 | hsw_power_well_post_enable(dev_priv); |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 6161 | } else { |
| 6162 | if (enable_requested) { |
| 6163 | I915_WRITE(HSW_PWR_WELL_DRIVER, 0); |
Paulo Zanoni | 9dbd8fe | 2013-07-23 10:48:11 -0300 | [diff] [blame] | 6164 | POSTING_READ(HSW_PWR_WELL_DRIVER); |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 6165 | DRM_DEBUG_KMS("Requesting to disable the power well\n"); |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 6166 | } |
| 6167 | } |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 6168 | } |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 6169 | |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6170 | static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 6171 | struct i915_power_well *power_well) |
| 6172 | { |
| 6173 | hsw_set_power_well(dev_priv, power_well, power_well->count > 0); |
| 6174 | |
| 6175 | /* |
| 6176 | * We're taking over the BIOS, so clear any requests made by it since |
| 6177 | * the driver is in charge now. |
| 6178 | */ |
| 6179 | if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST) |
| 6180 | I915_WRITE(HSW_PWR_WELL_BIOS, 0); |
| 6181 | } |
| 6182 | |
| 6183 | static void hsw_power_well_enable(struct drm_i915_private *dev_priv, |
| 6184 | struct i915_power_well *power_well) |
| 6185 | { |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6186 | hsw_set_power_well(dev_priv, power_well, true); |
| 6187 | } |
| 6188 | |
| 6189 | static void hsw_power_well_disable(struct drm_i915_private *dev_priv, |
| 6190 | struct i915_power_well *power_well) |
| 6191 | { |
| 6192 | hsw_set_power_well(dev_priv, power_well, false); |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6193 | } |
| 6194 | |
Imre Deak | a45f4466 | 2014-03-04 19:22:56 +0200 | [diff] [blame] | 6195 | static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv, |
| 6196 | struct i915_power_well *power_well) |
| 6197 | { |
| 6198 | } |
| 6199 | |
| 6200 | static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv, |
| 6201 | struct i915_power_well *power_well) |
| 6202 | { |
| 6203 | return true; |
| 6204 | } |
| 6205 | |
Ville Syrjälä | d2011dc | 2014-06-13 13:37:56 +0300 | [diff] [blame] | 6206 | static void vlv_set_power_well(struct drm_i915_private *dev_priv, |
| 6207 | struct i915_power_well *power_well, bool enable) |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6208 | { |
Ville Syrjälä | d2011dc | 2014-06-13 13:37:56 +0300 | [diff] [blame] | 6209 | enum punit_power_well power_well_id = power_well->data; |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6210 | u32 mask; |
| 6211 | u32 state; |
| 6212 | u32 ctrl; |
| 6213 | |
| 6214 | mask = PUNIT_PWRGT_MASK(power_well_id); |
| 6215 | state = enable ? PUNIT_PWRGT_PWR_ON(power_well_id) : |
| 6216 | PUNIT_PWRGT_PWR_GATE(power_well_id); |
| 6217 | |
| 6218 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6219 | |
| 6220 | #define COND \ |
| 6221 | ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) |
| 6222 | |
| 6223 | if (COND) |
| 6224 | goto out; |
| 6225 | |
| 6226 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); |
| 6227 | ctrl &= ~mask; |
| 6228 | ctrl |= state; |
| 6229 | vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl); |
| 6230 | |
| 6231 | if (wait_for(COND, 100)) |
| 6232 | DRM_ERROR("timout setting power well state %08x (%08x)\n", |
| 6233 | state, |
| 6234 | vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); |
| 6235 | |
| 6236 | #undef COND |
| 6237 | |
| 6238 | out: |
| 6239 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 6240 | } |
| 6241 | |
| 6242 | static void vlv_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 6243 | struct i915_power_well *power_well) |
| 6244 | { |
| 6245 | vlv_set_power_well(dev_priv, power_well, power_well->count > 0); |
| 6246 | } |
| 6247 | |
| 6248 | static void vlv_power_well_enable(struct drm_i915_private *dev_priv, |
| 6249 | struct i915_power_well *power_well) |
| 6250 | { |
| 6251 | vlv_set_power_well(dev_priv, power_well, true); |
| 6252 | } |
| 6253 | |
| 6254 | static void vlv_power_well_disable(struct drm_i915_private *dev_priv, |
| 6255 | struct i915_power_well *power_well) |
| 6256 | { |
| 6257 | vlv_set_power_well(dev_priv, power_well, false); |
| 6258 | } |
| 6259 | |
| 6260 | static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv, |
| 6261 | struct i915_power_well *power_well) |
| 6262 | { |
| 6263 | int power_well_id = power_well->data; |
| 6264 | bool enabled = false; |
| 6265 | u32 mask; |
| 6266 | u32 state; |
| 6267 | u32 ctrl; |
| 6268 | |
| 6269 | mask = PUNIT_PWRGT_MASK(power_well_id); |
| 6270 | ctrl = PUNIT_PWRGT_PWR_ON(power_well_id); |
| 6271 | |
| 6272 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6273 | |
| 6274 | state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; |
| 6275 | /* |
| 6276 | * We only ever set the power-on and power-gate states, anything |
| 6277 | * else is unexpected. |
| 6278 | */ |
| 6279 | WARN_ON(state != PUNIT_PWRGT_PWR_ON(power_well_id) && |
| 6280 | state != PUNIT_PWRGT_PWR_GATE(power_well_id)); |
| 6281 | if (state == ctrl) |
| 6282 | enabled = true; |
| 6283 | |
| 6284 | /* |
| 6285 | * A transient state at this point would mean some unexpected party |
| 6286 | * is poking at the power controls too. |
| 6287 | */ |
| 6288 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; |
| 6289 | WARN_ON(ctrl != state); |
| 6290 | |
| 6291 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 6292 | |
| 6293 | return enabled; |
| 6294 | } |
| 6295 | |
| 6296 | static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv, |
| 6297 | struct i915_power_well *power_well) |
| 6298 | { |
| 6299 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
| 6300 | |
| 6301 | vlv_set_power_well(dev_priv, power_well, true); |
| 6302 | |
| 6303 | spin_lock_irq(&dev_priv->irq_lock); |
| 6304 | valleyview_enable_display_irqs(dev_priv); |
| 6305 | spin_unlock_irq(&dev_priv->irq_lock); |
| 6306 | |
| 6307 | /* |
Imre Deak | 0d116a2 | 2014-04-25 13:19:05 +0300 | [diff] [blame] | 6308 | * During driver initialization/resume we can avoid restoring the |
| 6309 | * part of the HW/SW state that will be inited anyway explicitly. |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6310 | */ |
Imre Deak | 0d116a2 | 2014-04-25 13:19:05 +0300 | [diff] [blame] | 6311 | if (dev_priv->power_domains.initializing) |
| 6312 | return; |
| 6313 | |
| 6314 | intel_hpd_init(dev_priv->dev); |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6315 | |
| 6316 | i915_redisable_vga_power_on(dev_priv->dev); |
| 6317 | } |
| 6318 | |
| 6319 | static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv, |
| 6320 | struct i915_power_well *power_well) |
| 6321 | { |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6322 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DISP2D); |
| 6323 | |
| 6324 | spin_lock_irq(&dev_priv->irq_lock); |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6325 | valleyview_disable_display_irqs(dev_priv); |
| 6326 | spin_unlock_irq(&dev_priv->irq_lock); |
| 6327 | |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6328 | vlv_set_power_well(dev_priv, power_well, false); |
| 6329 | } |
| 6330 | |
Ville Syrjälä | aa519f2 | 2014-06-13 13:37:55 +0300 | [diff] [blame] | 6331 | static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
| 6332 | struct i915_power_well *power_well) |
| 6333 | { |
| 6334 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 6335 | |
| 6336 | /* |
| 6337 | * Enable the CRI clock source so we can get at the |
| 6338 | * display and the reference clock for VGA |
| 6339 | * hotplug / manual detection. |
| 6340 | */ |
| 6341 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
| 6342 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 6343 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
| 6344 | |
| 6345 | vlv_set_power_well(dev_priv, power_well, true); |
| 6346 | |
| 6347 | /* |
| 6348 | * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx - |
| 6349 | * 6. De-assert cmn_reset/side_reset. Same as VLV X0. |
| 6350 | * a. GUnit 0x2110 bit[0] set to 1 (def 0) |
| 6351 | * b. The other bits such as sfr settings / modesel may all |
| 6352 | * be set to 0. |
| 6353 | * |
| 6354 | * This should only be done on init and resume from S3 with |
| 6355 | * both PLLs disabled, or we risk losing DPIO and PLL |
| 6356 | * synchronization. |
| 6357 | */ |
| 6358 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) | DPIO_CMNRST); |
| 6359 | } |
| 6360 | |
| 6361 | static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, |
| 6362 | struct i915_power_well *power_well) |
| 6363 | { |
| 6364 | struct drm_device *dev = dev_priv->dev; |
| 6365 | enum pipe pipe; |
| 6366 | |
| 6367 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 6368 | |
| 6369 | for_each_pipe(pipe) |
| 6370 | assert_pll_disabled(dev_priv, pipe); |
| 6371 | |
| 6372 | /* Assert common reset */ |
| 6373 | I915_WRITE(DPIO_CTL, I915_READ(DPIO_CTL) & ~DPIO_CMNRST); |
| 6374 | |
| 6375 | vlv_set_power_well(dev_priv, power_well, false); |
| 6376 | } |
| 6377 | |
Ville Syrjälä | 5d6f7ea | 2014-06-28 02:04:08 +0300 | [diff] [blame] | 6378 | static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv, |
| 6379 | struct i915_power_well *power_well) |
| 6380 | { |
| 6381 | enum dpio_phy phy; |
| 6382 | |
| 6383 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && |
| 6384 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); |
| 6385 | |
| 6386 | /* |
| 6387 | * Enable the CRI clock source so we can get at the |
| 6388 | * display and the reference clock for VGA |
| 6389 | * hotplug / manual detection. |
| 6390 | */ |
| 6391 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
| 6392 | phy = DPIO_PHY0; |
| 6393 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
| 6394 | DPLL_REFA_CLK_ENABLE_VLV); |
| 6395 | I915_WRITE(DPLL(PIPE_B), I915_READ(DPLL(PIPE_B)) | |
| 6396 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 6397 | } else { |
| 6398 | phy = DPIO_PHY1; |
| 6399 | I915_WRITE(DPLL(PIPE_C), I915_READ(DPLL(PIPE_C)) | |
| 6400 | DPLL_REFA_CLK_ENABLE_VLV | DPLL_INTEGRATED_CRI_CLK_VLV); |
| 6401 | } |
| 6402 | udelay(1); /* >10ns for cmnreset, >0ns for sidereset */ |
| 6403 | vlv_set_power_well(dev_priv, power_well, true); |
| 6404 | |
| 6405 | /* Poll for phypwrgood signal */ |
| 6406 | if (wait_for(I915_READ(DISPLAY_PHY_STATUS) & PHY_POWERGOOD(phy), 1)) |
| 6407 | DRM_ERROR("Display PHY %d is not power up\n", phy); |
| 6408 | |
Ville Syrjälä | efd814b | 2014-06-27 19:52:13 +0300 | [diff] [blame] | 6409 | I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) | |
| 6410 | PHY_COM_LANE_RESET_DEASSERT(phy)); |
Ville Syrjälä | 5d6f7ea | 2014-06-28 02:04:08 +0300 | [diff] [blame] | 6411 | } |
| 6412 | |
| 6413 | static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv, |
| 6414 | struct i915_power_well *power_well) |
| 6415 | { |
| 6416 | enum dpio_phy phy; |
| 6417 | |
| 6418 | WARN_ON_ONCE(power_well->data != PUNIT_POWER_WELL_DPIO_CMN_BC && |
| 6419 | power_well->data != PUNIT_POWER_WELL_DPIO_CMN_D); |
| 6420 | |
| 6421 | if (power_well->data == PUNIT_POWER_WELL_DPIO_CMN_BC) { |
| 6422 | phy = DPIO_PHY0; |
| 6423 | assert_pll_disabled(dev_priv, PIPE_A); |
| 6424 | assert_pll_disabled(dev_priv, PIPE_B); |
| 6425 | } else { |
| 6426 | phy = DPIO_PHY1; |
| 6427 | assert_pll_disabled(dev_priv, PIPE_C); |
| 6428 | } |
| 6429 | |
Ville Syrjälä | efd814b | 2014-06-27 19:52:13 +0300 | [diff] [blame] | 6430 | I915_WRITE(DISPLAY_PHY_CONTROL, I915_READ(DISPLAY_PHY_CONTROL) & |
| 6431 | ~PHY_COM_LANE_RESET_DEASSERT(phy)); |
Ville Syrjälä | 5d6f7ea | 2014-06-28 02:04:08 +0300 | [diff] [blame] | 6432 | |
| 6433 | vlv_set_power_well(dev_priv, power_well, false); |
| 6434 | } |
| 6435 | |
Ville Syrjälä | 26972b0 | 2014-06-28 02:04:11 +0300 | [diff] [blame] | 6436 | static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv, |
| 6437 | struct i915_power_well *power_well) |
| 6438 | { |
| 6439 | enum pipe pipe = power_well->data; |
| 6440 | bool enabled; |
| 6441 | u32 state, ctrl; |
| 6442 | |
| 6443 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6444 | |
| 6445 | state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); |
| 6446 | /* |
| 6447 | * We only ever set the power-on and power-gate states, anything |
| 6448 | * else is unexpected. |
| 6449 | */ |
| 6450 | WARN_ON(state != DP_SSS_PWR_ON(pipe) && state != DP_SSS_PWR_GATE(pipe)); |
| 6451 | enabled = state == DP_SSS_PWR_ON(pipe); |
| 6452 | |
| 6453 | /* |
| 6454 | * A transient state at this point would mean some unexpected party |
| 6455 | * is poking at the power controls too. |
| 6456 | */ |
| 6457 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); |
| 6458 | WARN_ON(ctrl << 16 != state); |
| 6459 | |
| 6460 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 6461 | |
| 6462 | return enabled; |
| 6463 | } |
| 6464 | |
| 6465 | static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv, |
| 6466 | struct i915_power_well *power_well, |
| 6467 | bool enable) |
| 6468 | { |
| 6469 | enum pipe pipe = power_well->data; |
| 6470 | u32 state; |
| 6471 | u32 ctrl; |
| 6472 | |
| 6473 | state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe); |
| 6474 | |
| 6475 | mutex_lock(&dev_priv->rps.hw_lock); |
| 6476 | |
| 6477 | #define COND \ |
| 6478 | ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) |
| 6479 | |
| 6480 | if (COND) |
| 6481 | goto out; |
| 6482 | |
| 6483 | ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); |
| 6484 | ctrl &= ~DP_SSC_MASK(pipe); |
| 6485 | ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe); |
| 6486 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, ctrl); |
| 6487 | |
| 6488 | if (wait_for(COND, 100)) |
| 6489 | DRM_ERROR("timout setting power well state %08x (%08x)\n", |
| 6490 | state, |
| 6491 | vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); |
| 6492 | |
| 6493 | #undef COND |
| 6494 | |
| 6495 | out: |
| 6496 | mutex_unlock(&dev_priv->rps.hw_lock); |
| 6497 | } |
| 6498 | |
| 6499 | static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv, |
| 6500 | struct i915_power_well *power_well) |
| 6501 | { |
| 6502 | chv_set_pipe_power_well(dev_priv, power_well, power_well->count > 0); |
| 6503 | } |
| 6504 | |
| 6505 | static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, |
| 6506 | struct i915_power_well *power_well) |
| 6507 | { |
| 6508 | WARN_ON_ONCE(power_well->data != PIPE_A && |
| 6509 | power_well->data != PIPE_B && |
| 6510 | power_well->data != PIPE_C); |
| 6511 | |
| 6512 | chv_set_pipe_power_well(dev_priv, power_well, true); |
| 6513 | } |
| 6514 | |
| 6515 | static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, |
| 6516 | struct i915_power_well *power_well) |
| 6517 | { |
| 6518 | WARN_ON_ONCE(power_well->data != PIPE_A && |
| 6519 | power_well->data != PIPE_B && |
| 6520 | power_well->data != PIPE_C); |
| 6521 | |
| 6522 | chv_set_pipe_power_well(dev_priv, power_well, false); |
| 6523 | } |
| 6524 | |
Imre Deak | 25eaa00 | 2014-03-04 19:23:06 +0200 | [diff] [blame] | 6525 | static void check_power_well_state(struct drm_i915_private *dev_priv, |
| 6526 | struct i915_power_well *power_well) |
| 6527 | { |
| 6528 | bool enabled = power_well->ops->is_enabled(dev_priv, power_well); |
| 6529 | |
| 6530 | if (power_well->always_on || !i915.disable_power_well) { |
| 6531 | if (!enabled) |
| 6532 | goto mismatch; |
| 6533 | |
| 6534 | return; |
| 6535 | } |
| 6536 | |
| 6537 | if (enabled != (power_well->count > 0)) |
| 6538 | goto mismatch; |
| 6539 | |
| 6540 | return; |
| 6541 | |
| 6542 | mismatch: |
| 6543 | WARN(1, "state mismatch for '%s' (always_on %d hw state %d use-count %d disable_power_well %d\n", |
| 6544 | power_well->name, power_well->always_on, enabled, |
| 6545 | power_well->count, i915.disable_power_well); |
| 6546 | } |
| 6547 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6548 | void intel_display_power_get(struct drm_i915_private *dev_priv, |
Ville Syrjälä | 6765625 | 2013-09-16 17:38:28 +0300 | [diff] [blame] | 6549 | enum intel_display_power_domain domain) |
| 6550 | { |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 6551 | struct i915_power_domains *power_domains; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6552 | struct i915_power_well *power_well; |
| 6553 | int i; |
Ville Syrjälä | 6765625 | 2013-09-16 17:38:28 +0300 | [diff] [blame] | 6554 | |
Paulo Zanoni | 9e6ea71 | 2014-03-07 20:08:06 -0300 | [diff] [blame] | 6555 | intel_runtime_pm_get(dev_priv); |
| 6556 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 6557 | power_domains = &dev_priv->power_domains; |
| 6558 | |
| 6559 | mutex_lock(&power_domains->lock); |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 6560 | |
Imre Deak | 25eaa00 | 2014-03-04 19:23:06 +0200 | [diff] [blame] | 6561 | for_each_power_well(i, power_well, BIT(domain), power_domains) { |
| 6562 | if (!power_well->count++) { |
| 6563 | DRM_DEBUG_KMS("enabling %s\n", power_well->name); |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6564 | power_well->ops->enable(dev_priv, power_well); |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 6565 | power_well->hw_enabled = true; |
Imre Deak | 25eaa00 | 2014-03-04 19:23:06 +0200 | [diff] [blame] | 6566 | } |
| 6567 | |
| 6568 | check_power_well_state(dev_priv, power_well); |
| 6569 | } |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 6570 | |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 6571 | power_domains->domain_use_count[domain]++; |
| 6572 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 6573 | mutex_unlock(&power_domains->lock); |
Ville Syrjälä | 6765625 | 2013-09-16 17:38:28 +0300 | [diff] [blame] | 6574 | } |
| 6575 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6576 | void intel_display_power_put(struct drm_i915_private *dev_priv, |
Ville Syrjälä | 6765625 | 2013-09-16 17:38:28 +0300 | [diff] [blame] | 6577 | enum intel_display_power_domain domain) |
| 6578 | { |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 6579 | struct i915_power_domains *power_domains; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6580 | struct i915_power_well *power_well; |
| 6581 | int i; |
Ville Syrjälä | 6765625 | 2013-09-16 17:38:28 +0300 | [diff] [blame] | 6582 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 6583 | power_domains = &dev_priv->power_domains; |
| 6584 | |
| 6585 | mutex_lock(&power_domains->lock); |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 6586 | |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 6587 | WARN_ON(!power_domains->domain_use_count[domain]); |
| 6588 | power_domains->domain_use_count[domain]--; |
Imre Deak | ddf9c53 | 2013-11-27 22:02:02 +0200 | [diff] [blame] | 6589 | |
Imre Deak | 70bf407 | 2014-03-04 19:22:51 +0200 | [diff] [blame] | 6590 | for_each_power_well_rev(i, power_well, BIT(domain), power_domains) { |
| 6591 | WARN_ON(!power_well->count); |
| 6592 | |
Imre Deak | 25eaa00 | 2014-03-04 19:23:06 +0200 | [diff] [blame] | 6593 | if (!--power_well->count && i915.disable_power_well) { |
| 6594 | DRM_DEBUG_KMS("disabling %s\n", power_well->name); |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 6595 | power_well->hw_enabled = false; |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6596 | power_well->ops->disable(dev_priv, power_well); |
Imre Deak | 25eaa00 | 2014-03-04 19:23:06 +0200 | [diff] [blame] | 6597 | } |
| 6598 | |
| 6599 | check_power_well_state(dev_priv, power_well); |
Imre Deak | 70bf407 | 2014-03-04 19:22:51 +0200 | [diff] [blame] | 6600 | } |
Imre Deak | 1da5158 | 2013-11-25 17:15:35 +0200 | [diff] [blame] | 6601 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 6602 | mutex_unlock(&power_domains->lock); |
Paulo Zanoni | 9e6ea71 | 2014-03-07 20:08:06 -0300 | [diff] [blame] | 6603 | |
| 6604 | intel_runtime_pm_put(dev_priv); |
Ville Syrjälä | 6765625 | 2013-09-16 17:38:28 +0300 | [diff] [blame] | 6605 | } |
| 6606 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 6607 | static struct i915_power_domains *hsw_pwr; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 6608 | |
| 6609 | /* Display audio driver power well request */ |
Takashi Iwai | 74b0c2d | 2014-06-13 15:14:34 +0200 | [diff] [blame] | 6610 | int i915_request_power_well(void) |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 6611 | { |
Imre Deak | b4ed448 | 2013-10-25 17:36:49 +0300 | [diff] [blame] | 6612 | struct drm_i915_private *dev_priv; |
| 6613 | |
Takashi Iwai | 74b0c2d | 2014-06-13 15:14:34 +0200 | [diff] [blame] | 6614 | if (!hsw_pwr) |
| 6615 | return -ENODEV; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 6616 | |
Imre Deak | b4ed448 | 2013-10-25 17:36:49 +0300 | [diff] [blame] | 6617 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
| 6618 | power_domains); |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6619 | intel_display_power_get(dev_priv, POWER_DOMAIN_AUDIO); |
Takashi Iwai | 74b0c2d | 2014-06-13 15:14:34 +0200 | [diff] [blame] | 6620 | return 0; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 6621 | } |
| 6622 | EXPORT_SYMBOL_GPL(i915_request_power_well); |
| 6623 | |
| 6624 | /* Display audio driver power well release */ |
Takashi Iwai | 74b0c2d | 2014-06-13 15:14:34 +0200 | [diff] [blame] | 6625 | int i915_release_power_well(void) |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 6626 | { |
Imre Deak | b4ed448 | 2013-10-25 17:36:49 +0300 | [diff] [blame] | 6627 | struct drm_i915_private *dev_priv; |
| 6628 | |
Takashi Iwai | 74b0c2d | 2014-06-13 15:14:34 +0200 | [diff] [blame] | 6629 | if (!hsw_pwr) |
| 6630 | return -ENODEV; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 6631 | |
Imre Deak | b4ed448 | 2013-10-25 17:36:49 +0300 | [diff] [blame] | 6632 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
| 6633 | power_domains); |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 6634 | intel_display_power_put(dev_priv, POWER_DOMAIN_AUDIO); |
Takashi Iwai | 74b0c2d | 2014-06-13 15:14:34 +0200 | [diff] [blame] | 6635 | return 0; |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 6636 | } |
| 6637 | EXPORT_SYMBOL_GPL(i915_release_power_well); |
| 6638 | |
Jani Nikula | c149dcb | 2014-07-04 10:00:37 +0800 | [diff] [blame] | 6639 | /* |
| 6640 | * Private interface for the audio driver to get CDCLK in kHz. |
| 6641 | * |
| 6642 | * Caller must request power well using i915_request_power_well() prior to |
| 6643 | * making the call. |
| 6644 | */ |
| 6645 | int i915_get_cdclk_freq(void) |
| 6646 | { |
| 6647 | struct drm_i915_private *dev_priv; |
| 6648 | |
| 6649 | if (!hsw_pwr) |
| 6650 | return -ENODEV; |
| 6651 | |
| 6652 | dev_priv = container_of(hsw_pwr, struct drm_i915_private, |
| 6653 | power_domains); |
| 6654 | |
| 6655 | return intel_ddi_get_cdclk_freq(dev_priv); |
| 6656 | } |
| 6657 | EXPORT_SYMBOL_GPL(i915_get_cdclk_freq); |
| 6658 | |
| 6659 | |
Imre Deak | efcad91 | 2014-03-04 19:22:53 +0200 | [diff] [blame] | 6660 | #define POWER_DOMAIN_MASK (BIT(POWER_DOMAIN_NUM) - 1) |
| 6661 | |
| 6662 | #define HSW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 6663 | BIT(POWER_DOMAIN_PIPE_A) | \ |
Imre Deak | f5938f3 | 2014-03-04 19:22:54 +0200 | [diff] [blame] | 6664 | BIT(POWER_DOMAIN_TRANSCODER_EDP) | \ |
Imre Deak | 319be8a | 2014-03-04 19:22:57 +0200 | [diff] [blame] | 6665 | BIT(POWER_DOMAIN_PORT_DDI_A_2_LANES) | \ |
| 6666 | BIT(POWER_DOMAIN_PORT_DDI_A_4_LANES) | \ |
| 6667 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 6668 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 6669 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 6670 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 6671 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
| 6672 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
| 6673 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
Paulo Zanoni | bd2bb1b | 2014-07-04 11:27:38 -0300 | [diff] [blame] | 6674 | BIT(POWER_DOMAIN_PLLS) | \ |
Imre Deak | f5938f3 | 2014-03-04 19:22:54 +0200 | [diff] [blame] | 6675 | BIT(POWER_DOMAIN_INIT)) |
Imre Deak | efcad91 | 2014-03-04 19:22:53 +0200 | [diff] [blame] | 6676 | #define HSW_DISPLAY_POWER_DOMAINS ( \ |
| 6677 | (POWER_DOMAIN_MASK & ~HSW_ALWAYS_ON_POWER_DOMAINS) | \ |
| 6678 | BIT(POWER_DOMAIN_INIT)) |
| 6679 | |
| 6680 | #define BDW_ALWAYS_ON_POWER_DOMAINS ( \ |
| 6681 | HSW_ALWAYS_ON_POWER_DOMAINS | \ |
| 6682 | BIT(POWER_DOMAIN_PIPE_A_PANEL_FITTER)) |
| 6683 | #define BDW_DISPLAY_POWER_DOMAINS ( \ |
| 6684 | (POWER_DOMAIN_MASK & ~BDW_ALWAYS_ON_POWER_DOMAINS) | \ |
| 6685 | BIT(POWER_DOMAIN_INIT)) |
| 6686 | |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6687 | #define VLV_ALWAYS_ON_POWER_DOMAINS BIT(POWER_DOMAIN_INIT) |
| 6688 | #define VLV_DISPLAY_POWER_DOMAINS POWER_DOMAIN_MASK |
| 6689 | |
| 6690 | #define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
| 6691 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 6692 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 6693 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 6694 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 6695 | BIT(POWER_DOMAIN_PORT_CRT) | \ |
| 6696 | BIT(POWER_DOMAIN_INIT)) |
| 6697 | |
| 6698 | #define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \ |
| 6699 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 6700 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 6701 | BIT(POWER_DOMAIN_INIT)) |
| 6702 | |
| 6703 | #define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \ |
| 6704 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 6705 | BIT(POWER_DOMAIN_INIT)) |
| 6706 | |
| 6707 | #define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \ |
| 6708 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 6709 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 6710 | BIT(POWER_DOMAIN_INIT)) |
| 6711 | |
| 6712 | #define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \ |
| 6713 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 6714 | BIT(POWER_DOMAIN_INIT)) |
| 6715 | |
Ville Syrjälä | 26972b0 | 2014-06-28 02:04:11 +0300 | [diff] [blame] | 6716 | #define CHV_PIPE_A_POWER_DOMAINS ( \ |
| 6717 | BIT(POWER_DOMAIN_PIPE_A) | \ |
| 6718 | BIT(POWER_DOMAIN_INIT)) |
| 6719 | |
| 6720 | #define CHV_PIPE_B_POWER_DOMAINS ( \ |
| 6721 | BIT(POWER_DOMAIN_PIPE_B) | \ |
| 6722 | BIT(POWER_DOMAIN_INIT)) |
| 6723 | |
| 6724 | #define CHV_PIPE_C_POWER_DOMAINS ( \ |
| 6725 | BIT(POWER_DOMAIN_PIPE_C) | \ |
| 6726 | BIT(POWER_DOMAIN_INIT)) |
| 6727 | |
Ville Syrjälä | 5d6f7ea | 2014-06-28 02:04:08 +0300 | [diff] [blame] | 6728 | #define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \ |
| 6729 | BIT(POWER_DOMAIN_PORT_DDI_B_2_LANES) | \ |
| 6730 | BIT(POWER_DOMAIN_PORT_DDI_B_4_LANES) | \ |
| 6731 | BIT(POWER_DOMAIN_PORT_DDI_C_2_LANES) | \ |
| 6732 | BIT(POWER_DOMAIN_PORT_DDI_C_4_LANES) | \ |
| 6733 | BIT(POWER_DOMAIN_INIT)) |
| 6734 | |
| 6735 | #define CHV_DPIO_CMN_D_POWER_DOMAINS ( \ |
| 6736 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
| 6737 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
| 6738 | BIT(POWER_DOMAIN_INIT)) |
| 6739 | |
Ville Syrjälä | 2ce147f | 2014-06-28 02:04:13 +0300 | [diff] [blame] | 6740 | #define CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS ( \ |
| 6741 | BIT(POWER_DOMAIN_PORT_DDI_D_2_LANES) | \ |
| 6742 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
| 6743 | BIT(POWER_DOMAIN_INIT)) |
| 6744 | |
| 6745 | #define CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS ( \ |
| 6746 | BIT(POWER_DOMAIN_PORT_DDI_D_4_LANES) | \ |
| 6747 | BIT(POWER_DOMAIN_INIT)) |
| 6748 | |
Imre Deak | a45f4466 | 2014-03-04 19:22:56 +0200 | [diff] [blame] | 6749 | static const struct i915_power_well_ops i9xx_always_on_power_well_ops = { |
| 6750 | .sync_hw = i9xx_always_on_power_well_noop, |
| 6751 | .enable = i9xx_always_on_power_well_noop, |
| 6752 | .disable = i9xx_always_on_power_well_noop, |
| 6753 | .is_enabled = i9xx_always_on_power_well_enabled, |
| 6754 | }; |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6755 | |
Ville Syrjälä | 26972b0 | 2014-06-28 02:04:11 +0300 | [diff] [blame] | 6756 | static const struct i915_power_well_ops chv_pipe_power_well_ops = { |
| 6757 | .sync_hw = chv_pipe_power_well_sync_hw, |
| 6758 | .enable = chv_pipe_power_well_enable, |
| 6759 | .disable = chv_pipe_power_well_disable, |
| 6760 | .is_enabled = chv_pipe_power_well_enabled, |
| 6761 | }; |
| 6762 | |
Ville Syrjälä | 5d6f7ea | 2014-06-28 02:04:08 +0300 | [diff] [blame] | 6763 | static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = { |
| 6764 | .sync_hw = vlv_power_well_sync_hw, |
| 6765 | .enable = chv_dpio_cmn_power_well_enable, |
| 6766 | .disable = chv_dpio_cmn_power_well_disable, |
| 6767 | .is_enabled = vlv_power_well_enabled, |
| 6768 | }; |
| 6769 | |
Imre Deak | 1c2256d | 2013-11-25 17:15:34 +0200 | [diff] [blame] | 6770 | static struct i915_power_well i9xx_always_on_power_well[] = { |
| 6771 | { |
| 6772 | .name = "always-on", |
| 6773 | .always_on = 1, |
| 6774 | .domains = POWER_DOMAIN_MASK, |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6775 | .ops = &i9xx_always_on_power_well_ops, |
Imre Deak | 1c2256d | 2013-11-25 17:15:34 +0200 | [diff] [blame] | 6776 | }, |
| 6777 | }; |
| 6778 | |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6779 | static const struct i915_power_well_ops hsw_power_well_ops = { |
| 6780 | .sync_hw = hsw_power_well_sync_hw, |
| 6781 | .enable = hsw_power_well_enable, |
| 6782 | .disable = hsw_power_well_disable, |
| 6783 | .is_enabled = hsw_power_well_enabled, |
| 6784 | }; |
| 6785 | |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6786 | static struct i915_power_well hsw_power_wells[] = { |
| 6787 | { |
Imre Deak | 6f3ef5d | 2013-11-25 17:15:30 +0200 | [diff] [blame] | 6788 | .name = "always-on", |
| 6789 | .always_on = 1, |
| 6790 | .domains = HSW_ALWAYS_ON_POWER_DOMAINS, |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6791 | .ops = &i9xx_always_on_power_well_ops, |
Imre Deak | 6f3ef5d | 2013-11-25 17:15:30 +0200 | [diff] [blame] | 6792 | }, |
| 6793 | { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6794 | .name = "display", |
Imre Deak | efcad91 | 2014-03-04 19:22:53 +0200 | [diff] [blame] | 6795 | .domains = HSW_DISPLAY_POWER_DOMAINS, |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6796 | .ops = &hsw_power_well_ops, |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6797 | }, |
| 6798 | }; |
| 6799 | |
| 6800 | static struct i915_power_well bdw_power_wells[] = { |
| 6801 | { |
Imre Deak | 6f3ef5d | 2013-11-25 17:15:30 +0200 | [diff] [blame] | 6802 | .name = "always-on", |
| 6803 | .always_on = 1, |
| 6804 | .domains = BDW_ALWAYS_ON_POWER_DOMAINS, |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6805 | .ops = &i9xx_always_on_power_well_ops, |
Imre Deak | 6f3ef5d | 2013-11-25 17:15:30 +0200 | [diff] [blame] | 6806 | }, |
| 6807 | { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6808 | .name = "display", |
Imre Deak | efcad91 | 2014-03-04 19:22:53 +0200 | [diff] [blame] | 6809 | .domains = BDW_DISPLAY_POWER_DOMAINS, |
Imre Deak | c6cb582 | 2014-03-04 19:22:55 +0200 | [diff] [blame] | 6810 | .ops = &hsw_power_well_ops, |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 6811 | }, |
| 6812 | }; |
| 6813 | |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6814 | static const struct i915_power_well_ops vlv_display_power_well_ops = { |
| 6815 | .sync_hw = vlv_power_well_sync_hw, |
| 6816 | .enable = vlv_display_power_well_enable, |
| 6817 | .disable = vlv_display_power_well_disable, |
| 6818 | .is_enabled = vlv_power_well_enabled, |
| 6819 | }; |
| 6820 | |
Ville Syrjälä | aa519f2 | 2014-06-13 13:37:55 +0300 | [diff] [blame] | 6821 | static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = { |
| 6822 | .sync_hw = vlv_power_well_sync_hw, |
| 6823 | .enable = vlv_dpio_cmn_power_well_enable, |
| 6824 | .disable = vlv_dpio_cmn_power_well_disable, |
| 6825 | .is_enabled = vlv_power_well_enabled, |
| 6826 | }; |
| 6827 | |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6828 | static const struct i915_power_well_ops vlv_dpio_power_well_ops = { |
| 6829 | .sync_hw = vlv_power_well_sync_hw, |
| 6830 | .enable = vlv_power_well_enable, |
| 6831 | .disable = vlv_power_well_disable, |
| 6832 | .is_enabled = vlv_power_well_enabled, |
| 6833 | }; |
| 6834 | |
| 6835 | static struct i915_power_well vlv_power_wells[] = { |
| 6836 | { |
| 6837 | .name = "always-on", |
| 6838 | .always_on = 1, |
| 6839 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, |
| 6840 | .ops = &i9xx_always_on_power_well_ops, |
| 6841 | }, |
| 6842 | { |
| 6843 | .name = "display", |
| 6844 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
| 6845 | .data = PUNIT_POWER_WELL_DISP2D, |
| 6846 | .ops = &vlv_display_power_well_ops, |
| 6847 | }, |
| 6848 | { |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6849 | .name = "dpio-tx-b-01", |
| 6850 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 6851 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 6852 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 6853 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 6854 | .ops = &vlv_dpio_power_well_ops, |
| 6855 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, |
| 6856 | }, |
| 6857 | { |
| 6858 | .name = "dpio-tx-b-23", |
| 6859 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 6860 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 6861 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 6862 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 6863 | .ops = &vlv_dpio_power_well_ops, |
| 6864 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, |
| 6865 | }, |
| 6866 | { |
| 6867 | .name = "dpio-tx-c-01", |
| 6868 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 6869 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 6870 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 6871 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 6872 | .ops = &vlv_dpio_power_well_ops, |
| 6873 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, |
| 6874 | }, |
| 6875 | { |
| 6876 | .name = "dpio-tx-c-23", |
| 6877 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 6878 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS | |
| 6879 | VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 6880 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 6881 | .ops = &vlv_dpio_power_well_ops, |
| 6882 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, |
| 6883 | }, |
Jesse Barnes | f099a3c | 2014-05-23 13:16:43 -0700 | [diff] [blame] | 6884 | { |
| 6885 | .name = "dpio-common", |
| 6886 | .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS, |
| 6887 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
Ville Syrjälä | aa519f2 | 2014-06-13 13:37:55 +0300 | [diff] [blame] | 6888 | .ops = &vlv_dpio_cmn_power_well_ops, |
Jesse Barnes | f099a3c | 2014-05-23 13:16:43 -0700 | [diff] [blame] | 6889 | }, |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 6890 | }; |
| 6891 | |
Ville Syrjälä | 4811ff4 | 2014-06-28 02:04:07 +0300 | [diff] [blame] | 6892 | static struct i915_power_well chv_power_wells[] = { |
| 6893 | { |
| 6894 | .name = "always-on", |
| 6895 | .always_on = 1, |
| 6896 | .domains = VLV_ALWAYS_ON_POWER_DOMAINS, |
| 6897 | .ops = &i9xx_always_on_power_well_ops, |
| 6898 | }, |
Ville Syrjälä | f07057d | 2014-06-28 02:04:10 +0300 | [diff] [blame] | 6899 | #if 0 |
| 6900 | { |
| 6901 | .name = "display", |
| 6902 | .domains = VLV_DISPLAY_POWER_DOMAINS, |
| 6903 | .data = PUNIT_POWER_WELL_DISP2D, |
| 6904 | .ops = &vlv_display_power_well_ops, |
| 6905 | }, |
Ville Syrjälä | 26972b0 | 2014-06-28 02:04:11 +0300 | [diff] [blame] | 6906 | { |
| 6907 | .name = "pipe-a", |
| 6908 | .domains = CHV_PIPE_A_POWER_DOMAINS, |
| 6909 | .data = PIPE_A, |
| 6910 | .ops = &chv_pipe_power_well_ops, |
| 6911 | }, |
| 6912 | { |
| 6913 | .name = "pipe-b", |
| 6914 | .domains = CHV_PIPE_B_POWER_DOMAINS, |
| 6915 | .data = PIPE_B, |
| 6916 | .ops = &chv_pipe_power_well_ops, |
| 6917 | }, |
| 6918 | { |
| 6919 | .name = "pipe-c", |
| 6920 | .domains = CHV_PIPE_C_POWER_DOMAINS, |
| 6921 | .data = PIPE_C, |
| 6922 | .ops = &chv_pipe_power_well_ops, |
| 6923 | }, |
Ville Syrjälä | f07057d | 2014-06-28 02:04:10 +0300 | [diff] [blame] | 6924 | #endif |
Ville Syrjälä | 5d6f7ea | 2014-06-28 02:04:08 +0300 | [diff] [blame] | 6925 | { |
| 6926 | .name = "dpio-common-bc", |
Ville Syrjälä | 3dd7b974 | 2014-06-27 19:49:57 +0300 | [diff] [blame] | 6927 | /* |
| 6928 | * XXX: cmnreset for one PHY seems to disturb the other. |
| 6929 | * As a workaround keep both powered on at the same |
| 6930 | * time for now. |
| 6931 | */ |
| 6932 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, |
Ville Syrjälä | 5d6f7ea | 2014-06-28 02:04:08 +0300 | [diff] [blame] | 6933 | .data = PUNIT_POWER_WELL_DPIO_CMN_BC, |
| 6934 | .ops = &chv_dpio_cmn_power_well_ops, |
| 6935 | }, |
| 6936 | { |
| 6937 | .name = "dpio-common-d", |
Ville Syrjälä | 3dd7b974 | 2014-06-27 19:49:57 +0300 | [diff] [blame] | 6938 | /* |
| 6939 | * XXX: cmnreset for one PHY seems to disturb the other. |
| 6940 | * As a workaround keep both powered on at the same |
| 6941 | * time for now. |
| 6942 | */ |
| 6943 | .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS | CHV_DPIO_CMN_D_POWER_DOMAINS, |
Ville Syrjälä | 5d6f7ea | 2014-06-28 02:04:08 +0300 | [diff] [blame] | 6944 | .data = PUNIT_POWER_WELL_DPIO_CMN_D, |
| 6945 | .ops = &chv_dpio_cmn_power_well_ops, |
| 6946 | }, |
Ville Syrjälä | 8258356 | 2014-06-28 02:04:12 +0300 | [diff] [blame] | 6947 | #if 0 |
| 6948 | { |
| 6949 | .name = "dpio-tx-b-01", |
| 6950 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 6951 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, |
| 6952 | .ops = &vlv_dpio_power_well_ops, |
| 6953 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_01, |
| 6954 | }, |
| 6955 | { |
| 6956 | .name = "dpio-tx-b-23", |
| 6957 | .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS | |
| 6958 | VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS, |
| 6959 | .ops = &vlv_dpio_power_well_ops, |
| 6960 | .data = PUNIT_POWER_WELL_DPIO_TX_B_LANES_23, |
| 6961 | }, |
| 6962 | { |
| 6963 | .name = "dpio-tx-c-01", |
| 6964 | .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 6965 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 6966 | .ops = &vlv_dpio_power_well_ops, |
| 6967 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_01, |
| 6968 | }, |
| 6969 | { |
| 6970 | .name = "dpio-tx-c-23", |
| 6971 | .domains = VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS | |
| 6972 | VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS, |
| 6973 | .ops = &vlv_dpio_power_well_ops, |
| 6974 | .data = PUNIT_POWER_WELL_DPIO_TX_C_LANES_23, |
| 6975 | }, |
Ville Syrjälä | 2ce147f | 2014-06-28 02:04:13 +0300 | [diff] [blame] | 6976 | { |
| 6977 | .name = "dpio-tx-d-01", |
| 6978 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | |
| 6979 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, |
| 6980 | .ops = &vlv_dpio_power_well_ops, |
| 6981 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_01, |
| 6982 | }, |
| 6983 | { |
| 6984 | .name = "dpio-tx-d-23", |
| 6985 | .domains = CHV_DPIO_TX_D_LANES_01_POWER_DOMAINS | |
| 6986 | CHV_DPIO_TX_D_LANES_23_POWER_DOMAINS, |
| 6987 | .ops = &vlv_dpio_power_well_ops, |
| 6988 | .data = PUNIT_POWER_WELL_DPIO_TX_D_LANES_23, |
| 6989 | }, |
Ville Syrjälä | 8258356 | 2014-06-28 02:04:12 +0300 | [diff] [blame] | 6990 | #endif |
Ville Syrjälä | 4811ff4 | 2014-06-28 02:04:07 +0300 | [diff] [blame] | 6991 | }; |
| 6992 | |
Ville Syrjälä | d2011dc | 2014-06-13 13:37:56 +0300 | [diff] [blame] | 6993 | static struct i915_power_well *lookup_power_well(struct drm_i915_private *dev_priv, |
| 6994 | enum punit_power_well power_well_id) |
| 6995 | { |
| 6996 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 6997 | struct i915_power_well *power_well; |
| 6998 | int i; |
| 6999 | |
| 7000 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { |
| 7001 | if (power_well->data == power_well_id) |
| 7002 | return power_well; |
| 7003 | } |
| 7004 | |
| 7005 | return NULL; |
| 7006 | } |
| 7007 | |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 7008 | #define set_power_wells(power_domains, __power_wells) ({ \ |
| 7009 | (power_domains)->power_wells = (__power_wells); \ |
| 7010 | (power_domains)->power_well_count = ARRAY_SIZE(__power_wells); \ |
| 7011 | }) |
| 7012 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 7013 | int intel_power_domains_init(struct drm_i915_private *dev_priv) |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 7014 | { |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 7015 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 7016 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 7017 | mutex_init(&power_domains->lock); |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 7018 | |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 7019 | /* |
| 7020 | * The enabling order will be from lower to higher indexed wells, |
| 7021 | * the disabling order is reversed. |
| 7022 | */ |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 7023 | if (IS_HASWELL(dev_priv->dev)) { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 7024 | set_power_wells(power_domains, hsw_power_wells); |
| 7025 | hsw_pwr = power_domains; |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 7026 | } else if (IS_BROADWELL(dev_priv->dev)) { |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 7027 | set_power_wells(power_domains, bdw_power_wells); |
| 7028 | hsw_pwr = power_domains; |
Ville Syrjälä | 4811ff4 | 2014-06-28 02:04:07 +0300 | [diff] [blame] | 7029 | } else if (IS_CHERRYVIEW(dev_priv->dev)) { |
| 7030 | set_power_wells(power_domains, chv_power_wells); |
Imre Deak | 77961eb | 2014-03-05 16:20:56 +0200 | [diff] [blame] | 7031 | } else if (IS_VALLEYVIEW(dev_priv->dev)) { |
| 7032 | set_power_wells(power_domains, vlv_power_wells); |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 7033 | } else { |
Imre Deak | 1c2256d | 2013-11-25 17:15:34 +0200 | [diff] [blame] | 7034 | set_power_wells(power_domains, i9xx_always_on_power_well); |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 7035 | } |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 7036 | |
| 7037 | return 0; |
| 7038 | } |
| 7039 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 7040 | void intel_power_domains_remove(struct drm_i915_private *dev_priv) |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 7041 | { |
| 7042 | hsw_pwr = NULL; |
| 7043 | } |
| 7044 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 7045 | static void intel_power_domains_resume(struct drm_i915_private *dev_priv) |
Ville Syrjälä | 9cdb826 | 2013-09-16 17:38:27 +0300 | [diff] [blame] | 7046 | { |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 7047 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 7048 | struct i915_power_well *power_well; |
Imre Deak | c1ca727 | 2013-11-25 17:15:29 +0200 | [diff] [blame] | 7049 | int i; |
Ville Syrjälä | 9cdb826 | 2013-09-16 17:38:27 +0300 | [diff] [blame] | 7050 | |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 7051 | mutex_lock(&power_domains->lock); |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 7052 | for_each_power_well(i, power_well, POWER_DOMAIN_MASK, power_domains) { |
Imre Deak | a45f4466 | 2014-03-04 19:22:56 +0200 | [diff] [blame] | 7053 | power_well->ops->sync_hw(dev_priv, power_well); |
Imre Deak | bfafe93 | 2014-06-05 20:31:47 +0300 | [diff] [blame] | 7054 | power_well->hw_enabled = power_well->ops->is_enabled(dev_priv, |
| 7055 | power_well); |
| 7056 | } |
Imre Deak | 83c00f55 | 2013-10-25 17:36:47 +0300 | [diff] [blame] | 7057 | mutex_unlock(&power_domains->lock); |
Wang Xingchao | a38911a | 2013-05-30 22:07:11 +0800 | [diff] [blame] | 7058 | } |
| 7059 | |
Ville Syrjälä | d2011dc | 2014-06-13 13:37:56 +0300 | [diff] [blame] | 7060 | static void vlv_cmnlane_wa(struct drm_i915_private *dev_priv) |
| 7061 | { |
| 7062 | struct i915_power_well *cmn = |
| 7063 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DPIO_CMN_BC); |
| 7064 | struct i915_power_well *disp2d = |
| 7065 | lookup_power_well(dev_priv, PUNIT_POWER_WELL_DISP2D); |
| 7066 | |
| 7067 | /* nothing to do if common lane is already off */ |
| 7068 | if (!cmn->ops->is_enabled(dev_priv, cmn)) |
| 7069 | return; |
| 7070 | |
| 7071 | /* If the display might be already active skip this */ |
| 7072 | if (disp2d->ops->is_enabled(dev_priv, disp2d) && |
| 7073 | I915_READ(DPIO_CTL) & DPIO_CMNRST) |
| 7074 | return; |
| 7075 | |
| 7076 | DRM_DEBUG_KMS("toggling display PHY side reset\n"); |
| 7077 | |
| 7078 | /* cmnlane needs DPLL registers */ |
| 7079 | disp2d->ops->enable(dev_priv, disp2d); |
| 7080 | |
| 7081 | /* |
| 7082 | * From VLV2A0_DP_eDP_HDMI_DPIO_driver_vbios_notes_11.docx: |
| 7083 | * Need to assert and de-assert PHY SB reset by gating the |
| 7084 | * common lane power, then un-gating it. |
| 7085 | * Simply ungating isn't enough to reset the PHY enough to get |
| 7086 | * ports and lanes running. |
| 7087 | */ |
| 7088 | cmn->ops->disable(dev_priv, cmn); |
| 7089 | } |
| 7090 | |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 7091 | void intel_power_domains_init_hw(struct drm_i915_private *dev_priv) |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 7092 | { |
Ville Syrjälä | d2011dc | 2014-06-13 13:37:56 +0300 | [diff] [blame] | 7093 | struct drm_device *dev = dev_priv->dev; |
Imre Deak | 0d116a2 | 2014-04-25 13:19:05 +0300 | [diff] [blame] | 7094 | struct i915_power_domains *power_domains = &dev_priv->power_domains; |
| 7095 | |
| 7096 | power_domains->initializing = true; |
Ville Syrjälä | d2011dc | 2014-06-13 13:37:56 +0300 | [diff] [blame] | 7097 | |
| 7098 | if (IS_VALLEYVIEW(dev) && !IS_CHERRYVIEW(dev)) { |
| 7099 | mutex_lock(&power_domains->lock); |
| 7100 | vlv_cmnlane_wa(dev_priv); |
| 7101 | mutex_unlock(&power_domains->lock); |
| 7102 | } |
| 7103 | |
Paulo Zanoni | fa42e23 | 2013-01-25 16:59:11 -0200 | [diff] [blame] | 7104 | /* For now, we need the power well to be always enabled. */ |
Imre Deak | da7e29b | 2014-02-18 00:02:02 +0200 | [diff] [blame] | 7105 | intel_display_set_init_power(dev_priv, true); |
| 7106 | intel_power_domains_resume(dev_priv); |
Imre Deak | 0d116a2 | 2014-04-25 13:19:05 +0300 | [diff] [blame] | 7107 | power_domains->initializing = false; |
Eugeni Dodonov | d0d3e51 | 2012-05-09 15:37:16 -0300 | [diff] [blame] | 7108 | } |
| 7109 | |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7110 | void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv) |
| 7111 | { |
Paulo Zanoni | d361ae2 | 2014-03-07 20:08:12 -0300 | [diff] [blame] | 7112 | intel_runtime_pm_get(dev_priv); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7113 | } |
| 7114 | |
| 7115 | void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv) |
| 7116 | { |
Paulo Zanoni | d361ae2 | 2014-03-07 20:08:12 -0300 | [diff] [blame] | 7117 | intel_runtime_pm_put(dev_priv); |
Paulo Zanoni | c67a470 | 2013-08-19 13:18:09 -0300 | [diff] [blame] | 7118 | } |
| 7119 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 7120 | void intel_runtime_pm_get(struct drm_i915_private *dev_priv) |
| 7121 | { |
| 7122 | struct drm_device *dev = dev_priv->dev; |
| 7123 | struct device *device = &dev->pdev->dev; |
| 7124 | |
| 7125 | if (!HAS_RUNTIME_PM(dev)) |
| 7126 | return; |
| 7127 | |
| 7128 | pm_runtime_get_sync(device); |
| 7129 | WARN(dev_priv->pm.suspended, "Device still suspended.\n"); |
| 7130 | } |
| 7131 | |
Imre Deak | c6df39b | 2014-04-14 20:24:29 +0300 | [diff] [blame] | 7132 | void intel_runtime_pm_get_noresume(struct drm_i915_private *dev_priv) |
| 7133 | { |
| 7134 | struct drm_device *dev = dev_priv->dev; |
| 7135 | struct device *device = &dev->pdev->dev; |
| 7136 | |
| 7137 | if (!HAS_RUNTIME_PM(dev)) |
| 7138 | return; |
| 7139 | |
| 7140 | WARN(dev_priv->pm.suspended, "Getting nosync-ref while suspended.\n"); |
| 7141 | pm_runtime_get_noresume(device); |
| 7142 | } |
| 7143 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 7144 | void intel_runtime_pm_put(struct drm_i915_private *dev_priv) |
| 7145 | { |
| 7146 | struct drm_device *dev = dev_priv->dev; |
| 7147 | struct device *device = &dev->pdev->dev; |
| 7148 | |
| 7149 | if (!HAS_RUNTIME_PM(dev)) |
| 7150 | return; |
| 7151 | |
| 7152 | pm_runtime_mark_last_busy(device); |
| 7153 | pm_runtime_put_autosuspend(device); |
| 7154 | } |
| 7155 | |
| 7156 | void intel_init_runtime_pm(struct drm_i915_private *dev_priv) |
| 7157 | { |
| 7158 | struct drm_device *dev = dev_priv->dev; |
| 7159 | struct device *device = &dev->pdev->dev; |
| 7160 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 7161 | if (!HAS_RUNTIME_PM(dev)) |
| 7162 | return; |
| 7163 | |
| 7164 | pm_runtime_set_active(device); |
| 7165 | |
Imre Deak | aeab0b5 | 2014-04-14 20:24:36 +0300 | [diff] [blame] | 7166 | /* |
| 7167 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a |
| 7168 | * requirement. |
| 7169 | */ |
| 7170 | if (!intel_enable_rc6(dev)) { |
| 7171 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); |
| 7172 | return; |
| 7173 | } |
| 7174 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 7175 | pm_runtime_set_autosuspend_delay(device, 10000); /* 10s */ |
| 7176 | pm_runtime_mark_last_busy(device); |
| 7177 | pm_runtime_use_autosuspend(device); |
Paulo Zanoni | ba0239e | 2014-03-07 20:08:07 -0300 | [diff] [blame] | 7178 | |
| 7179 | pm_runtime_put_autosuspend(device); |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 7180 | } |
| 7181 | |
| 7182 | void intel_fini_runtime_pm(struct drm_i915_private *dev_priv) |
| 7183 | { |
| 7184 | struct drm_device *dev = dev_priv->dev; |
| 7185 | struct device *device = &dev->pdev->dev; |
| 7186 | |
| 7187 | if (!HAS_RUNTIME_PM(dev)) |
| 7188 | return; |
| 7189 | |
Imre Deak | aeab0b5 | 2014-04-14 20:24:36 +0300 | [diff] [blame] | 7190 | if (!intel_enable_rc6(dev)) |
| 7191 | return; |
| 7192 | |
Paulo Zanoni | 8a18745 | 2013-12-06 20:32:13 -0200 | [diff] [blame] | 7193 | /* Make sure we're not suspended first. */ |
| 7194 | pm_runtime_get_sync(device); |
| 7195 | pm_runtime_disable(device); |
| 7196 | } |
| 7197 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7198 | /* Set up chip specific power management-related functions */ |
| 7199 | void intel_init_pm(struct drm_device *dev) |
| 7200 | { |
| 7201 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7202 | |
Daniel Vetter | 3a77c4c | 2014-01-10 08:50:12 +0100 | [diff] [blame] | 7203 | if (HAS_FBC(dev)) { |
Ville Syrjälä | 4004546 | 2013-11-28 17:29:59 +0200 | [diff] [blame] | 7204 | if (INTEL_INFO(dev)->gen >= 7) { |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7205 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
Ville Syrjälä | 4004546 | 2013-11-28 17:29:59 +0200 | [diff] [blame] | 7206 | dev_priv->display.enable_fbc = gen7_enable_fbc; |
| 7207 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
| 7208 | } else if (INTEL_INFO(dev)->gen >= 5) { |
| 7209 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; |
| 7210 | dev_priv->display.enable_fbc = ironlake_enable_fbc; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7211 | dev_priv->display.disable_fbc = ironlake_disable_fbc; |
| 7212 | } else if (IS_GM45(dev)) { |
| 7213 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; |
| 7214 | dev_priv->display.enable_fbc = g4x_enable_fbc; |
| 7215 | dev_priv->display.disable_fbc = g4x_disable_fbc; |
Ville Syrjälä | 4004546 | 2013-11-28 17:29:59 +0200 | [diff] [blame] | 7216 | } else { |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7217 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; |
| 7218 | dev_priv->display.enable_fbc = i8xx_enable_fbc; |
| 7219 | dev_priv->display.disable_fbc = i8xx_disable_fbc; |
Ville Syrjälä | 993495a | 2013-12-12 17:27:40 +0200 | [diff] [blame] | 7220 | |
| 7221 | /* This value was pulled out of someone's hat */ |
| 7222 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7223 | } |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7224 | } |
| 7225 | |
Daniel Vetter | c921aba | 2012-04-26 23:28:17 +0200 | [diff] [blame] | 7226 | /* For cxsr */ |
| 7227 | if (IS_PINEVIEW(dev)) |
| 7228 | i915_pineview_get_mem_freq(dev); |
| 7229 | else if (IS_GEN5(dev)) |
| 7230 | i915_ironlake_get_mem_freq(dev); |
| 7231 | |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7232 | /* For FIFO watermark updates */ |
| 7233 | if (HAS_PCH_SPLIT(dev)) { |
Damien Lespiau | fa50ad6 | 2014-03-17 18:01:16 +0000 | [diff] [blame] | 7234 | ilk_setup_wm_latency(dev); |
Ville Syrjälä | 53615a5 | 2013-08-01 16:18:50 +0300 | [diff] [blame] | 7235 | |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 7236 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
| 7237 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || |
| 7238 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && |
| 7239 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { |
| 7240 | dev_priv->display.update_wm = ilk_update_wm; |
| 7241 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; |
| 7242 | } else { |
| 7243 | DRM_DEBUG_KMS("Failed to read display plane latency. " |
| 7244 | "Disable CxSR\n"); |
| 7245 | } |
| 7246 | |
| 7247 | if (IS_GEN5(dev)) |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7248 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 7249 | else if (IS_GEN6(dev)) |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7250 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 7251 | else if (IS_IVYBRIDGE(dev)) |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7252 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 7253 | else if (IS_HASWELL(dev)) |
Eugeni Dodonov | cad2a2d | 2012-07-02 11:51:09 -0300 | [diff] [blame] | 7254 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
Ville Syrjälä | bd60254 | 2014-01-07 16:14:10 +0200 | [diff] [blame] | 7255 | else if (INTEL_INFO(dev)->gen == 8) |
Ben Widawsky | 1020a5c | 2013-11-02 21:07:06 -0700 | [diff] [blame] | 7256 | dev_priv->display.init_clock_gating = gen8_init_clock_gating; |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 7257 | } else if (IS_CHERRYVIEW(dev)) { |
Ville Syrjälä | 3c2777f | 2014-06-26 17:03:06 +0300 | [diff] [blame] | 7258 | dev_priv->display.update_wm = cherryview_update_wm; |
Gajanan Bhat | 01e184c | 2014-08-07 17:03:30 +0530 | [diff] [blame^] | 7259 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
Ville Syrjälä | a4565da | 2014-04-09 13:28:10 +0300 | [diff] [blame] | 7260 | dev_priv->display.init_clock_gating = |
| 7261 | cherryview_init_clock_gating; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7262 | } else if (IS_VALLEYVIEW(dev)) { |
| 7263 | dev_priv->display.update_wm = valleyview_update_wm; |
Gajanan Bhat | 01e184c | 2014-08-07 17:03:30 +0530 | [diff] [blame^] | 7264 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7265 | dev_priv->display.init_clock_gating = |
| 7266 | valleyview_init_clock_gating; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7267 | } else if (IS_PINEVIEW(dev)) { |
| 7268 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), |
| 7269 | dev_priv->is_ddr3, |
| 7270 | dev_priv->fsb_freq, |
| 7271 | dev_priv->mem_freq)) { |
| 7272 | DRM_INFO("failed to find known CxSR latency " |
| 7273 | "(found ddr%s fsb freq %d, mem freq %d), " |
| 7274 | "disabling CxSR\n", |
| 7275 | (dev_priv->is_ddr3 == 1) ? "3" : "2", |
| 7276 | dev_priv->fsb_freq, dev_priv->mem_freq); |
| 7277 | /* Disable CxSR and never update its watermark again */ |
Imre Deak | 5209b1f | 2014-07-01 12:36:17 +0300 | [diff] [blame] | 7278 | intel_set_memory_cxsr(dev_priv, false); |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7279 | dev_priv->display.update_wm = NULL; |
| 7280 | } else |
| 7281 | dev_priv->display.update_wm = pineview_update_wm; |
| 7282 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
| 7283 | } else if (IS_G4X(dev)) { |
| 7284 | dev_priv->display.update_wm = g4x_update_wm; |
| 7285 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; |
| 7286 | } else if (IS_GEN4(dev)) { |
| 7287 | dev_priv->display.update_wm = i965_update_wm; |
| 7288 | if (IS_CRESTLINE(dev)) |
| 7289 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
| 7290 | else if (IS_BROADWATER(dev)) |
| 7291 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
| 7292 | } else if (IS_GEN3(dev)) { |
| 7293 | dev_priv->display.update_wm = i9xx_update_wm; |
| 7294 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; |
| 7295 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 7296 | } else if (IS_GEN2(dev)) { |
| 7297 | if (INTEL_INFO(dev)->num_pipes == 1) { |
| 7298 | dev_priv->display.update_wm = i845_update_wm; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7299 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 7300 | } else { |
| 7301 | dev_priv->display.update_wm = i9xx_update_wm; |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7302 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
Daniel Vetter | feb56b9 | 2013-12-14 20:38:30 -0200 | [diff] [blame] | 7303 | } |
| 7304 | |
| 7305 | if (IS_I85X(dev) || IS_I865G(dev)) |
| 7306 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; |
| 7307 | else |
| 7308 | dev_priv->display.init_clock_gating = i830_init_clock_gating; |
| 7309 | } else { |
| 7310 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); |
Eugeni Dodonov | 1fa6110 | 2012-04-18 15:29:26 -0300 | [diff] [blame] | 7311 | } |
| 7312 | } |
| 7313 | |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 7314 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
| 7315 | { |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 7316 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 7317 | |
| 7318 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
| 7319 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); |
| 7320 | return -EAGAIN; |
| 7321 | } |
| 7322 | |
| 7323 | I915_WRITE(GEN6_PCODE_DATA, *val); |
| 7324 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
| 7325 | |
| 7326 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 7327 | 500)) { |
| 7328 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); |
| 7329 | return -ETIMEDOUT; |
| 7330 | } |
| 7331 | |
| 7332 | *val = I915_READ(GEN6_PCODE_DATA); |
| 7333 | I915_WRITE(GEN6_PCODE_DATA, 0); |
| 7334 | |
| 7335 | return 0; |
| 7336 | } |
| 7337 | |
| 7338 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) |
| 7339 | { |
Jesse Barnes | 4fc688c | 2012-11-02 11:14:01 -0700 | [diff] [blame] | 7340 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
Ben Widawsky | 42c0526 | 2012-09-26 10:34:00 -0700 | [diff] [blame] | 7341 | |
| 7342 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { |
| 7343 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); |
| 7344 | return -EAGAIN; |
| 7345 | } |
| 7346 | |
| 7347 | I915_WRITE(GEN6_PCODE_DATA, val); |
| 7348 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
| 7349 | |
| 7350 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, |
| 7351 | 500)) { |
| 7352 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); |
| 7353 | return -ETIMEDOUT; |
| 7354 | } |
| 7355 | |
| 7356 | I915_WRITE(GEN6_PCODE_DATA, 0); |
| 7357 | |
| 7358 | return 0; |
| 7359 | } |
Jesse Barnes | a0e4e19 | 2013-04-02 11:23:05 -0700 | [diff] [blame] | 7360 | |
Fengguang Wu | b55dd64 | 2014-07-12 11:21:39 +0200 | [diff] [blame] | 7361 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7362 | { |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 7363 | int div; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7364 | |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 7365 | /* 4 x czclk */ |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 7366 | switch (dev_priv->mem_freq) { |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7367 | case 800: |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 7368 | div = 10; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7369 | break; |
| 7370 | case 1066: |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 7371 | div = 12; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7372 | break; |
| 7373 | case 1333: |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 7374 | div = 16; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7375 | break; |
| 7376 | default: |
| 7377 | return -1; |
| 7378 | } |
| 7379 | |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 7380 | return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div); |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7381 | } |
| 7382 | |
Fengguang Wu | b55dd64 | 2014-07-12 11:21:39 +0200 | [diff] [blame] | 7383 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7384 | { |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 7385 | int mul; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7386 | |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 7387 | /* 4 x czclk */ |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 7388 | switch (dev_priv->mem_freq) { |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7389 | case 800: |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 7390 | mul = 10; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7391 | break; |
| 7392 | case 1066: |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 7393 | mul = 12; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7394 | break; |
| 7395 | case 1333: |
Ville Syrjälä | 07ab118 | 2013-11-05 22:42:28 +0200 | [diff] [blame] | 7396 | mul = 16; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7397 | break; |
| 7398 | default: |
| 7399 | return -1; |
| 7400 | } |
| 7401 | |
Ville Syrjälä | 2ec3815 | 2013-11-05 22:42:29 +0200 | [diff] [blame] | 7402 | return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; |
Jesse Barnes | 855ba3b | 2013-04-17 15:54:57 -0700 | [diff] [blame] | 7403 | } |
| 7404 | |
Fengguang Wu | b55dd64 | 2014-07-12 11:21:39 +0200 | [diff] [blame] | 7405 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 7406 | { |
| 7407 | int div, freq; |
| 7408 | |
| 7409 | switch (dev_priv->rps.cz_freq) { |
| 7410 | case 200: |
| 7411 | div = 5; |
| 7412 | break; |
| 7413 | case 267: |
| 7414 | div = 6; |
| 7415 | break; |
| 7416 | case 320: |
| 7417 | case 333: |
| 7418 | case 400: |
| 7419 | div = 8; |
| 7420 | break; |
| 7421 | default: |
| 7422 | return -1; |
| 7423 | } |
| 7424 | |
| 7425 | freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2); |
| 7426 | |
| 7427 | return freq; |
| 7428 | } |
| 7429 | |
Fengguang Wu | b55dd64 | 2014-07-12 11:21:39 +0200 | [diff] [blame] | 7430 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
Deepak S | 22b1b2f | 2014-07-12 14:54:33 +0530 | [diff] [blame] | 7431 | { |
| 7432 | int mul, opcode; |
| 7433 | |
| 7434 | switch (dev_priv->rps.cz_freq) { |
| 7435 | case 200: |
| 7436 | mul = 5; |
| 7437 | break; |
| 7438 | case 267: |
| 7439 | mul = 6; |
| 7440 | break; |
| 7441 | case 320: |
| 7442 | case 333: |
| 7443 | case 400: |
| 7444 | mul = 8; |
| 7445 | break; |
| 7446 | default: |
| 7447 | return -1; |
| 7448 | } |
| 7449 | |
| 7450 | opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2); |
| 7451 | |
| 7452 | return opcode; |
| 7453 | } |
| 7454 | |
| 7455 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
| 7456 | { |
| 7457 | int ret = -1; |
| 7458 | |
| 7459 | if (IS_CHERRYVIEW(dev_priv->dev)) |
| 7460 | ret = chv_gpu_freq(dev_priv, val); |
| 7461 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
| 7462 | ret = byt_gpu_freq(dev_priv, val); |
| 7463 | |
| 7464 | return ret; |
| 7465 | } |
| 7466 | |
| 7467 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
| 7468 | { |
| 7469 | int ret = -1; |
| 7470 | |
| 7471 | if (IS_CHERRYVIEW(dev_priv->dev)) |
| 7472 | ret = chv_freq_opcode(dev_priv, val); |
| 7473 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
| 7474 | ret = byt_freq_opcode(dev_priv, val); |
| 7475 | |
| 7476 | return ret; |
| 7477 | } |
| 7478 | |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 7479 | void intel_pm_setup(struct drm_device *dev) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 7480 | { |
| 7481 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 7482 | |
Daniel Vetter | f742a55 | 2013-12-06 10:17:53 +0100 | [diff] [blame] | 7483 | mutex_init(&dev_priv->rps.hw_lock); |
| 7484 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 7485 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
| 7486 | intel_gen6_powersave_work); |
Paulo Zanoni | 5d584b2 | 2014-03-07 20:08:15 -0300 | [diff] [blame] | 7487 | |
Paulo Zanoni | 33688d9 | 2014-03-07 20:08:19 -0300 | [diff] [blame] | 7488 | dev_priv->pm.suspended = false; |
Jesse Barnes | 9df7575f | 2014-06-20 09:29:20 -0700 | [diff] [blame] | 7489 | dev_priv->pm._irqs_disabled = false; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 7490 | } |