Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1 | /* |
Pierre Ossman | 70f1048 | 2007-07-11 20:04:50 +0200 | [diff] [blame] | 2 | * linux/drivers/mmc/host/sdhci.c - Secure Digital Host Controller Interface driver |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3 | * |
Pierre Ossman | b69c905 | 2008-03-08 23:44:25 +0100 | [diff] [blame] | 4 | * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
Pierre Ossman | 643f720 | 2006-09-30 23:27:52 -0700 | [diff] [blame] | 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License, or (at |
| 9 | * your option) any later version. |
Pierre Ossman | 84c46a5 | 2007-12-02 19:58:16 +0100 | [diff] [blame] | 10 | * |
| 11 | * Thanks to the following companies for their support: |
| 12 | * |
| 13 | * - JMicron (hardware and technical support) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 14 | */ |
| 15 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 16 | #include <linux/delay.h> |
| 17 | #include <linux/highmem.h> |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 18 | #include <linux/io.h> |
Paul Gortmaker | 88b4767 | 2011-07-03 15:15:51 -0400 | [diff] [blame] | 19 | #include <linux/module.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 20 | #include <linux/dma-mapping.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 21 | #include <linux/slab.h> |
Ralf Baechle | 1176360 | 2007-10-23 20:42:11 +0200 | [diff] [blame] | 22 | #include <linux/scatterlist.h> |
Marek Szyprowski | 9bea3c8 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 23 | #include <linux/regulator/consumer.h> |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 24 | #include <linux/pm_runtime.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 25 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 26 | #include <linux/leds.h> |
| 27 | |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 28 | #include <linux/mmc/mmc.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 29 | #include <linux/mmc/host.h> |
Aaron Lu | 473b095a | 2012-07-03 17:27:49 +0800 | [diff] [blame] | 30 | #include <linux/mmc/card.h> |
Corneliu Doban | 85cc1c3 | 2015-02-09 16:06:29 -0800 | [diff] [blame] | 31 | #include <linux/mmc/sdio.h> |
Guennadi Liakhovetski | bec9d4e | 2012-09-17 16:45:10 +0800 | [diff] [blame] | 32 | #include <linux/mmc/slot-gpio.h> |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 33 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 34 | #include "sdhci.h" |
| 35 | |
| 36 | #define DRIVER_NAME "sdhci" |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 37 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 38 | #define DBG(f, x...) \ |
Russell King | c656317 | 2006-03-29 09:30:20 +0100 | [diff] [blame] | 39 | pr_debug(DRIVER_NAME " [%s()]: " f, __func__,## x) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 40 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 41 | #define MAX_TUNING_LOOP 40 |
| 42 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 43 | static unsigned int debug_quirks = 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 44 | static unsigned int debug_quirks2; |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 45 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 46 | static void sdhci_finish_data(struct sdhci_host *); |
| 47 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 48 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 49 | |
| 50 | static void sdhci_dumpregs(struct sdhci_host *host) |
| 51 | { |
Chuanxiao Dong | a7c5367 | 2016-06-22 14:40:01 +0300 | [diff] [blame] | 52 | pr_err(DRIVER_NAME ": =========== REGISTER DUMP (%s)===========\n", |
| 53 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 54 | |
Chuanxiao Dong | a7c5367 | 2016-06-22 14:40:01 +0300 | [diff] [blame] | 55 | pr_err(DRIVER_NAME ": Sys addr: 0x%08x | Version: 0x%08x\n", |
| 56 | sdhci_readl(host, SDHCI_DMA_ADDRESS), |
| 57 | sdhci_readw(host, SDHCI_HOST_VERSION)); |
| 58 | pr_err(DRIVER_NAME ": Blk size: 0x%08x | Blk cnt: 0x%08x\n", |
| 59 | sdhci_readw(host, SDHCI_BLOCK_SIZE), |
| 60 | sdhci_readw(host, SDHCI_BLOCK_COUNT)); |
| 61 | pr_err(DRIVER_NAME ": Argument: 0x%08x | Trn mode: 0x%08x\n", |
| 62 | sdhci_readl(host, SDHCI_ARGUMENT), |
| 63 | sdhci_readw(host, SDHCI_TRANSFER_MODE)); |
| 64 | pr_err(DRIVER_NAME ": Present: 0x%08x | Host ctl: 0x%08x\n", |
| 65 | sdhci_readl(host, SDHCI_PRESENT_STATE), |
| 66 | sdhci_readb(host, SDHCI_HOST_CONTROL)); |
| 67 | pr_err(DRIVER_NAME ": Power: 0x%08x | Blk gap: 0x%08x\n", |
| 68 | sdhci_readb(host, SDHCI_POWER_CONTROL), |
| 69 | sdhci_readb(host, SDHCI_BLOCK_GAP_CONTROL)); |
| 70 | pr_err(DRIVER_NAME ": Wake-up: 0x%08x | Clock: 0x%08x\n", |
| 71 | sdhci_readb(host, SDHCI_WAKE_UP_CONTROL), |
| 72 | sdhci_readw(host, SDHCI_CLOCK_CONTROL)); |
| 73 | pr_err(DRIVER_NAME ": Timeout: 0x%08x | Int stat: 0x%08x\n", |
| 74 | sdhci_readb(host, SDHCI_TIMEOUT_CONTROL), |
| 75 | sdhci_readl(host, SDHCI_INT_STATUS)); |
| 76 | pr_err(DRIVER_NAME ": Int enab: 0x%08x | Sig enab: 0x%08x\n", |
| 77 | sdhci_readl(host, SDHCI_INT_ENABLE), |
| 78 | sdhci_readl(host, SDHCI_SIGNAL_ENABLE)); |
| 79 | pr_err(DRIVER_NAME ": AC12 err: 0x%08x | Slot int: 0x%08x\n", |
| 80 | sdhci_readw(host, SDHCI_ACMD12_ERR), |
| 81 | sdhci_readw(host, SDHCI_SLOT_INT_STATUS)); |
| 82 | pr_err(DRIVER_NAME ": Caps: 0x%08x | Caps_1: 0x%08x\n", |
| 83 | sdhci_readl(host, SDHCI_CAPABILITIES), |
| 84 | sdhci_readl(host, SDHCI_CAPABILITIES_1)); |
| 85 | pr_err(DRIVER_NAME ": Cmd: 0x%08x | Max curr: 0x%08x\n", |
| 86 | sdhci_readw(host, SDHCI_COMMAND), |
| 87 | sdhci_readl(host, SDHCI_MAX_CURRENT)); |
| 88 | pr_err(DRIVER_NAME ": Host ctl2: 0x%08x\n", |
| 89 | sdhci_readw(host, SDHCI_HOST_CONTROL2)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 90 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 91 | if (host->flags & SDHCI_USE_ADMA) { |
| 92 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
Chuanxiao Dong | a7c5367 | 2016-06-22 14:40:01 +0300 | [diff] [blame] | 93 | pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x%08x\n", |
| 94 | readl(host->ioaddr + SDHCI_ADMA_ERROR), |
| 95 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS_HI), |
| 96 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 97 | else |
Chuanxiao Dong | a7c5367 | 2016-06-22 14:40:01 +0300 | [diff] [blame] | 98 | pr_err(DRIVER_NAME ": ADMA Err: 0x%08x | ADMA Ptr: 0x%08x\n", |
| 99 | readl(host->ioaddr + SDHCI_ADMA_ERROR), |
| 100 | readl(host->ioaddr + SDHCI_ADMA_ADDRESS)); |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 101 | } |
Ben Dooks | be3f4ae | 2009-06-08 23:33:52 +0100 | [diff] [blame] | 102 | |
Chuanxiao Dong | a7c5367 | 2016-06-22 14:40:01 +0300 | [diff] [blame] | 103 | pr_err(DRIVER_NAME ": ===========================================\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 104 | } |
| 105 | |
| 106 | /*****************************************************************************\ |
| 107 | * * |
| 108 | * Low level functions * |
| 109 | * * |
| 110 | \*****************************************************************************/ |
| 111 | |
Adrian Hunter | 56a590d | 2016-06-29 16:24:32 +0300 | [diff] [blame] | 112 | static inline bool sdhci_data_line_cmd(struct mmc_command *cmd) |
| 113 | { |
| 114 | return cmd->data || cmd->flags & MMC_RSP_BUSY; |
| 115 | } |
| 116 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 117 | static void sdhci_set_card_detection(struct sdhci_host *host, bool enable) |
| 118 | { |
Russell King | 5b4f1f6 | 2014-04-25 12:57:02 +0100 | [diff] [blame] | 119 | u32 present; |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 120 | |
Adrian Hunter | c79396c | 2011-12-27 15:48:42 +0200 | [diff] [blame] | 121 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) || |
Jaehoon Chung | 860951c | 2016-06-21 10:13:26 +0900 | [diff] [blame] | 122 | !mmc_card_is_removable(host->mmc)) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 123 | return; |
| 124 | |
Russell King | 5b4f1f6 | 2014-04-25 12:57:02 +0100 | [diff] [blame] | 125 | if (enable) { |
| 126 | present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
| 127 | SDHCI_CARD_PRESENT; |
Shawn Guo | d25928d | 2011-06-21 22:41:48 +0800 | [diff] [blame] | 128 | |
Russell King | 5b4f1f6 | 2014-04-25 12:57:02 +0100 | [diff] [blame] | 129 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
| 130 | SDHCI_INT_CARD_INSERT; |
| 131 | } else { |
| 132 | host->ier &= ~(SDHCI_INT_CARD_REMOVE | SDHCI_INT_CARD_INSERT); |
| 133 | } |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 134 | |
| 135 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 136 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 137 | } |
| 138 | |
| 139 | static void sdhci_enable_card_detection(struct sdhci_host *host) |
| 140 | { |
| 141 | sdhci_set_card_detection(host, true); |
| 142 | } |
| 143 | |
| 144 | static void sdhci_disable_card_detection(struct sdhci_host *host) |
| 145 | { |
| 146 | sdhci_set_card_detection(host, false); |
| 147 | } |
| 148 | |
Ulf Hansson | 02d0b68 | 2016-04-11 15:32:41 +0200 | [diff] [blame] | 149 | static void sdhci_runtime_pm_bus_on(struct sdhci_host *host) |
| 150 | { |
| 151 | if (host->bus_on) |
| 152 | return; |
| 153 | host->bus_on = true; |
| 154 | pm_runtime_get_noresume(host->mmc->parent); |
| 155 | } |
| 156 | |
| 157 | static void sdhci_runtime_pm_bus_off(struct sdhci_host *host) |
| 158 | { |
| 159 | if (!host->bus_on) |
| 160 | return; |
| 161 | host->bus_on = false; |
| 162 | pm_runtime_put_noidle(host->mmc->parent); |
| 163 | } |
| 164 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 165 | void sdhci_reset(struct sdhci_host *host, u8 mask) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 166 | { |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 167 | unsigned long timeout; |
Philip Rakity | 393c1a3 | 2011-01-21 11:26:40 -0800 | [diff] [blame] | 168 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 169 | sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 170 | |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 171 | if (mask & SDHCI_RESET_ALL) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 172 | host->clock = 0; |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 173 | /* Reset-all turns off SD Bus Power */ |
| 174 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
| 175 | sdhci_runtime_pm_bus_off(host); |
| 176 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 177 | |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 178 | /* Wait max 100 ms */ |
| 179 | timeout = 100; |
| 180 | |
| 181 | /* hw clears the bit when it's done */ |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 182 | while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) { |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 183 | if (timeout == 0) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 184 | pr_err("%s: Reset 0x%x never completed.\n", |
Pierre Ossman | e16514d8 | 2006-06-30 02:22:24 -0700 | [diff] [blame] | 185 | mmc_hostname(host->mmc), (int)mask); |
| 186 | sdhci_dumpregs(host); |
| 187 | return; |
| 188 | } |
| 189 | timeout--; |
| 190 | mdelay(1); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 191 | } |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 192 | } |
| 193 | EXPORT_SYMBOL_GPL(sdhci_reset); |
Anton Vorontsov | 063a9db | 2009-03-17 00:14:02 +0300 | [diff] [blame] | 194 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 195 | static void sdhci_do_reset(struct sdhci_host *host, u8 mask) |
| 196 | { |
| 197 | if (host->quirks & SDHCI_QUIRK_NO_CARD_NO_RESET) { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 198 | struct mmc_host *mmc = host->mmc; |
| 199 | |
| 200 | if (!mmc->ops->get_cd(mmc)) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 201 | return; |
| 202 | } |
| 203 | |
| 204 | host->ops->reset(host, mask); |
Philip Rakity | 393c1a3 | 2011-01-21 11:26:40 -0800 | [diff] [blame] | 205 | |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 206 | if (mask & SDHCI_RESET_ALL) { |
| 207 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
| 208 | if (host->ops->enable_dma) |
| 209 | host->ops->enable_dma(host); |
| 210 | } |
| 211 | |
| 212 | /* Resetting the controller clears many */ |
| 213 | host->preset_enabled = false; |
Shaohui Xie | 3abc1e80 | 2011-12-29 16:33:00 +0800 | [diff] [blame] | 214 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 215 | } |
| 216 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 217 | static void sdhci_init(struct sdhci_host *host, int soft) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 218 | { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 219 | struct mmc_host *mmc = host->mmc; |
| 220 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 221 | if (soft) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 222 | sdhci_do_reset(host, SDHCI_RESET_CMD|SDHCI_RESET_DATA); |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 223 | else |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 224 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 225 | |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 226 | host->ier = SDHCI_INT_BUS_POWER | SDHCI_INT_DATA_END_BIT | |
| 227 | SDHCI_INT_DATA_CRC | SDHCI_INT_DATA_TIMEOUT | |
| 228 | SDHCI_INT_INDEX | SDHCI_INT_END_BIT | SDHCI_INT_CRC | |
| 229 | SDHCI_INT_TIMEOUT | SDHCI_INT_DATA_END | |
| 230 | SDHCI_INT_RESPONSE; |
| 231 | |
| 232 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 233 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 234 | |
| 235 | if (soft) { |
| 236 | /* force clock reconfiguration */ |
| 237 | host->clock = 0; |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 238 | mmc->ops->set_ios(mmc, &mmc->ios); |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 239 | } |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 240 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 241 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 242 | static void sdhci_reinit(struct sdhci_host *host) |
| 243 | { |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 244 | sdhci_init(host, 0); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 245 | sdhci_enable_card_detection(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 246 | } |
| 247 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 248 | static void __sdhci_led_activate(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 249 | { |
| 250 | u8 ctrl; |
| 251 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 252 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 253 | ctrl |= SDHCI_CTRL_LED; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 254 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 255 | } |
| 256 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 257 | static void __sdhci_led_deactivate(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 258 | { |
| 259 | u8 ctrl; |
| 260 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 261 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 262 | ctrl &= ~SDHCI_CTRL_LED; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 263 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 264 | } |
| 265 | |
Masahiro Yamada | 4f78230 | 2016-04-14 13:19:39 +0900 | [diff] [blame] | 266 | #if IS_REACHABLE(CONFIG_LEDS_CLASS) |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 267 | static void sdhci_led_control(struct led_classdev *led, |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 268 | enum led_brightness brightness) |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 269 | { |
| 270 | struct sdhci_host *host = container_of(led, struct sdhci_host, led); |
| 271 | unsigned long flags; |
| 272 | |
| 273 | spin_lock_irqsave(&host->lock, flags); |
| 274 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 275 | if (host->runtime_suspended) |
| 276 | goto out; |
| 277 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 278 | if (brightness == LED_OFF) |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 279 | __sdhci_led_deactivate(host); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 280 | else |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 281 | __sdhci_led_activate(host); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 282 | out: |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 283 | spin_unlock_irqrestore(&host->lock, flags); |
| 284 | } |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 285 | |
| 286 | static int sdhci_led_register(struct sdhci_host *host) |
| 287 | { |
| 288 | struct mmc_host *mmc = host->mmc; |
| 289 | |
| 290 | snprintf(host->led_name, sizeof(host->led_name), |
| 291 | "%s::", mmc_hostname(mmc)); |
| 292 | |
| 293 | host->led.name = host->led_name; |
| 294 | host->led.brightness = LED_OFF; |
| 295 | host->led.default_trigger = mmc_hostname(mmc); |
| 296 | host->led.brightness_set = sdhci_led_control; |
| 297 | |
| 298 | return led_classdev_register(mmc_dev(mmc), &host->led); |
| 299 | } |
| 300 | |
| 301 | static void sdhci_led_unregister(struct sdhci_host *host) |
| 302 | { |
| 303 | led_classdev_unregister(&host->led); |
| 304 | } |
| 305 | |
| 306 | static inline void sdhci_led_activate(struct sdhci_host *host) |
| 307 | { |
| 308 | } |
| 309 | |
| 310 | static inline void sdhci_led_deactivate(struct sdhci_host *host) |
| 311 | { |
| 312 | } |
| 313 | |
| 314 | #else |
| 315 | |
| 316 | static inline int sdhci_led_register(struct sdhci_host *host) |
| 317 | { |
| 318 | return 0; |
| 319 | } |
| 320 | |
| 321 | static inline void sdhci_led_unregister(struct sdhci_host *host) |
| 322 | { |
| 323 | } |
| 324 | |
| 325 | static inline void sdhci_led_activate(struct sdhci_host *host) |
| 326 | { |
| 327 | __sdhci_led_activate(host); |
| 328 | } |
| 329 | |
| 330 | static inline void sdhci_led_deactivate(struct sdhci_host *host) |
| 331 | { |
| 332 | __sdhci_led_deactivate(host); |
| 333 | } |
| 334 | |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 335 | #endif |
| 336 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 337 | /*****************************************************************************\ |
| 338 | * * |
| 339 | * Core functions * |
| 340 | * * |
| 341 | \*****************************************************************************/ |
| 342 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 343 | static void sdhci_read_block_pio(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 344 | { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 345 | unsigned long flags; |
| 346 | size_t blksize, len, chunk; |
Steven Noonan | 7244b85 | 2008-10-01 01:50:25 -0700 | [diff] [blame] | 347 | u32 uninitialized_var(scratch); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 348 | u8 *buf; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 349 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 350 | DBG("PIO reading\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 351 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 352 | blksize = host->data->blksz; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 353 | chunk = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 354 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 355 | local_irq_save(flags); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 356 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 357 | while (blksize) { |
Fabio Estevam | bf3a35a | 2015-05-09 18:44:51 -0300 | [diff] [blame] | 358 | BUG_ON(!sg_miter_next(&host->sg_miter)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 359 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 360 | len = min(host->sg_miter.length, blksize); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 361 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 362 | blksize -= len; |
| 363 | host->sg_miter.consumed = len; |
Alex Dubov | 14d836e | 2007-04-13 19:04:38 +0200 | [diff] [blame] | 364 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 365 | buf = host->sg_miter.addr; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 366 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 367 | while (len) { |
| 368 | if (chunk == 0) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 369 | scratch = sdhci_readl(host, SDHCI_BUFFER); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 370 | chunk = 4; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 371 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 372 | |
| 373 | *buf = scratch & 0xFF; |
| 374 | |
| 375 | buf++; |
| 376 | scratch >>= 8; |
| 377 | chunk--; |
| 378 | len--; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 379 | } |
| 380 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 381 | |
| 382 | sg_miter_stop(&host->sg_miter); |
| 383 | |
| 384 | local_irq_restore(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 385 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 386 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 387 | static void sdhci_write_block_pio(struct sdhci_host *host) |
| 388 | { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 389 | unsigned long flags; |
| 390 | size_t blksize, len, chunk; |
| 391 | u32 scratch; |
| 392 | u8 *buf; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 393 | |
| 394 | DBG("PIO writing\n"); |
| 395 | |
| 396 | blksize = host->data->blksz; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 397 | chunk = 0; |
| 398 | scratch = 0; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 399 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 400 | local_irq_save(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 401 | |
| 402 | while (blksize) { |
Fabio Estevam | bf3a35a | 2015-05-09 18:44:51 -0300 | [diff] [blame] | 403 | BUG_ON(!sg_miter_next(&host->sg_miter)); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 404 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 405 | len = min(host->sg_miter.length, blksize); |
Alex Dubov | 14d836e | 2007-04-13 19:04:38 +0200 | [diff] [blame] | 406 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 407 | blksize -= len; |
| 408 | host->sg_miter.consumed = len; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 409 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 410 | buf = host->sg_miter.addr; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 411 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 412 | while (len) { |
| 413 | scratch |= (u32)*buf << (chunk * 8); |
| 414 | |
| 415 | buf++; |
| 416 | chunk++; |
| 417 | len--; |
| 418 | |
| 419 | if ((chunk == 4) || ((len == 0) && (blksize == 0))) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 420 | sdhci_writel(host, scratch, SDHCI_BUFFER); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 421 | chunk = 0; |
| 422 | scratch = 0; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 423 | } |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 424 | } |
| 425 | } |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 426 | |
| 427 | sg_miter_stop(&host->sg_miter); |
| 428 | |
| 429 | local_irq_restore(flags); |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | static void sdhci_transfer_pio(struct sdhci_host *host) |
| 433 | { |
| 434 | u32 mask; |
| 435 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 436 | if (host->blocks == 0) |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 437 | return; |
| 438 | |
| 439 | if (host->data->flags & MMC_DATA_READ) |
| 440 | mask = SDHCI_DATA_AVAILABLE; |
| 441 | else |
| 442 | mask = SDHCI_SPACE_AVAILABLE; |
| 443 | |
Pierre Ossman | 4a3cba3 | 2008-07-29 00:11:16 +0200 | [diff] [blame] | 444 | /* |
| 445 | * Some controllers (JMicron JMB38x) mess up the buffer bits |
| 446 | * for transfers < 4 bytes. As long as it is just one block, |
| 447 | * we can ignore the bits. |
| 448 | */ |
| 449 | if ((host->quirks & SDHCI_QUIRK_BROKEN_SMALL_PIO) && |
| 450 | (host->data->blocks == 1)) |
| 451 | mask = ~0; |
| 452 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 453 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
Anton Vorontsov | 3e3bf20 | 2009-03-17 00:14:00 +0300 | [diff] [blame] | 454 | if (host->quirks & SDHCI_QUIRK_PIO_NEEDS_DELAY) |
| 455 | udelay(100); |
| 456 | |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 457 | if (host->data->flags & MMC_DATA_READ) |
| 458 | sdhci_read_block_pio(host); |
| 459 | else |
| 460 | sdhci_write_block_pio(host); |
| 461 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 462 | host->blocks--; |
| 463 | if (host->blocks == 0) |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 464 | break; |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 465 | } |
| 466 | |
| 467 | DBG("PIO transfer complete.\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 468 | } |
| 469 | |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 470 | static int sdhci_pre_dma_transfer(struct sdhci_host *host, |
Russell King | c0999b7 | 2016-01-26 13:40:27 +0000 | [diff] [blame] | 471 | struct mmc_data *data, int cookie) |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 472 | { |
| 473 | int sg_count; |
| 474 | |
Russell King | 94538e5 | 2016-01-26 13:40:37 +0000 | [diff] [blame] | 475 | /* |
| 476 | * If the data buffers are already mapped, return the previous |
| 477 | * dma_map_sg() result. |
| 478 | */ |
| 479 | if (data->host_cookie == COOKIE_PRE_MAPPED) |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 480 | return data->sg_count; |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 481 | |
| 482 | sg_count = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
| 483 | data->flags & MMC_DATA_WRITE ? |
| 484 | DMA_TO_DEVICE : DMA_FROM_DEVICE); |
| 485 | |
| 486 | if (sg_count == 0) |
| 487 | return -ENOSPC; |
| 488 | |
| 489 | data->sg_count = sg_count; |
Russell King | c0999b7 | 2016-01-26 13:40:27 +0000 | [diff] [blame] | 490 | data->host_cookie = cookie; |
Russell King | 48857d9 | 2016-01-26 13:40:16 +0000 | [diff] [blame] | 491 | |
| 492 | return sg_count; |
| 493 | } |
| 494 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 495 | static char *sdhci_kmap_atomic(struct scatterlist *sg, unsigned long *flags) |
| 496 | { |
| 497 | local_irq_save(*flags); |
Cong Wang | 482fce9 | 2011-11-27 13:27:00 +0800 | [diff] [blame] | 498 | return kmap_atomic(sg_page(sg)) + sg->offset; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | static void sdhci_kunmap_atomic(void *buffer, unsigned long *flags) |
| 502 | { |
Cong Wang | 482fce9 | 2011-11-27 13:27:00 +0800 | [diff] [blame] | 503 | kunmap_atomic(buffer); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 504 | local_irq_restore(*flags); |
| 505 | } |
| 506 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 507 | static void sdhci_adma_write_desc(struct sdhci_host *host, void *desc, |
| 508 | dma_addr_t addr, int len, unsigned cmd) |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 509 | { |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 510 | struct sdhci_adma2_64_desc *dma_desc = desc; |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 511 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 512 | /* 32-bit and 64-bit descriptors have these members in same position */ |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 513 | dma_desc->cmd = cpu_to_le16(cmd); |
| 514 | dma_desc->len = cpu_to_le16(len); |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 515 | dma_desc->addr_lo = cpu_to_le32((u32)addr); |
| 516 | |
| 517 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 518 | dma_desc->addr_hi = cpu_to_le32((u64)addr >> 32); |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 519 | } |
| 520 | |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 521 | static void sdhci_adma_mark_end(void *desc) |
| 522 | { |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 523 | struct sdhci_adma2_64_desc *dma_desc = desc; |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 524 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 525 | /* 32-bit and 64-bit descriptors have 'cmd' in same position */ |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 526 | dma_desc->cmd |= cpu_to_le16(ADMA2_END); |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 527 | } |
| 528 | |
Russell King | 60c6476 | 2016-01-26 13:40:22 +0000 | [diff] [blame] | 529 | static void sdhci_adma_table_pre(struct sdhci_host *host, |
| 530 | struct mmc_data *data, int sg_count) |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 531 | { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 532 | struct scatterlist *sg; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 533 | unsigned long flags; |
Russell King | acc3ad1 | 2016-01-26 13:40:00 +0000 | [diff] [blame] | 534 | dma_addr_t addr, align_addr; |
| 535 | void *desc, *align; |
| 536 | char *buffer; |
| 537 | int len, offset, i; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 538 | |
| 539 | /* |
| 540 | * The spec does not specify endianness of descriptor table. |
| 541 | * We currently guess that it is LE. |
| 542 | */ |
| 543 | |
Russell King | 60c6476 | 2016-01-26 13:40:22 +0000 | [diff] [blame] | 544 | host->sg_count = sg_count; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 545 | |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 546 | desc = host->adma_table; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 547 | align = host->align_buffer; |
| 548 | |
| 549 | align_addr = host->align_addr; |
| 550 | |
| 551 | for_each_sg(data->sg, sg, host->sg_count, i) { |
| 552 | addr = sg_dma_address(sg); |
| 553 | len = sg_dma_len(sg); |
| 554 | |
| 555 | /* |
Russell King | acc3ad1 | 2016-01-26 13:40:00 +0000 | [diff] [blame] | 556 | * The SDHCI specification states that ADMA addresses must |
| 557 | * be 32-bit aligned. If they aren't, then we use a bounce |
| 558 | * buffer for the (up to three) bytes that screw up the |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 559 | * alignment. |
| 560 | */ |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 561 | offset = (SDHCI_ADMA2_ALIGN - (addr & SDHCI_ADMA2_MASK)) & |
| 562 | SDHCI_ADMA2_MASK; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 563 | if (offset) { |
| 564 | if (data->flags & MMC_DATA_WRITE) { |
| 565 | buffer = sdhci_kmap_atomic(sg, &flags); |
| 566 | memcpy(align, buffer, offset); |
| 567 | sdhci_kunmap_atomic(buffer, &flags); |
| 568 | } |
| 569 | |
Ben Dooks | 118cd17 | 2010-03-05 13:43:26 -0800 | [diff] [blame] | 570 | /* tran, valid */ |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 571 | sdhci_adma_write_desc(host, desc, align_addr, offset, |
Adrian Hunter | 739d46d | 2014-11-04 12:42:44 +0200 | [diff] [blame] | 572 | ADMA2_TRAN_VALID); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 573 | |
| 574 | BUG_ON(offset > 65536); |
| 575 | |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 576 | align += SDHCI_ADMA2_ALIGN; |
| 577 | align_addr += SDHCI_ADMA2_ALIGN; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 578 | |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 579 | desc += host->desc_sz; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 580 | |
| 581 | addr += offset; |
| 582 | len -= offset; |
| 583 | } |
| 584 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 585 | BUG_ON(len > 65536); |
| 586 | |
Adrian Hunter | 347ea32 | 2015-11-26 14:00:48 +0200 | [diff] [blame] | 587 | if (len) { |
| 588 | /* tran, valid */ |
| 589 | sdhci_adma_write_desc(host, desc, addr, len, |
| 590 | ADMA2_TRAN_VALID); |
| 591 | desc += host->desc_sz; |
| 592 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 593 | |
| 594 | /* |
| 595 | * If this triggers then we have a calculation bug |
| 596 | * somewhere. :/ |
| 597 | */ |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 598 | WARN_ON((desc - host->adma_table) >= host->adma_table_sz); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 599 | } |
| 600 | |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 601 | if (host->quirks & SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC) { |
Russell King | acc3ad1 | 2016-01-26 13:40:00 +0000 | [diff] [blame] | 602 | /* Mark the last descriptor as the terminating descriptor */ |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 603 | if (desc != host->adma_table) { |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 604 | desc -= host->desc_sz; |
Adrian Hunter | b5ffa67 | 2014-11-04 12:42:40 +0200 | [diff] [blame] | 605 | sdhci_adma_mark_end(desc); |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 606 | } |
| 607 | } else { |
Russell King | acc3ad1 | 2016-01-26 13:40:00 +0000 | [diff] [blame] | 608 | /* Add a terminating entry - nop, end, valid */ |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 609 | sdhci_adma_write_desc(host, desc, 0, 0, ADMA2_NOP_END_VALID); |
Thomas Abraham | 70764a9 | 2010-05-26 14:42:04 -0700 | [diff] [blame] | 610 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 611 | } |
| 612 | |
| 613 | static void sdhci_adma_table_post(struct sdhci_host *host, |
| 614 | struct mmc_data *data) |
| 615 | { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 616 | struct scatterlist *sg; |
| 617 | int i, size; |
Adrian Hunter | 1c3d5f6 | 2014-11-04 12:42:41 +0200 | [diff] [blame] | 618 | void *align; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 619 | char *buffer; |
| 620 | unsigned long flags; |
| 621 | |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 622 | if (data->flags & MMC_DATA_READ) { |
| 623 | bool has_unaligned = false; |
Russell King | de0b65a | 2014-04-25 12:58:29 +0100 | [diff] [blame] | 624 | |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 625 | /* Do a quick scan of the SG list for any unaligned mappings */ |
| 626 | for_each_sg(data->sg, sg, host->sg_count, i) |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 627 | if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 628 | has_unaligned = true; |
| 629 | break; |
| 630 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 631 | |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 632 | if (has_unaligned) { |
| 633 | dma_sync_sg_for_cpu(mmc_dev(host->mmc), data->sg, |
Russell King | f55c98f | 2016-01-26 13:40:11 +0000 | [diff] [blame] | 634 | data->sg_len, DMA_FROM_DEVICE); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 635 | |
Russell King | 47fa961 | 2016-01-26 13:40:06 +0000 | [diff] [blame] | 636 | align = host->align_buffer; |
| 637 | |
| 638 | for_each_sg(data->sg, sg, host->sg_count, i) { |
| 639 | if (sg_dma_address(sg) & SDHCI_ADMA2_MASK) { |
| 640 | size = SDHCI_ADMA2_ALIGN - |
| 641 | (sg_dma_address(sg) & SDHCI_ADMA2_MASK); |
| 642 | |
| 643 | buffer = sdhci_kmap_atomic(sg, &flags); |
| 644 | memcpy(buffer, align, size); |
| 645 | sdhci_kunmap_atomic(buffer, &flags); |
| 646 | |
| 647 | align += SDHCI_ADMA2_ALIGN; |
| 648 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 649 | } |
| 650 | } |
| 651 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 652 | } |
| 653 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 654 | static u8 sdhci_calc_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 655 | { |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 656 | u8 count; |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 657 | struct mmc_data *data = cmd->data; |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 658 | unsigned target_timeout, current_timeout; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 659 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 660 | /* |
| 661 | * If the host controller provides us with an incorrect timeout |
| 662 | * value, just skip the check and use 0xE. The hardware may take |
| 663 | * longer to time out, but that's much better than having a too-short |
| 664 | * timeout value. |
| 665 | */ |
Pierre Ossman | 11a2f1b | 2009-06-21 20:59:33 +0200 | [diff] [blame] | 666 | if (host->quirks & SDHCI_QUIRK_BROKEN_TIMEOUT_VAL) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 667 | return 0xE; |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 668 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 669 | /* Unspecified timeout, assume max */ |
Ulf Hansson | 1d4d774 | 2014-01-08 15:06:08 +0100 | [diff] [blame] | 670 | if (!data && !cmd->busy_timeout) |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 671 | return 0xE; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 672 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 673 | /* timeout in us */ |
| 674 | if (!data) |
Ulf Hansson | 1d4d774 | 2014-01-08 15:06:08 +0100 | [diff] [blame] | 675 | target_timeout = cmd->busy_timeout * 1000; |
Andy Shevchenko | 78a2ca2 | 2011-08-03 18:35:59 +0300 | [diff] [blame] | 676 | else { |
Russell King | fafcfda | 2016-01-26 13:40:58 +0000 | [diff] [blame] | 677 | target_timeout = DIV_ROUND_UP(data->timeout_ns, 1000); |
Russell King | 7f05538 | 2016-01-26 13:41:04 +0000 | [diff] [blame] | 678 | if (host->clock && data->timeout_clks) { |
| 679 | unsigned long long val; |
| 680 | |
| 681 | /* |
| 682 | * data->timeout_clks is in units of clock cycles. |
| 683 | * host->clock is in Hz. target_timeout is in us. |
| 684 | * Hence, us = 1000000 * cycles / Hz. Round up. |
| 685 | */ |
| 686 | val = 1000000 * data->timeout_clks; |
| 687 | if (do_div(val, host->clock)) |
| 688 | target_timeout++; |
| 689 | target_timeout += val; |
| 690 | } |
Andy Shevchenko | 78a2ca2 | 2011-08-03 18:35:59 +0300 | [diff] [blame] | 691 | } |
Anton Vorontsov | 81b3980 | 2009-09-22 16:45:13 -0700 | [diff] [blame] | 692 | |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 693 | /* |
| 694 | * Figure out needed cycles. |
| 695 | * We do this in steps in order to fit inside a 32 bit int. |
| 696 | * The first step is the minimum timeout, which will have a |
| 697 | * minimum resolution of 6 bits: |
| 698 | * (1) 2^13*1000 > 2^22, |
| 699 | * (2) host->timeout_clk < 2^16 |
| 700 | * => |
| 701 | * (1) / (2) > 2^6 |
| 702 | */ |
| 703 | count = 0; |
| 704 | current_timeout = (1 << 13) * 1000 / host->timeout_clk; |
| 705 | while (current_timeout < target_timeout) { |
| 706 | count++; |
| 707 | current_timeout <<= 1; |
| 708 | if (count >= 0xF) |
| 709 | break; |
| 710 | } |
| 711 | |
| 712 | if (count >= 0xF) { |
Chris Ball | 09eeff5 | 2012-06-01 10:39:45 -0400 | [diff] [blame] | 713 | DBG("%s: Too large timeout 0x%x requested for CMD%d!\n", |
| 714 | mmc_hostname(host->mmc), count, cmd->opcode); |
Pierre Ossman | 1c8cde9 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 715 | count = 0xE; |
| 716 | } |
| 717 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 718 | return count; |
| 719 | } |
| 720 | |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 721 | static void sdhci_set_transfer_irqs(struct sdhci_host *host) |
| 722 | { |
| 723 | u32 pio_irqs = SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL; |
| 724 | u32 dma_irqs = SDHCI_INT_DMA_END | SDHCI_INT_ADMA_ERROR; |
| 725 | |
| 726 | if (host->flags & SDHCI_REQ_USE_DMA) |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 727 | host->ier = (host->ier & ~pio_irqs) | dma_irqs; |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 728 | else |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 729 | host->ier = (host->ier & ~dma_irqs) | pio_irqs; |
| 730 | |
| 731 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 732 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 733 | } |
| 734 | |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 735 | static void sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 736 | { |
| 737 | u8 count; |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 738 | |
| 739 | if (host->ops->set_timeout) { |
| 740 | host->ops->set_timeout(host, cmd); |
| 741 | } else { |
| 742 | count = sdhci_calc_timeout(host, cmd); |
| 743 | sdhci_writeb(host, count, SDHCI_TIMEOUT_CONTROL); |
| 744 | } |
| 745 | } |
| 746 | |
| 747 | static void sdhci_prepare_data(struct sdhci_host *host, struct mmc_command *cmd) |
| 748 | { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 749 | u8 ctrl; |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 750 | struct mmc_data *data = cmd->data; |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 751 | |
Adrian Hunter | 56a590d | 2016-06-29 16:24:32 +0300 | [diff] [blame] | 752 | if (sdhci_data_line_cmd(cmd)) |
Aisheng Dong | b45e668 | 2014-08-27 15:26:29 +0800 | [diff] [blame] | 753 | sdhci_set_timeout(host, cmd); |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 754 | |
| 755 | if (!data) |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 756 | return; |
| 757 | |
Adrian Hunter | 43dea09 | 2016-06-29 16:24:26 +0300 | [diff] [blame] | 758 | WARN_ON(host->data); |
| 759 | |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 760 | /* Sanity checks */ |
| 761 | BUG_ON(data->blksz * data->blocks > 524288); |
| 762 | BUG_ON(data->blksz > host->mmc->max_blk_size); |
| 763 | BUG_ON(data->blocks > 65535); |
| 764 | |
| 765 | host->data = data; |
| 766 | host->data_early = 0; |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 767 | host->data->bytes_xfered = 0; |
Pierre Ossman | ee53ab5 | 2008-07-05 00:25:15 +0200 | [diff] [blame] | 768 | |
Russell King | fce1442 | 2016-01-26 13:41:20 +0000 | [diff] [blame] | 769 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 770 | struct scatterlist *sg; |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 771 | unsigned int length_mask, offset_mask; |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 772 | int i; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 773 | |
Russell King | fce1442 | 2016-01-26 13:41:20 +0000 | [diff] [blame] | 774 | host->flags |= SDHCI_REQ_USE_DMA; |
| 775 | |
| 776 | /* |
| 777 | * FIXME: This doesn't account for merging when mapping the |
| 778 | * scatterlist. |
| 779 | * |
| 780 | * The assumption here being that alignment and lengths are |
| 781 | * the same after DMA mapping to device address space. |
| 782 | */ |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 783 | length_mask = 0; |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 784 | offset_mask = 0; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 785 | if (host->flags & SDHCI_USE_ADMA) { |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 786 | if (host->quirks & SDHCI_QUIRK_32BIT_ADMA_SIZE) { |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 787 | length_mask = 3; |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 788 | /* |
| 789 | * As we use up to 3 byte chunks to work |
| 790 | * around alignment problems, we need to |
| 791 | * check the offset as well. |
| 792 | */ |
| 793 | offset_mask = 3; |
| 794 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 795 | } else { |
| 796 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_SIZE) |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 797 | length_mask = 3; |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 798 | if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) |
| 799 | offset_mask = 3; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 800 | } |
| 801 | |
Russell King | df95392 | 2016-01-26 13:41:14 +0000 | [diff] [blame] | 802 | if (unlikely(length_mask | offset_mask)) { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 803 | for_each_sg(data->sg, sg, data->sg_len, i) { |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 804 | if (sg->length & length_mask) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 805 | DBG("Reverting to PIO because of transfer size (%d)\n", |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 806 | sg->length); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 807 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 808 | break; |
| 809 | } |
Russell King | a0eaf0f | 2016-01-26 13:41:09 +0000 | [diff] [blame] | 810 | if (sg->offset & offset_mask) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 811 | DBG("Reverting to PIO because of bad alignment\n"); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 812 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 813 | break; |
| 814 | } |
| 815 | } |
| 816 | } |
| 817 | } |
| 818 | |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 819 | if (host->flags & SDHCI_REQ_USE_DMA) { |
Russell King | c0999b7 | 2016-01-26 13:40:27 +0000 | [diff] [blame] | 820 | int sg_cnt = sdhci_pre_dma_transfer(host, data, COOKIE_MAPPED); |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 821 | |
Russell King | 60c6476 | 2016-01-26 13:40:22 +0000 | [diff] [blame] | 822 | if (sg_cnt <= 0) { |
| 823 | /* |
| 824 | * This only happens when someone fed |
| 825 | * us an invalid request. |
| 826 | */ |
| 827 | WARN_ON(1); |
| 828 | host->flags &= ~SDHCI_REQ_USE_DMA; |
| 829 | } else if (host->flags & SDHCI_USE_ADMA) { |
| 830 | sdhci_adma_table_pre(host, data, sg_cnt); |
| 831 | |
| 832 | sdhci_writel(host, host->adma_addr, SDHCI_ADMA_ADDRESS); |
| 833 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 834 | sdhci_writel(host, |
| 835 | (u64)host->adma_addr >> 32, |
| 836 | SDHCI_ADMA_ADDRESS_HI); |
| 837 | } else { |
| 838 | WARN_ON(sg_cnt != 1); |
| 839 | sdhci_writel(host, sg_dma_address(data->sg), |
| 840 | SDHCI_DMA_ADDRESS); |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 841 | } |
| 842 | } |
| 843 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 844 | /* |
| 845 | * Always adjust the DMA selection as some controllers |
| 846 | * (e.g. JMicron) can't do PIO properly when the selection |
| 847 | * is ADMA. |
| 848 | */ |
| 849 | if (host->version >= SDHCI_SPEC_200) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 850 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 851 | ctrl &= ~SDHCI_CTRL_DMA_MASK; |
| 852 | if ((host->flags & SDHCI_REQ_USE_DMA) && |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 853 | (host->flags & SDHCI_USE_ADMA)) { |
| 854 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 855 | ctrl |= SDHCI_CTRL_ADMA64; |
| 856 | else |
| 857 | ctrl |= SDHCI_CTRL_ADMA32; |
| 858 | } else { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 859 | ctrl |= SDHCI_CTRL_SDMA; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 860 | } |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 861 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 862 | } |
| 863 | |
Pierre Ossman | 8f1934c | 2008-06-30 21:15:49 +0200 | [diff] [blame] | 864 | if (!(host->flags & SDHCI_REQ_USE_DMA)) { |
Sebastian Andrzej Siewior | da60a91 | 2009-06-18 09:33:32 +0200 | [diff] [blame] | 865 | int flags; |
| 866 | |
| 867 | flags = SG_MITER_ATOMIC; |
| 868 | if (host->data->flags & MMC_DATA_READ) |
| 869 | flags |= SG_MITER_TO_SG; |
| 870 | else |
| 871 | flags |= SG_MITER_FROM_SG; |
| 872 | sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 873 | host->blocks = data->blocks; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 874 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 875 | |
Anton Vorontsov | 6aa943a | 2009-03-17 00:13:50 +0300 | [diff] [blame] | 876 | sdhci_set_transfer_irqs(host); |
| 877 | |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 878 | /* Set the DMA boundary value and block size */ |
| 879 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG, |
| 880 | data->blksz), SDHCI_BLOCK_SIZE); |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 881 | sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT); |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 882 | } |
| 883 | |
Adrian Hunter | 0293d50 | 2016-06-29 16:24:35 +0300 | [diff] [blame^] | 884 | static inline bool sdhci_auto_cmd12(struct sdhci_host *host, |
| 885 | struct mmc_request *mrq) |
| 886 | { |
| 887 | return !mrq->sbc && (host->flags & SDHCI_AUTO_CMD12); |
| 888 | } |
| 889 | |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 890 | static void sdhci_set_transfer_mode(struct sdhci_host *host, |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 891 | struct mmc_command *cmd) |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 892 | { |
Vincent Yang | d3fc5d7 | 2015-01-20 16:05:17 +0800 | [diff] [blame] | 893 | u16 mode = 0; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 894 | struct mmc_data *data = cmd->data; |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 895 | |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 896 | if (data == NULL) { |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 897 | if (host->quirks2 & |
| 898 | SDHCI_QUIRK2_CLEAR_TRANSFERMODE_REG_BEFORE_CMD) { |
| 899 | sdhci_writew(host, 0x0, SDHCI_TRANSFER_MODE); |
| 900 | } else { |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 901 | /* clear Auto CMD settings for no data CMDs */ |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 902 | mode = sdhci_readw(host, SDHCI_TRANSFER_MODE); |
| 903 | sdhci_writew(host, mode & ~(SDHCI_TRNS_AUTO_CMD12 | |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 904 | SDHCI_TRNS_AUTO_CMD23), SDHCI_TRANSFER_MODE); |
Vincent Wan | 9b8ffea | 2014-11-05 14:09:00 +0800 | [diff] [blame] | 905 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 906 | return; |
Dong Aisheng | 2b558c1 | 2013-10-30 22:09:48 +0800 | [diff] [blame] | 907 | } |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 908 | |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 909 | WARN_ON(!host->data); |
| 910 | |
Vincent Yang | d3fc5d7 | 2015-01-20 16:05:17 +0800 | [diff] [blame] | 911 | if (!(host->quirks2 & SDHCI_QUIRK2_SUPPORT_SINGLE)) |
| 912 | mode = SDHCI_TRNS_BLK_CNT_EN; |
| 913 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 914 | if (mmc_op_multi(cmd->opcode) || data->blocks > 1) { |
Vincent Yang | d3fc5d7 | 2015-01-20 16:05:17 +0800 | [diff] [blame] | 915 | mode = SDHCI_TRNS_BLK_CNT_EN | SDHCI_TRNS_MULTI; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 916 | /* |
| 917 | * If we are sending CMD23, CMD12 never gets sent |
| 918 | * on successful completion (so no Auto-CMD12). |
| 919 | */ |
Adrian Hunter | 0293d50 | 2016-06-29 16:24:35 +0300 | [diff] [blame^] | 920 | if (sdhci_auto_cmd12(host, cmd->mrq) && |
Corneliu Doban | 85cc1c3 | 2015-02-09 16:06:29 -0800 | [diff] [blame] | 921 | (cmd->opcode != SD_IO_RW_EXTENDED)) |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 922 | mode |= SDHCI_TRNS_AUTO_CMD12; |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 923 | else if (cmd->mrq->sbc && (host->flags & SDHCI_AUTO_CMD23)) { |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 924 | mode |= SDHCI_TRNS_AUTO_CMD23; |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 925 | sdhci_writel(host, cmd->mrq->sbc->arg, SDHCI_ARGUMENT2); |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 926 | } |
Jerry Huang | c4512f7 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 927 | } |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 928 | |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 929 | if (data->flags & MMC_DATA_READ) |
| 930 | mode |= SDHCI_TRNS_READ; |
Pierre Ossman | c9fddbc | 2007-12-02 19:52:11 +0100 | [diff] [blame] | 931 | if (host->flags & SDHCI_REQ_USE_DMA) |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 932 | mode |= SDHCI_TRNS_DMA; |
| 933 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 934 | sdhci_writew(host, mode, SDHCI_TRANSFER_MODE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 935 | } |
| 936 | |
Adrian Hunter | 0cc563c | 2016-06-29 16:24:28 +0300 | [diff] [blame] | 937 | static bool sdhci_needs_reset(struct sdhci_host *host, struct mmc_request *mrq) |
| 938 | { |
| 939 | return (!(host->flags & SDHCI_DEVICE_DEAD) && |
| 940 | ((mrq->cmd && mrq->cmd->error) || |
| 941 | (mrq->sbc && mrq->sbc->error) || |
| 942 | (mrq->data && ((mrq->data->error && !mrq->data->stop) || |
| 943 | (mrq->data->stop && mrq->data->stop->error))) || |
| 944 | (host->quirks & SDHCI_QUIRK_RESET_AFTER_REQUEST))); |
| 945 | } |
| 946 | |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 947 | static void __sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) |
| 948 | { |
| 949 | int i; |
| 950 | |
| 951 | for (i = 0; i < SDHCI_MAX_MRQS; i++) { |
| 952 | if (host->mrqs_done[i] == mrq) { |
| 953 | WARN_ON(1); |
| 954 | return; |
| 955 | } |
| 956 | } |
| 957 | |
| 958 | for (i = 0; i < SDHCI_MAX_MRQS; i++) { |
| 959 | if (!host->mrqs_done[i]) { |
| 960 | host->mrqs_done[i] = mrq; |
| 961 | break; |
| 962 | } |
| 963 | } |
| 964 | |
| 965 | WARN_ON(i >= SDHCI_MAX_MRQS); |
| 966 | |
| 967 | tasklet_schedule(&host->finish_tasklet); |
| 968 | } |
| 969 | |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 970 | static void sdhci_finish_mrq(struct sdhci_host *host, struct mmc_request *mrq) |
| 971 | { |
Adrian Hunter | 5a8a3fe | 2016-06-29 16:24:30 +0300 | [diff] [blame] | 972 | if (host->cmd && host->cmd->mrq == mrq) |
| 973 | host->cmd = NULL; |
| 974 | |
| 975 | if (host->data_cmd && host->data_cmd->mrq == mrq) |
| 976 | host->data_cmd = NULL; |
| 977 | |
| 978 | if (host->data && host->data->mrq == mrq) |
| 979 | host->data = NULL; |
| 980 | |
Adrian Hunter | ed1563d | 2016-06-29 16:24:29 +0300 | [diff] [blame] | 981 | if (sdhci_needs_reset(host, mrq)) |
| 982 | host->pending_reset = true; |
| 983 | |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 984 | __sdhci_finish_mrq(host, mrq); |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 985 | } |
| 986 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 987 | static void sdhci_finish_data(struct sdhci_host *host) |
| 988 | { |
| 989 | struct mmc_data *data; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 990 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 991 | data = host->data; |
| 992 | host->data = NULL; |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 993 | host->data_cmd = NULL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 994 | |
Russell King | add8913 | 2016-01-26 13:40:42 +0000 | [diff] [blame] | 995 | if ((host->flags & (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) == |
| 996 | (SDHCI_REQ_USE_DMA | SDHCI_USE_ADMA)) |
| 997 | sdhci_adma_table_post(host, data); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 998 | |
| 999 | /* |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 1000 | * The specification states that the block count register must |
| 1001 | * be updated, but it does not specify at what point in the |
| 1002 | * data flow. That makes the register entirely useless to read |
| 1003 | * back so we have to assume that nothing made it to the card |
| 1004 | * in the event of an error. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1005 | */ |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 1006 | if (data->error) |
| 1007 | data->bytes_xfered = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1008 | else |
Pierre Ossman | c9b74c5 | 2008-04-18 20:41:49 +0200 | [diff] [blame] | 1009 | data->bytes_xfered = data->blksz * data->blocks; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1010 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1011 | /* |
| 1012 | * Need to send CMD12 if - |
| 1013 | * a) open-ended multiblock transfer (no CMD23) |
| 1014 | * b) error in multiblock transfer |
| 1015 | */ |
| 1016 | if (data->stop && |
| 1017 | (data->error || |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 1018 | !data->mrq->sbc)) { |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1019 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1020 | /* |
| 1021 | * The controller needs a reset of internal state machines |
| 1022 | * upon error conditions. |
| 1023 | */ |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1024 | if (data->error) { |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 1025 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 1026 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1027 | } |
| 1028 | |
| 1029 | sdhci_send_command(host, data->stop); |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1030 | } else { |
| 1031 | sdhci_finish_mrq(host, data->mrq); |
| 1032 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1033 | } |
| 1034 | |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 1035 | static void sdhci_mod_timer(struct sdhci_host *host, struct mmc_request *mrq, |
| 1036 | unsigned long timeout) |
| 1037 | { |
| 1038 | if (sdhci_data_line_cmd(mrq->cmd)) |
| 1039 | mod_timer(&host->data_timer, timeout); |
| 1040 | else |
| 1041 | mod_timer(&host->timer, timeout); |
| 1042 | } |
| 1043 | |
| 1044 | static void sdhci_del_timer(struct sdhci_host *host, struct mmc_request *mrq) |
| 1045 | { |
| 1046 | if (sdhci_data_line_cmd(mrq->cmd)) |
| 1047 | del_timer(&host->data_timer); |
| 1048 | else |
| 1049 | del_timer(&host->timer); |
| 1050 | } |
| 1051 | |
Dong Aisheng | c0e55129 | 2013-09-13 19:11:31 +0800 | [diff] [blame] | 1052 | void sdhci_send_command(struct sdhci_host *host, struct mmc_command *cmd) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1053 | { |
| 1054 | int flags; |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 1055 | u32 mask; |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1056 | unsigned long timeout; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1057 | |
| 1058 | WARN_ON(host->cmd); |
| 1059 | |
Russell King | 9677620 | 2016-01-26 13:39:34 +0000 | [diff] [blame] | 1060 | /* Initially, a command has no error */ |
| 1061 | cmd->error = 0; |
| 1062 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1063 | /* Wait max 10 ms */ |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1064 | timeout = 10; |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 1065 | |
| 1066 | mask = SDHCI_CMD_INHIBIT; |
Adrian Hunter | 56a590d | 2016-06-29 16:24:32 +0300 | [diff] [blame] | 1067 | if (sdhci_data_line_cmd(cmd)) |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 1068 | mask |= SDHCI_DATA_INHIBIT; |
| 1069 | |
| 1070 | /* We shouldn't wait for data inihibit for stop commands, even |
| 1071 | though they might use busy signaling */ |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 1072 | if (cmd->mrq->data && (cmd == cmd->mrq->data->stop)) |
Pierre Ossman | fd2208d | 2006-06-30 02:22:28 -0700 | [diff] [blame] | 1073 | mask &= ~SDHCI_DATA_INHIBIT; |
| 1074 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1075 | while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) { |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1076 | if (timeout == 0) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1077 | pr_err("%s: Controller never released inhibit bit(s).\n", |
| 1078 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1079 | sdhci_dumpregs(host); |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1080 | cmd->error = -EIO; |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1081 | sdhci_finish_mrq(host, cmd->mrq); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1082 | return; |
| 1083 | } |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1084 | timeout--; |
| 1085 | mdelay(1); |
| 1086 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1087 | |
Adrian Hunter | 3e1a689 | 2013-11-14 10:16:20 +0200 | [diff] [blame] | 1088 | timeout = jiffies; |
Ulf Hansson | 1d4d774 | 2014-01-08 15:06:08 +0100 | [diff] [blame] | 1089 | if (!cmd->data && cmd->busy_timeout > 9000) |
| 1090 | timeout += DIV_ROUND_UP(cmd->busy_timeout, 1000) * HZ + HZ; |
Adrian Hunter | 3e1a689 | 2013-11-14 10:16:20 +0200 | [diff] [blame] | 1091 | else |
| 1092 | timeout += 10 * HZ; |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 1093 | sdhci_mod_timer(host, cmd->mrq, timeout); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1094 | |
| 1095 | host->cmd = cmd; |
Adrian Hunter | 56a590d | 2016-06-29 16:24:32 +0300 | [diff] [blame] | 1096 | if (sdhci_data_line_cmd(cmd)) { |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 1097 | WARN_ON(host->data_cmd); |
| 1098 | host->data_cmd = cmd; |
| 1099 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1100 | |
Andrei Warkentin | a3c7778 | 2011-04-11 16:13:42 -0500 | [diff] [blame] | 1101 | sdhci_prepare_data(host, cmd); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1102 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1103 | sdhci_writel(host, cmd->arg, SDHCI_ARGUMENT); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1104 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1105 | sdhci_set_transfer_mode(host, cmd); |
Pierre Ossman | c7fa996 | 2006-06-30 02:22:25 -0700 | [diff] [blame] | 1106 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1107 | if ((cmd->flags & MMC_RSP_136) && (cmd->flags & MMC_RSP_BUSY)) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 1108 | pr_err("%s: Unsupported response type!\n", |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1109 | mmc_hostname(host->mmc)); |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 1110 | cmd->error = -EINVAL; |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1111 | sdhci_finish_mrq(host, cmd->mrq); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1112 | return; |
| 1113 | } |
| 1114 | |
| 1115 | if (!(cmd->flags & MMC_RSP_PRESENT)) |
| 1116 | flags = SDHCI_CMD_RESP_NONE; |
| 1117 | else if (cmd->flags & MMC_RSP_136) |
| 1118 | flags = SDHCI_CMD_RESP_LONG; |
| 1119 | else if (cmd->flags & MMC_RSP_BUSY) |
| 1120 | flags = SDHCI_CMD_RESP_SHORT_BUSY; |
| 1121 | else |
| 1122 | flags = SDHCI_CMD_RESP_SHORT; |
| 1123 | |
| 1124 | if (cmd->flags & MMC_RSP_CRC) |
| 1125 | flags |= SDHCI_CMD_CRC; |
| 1126 | if (cmd->flags & MMC_RSP_OPCODE) |
| 1127 | flags |= SDHCI_CMD_INDEX; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1128 | |
| 1129 | /* CMD19 is special in that the Data Present Select should be set */ |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1130 | if (cmd->data || cmd->opcode == MMC_SEND_TUNING_BLOCK || |
| 1131 | cmd->opcode == MMC_SEND_TUNING_BLOCK_HS200) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1132 | flags |= SDHCI_CMD_DATA; |
| 1133 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1134 | sdhci_writew(host, SDHCI_MAKE_CMD(cmd->opcode, flags), SDHCI_COMMAND); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1135 | } |
Dong Aisheng | c0e55129 | 2013-09-13 19:11:31 +0800 | [diff] [blame] | 1136 | EXPORT_SYMBOL_GPL(sdhci_send_command); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1137 | |
| 1138 | static void sdhci_finish_command(struct sdhci_host *host) |
| 1139 | { |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1140 | struct mmc_command *cmd = host->cmd; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1141 | int i; |
| 1142 | |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1143 | host->cmd = NULL; |
| 1144 | |
| 1145 | if (cmd->flags & MMC_RSP_PRESENT) { |
| 1146 | if (cmd->flags & MMC_RSP_136) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1147 | /* CRC is stripped so we need to do some shifting. */ |
| 1148 | for (i = 0;i < 4;i++) { |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1149 | cmd->resp[i] = sdhci_readl(host, |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1150 | SDHCI_RESPONSE + (3-i)*4) << 8; |
| 1151 | if (i != 3) |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1152 | cmd->resp[i] |= |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1153 | sdhci_readb(host, |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1154 | SDHCI_RESPONSE + (3-i)*4-1); |
| 1155 | } |
| 1156 | } else { |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1157 | cmd->resp[0] = sdhci_readl(host, SDHCI_RESPONSE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1158 | } |
| 1159 | } |
| 1160 | |
Adrian Hunter | 6bde868 | 2016-06-29 16:24:20 +0300 | [diff] [blame] | 1161 | /* |
| 1162 | * The host can send and interrupt when the busy state has |
| 1163 | * ended, allowing us to wait without wasting CPU cycles. |
| 1164 | * The busy signal uses DAT0 so this is similar to waiting |
| 1165 | * for data to complete. |
| 1166 | * |
| 1167 | * Note: The 1.0 specification is a bit ambiguous about this |
| 1168 | * feature so there might be some problems with older |
| 1169 | * controllers. |
| 1170 | */ |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1171 | if (cmd->flags & MMC_RSP_BUSY) { |
| 1172 | if (cmd->data) { |
Adrian Hunter | 6bde868 | 2016-06-29 16:24:20 +0300 | [diff] [blame] | 1173 | DBG("Cannot wait for busy signal when also doing a data transfer"); |
| 1174 | } else if (!(host->quirks & SDHCI_QUIRK_NO_BUSY_IRQ) && |
Adrian Hunter | ea96802 | 2016-06-29 16:24:24 +0300 | [diff] [blame] | 1175 | cmd == host->data_cmd) { |
| 1176 | /* Command complete before busy is ended */ |
Adrian Hunter | 6bde868 | 2016-06-29 16:24:20 +0300 | [diff] [blame] | 1177 | return; |
| 1178 | } |
| 1179 | } |
| 1180 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1181 | /* Finished CMD23, now send actual command. */ |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 1182 | if (cmd == cmd->mrq->sbc) { |
| 1183 | sdhci_send_command(host, cmd->mrq->cmd); |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1184 | } else { |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 1185 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1186 | /* Processed actual command. */ |
| 1187 | if (host->data && host->data_early) |
| 1188 | sdhci_finish_data(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1189 | |
Adrian Hunter | e0a5640 | 2016-06-29 16:24:22 +0300 | [diff] [blame] | 1190 | if (!cmd->data) |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1191 | sdhci_finish_mrq(host, cmd->mrq); |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1192 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1193 | } |
| 1194 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1195 | static u16 sdhci_get_preset_value(struct sdhci_host *host) |
| 1196 | { |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1197 | u16 preset = 0; |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1198 | |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1199 | switch (host->timing) { |
| 1200 | case MMC_TIMING_UHS_SDR12: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1201 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
| 1202 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1203 | case MMC_TIMING_UHS_SDR25: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1204 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR25); |
| 1205 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1206 | case MMC_TIMING_UHS_SDR50: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1207 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR50); |
| 1208 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1209 | case MMC_TIMING_UHS_SDR104: |
| 1210 | case MMC_TIMING_MMC_HS200: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1211 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR104); |
| 1212 | break; |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1213 | case MMC_TIMING_UHS_DDR50: |
Jisheng Zhang | 0dafa60 | 2015-08-18 16:21:39 +0800 | [diff] [blame] | 1214 | case MMC_TIMING_MMC_DDR52: |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1215 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_DDR50); |
| 1216 | break; |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1217 | case MMC_TIMING_MMC_HS400: |
| 1218 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_HS400); |
| 1219 | break; |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1220 | default: |
| 1221 | pr_warn("%s: Invalid UHS-I mode selected\n", |
| 1222 | mmc_hostname(host->mmc)); |
| 1223 | preset = sdhci_readw(host, SDHCI_PRESET_FOR_SDR12); |
| 1224 | break; |
| 1225 | } |
| 1226 | return preset; |
| 1227 | } |
| 1228 | |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1229 | u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock, |
| 1230 | unsigned int *actual_clock) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1231 | { |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1232 | int div = 0; /* Initialized for compiler warning */ |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1233 | int real_div = div, clk_mul = 1; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1234 | u16 clk = 0; |
ludovic.desroches@atmel.com | 5497159 | 2015-07-29 16:22:46 +0200 | [diff] [blame] | 1235 | bool switch_base_clk = false; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1236 | |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1237 | if (host->version >= SDHCI_SPEC_300) { |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 1238 | if (host->preset_enabled) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1239 | u16 pre_val; |
| 1240 | |
| 1241 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1242 | pre_val = sdhci_get_preset_value(host); |
| 1243 | div = (pre_val & SDHCI_PRESET_SDCLK_FREQ_MASK) |
| 1244 | >> SDHCI_PRESET_SDCLK_FREQ_SHIFT; |
| 1245 | if (host->clk_mul && |
| 1246 | (pre_val & SDHCI_PRESET_CLKGEN_SEL_MASK)) { |
| 1247 | clk = SDHCI_PROG_CLOCK_MODE; |
| 1248 | real_div = div + 1; |
| 1249 | clk_mul = host->clk_mul; |
| 1250 | } else { |
| 1251 | real_div = max_t(int, 1, div << 1); |
| 1252 | } |
| 1253 | goto clock_set; |
| 1254 | } |
| 1255 | |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1256 | /* |
| 1257 | * Check if the Host Controller supports Programmable Clock |
| 1258 | * Mode. |
| 1259 | */ |
| 1260 | if (host->clk_mul) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1261 | for (div = 1; div <= 1024; div++) { |
| 1262 | if ((host->max_clk * host->clk_mul / div) |
| 1263 | <= clock) |
| 1264 | break; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1265 | } |
ludovic.desroches@atmel.com | 5497159 | 2015-07-29 16:22:46 +0200 | [diff] [blame] | 1266 | if ((host->max_clk * host->clk_mul / div) <= clock) { |
| 1267 | /* |
| 1268 | * Set Programmable Clock Mode in the Clock |
| 1269 | * Control register. |
| 1270 | */ |
| 1271 | clk = SDHCI_PROG_CLOCK_MODE; |
| 1272 | real_div = div; |
| 1273 | clk_mul = host->clk_mul; |
| 1274 | div--; |
| 1275 | } else { |
| 1276 | /* |
| 1277 | * Divisor can be too small to reach clock |
| 1278 | * speed requirement. Then use the base clock. |
| 1279 | */ |
| 1280 | switch_base_clk = true; |
| 1281 | } |
| 1282 | } |
| 1283 | |
| 1284 | if (!host->clk_mul || switch_base_clk) { |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1285 | /* Version 3.00 divisors must be a multiple of 2. */ |
| 1286 | if (host->max_clk <= clock) |
| 1287 | div = 1; |
| 1288 | else { |
| 1289 | for (div = 2; div < SDHCI_MAX_DIV_SPEC_300; |
| 1290 | div += 2) { |
| 1291 | if ((host->max_clk / div) <= clock) |
| 1292 | break; |
| 1293 | } |
| 1294 | } |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1295 | real_div = div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1296 | div >>= 1; |
Suneel Garapati | d1955c3 | 2015-06-09 13:01:50 +0530 | [diff] [blame] | 1297 | if ((host->quirks2 & SDHCI_QUIRK2_CLOCK_DIV_ZERO_BROKEN) |
| 1298 | && !div && host->max_clk <= 25000000) |
| 1299 | div = 1; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1300 | } |
| 1301 | } else { |
| 1302 | /* Version 2.00 divisors must be a power of 2. */ |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 1303 | for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) { |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1304 | if ((host->max_clk / div) <= clock) |
| 1305 | break; |
| 1306 | } |
Giuseppe CAVALLARO | df16219 | 2011-11-04 13:53:19 +0100 | [diff] [blame] | 1307 | real_div = div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1308 | div >>= 1; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1309 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1310 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1311 | clock_set: |
Aisheng Dong | 03d6f5f | 2014-08-27 15:26:32 +0800 | [diff] [blame] | 1312 | if (real_div) |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1313 | *actual_clock = (host->max_clk * clk_mul) / real_div; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 1314 | clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT; |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 1315 | clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN) |
| 1316 | << SDHCI_DIVIDER_HI_SHIFT; |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1317 | |
| 1318 | return clk; |
| 1319 | } |
| 1320 | EXPORT_SYMBOL_GPL(sdhci_calc_clk); |
| 1321 | |
| 1322 | void sdhci_set_clock(struct sdhci_host *host, unsigned int clock) |
| 1323 | { |
| 1324 | u16 clk; |
| 1325 | unsigned long timeout; |
| 1326 | |
| 1327 | host->mmc->actual_clock = 0; |
| 1328 | |
| 1329 | sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL); |
Ludovic Desroches | fb9ee04 | 2016-04-07 11:13:08 +0200 | [diff] [blame] | 1330 | |
| 1331 | if (clock == 0) |
| 1332 | return; |
| 1333 | |
| 1334 | clk = sdhci_calc_clk(host, clock, &host->mmc->actual_clock); |
| 1335 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1336 | clk |= SDHCI_CLOCK_INT_EN; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1337 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1338 | |
Chris Ball | 27f6cb1 | 2009-09-22 16:45:31 -0700 | [diff] [blame] | 1339 | /* Wait max 20 ms */ |
| 1340 | timeout = 20; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1341 | while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL)) |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1342 | & SDHCI_CLOCK_INT_STABLE)) { |
| 1343 | if (timeout == 0) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1344 | pr_err("%s: Internal clock never stabilised.\n", |
| 1345 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1346 | sdhci_dumpregs(host); |
| 1347 | return; |
| 1348 | } |
Pierre Ossman | 7cb2c76 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1349 | timeout--; |
| 1350 | mdelay(1); |
| 1351 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1352 | |
| 1353 | clk |= SDHCI_CLOCK_CARD_EN; |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1354 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1355 | } |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1356 | EXPORT_SYMBOL_GPL(sdhci_set_clock); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1357 | |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 1358 | static void sdhci_set_power_reg(struct sdhci_host *host, unsigned char mode, |
| 1359 | unsigned short vdd) |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1360 | { |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1361 | struct mmc_host *mmc = host->mmc; |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 1362 | |
| 1363 | spin_unlock_irq(&host->lock); |
| 1364 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); |
| 1365 | spin_lock_irq(&host->lock); |
| 1366 | |
| 1367 | if (mode != MMC_POWER_OFF) |
| 1368 | sdhci_writeb(host, SDHCI_POWER_ON, SDHCI_POWER_CONTROL); |
| 1369 | else |
| 1370 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
| 1371 | } |
| 1372 | |
| 1373 | void sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
| 1374 | unsigned short vdd) |
| 1375 | { |
Giuseppe Cavallaro | 8364248 | 2010-09-28 10:41:28 +0200 | [diff] [blame] | 1376 | u8 pwr = 0; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1377 | |
Russell King | 24fbb3c | 2014-04-25 13:00:06 +0100 | [diff] [blame] | 1378 | if (mode != MMC_POWER_OFF) { |
| 1379 | switch (1 << vdd) { |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1380 | case MMC_VDD_165_195: |
| 1381 | pwr = SDHCI_POWER_180; |
| 1382 | break; |
| 1383 | case MMC_VDD_29_30: |
| 1384 | case MMC_VDD_30_31: |
| 1385 | pwr = SDHCI_POWER_300; |
| 1386 | break; |
| 1387 | case MMC_VDD_32_33: |
| 1388 | case MMC_VDD_33_34: |
| 1389 | pwr = SDHCI_POWER_330; |
| 1390 | break; |
| 1391 | default: |
Adrian Hunter | 9d5de93 | 2015-11-26 14:00:46 +0200 | [diff] [blame] | 1392 | WARN(1, "%s: Invalid vdd %#x\n", |
| 1393 | mmc_hostname(host->mmc), vdd); |
| 1394 | break; |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1395 | } |
| 1396 | } |
| 1397 | |
| 1398 | if (host->pwr == pwr) |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1399 | return; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1400 | |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1401 | host->pwr = pwr; |
| 1402 | |
| 1403 | if (pwr == 0) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1404 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
Adrian Hunter | f0710a5 | 2013-05-06 12:17:32 +0300 | [diff] [blame] | 1405 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
| 1406 | sdhci_runtime_pm_bus_off(host); |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1407 | } else { |
| 1408 | /* |
| 1409 | * Spec says that we should clear the power reg before setting |
| 1410 | * a new value. Some controllers don't seem to like this though. |
| 1411 | */ |
| 1412 | if (!(host->quirks & SDHCI_QUIRK_SINGLE_POWER_WRITE)) |
| 1413 | sdhci_writeb(host, 0, SDHCI_POWER_CONTROL); |
Darren Salt | 9e9dc5f | 2007-01-27 15:32:31 +0100 | [diff] [blame] | 1414 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1415 | /* |
| 1416 | * At least the Marvell CaFe chip gets confused if we set the |
| 1417 | * voltage and set turn on power at the same time, so set the |
| 1418 | * voltage first. |
| 1419 | */ |
| 1420 | if (host->quirks & SDHCI_QUIRK_NO_SIMULT_VDD_AND_POWER) |
| 1421 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1422 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1423 | pwr |= SDHCI_POWER_ON; |
| 1424 | |
Pierre Ossman | ae62890 | 2009-05-03 20:45:03 +0200 | [diff] [blame] | 1425 | sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL); |
| 1426 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1427 | if (host->quirks2 & SDHCI_QUIRK2_CARD_ON_NEEDS_BUS_ON) |
| 1428 | sdhci_runtime_pm_bus_on(host); |
Andres Salomon | e08c169 | 2008-07-04 10:00:03 -0700 | [diff] [blame] | 1429 | |
Russell King | e921a8b | 2014-04-25 13:00:01 +0100 | [diff] [blame] | 1430 | /* |
| 1431 | * Some controllers need an extra 10ms delay of 10ms before |
| 1432 | * they can apply clock after applying power |
| 1433 | */ |
| 1434 | if (host->quirks & SDHCI_QUIRK_DELAY_AFTER_POWER) |
| 1435 | mdelay(10); |
| 1436 | } |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 1437 | } |
| 1438 | EXPORT_SYMBOL_GPL(sdhci_set_power); |
Jisheng Zhang | 918f4cb | 2015-12-11 21:36:29 +0800 | [diff] [blame] | 1439 | |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 1440 | static void __sdhci_set_power(struct sdhci_host *host, unsigned char mode, |
| 1441 | unsigned short vdd) |
| 1442 | { |
| 1443 | struct mmc_host *mmc = host->mmc; |
| 1444 | |
| 1445 | if (host->ops->set_power) |
| 1446 | host->ops->set_power(host, mode, vdd); |
| 1447 | else if (!IS_ERR(mmc->supply.vmmc)) |
| 1448 | sdhci_set_power_reg(host, mode, vdd); |
| 1449 | else |
| 1450 | sdhci_set_power(host, mode, vdd); |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 1451 | } |
| 1452 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1453 | /*****************************************************************************\ |
| 1454 | * * |
| 1455 | * MMC callbacks * |
| 1456 | * * |
| 1457 | \*****************************************************************************/ |
| 1458 | |
| 1459 | static void sdhci_request(struct mmc_host *mmc, struct mmc_request *mrq) |
| 1460 | { |
| 1461 | struct sdhci_host *host; |
Shawn Guo | 505a868 | 2012-12-11 15:23:42 +0800 | [diff] [blame] | 1462 | int present; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1463 | unsigned long flags; |
| 1464 | |
| 1465 | host = mmc_priv(mmc); |
| 1466 | |
Scott Branden | 04e079c | 2015-03-10 11:35:10 -0700 | [diff] [blame] | 1467 | /* Firstly check card presence */ |
Adrian Hunter | 8d28b7a | 2016-02-09 16:12:36 +0200 | [diff] [blame] | 1468 | present = mmc->ops->get_cd(mmc); |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 1469 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1470 | spin_lock_irqsave(&host->lock, flags); |
| 1471 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 1472 | sdhci_led_activate(host); |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1473 | |
| 1474 | /* |
| 1475 | * Ensure we don't send the STOP for non-SET_BLOCK_COUNTED |
| 1476 | * requests if Auto-CMD12 is enabled. |
| 1477 | */ |
Adrian Hunter | 0293d50 | 2016-06-29 16:24:35 +0300 | [diff] [blame^] | 1478 | if (sdhci_auto_cmd12(host, mrq)) { |
Jerry Huang | c4512f7 | 2010-08-10 18:01:59 -0700 | [diff] [blame] | 1479 | if (mrq->stop) { |
| 1480 | mrq->data->stop = NULL; |
| 1481 | mrq->stop = NULL; |
| 1482 | } |
| 1483 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1484 | |
Anton Vorontsov | 68d1fb7 | 2009-03-17 00:13:52 +0300 | [diff] [blame] | 1485 | if (!present || host->flags & SDHCI_DEVICE_DEAD) { |
Adrian Hunter | a4c73ab | 2016-06-29 16:24:25 +0300 | [diff] [blame] | 1486 | mrq->cmd->error = -ENOMEDIUM; |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 1487 | sdhci_finish_mrq(host, mrq); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 1488 | } else { |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 1489 | if (mrq->sbc && !(host->flags & SDHCI_AUTO_CMD23)) |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 1490 | sdhci_send_command(host, mrq->sbc); |
| 1491 | else |
| 1492 | sdhci_send_command(host, mrq->cmd); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 1493 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1494 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 1495 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1496 | spin_unlock_irqrestore(&host->lock, flags); |
| 1497 | } |
| 1498 | |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 1499 | void sdhci_set_bus_width(struct sdhci_host *host, int width) |
| 1500 | { |
| 1501 | u8 ctrl; |
| 1502 | |
| 1503 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
| 1504 | if (width == MMC_BUS_WIDTH_8) { |
| 1505 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
| 1506 | if (host->version >= SDHCI_SPEC_300) |
| 1507 | ctrl |= SDHCI_CTRL_8BITBUS; |
| 1508 | } else { |
| 1509 | if (host->version >= SDHCI_SPEC_300) |
| 1510 | ctrl &= ~SDHCI_CTRL_8BITBUS; |
| 1511 | if (width == MMC_BUS_WIDTH_4) |
| 1512 | ctrl |= SDHCI_CTRL_4BITBUS; |
| 1513 | else |
| 1514 | ctrl &= ~SDHCI_CTRL_4BITBUS; |
| 1515 | } |
| 1516 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 1517 | } |
| 1518 | EXPORT_SYMBOL_GPL(sdhci_set_bus_width); |
| 1519 | |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 1520 | void sdhci_set_uhs_signaling(struct sdhci_host *host, unsigned timing) |
| 1521 | { |
| 1522 | u16 ctrl_2; |
| 1523 | |
| 1524 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1525 | /* Select Bus Speed Mode for host */ |
| 1526 | ctrl_2 &= ~SDHCI_CTRL_UHS_MASK; |
| 1527 | if ((timing == MMC_TIMING_MMC_HS200) || |
| 1528 | (timing == MMC_TIMING_UHS_SDR104)) |
| 1529 | ctrl_2 |= SDHCI_CTRL_UHS_SDR104; |
| 1530 | else if (timing == MMC_TIMING_UHS_SDR12) |
| 1531 | ctrl_2 |= SDHCI_CTRL_UHS_SDR12; |
| 1532 | else if (timing == MMC_TIMING_UHS_SDR25) |
| 1533 | ctrl_2 |= SDHCI_CTRL_UHS_SDR25; |
| 1534 | else if (timing == MMC_TIMING_UHS_SDR50) |
| 1535 | ctrl_2 |= SDHCI_CTRL_UHS_SDR50; |
| 1536 | else if ((timing == MMC_TIMING_UHS_DDR50) || |
| 1537 | (timing == MMC_TIMING_MMC_DDR52)) |
| 1538 | ctrl_2 |= SDHCI_CTRL_UHS_DDR50; |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1539 | else if (timing == MMC_TIMING_MMC_HS400) |
| 1540 | ctrl_2 |= SDHCI_CTRL_HS400; /* Non-standard */ |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 1541 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
| 1542 | } |
| 1543 | EXPORT_SYMBOL_GPL(sdhci_set_uhs_signaling); |
| 1544 | |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1545 | static void sdhci_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1546 | { |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1547 | struct sdhci_host *host = mmc_priv(mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1548 | unsigned long flags; |
| 1549 | u8 ctrl; |
| 1550 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1551 | spin_lock_irqsave(&host->lock, flags); |
| 1552 | |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1553 | if (host->flags & SDHCI_DEVICE_DEAD) { |
| 1554 | spin_unlock_irqrestore(&host->lock, flags); |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1555 | if (!IS_ERR(mmc->supply.vmmc) && |
| 1556 | ios->power_mode == MMC_POWER_OFF) |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 1557 | mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); |
Adrian Hunter | ceb6143 | 2011-12-27 15:48:41 +0200 | [diff] [blame] | 1558 | return; |
| 1559 | } |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1560 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1561 | /* |
| 1562 | * Reset the chip on each power off. |
| 1563 | * Should clear out any weird states. |
| 1564 | */ |
| 1565 | if (ios->power_mode == MMC_POWER_OFF) { |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1566 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 1567 | sdhci_reinit(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1568 | } |
| 1569 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1570 | if (host->version >= SDHCI_SPEC_300 && |
Dong Aisheng | 372c463 | 2013-10-18 19:48:50 +0800 | [diff] [blame] | 1571 | (ios->power_mode == MMC_POWER_UP) && |
| 1572 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1573 | sdhci_enable_preset_value(host, false); |
| 1574 | |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 1575 | if (!ios->clock || ios->clock != host->clock) { |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1576 | host->ops->set_clock(host, ios->clock); |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 1577 | host->clock = ios->clock; |
Aisheng Dong | 03d6f5f | 2014-08-27 15:26:32 +0800 | [diff] [blame] | 1578 | |
| 1579 | if (host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK && |
| 1580 | host->clock) { |
| 1581 | host->timeout_clk = host->mmc->actual_clock ? |
| 1582 | host->mmc->actual_clock / 1000 : |
| 1583 | host->clock / 1000; |
| 1584 | host->mmc->max_busy_timeout = |
| 1585 | host->ops->get_max_timeout_count ? |
| 1586 | host->ops->get_max_timeout_count(host) : |
| 1587 | 1 << 27; |
| 1588 | host->mmc->max_busy_timeout /= host->timeout_clk; |
| 1589 | } |
Russell King | 373073e | 2014-04-25 12:58:45 +0100 | [diff] [blame] | 1590 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1591 | |
Adrian Hunter | 1dceb04 | 2016-03-29 12:45:43 +0300 | [diff] [blame] | 1592 | __sdhci_set_power(host, ios->power_mode, ios->vdd); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1593 | |
Philip Rakity | 643a81f | 2010-09-23 08:24:32 -0700 | [diff] [blame] | 1594 | if (host->ops->platform_send_init_74_clocks) |
| 1595 | host->ops->platform_send_init_74_clocks(host, ios->power_mode); |
| 1596 | |
Russell King | 2317f56 | 2014-04-25 12:57:07 +0100 | [diff] [blame] | 1597 | host->ops->set_bus_width(host, ios->bus_width); |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 1598 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 1599 | ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 1600 | |
Philip Rakity | 3ab9c8d | 2010-10-06 11:57:23 -0700 | [diff] [blame] | 1601 | if ((ios->timing == MMC_TIMING_SD_HS || |
| 1602 | ios->timing == MMC_TIMING_MMC_HS) |
| 1603 | && !(host->quirks & SDHCI_QUIRK_NO_HISPD_BIT)) |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 1604 | ctrl |= SDHCI_CTRL_HISPD; |
| 1605 | else |
| 1606 | ctrl &= ~SDHCI_CTRL_HISPD; |
| 1607 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1608 | if (host->version >= SDHCI_SPEC_300) { |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1609 | u16 clk, ctrl_2; |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1610 | |
| 1611 | /* In case of UHS-I modes, set High Speed Enable */ |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1612 | if ((ios->timing == MMC_TIMING_MMC_HS400) || |
| 1613 | (ios->timing == MMC_TIMING_MMC_HS200) || |
Seungwon Jeon | bb8175a | 2014-03-14 21:12:48 +0900 | [diff] [blame] | 1614 | (ios->timing == MMC_TIMING_MMC_DDR52) || |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1615 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1616 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
| 1617 | (ios->timing == MMC_TIMING_UHS_DDR50) || |
Alexander Elbs | dd8df17 | 2012-01-03 23:26:53 -0500 | [diff] [blame] | 1618 | (ios->timing == MMC_TIMING_UHS_SDR25)) |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1619 | ctrl |= SDHCI_CTRL_HISPD; |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1620 | |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 1621 | if (!host->preset_enabled) { |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1622 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1623 | /* |
| 1624 | * We only need to set Driver Strength if the |
| 1625 | * preset value enable is not set. |
| 1626 | */ |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 1627 | ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1628 | ctrl_2 &= ~SDHCI_CTRL_DRV_TYPE_MASK; |
| 1629 | if (ios->drv_type == MMC_SET_DRIVER_TYPE_A) |
| 1630 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_A; |
Petri Gynther | 43e943a | 2015-05-20 14:35:00 -0700 | [diff] [blame] | 1631 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_B) |
| 1632 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1633 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_C) |
| 1634 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_C; |
Petri Gynther | 43e943a | 2015-05-20 14:35:00 -0700 | [diff] [blame] | 1635 | else if (ios->drv_type == MMC_SET_DRIVER_TYPE_D) |
| 1636 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_D; |
| 1637 | else { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 1638 | pr_warn("%s: invalid driver type, default to driver type B\n", |
| 1639 | mmc_hostname(mmc)); |
Petri Gynther | 43e943a | 2015-05-20 14:35:00 -0700 | [diff] [blame] | 1640 | ctrl_2 |= SDHCI_CTRL_DRV_TYPE_B; |
| 1641 | } |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1642 | |
| 1643 | sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1644 | } else { |
| 1645 | /* |
| 1646 | * According to SDHC Spec v3.00, if the Preset Value |
| 1647 | * Enable in the Host Control 2 register is set, we |
| 1648 | * need to reset SD Clock Enable before changing High |
| 1649 | * Speed Enable to avoid generating clock gliches. |
| 1650 | */ |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1651 | |
| 1652 | /* Reset SD Clock Enable */ |
| 1653 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1654 | clk &= ~SDHCI_CLOCK_CARD_EN; |
| 1655 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 1656 | |
| 1657 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
| 1658 | |
| 1659 | /* Re-enable SD Clock */ |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1660 | host->ops->set_clock(host, host->clock); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1661 | } |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1662 | |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1663 | /* Reset SD Clock Enable */ |
| 1664 | clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); |
| 1665 | clk &= ~SDHCI_CLOCK_CARD_EN; |
| 1666 | sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); |
| 1667 | |
Russell King | 96d7b78 | 2014-04-25 12:59:26 +0100 | [diff] [blame] | 1668 | host->ops->set_uhs_signaling(host, ios->timing); |
Russell King | d975f12 | 2014-04-25 12:59:31 +0100 | [diff] [blame] | 1669 | host->timing = ios->timing; |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1670 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1671 | if (!(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN) && |
| 1672 | ((ios->timing == MMC_TIMING_UHS_SDR12) || |
| 1673 | (ios->timing == MMC_TIMING_UHS_SDR25) || |
| 1674 | (ios->timing == MMC_TIMING_UHS_SDR50) || |
| 1675 | (ios->timing == MMC_TIMING_UHS_SDR104) || |
Jisheng Zhang | 0dafa60 | 2015-08-18 16:21:39 +0800 | [diff] [blame] | 1676 | (ios->timing == MMC_TIMING_UHS_DDR50) || |
| 1677 | (ios->timing == MMC_TIMING_MMC_DDR52))) { |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 1678 | u16 preset; |
| 1679 | |
| 1680 | sdhci_enable_preset_value(host, true); |
| 1681 | preset = sdhci_get_preset_value(host); |
| 1682 | ios->drv_type = (preset & SDHCI_PRESET_DRV_MASK) |
| 1683 | >> SDHCI_PRESET_DRV_SHIFT; |
| 1684 | } |
| 1685 | |
Arindam Nath | 49c468f | 2011-05-05 12:19:01 +0530 | [diff] [blame] | 1686 | /* Re-enable SD Clock */ |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 1687 | host->ops->set_clock(host, host->clock); |
Arindam Nath | 758535c | 2011-05-05 12:19:00 +0530 | [diff] [blame] | 1688 | } else |
| 1689 | sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 1690 | |
Leandro Dorileo | b835226 | 2007-07-25 23:47:04 +0200 | [diff] [blame] | 1691 | /* |
| 1692 | * Some (ENE) controllers go apeshit on some ios operation, |
| 1693 | * signalling timeout and CRC errors even on CMD0. Resetting |
| 1694 | * it on each ios seems to solve the problem. |
| 1695 | */ |
Mohammad Jamal | c63705e | 2015-01-13 20:47:24 +0530 | [diff] [blame] | 1696 | if (host->quirks & SDHCI_QUIRK_RESET_CMD_DATA_ON_IOS) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 1697 | sdhci_do_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); |
Leandro Dorileo | b835226 | 2007-07-25 23:47:04 +0200 | [diff] [blame] | 1698 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 1699 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1700 | spin_unlock_irqrestore(&host->lock, flags); |
| 1701 | } |
| 1702 | |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1703 | static int sdhci_get_cd(struct mmc_host *mmc) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1704 | { |
| 1705 | struct sdhci_host *host = mmc_priv(mmc); |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1706 | int gpio_cd = mmc_gpio_get_cd(mmc); |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 1707 | |
| 1708 | if (host->flags & SDHCI_DEVICE_DEAD) |
| 1709 | return 0; |
| 1710 | |
Ivan T. Ivanov | 88af565 | 2015-07-06 15:16:19 +0300 | [diff] [blame] | 1711 | /* If nonremovable, assume that the card is always present. */ |
Jaehoon Chung | 860951c | 2016-06-21 10:13:26 +0900 | [diff] [blame] | 1712 | if (!mmc_card_is_removable(host->mmc)) |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 1713 | return 1; |
| 1714 | |
Ivan T. Ivanov | 88af565 | 2015-07-06 15:16:19 +0300 | [diff] [blame] | 1715 | /* |
| 1716 | * Try slot gpio detect, if defined it take precedence |
| 1717 | * over build in controller functionality |
| 1718 | */ |
Arnd Bergmann | 287980e | 2016-05-27 23:23:25 +0200 | [diff] [blame] | 1719 | if (gpio_cd >= 0) |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 1720 | return !!gpio_cd; |
| 1721 | |
Ivan T. Ivanov | 88af565 | 2015-07-06 15:16:19 +0300 | [diff] [blame] | 1722 | /* If polling, assume that the card is always present. */ |
| 1723 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) |
| 1724 | return 1; |
| 1725 | |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 1726 | /* Host native card detect */ |
| 1727 | return !!(sdhci_readl(host, SDHCI_PRESENT_STATE) & SDHCI_CARD_PRESENT); |
| 1728 | } |
| 1729 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1730 | static int sdhci_check_ro(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1731 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1732 | unsigned long flags; |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1733 | int is_readonly; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1734 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1735 | spin_lock_irqsave(&host->lock, flags); |
| 1736 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1737 | if (host->flags & SDHCI_DEVICE_DEAD) |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1738 | is_readonly = 0; |
| 1739 | else if (host->ops->get_ro) |
| 1740 | is_readonly = host->ops->get_ro(host); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 1741 | else |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1742 | is_readonly = !(sdhci_readl(host, SDHCI_PRESENT_STATE) |
| 1743 | & SDHCI_WRITE_PROTECT); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1744 | |
| 1745 | spin_unlock_irqrestore(&host->lock, flags); |
| 1746 | |
Wolfram Sang | 2dfb579 | 2010-10-15 12:21:01 +0200 | [diff] [blame] | 1747 | /* This quirk needs to be replaced by a callback-function later */ |
| 1748 | return host->quirks & SDHCI_QUIRK_INVERTED_WRITE_PROTECT ? |
| 1749 | !is_readonly : is_readonly; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 1750 | } |
| 1751 | |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1752 | #define SAMPLE_COUNT 5 |
| 1753 | |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1754 | static int sdhci_get_ro(struct mmc_host *mmc) |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1755 | { |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1756 | struct sdhci_host *host = mmc_priv(mmc); |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1757 | int i, ro_count; |
| 1758 | |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1759 | if (!(host->quirks & SDHCI_QUIRK_UNSTABLE_RO_DETECT)) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1760 | return sdhci_check_ro(host); |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1761 | |
| 1762 | ro_count = 0; |
| 1763 | for (i = 0; i < SAMPLE_COUNT; i++) { |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1764 | if (sdhci_check_ro(host)) { |
Takashi Iwai | 82b0e23 | 2011-04-21 20:26:38 +0200 | [diff] [blame] | 1765 | if (++ro_count > SAMPLE_COUNT / 2) |
| 1766 | return 1; |
| 1767 | } |
| 1768 | msleep(30); |
| 1769 | } |
| 1770 | return 0; |
| 1771 | } |
| 1772 | |
Adrian Hunter | 20758b6 | 2011-08-29 16:42:12 +0300 | [diff] [blame] | 1773 | static void sdhci_hw_reset(struct mmc_host *mmc) |
| 1774 | { |
| 1775 | struct sdhci_host *host = mmc_priv(mmc); |
| 1776 | |
| 1777 | if (host->ops && host->ops->hw_reset) |
| 1778 | host->ops->hw_reset(host); |
| 1779 | } |
| 1780 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1781 | static void sdhci_enable_sdio_irq_nolock(struct sdhci_host *host, int enable) |
| 1782 | { |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 1783 | if (!(host->flags & SDHCI_DEVICE_DEAD)) { |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1784 | if (enable) |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 1785 | host->ier |= SDHCI_INT_CARD_INT; |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1786 | else |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 1787 | host->ier &= ~SDHCI_INT_CARD_INT; |
| 1788 | |
| 1789 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 1790 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1791 | mmiowb(); |
| 1792 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1793 | } |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1794 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1795 | static void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable) |
| 1796 | { |
| 1797 | struct sdhci_host *host = mmc_priv(mmc); |
| 1798 | unsigned long flags; |
| 1799 | |
| 1800 | spin_lock_irqsave(&host->lock, flags); |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 1801 | if (enable) |
| 1802 | host->flags |= SDHCI_SDIO_IRQ_ENABLED; |
| 1803 | else |
| 1804 | host->flags &= ~SDHCI_SDIO_IRQ_ENABLED; |
| 1805 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 1806 | sdhci_enable_sdio_irq_nolock(host, enable); |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 1807 | spin_unlock_irqrestore(&host->lock, flags); |
| 1808 | } |
| 1809 | |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1810 | static int sdhci_start_signal_voltage_switch(struct mmc_host *mmc, |
| 1811 | struct mmc_ios *ios) |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1812 | { |
Dong Aisheng | ded97e0 | 2016-04-16 01:29:25 +0800 | [diff] [blame] | 1813 | struct sdhci_host *host = mmc_priv(mmc); |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1814 | u16 ctrl; |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1815 | int ret; |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1816 | |
| 1817 | /* |
| 1818 | * Signal Voltage Switching is only applicable for Host Controllers |
| 1819 | * v3.00 and above. |
| 1820 | */ |
| 1821 | if (host->version < SDHCI_SPEC_300) |
| 1822 | return 0; |
| 1823 | |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 1824 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1825 | |
Fabio Estevam | 21f5998 | 2013-02-14 10:35:03 -0200 | [diff] [blame] | 1826 | switch (ios->signal_voltage) { |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1827 | case MMC_SIGNAL_VOLTAGE_330: |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 1828 | if (!(host->flags & SDHCI_SIGNALING_330)) |
| 1829 | return -EINVAL; |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1830 | /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ |
| 1831 | ctrl &= ~SDHCI_CTRL_VDD_180; |
| 1832 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1833 | |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1834 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 1835 | ret = regulator_set_voltage(mmc->supply.vqmmc, 2700000, |
| 1836 | 3600000); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1837 | if (ret) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1838 | pr_warn("%s: Switching to 3.3V signalling voltage failed\n", |
| 1839 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1840 | return -EIO; |
| 1841 | } |
| 1842 | } |
| 1843 | /* Wait for 5ms */ |
| 1844 | usleep_range(5000, 5500); |
| 1845 | |
| 1846 | /* 3.3V regulator output should be stable within 5 ms */ |
| 1847 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1848 | if (!(ctrl & SDHCI_CTRL_VDD_180)) |
| 1849 | return 0; |
| 1850 | |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1851 | pr_warn("%s: 3.3V regulator output did not became stable\n", |
| 1852 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1853 | |
| 1854 | return -EAGAIN; |
| 1855 | case MMC_SIGNAL_VOLTAGE_180: |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 1856 | if (!(host->flags & SDHCI_SIGNALING_180)) |
| 1857 | return -EINVAL; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1858 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 1859 | ret = regulator_set_voltage(mmc->supply.vqmmc, |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1860 | 1700000, 1950000); |
| 1861 | if (ret) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1862 | pr_warn("%s: Switching to 1.8V signalling voltage failed\n", |
| 1863 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1864 | return -EIO; |
| 1865 | } |
| 1866 | } |
| 1867 | |
| 1868 | /* |
| 1869 | * Enable 1.8V Signal Enable in the Host Control2 |
| 1870 | * register |
| 1871 | */ |
| 1872 | ctrl |= SDHCI_CTRL_VDD_180; |
| 1873 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1874 | |
Vincent Yang | 9d967a6 | 2015-01-20 16:05:15 +0800 | [diff] [blame] | 1875 | /* Some controller need to do more when switching */ |
| 1876 | if (host->ops->voltage_switch) |
| 1877 | host->ops->voltage_switch(host); |
| 1878 | |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1879 | /* 1.8V regulator output should be stable within 5 ms */ |
| 1880 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1881 | if (ctrl & SDHCI_CTRL_VDD_180) |
| 1882 | return 0; |
| 1883 | |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1884 | pr_warn("%s: 1.8V regulator output did not became stable\n", |
| 1885 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1886 | |
| 1887 | return -EAGAIN; |
| 1888 | case MMC_SIGNAL_VOLTAGE_120: |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 1889 | if (!(host->flags & SDHCI_SIGNALING_120)) |
| 1890 | return -EINVAL; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 1891 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 1892 | ret = regulator_set_voltage(mmc->supply.vqmmc, 1100000, |
| 1893 | 1300000); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1894 | if (ret) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 1895 | pr_warn("%s: Switching to 1.2V signalling voltage failed\n", |
| 1896 | mmc_hostname(mmc)); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1897 | return -EIO; |
| 1898 | } |
| 1899 | } |
| 1900 | return 0; |
| 1901 | default: |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 1902 | /* No signal voltage switch required */ |
| 1903 | return 0; |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1904 | } |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 1905 | } |
| 1906 | |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1907 | static int sdhci_card_busy(struct mmc_host *mmc) |
| 1908 | { |
| 1909 | struct sdhci_host *host = mmc_priv(mmc); |
| 1910 | u32 present_state; |
| 1911 | |
Adrian Hunter | e613cc4 | 2016-06-23 14:00:58 +0300 | [diff] [blame] | 1912 | /* Check whether DAT[0] is 0 */ |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1913 | present_state = sdhci_readl(host, SDHCI_PRESENT_STATE); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1914 | |
Adrian Hunter | e613cc4 | 2016-06-23 14:00:58 +0300 | [diff] [blame] | 1915 | return !(present_state & SDHCI_DATA_0_LVL_MASK); |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 1916 | } |
| 1917 | |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1918 | static int sdhci_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) |
| 1919 | { |
| 1920 | struct sdhci_host *host = mmc_priv(mmc); |
| 1921 | unsigned long flags; |
| 1922 | |
| 1923 | spin_lock_irqsave(&host->lock, flags); |
| 1924 | host->flags |= SDHCI_HS400_TUNING; |
| 1925 | spin_unlock_irqrestore(&host->lock, flags); |
| 1926 | |
| 1927 | return 0; |
| 1928 | } |
| 1929 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1930 | static int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode) |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1931 | { |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1932 | struct sdhci_host *host = mmc_priv(mmc); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1933 | u16 ctrl; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1934 | int tuning_loop_counter = MAX_TUNING_LOOP; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1935 | int err = 0; |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 1936 | unsigned long flags; |
Adrian Hunter | 38e40bf | 2014-12-05 19:25:30 +0200 | [diff] [blame] | 1937 | unsigned int tuning_count = 0; |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1938 | bool hs400_tuning; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1939 | |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 1940 | spin_lock_irqsave(&host->lock, flags); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1941 | |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1942 | hs400_tuning = host->flags & SDHCI_HS400_TUNING; |
| 1943 | host->flags &= ~SDHCI_HS400_TUNING; |
| 1944 | |
Adrian Hunter | 38e40bf | 2014-12-05 19:25:30 +0200 | [diff] [blame] | 1945 | if (host->tuning_mode == SDHCI_TUNING_MODE_1) |
| 1946 | tuning_count = host->tuning_count; |
| 1947 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1948 | /* |
Weijun Yang | 9faac7b | 2015-10-04 12:04:12 +0000 | [diff] [blame] | 1949 | * The Host Controller needs tuning in case of SDR104 and DDR50 |
| 1950 | * mode, and for SDR50 mode when Use Tuning for SDR50 is set in |
| 1951 | * the Capabilities register. |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1952 | * If the Host Controller supports the HS200 mode then the |
| 1953 | * tuning function has to be executed. |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1954 | */ |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1955 | switch (host->timing) { |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1956 | /* HS400 tuning is done in HS200 mode */ |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 1957 | case MMC_TIMING_MMC_HS400: |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1958 | err = -EINVAL; |
| 1959 | goto out_unlock; |
| 1960 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1961 | case MMC_TIMING_MMC_HS200: |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 1962 | /* |
| 1963 | * Periodic re-tuning for HS400 is not expected to be needed, so |
| 1964 | * disable it here. |
| 1965 | */ |
| 1966 | if (hs400_tuning) |
| 1967 | tuning_count = 0; |
| 1968 | break; |
| 1969 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1970 | case MMC_TIMING_UHS_SDR104: |
Weijun Yang | 9faac7b | 2015-10-04 12:04:12 +0000 | [diff] [blame] | 1971 | case MMC_TIMING_UHS_DDR50: |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1972 | break; |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 1973 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1974 | case MMC_TIMING_UHS_SDR50: |
Adrian Hunter | 4228b21 | 2016-04-20 09:24:03 +0300 | [diff] [blame] | 1975 | if (host->flags & SDHCI_SDR50_NEEDS_TUNING) |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1976 | break; |
| 1977 | /* FALLTHROUGH */ |
| 1978 | |
| 1979 | default: |
Adrian Hunter | d519c86 | 2014-12-05 19:25:29 +0200 | [diff] [blame] | 1980 | goto out_unlock; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1981 | } |
| 1982 | |
Dong Aisheng | 4525181 | 2013-09-13 19:11:30 +0800 | [diff] [blame] | 1983 | if (host->ops->platform_execute_tuning) { |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 1984 | spin_unlock_irqrestore(&host->lock, flags); |
Dong Aisheng | 4525181 | 2013-09-13 19:11:30 +0800 | [diff] [blame] | 1985 | err = host->ops->platform_execute_tuning(host, opcode); |
Dong Aisheng | 4525181 | 2013-09-13 19:11:30 +0800 | [diff] [blame] | 1986 | return err; |
| 1987 | } |
| 1988 | |
Russell King | 4b6f37d | 2014-04-25 12:59:36 +0100 | [diff] [blame] | 1989 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 1990 | ctrl |= SDHCI_CTRL_EXEC_TUNING; |
Vincent Yang | 67d0d04 | 2015-01-20 16:05:16 +0800 | [diff] [blame] | 1991 | if (host->quirks2 & SDHCI_QUIRK2_TUNING_WORK_AROUND) |
| 1992 | ctrl |= SDHCI_CTRL_TUNED_CLK; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 1993 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 1994 | |
| 1995 | /* |
| 1996 | * As per the Host Controller spec v3.00, tuning command |
| 1997 | * generates Buffer Read Ready interrupt, so enable that. |
| 1998 | * |
| 1999 | * Note: The spec clearly says that when tuning sequence |
| 2000 | * is being performed, the controller does not generate |
| 2001 | * interrupts other than Buffer Read Ready interrupt. But |
| 2002 | * to make sure we don't hit a controller bug, we _only_ |
| 2003 | * enable Buffer Read Ready interrupt here. |
| 2004 | */ |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2005 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE); |
| 2006 | sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2007 | |
| 2008 | /* |
| 2009 | * Issue CMD19 repeatedly till Execute Tuning is set to 0 or the number |
Simon Horman | 1473bdd | 2016-05-13 13:24:31 +0900 | [diff] [blame] | 2010 | * of loops reaches 40 times. |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2011 | */ |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2012 | do { |
| 2013 | struct mmc_command cmd = {0}; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2014 | struct mmc_request mrq = {NULL}; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2015 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2016 | cmd.opcode = opcode; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2017 | cmd.arg = 0; |
| 2018 | cmd.flags = MMC_RSP_R1 | MMC_CMD_ADTC; |
| 2019 | cmd.retries = 0; |
| 2020 | cmd.data = NULL; |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 2021 | cmd.mrq = &mrq; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2022 | cmd.error = 0; |
| 2023 | |
Al Cooper | 7ce45e9 | 2014-05-09 11:34:07 -0400 | [diff] [blame] | 2024 | if (tuning_loop_counter-- == 0) |
| 2025 | break; |
| 2026 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2027 | mrq.cmd = &cmd; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2028 | |
| 2029 | /* |
| 2030 | * In response to CMD19, the card sends 64 bytes of tuning |
| 2031 | * block to the Host Controller. So we set the block size |
| 2032 | * to 64 here. |
| 2033 | */ |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2034 | if (cmd.opcode == MMC_SEND_TUNING_BLOCK_HS200) { |
| 2035 | if (mmc->ios.bus_width == MMC_BUS_WIDTH_8) |
| 2036 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 128), |
| 2037 | SDHCI_BLOCK_SIZE); |
| 2038 | else if (mmc->ios.bus_width == MMC_BUS_WIDTH_4) |
| 2039 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), |
| 2040 | SDHCI_BLOCK_SIZE); |
| 2041 | } else { |
| 2042 | sdhci_writew(host, SDHCI_MAKE_BLKSZ(7, 64), |
| 2043 | SDHCI_BLOCK_SIZE); |
| 2044 | } |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2045 | |
| 2046 | /* |
| 2047 | * The tuning block is sent by the card to the host controller. |
| 2048 | * So we set the TRNS_READ bit in the Transfer Mode register. |
| 2049 | * This also takes care of setting DMA Enable and Multi Block |
| 2050 | * Select in the same register to 0. |
| 2051 | */ |
| 2052 | sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE); |
| 2053 | |
| 2054 | sdhci_send_command(host, &cmd); |
| 2055 | |
| 2056 | host->cmd = NULL; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2057 | |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 2058 | spin_unlock_irqrestore(&host->lock, flags); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2059 | /* Wait for Buffer Read Ready interrupt */ |
| 2060 | wait_event_interruptible_timeout(host->buf_ready_int, |
| 2061 | (host->tuning_done == 1), |
| 2062 | msecs_to_jiffies(50)); |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 2063 | spin_lock_irqsave(&host->lock, flags); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2064 | |
| 2065 | if (!host->tuning_done) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2066 | pr_info(DRIVER_NAME ": Timeout waiting for Buffer Read Ready interrupt during tuning procedure, falling back to fixed sampling clock\n"); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2067 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2068 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
| 2069 | ctrl &= ~SDHCI_CTRL_EXEC_TUNING; |
| 2070 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
| 2071 | |
| 2072 | err = -EIO; |
| 2073 | goto out; |
| 2074 | } |
| 2075 | |
| 2076 | host->tuning_done = 0; |
| 2077 | |
| 2078 | ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
Nick Sanders | 197160d | 2014-05-06 18:52:38 -0700 | [diff] [blame] | 2079 | |
| 2080 | /* eMMC spec does not require a delay between tuning cycles */ |
| 2081 | if (opcode == MMC_SEND_TUNING_BLOCK) |
| 2082 | mdelay(1); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2083 | } while (ctrl & SDHCI_CTRL_EXEC_TUNING); |
| 2084 | |
| 2085 | /* |
| 2086 | * The Host Driver has exhausted the maximum number of loops allowed, |
| 2087 | * so use fixed sampling frequency. |
| 2088 | */ |
Al Cooper | 7ce45e9 | 2014-05-09 11:34:07 -0400 | [diff] [blame] | 2089 | if (tuning_loop_counter < 0) { |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2090 | ctrl &= ~SDHCI_CTRL_TUNED_CLK; |
| 2091 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
Al Cooper | 7ce45e9 | 2014-05-09 11:34:07 -0400 | [diff] [blame] | 2092 | } |
| 2093 | if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2094 | pr_info(DRIVER_NAME ": Tuning procedure failed, falling back to fixed sampling clock\n"); |
Dong Aisheng | 114f2bf | 2013-10-18 19:48:45 +0800 | [diff] [blame] | 2095 | err = -EIO; |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2096 | } |
| 2097 | |
| 2098 | out: |
Adrian Hunter | 38e40bf | 2014-12-05 19:25:30 +0200 | [diff] [blame] | 2099 | if (tuning_count) { |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 2100 | /* |
| 2101 | * In case tuning fails, host controllers which support |
| 2102 | * re-tuning can try tuning again at a later time, when the |
| 2103 | * re-tuning timer expires. So for these controllers, we |
| 2104 | * return 0. Since there might be other controllers who do not |
| 2105 | * have this capability, we return error for them. |
| 2106 | */ |
| 2107 | err = 0; |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2108 | } |
| 2109 | |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 2110 | host->mmc->retune_period = err ? 0 : tuning_count; |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2111 | |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2112 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 2113 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Adrian Hunter | d519c86 | 2014-12-05 19:25:29 +0200 | [diff] [blame] | 2114 | out_unlock: |
Aisheng Dong | 2b35bd8 | 2013-12-23 19:13:04 +0800 | [diff] [blame] | 2115 | spin_unlock_irqrestore(&host->lock, flags); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2116 | return err; |
| 2117 | } |
| 2118 | |
Adrian Hunter | cb84964 | 2015-02-06 14:12:59 +0200 | [diff] [blame] | 2119 | static int sdhci_select_drive_strength(struct mmc_card *card, |
| 2120 | unsigned int max_dtr, int host_drv, |
| 2121 | int card_drv, int *drv_type) |
| 2122 | { |
| 2123 | struct sdhci_host *host = mmc_priv(card->host); |
| 2124 | |
| 2125 | if (!host->ops->select_drive_strength) |
| 2126 | return 0; |
| 2127 | |
| 2128 | return host->ops->select_drive_strength(host, card, max_dtr, host_drv, |
| 2129 | card_drv, drv_type); |
| 2130 | } |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 2131 | |
| 2132 | static void sdhci_enable_preset_value(struct sdhci_host *host, bool enable) |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2133 | { |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2134 | /* Host Controller v3.00 defines preset value registers */ |
| 2135 | if (host->version < SDHCI_SPEC_300) |
| 2136 | return; |
| 2137 | |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2138 | /* |
| 2139 | * We only enable or disable Preset Value if they are not already |
| 2140 | * enabled or disabled respectively. Otherwise, we bail out. |
| 2141 | */ |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 2142 | if (host->preset_enabled != enable) { |
| 2143 | u16 ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2); |
| 2144 | |
| 2145 | if (enable) |
| 2146 | ctrl |= SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 2147 | else |
| 2148 | ctrl &= ~SDHCI_CTRL_PRESET_VAL_ENABLE; |
| 2149 | |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2150 | sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2); |
Russell King | da91a8f | 2014-04-25 13:00:12 +0100 | [diff] [blame] | 2151 | |
| 2152 | if (enable) |
| 2153 | host->flags |= SDHCI_PV_ENABLED; |
| 2154 | else |
| 2155 | host->flags &= ~SDHCI_PV_ENABLED; |
| 2156 | |
| 2157 | host->preset_enabled = enable; |
Arindam Nath | 4d55c5a | 2011-05-05 12:19:05 +0530 | [diff] [blame] | 2158 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2159 | } |
| 2160 | |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2161 | static void sdhci_post_req(struct mmc_host *mmc, struct mmc_request *mrq, |
| 2162 | int err) |
| 2163 | { |
| 2164 | struct sdhci_host *host = mmc_priv(mmc); |
| 2165 | struct mmc_data *data = mrq->data; |
| 2166 | |
Russell King | f48f039 | 2016-01-26 13:40:32 +0000 | [diff] [blame] | 2167 | if (data->host_cookie != COOKIE_UNMAPPED) |
Russell King | 771a3dc | 2016-01-26 13:40:53 +0000 | [diff] [blame] | 2168 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
| 2169 | data->flags & MMC_DATA_WRITE ? |
| 2170 | DMA_TO_DEVICE : DMA_FROM_DEVICE); |
| 2171 | |
| 2172 | data->host_cookie = COOKIE_UNMAPPED; |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2173 | } |
| 2174 | |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2175 | static void sdhci_pre_req(struct mmc_host *mmc, struct mmc_request *mrq, |
| 2176 | bool is_first_req) |
| 2177 | { |
| 2178 | struct sdhci_host *host = mmc_priv(mmc); |
| 2179 | |
Haibo Chen | d31911b | 2015-08-25 10:02:11 +0800 | [diff] [blame] | 2180 | mrq->data->host_cookie = COOKIE_UNMAPPED; |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2181 | |
| 2182 | if (host->flags & SDHCI_REQ_USE_DMA) |
Russell King | 94538e5 | 2016-01-26 13:40:37 +0000 | [diff] [blame] | 2183 | sdhci_pre_dma_transfer(host, mrq->data, COOKIE_PRE_MAPPED); |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2184 | } |
| 2185 | |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 2186 | static inline bool sdhci_has_requests(struct sdhci_host *host) |
| 2187 | { |
| 2188 | return host->cmd || host->data_cmd; |
| 2189 | } |
| 2190 | |
| 2191 | static void sdhci_error_out_mrqs(struct sdhci_host *host, int err) |
| 2192 | { |
| 2193 | if (host->data_cmd) { |
| 2194 | host->data_cmd->error = err; |
| 2195 | sdhci_finish_mrq(host, host->data_cmd->mrq); |
| 2196 | } |
| 2197 | |
| 2198 | if (host->cmd) { |
| 2199 | host->cmd->error = err; |
| 2200 | sdhci_finish_mrq(host, host->cmd->mrq); |
| 2201 | } |
| 2202 | } |
| 2203 | |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2204 | static void sdhci_card_event(struct mmc_host *mmc) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2205 | { |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2206 | struct sdhci_host *host = mmc_priv(mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2207 | unsigned long flags; |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 2208 | int present; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2209 | |
Christian Daudt | 722e128 | 2013-06-20 14:26:36 -0700 | [diff] [blame] | 2210 | /* First check if client has provided their own card event */ |
| 2211 | if (host->ops->card_event) |
| 2212 | host->ops->card_event(host); |
| 2213 | |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2214 | present = mmc->ops->get_cd(mmc); |
Krzysztof Kozlowski | 2836766 | 2015-01-05 10:50:15 +0100 | [diff] [blame] | 2215 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2216 | spin_lock_irqsave(&host->lock, flags); |
| 2217 | |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 2218 | /* Check sdhci_has_requests() first in case we are runtime suspended */ |
| 2219 | if (sdhci_has_requests(host) && !present) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2220 | pr_err("%s: Card removed during transfer!\n", |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2221 | mmc_hostname(host->mmc)); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2222 | pr_err("%s: Resetting controller.\n", |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2223 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2224 | |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 2225 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 2226 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2227 | |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 2228 | sdhci_error_out_mrqs(host, -ENOMEDIUM); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2229 | } |
| 2230 | |
| 2231 | spin_unlock_irqrestore(&host->lock, flags); |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2232 | } |
| 2233 | |
| 2234 | static const struct mmc_host_ops sdhci_ops = { |
| 2235 | .request = sdhci_request, |
Haibo Chen | 348487c | 2014-12-09 17:04:05 +0800 | [diff] [blame] | 2236 | .post_req = sdhci_post_req, |
| 2237 | .pre_req = sdhci_pre_req, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2238 | .set_ios = sdhci_set_ios, |
Kevin Liu | 94144a4 | 2013-02-28 17:35:53 +0800 | [diff] [blame] | 2239 | .get_cd = sdhci_get_cd, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2240 | .get_ro = sdhci_get_ro, |
| 2241 | .hw_reset = sdhci_hw_reset, |
| 2242 | .enable_sdio_irq = sdhci_enable_sdio_irq, |
| 2243 | .start_signal_voltage_switch = sdhci_start_signal_voltage_switch, |
Adrian Hunter | b5540ce | 2014-12-05 19:25:31 +0200 | [diff] [blame] | 2244 | .prepare_hs400_tuning = sdhci_prepare_hs400_tuning, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2245 | .execute_tuning = sdhci_execute_tuning, |
Adrian Hunter | cb84964 | 2015-02-06 14:12:59 +0200 | [diff] [blame] | 2246 | .select_drive_strength = sdhci_select_drive_strength, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2247 | .card_event = sdhci_card_event, |
Kevin Liu | 20b92a3 | 2012-12-17 19:29:26 +0800 | [diff] [blame] | 2248 | .card_busy = sdhci_card_busy, |
Guennadi Liakhovetski | 71e6921 | 2012-12-04 16:51:40 +0100 | [diff] [blame] | 2249 | }; |
| 2250 | |
| 2251 | /*****************************************************************************\ |
| 2252 | * * |
| 2253 | * Tasklets * |
| 2254 | * * |
| 2255 | \*****************************************************************************/ |
| 2256 | |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 2257 | static bool sdhci_request_done(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2258 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2259 | unsigned long flags; |
| 2260 | struct mmc_request *mrq; |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 2261 | int i; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2262 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2263 | spin_lock_irqsave(&host->lock, flags); |
| 2264 | |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 2265 | for (i = 0; i < SDHCI_MAX_MRQS; i++) { |
| 2266 | mrq = host->mrqs_done[i]; |
| 2267 | if (mrq) { |
| 2268 | host->mrqs_done[i] = NULL; |
| 2269 | break; |
| 2270 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2271 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2272 | |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 2273 | if (!mrq) { |
| 2274 | spin_unlock_irqrestore(&host->lock, flags); |
| 2275 | return true; |
| 2276 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2277 | |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 2278 | sdhci_del_timer(host, mrq); |
| 2279 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2280 | /* |
Russell King | 054cedf | 2016-01-26 13:40:42 +0000 | [diff] [blame] | 2281 | * Always unmap the data buffers if they were mapped by |
| 2282 | * sdhci_prepare_data() whenever we finish with a request. |
| 2283 | * This avoids leaking DMA mappings on error. |
| 2284 | */ |
| 2285 | if (host->flags & SDHCI_REQ_USE_DMA) { |
| 2286 | struct mmc_data *data = mrq->data; |
| 2287 | |
| 2288 | if (data && data->host_cookie == COOKIE_MAPPED) { |
| 2289 | dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, |
| 2290 | (data->flags & MMC_DATA_READ) ? |
| 2291 | DMA_FROM_DEVICE : DMA_TO_DEVICE); |
| 2292 | data->host_cookie = COOKIE_UNMAPPED; |
| 2293 | } |
| 2294 | } |
| 2295 | |
| 2296 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2297 | * The controller needs a reset of internal state machines |
| 2298 | * upon error conditions. |
| 2299 | */ |
Adrian Hunter | 0cc563c | 2016-06-29 16:24:28 +0300 | [diff] [blame] | 2300 | if (sdhci_needs_reset(host, mrq)) { |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 2301 | /* Some controllers need this kick or reset won't work here */ |
Andy Shevchenko | 8213af3 | 2013-01-07 16:31:08 +0200 | [diff] [blame] | 2302 | if (host->quirks & SDHCI_QUIRK_CLOCK_BEFORE_RESET) |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 2303 | /* This is to force an update */ |
Russell King | 1771059 | 2014-04-25 12:58:55 +0100 | [diff] [blame] | 2304 | host->ops->set_clock(host, host->clock); |
Pierre Ossman | 645289d | 2006-06-30 02:22:33 -0700 | [diff] [blame] | 2305 | |
| 2306 | /* Spec says we should do both at the same time, but Ricoh |
| 2307 | controllers do not like that. */ |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 2308 | sdhci_do_reset(host, SDHCI_RESET_CMD); |
| 2309 | sdhci_do_reset(host, SDHCI_RESET_DATA); |
Adrian Hunter | ed1563d | 2016-06-29 16:24:29 +0300 | [diff] [blame] | 2310 | |
| 2311 | host->pending_reset = false; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2312 | } |
| 2313 | |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 2314 | if (!sdhci_has_requests(host)) |
| 2315 | sdhci_led_deactivate(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2316 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 2317 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2318 | spin_unlock_irqrestore(&host->lock, flags); |
| 2319 | |
| 2320 | mmc_request_done(host->mmc, mrq); |
Adrian Hunter | 4e9f8fe | 2016-06-29 16:24:34 +0300 | [diff] [blame] | 2321 | |
| 2322 | return false; |
| 2323 | } |
| 2324 | |
| 2325 | static void sdhci_tasklet_finish(unsigned long param) |
| 2326 | { |
| 2327 | struct sdhci_host *host = (struct sdhci_host *)param; |
| 2328 | |
| 2329 | while (!sdhci_request_done(host)) |
| 2330 | ; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2331 | } |
| 2332 | |
| 2333 | static void sdhci_timeout_timer(unsigned long data) |
| 2334 | { |
| 2335 | struct sdhci_host *host; |
| 2336 | unsigned long flags; |
| 2337 | |
| 2338 | host = (struct sdhci_host*)data; |
| 2339 | |
| 2340 | spin_lock_irqsave(&host->lock, flags); |
| 2341 | |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 2342 | if (host->cmd && !sdhci_data_line_cmd(host->cmd)) { |
| 2343 | pr_err("%s: Timeout waiting for hardware cmd interrupt.\n", |
| 2344 | mmc_hostname(host->mmc)); |
| 2345 | sdhci_dumpregs(host); |
| 2346 | |
| 2347 | host->cmd->error = -ETIMEDOUT; |
| 2348 | sdhci_finish_mrq(host, host->cmd->mrq); |
| 2349 | } |
| 2350 | |
| 2351 | mmiowb(); |
| 2352 | spin_unlock_irqrestore(&host->lock, flags); |
| 2353 | } |
| 2354 | |
| 2355 | static void sdhci_timeout_data_timer(unsigned long data) |
| 2356 | { |
| 2357 | struct sdhci_host *host; |
| 2358 | unsigned long flags; |
| 2359 | |
| 2360 | host = (struct sdhci_host *)data; |
| 2361 | |
| 2362 | spin_lock_irqsave(&host->lock, flags); |
| 2363 | |
| 2364 | if (host->data || host->data_cmd || |
| 2365 | (host->cmd && sdhci_data_line_cmd(host->cmd))) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2366 | pr_err("%s: Timeout waiting for hardware interrupt.\n", |
| 2367 | mmc_hostname(host->mmc)); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2368 | sdhci_dumpregs(host); |
| 2369 | |
| 2370 | if (host->data) { |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2371 | host->data->error = -ETIMEDOUT; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2372 | sdhci_finish_data(host); |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 2373 | } else if (host->data_cmd) { |
| 2374 | host->data_cmd->error = -ETIMEDOUT; |
| 2375 | sdhci_finish_mrq(host, host->data_cmd->mrq); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2376 | } else { |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 2377 | host->cmd->error = -ETIMEDOUT; |
| 2378 | sdhci_finish_mrq(host, host->cmd->mrq); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2379 | } |
| 2380 | } |
| 2381 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 2382 | mmiowb(); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2383 | spin_unlock_irqrestore(&host->lock, flags); |
| 2384 | } |
| 2385 | |
| 2386 | /*****************************************************************************\ |
| 2387 | * * |
| 2388 | * Interrupt handling * |
| 2389 | * * |
| 2390 | \*****************************************************************************/ |
| 2391 | |
Adrian Hunter | 6154139 | 2014-09-24 10:27:27 +0300 | [diff] [blame] | 2392 | static void sdhci_cmd_irq(struct sdhci_host *host, u32 intmask, u32 *mask) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2393 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2394 | if (!host->cmd) { |
Adrian Hunter | ed1563d | 2016-06-29 16:24:29 +0300 | [diff] [blame] | 2395 | /* |
| 2396 | * SDHCI recovers from errors by resetting the cmd and data |
| 2397 | * circuits. Until that is done, there very well might be more |
| 2398 | * interrupts, so ignore them in that case. |
| 2399 | */ |
| 2400 | if (host->pending_reset) |
| 2401 | return; |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2402 | pr_err("%s: Got command interrupt 0x%08x even though no command operation was in progress.\n", |
| 2403 | mmc_hostname(host->mmc), (unsigned)intmask); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2404 | sdhci_dumpregs(host); |
| 2405 | return; |
| 2406 | } |
| 2407 | |
Russell King | ec014cb | 2016-01-26 13:39:39 +0000 | [diff] [blame] | 2408 | if (intmask & (SDHCI_INT_TIMEOUT | SDHCI_INT_CRC | |
| 2409 | SDHCI_INT_END_BIT | SDHCI_INT_INDEX)) { |
| 2410 | if (intmask & SDHCI_INT_TIMEOUT) |
| 2411 | host->cmd->error = -ETIMEDOUT; |
| 2412 | else |
| 2413 | host->cmd->error = -EILSEQ; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2414 | |
Russell King | 71fcbda | 2016-01-26 13:39:45 +0000 | [diff] [blame] | 2415 | /* |
| 2416 | * If this command initiates a data phase and a response |
| 2417 | * CRC error is signalled, the card can start transferring |
| 2418 | * data - the card may have received the command without |
| 2419 | * error. We must not terminate the mmc_request early. |
| 2420 | * |
| 2421 | * If the card did not receive the command or returned an |
| 2422 | * error which prevented it sending data, the data phase |
| 2423 | * will time out. |
| 2424 | */ |
| 2425 | if (host->cmd->data && |
| 2426 | (intmask & (SDHCI_INT_CRC | SDHCI_INT_TIMEOUT)) == |
| 2427 | SDHCI_INT_CRC) { |
| 2428 | host->cmd = NULL; |
| 2429 | return; |
| 2430 | } |
| 2431 | |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 2432 | sdhci_finish_mrq(host, host->cmd->mrq); |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2433 | return; |
| 2434 | } |
| 2435 | |
Adrian Hunter | 6bde868 | 2016-06-29 16:24:20 +0300 | [diff] [blame] | 2436 | if ((host->quirks2 & SDHCI_QUIRK2_STOP_WITH_TC) && |
| 2437 | !(host->cmd->flags & MMC_RSP_BUSY) && !host->data && |
| 2438 | host->cmd->opcode == MMC_STOP_TRANSMISSION) |
Adrian Hunter | 6154139 | 2014-09-24 10:27:27 +0300 | [diff] [blame] | 2439 | *mask &= ~SDHCI_INT_DATA_END; |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2440 | |
| 2441 | if (intmask & SDHCI_INT_RESPONSE) |
Pierre Ossman | 43b58b3 | 2007-07-25 23:15:27 +0200 | [diff] [blame] | 2442 | sdhci_finish_command(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2443 | } |
| 2444 | |
George G. Davis | 0957c33 | 2010-02-18 12:32:12 -0500 | [diff] [blame] | 2445 | #ifdef CONFIG_MMC_DEBUG |
Adrian Hunter | 08621b1 | 2014-11-04 12:42:38 +0200 | [diff] [blame] | 2446 | static void sdhci_adma_show_error(struct sdhci_host *host) |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2447 | { |
| 2448 | const char *name = mmc_hostname(host->mmc); |
Adrian Hunter | 1c3d5f6 | 2014-11-04 12:42:41 +0200 | [diff] [blame] | 2449 | void *desc = host->adma_table; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2450 | |
| 2451 | sdhci_dumpregs(host); |
| 2452 | |
| 2453 | while (true) { |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2454 | struct sdhci_adma2_64_desc *dma_desc = desc; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2455 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 2456 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 2457 | DBG("%s: %p: DMA 0x%08x%08x, LEN 0x%04x, Attr=0x%02x\n", |
| 2458 | name, desc, le32_to_cpu(dma_desc->addr_hi), |
| 2459 | le32_to_cpu(dma_desc->addr_lo), |
| 2460 | le16_to_cpu(dma_desc->len), |
| 2461 | le16_to_cpu(dma_desc->cmd)); |
| 2462 | else |
| 2463 | DBG("%s: %p: DMA 0x%08x, LEN 0x%04x, Attr=0x%02x\n", |
| 2464 | name, desc, le32_to_cpu(dma_desc->addr_lo), |
| 2465 | le16_to_cpu(dma_desc->len), |
| 2466 | le16_to_cpu(dma_desc->cmd)); |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2467 | |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 2468 | desc += host->desc_sz; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2469 | |
Adrian Hunter | 0545230 | 2014-11-04 12:42:45 +0200 | [diff] [blame] | 2470 | if (dma_desc->cmd & cpu_to_le16(ADMA2_END)) |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2471 | break; |
| 2472 | } |
| 2473 | } |
| 2474 | #else |
Adrian Hunter | 08621b1 | 2014-11-04 12:42:38 +0200 | [diff] [blame] | 2475 | static void sdhci_adma_show_error(struct sdhci_host *host) { } |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2476 | #endif |
| 2477 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2478 | static void sdhci_data_irq(struct sdhci_host *host, u32 intmask) |
| 2479 | { |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2480 | u32 command; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2481 | |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2482 | /* CMD19 generates _only_ Buffer Read Ready interrupt */ |
| 2483 | if (intmask & SDHCI_INT_DATA_AVAIL) { |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 2484 | command = SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)); |
| 2485 | if (command == MMC_SEND_TUNING_BLOCK || |
| 2486 | command == MMC_SEND_TUNING_BLOCK_HS200) { |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 2487 | host->tuning_done = 1; |
| 2488 | wake_up(&host->buf_ready_int); |
| 2489 | return; |
| 2490 | } |
| 2491 | } |
| 2492 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2493 | if (!host->data) { |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 2494 | struct mmc_command *data_cmd = host->data_cmd; |
| 2495 | |
| 2496 | if (data_cmd) |
| 2497 | host->data_cmd = NULL; |
| 2498 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2499 | /* |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2500 | * The "data complete" interrupt is also used to |
| 2501 | * indicate that a busy state has ended. See comment |
| 2502 | * above in sdhci_cmd_irq(). |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2503 | */ |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 2504 | if (data_cmd && (data_cmd->flags & MMC_RSP_BUSY)) { |
Matthieu CASTET | c5abd5e | 2014-08-14 16:03:17 +0200 | [diff] [blame] | 2505 | if (intmask & SDHCI_INT_DATA_TIMEOUT) { |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 2506 | data_cmd->error = -ETIMEDOUT; |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 2507 | sdhci_finish_mrq(host, data_cmd->mrq); |
Matthieu CASTET | c5abd5e | 2014-08-14 16:03:17 +0200 | [diff] [blame] | 2508 | return; |
| 2509 | } |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2510 | if (intmask & SDHCI_INT_DATA_END) { |
Chanho Min | e99783a | 2014-08-30 12:40:40 +0900 | [diff] [blame] | 2511 | /* |
| 2512 | * Some cards handle busy-end interrupt |
| 2513 | * before the command completed, so make |
| 2514 | * sure we do things in the proper order. |
| 2515 | */ |
Adrian Hunter | ea96802 | 2016-06-29 16:24:24 +0300 | [diff] [blame] | 2516 | if (host->cmd == data_cmd) |
| 2517 | return; |
| 2518 | |
Adrian Hunter | a6d3bdd | 2016-06-29 16:24:27 +0300 | [diff] [blame] | 2519 | sdhci_finish_mrq(host, data_cmd->mrq); |
Pierre Ossman | e809517 | 2008-07-25 01:09:08 +0200 | [diff] [blame] | 2520 | return; |
| 2521 | } |
| 2522 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2523 | |
Adrian Hunter | ed1563d | 2016-06-29 16:24:29 +0300 | [diff] [blame] | 2524 | /* |
| 2525 | * SDHCI recovers from errors by resetting the cmd and data |
| 2526 | * circuits. Until that is done, there very well might be more |
| 2527 | * interrupts, so ignore them in that case. |
| 2528 | */ |
| 2529 | if (host->pending_reset) |
| 2530 | return; |
| 2531 | |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 2532 | pr_err("%s: Got data interrupt 0x%08x even though no data operation was in progress.\n", |
| 2533 | mmc_hostname(host->mmc), (unsigned)intmask); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2534 | sdhci_dumpregs(host); |
| 2535 | |
| 2536 | return; |
| 2537 | } |
| 2538 | |
| 2539 | if (intmask & SDHCI_INT_DATA_TIMEOUT) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2540 | host->data->error = -ETIMEDOUT; |
Aries Lee | 22113ef | 2010-12-15 08:14:24 +0100 | [diff] [blame] | 2541 | else if (intmask & SDHCI_INT_DATA_END_BIT) |
| 2542 | host->data->error = -EILSEQ; |
| 2543 | else if ((intmask & SDHCI_INT_DATA_CRC) && |
| 2544 | SDHCI_GET_CMD(sdhci_readw(host, SDHCI_COMMAND)) |
| 2545 | != MMC_BUS_TEST_R) |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2546 | host->data->error = -EILSEQ; |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2547 | else if (intmask & SDHCI_INT_ADMA_ERROR) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 2548 | pr_err("%s: ADMA error\n", mmc_hostname(host->mmc)); |
Adrian Hunter | 08621b1 | 2014-11-04 12:42:38 +0200 | [diff] [blame] | 2549 | sdhci_adma_show_error(host); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 2550 | host->data->error = -EIO; |
Haijun Zhang | a4071fb | 2012-12-04 10:41:28 +0800 | [diff] [blame] | 2551 | if (host->ops->adma_workaround) |
| 2552 | host->ops->adma_workaround(host, intmask); |
Ben Dooks | 6882a8c | 2009-06-14 13:52:38 +0100 | [diff] [blame] | 2553 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2554 | |
Pierre Ossman | 17b0429 | 2007-07-22 22:18:46 +0200 | [diff] [blame] | 2555 | if (host->data->error) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2556 | sdhci_finish_data(host); |
| 2557 | else { |
Pierre Ossman | a406f5a | 2006-07-02 16:50:59 +0100 | [diff] [blame] | 2558 | if (intmask & (SDHCI_INT_DATA_AVAIL | SDHCI_INT_SPACE_AVAIL)) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2559 | sdhci_transfer_pio(host); |
| 2560 | |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 2561 | /* |
| 2562 | * We currently don't do anything fancy with DMA |
| 2563 | * boundaries, but as we can't disable the feature |
| 2564 | * we need to at least restart the transfer. |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 2565 | * |
| 2566 | * According to the spec sdhci_readl(host, SDHCI_DMA_ADDRESS) |
| 2567 | * should return a valid address to continue from, but as |
| 2568 | * some controllers are faulty, don't trust them. |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 2569 | */ |
Mikko Vinni | f6a03cb | 2011-04-12 09:36:18 -0400 | [diff] [blame] | 2570 | if (intmask & SDHCI_INT_DMA_END) { |
| 2571 | u32 dmastart, dmanow; |
| 2572 | dmastart = sg_dma_address(host->data->sg); |
| 2573 | dmanow = dmastart + host->data->bytes_xfered; |
| 2574 | /* |
| 2575 | * Force update to the next DMA block boundary. |
| 2576 | */ |
| 2577 | dmanow = (dmanow & |
| 2578 | ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1)) + |
| 2579 | SDHCI_DEFAULT_BOUNDARY_SIZE; |
| 2580 | host->data->bytes_xfered = dmanow - dmastart; |
| 2581 | DBG("%s: DMA base 0x%08x, transferred 0x%06x bytes," |
| 2582 | " next 0x%08x\n", |
| 2583 | mmc_hostname(host->mmc), dmastart, |
| 2584 | host->data->bytes_xfered, dmanow); |
| 2585 | sdhci_writel(host, dmanow, SDHCI_DMA_ADDRESS); |
| 2586 | } |
Pierre Ossman | 6ba736a | 2007-05-13 22:39:23 +0200 | [diff] [blame] | 2587 | |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 2588 | if (intmask & SDHCI_INT_DATA_END) { |
Adrian Hunter | 7c89a3d | 2016-06-29 16:24:23 +0300 | [diff] [blame] | 2589 | if (host->cmd == host->data_cmd) { |
Pierre Ossman | e538fbe | 2007-08-12 16:46:32 +0200 | [diff] [blame] | 2590 | /* |
| 2591 | * Data managed to finish before the |
| 2592 | * command completed. Make sure we do |
| 2593 | * things in the proper order. |
| 2594 | */ |
| 2595 | host->data_early = 1; |
| 2596 | } else { |
| 2597 | sdhci_finish_data(host); |
| 2598 | } |
| 2599 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2600 | } |
| 2601 | } |
| 2602 | |
David Howells | 7d12e78 | 2006-10-05 14:55:46 +0100 | [diff] [blame] | 2603 | static irqreturn_t sdhci_irq(int irq, void *dev_id) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2604 | { |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2605 | irqreturn_t result = IRQ_NONE; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2606 | struct sdhci_host *host = dev_id; |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2607 | u32 intmask, mask, unexpected = 0; |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2608 | int max_loops = 16; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2609 | |
| 2610 | spin_lock(&host->lock); |
| 2611 | |
Russell King | be13855 | 2014-04-25 12:55:56 +0100 | [diff] [blame] | 2612 | if (host->runtime_suspended && !sdhci_sdio_irq_enabled(host)) { |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2613 | spin_unlock(&host->lock); |
Adrian Hunter | 655bca7 | 2014-03-11 10:09:36 +0200 | [diff] [blame] | 2614 | return IRQ_NONE; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2615 | } |
| 2616 | |
Anton Vorontsov | 4e4141a | 2009-03-17 00:13:46 +0300 | [diff] [blame] | 2617 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
Mark Lord | 62df67a5 | 2007-03-06 13:30:13 +0100 | [diff] [blame] | 2618 | if (!intmask || intmask == 0xffffffff) { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2619 | result = IRQ_NONE; |
| 2620 | goto out; |
| 2621 | } |
| 2622 | |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2623 | do { |
| 2624 | /* Clear selected interrupts. */ |
| 2625 | mask = intmask & (SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | |
| 2626 | SDHCI_INT_BUS_POWER); |
| 2627 | sdhci_writel(host, mask, SDHCI_INT_STATUS); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2628 | |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2629 | DBG("*** %s got interrupt: 0x%08x\n", |
| 2630 | mmc_hostname(host->mmc), intmask); |
| 2631 | |
| 2632 | if (intmask & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
| 2633 | u32 present = sdhci_readl(host, SDHCI_PRESENT_STATE) & |
| 2634 | SDHCI_CARD_PRESENT; |
| 2635 | |
| 2636 | /* |
| 2637 | * There is a observation on i.mx esdhc. INSERT |
| 2638 | * bit will be immediately set again when it gets |
| 2639 | * cleared, if a card is inserted. We have to mask |
| 2640 | * the irq to prevent interrupt storm which will |
| 2641 | * freeze the system. And the REMOVE gets the |
| 2642 | * same situation. |
| 2643 | * |
| 2644 | * More testing are needed here to ensure it works |
| 2645 | * for other platforms though. |
| 2646 | */ |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2647 | host->ier &= ~(SDHCI_INT_CARD_INSERT | |
| 2648 | SDHCI_INT_CARD_REMOVE); |
| 2649 | host->ier |= present ? SDHCI_INT_CARD_REMOVE : |
| 2650 | SDHCI_INT_CARD_INSERT; |
| 2651 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 2652 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2653 | |
| 2654 | sdhci_writel(host, intmask & (SDHCI_INT_CARD_INSERT | |
| 2655 | SDHCI_INT_CARD_REMOVE), SDHCI_INT_STATUS); |
Russell King | 3560db8 | 2014-04-25 12:55:51 +0100 | [diff] [blame] | 2656 | |
| 2657 | host->thread_isr |= intmask & (SDHCI_INT_CARD_INSERT | |
| 2658 | SDHCI_INT_CARD_REMOVE); |
| 2659 | result = IRQ_WAKE_THREAD; |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2660 | } |
| 2661 | |
| 2662 | if (intmask & SDHCI_INT_CMD_MASK) |
Adrian Hunter | 6154139 | 2014-09-24 10:27:27 +0300 | [diff] [blame] | 2663 | sdhci_cmd_irq(host, intmask & SDHCI_INT_CMD_MASK, |
| 2664 | &intmask); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2665 | |
| 2666 | if (intmask & SDHCI_INT_DATA_MASK) |
| 2667 | sdhci_data_irq(host, intmask & SDHCI_INT_DATA_MASK); |
| 2668 | |
| 2669 | if (intmask & SDHCI_INT_BUS_POWER) |
| 2670 | pr_err("%s: Card is consuming too much power!\n", |
| 2671 | mmc_hostname(host->mmc)); |
| 2672 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2673 | if (intmask & SDHCI_INT_CARD_INT) { |
| 2674 | sdhci_enable_sdio_irq_nolock(host, false); |
| 2675 | host->thread_isr |= SDHCI_INT_CARD_INT; |
| 2676 | result = IRQ_WAKE_THREAD; |
| 2677 | } |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2678 | |
| 2679 | intmask &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | |
| 2680 | SDHCI_INT_CMD_MASK | SDHCI_INT_DATA_MASK | |
| 2681 | SDHCI_INT_ERROR | SDHCI_INT_BUS_POWER | |
| 2682 | SDHCI_INT_CARD_INT); |
| 2683 | |
| 2684 | if (intmask) { |
| 2685 | unexpected |= intmask; |
| 2686 | sdhci_writel(host, intmask, SDHCI_INT_STATUS); |
| 2687 | } |
| 2688 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2689 | if (result == IRQ_NONE) |
| 2690 | result = IRQ_HANDLED; |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2691 | |
| 2692 | intmask = sdhci_readl(host, SDHCI_INT_STATUS); |
Russell King | 4100500 | 2014-04-25 12:55:36 +0100 | [diff] [blame] | 2693 | } while (intmask && --max_loops); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2694 | out: |
| 2695 | spin_unlock(&host->lock); |
| 2696 | |
Alexander Stein | 6379b23 | 2012-03-14 09:52:10 +0100 | [diff] [blame] | 2697 | if (unexpected) { |
| 2698 | pr_err("%s: Unexpected interrupt 0x%08x.\n", |
| 2699 | mmc_hostname(host->mmc), unexpected); |
| 2700 | sdhci_dumpregs(host); |
| 2701 | } |
Pierre Ossman | f75979b | 2007-09-04 07:59:18 +0200 | [diff] [blame] | 2702 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2703 | return result; |
| 2704 | } |
| 2705 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2706 | static irqreturn_t sdhci_thread_irq(int irq, void *dev_id) |
| 2707 | { |
| 2708 | struct sdhci_host *host = dev_id; |
| 2709 | unsigned long flags; |
| 2710 | u32 isr; |
| 2711 | |
| 2712 | spin_lock_irqsave(&host->lock, flags); |
| 2713 | isr = host->thread_isr; |
| 2714 | host->thread_isr = 0; |
| 2715 | spin_unlock_irqrestore(&host->lock, flags); |
| 2716 | |
Russell King | 3560db8 | 2014-04-25 12:55:51 +0100 | [diff] [blame] | 2717 | if (isr & (SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE)) { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2718 | struct mmc_host *mmc = host->mmc; |
| 2719 | |
| 2720 | mmc->ops->card_event(mmc); |
| 2721 | mmc_detect_change(mmc, msecs_to_jiffies(200)); |
Russell King | 3560db8 | 2014-04-25 12:55:51 +0100 | [diff] [blame] | 2722 | } |
| 2723 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2724 | if (isr & SDHCI_INT_CARD_INT) { |
| 2725 | sdio_run_irqs(host->mmc); |
| 2726 | |
| 2727 | spin_lock_irqsave(&host->lock, flags); |
| 2728 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) |
| 2729 | sdhci_enable_sdio_irq_nolock(host, true); |
| 2730 | spin_unlock_irqrestore(&host->lock, flags); |
| 2731 | } |
| 2732 | |
| 2733 | return isr ? IRQ_HANDLED : IRQ_NONE; |
| 2734 | } |
| 2735 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2736 | /*****************************************************************************\ |
| 2737 | * * |
| 2738 | * Suspend/resume * |
| 2739 | * * |
| 2740 | \*****************************************************************************/ |
| 2741 | |
| 2742 | #ifdef CONFIG_PM |
Ludovic Desroches | 84d6260 | 2016-05-13 15:16:02 +0200 | [diff] [blame] | 2743 | /* |
| 2744 | * To enable wakeup events, the corresponding events have to be enabled in |
| 2745 | * the Interrupt Status Enable register too. See 'Table 1-6: Wakeup Signal |
| 2746 | * Table' in the SD Host Controller Standard Specification. |
| 2747 | * It is useless to restore SDHCI_INT_ENABLE state in |
| 2748 | * sdhci_disable_irq_wakeups() since it will be set by |
| 2749 | * sdhci_enable_card_detection() or sdhci_init(). |
| 2750 | */ |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2751 | void sdhci_enable_irq_wakeups(struct sdhci_host *host) |
| 2752 | { |
| 2753 | u8 val; |
| 2754 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
| 2755 | | SDHCI_WAKE_ON_INT; |
Ludovic Desroches | 84d6260 | 2016-05-13 15:16:02 +0200 | [diff] [blame] | 2756 | u32 irq_val = SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE | |
| 2757 | SDHCI_INT_CARD_INT; |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2758 | |
| 2759 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); |
| 2760 | val |= mask ; |
| 2761 | /* Avoid fake wake up */ |
Ludovic Desroches | 84d6260 | 2016-05-13 15:16:02 +0200 | [diff] [blame] | 2762 | if (host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) { |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2763 | val &= ~(SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE); |
Ludovic Desroches | 84d6260 | 2016-05-13 15:16:02 +0200 | [diff] [blame] | 2764 | irq_val &= ~(SDHCI_INT_CARD_INSERT | SDHCI_INT_CARD_REMOVE); |
| 2765 | } |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2766 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); |
Ludovic Desroches | 84d6260 | 2016-05-13 15:16:02 +0200 | [diff] [blame] | 2767 | sdhci_writel(host, irq_val, SDHCI_INT_ENABLE); |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2768 | } |
| 2769 | EXPORT_SYMBOL_GPL(sdhci_enable_irq_wakeups); |
| 2770 | |
Fabio Estevam | 0b10f47 | 2014-08-30 14:53:13 -0300 | [diff] [blame] | 2771 | static void sdhci_disable_irq_wakeups(struct sdhci_host *host) |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2772 | { |
| 2773 | u8 val; |
| 2774 | u8 mask = SDHCI_WAKE_ON_INSERT | SDHCI_WAKE_ON_REMOVE |
| 2775 | | SDHCI_WAKE_ON_INT; |
| 2776 | |
| 2777 | val = sdhci_readb(host, SDHCI_WAKE_UP_CONTROL); |
| 2778 | val &= ~mask; |
| 2779 | sdhci_writeb(host, val, SDHCI_WAKE_UP_CONTROL); |
| 2780 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2781 | |
Manuel Lauss | 29495aa | 2011-11-03 11:09:45 +0100 | [diff] [blame] | 2782 | int sdhci_suspend_host(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2783 | { |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 2784 | sdhci_disable_card_detection(host); |
| 2785 | |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 2786 | mmc_retune_timer_stop(host->mmc); |
| 2787 | mmc_retune_needed(host->mmc); |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 2788 | |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2789 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2790 | host->ier = 0; |
| 2791 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
| 2792 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Kevin Liu | ad080d7 | 2013-01-05 17:21:33 +0800 | [diff] [blame] | 2793 | free_irq(host->irq, host); |
| 2794 | } else { |
| 2795 | sdhci_enable_irq_wakeups(host); |
| 2796 | enable_irq_wake(host->irq); |
| 2797 | } |
Ulf Hansson | 4ee14ec | 2013-09-25 14:15:24 +0200 | [diff] [blame] | 2798 | return 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2799 | } |
| 2800 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2801 | EXPORT_SYMBOL_GPL(sdhci_suspend_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2802 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2803 | int sdhci_resume_host(struct sdhci_host *host) |
| 2804 | { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2805 | struct mmc_host *mmc = host->mmc; |
Ulf Hansson | 4ee14ec | 2013-09-25 14:15:24 +0200 | [diff] [blame] | 2806 | int ret = 0; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2807 | |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 2808 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2809 | if (host->ops->enable_dma) |
| 2810 | host->ops->enable_dma(host); |
| 2811 | } |
| 2812 | |
Adrian Hunter | 6308d29 | 2012-02-07 14:48:54 +0200 | [diff] [blame] | 2813 | if ((host->mmc->pm_flags & MMC_PM_KEEP_POWER) && |
| 2814 | (host->quirks2 & SDHCI_QUIRK2_HOST_OFF_CARD_ON)) { |
| 2815 | /* Card keeps power but host controller does not */ |
| 2816 | sdhci_init(host, 0); |
| 2817 | host->pwr = 0; |
| 2818 | host->clock = 0; |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2819 | mmc->ops->set_ios(mmc, &mmc->ios); |
Adrian Hunter | 6308d29 | 2012-02-07 14:48:54 +0200 | [diff] [blame] | 2820 | } else { |
| 2821 | sdhci_init(host, (host->mmc->pm_flags & MMC_PM_KEEP_POWER)); |
| 2822 | mmiowb(); |
| 2823 | } |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2824 | |
Haibo Chen | 14a7b4164 | 2015-09-15 18:32:58 +0800 | [diff] [blame] | 2825 | if (!device_may_wakeup(mmc_dev(host->mmc))) { |
| 2826 | ret = request_threaded_irq(host->irq, sdhci_irq, |
| 2827 | sdhci_thread_irq, IRQF_SHARED, |
| 2828 | mmc_hostname(host->mmc), host); |
| 2829 | if (ret) |
| 2830 | return ret; |
| 2831 | } else { |
| 2832 | sdhci_disable_irq_wakeups(host); |
| 2833 | disable_irq_wake(host->irq); |
| 2834 | } |
| 2835 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 2836 | sdhci_enable_card_detection(host); |
| 2837 | |
Nicolas Pitre | 2f4cbb3 | 2010-03-05 13:43:32 -0800 | [diff] [blame] | 2838 | return ret; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2839 | } |
| 2840 | |
| 2841 | EXPORT_SYMBOL_GPL(sdhci_resume_host); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2842 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2843 | int sdhci_runtime_suspend_host(struct sdhci_host *host) |
| 2844 | { |
| 2845 | unsigned long flags; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2846 | |
Adrian Hunter | 66c39dfc | 2015-05-07 13:10:21 +0300 | [diff] [blame] | 2847 | mmc_retune_timer_stop(host->mmc); |
| 2848 | mmc_retune_needed(host->mmc); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2849 | |
| 2850 | spin_lock_irqsave(&host->lock, flags); |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 2851 | host->ier &= SDHCI_INT_CARD_INT; |
| 2852 | sdhci_writel(host, host->ier, SDHCI_INT_ENABLE); |
| 2853 | sdhci_writel(host, host->ier, SDHCI_SIGNAL_ENABLE); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2854 | spin_unlock_irqrestore(&host->lock, flags); |
| 2855 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 2856 | synchronize_hardirq(host->irq); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2857 | |
| 2858 | spin_lock_irqsave(&host->lock, flags); |
| 2859 | host->runtime_suspended = true; |
| 2860 | spin_unlock_irqrestore(&host->lock, flags); |
| 2861 | |
Markus Pargmann | 8a125ba | 2014-06-04 15:24:29 +0200 | [diff] [blame] | 2862 | return 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2863 | } |
| 2864 | EXPORT_SYMBOL_GPL(sdhci_runtime_suspend_host); |
| 2865 | |
| 2866 | int sdhci_runtime_resume_host(struct sdhci_host *host) |
| 2867 | { |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2868 | struct mmc_host *mmc = host->mmc; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2869 | unsigned long flags; |
Markus Pargmann | 8a125ba | 2014-06-04 15:24:29 +0200 | [diff] [blame] | 2870 | int host_flags = host->flags; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2871 | |
| 2872 | if (host_flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
| 2873 | if (host->ops->enable_dma) |
| 2874 | host->ops->enable_dma(host); |
| 2875 | } |
| 2876 | |
| 2877 | sdhci_init(host, 0); |
| 2878 | |
| 2879 | /* Force clock and power re-program */ |
| 2880 | host->pwr = 0; |
| 2881 | host->clock = 0; |
Adrian Hunter | d3940f2 | 2016-06-29 16:24:14 +0300 | [diff] [blame] | 2882 | mmc->ops->start_signal_voltage_switch(mmc, &mmc->ios); |
| 2883 | mmc->ops->set_ios(mmc, &mmc->ios); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2884 | |
Kevin Liu | 5298338 | 2013-01-31 11:31:37 +0800 | [diff] [blame] | 2885 | if ((host_flags & SDHCI_PV_ENABLED) && |
| 2886 | !(host->quirks2 & SDHCI_QUIRK2_PRESET_VALUE_BROKEN)) { |
| 2887 | spin_lock_irqsave(&host->lock, flags); |
| 2888 | sdhci_enable_preset_value(host, true); |
| 2889 | spin_unlock_irqrestore(&host->lock, flags); |
| 2890 | } |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2891 | |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2892 | spin_lock_irqsave(&host->lock, flags); |
| 2893 | |
| 2894 | host->runtime_suspended = false; |
| 2895 | |
| 2896 | /* Enable SDIO IRQ */ |
Russell King | ef10433 | 2014-04-25 12:55:41 +0100 | [diff] [blame] | 2897 | if (host->flags & SDHCI_SDIO_IRQ_ENABLED) |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2898 | sdhci_enable_sdio_irq_nolock(host, true); |
| 2899 | |
| 2900 | /* Enable Card Detection */ |
| 2901 | sdhci_enable_card_detection(host); |
| 2902 | |
| 2903 | spin_unlock_irqrestore(&host->lock, flags); |
| 2904 | |
Markus Pargmann | 8a125ba | 2014-06-04 15:24:29 +0200 | [diff] [blame] | 2905 | return 0; |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2906 | } |
| 2907 | EXPORT_SYMBOL_GPL(sdhci_runtime_resume_host); |
| 2908 | |
Rafael J. Wysocki | 162d6f9 | 2014-12-05 03:05:33 +0100 | [diff] [blame] | 2909 | #endif /* CONFIG_PM */ |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 2910 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2911 | /*****************************************************************************\ |
| 2912 | * * |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2913 | * Device allocation/registration * |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2914 | * * |
| 2915 | \*****************************************************************************/ |
| 2916 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2917 | struct sdhci_host *sdhci_alloc_host(struct device *dev, |
| 2918 | size_t priv_size) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2919 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2920 | struct mmc_host *mmc; |
| 2921 | struct sdhci_host *host; |
| 2922 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2923 | WARN_ON(dev == NULL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2924 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2925 | mmc = mmc_alloc_host(sizeof(struct sdhci_host) + priv_size, dev); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2926 | if (!mmc) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2927 | return ERR_PTR(-ENOMEM); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2928 | |
| 2929 | host = mmc_priv(mmc); |
| 2930 | host->mmc = mmc; |
Adrian Hunter | bf60e59 | 2016-02-09 16:12:35 +0200 | [diff] [blame] | 2931 | host->mmc_host_ops = sdhci_ops; |
| 2932 | mmc->ops = &host->mmc_host_ops; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2933 | |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 2934 | host->flags = SDHCI_SIGNALING_330; |
| 2935 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2936 | return host; |
| 2937 | } |
Pierre Ossman | 8a4da14 | 2006-10-04 02:15:40 -0700 | [diff] [blame] | 2938 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 2939 | EXPORT_SYMBOL_GPL(sdhci_alloc_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 2940 | |
Alexandre Courbot | 7b91369 | 2016-03-07 11:07:55 +0900 | [diff] [blame] | 2941 | static int sdhci_set_dma_mask(struct sdhci_host *host) |
| 2942 | { |
| 2943 | struct mmc_host *mmc = host->mmc; |
| 2944 | struct device *dev = mmc_dev(mmc); |
| 2945 | int ret = -EINVAL; |
| 2946 | |
| 2947 | if (host->quirks2 & SDHCI_QUIRK2_BROKEN_64_BIT_DMA) |
| 2948 | host->flags &= ~SDHCI_USE_64_BIT_DMA; |
| 2949 | |
| 2950 | /* Try 64-bit mask if hardware is capable of it */ |
| 2951 | if (host->flags & SDHCI_USE_64_BIT_DMA) { |
| 2952 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64)); |
| 2953 | if (ret) { |
| 2954 | pr_warn("%s: Failed to set 64-bit DMA mask.\n", |
| 2955 | mmc_hostname(mmc)); |
| 2956 | host->flags &= ~SDHCI_USE_64_BIT_DMA; |
| 2957 | } |
| 2958 | } |
| 2959 | |
| 2960 | /* 32-bit mask as default & fallback */ |
| 2961 | if (ret) { |
| 2962 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
| 2963 | if (ret) |
| 2964 | pr_warn("%s: Failed to set 32-bit DMA mask.\n", |
| 2965 | mmc_hostname(mmc)); |
| 2966 | } |
| 2967 | |
| 2968 | return ret; |
| 2969 | } |
| 2970 | |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 2971 | void __sdhci_read_caps(struct sdhci_host *host, u16 *ver, u32 *caps, u32 *caps1) |
| 2972 | { |
| 2973 | u16 v; |
| 2974 | |
| 2975 | if (host->read_caps) |
| 2976 | return; |
| 2977 | |
| 2978 | host->read_caps = true; |
| 2979 | |
| 2980 | if (debug_quirks) |
| 2981 | host->quirks = debug_quirks; |
| 2982 | |
| 2983 | if (debug_quirks2) |
| 2984 | host->quirks2 = debug_quirks2; |
| 2985 | |
| 2986 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
| 2987 | |
| 2988 | v = ver ? *ver : sdhci_readw(host, SDHCI_HOST_VERSION); |
| 2989 | host->version = (v & SDHCI_SPEC_VER_MASK) >> SDHCI_SPEC_VER_SHIFT; |
| 2990 | |
| 2991 | if (host->quirks & SDHCI_QUIRK_MISSING_CAPS) |
| 2992 | return; |
| 2993 | |
| 2994 | host->caps = caps ? *caps : sdhci_readl(host, SDHCI_CAPABILITIES); |
| 2995 | |
| 2996 | if (host->version < SDHCI_SPEC_300) |
| 2997 | return; |
| 2998 | |
| 2999 | host->caps1 = caps1 ? *caps1 : sdhci_readl(host, SDHCI_CAPABILITIES_1); |
| 3000 | } |
| 3001 | EXPORT_SYMBOL_GPL(__sdhci_read_caps); |
| 3002 | |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 3003 | int sdhci_setup_host(struct sdhci_host *host) |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3004 | { |
| 3005 | struct mmc_host *mmc; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3006 | u32 max_current_caps; |
| 3007 | unsigned int ocr_avail; |
Adrian Hunter | f5fa92e | 2014-09-24 10:27:32 +0300 | [diff] [blame] | 3008 | unsigned int override_timeout_clk; |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 3009 | u32 max_clk; |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3010 | int ret; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3011 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3012 | WARN_ON(host == NULL); |
| 3013 | if (host == NULL) |
| 3014 | return -EINVAL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3015 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3016 | mmc = host->mmc; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3017 | |
Adrian Hunter | 6132a3b | 2016-06-29 16:24:18 +0300 | [diff] [blame] | 3018 | sdhci_read_caps(host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3019 | |
Adrian Hunter | f5fa92e | 2014-09-24 10:27:32 +0300 | [diff] [blame] | 3020 | override_timeout_clk = host->timeout_clk; |
| 3021 | |
Zhangfei Gao | 85105c5 | 2010-08-06 07:10:01 +0800 | [diff] [blame] | 3022 | if (host->version > SDHCI_SPEC_300) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 3023 | pr_err("%s: Unknown controller version (%d). You may experience problems.\n", |
| 3024 | mmc_hostname(mmc), host->version); |
Pierre Ossman | 4a96550 | 2006-06-30 02:22:29 -0700 | [diff] [blame] | 3025 | } |
| 3026 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3027 | if (host->quirks & SDHCI_QUIRK_FORCE_DMA) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3028 | host->flags |= SDHCI_USE_SDMA; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3029 | else if (!(host->caps & SDHCI_CAN_DO_SDMA)) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3030 | DBG("Controller doesn't have SDMA capability\n"); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3031 | else |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3032 | host->flags |= SDHCI_USE_SDMA; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3033 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3034 | if ((host->quirks & SDHCI_QUIRK_BROKEN_DMA) && |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3035 | (host->flags & SDHCI_USE_SDMA)) { |
Rolf Eike Beer | cee687c | 2007-11-02 15:22:30 +0100 | [diff] [blame] | 3036 | DBG("Disabling DMA as it is marked broken\n"); |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3037 | host->flags &= ~SDHCI_USE_SDMA; |
Feng Tang | 7c168e3 | 2007-09-30 12:44:18 +0200 | [diff] [blame] | 3038 | } |
| 3039 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3040 | if ((host->version >= SDHCI_SPEC_200) && |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3041 | (host->caps & SDHCI_CAN_DO_ADMA2)) |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3042 | host->flags |= SDHCI_USE_ADMA; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3043 | |
| 3044 | if ((host->quirks & SDHCI_QUIRK_BROKEN_ADMA) && |
| 3045 | (host->flags & SDHCI_USE_ADMA)) { |
| 3046 | DBG("Disabling ADMA as it is marked broken\n"); |
| 3047 | host->flags &= ~SDHCI_USE_ADMA; |
| 3048 | } |
| 3049 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3050 | /* |
| 3051 | * It is assumed that a 64-bit capable device has set a 64-bit DMA mask |
| 3052 | * and *must* do 64-bit DMA. A driver has the opportunity to change |
| 3053 | * that during the first call to ->enable_dma(). Similarly |
| 3054 | * SDHCI_QUIRK2_BROKEN_64_BIT_DMA must be left to the drivers to |
| 3055 | * implement. |
| 3056 | */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3057 | if (host->caps & SDHCI_CAN_64BIT) |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3058 | host->flags |= SDHCI_USE_64_BIT_DMA; |
| 3059 | |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3060 | if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA)) { |
Alexandre Courbot | 7b91369 | 2016-03-07 11:07:55 +0900 | [diff] [blame] | 3061 | ret = sdhci_set_dma_mask(host); |
| 3062 | |
| 3063 | if (!ret && host->ops->enable_dma) |
| 3064 | ret = host->ops->enable_dma(host); |
| 3065 | |
| 3066 | if (ret) { |
| 3067 | pr_warn("%s: No suitable DMA available - falling back to PIO\n", |
| 3068 | mmc_hostname(mmc)); |
| 3069 | host->flags &= ~(SDHCI_USE_SDMA | SDHCI_USE_ADMA); |
| 3070 | |
| 3071 | ret = 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3072 | } |
| 3073 | } |
| 3074 | |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3075 | /* SDMA does not support 64-bit DMA */ |
| 3076 | if (host->flags & SDHCI_USE_64_BIT_DMA) |
| 3077 | host->flags &= ~SDHCI_USE_SDMA; |
| 3078 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3079 | if (host->flags & SDHCI_USE_ADMA) { |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3080 | dma_addr_t dma; |
| 3081 | void *buf; |
| 3082 | |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3083 | /* |
Adrian Hunter | 76fe379 | 2014-11-04 12:42:42 +0200 | [diff] [blame] | 3084 | * The DMA descriptor table size is calculated as the maximum |
| 3085 | * number of segments times 2, to allow for an alignment |
| 3086 | * descriptor for each segment, plus 1 for a nop end descriptor, |
| 3087 | * all multipled by the descriptor size. |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3088 | */ |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3089 | if (host->flags & SDHCI_USE_64_BIT_DMA) { |
| 3090 | host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * |
| 3091 | SDHCI_ADMA2_64_DESC_SZ; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3092 | host->desc_sz = SDHCI_ADMA2_64_DESC_SZ; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3093 | } else { |
| 3094 | host->adma_table_sz = (SDHCI_MAX_SEGS * 2 + 1) * |
| 3095 | SDHCI_ADMA2_32_DESC_SZ; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3096 | host->desc_sz = SDHCI_ADMA2_32_DESC_SZ; |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3097 | } |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3098 | |
Adrian Hunter | 04a5ae6 | 2015-11-26 14:00:49 +0200 | [diff] [blame] | 3099 | host->align_buffer_sz = SDHCI_MAX_SEGS * SDHCI_ADMA2_ALIGN; |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3100 | buf = dma_alloc_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 3101 | host->adma_table_sz, &dma, GFP_KERNEL); |
| 3102 | if (!buf) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 3103 | pr_warn("%s: Unable to allocate ADMA buffers - falling back to standard DMA\n", |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3104 | mmc_hostname(mmc)); |
| 3105 | host->flags &= ~SDHCI_USE_ADMA; |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3106 | } else if ((dma + host->align_buffer_sz) & |
| 3107 | (SDHCI_ADMA2_DESC_ALIGN - 1)) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 3108 | pr_warn("%s: unable to allocate aligned ADMA descriptor\n", |
| 3109 | mmc_hostname(mmc)); |
Russell King | d1e49f7 | 2014-04-25 12:58:34 +0100 | [diff] [blame] | 3110 | host->flags &= ~SDHCI_USE_ADMA; |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3111 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 3112 | host->adma_table_sz, buf, dma); |
| 3113 | } else { |
| 3114 | host->align_buffer = buf; |
| 3115 | host->align_addr = dma; |
Russell King | edd63fc | 2016-01-26 13:39:50 +0000 | [diff] [blame] | 3116 | |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3117 | host->adma_table = buf + host->align_buffer_sz; |
| 3118 | host->adma_addr = dma + host->align_buffer_sz; |
| 3119 | } |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3120 | } |
| 3121 | |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 3122 | /* |
| 3123 | * If we use DMA, then it's up to the caller to set the DMA |
| 3124 | * mask, but PIO does not need the hw shim so we set a new |
| 3125 | * mask here in that case. |
| 3126 | */ |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3127 | if (!(host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA))) { |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 3128 | host->dma_mask = DMA_BIT_MASK(64); |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 3129 | mmc_dev(mmc)->dma_mask = &host->dma_mask; |
Pierre Ossman | 7659150 | 2008-07-21 00:32:11 +0200 | [diff] [blame] | 3130 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3131 | |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 3132 | if (host->version >= SDHCI_SPEC_300) |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3133 | host->max_clk = (host->caps & SDHCI_CLOCK_V3_BASE_MASK) |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 3134 | >> SDHCI_CLOCK_BASE_SHIFT; |
| 3135 | else |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3136 | host->max_clk = (host->caps & SDHCI_CLOCK_BASE_MASK) |
Zhangfei Gao | c4687d5 | 2010-08-20 14:02:36 -0400 | [diff] [blame] | 3137 | >> SDHCI_CLOCK_BASE_SHIFT; |
| 3138 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3139 | host->max_clk *= 1000000; |
Anton Vorontsov | f27f47e | 2010-05-26 14:41:53 -0700 | [diff] [blame] | 3140 | if (host->max_clk == 0 || host->quirks & |
| 3141 | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN) { |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 3142 | if (!host->ops->get_max_clock) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 3143 | pr_err("%s: Hardware doesn't specify base clock frequency.\n", |
| 3144 | mmc_hostname(mmc)); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3145 | ret = -ENODEV; |
| 3146 | goto undma; |
Ben Dooks | 4240ff0 | 2009-03-17 00:13:57 +0300 | [diff] [blame] | 3147 | } |
| 3148 | host->max_clk = host->ops->get_max_clock(host); |
| 3149 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3150 | |
| 3151 | /* |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 3152 | * In case of Host Controller v3.00, find out whether clock |
| 3153 | * multiplier is supported. |
| 3154 | */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3155 | host->clk_mul = (host->caps1 & SDHCI_CLOCK_MUL_MASK) >> |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 3156 | SDHCI_CLOCK_MUL_SHIFT; |
| 3157 | |
| 3158 | /* |
| 3159 | * In case the value in Clock Multiplier is 0, then programmable |
| 3160 | * clock mode is not supported, otherwise the actual clock |
| 3161 | * multiplier is one more than the value of Clock Multiplier |
| 3162 | * in the Capabilities Register. |
| 3163 | */ |
| 3164 | if (host->clk_mul) |
| 3165 | host->clk_mul += 1; |
| 3166 | |
| 3167 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3168 | * Set host parameters. |
| 3169 | */ |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 3170 | max_clk = host->max_clk; |
| 3171 | |
Marek Szyprowski | ce5f036 | 2010-08-10 18:01:56 -0700 | [diff] [blame] | 3172 | if (host->ops->get_min_clock) |
Anton Vorontsov | a9e58f2 | 2009-07-29 15:04:16 -0700 | [diff] [blame] | 3173 | mmc->f_min = host->ops->get_min_clock(host); |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 3174 | else if (host->version >= SDHCI_SPEC_300) { |
| 3175 | if (host->clk_mul) { |
| 3176 | mmc->f_min = (host->max_clk * host->clk_mul) / 1024; |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 3177 | max_clk = host->max_clk * host->clk_mul; |
Arindam Nath | c3ed387 | 2011-05-05 12:19:06 +0530 | [diff] [blame] | 3178 | } else |
| 3179 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_300; |
| 3180 | } else |
Zhangfei Gao | 0397526 | 2010-09-20 15:15:18 -0400 | [diff] [blame] | 3181 | mmc->f_min = host->max_clk / SDHCI_MAX_DIV_SPEC_200; |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 3182 | |
Adrian Hunter | d310ae4 | 2016-04-12 14:25:07 +0300 | [diff] [blame] | 3183 | if (!mmc->f_max || mmc->f_max > max_clk) |
Dong Aisheng | 5924175 | 2015-07-22 20:53:07 +0800 | [diff] [blame] | 3184 | mmc->f_max = max_clk; |
| 3185 | |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3186 | if (!(host->quirks & SDHCI_QUIRK_DATA_TIMEOUT_USES_SDCLK)) { |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3187 | host->timeout_clk = (host->caps & SDHCI_TIMEOUT_CLK_MASK) >> |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3188 | SDHCI_TIMEOUT_CLK_SHIFT; |
| 3189 | if (host->timeout_clk == 0) { |
| 3190 | if (host->ops->get_timeout_clock) { |
| 3191 | host->timeout_clk = |
| 3192 | host->ops->get_timeout_clock(host); |
| 3193 | } else { |
| 3194 | pr_err("%s: Hardware doesn't specify timeout clock frequency.\n", |
| 3195 | mmc_hostname(mmc)); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3196 | ret = -ENODEV; |
| 3197 | goto undma; |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3198 | } |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 3199 | } |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 3200 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3201 | if (host->caps & SDHCI_TIMEOUT_CLK_UNIT) |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3202 | host->timeout_clk *= 1000; |
Andy Shevchenko | 272308c | 2011-08-03 18:36:00 +0300 | [diff] [blame] | 3203 | |
Adrian Hunter | 9951362 | 2016-03-07 13:33:55 +0200 | [diff] [blame] | 3204 | if (override_timeout_clk) |
| 3205 | host->timeout_clk = override_timeout_clk; |
| 3206 | |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3207 | mmc->max_busy_timeout = host->ops->get_max_timeout_count ? |
Aisheng Dong | a6ff5ae | 2014-08-27 15:26:27 +0800 | [diff] [blame] | 3208 | host->ops->get_max_timeout_count(host) : 1 << 27; |
Aisheng Dong | 28aab05 | 2014-08-27 15:26:31 +0800 | [diff] [blame] | 3209 | mmc->max_busy_timeout /= host->timeout_clk; |
| 3210 | } |
Adrian Hunter | 58d1246 | 2011-06-28 17:16:03 +0300 | [diff] [blame] | 3211 | |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 3212 | mmc->caps |= MMC_CAP_SDIO_IRQ | MMC_CAP_ERASE | MMC_CAP_CMD23; |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3213 | mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; |
Andrei Warkentin | e89d456 | 2011-05-23 15:06:37 -0500 | [diff] [blame] | 3214 | |
| 3215 | if (host->quirks & SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12) |
| 3216 | host->flags |= SDHCI_AUTO_CMD12; |
Anton Vorontsov | 5fe23c7 | 2009-06-18 00:14:08 +0400 | [diff] [blame] | 3217 | |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 3218 | /* Auto-CMD23 stuff only works in ADMA or PIO. */ |
Andrei Warkentin | 4f3d3e9 | 2011-05-25 10:42:50 -0400 | [diff] [blame] | 3219 | if ((host->version >= SDHCI_SPEC_300) && |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 3220 | ((host->flags & SDHCI_USE_ADMA) || |
Scott Branden | 3bfa6f0 | 2015-02-09 16:06:28 -0800 | [diff] [blame] | 3221 | !(host->flags & SDHCI_USE_SDMA)) && |
| 3222 | !(host->quirks2 & SDHCI_QUIRK2_ACMD23_BROKEN)) { |
Andrei Warkentin | 8edf6371 | 2011-05-23 15:06:39 -0500 | [diff] [blame] | 3223 | host->flags |= SDHCI_AUTO_CMD23; |
| 3224 | DBG("%s: Auto-CMD23 available\n", mmc_hostname(mmc)); |
| 3225 | } else { |
| 3226 | DBG("%s: Auto-CMD23 unavailable\n", mmc_hostname(mmc)); |
| 3227 | } |
| 3228 | |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 3229 | /* |
| 3230 | * A controller may support 8-bit width, but the board itself |
| 3231 | * might not have the pins brought out. Boards that support |
| 3232 | * 8-bit width must set "mmc->caps |= MMC_CAP_8_BIT_DATA;" in |
| 3233 | * their platform code before calling sdhci_add_host(), and we |
| 3234 | * won't assume 8-bit width for hosts without that CAP. |
| 3235 | */ |
Anton Vorontsov | 5fe23c7 | 2009-06-18 00:14:08 +0400 | [diff] [blame] | 3236 | if (!(host->quirks & SDHCI_QUIRK_FORCE_1_BIT_DATA)) |
Philip Rakity | 15ec446 | 2010-11-19 16:48:39 -0500 | [diff] [blame] | 3237 | mmc->caps |= MMC_CAP_4_BIT_DATA; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3238 | |
Jerry Huang | 63ef5d8 | 2012-10-25 13:47:19 +0800 | [diff] [blame] | 3239 | if (host->quirks2 & SDHCI_QUIRK2_HOST_NO_CMD23) |
| 3240 | mmc->caps &= ~MMC_CAP_CMD23; |
| 3241 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3242 | if (host->caps & SDHCI_CAN_DO_HISPD) |
Zhangfei Gao | a29e7e1 | 2010-08-16 21:15:32 -0400 | [diff] [blame] | 3243 | mmc->caps |= MMC_CAP_SD_HIGHSPEED | MMC_CAP_MMC_HIGHSPEED; |
Pierre Ossman | cd9277c | 2007-02-18 12:07:47 +0100 | [diff] [blame] | 3244 | |
Jaehoon Chung | 176d1ed | 2010-09-27 09:42:20 +0100 | [diff] [blame] | 3245 | if ((host->quirks & SDHCI_QUIRK_BROKEN_CARD_DETECTION) && |
Jaehoon Chung | 860951c | 2016-06-21 10:13:26 +0900 | [diff] [blame] | 3246 | mmc_card_is_removable(mmc) && |
Arnd Bergmann | 287980e | 2016-05-27 23:23:25 +0200 | [diff] [blame] | 3247 | mmc_gpio_get_cd(host->mmc) < 0) |
Anton Vorontsov | 68d1fb7 | 2009-03-17 00:13:52 +0300 | [diff] [blame] | 3248 | mmc->caps |= MMC_CAP_NEEDS_POLL; |
| 3249 | |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3250 | /* If there are external regulators, get them */ |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3251 | ret = mmc_regulator_get_supply(mmc); |
| 3252 | if (ret == -EPROBE_DEFER) |
| 3253 | goto undma; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3254 | |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 3255 | /* If vqmmc regulator and no 1.8V signalling, then there's no UHS */ |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3256 | if (!IS_ERR(mmc->supply.vqmmc)) { |
| 3257 | ret = regulator_enable(mmc->supply.vqmmc); |
| 3258 | if (!regulator_is_supported_voltage(mmc->supply.vqmmc, 1700000, |
| 3259 | 1950000)) |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3260 | host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | |
| 3261 | SDHCI_SUPPORT_SDR50 | |
| 3262 | SDHCI_SUPPORT_DDR50); |
Chris Ball | a3361ab | 2013-03-11 17:51:53 -0400 | [diff] [blame] | 3263 | if (ret) { |
| 3264 | pr_warn("%s: Failed to enable vqmmc regulator: %d\n", |
| 3265 | mmc_hostname(mmc), ret); |
Adrian Hunter | 4bb7431 | 2014-11-06 15:19:04 +0200 | [diff] [blame] | 3266 | mmc->supply.vqmmc = ERR_PTR(-EINVAL); |
Chris Ball | a3361ab | 2013-03-11 17:51:53 -0400 | [diff] [blame] | 3267 | } |
Kevin Liu | 8363c37 | 2012-11-17 17:55:51 -0500 | [diff] [blame] | 3268 | } |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 3269 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3270 | if (host->quirks2 & SDHCI_QUIRK2_NO_1_8_V) { |
| 3271 | host->caps1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | |
| 3272 | SDHCI_SUPPORT_DDR50); |
| 3273 | } |
Daniel Drake | 6a66180 | 2012-11-25 13:01:19 -0500 | [diff] [blame] | 3274 | |
Al Cooper | 4188bba | 2012-03-16 15:54:17 -0400 | [diff] [blame] | 3275 | /* Any UHS-I mode in caps implies SDR12 and SDR25 support. */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3276 | if (host->caps1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | |
| 3277 | SDHCI_SUPPORT_DDR50)) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3278 | mmc->caps |= MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25; |
| 3279 | |
| 3280 | /* SDR104 supports also implies SDR50 support */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3281 | if (host->caps1 & SDHCI_SUPPORT_SDR104) { |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3282 | mmc->caps |= MMC_CAP_UHS_SDR104 | MMC_CAP_UHS_SDR50; |
Giuseppe CAVALLARO | 156e14b | 2013-06-12 08:16:38 +0200 | [diff] [blame] | 3283 | /* SD3.0: SDR104 is supported so (for eMMC) the caps2 |
| 3284 | * field can be promoted to support HS200. |
| 3285 | */ |
Adrian Hunter | 549c0b1 | 2014-11-06 15:19:05 +0200 | [diff] [blame] | 3286 | if (!(host->quirks2 & SDHCI_QUIRK2_BROKEN_HS200)) |
David Cohen | 13868bf | 2013-10-29 10:58:26 -0700 | [diff] [blame] | 3287 | mmc->caps2 |= MMC_CAP2_HS200; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3288 | } else if (host->caps1 & SDHCI_SUPPORT_SDR50) { |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3289 | mmc->caps |= MMC_CAP_UHS_SDR50; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3290 | } |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3291 | |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 3292 | if (host->quirks2 & SDHCI_QUIRK2_CAPS_BIT63_FOR_HS400 && |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3293 | (host->caps1 & SDHCI_SUPPORT_HS400)) |
Adrian Hunter | e9fb05d | 2014-11-06 15:19:06 +0200 | [diff] [blame] | 3294 | mmc->caps2 |= MMC_CAP2_HS400; |
| 3295 | |
Adrian Hunter | 549c0b1 | 2014-11-06 15:19:05 +0200 | [diff] [blame] | 3296 | if ((mmc->caps2 & MMC_CAP2_HSX00_1_2V) && |
| 3297 | (IS_ERR(mmc->supply.vqmmc) || |
| 3298 | !regulator_is_supported_voltage(mmc->supply.vqmmc, 1100000, |
| 3299 | 1300000))) |
| 3300 | mmc->caps2 &= ~MMC_CAP2_HSX00_1_2V; |
| 3301 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3302 | if ((host->caps1 & SDHCI_SUPPORT_DDR50) && |
| 3303 | !(host->quirks2 & SDHCI_QUIRK2_BROKEN_DDR50)) |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3304 | mmc->caps |= MMC_CAP_UHS_DDR50; |
| 3305 | |
Girish K S | 069c9f1 | 2012-01-06 09:56:39 +0530 | [diff] [blame] | 3306 | /* Does the host need tuning for SDR50? */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3307 | if (host->caps1 & SDHCI_USE_SDR50_TUNING) |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 3308 | host->flags |= SDHCI_SDR50_NEEDS_TUNING; |
| 3309 | |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 3310 | /* Driver Type(s) (A, C, D) supported by the host */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3311 | if (host->caps1 & SDHCI_DRIVER_TYPE_A) |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 3312 | mmc->caps |= MMC_CAP_DRIVER_TYPE_A; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3313 | if (host->caps1 & SDHCI_DRIVER_TYPE_C) |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 3314 | mmc->caps |= MMC_CAP_DRIVER_TYPE_C; |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3315 | if (host->caps1 & SDHCI_DRIVER_TYPE_D) |
Arindam Nath | d6d50a1 | 2011-05-05 12:18:59 +0530 | [diff] [blame] | 3316 | mmc->caps |= MMC_CAP_DRIVER_TYPE_D; |
| 3317 | |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 3318 | /* Initial value for re-tuning timer count */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3319 | host->tuning_count = (host->caps1 & SDHCI_RETUNING_TIMER_COUNT_MASK) >> |
| 3320 | SDHCI_RETUNING_TIMER_COUNT_SHIFT; |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 3321 | |
| 3322 | /* |
| 3323 | * In case Re-tuning Timer is not disabled, the actual value of |
| 3324 | * re-tuning timer will be 2 ^ (n - 1). |
| 3325 | */ |
| 3326 | if (host->tuning_count) |
| 3327 | host->tuning_count = 1 << (host->tuning_count - 1); |
| 3328 | |
| 3329 | /* Re-tuning mode supported by the Host Controller */ |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3330 | host->tuning_mode = (host->caps1 & SDHCI_RETUNING_MODE_MASK) >> |
Arindam Nath | cf2b5ee | 2011-05-05 12:19:07 +0530 | [diff] [blame] | 3331 | SDHCI_RETUNING_MODE_SHIFT; |
| 3332 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3333 | ocr_avail = 0; |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 3334 | |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3335 | /* |
| 3336 | * According to SD Host Controller spec v3.00, if the Host System |
| 3337 | * can afford more than 150mA, Host Driver should set XPC to 1. Also |
| 3338 | * the value is meaningful only if Voltage Support in the Capabilities |
| 3339 | * register is set. The actual current value is 4 times the register |
| 3340 | * value. |
| 3341 | */ |
| 3342 | max_current_caps = sdhci_readl(host, SDHCI_MAX_CURRENT); |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3343 | if (!max_current_caps && !IS_ERR(mmc->supply.vmmc)) { |
Chuanxiao.Dong | ae90603 | 2014-08-01 14:00:13 +0800 | [diff] [blame] | 3344 | int curr = regulator_get_current_limit(mmc->supply.vmmc); |
Philip Rakity | bad37e1 | 2012-05-27 18:36:44 -0700 | [diff] [blame] | 3345 | if (curr > 0) { |
| 3346 | |
| 3347 | /* convert to SDHCI_MAX_CURRENT format */ |
| 3348 | curr = curr/1000; /* convert to mA */ |
| 3349 | curr = curr/SDHCI_MAX_CURRENT_MULTIPLIER; |
| 3350 | |
| 3351 | curr = min_t(u32, curr, SDHCI_MAX_CURRENT_LIMIT); |
| 3352 | max_current_caps = |
| 3353 | (curr << SDHCI_MAX_CURRENT_330_SHIFT) | |
| 3354 | (curr << SDHCI_MAX_CURRENT_300_SHIFT) | |
| 3355 | (curr << SDHCI_MAX_CURRENT_180_SHIFT); |
| 3356 | } |
| 3357 | } |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3358 | |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3359 | if (host->caps & SDHCI_CAN_VDD_330) { |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3360 | ocr_avail |= MMC_VDD_32_33 | MMC_VDD_33_34; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3361 | |
Aaron Lu | 55c4665 | 2012-07-04 13:31:48 +0800 | [diff] [blame] | 3362 | mmc->max_current_330 = ((max_current_caps & |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3363 | SDHCI_MAX_CURRENT_330_MASK) >> |
| 3364 | SDHCI_MAX_CURRENT_330_SHIFT) * |
| 3365 | SDHCI_MAX_CURRENT_MULTIPLIER; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3366 | } |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3367 | if (host->caps & SDHCI_CAN_VDD_300) { |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3368 | ocr_avail |= MMC_VDD_29_30 | MMC_VDD_30_31; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3369 | |
Aaron Lu | 55c4665 | 2012-07-04 13:31:48 +0800 | [diff] [blame] | 3370 | mmc->max_current_300 = ((max_current_caps & |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3371 | SDHCI_MAX_CURRENT_300_MASK) >> |
| 3372 | SDHCI_MAX_CURRENT_300_SHIFT) * |
| 3373 | SDHCI_MAX_CURRENT_MULTIPLIER; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3374 | } |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3375 | if (host->caps & SDHCI_CAN_VDD_180) { |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3376 | ocr_avail |= MMC_VDD_165_195; |
| 3377 | |
Aaron Lu | 55c4665 | 2012-07-04 13:31:48 +0800 | [diff] [blame] | 3378 | mmc->max_current_180 = ((max_current_caps & |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3379 | SDHCI_MAX_CURRENT_180_MASK) >> |
| 3380 | SDHCI_MAX_CURRENT_180_SHIFT) * |
| 3381 | SDHCI_MAX_CURRENT_MULTIPLIER; |
Arindam Nath | f2119df | 2011-05-05 12:18:57 +0530 | [diff] [blame] | 3382 | } |
| 3383 | |
Ulf Hansson | 5fd26c7 | 2015-06-05 11:40:08 +0200 | [diff] [blame] | 3384 | /* If OCR set by host, use it instead. */ |
| 3385 | if (host->ocr_mask) |
| 3386 | ocr_avail = host->ocr_mask; |
| 3387 | |
| 3388 | /* If OCR set by external regulators, give it highest prio. */ |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3389 | if (mmc->ocr_avail) |
Tim Kryger | 5222161 | 2014-06-25 00:25:34 -0700 | [diff] [blame] | 3390 | ocr_avail = mmc->ocr_avail; |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3391 | |
Takashi Iwai | 8f230f4 | 2010-12-08 10:04:30 +0100 | [diff] [blame] | 3392 | mmc->ocr_avail = ocr_avail; |
| 3393 | mmc->ocr_avail_sdio = ocr_avail; |
| 3394 | if (host->ocr_avail_sdio) |
| 3395 | mmc->ocr_avail_sdio &= host->ocr_avail_sdio; |
| 3396 | mmc->ocr_avail_sd = ocr_avail; |
| 3397 | if (host->ocr_avail_sd) |
| 3398 | mmc->ocr_avail_sd &= host->ocr_avail_sd; |
| 3399 | else /* normal SD controllers don't support 1.8V */ |
| 3400 | mmc->ocr_avail_sd &= ~MMC_VDD_165_195; |
| 3401 | mmc->ocr_avail_mmc = ocr_avail; |
| 3402 | if (host->ocr_avail_mmc) |
| 3403 | mmc->ocr_avail_mmc &= host->ocr_avail_mmc; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 3404 | |
| 3405 | if (mmc->ocr_avail == 0) { |
Marek Vasut | 2e4456f | 2015-11-18 10:47:02 +0100 | [diff] [blame] | 3406 | pr_err("%s: Hardware doesn't report any support voltages.\n", |
| 3407 | mmc_hostname(mmc)); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3408 | ret = -ENODEV; |
| 3409 | goto unreg; |
Pierre Ossman | 146ad66 | 2006-06-30 02:22:23 -0700 | [diff] [blame] | 3410 | } |
| 3411 | |
Adrian Hunter | 8cb851a | 2016-06-29 16:24:16 +0300 | [diff] [blame] | 3412 | if ((mmc->caps & (MMC_CAP_UHS_SDR12 | MMC_CAP_UHS_SDR25 | |
| 3413 | MMC_CAP_UHS_SDR50 | MMC_CAP_UHS_SDR104 | |
| 3414 | MMC_CAP_UHS_DDR50 | MMC_CAP_1_8V_DDR)) || |
| 3415 | (mmc->caps2 & (MMC_CAP2_HS200_1_8V_SDR | MMC_CAP2_HS400_1_8V))) |
| 3416 | host->flags |= SDHCI_SIGNALING_180; |
| 3417 | |
| 3418 | if (mmc->caps2 & MMC_CAP2_HSX00_1_2V) |
| 3419 | host->flags |= SDHCI_SIGNALING_120; |
| 3420 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3421 | spin_lock_init(&host->lock); |
| 3422 | |
| 3423 | /* |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3424 | * Maximum number of segments. Depends on if the hardware |
| 3425 | * can do scatter/gather or not. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3426 | */ |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3427 | if (host->flags & SDHCI_USE_ADMA) |
Adrian Hunter | 4fb213f | 2014-11-04 12:42:43 +0200 | [diff] [blame] | 3428 | mmc->max_segs = SDHCI_MAX_SEGS; |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3429 | else if (host->flags & SDHCI_USE_SDMA) |
Martin K. Petersen | a36274e | 2010-09-10 01:33:59 -0400 | [diff] [blame] | 3430 | mmc->max_segs = 1; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3431 | else /* PIO */ |
Adrian Hunter | 4fb213f | 2014-11-04 12:42:43 +0200 | [diff] [blame] | 3432 | mmc->max_segs = SDHCI_MAX_SEGS; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3433 | |
| 3434 | /* |
Adrian Hunter | ac00531 | 2014-12-05 19:25:28 +0200 | [diff] [blame] | 3435 | * Maximum number of sectors in one transfer. Limited by SDMA boundary |
| 3436 | * size (512KiB). Note some tuning modes impose a 4MiB limit, but this |
| 3437 | * is less anyway. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3438 | */ |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 3439 | mmc->max_req_size = 524288; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3440 | |
| 3441 | /* |
| 3442 | * Maximum segment size. Could be one segment with the maximum number |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3443 | * of bytes. When doing hardware scatter/gather, each entry cannot |
| 3444 | * be larger than 64 KiB though. |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3445 | */ |
Olof Johansson | 30652aa | 2011-01-01 18:37:32 -0600 | [diff] [blame] | 3446 | if (host->flags & SDHCI_USE_ADMA) { |
| 3447 | if (host->quirks & SDHCI_QUIRK_BROKEN_ADMA_ZEROLEN_DESC) |
| 3448 | mmc->max_seg_size = 65535; |
| 3449 | else |
| 3450 | mmc->max_seg_size = 65536; |
| 3451 | } else { |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3452 | mmc->max_seg_size = mmc->max_req_size; |
Olof Johansson | 30652aa | 2011-01-01 18:37:32 -0600 | [diff] [blame] | 3453 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3454 | |
| 3455 | /* |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 3456 | * Maximum block size. This varies from controller to controller and |
| 3457 | * is specified in the capabilities register. |
| 3458 | */ |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 3459 | if (host->quirks & SDHCI_QUIRK_FORCE_BLK_SZ_2048) { |
| 3460 | mmc->max_blk_size = 2; |
| 3461 | } else { |
Adrian Hunter | 28da358 | 2016-06-29 16:24:17 +0300 | [diff] [blame] | 3462 | mmc->max_blk_size = (host->caps & SDHCI_MAX_BLOCK_MASK) >> |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 3463 | SDHCI_MAX_BLOCK_SHIFT; |
| 3464 | if (mmc->max_blk_size >= 3) { |
Joe Perches | 6606110 | 2014-09-12 14:56:56 -0700 | [diff] [blame] | 3465 | pr_warn("%s: Invalid maximum block size, assuming 512 bytes\n", |
| 3466 | mmc_hostname(mmc)); |
Anton Vorontsov | 0633f65 | 2009-03-17 00:14:03 +0300 | [diff] [blame] | 3467 | mmc->max_blk_size = 0; |
| 3468 | } |
| 3469 | } |
| 3470 | |
| 3471 | mmc->max_blk_size = 512 << mmc->max_blk_size; |
Pierre Ossman | fe4a3c7 | 2006-11-21 17:54:23 +0100 | [diff] [blame] | 3472 | |
| 3473 | /* |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 3474 | * Maximum block count. |
| 3475 | */ |
Ben Dooks | 1388eef | 2009-06-14 12:40:53 +0100 | [diff] [blame] | 3476 | mmc->max_blk_count = (host->quirks & SDHCI_QUIRK_NO_MULTIBLOCK) ? 1 : 65535; |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 3477 | |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 3478 | return 0; |
| 3479 | |
| 3480 | unreg: |
| 3481 | if (!IS_ERR(mmc->supply.vqmmc)) |
| 3482 | regulator_disable(mmc->supply.vqmmc); |
| 3483 | undma: |
| 3484 | if (host->align_buffer) |
| 3485 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 3486 | host->adma_table_sz, host->align_buffer, |
| 3487 | host->align_addr); |
| 3488 | host->adma_table = NULL; |
| 3489 | host->align_buffer = NULL; |
| 3490 | |
| 3491 | return ret; |
| 3492 | } |
| 3493 | EXPORT_SYMBOL_GPL(sdhci_setup_host); |
| 3494 | |
| 3495 | int __sdhci_add_host(struct sdhci_host *host) |
| 3496 | { |
| 3497 | struct mmc_host *mmc = host->mmc; |
| 3498 | int ret; |
| 3499 | |
Pierre Ossman | 55db890 | 2006-11-21 17:55:45 +0100 | [diff] [blame] | 3500 | /* |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3501 | * Init tasklets. |
| 3502 | */ |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3503 | tasklet_init(&host->finish_tasklet, |
| 3504 | sdhci_tasklet_finish, (unsigned long)host); |
| 3505 | |
Al Viro | e4cad1b | 2006-10-10 22:47:07 +0100 | [diff] [blame] | 3506 | setup_timer(&host->timer, sdhci_timeout_timer, (unsigned long)host); |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 3507 | setup_timer(&host->data_timer, sdhci_timeout_data_timer, |
| 3508 | (unsigned long)host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3509 | |
Adrian Hunter | 250fb7b4 | 2014-12-05 19:41:10 +0200 | [diff] [blame] | 3510 | init_waitqueue_head(&host->buf_ready_int); |
Arindam Nath | b513ea2 | 2011-05-05 12:19:04 +0530 | [diff] [blame] | 3511 | |
Shawn Guo | 2af502c | 2013-07-05 14:38:55 +0800 | [diff] [blame] | 3512 | sdhci_init(host, 0); |
| 3513 | |
Russell King | 781e989 | 2014-04-25 12:55:46 +0100 | [diff] [blame] | 3514 | ret = request_threaded_irq(host->irq, sdhci_irq, sdhci_thread_irq, |
| 3515 | IRQF_SHARED, mmc_hostname(mmc), host); |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 3516 | if (ret) { |
| 3517 | pr_err("%s: Failed to request IRQ %d: %d\n", |
| 3518 | mmc_hostname(mmc), host->irq, ret); |
Pierre Ossman | 8ef1a14 | 2006-06-30 02:22:21 -0700 | [diff] [blame] | 3519 | goto untasklet; |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 3520 | } |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3521 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3522 | #ifdef CONFIG_MMC_DEBUG |
| 3523 | sdhci_dumpregs(host); |
| 3524 | #endif |
| 3525 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 3526 | ret = sdhci_led_register(host); |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 3527 | if (ret) { |
| 3528 | pr_err("%s: Failed to register LED device: %d\n", |
| 3529 | mmc_hostname(mmc), ret); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3530 | goto unirq; |
Mark Brown | 0fc81ee | 2012-07-02 14:26:15 +0100 | [diff] [blame] | 3531 | } |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3532 | |
Pierre Ossman | 5f25a66 | 2006-10-04 02:15:39 -0700 | [diff] [blame] | 3533 | mmiowb(); |
| 3534 | |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3535 | ret = mmc_add_host(mmc); |
| 3536 | if (ret) |
| 3537 | goto unled; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3538 | |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3539 | pr_info("%s: SDHCI controller on %s [%s] using %s\n", |
Kay Sievers | d1b2686 | 2008-11-08 21:37:46 +0100 | [diff] [blame] | 3540 | mmc_hostname(mmc), host->hw_name, dev_name(mmc_dev(mmc)), |
Adrian Hunter | e57a5f6 | 2014-11-04 12:42:46 +0200 | [diff] [blame] | 3541 | (host->flags & SDHCI_USE_ADMA) ? |
| 3542 | (host->flags & SDHCI_USE_64_BIT_DMA) ? "ADMA 64-bit" : "ADMA" : |
Richard Röjfors | a13abc7 | 2009-09-22 16:45:30 -0700 | [diff] [blame] | 3543 | (host->flags & SDHCI_USE_SDMA) ? "DMA" : "PIO"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3544 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 3545 | sdhci_enable_card_detection(host); |
| 3546 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3547 | return 0; |
| 3548 | |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3549 | unled: |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 3550 | sdhci_led_unregister(host); |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3551 | unirq: |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 3552 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 3553 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
| 3554 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3555 | free_irq(host->irq, host); |
Pierre Ossman | 8ef1a14 | 2006-06-30 02:22:21 -0700 | [diff] [blame] | 3556 | untasklet: |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3557 | tasklet_kill(&host->finish_tasklet); |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 3558 | |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3559 | if (!IS_ERR(mmc->supply.vqmmc)) |
| 3560 | regulator_disable(mmc->supply.vqmmc); |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 3561 | |
Adrian Hunter | eb5c20d | 2016-04-12 14:25:08 +0300 | [diff] [blame] | 3562 | if (host->align_buffer) |
| 3563 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 3564 | host->adma_table_sz, host->align_buffer, |
| 3565 | host->align_addr); |
| 3566 | host->adma_table = NULL; |
| 3567 | host->align_buffer = NULL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3568 | |
| 3569 | return ret; |
| 3570 | } |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 3571 | EXPORT_SYMBOL_GPL(__sdhci_add_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3572 | |
Adrian Hunter | 52f5336 | 2016-06-29 16:24:15 +0300 | [diff] [blame] | 3573 | int sdhci_add_host(struct sdhci_host *host) |
| 3574 | { |
| 3575 | int ret; |
| 3576 | |
| 3577 | ret = sdhci_setup_host(host); |
| 3578 | if (ret) |
| 3579 | return ret; |
| 3580 | |
| 3581 | return __sdhci_add_host(host); |
| 3582 | } |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3583 | EXPORT_SYMBOL_GPL(sdhci_add_host); |
| 3584 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3585 | void sdhci_remove_host(struct sdhci_host *host, int dead) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3586 | { |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3587 | struct mmc_host *mmc = host->mmc; |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3588 | unsigned long flags; |
| 3589 | |
| 3590 | if (dead) { |
| 3591 | spin_lock_irqsave(&host->lock, flags); |
| 3592 | |
| 3593 | host->flags |= SDHCI_DEVICE_DEAD; |
| 3594 | |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 3595 | if (sdhci_has_requests(host)) { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3596 | pr_err("%s: Controller removed during " |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 3597 | " transfer!\n", mmc_hostname(mmc)); |
Adrian Hunter | 5d0d11c | 2016-06-29 16:24:31 +0300 | [diff] [blame] | 3598 | sdhci_error_out_mrqs(host, -ENOMEDIUM); |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3599 | } |
| 3600 | |
| 3601 | spin_unlock_irqrestore(&host->lock, flags); |
| 3602 | } |
| 3603 | |
Anton Vorontsov | 7260cf5 | 2009-03-17 00:13:48 +0300 | [diff] [blame] | 3604 | sdhci_disable_card_detection(host); |
| 3605 | |
Markus Mayer | 4e743f1 | 2014-07-03 13:27:42 -0700 | [diff] [blame] | 3606 | mmc_remove_host(mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3607 | |
Adrian Hunter | 061d17a | 2016-04-12 14:25:09 +0300 | [diff] [blame] | 3608 | sdhci_led_unregister(host); |
Pierre Ossman | 2f730fe | 2008-03-17 10:29:38 +0100 | [diff] [blame] | 3609 | |
Pierre Ossman | 1e72859 | 2008-04-16 19:13:13 +0200 | [diff] [blame] | 3610 | if (!dead) |
Russell King | 03231f9 | 2014-04-25 12:57:12 +0100 | [diff] [blame] | 3611 | sdhci_do_reset(host, SDHCI_RESET_ALL); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3612 | |
Russell King | b537f94 | 2014-04-25 12:56:01 +0100 | [diff] [blame] | 3613 | sdhci_writel(host, 0, SDHCI_INT_ENABLE); |
| 3614 | sdhci_writel(host, 0, SDHCI_SIGNAL_ENABLE); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3615 | free_irq(host->irq, host); |
| 3616 | |
| 3617 | del_timer_sync(&host->timer); |
Adrian Hunter | d7422fb | 2016-06-29 16:24:33 +0300 | [diff] [blame] | 3618 | del_timer_sync(&host->data_timer); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3619 | |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3620 | tasklet_kill(&host->finish_tasklet); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3621 | |
Tim Kryger | 3a48edc | 2014-06-13 10:13:56 -0700 | [diff] [blame] | 3622 | if (!IS_ERR(mmc->supply.vqmmc)) |
| 3623 | regulator_disable(mmc->supply.vqmmc); |
Philip Rakity | 6231f3d | 2012-07-23 15:56:23 -0700 | [diff] [blame] | 3624 | |
Russell King | edd63fc | 2016-01-26 13:39:50 +0000 | [diff] [blame] | 3625 | if (host->align_buffer) |
Russell King | e66e61c | 2016-01-26 13:39:55 +0000 | [diff] [blame] | 3626 | dma_free_coherent(mmc_dev(mmc), host->align_buffer_sz + |
| 3627 | host->adma_table_sz, host->align_buffer, |
| 3628 | host->align_addr); |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3629 | |
Adrian Hunter | 4efaa6f | 2014-11-04 12:42:39 +0200 | [diff] [blame] | 3630 | host->adma_table = NULL; |
Pierre Ossman | 2134a92 | 2008-06-28 18:28:51 +0200 | [diff] [blame] | 3631 | host->align_buffer = NULL; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3632 | } |
| 3633 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3634 | EXPORT_SYMBOL_GPL(sdhci_remove_host); |
| 3635 | |
| 3636 | void sdhci_free_host(struct sdhci_host *host) |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3637 | { |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3638 | mmc_free_host(host->mmc); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3639 | } |
| 3640 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3641 | EXPORT_SYMBOL_GPL(sdhci_free_host); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3642 | |
| 3643 | /*****************************************************************************\ |
| 3644 | * * |
| 3645 | * Driver init/exit * |
| 3646 | * * |
| 3647 | \*****************************************************************************/ |
| 3648 | |
| 3649 | static int __init sdhci_drv_init(void) |
| 3650 | { |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3651 | pr_info(DRIVER_NAME |
Pierre Ossman | 52fbf9c | 2007-02-09 08:23:41 +0100 | [diff] [blame] | 3652 | ": Secure Digital Host Controller Interface driver\n"); |
Girish K S | a3c76eb | 2011-10-11 11:44:09 +0530 | [diff] [blame] | 3653 | pr_info(DRIVER_NAME ": Copyright(c) Pierre Ossman\n"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3654 | |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3655 | return 0; |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3656 | } |
| 3657 | |
| 3658 | static void __exit sdhci_drv_exit(void) |
| 3659 | { |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3660 | } |
| 3661 | |
| 3662 | module_init(sdhci_drv_init); |
| 3663 | module_exit(sdhci_drv_exit); |
| 3664 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3665 | module_param(debug_quirks, uint, 0444); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3666 | module_param(debug_quirks2, uint, 0444); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3667 | |
Pierre Ossman | 32710e8 | 2009-04-08 20:14:54 +0200 | [diff] [blame] | 3668 | MODULE_AUTHOR("Pierre Ossman <pierre@ossman.eu>"); |
Pierre Ossman | b8c86fc | 2008-03-18 17:35:49 +0100 | [diff] [blame] | 3669 | MODULE_DESCRIPTION("Secure Digital Host Controller Interface core driver"); |
Pierre Ossman | d129bce | 2006-03-24 03:18:17 -0800 | [diff] [blame] | 3670 | MODULE_LICENSE("GPL"); |
Pierre Ossman | 6743527 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3671 | |
Pierre Ossman | df673b2 | 2006-06-30 02:22:31 -0700 | [diff] [blame] | 3672 | MODULE_PARM_DESC(debug_quirks, "Force certain quirks."); |
Adrian Hunter | 66fd8ad | 2011-10-03 15:33:34 +0300 | [diff] [blame] | 3673 | MODULE_PARM_DESC(debug_quirks2, "Force certain other quirks."); |