Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 1 | /* |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 2 | * Copyright 2012 Red Hat Inc. |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 24 | #include <engine/fifo.h> |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 25 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 26 | #include <core/client.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 27 | #include <core/engctx.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 28 | #include <core/enum.h> |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 29 | #include <core/handle.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 30 | #include <subdev/bar.h> |
Ben Skeggs | 5222555 | 2013-12-23 01:51:16 +1000 | [diff] [blame] | 31 | #include <subdev/fb.h> |
Ben Skeggs | 5ce3bf3 | 2015-01-14 09:57:36 +1000 | [diff] [blame] | 32 | #include <subdev/mmu.h> |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 33 | #include <subdev/timer.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 34 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 35 | #include <nvif/class.h> |
| 36 | #include <nvif/unpack.h> |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 37 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 38 | struct gf100_fifo { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 39 | struct nvkm_fifo base; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 40 | |
| 41 | struct work_struct fault; |
| 42 | u64 mask; |
| 43 | |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 44 | struct { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 45 | struct nvkm_gpuobj *mem[2]; |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 46 | int active; |
| 47 | wait_queue_head_t wait; |
| 48 | } runlist; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 49 | |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 50 | struct { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 51 | struct nvkm_gpuobj *mem; |
| 52 | struct nvkm_vma bar; |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 53 | } user; |
Ben Skeggs | ec9c088 | 2010-12-31 12:10:49 +1000 | [diff] [blame] | 54 | int spoon_nr; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 55 | }; |
| 56 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 57 | struct gf100_fifo_base { |
| 58 | struct nvkm_fifo_base base; |
| 59 | struct nvkm_gpuobj *pgd; |
| 60 | struct nvkm_vm *vm; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 61 | }; |
| 62 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 63 | struct gf100_fifo_chan { |
| 64 | struct nvkm_fifo_chan base; |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 65 | enum { |
| 66 | STOPPED, |
| 67 | RUNNING, |
| 68 | KILLED |
| 69 | } state; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 70 | }; |
| 71 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 72 | /******************************************************************************* |
| 73 | * FIFO channel objects |
| 74 | ******************************************************************************/ |
| 75 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 76 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 77 | gf100_fifo_runlist_update(struct gf100_fifo *fifo) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 78 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 79 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 80 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 81 | struct nvkm_bar *bar = device->bar; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 82 | struct nvkm_gpuobj *cur; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 83 | int i, p; |
| 84 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 85 | mutex_lock(&nv_subdev(fifo)->mutex); |
| 86 | cur = fifo->runlist.mem[fifo->runlist.active]; |
| 87 | fifo->runlist.active = !fifo->runlist.active; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 88 | |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 89 | nvkm_kmap(cur); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 90 | for (i = 0, p = 0; i < 128; i++) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 91 | struct gf100_fifo_chan *chan = (void *)fifo->base.channel[i]; |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 92 | if (chan && chan->state == RUNNING) { |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 93 | nvkm_wo32(cur, p + 0, i); |
| 94 | nvkm_wo32(cur, p + 4, 0x00000004); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 95 | p += 8; |
| 96 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 97 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 98 | bar->flush(bar); |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 99 | nvkm_done(cur); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 100 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 101 | nvkm_wr32(device, 0x002270, cur->addr >> 12); |
| 102 | nvkm_wr32(device, 0x002274, 0x01f00000 | (p >> 3)); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 103 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 104 | if (wait_event_timeout(fifo->runlist.wait, |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 105 | !(nvkm_rd32(device, 0x00227c) & 0x00100000), |
Ben Skeggs | 3cf6290 | 2014-02-22 01:05:01 +1000 | [diff] [blame] | 106 | msecs_to_jiffies(2000)) == 0) |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 107 | nvkm_error(subdev, "runlist update timeout\n"); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 108 | mutex_unlock(&nv_subdev(fifo)->mutex); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 109 | } |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 110 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 111 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 112 | gf100_fifo_context_attach(struct nvkm_object *parent, |
| 113 | struct nvkm_object *object) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 114 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 115 | struct nvkm_bar *bar = nvkm_bar(parent); |
| 116 | struct gf100_fifo_base *base = (void *)parent->parent; |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 117 | struct nvkm_gpuobj *engn = &base->base.gpuobj; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 118 | struct nvkm_engctx *ectx = (void *)object; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 119 | u32 addr; |
| 120 | int ret; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 121 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 122 | switch (nv_engidx(object->engine)) { |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 123 | case NVDEV_ENGINE_SW : return 0; |
| 124 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
| 125 | case NVDEV_ENGINE_CE0 : addr = 0x0230; break; |
| 126 | case NVDEV_ENGINE_CE1 : addr = 0x0240; break; |
| 127 | case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; |
| 128 | case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; |
| 129 | case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 130 | default: |
| 131 | return -EINVAL; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 132 | } |
| 133 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 134 | if (!ectx->vma.node) { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 135 | ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, |
| 136 | NV_MEM_ACCESS_RW, &ectx->vma); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 137 | if (ret) |
| 138 | return ret; |
Ben Skeggs | 4c2d422 | 2012-08-10 15:10:34 +1000 | [diff] [blame] | 139 | |
| 140 | nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 141 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 142 | |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 143 | nvkm_kmap(engn); |
| 144 | nvkm_wo32(engn, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); |
| 145 | nvkm_wo32(engn, addr + 0x04, upper_32_bits(ectx->vma.offset)); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 146 | bar->flush(bar); |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 147 | nvkm_done(engn); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 148 | return 0; |
| 149 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 150 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 151 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 152 | gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, |
| 153 | struct nvkm_object *object) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 154 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 155 | struct gf100_fifo *fifo = (void *)parent->engine; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 156 | struct gf100_fifo_base *base = (void *)parent->parent; |
| 157 | struct gf100_fifo_chan *chan = (void *)parent; |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 158 | struct nvkm_gpuobj *engn = &base->base.gpuobj; |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 159 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 160 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 161 | struct nvkm_bar *bar = device->bar; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 162 | u32 addr; |
| 163 | |
| 164 | switch (nv_engidx(object->engine)) { |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 165 | case NVDEV_ENGINE_SW : return 0; |
| 166 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
| 167 | case NVDEV_ENGINE_CE0 : addr = 0x0230; break; |
| 168 | case NVDEV_ENGINE_CE1 : addr = 0x0240; break; |
| 169 | case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; |
| 170 | case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; |
| 171 | case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 172 | default: |
| 173 | return -EINVAL; |
| 174 | } |
| 175 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 176 | nvkm_wr32(device, 0x002634, chan->base.chid); |
Ben Skeggs | af3082b | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 177 | if (nvkm_msec(device, 2000, |
| 178 | if (nvkm_rd32(device, 0x002634) == chan->base.chid) |
| 179 | break; |
| 180 | ) < 0) { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 181 | nvkm_error(subdev, "channel %d [%s] kick timeout\n", |
| 182 | chan->base.chid, nvkm_client_name(chan)); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 183 | if (suspend) |
| 184 | return -EBUSY; |
| 185 | } |
| 186 | |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 187 | nvkm_kmap(engn); |
| 188 | nvkm_wo32(engn, addr + 0x00, 0x00000000); |
| 189 | nvkm_wo32(engn, addr + 0x04, 0x00000000); |
Ben Skeggs | edc260d | 2012-11-27 11:05:36 +1000 | [diff] [blame] | 190 | bar->flush(bar); |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 191 | nvkm_done(engn); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 192 | return 0; |
| 193 | } |
| 194 | |
| 195 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 196 | gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
| 197 | struct nvkm_oclass *oclass, void *data, u32 size, |
| 198 | struct nvkm_object **pobject) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 199 | { |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 200 | union { |
| 201 | struct nv50_channel_gpfifo_v0 v0; |
| 202 | } *args = data; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 203 | struct nvkm_bar *bar = nvkm_bar(parent); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 204 | struct gf100_fifo *fifo = (void *)engine; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 205 | struct gf100_fifo_base *base = (void *)parent; |
| 206 | struct gf100_fifo_chan *chan; |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 207 | struct nvkm_gpuobj *ramfc = &base->base.gpuobj; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 208 | u64 usermem, ioffset, ilength; |
| 209 | int ret, i; |
| 210 | |
Ben Skeggs | 5300394 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 211 | nvif_ioctl(parent, "create channel gpfifo size %d\n", size); |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 212 | if (nvif_unpack(args->v0, 0, 0, false)) { |
Ben Skeggs | 5300394 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 213 | nvif_ioctl(parent, "create channel gpfifo vers %d pushbuf %08x " |
| 214 | "ioffset %016llx ilength %08x\n", |
| 215 | args->v0.version, args->v0.pushbuf, args->v0.ioffset, |
| 216 | args->v0.ilength); |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 217 | } else |
| 218 | return ret; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 219 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 220 | ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 221 | fifo->user.bar.offset, 0x1000, |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 222 | args->v0.pushbuf, |
| 223 | (1ULL << NVDEV_ENGINE_SW) | |
| 224 | (1ULL << NVDEV_ENGINE_GR) | |
| 225 | (1ULL << NVDEV_ENGINE_CE0) | |
| 226 | (1ULL << NVDEV_ENGINE_CE1) | |
| 227 | (1ULL << NVDEV_ENGINE_MSVLD) | |
| 228 | (1ULL << NVDEV_ENGINE_MSPDEC) | |
| 229 | (1ULL << NVDEV_ENGINE_MSPPP), &chan); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 230 | *pobject = nv_object(chan); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 231 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 232 | return ret; |
| 233 | |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 234 | args->v0.chid = chan->base.chid; |
| 235 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 236 | nv_parent(chan)->context_attach = gf100_fifo_context_attach; |
| 237 | nv_parent(chan)->context_detach = gf100_fifo_context_detach; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 238 | |
| 239 | usermem = chan->base.chid * 0x1000; |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 240 | ioffset = args->v0.ioffset; |
| 241 | ilength = order_base_2(args->v0.ilength / 8); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 242 | |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 243 | nvkm_kmap(fifo->user.mem); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 244 | for (i = 0; i < 0x1000; i += 4) |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 245 | nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000); |
| 246 | nvkm_done(fifo->user.mem); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 247 | |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 248 | nvkm_kmap(ramfc); |
| 249 | nvkm_wo32(ramfc, 0x08, lower_32_bits(fifo->user.mem->addr + usermem)); |
| 250 | nvkm_wo32(ramfc, 0x0c, upper_32_bits(fifo->user.mem->addr + usermem)); |
| 251 | nvkm_wo32(ramfc, 0x10, 0x0000face); |
| 252 | nvkm_wo32(ramfc, 0x30, 0xfffff902); |
| 253 | nvkm_wo32(ramfc, 0x48, lower_32_bits(ioffset)); |
| 254 | nvkm_wo32(ramfc, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); |
| 255 | nvkm_wo32(ramfc, 0x54, 0x00000002); |
| 256 | nvkm_wo32(ramfc, 0x84, 0x20400000); |
| 257 | nvkm_wo32(ramfc, 0x94, 0x30000001); |
| 258 | nvkm_wo32(ramfc, 0x9c, 0x00000100); |
| 259 | nvkm_wo32(ramfc, 0xa4, 0x1f1f1f1f); |
| 260 | nvkm_wo32(ramfc, 0xa8, 0x1f1f1f1f); |
| 261 | nvkm_wo32(ramfc, 0xac, 0x0000001f); |
| 262 | nvkm_wo32(ramfc, 0xb8, 0xf8000000); |
| 263 | nvkm_wo32(ramfc, 0xf8, 0x10003080); /* 0x002310 */ |
| 264 | nvkm_wo32(ramfc, 0xfc, 0x10000010); /* 0x002350 */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 265 | bar->flush(bar); |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 266 | nvkm_done(ramfc); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 267 | return 0; |
| 268 | } |
| 269 | |
| 270 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 271 | gf100_fifo_chan_init(struct nvkm_object *object) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 272 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 273 | struct nvkm_gpuobj *base = nv_gpuobj(object->parent); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 274 | struct gf100_fifo *fifo = (void *)object->engine; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 275 | struct gf100_fifo_chan *chan = (void *)object; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 276 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 277 | u32 chid = chan->base.chid; |
| 278 | int ret; |
| 279 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 280 | ret = nvkm_fifo_channel_init(&chan->base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 281 | if (ret) |
| 282 | return ret; |
| 283 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 284 | nvkm_wr32(device, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 285 | |
| 286 | if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 287 | nvkm_wr32(device, 0x003004 + (chid * 8), 0x001f0001); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 288 | gf100_fifo_runlist_update(fifo); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 289 | } |
| 290 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 291 | return 0; |
| 292 | } |
| 293 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 294 | static void gf100_fifo_intr_engine(struct gf100_fifo *fifo); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 295 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 296 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 297 | gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 298 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 299 | struct gf100_fifo *fifo = (void *)object->engine; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 300 | struct gf100_fifo_chan *chan = (void *)object; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 301 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 302 | u32 chid = chan->base.chid; |
| 303 | |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 304 | if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 305 | nvkm_mask(device, 0x003004 + (chid * 8), 0x00000001, 0x00000000); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 306 | gf100_fifo_runlist_update(fifo); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 307 | } |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 308 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 309 | gf100_fifo_intr_engine(fifo); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 310 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 311 | nvkm_wr32(device, 0x003000 + (chid * 8), 0x00000000); |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 312 | return nvkm_fifo_channel_fini(&chan->base, suspend); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 313 | } |
| 314 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 315 | static struct nvkm_ofuncs |
| 316 | gf100_fifo_ofuncs = { |
| 317 | .ctor = gf100_fifo_chan_ctor, |
| 318 | .dtor = _nvkm_fifo_channel_dtor, |
| 319 | .init = gf100_fifo_chan_init, |
| 320 | .fini = gf100_fifo_chan_fini, |
| 321 | .map = _nvkm_fifo_channel_map, |
| 322 | .rd32 = _nvkm_fifo_channel_rd32, |
| 323 | .wr32 = _nvkm_fifo_channel_wr32, |
| 324 | .ntfy = _nvkm_fifo_channel_ntfy |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 325 | }; |
| 326 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 327 | static struct nvkm_oclass |
| 328 | gf100_fifo_sclass[] = { |
| 329 | { FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs }, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 330 | {} |
| 331 | }; |
| 332 | |
| 333 | /******************************************************************************* |
| 334 | * FIFO context - instmem heap and vm setup |
| 335 | ******************************************************************************/ |
| 336 | |
| 337 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 338 | gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
| 339 | struct nvkm_oclass *oclass, void *data, u32 size, |
| 340 | struct nvkm_object **pobject) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 341 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 342 | struct gf100_fifo_base *base; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 343 | int ret; |
| 344 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 345 | ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, |
| 346 | 0x1000, NVOBJ_FLAG_ZERO_ALLOC | |
| 347 | NVOBJ_FLAG_HEAP, &base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 348 | *pobject = nv_object(base); |
| 349 | if (ret) |
| 350 | return ret; |
| 351 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 352 | ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, |
| 353 | &base->pgd); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 354 | if (ret) |
| 355 | return ret; |
| 356 | |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame^] | 357 | nvkm_kmap(&base->base.gpuobj); |
| 358 | nvkm_wo32(&base->base.gpuobj, 0x0200, lower_32_bits(base->pgd->addr)); |
| 359 | nvkm_wo32(&base->base.gpuobj, 0x0204, upper_32_bits(base->pgd->addr)); |
| 360 | nvkm_wo32(&base->base.gpuobj, 0x0208, 0xffffffff); |
| 361 | nvkm_wo32(&base->base.gpuobj, 0x020c, 0x000000ff); |
| 362 | nvkm_done(&base->base.gpuobj); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 363 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 364 | ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 365 | if (ret) |
| 366 | return ret; |
| 367 | |
| 368 | return 0; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 369 | } |
| 370 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 371 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 372 | gf100_fifo_context_dtor(struct nvkm_object *object) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 373 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 374 | struct gf100_fifo_base *base = (void *)object; |
| 375 | nvkm_vm_ref(NULL, &base->vm, base->pgd); |
| 376 | nvkm_gpuobj_ref(NULL, &base->pgd); |
| 377 | nvkm_fifo_context_destroy(&base->base); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 378 | } |
| 379 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 380 | static struct nvkm_oclass |
| 381 | gf100_fifo_cclass = { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 382 | .handle = NV_ENGCTX(FIFO, 0xc0), |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 383 | .ofuncs = &(struct nvkm_ofuncs) { |
| 384 | .ctor = gf100_fifo_context_ctor, |
| 385 | .dtor = gf100_fifo_context_dtor, |
| 386 | .init = _nvkm_fifo_context_init, |
| 387 | .fini = _nvkm_fifo_context_fini, |
| 388 | .rd32 = _nvkm_fifo_context_rd32, |
| 389 | .wr32 = _nvkm_fifo_context_wr32, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 390 | }, |
| 391 | }; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 392 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 393 | /******************************************************************************* |
| 394 | * PFIFO engine |
| 395 | ******************************************************************************/ |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 396 | |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 397 | static inline int |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 398 | gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 399 | { |
| 400 | switch (engn) { |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 401 | case NVDEV_ENGINE_GR : engn = 0; break; |
| 402 | case NVDEV_ENGINE_MSVLD : engn = 1; break; |
| 403 | case NVDEV_ENGINE_MSPPP : engn = 2; break; |
| 404 | case NVDEV_ENGINE_MSPDEC: engn = 3; break; |
| 405 | case NVDEV_ENGINE_CE0 : engn = 4; break; |
| 406 | case NVDEV_ENGINE_CE1 : engn = 5; break; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 407 | default: |
| 408 | return -1; |
| 409 | } |
| 410 | |
| 411 | return engn; |
| 412 | } |
| 413 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 414 | static inline struct nvkm_engine * |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 415 | gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 416 | { |
| 417 | switch (engn) { |
| 418 | case 0: engn = NVDEV_ENGINE_GR; break; |
Ben Skeggs | eccf7e8a | 2015-01-14 10:09:24 +1000 | [diff] [blame] | 419 | case 1: engn = NVDEV_ENGINE_MSVLD; break; |
Ben Skeggs | fd8666f | 2015-01-14 12:26:28 +1000 | [diff] [blame] | 420 | case 2: engn = NVDEV_ENGINE_MSPPP; break; |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 421 | case 3: engn = NVDEV_ENGINE_MSPDEC; break; |
Ben Skeggs | aedf24f | 2015-01-14 11:50:20 +1000 | [diff] [blame] | 422 | case 4: engn = NVDEV_ENGINE_CE0; break; |
| 423 | case 5: engn = NVDEV_ENGINE_CE1; break; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 424 | default: |
| 425 | return NULL; |
| 426 | } |
| 427 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 428 | return nvkm_engine(fifo, engn); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 429 | } |
| 430 | |
| 431 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 432 | gf100_fifo_recover_work(struct work_struct *work) |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 433 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 434 | struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 435 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 436 | struct nvkm_object *engine; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 437 | unsigned long flags; |
| 438 | u32 engn, engm = 0; |
| 439 | u64 mask, todo; |
| 440 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 441 | spin_lock_irqsave(&fifo->base.lock, flags); |
| 442 | mask = fifo->mask; |
| 443 | fifo->mask = 0ULL; |
| 444 | spin_unlock_irqrestore(&fifo->base.lock, flags); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 445 | |
| 446 | for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 447 | engm |= 1 << gf100_fifo_engidx(fifo, engn); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 448 | nvkm_mask(device, 0x002630, engm, engm); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 449 | |
| 450 | for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 451 | if ((engine = (void *)nvkm_engine(fifo, engn))) { |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 452 | nv_ofuncs(engine)->fini(engine, false); |
| 453 | WARN_ON(nv_ofuncs(engine)->init(engine)); |
| 454 | } |
| 455 | } |
| 456 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 457 | gf100_fifo_runlist_update(fifo); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 458 | nvkm_wr32(device, 0x00262c, engm); |
| 459 | nvkm_mask(device, 0x002630, engm, 0x00000000); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 460 | } |
| 461 | |
| 462 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 463 | gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 464 | struct gf100_fifo_chan *chan) |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 465 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 466 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 467 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 468 | u32 chid = chan->base.chid; |
| 469 | unsigned long flags; |
| 470 | |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 471 | nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n", |
| 472 | engine->subdev.name, chid); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 473 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 474 | nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 475 | chan->state = KILLED; |
| 476 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 477 | spin_lock_irqsave(&fifo->base.lock, flags); |
| 478 | fifo->mask |= 1ULL << nv_engidx(engine); |
| 479 | spin_unlock_irqrestore(&fifo->base.lock, flags); |
| 480 | schedule_work(&fifo->fault); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 481 | } |
| 482 | |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 483 | static int |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 484 | gf100_fifo_swmthd(struct gf100_fifo *fifo, u32 chid, u32 mthd, u32 data) |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 485 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 486 | struct gf100_fifo_chan *chan = NULL; |
| 487 | struct nvkm_handle *bind; |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 488 | unsigned long flags; |
| 489 | int ret = -EINVAL; |
| 490 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 491 | spin_lock_irqsave(&fifo->base.lock, flags); |
| 492 | if (likely(chid >= fifo->base.min && chid <= fifo->base.max)) |
| 493 | chan = (void *)fifo->base.channel[chid]; |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 494 | if (unlikely(!chan)) |
| 495 | goto out; |
| 496 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 497 | bind = nvkm_namedb_get_class(nv_namedb(chan), 0x906e); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 498 | if (likely(bind)) { |
| 499 | if (!mthd || !nv_call(bind->object, mthd, data)) |
| 500 | ret = 0; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 501 | nvkm_namedb_put(bind); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 502 | } |
| 503 | |
| 504 | out: |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 505 | spin_unlock_irqrestore(&fifo->base.lock, flags); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 506 | return ret; |
| 507 | } |
| 508 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 509 | static const struct nvkm_enum |
| 510 | gf100_fifo_sched_reason[] = { |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 511 | { 0x0a, "CTXSW_TIMEOUT" }, |
| 512 | {} |
| 513 | }; |
| 514 | |
| 515 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 516 | gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo) |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 517 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 518 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 519 | struct nvkm_engine *engine; |
| 520 | struct gf100_fifo_chan *chan; |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 521 | u32 engn; |
| 522 | |
| 523 | for (engn = 0; engn < 6; engn++) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 524 | u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 525 | u32 busy = (stat & 0x80000000); |
| 526 | u32 save = (stat & 0x00100000); /* maybe? */ |
| 527 | u32 unk0 = (stat & 0x00040000); |
| 528 | u32 unk1 = (stat & 0x00001000); |
| 529 | u32 chid = (stat & 0x0000007f); |
| 530 | (void)save; |
| 531 | |
| 532 | if (busy && unk0 && unk1) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 533 | if (!(chan = (void *)fifo->base.channel[chid])) |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 534 | continue; |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 535 | if (!(engine = gf100_fifo_engine(fifo, engn))) |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 536 | continue; |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 537 | gf100_fifo_recover(fifo, engine, chan); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 538 | } |
| 539 | } |
| 540 | } |
| 541 | |
| 542 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 543 | gf100_fifo_intr_sched(struct gf100_fifo *fifo) |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 544 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 545 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 546 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 547 | u32 intr = nvkm_rd32(device, 0x00254c); |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 548 | u32 code = intr & 0x000000ff; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 549 | const struct nvkm_enum *en; |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 550 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 551 | en = nvkm_enum_find(gf100_fifo_sched_reason, code); |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 552 | |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 553 | nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : ""); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 554 | |
| 555 | switch (code) { |
| 556 | case 0x0a: |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 557 | gf100_fifo_intr_sched_ctxsw(fifo); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 558 | break; |
| 559 | default: |
| 560 | break; |
| 561 | } |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 562 | } |
| 563 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 564 | static const struct nvkm_enum |
| 565 | gf100_fifo_fault_engine[] = { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 566 | { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR }, |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 567 | { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB }, |
| 568 | { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, |
| 569 | { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 570 | { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO }, |
Ben Skeggs | eccf7e8a | 2015-01-14 10:09:24 +1000 | [diff] [blame] | 571 | { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD }, |
Ben Skeggs | fd8666f | 2015-01-14 12:26:28 +1000 | [diff] [blame] | 572 | { 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 573 | { 0x13, "PCOUNTER" }, |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 574 | { 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC }, |
Ben Skeggs | aedf24f | 2015-01-14 11:50:20 +1000 | [diff] [blame] | 575 | { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 }, |
| 576 | { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 577 | { 0x17, "PDAEMON" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 578 | {} |
| 579 | }; |
| 580 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 581 | static const struct nvkm_enum |
| 582 | gf100_fifo_fault_reason[] = { |
Ben Skeggs | e296663 | 2011-03-29 08:57:34 +1000 | [diff] [blame] | 583 | { 0x00, "PT_NOT_PRESENT" }, |
| 584 | { 0x01, "PT_TOO_SHORT" }, |
| 585 | { 0x02, "PAGE_NOT_PRESENT" }, |
| 586 | { 0x03, "VM_LIMIT_EXCEEDED" }, |
| 587 | { 0x04, "NO_CHANNEL" }, |
| 588 | { 0x05, "PAGE_SYSTEM_ONLY" }, |
| 589 | { 0x06, "PAGE_READ_ONLY" }, |
| 590 | { 0x0a, "COMPRESSED_SYSRAM" }, |
| 591 | { 0x0c, "INVALID_STORAGE_TYPE" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 592 | {} |
| 593 | }; |
| 594 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 595 | static const struct nvkm_enum |
| 596 | gf100_fifo_fault_hubclient[] = { |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 597 | { 0x01, "PCOPY0" }, |
| 598 | { 0x02, "PCOPY1" }, |
| 599 | { 0x04, "DISPATCH" }, |
| 600 | { 0x05, "CTXCTL" }, |
| 601 | { 0x06, "PFIFO" }, |
| 602 | { 0x07, "BAR_READ" }, |
| 603 | { 0x08, "BAR_WRITE" }, |
| 604 | { 0x0b, "PVP" }, |
Ben Skeggs | fd8666f | 2015-01-14 12:26:28 +1000 | [diff] [blame] | 605 | { 0x0c, "PMSPPP" }, |
Ben Skeggs | eccf7e8a | 2015-01-14 10:09:24 +1000 | [diff] [blame] | 606 | { 0x0d, "PMSVLD" }, |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 607 | { 0x11, "PCOUNTER" }, |
| 608 | { 0x12, "PDAEMON" }, |
| 609 | { 0x14, "CCACHE" }, |
| 610 | { 0x15, "CCACHE_POST" }, |
| 611 | {} |
| 612 | }; |
| 613 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 614 | static const struct nvkm_enum |
| 615 | gf100_fifo_fault_gpcclient[] = { |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 616 | { 0x01, "TEX" }, |
| 617 | { 0x0c, "ESETUP" }, |
| 618 | { 0x0e, "CTXCTL" }, |
| 619 | { 0x0f, "PROP" }, |
| 620 | {} |
| 621 | }; |
| 622 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 623 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 624 | gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 625 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 626 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 627 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 628 | u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); |
| 629 | u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); |
| 630 | u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); |
| 631 | u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10)); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 632 | u32 gpc = (stat & 0x1f000000) >> 24; |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 633 | u32 client = (stat & 0x00001f00) >> 8; |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 634 | u32 write = (stat & 0x00000080); |
| 635 | u32 hub = (stat & 0x00000040); |
| 636 | u32 reason = (stat & 0x0000000f); |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 637 | struct nvkm_object *engctx = NULL, *object; |
| 638 | struct nvkm_engine *engine = NULL; |
| 639 | const struct nvkm_enum *er, *eu, *ec; |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 640 | char gpcid[8] = ""; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 641 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 642 | er = nvkm_enum_find(gf100_fifo_fault_reason, reason); |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 643 | eu = nvkm_enum_find(gf100_fifo_fault_engine, unit); |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 644 | if (hub) { |
| 645 | ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client); |
| 646 | } else { |
| 647 | ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client); |
| 648 | snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc); |
| 649 | } |
| 650 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 651 | if (eu) { |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 652 | switch (eu->data2) { |
| 653 | case NVDEV_SUBDEV_BAR: |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 654 | nvkm_mask(device, 0x001704, 0x00000000, 0x00000000); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 655 | break; |
| 656 | case NVDEV_SUBDEV_INSTMEM: |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 657 | nvkm_mask(device, 0x001714, 0x00000000, 0x00000000); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 658 | break; |
| 659 | case NVDEV_ENGINE_IFB: |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 660 | nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 661 | break; |
| 662 | default: |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 663 | engine = nvkm_engine(fifo, eu->data2); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 664 | if (engine) |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 665 | engctx = nvkm_engctx_get(engine, inst); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 666 | break; |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 667 | } |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 668 | } |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 669 | |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 670 | nvkm_error(subdev, |
| 671 | "%s fault at %010llx engine %02x [%s] client %02x [%s%s] " |
| 672 | "reason %02x [%s] on channel %d [%010llx %s]\n", |
| 673 | write ? "write" : "read", (u64)vahi << 32 | valo, |
| 674 | unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "", |
| 675 | reason, er ? er->name : "", -1, (u64)inst << 12, |
| 676 | nvkm_client_name(engctx)); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 677 | |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 678 | object = engctx; |
| 679 | while (object) { |
| 680 | switch (nv_mclass(object)) { |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 681 | case FERMI_CHANNEL_GPFIFO: |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 682 | gf100_fifo_recover(fifo, engine, (void *)object); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 683 | break; |
| 684 | } |
| 685 | object = object->parent; |
| 686 | } |
| 687 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 688 | nvkm_engctx_put(engctx); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 689 | } |
| 690 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 691 | static const struct nvkm_bitfield |
| 692 | gf100_fifo_pbdma_intr[] = { |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 693 | /* { 0x00008000, "" } seen with null ib push */ |
| 694 | { 0x00200000, "ILLEGAL_MTHD" }, |
| 695 | { 0x00800000, "EMPTY_SUBC" }, |
| 696 | {} |
| 697 | }; |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 698 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 699 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 700 | gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 701 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 702 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 703 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 704 | u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)); |
| 705 | u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000)); |
| 706 | u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000)); |
| 707 | u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 708 | u32 subc = (addr & 0x00070000) >> 16; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 709 | u32 mthd = (addr & 0x00003ffc); |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 710 | u32 show= stat; |
| 711 | char msg[128]; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 712 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 713 | if (stat & 0x00800000) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 714 | if (!gf100_fifo_swmthd(fifo, chid, mthd, data)) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 715 | show &= ~0x00800000; |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 716 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 717 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 718 | if (show) { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 719 | nvkm_snprintbf(msg, sizeof(msg), gf100_fifo_pbdma_intr, show); |
| 720 | nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%s] subc %d " |
| 721 | "mthd %04x data %08x\n", |
| 722 | unit, show, msg, chid, |
| 723 | nvkm_client_name_for_fifo_chid(&fifo->base, chid), |
| 724 | subc, mthd, data); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 725 | } |
| 726 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 727 | nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008); |
| 728 | nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 729 | } |
| 730 | |
| 731 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 732 | gf100_fifo_intr_runlist(struct gf100_fifo *fifo) |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 733 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 734 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 735 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 736 | u32 intr = nvkm_rd32(device, 0x002a00); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 737 | |
| 738 | if (intr & 0x10000000) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 739 | wake_up(&fifo->runlist.wait); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 740 | nvkm_wr32(device, 0x002a00, 0x10000000); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 741 | intr &= ~0x10000000; |
| 742 | } |
| 743 | |
| 744 | if (intr) { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 745 | nvkm_error(subdev, "RUNLIST %08x\n", intr); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 746 | nvkm_wr32(device, 0x002a00, intr); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 747 | } |
| 748 | } |
| 749 | |
| 750 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 751 | gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn) |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 752 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 753 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 754 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 755 | u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04)); |
| 756 | u32 inte = nvkm_rd32(device, 0x002628); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 757 | u32 unkn; |
| 758 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 759 | nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr); |
Ben Skeggs | 19a1082 | 2014-12-01 11:44:27 +1000 | [diff] [blame] | 760 | |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 761 | for (unkn = 0; unkn < 8; unkn++) { |
| 762 | u32 ints = (intr >> (unkn * 0x04)) & inte; |
| 763 | if (ints & 0x1) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 764 | nvkm_fifo_uevent(&fifo->base); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 765 | ints &= ~1; |
| 766 | } |
| 767 | if (ints) { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 768 | nvkm_error(subdev, "ENGINE %d %d %01x", |
| 769 | engn, unkn, ints); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 770 | nvkm_mask(device, 0x002628, ints, 0); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 771 | } |
| 772 | } |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 773 | } |
| 774 | |
| 775 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 776 | gf100_fifo_intr_engine(struct gf100_fifo *fifo) |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 777 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 778 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 779 | u32 mask = nvkm_rd32(device, 0x0025a4); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 780 | while (mask) { |
| 781 | u32 unit = __ffs(mask); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 782 | gf100_fifo_intr_engine_unit(fifo, unit); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 783 | mask &= ~(1 << unit); |
| 784 | } |
| 785 | } |
| 786 | |
| 787 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 788 | gf100_fifo_intr(struct nvkm_subdev *subdev) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 789 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 790 | struct gf100_fifo *fifo = (void *)subdev; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 791 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 792 | u32 mask = nvkm_rd32(device, 0x002140); |
| 793 | u32 stat = nvkm_rd32(device, 0x002100) & mask; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 794 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 795 | if (stat & 0x00000001) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 796 | u32 intr = nvkm_rd32(device, 0x00252c); |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 797 | nvkm_warn(subdev, "INTR 00000001: %08x\n", intr); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 798 | nvkm_wr32(device, 0x002100, 0x00000001); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 799 | stat &= ~0x00000001; |
| 800 | } |
| 801 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 802 | if (stat & 0x00000100) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 803 | gf100_fifo_intr_sched(fifo); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 804 | nvkm_wr32(device, 0x002100, 0x00000100); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 805 | stat &= ~0x00000100; |
| 806 | } |
| 807 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 808 | if (stat & 0x00010000) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 809 | u32 intr = nvkm_rd32(device, 0x00256c); |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 810 | nvkm_warn(subdev, "INTR 00010000: %08x\n", intr); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 811 | nvkm_wr32(device, 0x002100, 0x00010000); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 812 | stat &= ~0x00010000; |
| 813 | } |
| 814 | |
| 815 | if (stat & 0x01000000) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 816 | u32 intr = nvkm_rd32(device, 0x00258c); |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 817 | nvkm_warn(subdev, "INTR 01000000: %08x\n", intr); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 818 | nvkm_wr32(device, 0x002100, 0x01000000); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 819 | stat &= ~0x01000000; |
| 820 | } |
| 821 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 822 | if (stat & 0x10000000) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 823 | u32 mask = nvkm_rd32(device, 0x00259c); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 824 | while (mask) { |
| 825 | u32 unit = __ffs(mask); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 826 | gf100_fifo_intr_fault(fifo, unit); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 827 | nvkm_wr32(device, 0x00259c, (1 << unit)); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 828 | mask &= ~(1 << unit); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 829 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 830 | stat &= ~0x10000000; |
| 831 | } |
| 832 | |
| 833 | if (stat & 0x20000000) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 834 | u32 mask = nvkm_rd32(device, 0x0025a0); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 835 | while (mask) { |
| 836 | u32 unit = __ffs(mask); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 837 | gf100_fifo_intr_pbdma(fifo, unit); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 838 | nvkm_wr32(device, 0x0025a0, (1 << unit)); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 839 | mask &= ~(1 << unit); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 840 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 841 | stat &= ~0x20000000; |
| 842 | } |
| 843 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 844 | if (stat & 0x40000000) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 845 | gf100_fifo_intr_runlist(fifo); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 846 | stat &= ~0x40000000; |
| 847 | } |
| 848 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 849 | if (stat & 0x80000000) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 850 | gf100_fifo_intr_engine(fifo); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 851 | stat &= ~0x80000000; |
| 852 | } |
| 853 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 854 | if (stat) { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 855 | nvkm_error(subdev, "INTR %08x\n", stat); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 856 | nvkm_mask(device, 0x002140, stat, 0x00000000); |
| 857 | nvkm_wr32(device, 0x002100, stat); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 858 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 859 | } |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 860 | |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 861 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 862 | gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index) |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 863 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 864 | struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 865 | struct nvkm_device *device = fifo->engine.subdev.device; |
| 866 | nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 867 | } |
| 868 | |
| 869 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 870 | gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index) |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 871 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 872 | struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 873 | struct nvkm_device *device = fifo->engine.subdev.device; |
| 874 | nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 875 | } |
| 876 | |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 877 | static const struct nvkm_event_func |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 878 | gf100_fifo_uevent_func = { |
| 879 | .ctor = nvkm_fifo_uevent_ctor, |
| 880 | .init = gf100_fifo_uevent_init, |
| 881 | .fini = gf100_fifo_uevent_fini, |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 882 | }; |
| 883 | |
| 884 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 885 | gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
| 886 | struct nvkm_oclass *oclass, void *data, u32 size, |
| 887 | struct nvkm_object **pobject) |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 888 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 889 | struct gf100_fifo *fifo; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 890 | int ret; |
| 891 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 892 | ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &fifo); |
| 893 | *pobject = nv_object(fifo); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 894 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 895 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 896 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 897 | INIT_WORK(&fifo->fault, gf100_fifo_recover_work); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 898 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 899 | ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0, |
| 900 | &fifo->runlist.mem[0]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 901 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 902 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 903 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 904 | ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0, |
| 905 | &fifo->runlist.mem[1]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 906 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 907 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 908 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 909 | init_waitqueue_head(&fifo->runlist.wait); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 910 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 911 | ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 0x1000, 0x1000, 0, |
| 912 | &fifo->user.mem); |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 913 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 914 | return ret; |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 915 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 916 | ret = nvkm_gpuobj_map(fifo->user.mem, NV_MEM_ACCESS_RW, |
| 917 | &fifo->user.bar); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 918 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 919 | return ret; |
| 920 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 921 | ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &fifo->base.uevent); |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 922 | if (ret) |
| 923 | return ret; |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 924 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 925 | nv_subdev(fifo)->unit = 0x00000100; |
| 926 | nv_subdev(fifo)->intr = gf100_fifo_intr; |
| 927 | nv_engine(fifo)->cclass = &gf100_fifo_cclass; |
| 928 | nv_engine(fifo)->sclass = gf100_fifo_sclass; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 929 | return 0; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 930 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 931 | |
| 932 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 933 | gf100_fifo_dtor(struct nvkm_object *object) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 934 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 935 | struct gf100_fifo *fifo = (void *)object; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 936 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 937 | nvkm_gpuobj_unmap(&fifo->user.bar); |
| 938 | nvkm_gpuobj_ref(NULL, &fifo->user.mem); |
| 939 | nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[0]); |
| 940 | nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[1]); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 941 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 942 | nvkm_fifo_destroy(&fifo->base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 943 | } |
| 944 | |
| 945 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 946 | gf100_fifo_init(struct nvkm_object *object) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 947 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 948 | struct gf100_fifo *fifo = (void *)object; |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 949 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 950 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 951 | int ret, i; |
| 952 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 953 | ret = nvkm_fifo_init(&fifo->base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 954 | if (ret) |
| 955 | return ret; |
| 956 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 957 | nvkm_wr32(device, 0x000204, 0xffffffff); |
| 958 | nvkm_wr32(device, 0x002204, 0xffffffff); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 959 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 960 | fifo->spoon_nr = hweight32(nvkm_rd32(device, 0x002204)); |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 961 | nvkm_debug(subdev, "%d PBDMA unit(s)\n", fifo->spoon_nr); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 962 | |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 963 | /* assign engines to PBDMAs */ |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 964 | if (fifo->spoon_nr >= 3) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 965 | nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */ |
| 966 | nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */ |
| 967 | nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */ |
| 968 | nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */ |
| 969 | nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */ |
| 970 | nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 971 | } |
| 972 | |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 973 | /* PBDMA[n] */ |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 974 | for (i = 0; i < fifo->spoon_nr; i++) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 975 | nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); |
| 976 | nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ |
| 977 | nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 978 | } |
| 979 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 980 | nvkm_mask(device, 0x002200, 0x00000001, 0x00000001); |
| 981 | nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 982 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 983 | nvkm_wr32(device, 0x002100, 0xffffffff); |
| 984 | nvkm_wr32(device, 0x002140, 0x7fffffff); |
| 985 | nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 986 | return 0; |
| 987 | } |
| 988 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 989 | struct nvkm_oclass * |
| 990 | gf100_fifo_oclass = &(struct nvkm_oclass) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 991 | .handle = NV_ENGINE(FIFO, 0xc0), |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 992 | .ofuncs = &(struct nvkm_ofuncs) { |
| 993 | .ctor = gf100_fifo_ctor, |
| 994 | .dtor = gf100_fifo_dtor, |
| 995 | .init = gf100_fifo_init, |
| 996 | .fini = _nvkm_fifo_fini, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 997 | }, |
| 998 | }; |