blob: 6663b76934ad711a6a835dda88f093b5bdbd5e00 [file] [log] [blame]
Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
2 * This file contains work-arounds for many known PCI hardware
3 * bugs. Devices present only on certain architectures (host
4 * bridges et cetera) should be handled in arch-specific code.
5 *
6 * Note: any quirks for hotpluggable devices must _NOT_ be declared __init.
7 *
8 * Copyright (c) 1999 Martin Mares <mj@ucw.cz>
9 *
David Brownell75862692005-09-23 17:14:37 -070010 * Init/reset quirks for USB host controllers should be in the
11 * USB quirks file, where their drivers can access reuse it.
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 */
13
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/types.h>
15#include <linux/kernel.h>
Paul Gortmaker363c75d2011-05-27 09:37:25 -040016#include <linux/export.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/pci.h>
18#include <linux/init.h>
19#include <linux/delay.h>
Len Brown25be5e62005-05-27 04:21:50 -040020#include <linux/acpi.h>
bjorn.helgaas@hp.com9f23ed32007-12-17 14:09:38 -070021#include <linux/kallsyms.h>
Andreas Petlund75e07fc2008-11-20 20:42:25 -080022#include <linux/dmi.h>
Alexander Duyck649426e2009-03-05 13:57:28 -050023#include <linux/pci-aspm.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090024#include <linux/ioport.h>
Arjan van de Ven32098742012-01-30 20:52:07 -080025#include <linux/sched.h>
26#include <linux/ktime.h>
Douglas Lehr9fe373f2014-08-21 09:26:52 +100027#include <linux/mm.h>
Rafael J. Wysocki93177a72010-01-02 22:57:24 +010028#include <asm/dma.h> /* isa_dma_bridge_buggy */
Greg KHbc56b9e2005-04-08 14:53:31 +090029#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070030
Yuji Shimada32a9a6822009-03-16 17:13:39 +090031/*
Jacob Pan253d2e52010-07-16 10:19:22 -070032 * Decoding should be disabled for a PCI device during BAR sizing to avoid
33 * conflict. But doing so may cause problems on host bridge and perhaps other
34 * key system devices. For devices that need to have mmio decoding always-on,
35 * we need to set the dev->mmio_always_on bit.
36 */
Bill Pemberton15856ad2012-11-21 15:35:00 -050037static void quirk_mmio_always_on(struct pci_dev *dev)
Jacob Pan253d2e52010-07-16 10:19:22 -070038{
Yinghai Lu52d21b52012-02-23 23:46:53 -080039 dev->mmio_always_on = 1;
Jacob Pan253d2e52010-07-16 10:19:22 -070040}
Yinghai Lu52d21b52012-02-23 23:46:53 -080041DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_ANY_ID, PCI_ANY_ID,
42 PCI_CLASS_BRIDGE_HOST, 8, quirk_mmio_always_on);
Jacob Pan253d2e52010-07-16 10:19:22 -070043
Doug Thompsonbd8481e2006-05-08 17:06:09 -070044/* The Mellanox Tavor device gives false positive parity errors
45 * Mark this device with a broken_parity_status, to allow
46 * PCI scanning code to "skip" this now blacklisted device.
47 */
Bill Pemberton15856ad2012-11-21 15:35:00 -050048static void quirk_mellanox_tavor(struct pci_dev *dev)
Doug Thompsonbd8481e2006-05-08 17:06:09 -070049{
50 dev->broken_parity_status = 1; /* This device gives false positives */
51}
Ryan Desfosses3c78bc62014-04-18 20:13:49 -040052DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR, quirk_mellanox_tavor);
53DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_DEVICE_ID_MELLANOX_TAVOR_BRIDGE, quirk_mellanox_tavor);
Doug Thompsonbd8481e2006-05-08 17:06:09 -070054
Bjorn Helgaasf7625982013-11-14 11:28:18 -070055/* Deal with broken BIOSes that neglect to enable passive release,
Linus Torvalds1da177e2005-04-16 15:20:36 -070056 which can cause problems in combination with the 82441FX/PPro MTRRs */
Alan Cox1597cac2006-12-04 15:14:45 -080057static void quirk_passive_release(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070058{
59 struct pci_dev *d = NULL;
60 unsigned char dlc;
61
62 /* We have to make sure a particular bit is set in the PIIX3
63 ISA bridge, so we have to go out and find it. */
64 while ((d = pci_get_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, d))) {
65 pci_read_config_byte(d, 0x82, &dlc);
66 if (!(dlc & 1<<1)) {
Adam Jackson999da9f2008-12-01 14:30:29 -080067 dev_info(&d->dev, "PIIX3: Enabling Passive Release\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070068 dlc |= 1<<1;
69 pci_write_config_byte(d, 0x82, dlc);
70 }
71 }
72}
Andrew Morton652c5382007-11-21 15:07:13 -080073DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
74DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_passive_release);
Linus Torvalds1da177e2005-04-16 15:20:36 -070075
76/* The VIA VP2/VP3/MVP3 seem to have some 'features'. There may be a workaround
77 but VIA don't answer queries. If you happen to have good contacts at VIA
Bjorn Helgaasf7625982013-11-14 11:28:18 -070078 ask them for me please -- Alan
79
80 This appears to be BIOS not version dependent. So presumably there is a
Linus Torvalds1da177e2005-04-16 15:20:36 -070081 chipset level fix */
Bjorn Helgaasf7625982013-11-14 11:28:18 -070082
Bill Pemberton15856ad2012-11-21 15:35:00 -050083static void quirk_isa_dma_hangs(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -070084{
85 if (!isa_dma_bridge_buggy) {
Ryan Desfosses3c78bc62014-04-18 20:13:49 -040086 isa_dma_bridge_buggy = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -070087 dev_info(&dev->dev, "Activating ISA DMA hang workarounds\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -070088 }
89}
90 /*
91 * Its not totally clear which chipsets are the problematic ones
92 * We know 82C586 and 82C596 variants are affected.
93 */
Andrew Morton652c5382007-11-21 15:07:13 -080094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_0, quirk_isa_dma_hangs);
95DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C596, quirk_isa_dma_hangs);
96DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371SB_0, quirk_isa_dma_hangs);
Bjorn Helgaasf7625982013-11-14 11:28:18 -070097DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1533, quirk_isa_dma_hangs);
Andrew Morton652c5382007-11-21 15:07:13 -080098DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_1, quirk_isa_dma_hangs);
99DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_2, quirk_isa_dma_hangs);
100DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NEC, PCI_DEVICE_ID_NEC_CBUS_3, quirk_isa_dma_hangs);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700101
Linus Torvalds1da177e2005-04-16 15:20:36 -0700102/*
Len Brown4731fdc2010-09-24 21:02:27 -0400103 * Intel NM10 "TigerPoint" LPC PM1a_STS.BM_STS must be clear
104 * for some HT machines to use C4 w/o hanging.
105 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500106static void quirk_tigerpoint_bm_sts(struct pci_dev *dev)
Len Brown4731fdc2010-09-24 21:02:27 -0400107{
108 u32 pmbase;
109 u16 pm1a;
110
111 pci_read_config_dword(dev, 0x40, &pmbase);
112 pmbase = pmbase & 0xff80;
113 pm1a = inw(pmbase);
114
115 if (pm1a & 0x10) {
116 dev_info(&dev->dev, FW_BUG "TigerPoint LPC.BM_STS cleared\n");
117 outw(0x10, pmbase);
118 }
119}
120DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_TGP_LPC, quirk_tigerpoint_bm_sts);
121
122/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700123 * Chipsets where PCI->PCI transfers vanish or hang
124 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500125static void quirk_nopcipci(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400127 if ((pci_pci_problems & PCIPCI_FAIL) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700128 dev_info(&dev->dev, "Disabling direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700129 pci_pci_problems |= PCIPCI_FAIL;
130 }
131}
Andrew Morton652c5382007-11-21 15:07:13 -0800132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_5597, quirk_nopcipci);
133DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_496, quirk_nopcipci);
Alan Cox236561e2006-09-30 23:27:03 -0700134
Bill Pemberton15856ad2012-11-21 15:35:00 -0500135static void quirk_nopciamd(struct pci_dev *dev)
Alan Cox236561e2006-09-30 23:27:03 -0700136{
137 u8 rev;
138 pci_read_config_byte(dev, 0x08, &rev);
139 if (rev == 0x13) {
140 /* Erratum 24 */
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700141 dev_info(&dev->dev, "Chipset erratum: Disabling direct PCI/AGP transfers\n");
Alan Cox236561e2006-09-30 23:27:03 -0700142 pci_pci_problems |= PCIAGP_FAIL;
143 }
144}
Andrew Morton652c5382007-11-21 15:07:13 -0800145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8151_0, quirk_nopciamd);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700146
147/*
148 * Triton requires workarounds to be used by the drivers
149 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500150static void quirk_triton(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700151{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400152 if ((pci_pci_problems&PCIPCI_TRITON) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700153 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700154 pci_pci_problems |= PCIPCI_TRITON;
155 }
156}
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437, quirk_triton);
158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82437VX, quirk_triton);
159DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439, quirk_triton);
160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82439TX, quirk_triton);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700161
162/*
163 * VIA Apollo KT133 needs PCI latency patch
164 * Made according to a windows driver based patch by George E. Breese
165 * see PCI Latency Adjust on http://www.viahardware.com/download/viatweak.shtm
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400166 * Also see http://www.au-ja.org/review-kt133a-1-en.phtml for
167 * the info on which Mr Breese based his work.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700168 *
169 * Updated based on further information from the site and also on
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700170 * information provided by VIA
Linus Torvalds1da177e2005-04-16 15:20:36 -0700171 */
Alan Cox1597cac2006-12-04 15:14:45 -0800172static void quirk_vialatency(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700173{
174 struct pci_dev *p;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175 u8 busarb;
176 /* Ok we have a potential problem chipset here. Now see if we have
177 a buggy southbridge */
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700178
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, NULL);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400180 if (p != NULL) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 /* 0x40 - 0x4f == 686B, 0x10 - 0x2f == 686A; thanks Dan Hollis */
182 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700183 if (p->revision < 0x40 || p->revision > 0x42)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700184 goto exit;
185 } else {
186 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, NULL);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400187 if (p == NULL) /* No problem parts */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700188 goto exit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700189 /* Check for buggy part revisions */
Auke Kok2b1afa82007-10-29 14:55:02 -0700190 if (p->revision < 0x10 || p->revision > 0x12)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700191 goto exit;
192 }
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700193
Linus Torvalds1da177e2005-04-16 15:20:36 -0700194 /*
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700195 * Ok we have the problem. Now set the PCI master grant to
Linus Torvalds1da177e2005-04-16 15:20:36 -0700196 * occur every master grant. The apparent bug is that under high
197 * PCI load (quite common in Linux of course) you can get data
198 * loss when the CPU is held off the bus for 3 bus master requests
199 * This happens to include the IDE controllers....
200 *
201 * VIA only apply this fix when an SB Live! is present but under
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300202 * both Linux and Windows this isn't enough, and we have seen
Linus Torvalds1da177e2005-04-16 15:20:36 -0700203 * corruption without SB Live! but with things like 3 UDMA IDE
204 * controllers. So we ignore that bit of the VIA recommendation..
205 */
206
207 pci_read_config_byte(dev, 0x76, &busarb);
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700208 /* Set bit 4 and bi 5 of byte 76 to 0x01
Linus Torvalds1da177e2005-04-16 15:20:36 -0700209 "Master priority rotation on every PCI master grant */
210 busarb &= ~(1<<5);
211 busarb |= (1<<4);
212 pci_write_config_byte(dev, 0x76, busarb);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700213 dev_info(&dev->dev, "Applying VIA southbridge workaround\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700214exit:
215 pci_dev_put(p);
216}
Andrew Morton652c5382007-11-21 15:07:13 -0800217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
218DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Alan Cox1597cac2006-12-04 15:14:45 -0800220/* Must restore this on a resume from RAM */
Andrew Morton652c5382007-11-21 15:07:13 -0800221DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8363_0, quirk_vialatency);
222DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8371_1, quirk_vialatency);
223DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8361, quirk_vialatency);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700224
225/*
226 * VIA Apollo VP3 needs ETBF on BT848/878
227 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500228static void quirk_viaetbf(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700229{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400230 if ((pci_pci_problems&PCIPCI_VIAETBF) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700231 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 pci_pci_problems |= PCIPCI_VIAETBF;
233 }
234}
Andrew Morton652c5382007-11-21 15:07:13 -0800235DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_viaetbf);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700236
Bill Pemberton15856ad2012-11-21 15:35:00 -0500237static void quirk_vsfx(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700238{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400239 if ((pci_pci_problems&PCIPCI_VSFX) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700240 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 pci_pci_problems |= PCIPCI_VSFX;
242 }
243}
Andrew Morton652c5382007-11-21 15:07:13 -0800244DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C576, quirk_vsfx);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700245
246/*
247 * Ali Magik requires workarounds to be used by the drivers
248 * that DMA to AGP space. Latency must be set to 0xA and triton
249 * workaround applied too
250 * [Info kindly provided by ALi]
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700251 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500252static void quirk_alimagik(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400254 if ((pci_pci_problems&PCIPCI_ALIMAGIK) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700255 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700256 pci_pci_problems |= PCIPCI_ALIMAGIK|PCIPCI_TRITON;
257 }
258}
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700259DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1647, quirk_alimagik);
260DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M1651, quirk_alimagik);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700261
262/*
263 * Natoma has some interesting boundary conditions with Zoran stuff
264 * at least
265 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500266static void quirk_natoma(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400268 if ((pci_pci_problems&PCIPCI_NATOMA) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700269 dev_info(&dev->dev, "Limiting direct PCI/PCI transfers\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700270 pci_pci_problems |= PCIPCI_NATOMA;
271 }
272}
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700273DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441, quirk_natoma);
274DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_0, quirk_natoma);
275DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX_1, quirk_natoma);
276DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_0, quirk_natoma);
277DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_1, quirk_natoma);
278DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_2, quirk_natoma);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700279
280/*
281 * This chip can cause PCI parity errors if config register 0xA0 is read
282 * while DMAs are occurring.
283 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500284static void quirk_citrine(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700285{
286 dev->cfg_size = 0xA0;
287}
Andrew Morton652c5382007-11-21 15:07:13 -0800288DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, PCI_DEVICE_ID_IBM_CITRINE, quirk_citrine);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700289
Jason S. McMullan9f33a2a2015-09-30 15:35:07 +0900290/*
291 * This chip can cause bus lockups if config addresses above 0x600
292 * are read or written.
293 */
294static void quirk_nfp6000(struct pci_dev *dev)
295{
296 dev->cfg_size = 0x600;
297}
Simon Hormanc2e771b2015-12-11 11:30:12 +0900298DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP4000, quirk_nfp6000);
Jason S. McMullan9f33a2a2015-09-30 15:35:07 +0900299DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000, quirk_nfp6000);
300DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NETRONOME, PCI_DEVICE_ID_NETRONOME_NFP6000_VF, quirk_nfp6000);
301
Douglas Lehr9fe373f2014-08-21 09:26:52 +1000302/* On IBM Crocodile ipr SAS adapters, expand BAR to system page size */
303static void quirk_extend_bar_to_page(struct pci_dev *dev)
304{
305 int i;
306
307 for (i = 0; i < PCI_STD_RESOURCE_END; i++) {
308 struct resource *r = &dev->resource[i];
309
310 if (r->flags & IORESOURCE_MEM && resource_size(r) < PAGE_SIZE) {
311 r->end = PAGE_SIZE - 1;
312 r->start = 0;
313 r->flags |= IORESOURCE_UNSET;
314 dev_info(&dev->dev, "expanded BAR %d to page size: %pR\n",
315 i, r);
316 }
317 }
318}
319DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_IBM, 0x034a, quirk_extend_bar_to_page);
320
Linus Torvalds1da177e2005-04-16 15:20:36 -0700321/*
322 * S3 868 and 968 chips report region size equal to 32M, but they decode 64M.
323 * If it's needed, re-allocate the region.
324 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500325static void quirk_s3_64M(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700326{
327 struct resource *r = &dev->resource[0];
328
329 if ((r->start & 0x3ffffff) || r->end != r->start + 0x3ffffff) {
Bjorn Helgaasbd064f02014-02-26 11:25:58 -0700330 r->flags |= IORESOURCE_UNSET;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700331 r->start = 0;
332 r->end = 0x3ffffff;
333 }
334}
Andrew Morton652c5382007-11-21 15:07:13 -0800335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_868, quirk_s3_64M);
336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_S3, PCI_DEVICE_ID_S3_968, quirk_s3_64M);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700337
Myron Stowe06cf35f2015-02-03 16:01:24 -0700338static void quirk_io(struct pci_dev *dev, int pos, unsigned size,
339 const char *name)
340{
341 u32 region;
342 struct pci_bus_region bus_region;
343 struct resource *res = dev->resource + pos;
344
345 pci_read_config_dword(dev, PCI_BASE_ADDRESS_0 + (pos << 2), &region);
346
347 if (!region)
348 return;
349
350 res->name = pci_name(dev);
351 res->flags = region & ~PCI_BASE_ADDRESS_IO_MASK;
352 res->flags |=
353 (IORESOURCE_IO | IORESOURCE_PCI_FIXED | IORESOURCE_SIZEALIGN);
354 region &= ~(size - 1);
355
356 /* Convert from PCI bus to resource space */
357 bus_region.start = region;
358 bus_region.end = region + size - 1;
359 pcibios_bus_to_resource(dev->bus, res, &bus_region);
360
361 dev_info(&dev->dev, FW_BUG "%s quirk: reg 0x%x: %pR\n",
362 name, PCI_BASE_ADDRESS_0 + (pos << 2), res);
363}
364
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500365/*
366 * Some CS5536 BIOSes (for example, the Soekris NET5501 board w/ comBIOS
367 * ver. 1.33 20070103) don't set the correct ISA PCI region header info.
368 * BAR0 should be 8 bytes; instead, it may be set to something like 8k
369 * (which conflicts w/ BAR1's memory range).
Myron Stowe06cf35f2015-02-03 16:01:24 -0700370 *
371 * CS553x's ISA PCI BARs may also be read-only (ref:
372 * https://bugzilla.kernel.org/show_bug.cgi?id=85991 - Comment #4 forward).
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500373 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500374static void quirk_cs5536_vsa(struct pci_dev *dev)
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500375{
Myron Stowe06cf35f2015-02-03 16:01:24 -0700376 static char *name = "CS5536 ISA bridge";
377
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500378 if (pci_resource_len(dev, 0) != 8) {
Myron Stowe06cf35f2015-02-03 16:01:24 -0700379 quirk_io(dev, 0, 8, name); /* SMB */
380 quirk_io(dev, 1, 256, name); /* GPIO */
381 quirk_io(dev, 2, 64, name); /* MFGPT */
382 dev_info(&dev->dev, "%s bug detected (incorrect header); workaround applied\n",
383 name);
Andres Salomon73d2eaa2010-02-05 01:42:43 -0500384 }
385}
386DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_CS5536_ISA, quirk_cs5536_vsa);
387
Yinghai Lu65195c72013-04-12 12:44:15 +0000388static void quirk_io_region(struct pci_dev *dev, int port,
389 unsigned size, int nr, const char *name)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700390{
Yinghai Lu65195c72013-04-12 12:44:15 +0000391 u16 region;
392 struct pci_bus_region bus_region;
393 struct resource *res = dev->resource + nr;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700394
Yinghai Lu65195c72013-04-12 12:44:15 +0000395 pci_read_config_word(dev, port, &region);
396 region &= ~(size - 1);
David S. Miller085ae412005-08-08 13:19:08 -0700397
Yinghai Lu65195c72013-04-12 12:44:15 +0000398 if (!region)
399 return;
David S. Miller085ae412005-08-08 13:19:08 -0700400
Yinghai Lu65195c72013-04-12 12:44:15 +0000401 res->name = pci_name(dev);
402 res->flags = IORESOURCE_IO;
403
404 /* Convert from PCI bus to resource space */
405 bus_region.start = region;
406 bus_region.end = region + size - 1;
Yinghai Lufc279852013-12-09 22:54:40 -0800407 pcibios_bus_to_resource(dev->bus, res, &bus_region);
Yinghai Lu65195c72013-04-12 12:44:15 +0000408
409 if (!pci_claim_resource(dev, nr))
410 dev_info(&dev->dev, "quirk: %pR claimed by %s\n", res, name);
411}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700412
413/*
414 * ATI Northbridge setups MCE the processor if you even
415 * read somewhere between 0x3b0->0x3bb or read 0x3d3
416 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500417static void quirk_ati_exploding_mce(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700418{
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700419 dev_info(&dev->dev, "ATI Northbridge, reserving I/O ports 0x3b0 to 0x3bb\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700420 /* Mae rhaid i ni beidio ag edrych ar y lleoliadiau I/O hyn */
421 request_region(0x3b0, 0x0C, "RadeonIGP");
422 request_region(0x3d3, 0x01, "RadeonIGP");
423}
Andrew Morton652c5382007-11-21 15:07:13 -0800424DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS100, quirk_ati_exploding_mce);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700425
426/*
Huang Ruibe6646b2014-10-31 11:11:16 +0800427 * In the AMD NL platform, this device ([1022:7912]) has a class code of
428 * PCI_CLASS_SERIAL_USB_XHCI (0x0c0330), which means the xhci driver will
429 * claim it.
430 * But the dwc3 driver is a more specific driver for this device, and we'd
431 * prefer to use it instead of xhci. To prevent xhci from claiming the
432 * device, change the class code to 0x0c03fe, which the PCI r3.0 spec
433 * defines as "USB device (not host controller)". The dwc3 driver can then
434 * claim it based on its Vendor and Device ID.
435 */
436static void quirk_amd_nl_class(struct pci_dev *pdev)
437{
Bjorn Helgaascd76d102015-06-19 15:28:31 -0500438 u32 class = pdev->class;
439
440 /* Use "USB Device (not host controller)" class */
Heikki Krogerus7b78f482016-03-15 14:06:00 +0200441 pdev->class = PCI_CLASS_SERIAL_USB_DEVICE;
Bjorn Helgaascd76d102015-06-19 15:28:31 -0500442 dev_info(&pdev->dev, "PCI class overridden (%#08x -> %#08x) so dwc3 driver can claim this instead of xhci\n",
443 class, pdev->class);
Huang Ruibe6646b2014-10-31 11:11:16 +0800444}
445DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_NL_USB,
446 quirk_amd_nl_class);
447
448/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449 * Let's make the southbridge information explicit instead
450 * of having to worry about people probing the ACPI areas,
451 * for example.. (Yes, it happens, and if you read the wrong
452 * ACPI register it will put the machine to sleep with no
453 * way of waking it up again. Bummer).
454 *
455 * ALI M7101: Two IO regions pointed to by words at
456 * 0xE0 (64 bytes of ACPI registers)
457 * 0xE2 (32 bytes of SMB registers)
458 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500459static void quirk_ali7101_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700460{
Yinghai Lu65195c72013-04-12 12:44:15 +0000461 quirk_io_region(dev, 0xE0, 64, PCI_BRIDGE_RESOURCES, "ali7101 ACPI");
462 quirk_io_region(dev, 0xE2, 32, PCI_BRIDGE_RESOURCES+1, "ali7101 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700463}
Andrew Morton652c5382007-11-21 15:07:13 -0800464DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AL, PCI_DEVICE_ID_AL_M7101, quirk_ali7101_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700465
Linus Torvalds6693e742005-10-25 20:40:09 -0700466static void piix4_io_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
467{
468 u32 devres;
469 u32 mask, size, base;
470
471 pci_read_config_dword(dev, port, &devres);
472 if ((devres & enable) != enable)
473 return;
474 mask = (devres >> 16) & 15;
475 base = devres & 0xffff;
476 size = 16;
477 for (;;) {
478 unsigned bit = size >> 1;
479 if ((bit & mask) == bit)
480 break;
481 size = bit;
482 }
483 /*
484 * For now we only print it out. Eventually we'll want to
485 * reserve it (at least if it's in the 0x1000+ range), but
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700486 * let's get enough confirmation reports first.
Linus Torvalds6693e742005-10-25 20:40:09 -0700487 */
488 base &= -size;
Ryan Desfosses227f0642014-04-18 20:13:50 -0400489 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base,
490 base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700491}
492
493static void piix4_mem_quirk(struct pci_dev *dev, const char *name, unsigned int port, unsigned int enable)
494{
495 u32 devres;
496 u32 mask, size, base;
497
498 pci_read_config_dword(dev, port, &devres);
499 if ((devres & enable) != enable)
500 return;
501 base = devres & 0xffff0000;
502 mask = (devres & 0x3f) << 16;
503 size = 128 << 16;
504 for (;;) {
505 unsigned bit = size >> 1;
506 if ((bit & mask) == bit)
507 break;
508 size = bit;
509 }
510 /*
511 * For now we only print it out. Eventually we'll want to
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700512 * reserve it, but let's get enough confirmation reports first.
Linus Torvalds6693e742005-10-25 20:40:09 -0700513 */
514 base &= -size;
Ryan Desfosses227f0642014-04-18 20:13:50 -0400515 dev_info(&dev->dev, "%s MMIO at %04x-%04x\n", name, base,
516 base + size - 1);
Linus Torvalds6693e742005-10-25 20:40:09 -0700517}
518
Linus Torvalds1da177e2005-04-16 15:20:36 -0700519/*
520 * PIIX4 ACPI: Two IO regions pointed to by longwords at
521 * 0x40 (64 bytes of ACPI registers)
Linus Torvalds08db2a72005-10-30 14:40:07 -0800522 * 0x90 (16 bytes of SMB registers)
Linus Torvalds6693e742005-10-25 20:40:09 -0700523 * and a few strange programmable PIIX4 device resources.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700524 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500525static void quirk_piix4_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700526{
Yinghai Lu65195c72013-04-12 12:44:15 +0000527 u32 res_a;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700528
Yinghai Lu65195c72013-04-12 12:44:15 +0000529 quirk_io_region(dev, 0x40, 64, PCI_BRIDGE_RESOURCES, "PIIX4 ACPI");
530 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+1, "PIIX4 SMB");
Linus Torvalds6693e742005-10-25 20:40:09 -0700531
532 /* Device resource A has enables for some of the other ones */
533 pci_read_config_dword(dev, 0x5c, &res_a);
534
535 piix4_io_quirk(dev, "PIIX4 devres B", 0x60, 3 << 21);
536 piix4_io_quirk(dev, "PIIX4 devres C", 0x64, 3 << 21);
537
538 /* Device resource D is just bitfields for static resources */
539
540 /* Device 12 enabled? */
541 if (res_a & (1 << 29)) {
542 piix4_io_quirk(dev, "PIIX4 devres E", 0x68, 1 << 20);
543 piix4_mem_quirk(dev, "PIIX4 devres F", 0x6c, 1 << 7);
544 }
545 /* Device 13 enabled? */
546 if (res_a & (1 << 30)) {
547 piix4_io_quirk(dev, "PIIX4 devres G", 0x70, 1 << 20);
548 piix4_mem_quirk(dev, "PIIX4 devres H", 0x74, 1 << 7);
549 }
550 piix4_io_quirk(dev, "PIIX4 devres I", 0x78, 1 << 20);
551 piix4_io_quirk(dev, "PIIX4 devres J", 0x7c, 1 << 20);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700552}
Andrew Morton652c5382007-11-21 15:07:13 -0800553DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3, quirk_piix4_acpi);
554DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3, quirk_piix4_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700555
Jiri Slabycdb97552011-02-28 10:45:09 +0100556#define ICH_PMBASE 0x40
557#define ICH_ACPI_CNTL 0x44
558#define ICH4_ACPI_EN 0x10
559#define ICH6_ACPI_EN 0x80
560#define ICH4_GPIOBASE 0x58
561#define ICH4_GPIO_CNTL 0x5c
562#define ICH4_GPIO_EN 0x10
563#define ICH6_GPIOBASE 0x48
564#define ICH6_GPIO_CNTL 0x4c
565#define ICH6_GPIO_EN 0x10
566
Linus Torvalds1da177e2005-04-16 15:20:36 -0700567/*
568 * ICH4, ICH4-M, ICH5, ICH5-M ACPI: Three IO regions pointed to by longwords at
569 * 0x40 (128 bytes of ACPI, GPIO & TCO registers)
570 * 0x58 (64 bytes of GPIO I/O space)
571 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500572static void quirk_ich4_lpc_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700573{
Jiri Slabycdb97552011-02-28 10:45:09 +0100574 u8 enable;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700575
Jiri Slaby87e3dc32011-02-28 10:45:10 +0100576 /*
577 * The check for PCIBIOS_MIN_IO is to ensure we won't create a conflict
578 * with low legacy (and fixed) ports. We don't know the decoding
579 * priority and can't tell whether the legacy device or the one created
580 * here is really at that address. This happens on boards with broken
581 * BIOSes.
582 */
583
Jiri Slabycdb97552011-02-28 10:45:09 +0100584 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000585 if (enable & ICH4_ACPI_EN)
586 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
587 "ICH4 ACPI/GPIO/TCO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700588
Jiri Slabycdb97552011-02-28 10:45:09 +0100589 pci_read_config_byte(dev, ICH4_GPIO_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000590 if (enable & ICH4_GPIO_EN)
591 quirk_io_region(dev, ICH4_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
592 "ICH4 GPIO");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700593}
Andrew Morton652c5382007-11-21 15:07:13 -0800594DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, quirk_ich4_lpc_acpi);
595DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_0, quirk_ich4_lpc_acpi);
596DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, quirk_ich4_lpc_acpi);
597DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_10, quirk_ich4_lpc_acpi);
598DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, quirk_ich4_lpc_acpi);
599DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, quirk_ich4_lpc_acpi);
600DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, quirk_ich4_lpc_acpi);
601DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, quirk_ich4_lpc_acpi);
602DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, quirk_ich4_lpc_acpi);
603DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_1, quirk_ich4_lpc_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700604
Bill Pemberton15856ad2012-11-21 15:35:00 -0500605static void ich6_lpc_acpi_gpio(struct pci_dev *dev)
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000606{
Jiri Slabycdb97552011-02-28 10:45:09 +0100607 u8 enable;
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000608
Jiri Slabycdb97552011-02-28 10:45:09 +0100609 pci_read_config_byte(dev, ICH_ACPI_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000610 if (enable & ICH6_ACPI_EN)
611 quirk_io_region(dev, ICH_PMBASE, 128, PCI_BRIDGE_RESOURCES,
612 "ICH6 ACPI/GPIO/TCO");
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000613
Jiri Slabycdb97552011-02-28 10:45:09 +0100614 pci_read_config_byte(dev, ICH6_GPIO_CNTL, &enable);
Yinghai Lu65195c72013-04-12 12:44:15 +0000615 if (enable & ICH6_GPIO_EN)
616 quirk_io_region(dev, ICH6_GPIOBASE, 64, PCI_BRIDGE_RESOURCES+1,
617 "ICH6 GPIO");
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000618}
Linus Torvalds894886e2008-12-06 10:10:10 -0800619
Bill Pemberton15856ad2012-11-21 15:35:00 -0500620static void ich6_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name, int dynsize)
Linus Torvalds894886e2008-12-06 10:10:10 -0800621{
622 u32 val;
623 u32 size, base;
624
625 pci_read_config_dword(dev, reg, &val);
626
627 /* Enabled? */
628 if (!(val & 1))
629 return;
630 base = val & 0xfffc;
631 if (dynsize) {
632 /*
633 * This is not correct. It is 16, 32 or 64 bytes depending on
634 * register D31:F0:ADh bits 5:4.
635 *
636 * But this gets us at least _part_ of it.
637 */
638 size = 16;
639 } else {
640 size = 128;
641 }
642 base &= ~(size-1);
643
644 /* Just print it out for now. We should reserve it after more debugging */
645 dev_info(&dev->dev, "%s PIO at %04x-%04x\n", name, base, base+size-1);
646}
647
Bill Pemberton15856ad2012-11-21 15:35:00 -0500648static void quirk_ich6_lpc(struct pci_dev *dev)
Linus Torvalds894886e2008-12-06 10:10:10 -0800649{
650 /* Shared ACPI/GPIO decode with all ICH6+ */
651 ich6_lpc_acpi_gpio(dev);
652
653 /* ICH6-specific generic IO decode */
654 ich6_lpc_generic_decode(dev, 0x84, "LPC Generic IO decode 1", 0);
655 ich6_lpc_generic_decode(dev, 0x88, "LPC Generic IO decode 2", 1);
656}
657DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_0, quirk_ich6_lpc);
658DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, quirk_ich6_lpc);
659
Bill Pemberton15856ad2012-11-21 15:35:00 -0500660static void ich7_lpc_generic_decode(struct pci_dev *dev, unsigned reg, const char *name)
Linus Torvalds894886e2008-12-06 10:10:10 -0800661{
662 u32 val;
663 u32 mask, base;
664
665 pci_read_config_dword(dev, reg, &val);
666
667 /* Enabled? */
668 if (!(val & 1))
669 return;
670
671 /*
672 * IO base in bits 15:2, mask in bits 23:18, both
673 * are dword-based
674 */
675 base = val & 0xfffc;
676 mask = (val >> 16) & 0xfc;
677 mask |= 3;
678
679 /* Just print it out for now. We should reserve it after more debugging */
680 dev_info(&dev->dev, "%s PIO at %04x (mask %04x)\n", name, base, mask);
681}
682
683/* ICH7-10 has the same common LPC generic IO decode registers */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500684static void quirk_ich7_lpc(struct pci_dev *dev)
Linus Torvalds894886e2008-12-06 10:10:10 -0800685{
Jean Delvare5d9c0a72011-04-15 10:03:53 +0200686 /* We share the common ACPI/GPIO decode with ICH6 */
Linus Torvalds894886e2008-12-06 10:10:10 -0800687 ich6_lpc_acpi_gpio(dev);
688
689 /* And have 4 ICH7+ generic decodes */
690 ich7_lpc_generic_decode(dev, 0x84, "ICH7 LPC Generic IO decode 1");
691 ich7_lpc_generic_decode(dev, 0x88, "ICH7 LPC Generic IO decode 2");
692 ich7_lpc_generic_decode(dev, 0x8c, "ICH7 LPC Generic IO decode 3");
693 ich7_lpc_generic_decode(dev, 0x90, "ICH7 LPC Generic IO decode 4");
694}
695DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_0, quirk_ich7_lpc);
696DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_1, quirk_ich7_lpc);
697DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_31, quirk_ich7_lpc);
698DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_0, quirk_ich7_lpc);
699DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_2, quirk_ich7_lpc);
700DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_3, quirk_ich7_lpc);
701DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_1, quirk_ich7_lpc);
702DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_4, quirk_ich7_lpc);
703DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_2, quirk_ich7_lpc);
704DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_4, quirk_ich7_lpc);
705DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_7, quirk_ich7_lpc);
706DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_8, quirk_ich7_lpc);
707DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_1, quirk_ich7_lpc);
R.Marek@sh.cvut.cz2cea7522005-09-27 21:54:51 +0000708
Linus Torvalds1da177e2005-04-16 15:20:36 -0700709/*
710 * VIA ACPI: One IO region pointed to by longword at
711 * 0x48 or 0x20 (256 bytes of ACPI registers)
712 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500713static void quirk_vt82c586_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700714{
Yinghai Lu65195c72013-04-12 12:44:15 +0000715 if (dev->revision & 0x10)
716 quirk_io_region(dev, 0x48, 256, PCI_BRIDGE_RESOURCES,
717 "vt82c586 ACPI");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700718}
Andrew Morton652c5382007-11-21 15:07:13 -0800719DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_vt82c586_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700720
721/*
722 * VIA VT82C686 ACPI: Three IO region pointed to by (long)words at
723 * 0x48 (256 bytes of ACPI registers)
724 * 0x70 (128 bytes of hardware monitoring register)
725 * 0x90 (16 bytes of SMB registers)
726 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500727static void quirk_vt82c686_acpi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700728{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729 quirk_vt82c586_acpi(dev);
730
Yinghai Lu65195c72013-04-12 12:44:15 +0000731 quirk_io_region(dev, 0x70, 128, PCI_BRIDGE_RESOURCES+1,
732 "vt82c686 HW-mon");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733
Yinghai Lu65195c72013-04-12 12:44:15 +0000734 quirk_io_region(dev, 0x90, 16, PCI_BRIDGE_RESOURCES+2, "vt82c686 SMB");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700735}
Andrew Morton652c5382007-11-21 15:07:13 -0800736DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_vt82c686_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700737
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400738/*
739 * VIA VT8235 ISA Bridge: Two IO regions pointed to by words at
740 * 0x88 (128 bytes of power management registers)
741 * 0xd0 (16 bytes of SMB registers)
742 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500743static void quirk_vt8235_acpi(struct pci_dev *dev)
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400744{
Yinghai Lu65195c72013-04-12 12:44:15 +0000745 quirk_io_region(dev, 0x88, 128, PCI_BRIDGE_RESOURCES, "vt8235 PM");
746 quirk_io_region(dev, 0xd0, 16, PCI_BRIDGE_RESOURCES+1, "vt8235 SMB");
Ivan Kokshaysky6d85f292005-08-08 12:55:54 +0400747}
748DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_vt8235_acpi);
749
Gabe Black1f56f4a2009-10-06 09:19:45 -0500750/*
751 * TI XIO2000a PCIe-PCI Bridge erroneously reports it supports fast back-to-back:
752 * Disable fast back-to-back on the secondary bus segment
753 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500754static void quirk_xio2000a(struct pci_dev *dev)
Gabe Black1f56f4a2009-10-06 09:19:45 -0500755{
756 struct pci_dev *pdev;
757 u16 command;
758
Ryan Desfosses227f0642014-04-18 20:13:50 -0400759 dev_warn(&dev->dev, "TI XIO2000a quirk detected; secondary bus fast back-to-back transfers disabled\n");
Gabe Black1f56f4a2009-10-06 09:19:45 -0500760 list_for_each_entry(pdev, &dev->subordinate->devices, bus_list) {
761 pci_read_config_word(pdev, PCI_COMMAND, &command);
762 if (command & PCI_COMMAND_FAST_BACK)
763 pci_write_config_word(pdev, PCI_COMMAND, command & ~PCI_COMMAND_FAST_BACK);
764 }
765}
766DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_XIO2000A,
767 quirk_xio2000a);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700768
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700769#ifdef CONFIG_X86_IO_APIC
Linus Torvalds1da177e2005-04-16 15:20:36 -0700770
771#include <asm/io_apic.h>
772
773/*
774 * VIA 686A/B: If an IO-APIC is active, we need to route all on-chip
775 * devices to the external APIC.
776 *
777 * TODO: When we have device-specific interrupt routers,
778 * this code will go away from quirks.
779 */
Alan Cox1597cac2006-12-04 15:14:45 -0800780static void quirk_via_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700781{
782 u8 tmp;
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700783
Linus Torvalds1da177e2005-04-16 15:20:36 -0700784 if (nr_ioapics < 1)
785 tmp = 0; /* nothing routed to external APIC */
786 else
787 tmp = 0x1f; /* all known bits (4-0) routed to external APIC */
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700788
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700789 dev_info(&dev->dev, "%sbling VIA external APIC routing\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -0700790 tmp == 0 ? "Disa" : "Ena");
791
792 /* Offset 0x58: External APIC IRQ output control */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400793 pci_write_config_byte(dev, 0x58, tmp);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700794}
Andrew Morton652c5382007-11-21 15:07:13 -0800795DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200796DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700797
798/*
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700799 * VIA 8237: Some BIOSes don't set the 'Bypass APIC De-Assert Message' Bit.
Karsten Wiesea1740912005-09-03 15:56:33 -0700800 * This leads to doubled level interrupt rates.
801 * Set this bit to get rid of cycle wastage.
802 * Otherwise uncritical.
803 */
Alan Cox1597cac2006-12-04 15:14:45 -0800804static void quirk_via_vt8237_bypass_apic_deassert(struct pci_dev *dev)
Karsten Wiesea1740912005-09-03 15:56:33 -0700805{
806 u8 misc_control2;
807#define BYPASS_APIC_DEASSERT 8
808
809 pci_read_config_byte(dev, 0x5B, &misc_control2);
810 if (!(misc_control2 & BYPASS_APIC_DEASSERT)) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700811 dev_info(&dev->dev, "Bypassing VIA 8237 APIC De-Assert Message\n");
Karsten Wiesea1740912005-09-03 15:56:33 -0700812 pci_write_config_byte(dev, 0x5B, misc_control2|BYPASS_APIC_DEASSERT);
813 }
814}
815DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +0200816DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_vt8237_bypass_apic_deassert);
Karsten Wiesea1740912005-09-03 15:56:33 -0700817
818/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819 * The AMD io apic can hang the box when an apic irq is masked.
820 * We check all revs >= B0 (yet not in the pre production!) as the bug
821 * is currently marked NoFix
822 *
823 * We have multiple reports of hangs with this chipset that went away with
Alan Cox236561e2006-09-30 23:27:03 -0700824 * noapic specified. For the moment we assume it's the erratum. We may be wrong
Linus Torvalds1da177e2005-04-16 15:20:36 -0700825 * of course. However the advice is demonstrably good even if so..
826 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500827static void quirk_amd_ioapic(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700828{
Auke Kok44c10132007-06-08 15:46:36 -0700829 if (dev->revision >= 0x02) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700830 dev_warn(&dev->dev, "I/O APIC: AMD Erratum #22 may be present. In the event of instability try\n");
831 dev_warn(&dev->dev, " : booting with the \"noapic\" option\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -0700832 }
833}
Andrew Morton652c5382007-11-21 15:07:13 -0800834DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_VIPER_7410, quirk_amd_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700835#endif /* CONFIG_X86_IO_APIC */
836
Herbert Xu0bec90572016-09-05 17:12:57 +0800837#if defined(CONFIG_ARM64) && defined(CONFIG_PCI_ATS)
Ananth Jasty21b5b8e2016-08-23 16:27:14 -0700838
839static void quirk_cavium_sriov_rnm_link(struct pci_dev *dev)
840{
841 /* Fix for improper SRIOV configuration on Cavium cn88xx RNM device */
842 if (dev->subsystem_device == 0xa118)
843 dev->sriov->link = dev->devfn;
844}
845DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CAVIUM, 0xa018, quirk_cavium_sriov_rnm_link);
846#endif
847
Peter Orubad556ad42007-05-15 13:59:13 +0200848/*
849 * Some settings of MMRBC can lead to data corruption so block changes.
850 * See AMD 8131 HyperTransport PCI-X Tunnel Revision Guide
851 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500852static void quirk_amd_8131_mmrbc(struct pci_dev *dev)
Peter Orubad556ad42007-05-15 13:59:13 +0200853{
Auke Kokaa288d42007-08-27 16:17:47 -0700854 if (dev->subordinate && dev->revision <= 0x12) {
Ryan Desfosses227f0642014-04-18 20:13:50 -0400855 dev_info(&dev->dev, "AMD8131 rev %x detected; disabling PCI-X MMRBC\n",
856 dev->revision);
Peter Orubad556ad42007-05-15 13:59:13 +0200857 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MMRBC;
858 }
859}
860DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_amd_8131_mmrbc);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700861
862/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700863 * FIXME: it is questionable that quirk_via_acpi
864 * is needed. It shows up as an ISA bridge, and does not
865 * support the PCI_INTERRUPT_LINE register at all. Therefore
866 * it seems like setting the pci_dev's 'irq' to the
867 * value of the ACPI SCI interrupt is only done for convenience.
868 * -jgarzik
869 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500870static void quirk_via_acpi(struct pci_dev *d)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700871{
872 /*
873 * VIA ACPI device: SCI IRQ line in PCI config byte 0x42
874 */
875 u8 irq;
876 pci_read_config_byte(d, 0x42, &irq);
877 irq &= 0xf;
878 if (irq && (irq != 2))
879 d->irq = irq;
880}
Andrew Morton652c5382007-11-21 15:07:13 -0800881DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C586_3, quirk_via_acpi);
882DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686_4, quirk_via_acpi);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700883
Daniel Drake09d60292006-09-25 16:52:19 -0700884
885/*
Alan Cox1597cac2006-12-04 15:14:45 -0800886 * VIA bridges which have VLink
Daniel Drake09d60292006-09-25 16:52:19 -0700887 */
Alan Cox1597cac2006-12-04 15:14:45 -0800888
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800889static int via_vlink_dev_lo = -1, via_vlink_dev_hi = 18;
890
891static void quirk_via_bridge(struct pci_dev *dev)
892{
893 /* See what bridge we have and find the device ranges */
894 switch (dev->device) {
895 case PCI_DEVICE_ID_VIA_82C686:
Jean Delvarecb7468e2007-01-31 23:48:12 -0800896 /* The VT82C686 is special, it attaches to PCI and can have
897 any device number. All its subdevices are functions of
898 that single device. */
899 via_vlink_dev_lo = PCI_SLOT(dev->devfn);
900 via_vlink_dev_hi = PCI_SLOT(dev->devfn);
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800901 break;
902 case PCI_DEVICE_ID_VIA_8237:
903 case PCI_DEVICE_ID_VIA_8237A:
904 via_vlink_dev_lo = 15;
905 break;
906 case PCI_DEVICE_ID_VIA_8235:
907 via_vlink_dev_lo = 16;
908 break;
909 case PCI_DEVICE_ID_VIA_8231:
910 case PCI_DEVICE_ID_VIA_8233_0:
911 case PCI_DEVICE_ID_VIA_8233A:
912 case PCI_DEVICE_ID_VIA_8233C_0:
913 via_vlink_dev_lo = 17;
914 break;
915 }
916}
917DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686, quirk_via_bridge);
918DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8231, quirk_via_bridge);
919DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233_0, quirk_via_bridge);
920DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233A, quirk_via_bridge);
921DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8233C_0, quirk_via_bridge);
922DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235, quirk_via_bridge);
923DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, quirk_via_bridge);
924DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237A, quirk_via_bridge);
Daniel Drake09d60292006-09-25 16:52:19 -0700925
Alan Cox1597cac2006-12-04 15:14:45 -0800926/**
927 * quirk_via_vlink - VIA VLink IRQ number update
928 * @dev: PCI device
929 *
930 * If the device we are dealing with is on a PIC IRQ we need to
931 * ensure that the IRQ line register which usually is not relevant
932 * for PCI cards, is actually written so that interrupts get sent
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800933 * to the right place.
934 * We only do this on systems where a VIA south bridge was detected,
935 * and only for VIA devices on the motherboard (see quirk_via_bridge
936 * above).
Alan Cox1597cac2006-12-04 15:14:45 -0800937 */
938
939static void quirk_via_vlink(struct pci_dev *dev)
Len Brown25be5e62005-05-27 04:21:50 -0400940{
941 u8 irq, new_irq;
942
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800943 /* Check if we have VLink at all */
944 if (via_vlink_dev_lo == -1)
Daniel Drake09d60292006-09-25 16:52:19 -0700945 return;
946
947 new_irq = dev->irq;
948
949 /* Don't quirk interrupts outside the legacy IRQ range */
950 if (!new_irq || new_irq > 15)
951 return;
952
Alan Cox1597cac2006-12-04 15:14:45 -0800953 /* Internal device ? */
Jean Delvarec06bb5d2007-01-30 14:36:09 -0800954 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) > via_vlink_dev_hi ||
955 PCI_SLOT(dev->devfn) < via_vlink_dev_lo)
Alan Cox1597cac2006-12-04 15:14:45 -0800956 return;
957
958 /* This is an internal VLink device on a PIC interrupt. The BIOS
959 ought to have set this but may not have, so we redo it */
960
Len Brown25be5e62005-05-27 04:21:50 -0400961 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
962 if (new_irq != irq) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -0700963 dev_info(&dev->dev, "VIA VLink IRQ fixup, from %d to %d\n",
964 irq, new_irq);
Len Brown25be5e62005-05-27 04:21:50 -0400965 udelay(15); /* unknown if delay really needed */
966 pci_write_config_byte(dev, PCI_INTERRUPT_LINE, new_irq);
967 }
968}
Alan Cox1597cac2006-12-04 15:14:45 -0800969DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_VIA, PCI_ANY_ID, quirk_via_vlink);
Len Brown25be5e62005-05-27 04:21:50 -0400970
Linus Torvalds1da177e2005-04-16 15:20:36 -0700971/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700972 * VIA VT82C598 has its device ID settable and many BIOSes
973 * set it to the ID of VT82C597 for backward compatibility.
974 * We need to switch it off to be able to recognize the real
975 * type of the chip.
976 */
Bill Pemberton15856ad2012-11-21 15:35:00 -0500977static void quirk_vt82c598_id(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700978{
979 pci_write_config_byte(dev, 0xfc, 0);
980 pci_read_config_word(dev, PCI_DEVICE_ID, &dev->device);
981}
Andrew Morton652c5382007-11-21 15:07:13 -0800982DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C597_0, quirk_vt82c598_id);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700983
984/*
985 * CardBus controllers have a legacy base address that enables them
986 * to respond as i82365 pcmcia controllers. We don't want them to
987 * do this even if the Linux CardBus driver is not loaded, because
988 * the Linux i82365 driver does not (and should not) handle CardBus.
989 */
Alan Cox1597cac2006-12-04 15:14:45 -0800990static void quirk_cardbus_legacy(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700991{
Linus Torvalds1da177e2005-04-16 15:20:36 -0700992 pci_write_config_dword(dev, PCI_CB_LEGACY_MODE_BASE, 0);
993}
Yinghai Luae9de562012-02-23 23:46:54 -0800994DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_ANY_ID, PCI_ANY_ID,
995 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
996DECLARE_PCI_FIXUP_CLASS_RESUME_EARLY(PCI_ANY_ID, PCI_ANY_ID,
997 PCI_CLASS_BRIDGE_CARDBUS, 8, quirk_cardbus_legacy);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700998
999/*
1000 * Following the PCI ordering rules is optional on the AMD762. I'm not
1001 * sure what the designers were smoking but let's not inhale...
1002 *
1003 * To be fair to AMD, it follows the spec by default, its BIOS people
1004 * who turn it off!
1005 */
Alan Cox1597cac2006-12-04 15:14:45 -08001006static void quirk_amd_ordering(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001007{
1008 u32 pcic;
1009 pci_read_config_dword(dev, 0x4C, &pcic);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001010 if ((pcic & 6) != 6) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001011 pcic |= 6;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001012 dev_warn(&dev->dev, "BIOS failed to enable PCI standards compliance; fixing this error\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001013 pci_write_config_dword(dev, 0x4C, pcic);
1014 pci_read_config_dword(dev, 0x84, &pcic);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001015 pcic |= (1 << 23); /* Required in this mode */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001016 pci_write_config_dword(dev, 0x84, pcic);
1017 }
1018}
Andrew Morton652c5382007-11-21 15:07:13 -08001019DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001020DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_FE_GATE_700C, quirk_amd_ordering);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001021
1022/*
1023 * DreamWorks provided workaround for Dunord I-3000 problem
1024 *
1025 * This card decodes and responds to addresses not apparently
1026 * assigned to it. We force a larger allocation to ensure that
1027 * nothing gets put too close to it.
1028 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001029static void quirk_dunord(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001030{
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001031 struct resource *r = &dev->resource[1];
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07001032
1033 r->flags |= IORESOURCE_UNSET;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001034 r->start = 0;
1035 r->end = 0xffffff;
1036}
Andrew Morton652c5382007-11-21 15:07:13 -08001037DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_DUNORD, PCI_DEVICE_ID_DUNORD_I3000, quirk_dunord);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001038
1039/*
1040 * i82380FB mobile docking controller: its PCI-to-PCI bridge
1041 * is subtractive decoding (transparent), and does indicate this
1042 * in the ProgIf. Unfortunately, the ProgIf value is wrong - 0x80
1043 * instead of 0x01.
1044 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001045static void quirk_transparent_bridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001046{
1047 dev->transparent = 1;
1048}
Andrew Morton652c5382007-11-21 15:07:13 -08001049DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82380FB, quirk_transparent_bridge);
1050DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA, 0x605, quirk_transparent_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001051
1052/*
1053 * Common misconfiguration of the MediaGX/Geode PCI master that will
1054 * reduce PCI bandwidth from 70MB/s to 25MB/s. See the GXM/GXLV/GX1
Justin P. Mattock631dd1a2010-10-18 11:03:14 +02001055 * datasheets found at http://www.national.com/analog for info on what
Linus Torvalds1da177e2005-04-16 15:20:36 -07001056 * these bits do. <christer@weinigel.se>
1057 */
Alan Cox1597cac2006-12-04 15:14:45 -08001058static void quirk_mediagx_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001059{
1060 u8 reg;
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001061
Linus Torvalds1da177e2005-04-16 15:20:36 -07001062 pci_read_config_byte(dev, 0x41, &reg);
1063 if (reg & 2) {
1064 reg &= ~2;
Ryan Desfosses227f0642014-04-18 20:13:50 -04001065 dev_info(&dev->dev, "Fixup for MediaGX/Geode Slave Disconnect Boundary (0x41=0x%02x)\n",
1066 reg);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001067 pci_write_config_byte(dev, 0x41, reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001068 }
1069}
Andrew Morton652c5382007-11-21 15:07:13 -08001070DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
1071DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_CYRIX, PCI_DEVICE_ID_CYRIX_PCI_MASTER, quirk_mediagx_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001072
1073/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001074 * Ensure C0 rev restreaming is off. This is normally done by
1075 * the BIOS but in the odd case it is not the results are corruption
1076 * hence the presence of a Linux check
1077 */
Alan Cox1597cac2006-12-04 15:14:45 -08001078static void quirk_disable_pxb(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001079{
1080 u16 config;
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001081
Auke Kok44c10132007-06-08 15:46:36 -07001082 if (pdev->revision != 0x04) /* Only C0 requires this */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001083 return;
1084 pci_read_config_word(pdev, 0x40, &config);
1085 if (config & (1<<6)) {
1086 config &= ~(1<<6);
1087 pci_write_config_word(pdev, 0x40, config);
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001088 dev_info(&pdev->dev, "C0 revision 450NX. Disabling PCI restreaming\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001089 }
1090}
Andrew Morton652c5382007-11-21 15:07:13 -08001091DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001092DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82454NX, quirk_disable_pxb);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001093
Myron Stowe25e742b2012-07-09 15:36:14 -06001094static void quirk_amd_ide_mode(struct pci_dev *pdev)
Conke Huab174432006-12-19 13:11:37 -08001095{
Shane Huang5deab532009-10-13 11:14:00 +08001096 /* set SBX00/Hudson-2 SATA in IDE mode to AHCI mode */
Crane Cai05a7d222008-02-02 13:56:56 +08001097 u8 tmp;
Conke Huab174432006-12-19 13:11:37 -08001098
Crane Cai05a7d222008-02-02 13:56:56 +08001099 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &tmp);
1100 if (tmp == 0x01) {
Conke Huab174432006-12-19 13:11:37 -08001101 pci_read_config_byte(pdev, 0x40, &tmp);
1102 pci_write_config_byte(pdev, 0x40, tmp|1);
1103 pci_write_config_byte(pdev, 0x9, 1);
1104 pci_write_config_byte(pdev, 0xa, 6);
1105 pci_write_config_byte(pdev, 0x40, tmp);
1106
Conke Huc9f89472007-01-09 05:32:51 -05001107 pdev->class = PCI_CLASS_STORAGE_SATA_AHCI;
Crane Cai05a7d222008-02-02 13:56:56 +08001108 dev_info(&pdev->dev, "set SATA to AHCI mode\n");
Conke Huab174432006-12-19 13:11:37 -08001109 }
1110}
Crane Cai05a7d222008-02-02 13:56:56 +08001111DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001112DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP600_SATA, quirk_amd_ide_mode);
Crane Cai05a7d222008-02-02 13:56:56 +08001113DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001114DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP700_SATA, quirk_amd_ide_mode);
Shane Huang5deab532009-10-13 11:14:00 +08001115DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
1116DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SATA_IDE, quirk_amd_ide_mode);
Shane Huangfafe5c3d82013-06-03 18:24:10 +08001117DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
1118DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AMD, 0x7900, quirk_amd_ide_mode);
Conke Huab174432006-12-19 13:11:37 -08001119
Linus Torvalds1da177e2005-04-16 15:20:36 -07001120/*
1121 * Serverworks CSB5 IDE does not fully support native mode
1122 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001123static void quirk_svwks_csb5ide(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001124{
1125 u8 prog;
1126 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1127 if (prog & 5) {
1128 prog &= ~5;
1129 pdev->class &= ~5;
1130 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Alan Cox368c73d2006-10-04 00:41:26 +01001131 /* PCI layer will sort out resources */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001132 }
1133}
Andrew Morton652c5382007-11-21 15:07:13 -08001134DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_CSB5IDE, quirk_svwks_csb5ide);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001135
1136/*
1137 * Intel 82801CAM ICH3-M datasheet says IDE modes must be the same
1138 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001139static void quirk_ide_samemode(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001140{
1141 u8 prog;
1142
1143 pci_read_config_byte(pdev, PCI_CLASS_PROG, &prog);
1144
1145 if (((prog & 1) && !(prog & 4)) || ((prog & 4) && !(prog & 1))) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001146 dev_info(&pdev->dev, "IDE mode mismatch; forcing legacy mode\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001147 prog &= ~5;
1148 pdev->class &= ~5;
1149 pci_write_config_byte(pdev, PCI_CLASS_PROG, prog);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001150 }
1151}
Alan Cox368c73d2006-10-04 00:41:26 +01001152DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_10, quirk_ide_samemode);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001153
Alan Cox979b1792008-07-24 17:18:38 +01001154/*
1155 * Some ATA devices break if put into D3
1156 */
1157
Bill Pemberton15856ad2012-11-21 15:35:00 -05001158static void quirk_no_ata_d3(struct pci_dev *pdev)
Alan Cox979b1792008-07-24 17:18:38 +01001159{
Yinghai Lufaa738b2012-02-23 23:46:55 -08001160 pdev->dev_flags |= PCI_DEV_FLAGS_NO_D3;
Alan Cox979b1792008-07-24 17:18:38 +01001161}
Yinghai Lufaa738b2012-02-23 23:46:55 -08001162/* Quirk the legacy ATA devices only. The AHCI ones are ok */
1163DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_SERVERWORKS, PCI_ANY_ID,
1164 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
1165DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
1166 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox7a661c62009-06-24 16:02:27 +01001167/* ALi loses some register settings that we cannot then restore */
Yinghai Lufaa738b2012-02-23 23:46:55 -08001168DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID,
1169 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox7a661c62009-06-24 16:02:27 +01001170/* VIA comes back fine but we need to keep it alive or ACPI GTM failures
1171 occur when mode detecting */
Yinghai Lufaa738b2012-02-23 23:46:55 -08001172DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_VIA, PCI_ANY_ID,
1173 PCI_CLASS_STORAGE_IDE, 8, quirk_no_ata_d3);
Alan Cox979b1792008-07-24 17:18:38 +01001174
Linus Torvalds1da177e2005-04-16 15:20:36 -07001175/* This was originally an Alpha specific thing, but it really fits here.
1176 * The i82375 PCI/EISA bridge appears as non-classified. Fix that.
1177 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001178static void quirk_eisa_bridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001179{
1180 dev->class = PCI_CLASS_BRIDGE_EISA << 8;
1181}
Andrew Morton652c5382007-11-21 15:07:13 -08001182DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82375, quirk_eisa_bridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001183
Johannes Goecke7daa0c42006-04-20 02:43:17 -07001184
1185/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001186 * On ASUS P4B boards, the SMBus PCI Device within the ICH2/4 southbridge
1187 * is not activated. The myth is that Asus said that they do not want the
1188 * users to be irritated by just another PCI Device in the Win98 device
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001189 * manager. (see the file prog/hotplug/README.p4b in the lm_sensors
Linus Torvalds1da177e2005-04-16 15:20:36 -07001190 * package 2.7.0 for details)
1191 *
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001192 * The SMBus PCI Device can be activated by setting a bit in the ICH LPC
1193 * bridge. Unfortunately, this device has no subvendor/subdevice ID. So it
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001194 * becomes necessary to do this tweak in two steps -- the chosen trigger
1195 * is either the Host bridge (preferred) or on-board VGA controller.
Jean Delvare9208ee82007-03-24 16:56:44 +01001196 *
1197 * Note that we used to unhide the SMBus that way on Toshiba laptops
1198 * (Satellite A40 and Tecra M2) but then found that the thermal management
1199 * was done by SMM code, which could cause unsynchronized concurrent
1200 * accesses to the SMBus registers, with potentially bad effects. Thus you
1201 * should be very careful when adding new entries: if SMM is accessing the
1202 * Intel SMBus, this is a very good reason to leave it hidden.
Jean Delvarea99acc82008-03-28 14:16:04 -07001203 *
1204 * Likewise, many recent laptops use ACPI for thermal management. If the
1205 * ACPI DSDT code accesses the SMBus, then Linux should not access it
1206 * natively, and keeping the SMBus hidden is the right thing to do. If you
1207 * are about to add an entry in the table below, please first disassemble
1208 * the DSDT and double-check that there is no code accessing the SMBus.
Linus Torvalds1da177e2005-04-16 15:20:36 -07001209 */
Vivek Goyal9d24a812007-01-11 01:52:44 +01001210static int asus_hides_smbus;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001211
Bill Pemberton15856ad2012-11-21 15:35:00 -05001212static void asus_hides_smbus_hostbridge(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213{
1214 if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1215 if (dev->device == PCI_DEVICE_ID_INTEL_82845_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001216 switch (dev->subsystem_device) {
Jean Delvarea00db372005-06-29 17:04:06 +02001217 case 0x8025: /* P4B-LX */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001218 case 0x8070: /* P4B */
1219 case 0x8088: /* P4B533 */
1220 case 0x1626: /* L3C notebook */
1221 asus_hides_smbus = 1;
1222 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001223 else if (dev->device == PCI_DEVICE_ID_INTEL_82845G_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001224 switch (dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001225 case 0x80b1: /* P4GE-V */
1226 case 0x80b2: /* P4PE */
1227 case 0x8093: /* P4B533-V */
1228 asus_hides_smbus = 1;
1229 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001230 else if (dev->device == PCI_DEVICE_ID_INTEL_82850_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001231 switch (dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001232 case 0x8030: /* P4T533 */
1233 asus_hides_smbus = 1;
1234 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001235 else if (dev->device == PCI_DEVICE_ID_INTEL_7205_0)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001236 switch (dev->subsystem_device) {
1237 case 0x8070: /* P4G8X Deluxe */
1238 asus_hides_smbus = 1;
1239 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001240 else if (dev->device == PCI_DEVICE_ID_INTEL_E7501_MCH)
Jean Delvare321311a2006-07-31 08:53:15 +02001241 switch (dev->subsystem_device) {
1242 case 0x80c9: /* PU-DLS */
1243 asus_hides_smbus = 1;
1244 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001245 else if (dev->device == PCI_DEVICE_ID_INTEL_82855GM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001246 switch (dev->subsystem_device) {
1247 case 0x1751: /* M2N notebook */
1248 case 0x1821: /* M5N notebook */
Mats Erik Andersson4096ed02009-05-12 12:05:23 +02001249 case 0x1897: /* A6L notebook */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001250 asus_hides_smbus = 1;
1251 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001252 else if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001253 switch (dev->subsystem_device) {
1254 case 0x184b: /* W1N notebook */
1255 case 0x186a: /* M6Ne notebook */
1256 asus_hides_smbus = 1;
1257 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001258 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Jean Delvare2e457852007-01-05 09:17:56 +01001259 switch (dev->subsystem_device) {
1260 case 0x80f2: /* P4P800-X */
1261 asus_hides_smbus = 1;
1262 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001263 else if (dev->device == PCI_DEVICE_ID_INTEL_82915GM_HB)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001264 switch (dev->subsystem_device) {
1265 case 0x1882: /* M6V notebook */
Jean Delvare2d1e1c72006-04-01 16:46:35 +02001266 case 0x1977: /* A6VA notebook */
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001267 asus_hides_smbus = 1;
1268 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001269 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_HP)) {
1270 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001271 switch (dev->subsystem_device) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001272 case 0x088C: /* HP Compaq nc8000 */
1273 case 0x0890: /* HP Compaq nc6000 */
1274 asus_hides_smbus = 1;
1275 }
Jean Delvare2f2d39d2007-01-05 11:23:15 +01001276 else if (dev->device == PCI_DEVICE_ID_INTEL_82865_HB)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001277 switch (dev->subsystem_device) {
1278 case 0x12bc: /* HP D330L */
Jean Delvaree3b1bd52005-09-21 22:26:31 +02001279 case 0x12bd: /* HP D530 */
Michal Miroslaw74c57422009-05-12 13:49:25 -07001280 case 0x006a: /* HP Compaq nx9500 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001281 asus_hides_smbus = 1;
1282 }
Jean Delvare677cc642007-11-21 18:29:06 +01001283 else if (dev->device == PCI_DEVICE_ID_INTEL_82875_HB)
1284 switch (dev->subsystem_device) {
1285 case 0x12bf: /* HP xw4100 */
1286 asus_hides_smbus = 1;
1287 }
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001288 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_SAMSUNG)) {
1289 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
1290 switch (dev->subsystem_device) {
1291 case 0xC00C: /* Samsung P35 notebook */
1292 asus_hides_smbus = 1;
1293 }
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001294 } else if (unlikely(dev->subsystem_vendor == PCI_VENDOR_ID_COMPAQ)) {
1295 if (dev->device == PCI_DEVICE_ID_INTEL_82855PM_HB)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001296 switch (dev->subsystem_device) {
Rumen Ivanov Zarevc87f8832005-09-06 13:39:32 -07001297 case 0x0058: /* Compaq Evo N620c */
1298 asus_hides_smbus = 1;
1299 }
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001300 else if (dev->device == PCI_DEVICE_ID_INTEL_82810_IG3)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001301 switch (dev->subsystem_device) {
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001302 case 0xB16C: /* Compaq Deskpro EP 401963-001 (PCA# 010174) */
1303 /* Motherboard doesn't have Host bridge
1304 * subvendor/subdevice IDs, therefore checking
1305 * its on-board VGA controller */
1306 asus_hides_smbus = 1;
1307 }
David O'Shea8293b0f2009-03-02 09:51:13 +01001308 else if (dev->device == PCI_DEVICE_ID_INTEL_82801DB_2)
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001309 switch (dev->subsystem_device) {
Jean Delvare10260d92008-06-04 13:53:31 +02001310 case 0x00b8: /* Compaq Evo D510 CMT */
1311 case 0x00b9: /* Compaq Evo D510 SFF */
Jean Delvare6b5096e2009-07-28 11:49:19 +02001312 case 0x00ba: /* Compaq Evo D510 USDT */
David O'Shea8293b0f2009-03-02 09:51:13 +01001313 /* Motherboard doesn't have Host bridge
1314 * subvendor/subdevice IDs and on-board VGA
1315 * controller is disabled if an AGP card is
1316 * inserted, therefore checking USB UHCI
1317 * Controller #1 */
Jean Delvare10260d92008-06-04 13:53:31 +02001318 asus_hides_smbus = 1;
1319 }
Krzysztof Helt27e46852008-06-08 13:47:02 +02001320 else if (dev->device == PCI_DEVICE_ID_INTEL_82815_CGC)
1321 switch (dev->subsystem_device) {
1322 case 0x001A: /* Compaq Deskpro EN SSF P667 815E */
1323 /* Motherboard doesn't have host bridge
1324 * subvendor/subdevice IDs, therefore checking
1325 * its on-board VGA controller */
1326 asus_hides_smbus = 1;
1327 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001328 }
1329}
Andrew Morton652c5382007-11-21 15:07:13 -08001330DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845_HB, asus_hides_smbus_hostbridge);
1331DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845G_HB, asus_hides_smbus_hostbridge);
1332DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82850_HB, asus_hides_smbus_hostbridge);
1333DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB, asus_hides_smbus_hostbridge);
Jean Delvare677cc642007-11-21 18:29:06 +01001334DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB, asus_hides_smbus_hostbridge);
Andrew Morton652c5382007-11-21 15:07:13 -08001335DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_7205_0, asus_hides_smbus_hostbridge);
1336DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7501_MCH, asus_hides_smbus_hostbridge);
1337DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855PM_HB, asus_hides_smbus_hostbridge);
1338DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82855GM_HB, asus_hides_smbus_hostbridge);
1339DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915GM_HB, asus_hides_smbus_hostbridge);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001340
Andrew Morton652c5382007-11-21 15:07:13 -08001341DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_IG3, asus_hides_smbus_hostbridge);
David O'Shea8293b0f2009-03-02 09:51:13 +01001342DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_2, asus_hides_smbus_hostbridge);
Krzysztof Helt27e46852008-06-08 13:47:02 +02001343DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82815_CGC, asus_hides_smbus_hostbridge);
gw.kernel@tnode.comd7698ed2007-08-23 21:22:04 +02001344
Alan Cox1597cac2006-12-04 15:14:45 -08001345static void asus_hides_smbus_lpc(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001346{
1347 u16 val;
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001348
Linus Torvalds1da177e2005-04-16 15:20:36 -07001349 if (likely(!asus_hides_smbus))
1350 return;
1351
1352 pci_read_config_word(dev, 0xF2, &val);
1353 if (val & 0x8) {
1354 pci_write_config_word(dev, 0xF2, val & (~0x8));
1355 pci_read_config_word(dev, 0xF2, &val);
1356 if (val & 0x8)
Ryan Desfosses227f0642014-04-18 20:13:50 -04001357 dev_info(&dev->dev, "i801 SMBus device continues to play 'hide and seek'! 0x%x\n",
1358 val);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001359 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001360 dev_info(&dev->dev, "Enabled i801 SMBus device\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361 }
1362}
Andrew Morton652c5382007-11-21 15:07:13 -08001363DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1364DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1365DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1366DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1367DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1368DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1369DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001370DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_0, asus_hides_smbus_lpc);
1371DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_0, asus_hides_smbus_lpc);
1372DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_0, asus_hides_smbus_lpc);
1373DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_0, asus_hides_smbus_lpc);
1374DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_12, asus_hides_smbus_lpc);
1375DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_12, asus_hides_smbus_lpc);
1376DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_0, asus_hides_smbus_lpc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001377
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001378/* It appears we just have one such device. If not, we have a warning */
1379static void __iomem *asus_rcba_base;
1380static void asus_hides_smbus_lpc_ich6_suspend(struct pci_dev *dev)
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001381{
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001382 u32 rcba;
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001383
1384 if (likely(!asus_hides_smbus))
1385 return;
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001386 WARN_ON(asus_rcba_base);
1387
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001388 pci_read_config_dword(dev, 0xF0, &rcba);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001389 /* use bits 31:14, 16 kB aligned */
1390 asus_rcba_base = ioremap_nocache(rcba & 0xFFFFC000, 0x4000);
1391 if (asus_rcba_base == NULL)
1392 return;
1393}
1394
1395static void asus_hides_smbus_lpc_ich6_resume_early(struct pci_dev *dev)
1396{
1397 u32 val;
1398
1399 if (likely(!asus_hides_smbus || !asus_rcba_base))
1400 return;
1401 /* read the Function Disable register, dword mode only */
1402 val = readl(asus_rcba_base + 0x3418);
1403 writel(val & 0xFFFFFFF7, asus_rcba_base + 0x3418); /* enable the SMBus device */
1404}
1405
1406static void asus_hides_smbus_lpc_ich6_resume(struct pci_dev *dev)
1407{
1408 if (likely(!asus_hides_smbus || !asus_rcba_base))
1409 return;
1410 iounmap(asus_rcba_base);
1411 asus_rcba_base = NULL;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001412 dev_info(&dev->dev, "Enabled ICH6/i801 SMBus device\n");
R.Marek@sh.cvut.czacc06632005-09-29 08:35:41 +00001413}
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001414
1415static void asus_hides_smbus_lpc_ich6(struct pci_dev *dev)
1416{
1417 asus_hides_smbus_lpc_ich6_suspend(dev);
1418 asus_hides_smbus_lpc_ich6_resume_early(dev);
1419 asus_hides_smbus_lpc_ich6_resume(dev);
1420}
Andrew Morton652c5382007-11-21 15:07:13 -08001421DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001422DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_suspend);
1423DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume);
1424DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_1, asus_hides_smbus_lpc_ich6_resume_early);
Carl-Daniel Hailfingerce007ea2006-05-15 09:44:33 -07001425
Linus Torvalds1da177e2005-04-16 15:20:36 -07001426/*
1427 * SiS 96x south bridge: BIOS typically hides SMBus device...
1428 */
Alan Cox1597cac2006-12-04 15:14:45 -08001429static void quirk_sis_96x_smbus(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001430{
1431 u8 val = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001432 pci_read_config_byte(dev, 0x77, &val);
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001433 if (val & 0x10) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001434 dev_info(&dev->dev, "Enabling SiS 96x SMBus\n");
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001435 pci_write_config_byte(dev, 0x77, val & ~0x10);
1436 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001437}
Andrew Morton652c5382007-11-21 15:07:13 -08001438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1439DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1440DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1441DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001442DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_961, quirk_sis_96x_smbus);
1443DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_962, quirk_sis_96x_smbus);
1444DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_963, quirk_sis_96x_smbus);
1445DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_LPC, quirk_sis_96x_smbus);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001446
Linus Torvalds1da177e2005-04-16 15:20:36 -07001447/*
1448 * ... This is further complicated by the fact that some SiS96x south
1449 * bridges pretend to be 85C503/5513 instead. In that case see if we
1450 * spotted a compatible north bridge to make sure.
1451 * (pci_find_device doesn't work yet)
1452 *
1453 * We can also enable the sis96x bit in the discovery register..
1454 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001455#define SIS_DETECT_REGISTER 0x40
1456
Alan Cox1597cac2006-12-04 15:14:45 -08001457static void quirk_sis_503(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001458{
1459 u8 reg;
1460 u16 devid;
1461
1462 pci_read_config_byte(dev, SIS_DETECT_REGISTER, &reg);
1463 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg | (1 << 6));
1464 pci_read_config_word(dev, PCI_DEVICE_ID, &devid);
1465 if (((devid & 0xfff0) != 0x0960) && (devid != 0x0018)) {
1466 pci_write_config_byte(dev, SIS_DETECT_REGISTER, reg);
1467 return;
1468 }
1469
Linus Torvalds1da177e2005-04-16 15:20:36 -07001470 /*
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001471 * Ok, it now shows up as a 96x.. run the 96x quirk by
1472 * hand in case it has already been processed.
1473 * (depends on link order, which is apparently not guaranteed)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001474 */
1475 dev->device = devid;
Mark M. Hoffman2f5c33b2007-01-08 22:11:29 -05001476 quirk_sis_96x_smbus(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001477}
Andrew Morton652c5382007-11-21 15:07:13 -08001478DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001479DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_SI, PCI_DEVICE_ID_SI_503, quirk_sis_503);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001480
Linus Torvalds1da177e2005-04-16 15:20:36 -07001481
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001482/*
1483 * On ASUS A8V and A8V Deluxe boards, the onboard AC97 audio controller
1484 * and MC97 modem controller are disabled when a second PCI soundcard is
1485 * present. This patch, tweaking the VT8237 ISA bridge, enables them.
1486 * -- bjd
1487 */
Alan Cox1597cac2006-12-04 15:14:45 -08001488static void asus_hides_ac97_lpc(struct pci_dev *dev)
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001489{
1490 u8 val;
1491 int asus_hides_ac97 = 0;
1492
1493 if (likely(dev->subsystem_vendor == PCI_VENDOR_ID_ASUSTEK)) {
1494 if (dev->device == PCI_DEVICE_ID_VIA_8237)
1495 asus_hides_ac97 = 1;
1496 }
1497
1498 if (!asus_hides_ac97)
1499 return;
1500
1501 pci_read_config_byte(dev, 0x50, &val);
1502 if (val & 0xc0) {
1503 pci_write_config_byte(dev, 0x50, val & (~0xc0));
1504 pci_read_config_byte(dev, 0x50, &val);
1505 if (val & 0xc0)
Ryan Desfosses227f0642014-04-18 20:13:50 -04001506 dev_info(&dev->dev, "Onboard AC97/MC97 devices continue to play 'hide and seek'! 0x%x\n",
1507 val);
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001508 else
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001509 dev_info(&dev->dev, "Enabled onboard AC97/MC97 devices\n");
Bauke Jan Doumae5548e92006-02-28 21:44:36 +01001510 }
1511}
Andrew Morton652c5382007-11-21 15:07:13 -08001512DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001513DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8237, asus_hides_ac97_lpc);
Alan Cox1597cac2006-12-04 15:14:45 -08001514
Tejun Heo77967052006-08-19 03:54:39 +09001515#if defined(CONFIG_ATA) || defined(CONFIG_ATA_MODULE)
Alan Cox15e0c692006-07-12 15:05:41 +01001516
1517/*
1518 * If we are using libata we can drive this chip properly but must
1519 * do this early on to make the additional device appear during
1520 * the PCI scanning.
1521 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001522static void quirk_jmicron_ata(struct pci_dev *pdev)
Alan Cox15e0c692006-07-12 15:05:41 +01001523{
Tejun Heoe34bb372007-02-26 20:24:03 +09001524 u32 conf1, conf5, class;
Alan Cox15e0c692006-07-12 15:05:41 +01001525 u8 hdr;
1526
1527 /* Only poke fn 0 */
1528 if (PCI_FUNC(pdev->devfn))
1529 return;
1530
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001531 pci_read_config_dword(pdev, 0x40, &conf1);
1532 pci_read_config_dword(pdev, 0x80, &conf5);
Alan Cox15e0c692006-07-12 15:05:41 +01001533
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001534 conf1 &= ~0x00CFF302; /* Clear bit 1, 8, 9, 12-19, 22, 23 */
1535 conf5 &= ~(1 << 24); /* Clear bit 24 */
Alan Cox15e0c692006-07-12 15:05:41 +01001536
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001537 switch (pdev->device) {
Tejun Heo4daedcf2010-06-03 11:57:04 +02001538 case PCI_DEVICE_ID_JMICRON_JMB360: /* SATA single port */
1539 case PCI_DEVICE_ID_JMICRON_JMB362: /* SATA dual ports */
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001540 case PCI_DEVICE_ID_JMICRON_JMB364: /* SATA dual ports */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001541 /* The controller should be in single function ahci mode */
1542 conf1 |= 0x0002A100; /* Set 8, 13, 15, 17 */
1543 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001544
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001545 case PCI_DEVICE_ID_JMICRON_JMB365:
1546 case PCI_DEVICE_ID_JMICRON_JMB366:
1547 /* Redirect IDE second PATA port to the right spot */
1548 conf5 |= (1 << 24);
1549 /* Fall through */
1550 case PCI_DEVICE_ID_JMICRON_JMB361:
1551 case PCI_DEVICE_ID_JMICRON_JMB363:
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001552 case PCI_DEVICE_ID_JMICRON_JMB369:
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001553 /* Enable dual function mode, AHCI on fn 0, IDE fn1 */
1554 /* Set the class codes correctly and then direct IDE 0 */
Tejun Heo3a9e3a52007-10-23 15:27:31 +09001555 conf1 |= 0x00C2A1B3; /* Set 0, 1, 4, 5, 7, 8, 13, 15, 17, 22, 23 */
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001556 break;
1557
1558 case PCI_DEVICE_ID_JMICRON_JMB368:
1559 /* The controller should be in single function IDE mode */
1560 conf1 |= 0x00C00000; /* Set 22, 23 */
1561 break;
Alan Cox15e0c692006-07-12 15:05:41 +01001562 }
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001563
1564 pci_write_config_dword(pdev, 0x40, conf1);
1565 pci_write_config_dword(pdev, 0x80, conf5);
1566
1567 /* Update pdev accordingly */
1568 pci_read_config_byte(pdev, PCI_HEADER_TYPE, &hdr);
1569 pdev->hdr_type = hdr & 0x7f;
1570 pdev->multifunction = !!(hdr & 0x80);
Tejun Heoe34bb372007-02-26 20:24:03 +09001571
1572 pci_read_config_dword(pdev, PCI_CLASS_REVISION, &class);
1573 pdev->class = class >> 8;
Alan Cox15e0c692006-07-12 15:05:41 +01001574}
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001575DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1576DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
Tejun Heo4daedcf2010-06-03 11:57:04 +02001577DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001578DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001579DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
Tejun Heo5ee2ae72007-02-26 20:16:13 +09001580DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1581DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1582DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001583DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001584DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB360, quirk_jmicron_ata);
1585DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB361, quirk_jmicron_ata);
Tejun Heo4daedcf2010-06-03 11:57:04 +02001586DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB362, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001587DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB363, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001588DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB364, quirk_jmicron_ata);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02001589DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB365, quirk_jmicron_ata);
1590DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB366, quirk_jmicron_ata);
1591DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB368, quirk_jmicron_ata);
Tejun Heo5b6ae5b2010-07-30 11:42:42 +02001592DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB369, quirk_jmicron_ata);
Alan Cox15e0c692006-07-12 15:05:41 +01001593
1594#endif
1595
Zhang Rui91f15fb2015-08-24 15:27:11 -05001596static void quirk_jmicron_async_suspend(struct pci_dev *dev)
1597{
1598 if (dev->multifunction) {
1599 device_disable_async_suspend(&dev->dev);
1600 dev_info(&dev->dev, "async suspend disabled to avoid multi-function power-on ordering issue\n");
1601 }
1602}
1603DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_IDE, 8, quirk_jmicron_async_suspend);
1604DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_JMICRON, PCI_ANY_ID, PCI_CLASS_STORAGE_SATA_AHCI, 0, quirk_jmicron_async_suspend);
1605DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x2362, quirk_jmicron_async_suspend);
1606DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_JMICRON, 0x236f, quirk_jmicron_async_suspend);
1607
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608#ifdef CONFIG_X86_IO_APIC
Bill Pemberton15856ad2012-11-21 15:35:00 -05001609static void quirk_alder_ioapic(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001610{
1611 int i;
1612
1613 if ((pdev->class >> 8) != 0xff00)
1614 return;
1615
1616 /* the first BAR is the location of the IO APIC...we must
1617 * not touch this (and it's already covered by the fixmap), so
1618 * forcibly insert it into the resource tree */
1619 if (pci_resource_start(pdev, 0) && pci_resource_len(pdev, 0))
1620 insert_resource(&iomem_resource, &pdev->resource[0]);
1621
1622 /* The next five BARs all seem to be rubbish, so just clean
1623 * them out */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001624 for (i = 1; i < 6; i++)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001625 memset(&pdev->resource[i], 0, sizeof(pdev->resource[i]));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001626}
Andrew Morton652c5382007-11-21 15:07:13 -08001627DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EESSC, quirk_alder_ioapic);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001628#endif
1629
Bill Pemberton15856ad2012-11-21 15:35:00 -05001630static void quirk_pcie_mch(struct pci_dev *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001631{
Eric W. Biederman0ba379e2009-09-06 21:48:35 -07001632 pdev->no_msi = 1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001633}
Andrew Morton652c5382007-11-21 15:07:13 -08001634DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7520_MCH, quirk_pcie_mch);
1635DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7320_MCH, quirk_pcie_mch);
1636DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_E7525_MCH, quirk_pcie_mch);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001637
Dongdong Liu9e431e02017-12-28 17:53:32 +08001638DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_HUAWEI, 0x1610, PCI_CLASS_BRIDGE_PCI, 8, quirk_pcie_mch);
Kristen Accardi4602b882005-08-16 15:15:58 -07001639
1640/*
1641 * It's possible for the MSI to get corrupted if shpc and acpi
1642 * are used together on certain PXH-based systems.
1643 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001644static void quirk_pcie_pxh(struct pci_dev *dev)
Kristen Accardi4602b882005-08-16 15:15:58 -07001645{
Kristen Accardi4602b882005-08-16 15:15:58 -07001646 dev->no_msi = 1;
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07001647 dev_warn(&dev->dev, "PXH quirk detected; SHPC device MSI disabled\n");
Kristen Accardi4602b882005-08-16 15:15:58 -07001648}
1649DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_0, quirk_pcie_pxh);
1650DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHD_1, quirk_pcie_pxh);
1651DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_pcie_pxh);
1652DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_pcie_pxh);
1653DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_pcie_pxh);
1654
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001655/*
1656 * Some Intel PCI Express chipsets have trouble with downstream
1657 * device power management.
1658 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001659static void quirk_intel_pcie_pm(struct pci_dev *dev)
Kristen Carlson Accardiffadcc22006-07-12 08:59:00 -07001660{
1661 pci_pm_d3_delay = 120;
1662 dev->no_d1d2 = 1;
1663}
1664
1665DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_pcie_pm);
1666DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_pcie_pm);
1667DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_pcie_pm);
1668DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_pcie_pm);
1669DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_pcie_pm);
1670DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_pcie_pm);
1671DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_pcie_pm);
1672DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_pcie_pm);
1673DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_pcie_pm);
1674DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_pcie_pm);
1675DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2601, quirk_intel_pcie_pm);
1676DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2602, quirk_intel_pcie_pm);
1677DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2603, quirk_intel_pcie_pm);
1678DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2604, quirk_intel_pcie_pm);
1679DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2605, quirk_intel_pcie_pm);
1680DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2606, quirk_intel_pcie_pm);
1681DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2607, quirk_intel_pcie_pm);
1682DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2608, quirk_intel_pcie_pm);
1683DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2609, quirk_intel_pcie_pm);
1684DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260a, quirk_intel_pcie_pm);
1685DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x260b, quirk_intel_pcie_pm);
Kristen Accardi4602b882005-08-16 15:15:58 -07001686
Stefan Assmann426b3b82008-06-11 16:35:16 +02001687#ifdef CONFIG_X86_IO_APIC
1688/*
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001689 * Boot interrupts on some chipsets cannot be turned off. For these chipsets,
1690 * remap the original interrupt in the linux kernel to the boot interrupt, so
1691 * that a PCI device's interrupt handler is installed on the boot interrupt
1692 * line instead.
1693 */
1694static void quirk_reroute_to_boot_interrupts_intel(struct pci_dev *dev)
1695{
Stefan Assmann41b9eb22008-07-15 13:48:55 +02001696 if (noioapicquirk || noioapicreroute)
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001697 return;
1698
1699 dev->irq_reroute_variant = INTEL_IRQ_REROUTE_VARIANT;
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001700 dev_info(&dev->dev, "rerouting interrupts for [%04x:%04x]\n",
1701 dev->vendor, dev->device);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001702}
Olaf Dabrunz88d1dce2008-07-08 15:59:48 +02001703DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1704DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1705DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1706DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1707DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1708DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1709DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1710DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
1711DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_0, quirk_reroute_to_boot_interrupts_intel);
1712DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80333_1, quirk_reroute_to_boot_interrupts_intel);
1713DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_0, quirk_reroute_to_boot_interrupts_intel);
1714DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_0, quirk_reroute_to_boot_interrupts_intel);
1715DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXH_1, quirk_reroute_to_boot_interrupts_intel);
1716DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PXHV, quirk_reroute_to_boot_interrupts_intel);
1717DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_0, quirk_reroute_to_boot_interrupts_intel);
1718DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80332_1, quirk_reroute_to_boot_interrupts_intel);
Stefan Assmanne1d3a902008-06-11 16:35:17 +02001719
1720/*
Stefan Assmann426b3b82008-06-11 16:35:16 +02001721 * On some chipsets we can disable the generation of legacy INTx boot
1722 * interrupts.
1723 */
1724
1725/*
1726 * IO-APIC1 on 6300ESB generates boot interrupts, see intel order no
1727 * 300641-004US, section 5.7.3.
1728 */
1729#define INTEL_6300_IOAPIC_ABAR 0x40
1730#define INTEL_6300_DISABLE_BOOT_IRQ (1<<14)
1731
1732static void quirk_disable_intel_boot_interrupt(struct pci_dev *dev)
1733{
1734 u16 pci_config_word;
1735
1736 if (noioapicquirk)
1737 return;
1738
1739 pci_read_config_word(dev, INTEL_6300_IOAPIC_ABAR, &pci_config_word);
1740 pci_config_word |= INTEL_6300_DISABLE_BOOT_IRQ;
1741 pci_write_config_word(dev, INTEL_6300_IOAPIC_ABAR, pci_config_word);
1742
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001743 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1744 dev->vendor, dev->device);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001745}
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001746DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
1747DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_10, quirk_disable_intel_boot_interrupt);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001748
1749/*
1750 * disable boot interrupts on HT-1000
1751 */
1752#define BC_HT1000_FEATURE_REG 0x64
1753#define BC_HT1000_PIC_REGS_ENABLE (1<<0)
1754#define BC_HT1000_MAP_IDX 0xC00
1755#define BC_HT1000_MAP_DATA 0xC01
1756
1757static void quirk_disable_broadcom_boot_interrupt(struct pci_dev *dev)
1758{
1759 u32 pci_config_dword;
1760 u8 irq;
1761
1762 if (noioapicquirk)
1763 return;
1764
1765 pci_read_config_dword(dev, BC_HT1000_FEATURE_REG, &pci_config_dword);
1766 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword |
1767 BC_HT1000_PIC_REGS_ENABLE);
1768
1769 for (irq = 0x10; irq < 0x10 + 32; irq++) {
1770 outb(irq, BC_HT1000_MAP_IDX);
1771 outb(0x00, BC_HT1000_MAP_DATA);
1772 }
1773
1774 pci_write_config_dword(dev, BC_HT1000_FEATURE_REG, pci_config_dword);
1775
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001776 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1777 dev->vendor, dev->device);
Olaf Dabrunz77251182008-07-08 15:59:47 +02001778}
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001779DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
1780DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT1000SB, quirk_disable_broadcom_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001781
1782/*
1783 * disable boot interrupts on AMD and ATI chipsets
1784 */
1785/*
1786 * NOIOAMODE needs to be disabled to disable "boot interrupts". For AMD 8131
1787 * rev. A0 and B0, NOIOAMODE needs to be disabled anyway to fix IO-APIC mode
1788 * (due to an erratum).
1789 */
1790#define AMD_813X_MISC 0x40
1791#define AMD_813X_NOIOAMODE (1<<0)
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001792#define AMD_813X_REV_B1 0x12
Stefan Assmannbbe19442009-02-26 10:46:48 -08001793#define AMD_813X_REV_B2 0x13
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001794
1795static void quirk_disable_amd_813x_boot_interrupt(struct pci_dev *dev)
1796{
1797 u32 pci_config_dword;
1798
1799 if (noioapicquirk)
1800 return;
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001801 if ((dev->revision == AMD_813X_REV_B1) ||
1802 (dev->revision == AMD_813X_REV_B2))
Stefan Assmannbbe19442009-02-26 10:46:48 -08001803 return;
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001804
1805 pci_read_config_dword(dev, AMD_813X_MISC, &pci_config_dword);
1806 pci_config_dword &= ~AMD_813X_NOIOAMODE;
1807 pci_write_config_dword(dev, AMD_813X_MISC, pci_config_dword);
1808
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001809 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1810 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001811}
Stefan Assmann4fd8bdc2009-10-27 08:57:42 +01001812DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1813DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1814DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
1815DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE, quirk_disable_amd_813x_boot_interrupt);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001816
1817#define AMD_8111_PCI_IRQ_ROUTING 0x56
1818
1819static void quirk_disable_amd_8111_boot_interrupt(struct pci_dev *dev)
1820{
1821 u16 pci_config_word;
1822
1823 if (noioapicquirk)
1824 return;
1825
1826 pci_read_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, &pci_config_word);
1827 if (!pci_config_word) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001828 dev_info(&dev->dev, "boot interrupts on device [%04x:%04x] already disabled\n",
1829 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001830 return;
1831 }
1832 pci_write_config_word(dev, AMD_8111_PCI_IRQ_ROUTING, 0);
Bjorn Helgaasfdcdaf62009-09-14 14:36:41 -06001833 dev_info(&dev->dev, "disabled boot interrupts on device [%04x:%04x]\n",
1834 dev->vendor, dev->device);
Olaf Dabrunz542622d2008-07-08 15:59:48 +02001835}
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001836DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
1837DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_SMBUS, quirk_disable_amd_8111_boot_interrupt);
Stefan Assmann426b3b82008-06-11 16:35:16 +02001838#endif /* CONFIG_X86_IO_APIC */
1839
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001840/*
1841 * Toshiba TC86C001 IDE controller reports the standard 8-byte BAR0 size
1842 * but the PIO transfers won't work if BAR0 falls at the odd 8 bytes.
1843 * Re-allocate the region if needed...
1844 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05001845static void quirk_tc86c001_ide(struct pci_dev *dev)
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001846{
1847 struct resource *r = &dev->resource[0];
1848
1849 if (r->start & 0x8) {
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07001850 r->flags |= IORESOURCE_UNSET;
Sergei Shtylyov33dced22007-02-07 18:18:45 +01001851 r->start = 0;
1852 r->end = 0xf;
1853 }
1854}
1855DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TOSHIBA_2,
1856 PCI_DEVICE_ID_TOSHIBA_TC86C001_IDE,
1857 quirk_tc86c001_ide);
1858
Ian Abbott21c5fd92012-10-30 17:25:53 +00001859/*
1860 * PLX PCI 9050 PCI Target bridge controller has an errata that prevents the
1861 * local configuration registers accessible via BAR0 (memory) or BAR1 (i/o)
1862 * being read correctly if bit 7 of the base address is set.
1863 * The BAR0 or BAR1 region may be disabled (size 0) or enabled (size 128).
1864 * Re-allocate the regions to a 256-byte boundary if necessary.
1865 */
Linus Torvalds193c0d62012-12-13 12:14:47 -08001866static void quirk_plx_pci9050(struct pci_dev *dev)
Ian Abbott21c5fd92012-10-30 17:25:53 +00001867{
1868 unsigned int bar;
1869
1870 /* Fixed in revision 2 (PCI 9052). */
1871 if (dev->revision >= 2)
1872 return;
1873 for (bar = 0; bar <= 1; bar++)
1874 if (pci_resource_len(dev, bar) == 0x80 &&
1875 (pci_resource_start(dev, bar) & 0x80)) {
1876 struct resource *r = &dev->resource[bar];
Ryan Desfosses227f0642014-04-18 20:13:50 -04001877 dev_info(&dev->dev, "Re-allocating PLX PCI 9050 BAR %u to length 256 to avoid bit 7 bug\n",
Ian Abbott21c5fd92012-10-30 17:25:53 +00001878 bar);
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07001879 r->flags |= IORESOURCE_UNSET;
Ian Abbott21c5fd92012-10-30 17:25:53 +00001880 r->start = 0;
1881 r->end = 0xff;
1882 }
1883}
1884DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_PLX, PCI_DEVICE_ID_PLX_9050,
1885 quirk_plx_pci9050);
Ian Abbott2794bb22012-10-29 14:40:18 +00001886/*
1887 * The following Meilhaus (vendor ID 0x1402) device IDs (amongst others)
1888 * may be using the PLX PCI 9050: 0x0630, 0x0940, 0x0950, 0x0960, 0x100b,
1889 * 0x1400, 0x140a, 0x140b, 0x14e0, 0x14ea, 0x14eb, 0x1604, 0x1608, 0x160c,
1890 * 0x168f, 0x2000, 0x2600, 0x3000, 0x810a, 0x810b.
1891 *
1892 * Currently, device IDs 0x2000 and 0x2600 are used by the Comedi "me_daq"
1893 * driver.
1894 */
1895DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2000, quirk_plx_pci9050);
1896DECLARE_PCI_FIXUP_HEADER(0x1402, 0x2600, quirk_plx_pci9050);
Ian Abbott21c5fd92012-10-30 17:25:53 +00001897
Bill Pemberton15856ad2012-11-21 15:35:00 -05001898static void quirk_netmos(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001899{
1900 unsigned int num_parallel = (dev->subsystem_device & 0xf0) >> 4;
1901 unsigned int num_serial = dev->subsystem_device & 0xf;
1902
1903 /*
1904 * These Netmos parts are multiport serial devices with optional
1905 * parallel ports. Even when parallel ports are present, they
1906 * are identified as class SERIAL, which means the serial driver
1907 * will claim them. To prevent this, mark them as class OTHER.
1908 * These combo devices should be claimed by parport_serial.
1909 *
1910 * The subdevice ID is of the form 0x00PS, where <P> is the number
1911 * of parallel ports and <S> is the number of serial ports.
1912 */
1913 switch (dev->device) {
Jiri Slaby4c9c1682008-12-08 16:19:14 +01001914 case PCI_DEVICE_ID_NETMOS_9835:
1915 /* Well, this rule doesn't hold for the following 9835 device */
1916 if (dev->subsystem_vendor == PCI_VENDOR_ID_IBM &&
1917 dev->subsystem_device == 0x0299)
1918 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001919 case PCI_DEVICE_ID_NETMOS_9735:
1920 case PCI_DEVICE_ID_NETMOS_9745:
Linus Torvalds1da177e2005-04-16 15:20:36 -07001921 case PCI_DEVICE_ID_NETMOS_9845:
1922 case PCI_DEVICE_ID_NETMOS_9855:
Yinghai Lu08803ef2012-02-23 23:46:56 -08001923 if (num_parallel) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001924 dev_info(&dev->dev, "Netmos %04x (%u parallel, %u serial); changing class SERIAL to OTHER (use parport_serial)\n",
Linus Torvalds1da177e2005-04-16 15:20:36 -07001925 dev->device, num_parallel, num_serial);
1926 dev->class = (PCI_CLASS_COMMUNICATION_OTHER << 8) |
1927 (dev->class & 0xff);
1928 }
1929 }
1930}
Yinghai Lu08803ef2012-02-23 23:46:56 -08001931DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_NETMOS, PCI_ANY_ID,
1932 PCI_CLASS_COMMUNICATION_SERIAL, 8, quirk_netmos);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001933
Alex Williamsonda2d03e2015-09-15 22:24:46 -06001934/*
1935 * Quirk non-zero PCI functions to route VPD access through function 0 for
1936 * devices that share VPD resources between functions. The functions are
1937 * expected to be identical devices.
1938 */
Mark Rustad7aa6ca42015-07-13 11:40:07 -07001939static void quirk_f0_vpd_link(struct pci_dev *dev)
1940{
Alex Williamsonda2d03e2015-09-15 22:24:46 -06001941 struct pci_dev *f0;
1942
1943 if (!PCI_FUNC(dev->devfn))
Mark Rustad7aa6ca42015-07-13 11:40:07 -07001944 return;
Alex Williamsonda2d03e2015-09-15 22:24:46 -06001945
1946 f0 = pci_get_slot(dev->bus, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
1947 if (!f0)
1948 return;
1949
1950 if (f0->vpd && dev->class == f0->class &&
1951 dev->vendor == f0->vendor && dev->device == f0->device)
1952 dev->dev_flags |= PCI_DEV_FLAGS_VPD_REF_F0;
1953
1954 pci_dev_put(f0);
Mark Rustad7aa6ca42015-07-13 11:40:07 -07001955}
1956DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
1957 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_f0_vpd_link);
1958
Bill Pemberton15856ad2012-11-21 15:35:00 -05001959static void quirk_e100_interrupt(struct pci_dev *dev)
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001960{
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001961 u16 command, pmcsr;
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001962 u8 __iomem *csr;
1963 u8 cmd_hi;
1964
1965 switch (dev->device) {
1966 /* PCI IDs taken from drivers/net/e100.c */
1967 case 0x1029:
1968 case 0x1030 ... 0x1034:
1969 case 0x1038 ... 0x103E:
1970 case 0x1050 ... 0x1057:
1971 case 0x1059:
1972 case 0x1064 ... 0x106B:
1973 case 0x1091 ... 0x1095:
1974 case 0x1209:
1975 case 0x1229:
1976 case 0x2449:
1977 case 0x2459:
1978 case 0x245D:
1979 case 0x27DC:
1980 break;
1981 default:
1982 return;
1983 }
1984
1985 /*
1986 * Some firmware hands off the e100 with interrupts enabled,
1987 * which can cause a flood of interrupts if packets are
1988 * received before the driver attaches to the device. So
1989 * disable all e100 interrupts here. The driver will
1990 * re-enable them when it's ready.
1991 */
1992 pci_read_config_word(dev, PCI_COMMAND, &command);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001993
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10001994 if (!(command & PCI_COMMAND_MEMORY) || !pci_resource_start(dev, 0))
Bjorn Helgaas16a74742006-04-05 08:47:00 -04001995 return;
1996
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03001997 /*
1998 * Check that the device is in the D0 power state. If it's not,
1999 * there is no point to look any further.
2000 */
Yijing Wang728cdb72013-06-18 16:22:14 +08002001 if (dev->pm_cap) {
2002 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Ivan Kokshayskye64aecc2007-12-18 00:39:27 +03002003 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) != PCI_D0)
2004 return;
2005 }
2006
Benjamin Herrenschmidt1bef7dc2007-09-29 09:06:21 +10002007 /* Convert from PCI bus to resource space. */
2008 csr = ioremap(pci_resource_start(dev, 0), 8);
Bjorn Helgaas16a74742006-04-05 08:47:00 -04002009 if (!csr) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002010 dev_warn(&dev->dev, "Can't map e100 registers\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04002011 return;
2012 }
2013
2014 cmd_hi = readb(csr + 3);
2015 if (cmd_hi == 0) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002016 dev_warn(&dev->dev, "Firmware left e100 interrupts enabled; disabling\n");
Bjorn Helgaas16a74742006-04-05 08:47:00 -04002017 writeb(1, csr + 3);
2018 }
2019
2020 iounmap(csr);
2021}
Yinghai Lu4c5b28e2012-02-23 23:46:57 -08002022DECLARE_PCI_FIXUP_CLASS_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID,
2023 PCI_CLASS_NETWORK_ETHERNET, 8, quirk_e100_interrupt);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002024
Alexander Duyck649426e2009-03-05 13:57:28 -05002025/*
2026 * The 82575 and 82598 may experience data corruption issues when transitioning
2027 * out of L0S. To prevent this we need to disable L0S on the pci-e link
2028 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002029static void quirk_disable_aspm_l0s(struct pci_dev *dev)
Alexander Duyck649426e2009-03-05 13:57:28 -05002030{
2031 dev_info(&dev->dev, "Disabling L0s\n");
2032 pci_disable_link_state(dev, PCIE_LINK_STATE_L0S);
2033}
2034DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a7, quirk_disable_aspm_l0s);
2035DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10a9, quirk_disable_aspm_l0s);
2036DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10b6, quirk_disable_aspm_l0s);
2037DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c6, quirk_disable_aspm_l0s);
2038DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c7, quirk_disable_aspm_l0s);
2039DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10c8, quirk_disable_aspm_l0s);
2040DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10d6, quirk_disable_aspm_l0s);
2041DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10db, quirk_disable_aspm_l0s);
2042DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10dd, quirk_disable_aspm_l0s);
2043DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10e1, quirk_disable_aspm_l0s);
2044DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10ec, quirk_disable_aspm_l0s);
2045DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f1, quirk_disable_aspm_l0s);
2046DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x10f4, quirk_disable_aspm_l0s);
2047DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1508, quirk_disable_aspm_l0s);
2048
Bill Pemberton15856ad2012-11-21 15:35:00 -05002049static void fixup_rev1_53c810(struct pci_dev *dev)
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002050{
Bjorn Helgaase6323e32015-06-19 15:36:45 -05002051 u32 class = dev->class;
2052
2053 /*
2054 * rev 1 ncr53c810 chips don't set the class at all which means
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002055 * they don't get their resources remapped. Fix that here.
2056 */
Bjorn Helgaase6323e32015-06-19 15:36:45 -05002057 if (class)
2058 return;
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002059
Bjorn Helgaase6323e32015-06-19 15:36:45 -05002060 dev->class = PCI_CLASS_STORAGE_SCSI << 8;
2061 dev_info(&dev->dev, "NCR 53c810 rev 1 PCI class overridden (%#08x -> %#08x)\n",
2062 class, dev->class);
Ivan Kokshayskya5312e22005-11-01 01:43:56 +03002063}
2064DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_NCR, PCI_DEVICE_ID_NCR_53C810, fixup_rev1_53c810);
2065
Daniel Yeisley9d265122005-12-05 07:06:43 -05002066/* Enable 1k I/O space granularity on the Intel P64H2 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002067static void quirk_p64h2_1k_io(struct pci_dev *dev)
Daniel Yeisley9d265122005-12-05 07:06:43 -05002068{
2069 u16 en1k;
Daniel Yeisley9d265122005-12-05 07:06:43 -05002070
2071 pci_read_config_word(dev, 0x40, &en1k);
2072
2073 if (en1k & 0x200) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002074 dev_info(&dev->dev, "Enable I/O Space to 1KB granularity\n");
Bjorn Helgaas2b28ae12012-07-09 13:38:57 -06002075 dev->io_window_1k = 1;
Daniel Yeisley9d265122005-12-05 07:06:43 -05002076 }
2077}
2078DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x1460, quirk_p64h2_1k_io);
2079
Brice Goglincf34a8e2006-06-13 14:35:42 -04002080/* Under some circumstances, AER is not linked with extended capabilities.
2081 * Force it to be linked by setting the corresponding control bit in the
2082 * config space.
2083 */
Alan Cox1597cac2006-12-04 15:14:45 -08002084static void quirk_nvidia_ck804_pcie_aer_ext_cap(struct pci_dev *dev)
Brice Goglincf34a8e2006-06-13 14:35:42 -04002085{
2086 uint8_t b;
2087 if (pci_read_config_byte(dev, 0xf41, &b) == 0) {
2088 if (!(b & 0x20)) {
2089 pci_write_config_byte(dev, 0xf41, b | 0x20);
Ryan Desfosses227f0642014-04-18 20:13:50 -04002090 dev_info(&dev->dev, "Linking AER extended capability\n");
Brice Goglincf34a8e2006-06-13 14:35:42 -04002091 }
2092 }
2093}
2094DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2095 quirk_nvidia_ck804_pcie_aer_ext_cap);
Rafael J. Wysockie1a2a512008-05-15 21:51:31 +02002096DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
Alan Cox1597cac2006-12-04 15:14:45 -08002097 quirk_nvidia_ck804_pcie_aer_ext_cap);
Brice Goglincf34a8e2006-06-13 14:35:42 -04002098
Bill Pemberton15856ad2012-11-21 15:35:00 -05002099static void quirk_via_cx700_pci_parking_caching(struct pci_dev *dev)
Tim Yamin53a9bf42007-11-01 23:14:54 +00002100{
2101 /*
2102 * Disable PCI Bus Parking and PCI Master read caching on CX700
2103 * which causes unspecified timing errors with a VT6212L on the PCI
Tim Yaminca846392010-03-19 14:22:58 -07002104 * bus leading to USB2.0 packet loss.
2105 *
2106 * This quirk is only enabled if a second (on the external PCI bus)
2107 * VT6212L is found -- the CX700 core itself also contains a USB
2108 * host controller with the same PCI ID as the VT6212L.
Tim Yamin53a9bf42007-11-01 23:14:54 +00002109 */
2110
Tim Yaminca846392010-03-19 14:22:58 -07002111 /* Count VT6212L instances */
2112 struct pci_dev *p = pci_get_device(PCI_VENDOR_ID_VIA,
2113 PCI_DEVICE_ID_VIA_8235_USB_2, NULL);
Tim Yamin53a9bf42007-11-01 23:14:54 +00002114 uint8_t b;
Tim Yaminca846392010-03-19 14:22:58 -07002115
2116 /* p should contain the first (internal) VT6212L -- see if we have
2117 an external one by searching again */
2118 p = pci_get_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8235_USB_2, p);
2119 if (!p)
2120 return;
2121 pci_dev_put(p);
2122
Tim Yamin53a9bf42007-11-01 23:14:54 +00002123 if (pci_read_config_byte(dev, 0x76, &b) == 0) {
2124 if (b & 0x40) {
2125 /* Turn off PCI Bus Parking */
2126 pci_write_config_byte(dev, 0x76, b ^ 0x40);
2127
Ryan Desfosses227f0642014-04-18 20:13:50 -04002128 dev_info(&dev->dev, "Disabling VIA CX700 PCI parking\n");
Tim Yaminbc043272008-03-30 20:58:59 +01002129 }
2130 }
2131
2132 if (pci_read_config_byte(dev, 0x72, &b) == 0) {
2133 if (b != 0) {
Tim Yamin53a9bf42007-11-01 23:14:54 +00002134 /* Turn off PCI Master read caching */
2135 pci_write_config_byte(dev, 0x72, 0x0);
Tim Yaminbc043272008-03-30 20:58:59 +01002136
2137 /* Set PCI Master Bus time-out to "1x16 PCLK" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00002138 pci_write_config_byte(dev, 0x75, 0x1);
Tim Yaminbc043272008-03-30 20:58:59 +01002139
2140 /* Disable "Read FIFO Timer" */
Tim Yamin53a9bf42007-11-01 23:14:54 +00002141 pci_write_config_byte(dev, 0x77, 0x0);
2142
Ryan Desfosses227f0642014-04-18 20:13:50 -04002143 dev_info(&dev->dev, "Disabling VIA CX700 PCI caching\n");
Tim Yamin53a9bf42007-11-01 23:14:54 +00002144 }
2145 }
2146}
Tim Yaminca846392010-03-19 14:22:58 -07002147DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0x324e, quirk_via_cx700_pci_parking_caching);
Tim Yamin53a9bf42007-11-01 23:14:54 +00002148
Benjamin Li99cb233d2008-07-02 10:59:04 -07002149/*
Babu Moger7c200782016-02-15 09:42:02 +01002150 * If a device follows the VPD format spec, the PCI core will not read or
2151 * write past the VPD End Tag. But some vendors do not follow the VPD
2152 * format spec, so we can't tell how much data is safe to access. Devices
2153 * may behave unpredictably if we access too much. Blacklist these devices
2154 * so we don't touch VPD at all.
2155 */
2156static void quirk_blacklist_vpd(struct pci_dev *dev)
2157{
2158 if (dev->vpd) {
2159 dev->vpd->len = 0;
Bjorn Helgaas8ae72422017-04-04 19:32:14 +00002160 dev_warn(&dev->dev, FW_BUG "disabling VPD access (can't determine size of non-standard VPD format)\n");
Babu Moger7c200782016-02-15 09:42:02 +01002161 }
2162}
2163
2164DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0060, quirk_blacklist_vpd);
2165DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x007c, quirk_blacklist_vpd);
2166DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0413, quirk_blacklist_vpd);
2167DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0078, quirk_blacklist_vpd);
2168DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0079, quirk_blacklist_vpd);
2169DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0073, quirk_blacklist_vpd);
2170DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x0071, quirk_blacklist_vpd);
2171DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005b, quirk_blacklist_vpd);
2172DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x002f, quirk_blacklist_vpd);
2173DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005d, quirk_blacklist_vpd);
2174DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_LSI_LOGIC, 0x005f, quirk_blacklist_vpd);
2175DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, PCI_ANY_ID,
2176 quirk_blacklist_vpd);
Ethan Zhaoed99f5a2017-02-27 17:08:44 +09002177DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_QLOGIC, 0x2261, quirk_blacklist_vpd);
Babu Moger7c200782016-02-15 09:42:02 +01002178
2179/*
Benjamin Li99cb233d2008-07-02 10:59:04 -07002180 * For Broadcom 5706, 5708, 5709 rev. A nics, any read beyond the
2181 * VPD end tag will hang the device. This problem was initially
2182 * observed when a vpd entry was created in sysfs
2183 * ('/sys/bus/pci/devices/<id>/vpd'). A read to this sysfs entry
2184 * will dump 32k of data. Reading a full 32k will cause an access
2185 * beyond the VPD end tag causing the device to hang. Once the device
2186 * is hung, the bnx2 driver will not be able to reset the device.
2187 * We believe that it is legal to read beyond the end tag and
2188 * therefore the solution is to limit the read/write length.
2189 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002190static void quirk_brcm_570x_limit_vpd(struct pci_dev *dev)
Benjamin Li99cb233d2008-07-02 10:59:04 -07002191{
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002192 /*
Dean Hildebrand35405f22008-08-07 17:31:45 -07002193 * Only disable the VPD capability for 5706, 5706S, 5708,
2194 * 5708S and 5709 rev. A
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002195 */
Benjamin Li99cb233d2008-07-02 10:59:04 -07002196 if ((dev->device == PCI_DEVICE_ID_NX2_5706) ||
Dean Hildebrand35405f22008-08-07 17:31:45 -07002197 (dev->device == PCI_DEVICE_ID_NX2_5706S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002198 (dev->device == PCI_DEVICE_ID_NX2_5708) ||
Eric Dumazet9d82d8e2008-07-31 20:27:31 +02002199 (dev->device == PCI_DEVICE_ID_NX2_5708S) ||
Benjamin Li99cb233d2008-07-02 10:59:04 -07002200 ((dev->device == PCI_DEVICE_ID_NX2_5709) &&
2201 (dev->revision & 0xf0) == 0x0)) {
2202 if (dev->vpd)
2203 dev->vpd->len = 0x80;
2204 }
2205}
2206
Yu Zhaobffadff2008-10-28 14:44:11 +08002207DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2208 PCI_DEVICE_ID_NX2_5706,
2209 quirk_brcm_570x_limit_vpd);
2210DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2211 PCI_DEVICE_ID_NX2_5706S,
2212 quirk_brcm_570x_limit_vpd);
2213DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2214 PCI_DEVICE_ID_NX2_5708,
2215 quirk_brcm_570x_limit_vpd);
2216DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2217 PCI_DEVICE_ID_NX2_5708S,
2218 quirk_brcm_570x_limit_vpd);
2219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2220 PCI_DEVICE_ID_NX2_5709,
2221 quirk_brcm_570x_limit_vpd);
2222DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2223 PCI_DEVICE_ID_NX2_5709S,
2224 quirk_brcm_570x_limit_vpd);
Benjamin Li99cb233d2008-07-02 10:59:04 -07002225
Myron Stowe25e742b2012-07-09 15:36:14 -06002226static void quirk_brcm_5719_limit_mrrs(struct pci_dev *dev)
Matt Carlson0b471502012-02-27 09:44:48 +00002227{
2228 u32 rev;
2229
2230 pci_read_config_dword(dev, 0xf4, &rev);
2231
2232 /* Only CAP the MRRS if the device is a 5719 A0 */
2233 if (rev == 0x05719000) {
2234 int readrq = pcie_get_readrq(dev);
2235 if (readrq > 2048)
2236 pcie_set_readrq(dev, 2048);
2237 }
2238}
2239
2240DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_BROADCOM,
2241 PCI_DEVICE_ID_TIGON3_5719,
2242 quirk_brcm_5719_limit_mrrs);
2243
Jon Mason28dd2312017-04-04 19:32:33 +00002244#ifdef CONFIG_PCIE_IPROC_PLATFORM
2245static void quirk_paxc_bridge(struct pci_dev *pdev)
2246{
2247 /* The PCI config space is shared with the PAXC root port and the first
2248 * Ethernet device. So, we need to workaround this by telling the PCI
2249 * code that the bridge is not an Ethernet device.
2250 */
2251 if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2252 pdev->class = PCI_CLASS_BRIDGE_PCI << 8;
2253
2254 /* MPSS is not being set properly (as it is currently 0). This is
2255 * because that area of the PCI config space is hard coded to zero, and
2256 * is not modifiable by firmware. Set this to 2 (e.g., 512 byte MPS)
2257 * so that the MPS can be set to the real max value.
2258 */
2259 pdev->pcie_mpss = 2;
2260}
2261DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16cd, quirk_paxc_bridge);
2262DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x16f0, quirk_paxc_bridge);
2263#endif
2264
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002265/* Originally in EDAC sources for i82875P:
2266 * Intel tells BIOS developers to hide device 6 which
2267 * configures the overflow device access containing
2268 * the DRBs - this is where we expose device 6.
2269 * http://www.x86-secret.com/articles/tweak/pat/patsecrets-2.htm
2270 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002271static void quirk_unhide_mch_dev6(struct pci_dev *dev)
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002272{
2273 u8 reg;
2274
2275 if (pci_read_config_byte(dev, 0xF4, &reg) == 0 && !(reg & 0x02)) {
2276 dev_info(&dev->dev, "Enabling MCH 'Overflow' Device\n");
2277 pci_write_config_byte(dev, 0xF4, reg | 0x02);
2278 }
2279}
2280
2281DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865_HB,
2282 quirk_unhide_mch_dev6);
2283DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82875_HB,
2284 quirk_unhide_mch_dev6);
2285
Chris Metcalf12962262012-04-07 17:10:17 -04002286#ifdef CONFIG_TILEPRO
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002287/*
Chris Metcalf12962262012-04-07 17:10:17 -04002288 * The Tilera TILEmpower tilepro platform needs to set the link speed
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002289 * to 2.5GT(Giga-Transfers)/s (Gen 1). The default link speed
2290 * setting is 5GT/s (Gen 2). 0x98 is the Link Control2 PCIe
2291 * capability register of the PEX8624 PCIe switch. The switch
2292 * supports link speed auto negotiation, but falsely sets
2293 * the link speed to 5GT/s.
2294 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002295static void quirk_tile_plx_gen1(struct pci_dev *dev)
Chris Metcalff02cbbe2010-11-02 12:05:10 -04002296{
2297 if (tile_plx_gen1) {
2298 pci_write_config_dword(dev, 0x98, 0x1);
2299 mdelay(50);
2300 }
2301}
2302DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_PLX, 0x8624, quirk_tile_plx_gen1);
Chris Metcalf12962262012-04-07 17:10:17 -04002303#endif /* CONFIG_TILEPRO */
Michal Miroslaw26c56dc2009-05-12 13:49:26 -07002304
Brice Goglin3f79e102006-08-31 01:54:56 -04002305#ifdef CONFIG_PCI_MSI
Tejun Heoebdf7d32007-05-31 00:40:48 -07002306/* Some chipsets do not support MSI. We cannot easily rely on setting
2307 * PCI_BUS_FLAGS_NO_MSI in its bus flags because there are actually
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002308 * some other buses controlled by the chipset even if Linux is not
2309 * aware of it. Instead of setting the flag on all buses in the
Tejun Heoebdf7d32007-05-31 00:40:48 -07002310 * machine, simply disable MSI globally.
Brice Goglin3f79e102006-08-31 01:54:56 -04002311 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002312static void quirk_disable_all_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04002313{
Michael Ellerman88187df2007-01-25 19:34:07 +11002314 pci_no_msi();
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002315 dev_warn(&dev->dev, "MSI quirk detected; MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002316}
Tejun Heoebdf7d32007-05-31 00:40:48 -07002317DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_GCNB_LE, quirk_disable_all_msi);
2318DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS400_200, quirk_disable_all_msi);
2319DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_RS480, quirk_disable_all_msi);
Tejun Heo66d715c2008-07-04 09:59:32 -07002320DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3336, quirk_disable_all_msi);
Jay Cliburn184b8122007-05-26 17:01:04 -05002321DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3351, quirk_disable_all_msi);
Thomas Renninger162dedd2009-04-03 06:34:00 -07002322DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_VT3364, quirk_disable_all_msi);
Tejun Heo549e1562010-05-23 10:22:55 +02002323DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_8380_0, quirk_disable_all_msi);
Ondrej Zary10b4ad12015-09-24 17:02:07 -05002324DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SI, 0x0761, quirk_disable_all_msi);
Brice Goglin3f79e102006-08-31 01:54:56 -04002325
2326/* Disable MSI on chipsets that are known to not support it */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002327static void quirk_disable_msi(struct pci_dev *dev)
Brice Goglin3f79e102006-08-31 01:54:56 -04002328{
2329 if (dev->subordinate) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002330 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
Brice Goglin3f79e102006-08-31 01:54:56 -04002331 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2332 }
2333}
2334DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8131_BRIDGE, quirk_disable_msi);
Matthew Wilcox134b3452010-03-24 07:11:01 -06002335DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_VIA, 0xa238, quirk_disable_msi);
Alex Deucher9313ff42010-05-18 10:42:53 -04002336DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x5a3f, quirk_disable_msi);
Brice Goglin6397c752006-08-31 01:55:32 -04002337
Clemens Ladischaff61362010-05-26 12:21:10 +02002338/*
2339 * The APC bridge device in AMD 780 family northbridges has some random
2340 * OEM subsystem ID in its vendor ID register (erratum 18), so instead
2341 * we use the possible vendor/device IDs of the host bridge for the
2342 * declared quirk, and search for the APC bridge by slot number.
2343 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002344static void quirk_amd_780_apc_msi(struct pci_dev *host_bridge)
Clemens Ladischaff61362010-05-26 12:21:10 +02002345{
2346 struct pci_dev *apc_bridge;
2347
2348 apc_bridge = pci_get_slot(host_bridge->bus, PCI_DEVFN(1, 0));
2349 if (apc_bridge) {
2350 if (apc_bridge->device == 0x9602)
2351 quirk_disable_msi(apc_bridge);
2352 pci_dev_put(apc_bridge);
2353 }
2354}
2355DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9600, quirk_amd_780_apc_msi);
2356DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AMD, 0x9601, quirk_amd_780_apc_msi);
2357
Brice Goglin6397c752006-08-31 01:55:32 -04002358/* Go through the list of Hypertransport capabilities and
2359 * return 1 if a HT MSI capability is found and enabled */
Myron Stowe25e742b2012-07-09 15:36:14 -06002360static int msi_ht_cap_enabled(struct pci_dev *dev)
Brice Goglin6397c752006-08-31 01:55:32 -04002361{
Wei Yangfff905f2015-06-30 09:16:41 +08002362 int pos, ttl = PCI_FIND_CAP_TTL;
Michael Ellerman7a380502006-11-22 18:26:21 +11002363
2364 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2365 while (pos && ttl--) {
2366 u8 flags;
2367
2368 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04002369 &flags) == 0) {
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002370 dev_info(&dev->dev, "Found %s HT MSI Mapping\n",
Michael Ellerman7a380502006-11-22 18:26:21 +11002371 flags & HT_MSI_FLAGS_ENABLE ?
bjorn.helgaas@hp.comf0fda802007-12-17 14:09:39 -07002372 "enabled" : "disabled");
Michael Ellerman7a380502006-11-22 18:26:21 +11002373 return (flags & HT_MSI_FLAGS_ENABLE) != 0;
Brice Goglin6397c752006-08-31 01:55:32 -04002374 }
Michael Ellerman7a380502006-11-22 18:26:21 +11002375
2376 pos = pci_find_next_ht_capability(dev, pos,
2377 HT_CAPTYPE_MSI_MAPPING);
Brice Goglin6397c752006-08-31 01:55:32 -04002378 }
2379 return 0;
2380}
2381
2382/* Check the hypertransport MSI mapping to know whether MSI is enabled or not */
Myron Stowe25e742b2012-07-09 15:36:14 -06002383static void quirk_msi_ht_cap(struct pci_dev *dev)
Brice Goglin6397c752006-08-31 01:55:32 -04002384{
2385 if (dev->subordinate && !msi_ht_cap_enabled(dev)) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002386 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002387 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2388 }
2389}
2390DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_SERVERWORKS, PCI_DEVICE_ID_SERVERWORKS_HT2000_PCIE,
2391 quirk_msi_ht_cap);
Sebastien Dugue6bae1d92007-12-13 16:09:25 -08002392
Brice Goglin6397c752006-08-31 01:55:32 -04002393/* The nVidia CK804 chipset may have 2 HT MSI mappings.
2394 * MSI are supported if the MSI capability set in any of these mappings.
2395 */
Myron Stowe25e742b2012-07-09 15:36:14 -06002396static void quirk_nvidia_ck804_msi_ht_cap(struct pci_dev *dev)
Brice Goglin6397c752006-08-31 01:55:32 -04002397{
2398 struct pci_dev *pdev;
2399
2400 if (!dev->subordinate)
2401 return;
2402
2403 /* check HT MSI cap on this chipset and the root one.
2404 * a single one having MSI is enough to be sure that MSI are supported.
2405 */
Alan Cox11f242f2006-10-10 14:39:00 -07002406 pdev = pci_get_slot(dev->bus, 0);
Jesper Juhl9ac0ce82006-12-04 15:14:48 -08002407 if (!pdev)
2408 return;
David Rientjes0c875c22006-12-03 11:55:34 -08002409 if (!msi_ht_cap_enabled(dev) && !msi_ht_cap_enabled(pdev)) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002410 dev_warn(&dev->dev, "MSI quirk detected; subordinate MSI disabled\n");
Brice Goglin6397c752006-08-31 01:55:32 -04002411 dev->subordinate->bus_flags |= PCI_BUS_FLAGS_NO_MSI;
2412 }
Alan Cox11f242f2006-10-10 14:39:00 -07002413 pci_dev_put(pdev);
Brice Goglin6397c752006-08-31 01:55:32 -04002414}
2415DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_CK804_PCIE,
2416 quirk_nvidia_ck804_msi_ht_cap);
David Millerba698ad2007-10-25 01:16:30 -07002417
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002418/* Force enable MSI mapping capability on HT bridges */
Myron Stowe25e742b2012-07-09 15:36:14 -06002419static void ht_enable_msi_mapping(struct pci_dev *dev)
Peer Chen9dc625e2008-02-04 23:50:13 -08002420{
Wei Yangfff905f2015-06-30 09:16:41 +08002421 int pos, ttl = PCI_FIND_CAP_TTL;
Peer Chen9dc625e2008-02-04 23:50:13 -08002422
2423 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2424 while (pos && ttl--) {
2425 u8 flags;
2426
2427 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2428 &flags) == 0) {
2429 dev_info(&dev->dev, "Enabling HT MSI Mapping\n");
2430
2431 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2432 flags | HT_MSI_FLAGS_ENABLE);
2433 }
2434 pos = pci_find_next_ht_capability(dev, pos,
2435 HT_CAPTYPE_MSI_MAPPING);
2436 }
2437}
Bjorn Helgaas415b6d02008-02-29 16:04:39 -07002438DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SERVERWORKS,
2439 PCI_DEVICE_ID_SERVERWORKS_HT1000_PXB,
2440 ht_enable_msi_mapping);
Peer Chen9dc625e2008-02-04 23:50:13 -08002441
Yinghai Lue0ae4f52009-02-17 20:40:09 -08002442DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8132_BRIDGE,
2443 ht_enable_msi_mapping);
2444
Ben Hutchingse4146bb2010-05-16 02:28:49 +01002445/* The P5N32-SLI motherboards from Asus have a problem with msi
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002446 * for the MCP55 NIC. It is not yet determined whether the msi problem
2447 * also affects other devices. As for now, turn off msi for this device.
2448 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002449static void nvenet_msi_disable(struct pci_dev *dev)
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002450{
Jean Delvare9251bac2011-05-15 18:13:46 +02002451 const char *board_name = dmi_get_system_info(DMI_BOARD_NAME);
2452
2453 if (board_name &&
2454 (strstr(board_name, "P5N32-SLI PREMIUM") ||
2455 strstr(board_name, "P5N32-E SLI"))) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002456 dev_info(&dev->dev, "Disabling msi for MCP55 NIC on P5N32-SLI\n");
Andreas Petlund75e07fc2008-11-20 20:42:25 -08002457 dev->no_msi = 1;
2458 }
2459}
2460DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2461 PCI_DEVICE_ID_NVIDIA_NVENET_15,
2462 nvenet_msi_disable);
2463
Neil Horman66db60e2010-09-21 13:54:39 -04002464/*
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002465 * Some versions of the MCP55 bridge from Nvidia have a legacy IRQ routing
2466 * config register. This register controls the routing of legacy
2467 * interrupts from devices that route through the MCP55. If this register
2468 * is misprogrammed, interrupts are only sent to the BSP, unlike
2469 * conventional systems where the IRQ is broadcast to all online CPUs. Not
2470 * having this register set properly prevents kdump from booting up
2471 * properly, so let's make sure that we have it set correctly.
2472 * Note that this is an undocumented register.
Neil Horman66db60e2010-09-21 13:54:39 -04002473 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002474static void nvbridge_check_legacy_irq_routing(struct pci_dev *dev)
Neil Horman66db60e2010-09-21 13:54:39 -04002475{
2476 u32 cfg;
2477
Neil Horman49c2fa082010-12-08 09:47:48 -05002478 if (!pci_find_capability(dev, PCI_CAP_ID_HT))
2479 return;
2480
Neil Horman66db60e2010-09-21 13:54:39 -04002481 pci_read_config_dword(dev, 0x74, &cfg);
2482
2483 if (cfg & ((1 << 2) | (1 << 15))) {
2484 printk(KERN_INFO "Rewriting irq routing register on MCP55\n");
2485 cfg &= ~((1 << 2) | (1 << 15));
2486 pci_write_config_dword(dev, 0x74, cfg);
2487 }
2488}
2489
2490DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2491 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V0,
2492 nvbridge_check_legacy_irq_routing);
2493
2494DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_NVIDIA,
2495 PCI_DEVICE_ID_NVIDIA_MCP55_BRIDGE_V4,
2496 nvbridge_check_legacy_irq_routing);
2497
Myron Stowe25e742b2012-07-09 15:36:14 -06002498static int ht_check_msi_mapping(struct pci_dev *dev)
Yinghai Lude745302009-03-20 19:29:41 -07002499{
Wei Yangfff905f2015-06-30 09:16:41 +08002500 int pos, ttl = PCI_FIND_CAP_TTL;
Yinghai Lude745302009-03-20 19:29:41 -07002501 int found = 0;
2502
2503 /* check if there is HT MSI cap or enabled on this device */
2504 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2505 while (pos && ttl--) {
2506 u8 flags;
2507
2508 if (found < 1)
2509 found = 1;
2510 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2511 &flags) == 0) {
2512 if (flags & HT_MSI_FLAGS_ENABLE) {
2513 if (found < 2) {
2514 found = 2;
2515 break;
2516 }
2517 }
2518 }
2519 pos = pci_find_next_ht_capability(dev, pos,
2520 HT_CAPTYPE_MSI_MAPPING);
2521 }
2522
2523 return found;
2524}
2525
Myron Stowe25e742b2012-07-09 15:36:14 -06002526static int host_bridge_with_leaf(struct pci_dev *host_bridge)
Yinghai Lude745302009-03-20 19:29:41 -07002527{
2528 struct pci_dev *dev;
2529 int pos;
2530 int i, dev_no;
2531 int found = 0;
2532
2533 dev_no = host_bridge->devfn >> 3;
2534 for (i = dev_no + 1; i < 0x20; i++) {
2535 dev = pci_get_slot(host_bridge->bus, PCI_DEVFN(i, 0));
2536 if (!dev)
2537 continue;
2538
2539 /* found next host bridge ?*/
2540 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2541 if (pos != 0) {
2542 pci_dev_put(dev);
2543 break;
2544 }
2545
2546 if (ht_check_msi_mapping(dev)) {
2547 found = 1;
2548 pci_dev_put(dev);
2549 break;
2550 }
2551 pci_dev_put(dev);
2552 }
2553
2554 return found;
2555}
2556
Yinghai Lueeafda72009-03-29 12:30:05 -07002557#define PCI_HT_CAP_SLAVE_CTRL0 4 /* link control */
2558#define PCI_HT_CAP_SLAVE_CTRL1 8 /* link control to */
2559
Myron Stowe25e742b2012-07-09 15:36:14 -06002560static int is_end_of_ht_chain(struct pci_dev *dev)
Yinghai Lueeafda72009-03-29 12:30:05 -07002561{
2562 int pos, ctrl_off;
2563 int end = 0;
2564 u16 flags, ctrl;
2565
2566 pos = pci_find_ht_capability(dev, HT_CAPTYPE_SLAVE);
2567
2568 if (!pos)
2569 goto out;
2570
2571 pci_read_config_word(dev, pos + PCI_CAP_FLAGS, &flags);
2572
2573 ctrl_off = ((flags >> 10) & 1) ?
2574 PCI_HT_CAP_SLAVE_CTRL0 : PCI_HT_CAP_SLAVE_CTRL1;
2575 pci_read_config_word(dev, pos + ctrl_off, &ctrl);
2576
2577 if (ctrl & (1 << 6))
2578 end = 1;
2579
2580out:
2581 return end;
2582}
2583
Myron Stowe25e742b2012-07-09 15:36:14 -06002584static void nv_ht_enable_msi_mapping(struct pci_dev *dev)
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002585{
2586 struct pci_dev *host_bridge;
2587 int pos;
2588 int i, dev_no;
2589 int found = 0;
2590
2591 dev_no = dev->devfn >> 3;
2592 for (i = dev_no; i >= 0; i--) {
2593 host_bridge = pci_get_slot(dev->bus, PCI_DEVFN(i, 0));
2594 if (!host_bridge)
2595 continue;
2596
2597 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2598 if (pos != 0) {
2599 found = 1;
2600 break;
2601 }
2602 pci_dev_put(host_bridge);
2603 }
2604
2605 if (!found)
2606 return;
2607
Yinghai Lueeafda72009-03-29 12:30:05 -07002608 /* don't enable end_device/host_bridge with leaf directly here */
2609 if (host_bridge == dev && is_end_of_ht_chain(host_bridge) &&
2610 host_bridge_with_leaf(host_bridge))
Yinghai Lude745302009-03-20 19:29:41 -07002611 goto out;
2612
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002613 /* root did that ! */
2614 if (msi_ht_cap_enabled(host_bridge))
2615 goto out;
2616
2617 ht_enable_msi_mapping(dev);
2618
2619out:
2620 pci_dev_put(host_bridge);
2621}
2622
Myron Stowe25e742b2012-07-09 15:36:14 -06002623static void ht_disable_msi_mapping(struct pci_dev *dev)
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002624{
Wei Yangfff905f2015-06-30 09:16:41 +08002625 int pos, ttl = PCI_FIND_CAP_TTL;
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002626
2627 pos = pci_find_ht_capability(dev, HT_CAPTYPE_MSI_MAPPING);
2628 while (pos && ttl--) {
2629 u8 flags;
2630
2631 if (pci_read_config_byte(dev, pos + HT_MSI_FLAGS,
2632 &flags) == 0) {
Prakash Punnoor6a958d52009-03-06 10:10:35 +01002633 dev_info(&dev->dev, "Disabling HT MSI Mapping\n");
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002634
2635 pci_write_config_byte(dev, pos + HT_MSI_FLAGS,
2636 flags & ~HT_MSI_FLAGS_ENABLE);
2637 }
2638 pos = pci_find_next_ht_capability(dev, pos,
2639 HT_CAPTYPE_MSI_MAPPING);
2640 }
2641}
2642
Myron Stowe25e742b2012-07-09 15:36:14 -06002643static void __nv_msi_ht_cap_quirk(struct pci_dev *dev, int all)
Peer Chen9dc625e2008-02-04 23:50:13 -08002644{
2645 struct pci_dev *host_bridge;
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002646 int pos;
2647 int found;
2648
Rafael J. Wysocki3d2a5312010-07-23 22:19:55 +02002649 if (!pci_msi_enabled())
2650 return;
2651
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002652 /* check if there is HT MSI cap or enabled on this device */
2653 found = ht_check_msi_mapping(dev);
2654
2655 /* no HT MSI CAP */
2656 if (found == 0)
2657 return;
Peer Chen9dc625e2008-02-04 23:50:13 -08002658
2659 /*
2660 * HT MSI mapping should be disabled on devices that are below
2661 * a non-Hypertransport host bridge. Locate the host bridge...
2662 */
2663 host_bridge = pci_get_bus_and_slot(0, PCI_DEVFN(0, 0));
2664 if (host_bridge == NULL) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002665 dev_warn(&dev->dev, "nv_msi_ht_cap_quirk didn't locate host bridge\n");
Peer Chen9dc625e2008-02-04 23:50:13 -08002666 return;
2667 }
2668
2669 pos = pci_find_ht_capability(host_bridge, HT_CAPTYPE_SLAVE);
2670 if (pos != 0) {
2671 /* Host bridge is to HT */
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002672 if (found == 1) {
2673 /* it is not enabled, try to enable it */
Yinghai Lude745302009-03-20 19:29:41 -07002674 if (all)
2675 ht_enable_msi_mapping(dev);
2676 else
2677 nv_ht_enable_msi_mapping(dev);
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002678 }
Myron Stowedff3aef2012-07-09 15:36:08 -06002679 goto out;
Peer Chen9dc625e2008-02-04 23:50:13 -08002680 }
2681
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002682 /* HT MSI is not enabled */
2683 if (found == 1)
Myron Stowedff3aef2012-07-09 15:36:08 -06002684 goto out;
Peer Chen9dc625e2008-02-04 23:50:13 -08002685
Yinghai Lu1dec6b02009-02-23 11:51:59 -08002686 /* Host bridge is not to HT, disable HT MSI mapping on this device */
2687 ht_disable_msi_mapping(dev);
Myron Stowedff3aef2012-07-09 15:36:08 -06002688
2689out:
2690 pci_dev_put(host_bridge);
Peer Chen9dc625e2008-02-04 23:50:13 -08002691}
Yinghai Lude745302009-03-20 19:29:41 -07002692
Myron Stowe25e742b2012-07-09 15:36:14 -06002693static void nv_msi_ht_cap_quirk_all(struct pci_dev *dev)
Yinghai Lude745302009-03-20 19:29:41 -07002694{
2695 return __nv_msi_ht_cap_quirk(dev, 1);
2696}
2697
Myron Stowe25e742b2012-07-09 15:36:14 -06002698static void nv_msi_ht_cap_quirk_leaf(struct pci_dev *dev)
Yinghai Lude745302009-03-20 19:29:41 -07002699{
2700 return __nv_msi_ht_cap_quirk(dev, 0);
2701}
2702
2703DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002704DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, nv_msi_ht_cap_quirk_leaf);
Yinghai Lude745302009-03-20 19:29:41 -07002705
2706DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Tejun Heo6dab62e2009-07-21 16:08:43 -07002707DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_AL, PCI_ANY_ID, nv_msi_ht_cap_quirk_all);
Peer Chen9dc625e2008-02-04 23:50:13 -08002708
Bill Pemberton15856ad2012-11-21 15:35:00 -05002709static void quirk_msi_intx_disable_bug(struct pci_dev *dev)
David Millerba698ad2007-10-25 01:16:30 -07002710{
2711 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2712}
Bill Pemberton15856ad2012-11-21 15:35:00 -05002713static void quirk_msi_intx_disable_ati_bug(struct pci_dev *dev)
Shane Huang4600c9d2008-01-25 15:46:24 +09002714{
2715 struct pci_dev *p;
2716
2717 /* SB700 MSI issue will be fixed at HW level from revision A21,
2718 * we need check PCI REVISION ID of SMBus controller to get SB700
2719 * revision.
2720 */
2721 p = pci_get_device(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS,
2722 NULL);
2723 if (!p)
2724 return;
2725
2726 if ((p->revision < 0x3B) && (p->revision >= 0x30))
2727 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2728 pci_dev_put(p);
2729}
Xiong Huang70588812013-03-07 08:55:16 +00002730static void quirk_msi_intx_disable_qca_bug(struct pci_dev *dev)
2731{
2732 /* AR816X/AR817X/E210X MSI is fixed at HW level from revision 0x18 */
2733 if (dev->revision < 0x18) {
2734 dev_info(&dev->dev, "set MSI_INTX_DISABLE_BUG flag\n");
2735 dev->dev_flags |= PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG;
2736 }
2737}
David Millerba698ad2007-10-25 01:16:30 -07002738DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2739 PCI_DEVICE_ID_TIGON3_5780,
2740 quirk_msi_intx_disable_bug);
2741DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2742 PCI_DEVICE_ID_TIGON3_5780S,
2743 quirk_msi_intx_disable_bug);
2744DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2745 PCI_DEVICE_ID_TIGON3_5714,
2746 quirk_msi_intx_disable_bug);
2747DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2748 PCI_DEVICE_ID_TIGON3_5714S,
2749 quirk_msi_intx_disable_bug);
2750DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2751 PCI_DEVICE_ID_TIGON3_5715,
2752 quirk_msi_intx_disable_bug);
2753DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_BROADCOM,
2754 PCI_DEVICE_ID_TIGON3_5715S,
2755 quirk_msi_intx_disable_bug);
2756
David Millerbc38b412007-10-25 01:16:52 -07002757DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4390,
Shane Huang4600c9d2008-01-25 15:46:24 +09002758 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002759DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4391,
Shane Huang4600c9d2008-01-25 15:46:24 +09002760 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002761DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4392,
Shane Huang4600c9d2008-01-25 15:46:24 +09002762 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002763DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4393,
Shane Huang4600c9d2008-01-25 15:46:24 +09002764 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002765DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4394,
Shane Huang4600c9d2008-01-25 15:46:24 +09002766 quirk_msi_intx_disable_ati_bug);
David Millerbc38b412007-10-25 01:16:52 -07002767
2768DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4373,
2769 quirk_msi_intx_disable_bug);
2770DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4374,
2771 quirk_msi_intx_disable_bug);
2772DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATI, 0x4375,
2773 quirk_msi_intx_disable_bug);
2774
Huang, Xiong7cb6a292012-04-30 15:38:49 +00002775DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1062,
2776 quirk_msi_intx_disable_bug);
2777DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1063,
2778 quirk_msi_intx_disable_bug);
2779DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2060,
2780 quirk_msi_intx_disable_bug);
2781DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x2062,
2782 quirk_msi_intx_disable_bug);
2783DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1073,
2784 quirk_msi_intx_disable_bug);
2785DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1083,
2786 quirk_msi_intx_disable_bug);
Xiong Huang70588812013-03-07 08:55:16 +00002787DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1090,
2788 quirk_msi_intx_disable_qca_bug);
2789DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x1091,
2790 quirk_msi_intx_disable_qca_bug);
2791DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a0,
2792 quirk_msi_intx_disable_qca_bug);
2793DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0x10a1,
2794 quirk_msi_intx_disable_qca_bug);
2795DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_ATTANSIC, 0xe091,
2796 quirk_msi_intx_disable_qca_bug);
Brice Goglin3f79e102006-08-31 01:54:56 -04002797#endif /* CONFIG_PCI_MSI */
Thomas Petazzoni3d137312008-08-19 10:28:24 +02002798
Felix Radensky33223402010-03-28 16:02:02 +03002799/* Allow manual resource allocation for PCI hotplug bridges
2800 * via pci=hpmemsize=nnM and pci=hpiosize=nnM parameters. For
2801 * some PCI-PCI hotplug bridges, like PLX 6254 (former HINT HB6),
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002802 * kernel fails to allocate resources when hotplug device is
Felix Radensky33223402010-03-28 16:02:02 +03002803 * inserted and PCI bus is rescanned.
2804 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002805static void quirk_hotplug_bridge(struct pci_dev *dev)
Felix Radensky33223402010-03-28 16:02:02 +03002806{
2807 dev->is_hotplug_bridge = 1;
2808}
2809
2810DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_HINT, 0x0020, quirk_hotplug_bridge);
2811
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002812/*
2813 * This is a quirk for the Ricoh MMC controller found as a part of
2814 * some mulifunction chips.
2815
Lucas De Marchi25985ed2011-03-30 22:57:33 -03002816 * This is very similar and based on the ricoh_mmc driver written by
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002817 * Philip Langdale. Thank you for these magic sequences.
2818 *
2819 * These chips implement the four main memory card controllers (SD, MMC, MS, xD)
2820 * and one or both of cardbus or firewire.
2821 *
2822 * It happens that they implement SD and MMC
2823 * support as separate controllers (and PCI functions). The linux SDHCI
2824 * driver supports MMC cards but the chip detects MMC cards in hardware
2825 * and directs them to the MMC controller - so the SDHCI driver never sees
2826 * them.
2827 *
2828 * To get around this, we must disable the useless MMC controller.
2829 * At that point, the SDHCI controller will start seeing them
2830 * It seems to be the case that the relevant PCI registers to deactivate the
2831 * MMC controller live on PCI function 0, which might be the cardbus controller
2832 * or the firewire controller, depending on the particular chip in question
2833 *
2834 * This has to be done early, because as soon as we disable the MMC controller
2835 * other pci functions shift up one level, e.g. function #2 becomes function
2836 * #1, and this will confuse the pci core.
2837 */
2838
2839#ifdef CONFIG_MMC_RICOH_MMC
2840static void ricoh_mmc_fixup_rl5c476(struct pci_dev *dev)
2841{
2842 /* disable via cardbus interface */
2843 u8 write_enable;
2844 u8 write_target;
2845 u8 disable;
2846
2847 /* disable must be done via function #0 */
2848 if (PCI_FUNC(dev->devfn))
2849 return;
2850
2851 pci_read_config_byte(dev, 0xB7, &disable);
2852 if (disable & 0x02)
2853 return;
2854
2855 pci_read_config_byte(dev, 0x8E, &write_enable);
2856 pci_write_config_byte(dev, 0x8E, 0xAA);
2857 pci_read_config_byte(dev, 0x8D, &write_target);
2858 pci_write_config_byte(dev, 0x8D, 0xB7);
2859 pci_write_config_byte(dev, 0xB7, disable | 0x02);
2860 pci_write_config_byte(dev, 0x8E, write_enable);
2861 pci_write_config_byte(dev, 0x8D, write_target);
2862
2863 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via cardbus function)\n");
2864 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2865}
2866DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2867DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_RL5C476, ricoh_mmc_fixup_rl5c476);
2868
2869static void ricoh_mmc_fixup_r5c832(struct pci_dev *dev)
2870{
2871 /* disable via firewire interface */
2872 u8 write_enable;
2873 u8 disable;
2874
2875 /* disable must be done via function #0 */
2876 if (PCI_FUNC(dev->devfn))
2877 return;
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002878 /*
Andy Lutomirski812089e2012-12-01 12:37:20 -08002879 * RICOH 0xe822 and 0xe823 SD/MMC card readers fail to recognize
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002880 * certain types of SD/MMC cards. Lowering the SD base
2881 * clock frequency from 200Mhz to 50Mhz fixes this issue.
2882 *
2883 * 0x150 - SD2.0 mode enable for changing base clock
2884 * frequency to 50Mhz
2885 * 0xe1 - Base clock frequency
2886 * 0x32 - 50Mhz new clock frequency
2887 * 0xf9 - Key register for 0x150
2888 * 0xfc - key register for 0xe1
2889 */
Andy Lutomirski812089e2012-12-01 12:37:20 -08002890 if (dev->device == PCI_DEVICE_ID_RICOH_R5CE822 ||
2891 dev->device == PCI_DEVICE_ID_RICOH_R5CE823) {
Manoj Iyer15bed0f2011-07-11 16:28:35 -05002892 pci_write_config_byte(dev, 0xf9, 0xfc);
2893 pci_write_config_byte(dev, 0x150, 0x10);
2894 pci_write_config_byte(dev, 0xf9, 0x00);
2895 pci_write_config_byte(dev, 0xfc, 0x01);
2896 pci_write_config_byte(dev, 0xe1, 0x32);
2897 pci_write_config_byte(dev, 0xfc, 0x00);
2898
2899 dev_notice(&dev->dev, "MMC controller base frequency changed to 50Mhz.\n");
2900 }
Josh Boyer3e309cd2011-10-05 11:44:50 -04002901
2902 pci_read_config_byte(dev, 0xCB, &disable);
2903
2904 if (disable & 0x02)
2905 return;
2906
2907 pci_read_config_byte(dev, 0xCA, &write_enable);
2908 pci_write_config_byte(dev, 0xCA, 0x57);
2909 pci_write_config_byte(dev, 0xCB, disable | 0x02);
2910 pci_write_config_byte(dev, 0xCA, write_enable);
2911
2912 dev_notice(&dev->dev, "proprietary Ricoh MMC controller disabled (via firewire function)\n");
2913 dev_notice(&dev->dev, "MMC cards are now supported by standard SDHCI controller\n");
2914
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002915}
2916DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
2917DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5C832, ricoh_mmc_fixup_r5c832);
Andy Lutomirski812089e2012-12-01 12:37:20 -08002918DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
2919DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE822, ricoh_mmc_fixup_r5c832);
Manoj Iyerbe98ca62011-05-26 11:19:05 -05002920DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
2921DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_RICOH, PCI_DEVICE_ID_RICOH_R5CE823, ricoh_mmc_fixup_r5c832);
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002922#endif /*CONFIG_MMC_RICOH_MMC*/
2923
Suresh Siddhad3f13812011-08-23 17:05:25 -07002924#ifdef CONFIG_DMAR_TABLE
Suresh Siddha254e42002010-12-06 12:26:30 -08002925#define VTUNCERRMSK_REG 0x1ac
2926#define VTD_MSK_SPEC_ERRORS (1 << 31)
2927/*
2928 * This is a quirk for masking vt-d spec defined errors to platform error
2929 * handling logic. With out this, platforms using Intel 7500, 5500 chipsets
2930 * (and the derivative chipsets like X58 etc) seem to generate NMI/SMI (based
2931 * on the RAS config settings of the platform) when a vt-d fault happens.
2932 * The resulting SMI caused the system to hang.
2933 *
2934 * VT-d spec related errors are already handled by the VT-d OS code, so no
2935 * need to report the same error through other channels.
2936 */
2937static void vtd_mask_spec_errors(struct pci_dev *dev)
2938{
2939 u32 word;
2940
2941 pci_read_config_dword(dev, VTUNCERRMSK_REG, &word);
2942 pci_write_config_dword(dev, VTUNCERRMSK_REG, word | VTD_MSK_SPEC_ERRORS);
2943}
2944DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x342e, vtd_mask_spec_errors);
2945DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x3c28, vtd_mask_spec_errors);
2946#endif
Maxim Levitsky03cd8f72010-03-05 13:43:20 -08002947
Bill Pemberton15856ad2012-11-21 15:35:00 -05002948static void fixup_ti816x_class(struct pci_dev *dev)
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302949{
Bjorn Helgaasd1541dc2015-06-19 15:58:24 -05002950 u32 class = dev->class;
2951
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302952 /* TI 816x devices do not have class code set when in PCIe boot mode */
Bjorn Helgaasd1541dc2015-06-19 15:58:24 -05002953 dev->class = PCI_CLASS_MULTIMEDIA_VIDEO << 8;
2954 dev_info(&dev->dev, "PCI class overridden (%#08x -> %#08x)\n",
2955 class, dev->class);
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302956}
Yinghai Lu40c96232012-02-23 23:46:58 -08002957DECLARE_PCI_FIXUP_CLASS_EARLY(PCI_VENDOR_ID_TI, 0xb800,
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05002958 PCI_CLASS_NOT_DEFINED, 8, fixup_ti816x_class);
Hemant Pedanekar63c44082011-04-05 12:32:50 +05302959
Ben Hutchingsa94d0722011-10-05 22:35:03 +01002960/* Some PCIe devices do not work reliably with the claimed maximum
2961 * payload size supported.
2962 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002963static void fixup_mpss_256(struct pci_dev *dev)
Ben Hutchingsa94d0722011-10-05 22:35:03 +01002964{
2965 dev->pcie_mpss = 1; /* 256 bytes */
2966}
2967DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2968 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_0, fixup_mpss_256);
2969DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2970 PCI_DEVICE_ID_SOLARFLARE_SFC4000A_1, fixup_mpss_256);
2971DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_SOLARFLARE,
2972 PCI_DEVICE_ID_SOLARFLARE_SFC4000B, fixup_mpss_256);
2973
Jon Masond387a8d2011-10-14 14:56:13 -05002974/* Intel 5000 and 5100 Memory controllers have an errata with read completion
2975 * coalescing (which is enabled by default on some BIOSes) and MPS of 256B.
2976 * Since there is no way of knowing what the PCIE MPS on each fabric will be
2977 * until all of the devices are discovered and buses walked, read completion
2978 * coalescing must be disabled. Unfortunately, it cannot be re-enabled because
2979 * it is possible to hotplug a device with MPS of 256B.
2980 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05002981static void quirk_intel_mc_errata(struct pci_dev *dev)
Jon Masond387a8d2011-10-14 14:56:13 -05002982{
2983 int err;
2984 u16 rcc;
2985
Keith Busch27d868b2015-08-24 08:48:16 -05002986 if (pcie_bus_config == PCIE_BUS_TUNE_OFF ||
2987 pcie_bus_config == PCIE_BUS_DEFAULT)
Jon Masond387a8d2011-10-14 14:56:13 -05002988 return;
2989
2990 /* Intel errata specifies bits to change but does not say what they are.
2991 * Keeping them magical until such time as the registers and values can
2992 * be explained.
2993 */
2994 err = pci_read_config_word(dev, 0x48, &rcc);
2995 if (err) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04002996 dev_err(&dev->dev, "Error attempting to read the read completion coalescing register\n");
Jon Masond387a8d2011-10-14 14:56:13 -05002997 return;
2998 }
2999
3000 if (!(rcc & (1 << 10)))
3001 return;
3002
3003 rcc &= ~(1 << 10);
3004
3005 err = pci_write_config_word(dev, 0x48, rcc);
3006 if (err) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04003007 dev_err(&dev->dev, "Error attempting to write the read completion coalescing register\n");
Jon Masond387a8d2011-10-14 14:56:13 -05003008 return;
3009 }
3010
Ryan Desfosses227f0642014-04-18 20:13:50 -04003011 pr_info_once("Read completion coalescing disabled due to hardware errata relating to 256B MPS\n");
Jon Masond387a8d2011-10-14 14:56:13 -05003012}
3013/* Intel 5000 series memory controllers and ports 2-7 */
3014DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25c0, quirk_intel_mc_errata);
3015DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d0, quirk_intel_mc_errata);
3016DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d4, quirk_intel_mc_errata);
3017DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25d8, quirk_intel_mc_errata);
3018DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e2, quirk_intel_mc_errata);
3019DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e3, quirk_intel_mc_errata);
3020DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e4, quirk_intel_mc_errata);
3021DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e5, quirk_intel_mc_errata);
3022DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e6, quirk_intel_mc_errata);
3023DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25e7, quirk_intel_mc_errata);
3024DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f7, quirk_intel_mc_errata);
3025DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f8, quirk_intel_mc_errata);
3026DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25f9, quirk_intel_mc_errata);
3027DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x25fa, quirk_intel_mc_errata);
3028/* Intel 5100 series memory controllers and ports 2-7 */
3029DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65c0, quirk_intel_mc_errata);
3030DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e2, quirk_intel_mc_errata);
3031DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e3, quirk_intel_mc_errata);
3032DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e4, quirk_intel_mc_errata);
3033DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e5, quirk_intel_mc_errata);
3034DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e6, quirk_intel_mc_errata);
3035DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65e7, quirk_intel_mc_errata);
3036DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f7, quirk_intel_mc_errata);
3037DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f8, quirk_intel_mc_errata);
3038DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65f9, quirk_intel_mc_errata);
3039DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x65fa, quirk_intel_mc_errata);
3040
Arjan van de Ven32098742012-01-30 20:52:07 -08003041
Jon Mason12b03182013-05-06 08:03:33 +00003042/*
3043 * Ivytown NTB BAR sizes are misreported by the hardware due to an erratum. To
3044 * work around this, query the size it should be configured to by the device and
3045 * modify the resource end to correspond to this new size.
3046 */
3047static void quirk_intel_ntb(struct pci_dev *dev)
3048{
3049 int rc;
3050 u8 val;
3051
3052 rc = pci_read_config_byte(dev, 0x00D0, &val);
3053 if (rc)
3054 return;
3055
3056 dev->resource[2].end = dev->resource[2].start + ((u64) 1 << val) - 1;
3057
3058 rc = pci_read_config_byte(dev, 0x00D1, &val);
3059 if (rc)
3060 return;
3061
3062 dev->resource[4].end = dev->resource[4].start + ((u64) 1 << val) - 1;
3063}
3064DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e08, quirk_intel_ntb);
3065DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x0e0d, quirk_intel_ntb);
3066
Myron Stowe2729d5b2012-07-09 15:36:02 -06003067static ktime_t fixup_debug_start(struct pci_dev *dev,
3068 void (*fn)(struct pci_dev *dev))
Arjan van de Ven32098742012-01-30 20:52:07 -08003069{
Myron Stowe2729d5b2012-07-09 15:36:02 -06003070 ktime_t calltime = ktime_set(0, 0);
3071
3072 dev_dbg(&dev->dev, "calling %pF\n", fn);
3073 if (initcall_debug) {
3074 pr_debug("calling %pF @ %i for %s\n",
3075 fn, task_pid_nr(current), dev_name(&dev->dev));
3076 calltime = ktime_get();
3077 }
3078
3079 return calltime;
3080}
3081
3082static void fixup_debug_report(struct pci_dev *dev, ktime_t calltime,
3083 void (*fn)(struct pci_dev *dev))
3084{
3085 ktime_t delta, rettime;
Arjan van de Ven32098742012-01-30 20:52:07 -08003086 unsigned long long duration;
3087
Myron Stowe2729d5b2012-07-09 15:36:02 -06003088 if (initcall_debug) {
3089 rettime = ktime_get();
3090 delta = ktime_sub(rettime, calltime);
3091 duration = (unsigned long long) ktime_to_ns(delta) >> 10;
3092 pr_debug("pci fixup %pF returned after %lld usecs for %s\n",
3093 fn, duration, dev_name(&dev->dev));
3094 }
Arjan van de Ven32098742012-01-30 20:52:07 -08003095}
3096
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003097/*
3098 * Some BIOS implementations leave the Intel GPU interrupts enabled,
3099 * even though no one is handling them (f.e. i915 driver is never loaded).
3100 * Additionally the interrupt destination is not set up properly
3101 * and the interrupt ends up -somewhere-.
3102 *
3103 * These spurious interrupts are "sticky" and the kernel disables
3104 * the (shared) interrupt line after 100.000+ generated interrupts.
3105 *
3106 * Fix it by disabling the still enabled interrupts.
3107 * This resolves crashes often seen on monitor unplug.
3108 */
3109#define I915_DEIER_REG 0x4400c
Bill Pemberton15856ad2012-11-21 15:35:00 -05003110static void disable_igfx_irq(struct pci_dev *dev)
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003111{
3112 void __iomem *regs = pci_iomap(dev, 0, 0);
3113 if (regs == NULL) {
3114 dev_warn(&dev->dev, "igfx quirk: Can't iomap PCI device\n");
3115 return;
3116 }
3117
3118 /* Check if any interrupt line is still enabled */
3119 if (readl(regs + I915_DEIER_REG) != 0) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04003120 dev_warn(&dev->dev, "BIOS left Intel GPU interrupts enabled; disabling\n");
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003121
3122 writel(0, regs + I915_DEIER_REG);
3123 }
3124
3125 pci_iounmap(dev, regs);
3126}
Bin Meng0a38f3a2018-09-26 08:14:01 -07003127DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0042, disable_igfx_irq);
3128DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0046, disable_igfx_irq);
3129DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x004a, disable_igfx_irq);
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003130DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0102, disable_igfx_irq);
Bin Meng0a38f3a2018-09-26 08:14:01 -07003131DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0106, disable_igfx_irq);
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003132DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x010a, disable_igfx_irq);
Thomas Jarosch7c821262014-04-07 15:10:32 +02003133DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0152, disable_igfx_irq);
Thomas Jaroschf67fd552011-12-07 22:08:11 +01003134
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003135/*
Todd E Brandtb8cac702013-09-10 16:10:43 -07003136 * PCI devices which are on Intel chips can skip the 10ms delay
3137 * before entering D3 mode.
3138 */
3139static void quirk_remove_d3_delay(struct pci_dev *dev)
3140{
3141 dev->d3_delay = 0;
3142}
Andy Shevchenko5feac342017-04-04 19:32:34 +00003143/* C600 Series devices do not need 10ms d3_delay */
Todd E Brandtb8cac702013-09-10 16:10:43 -07003144DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0412, quirk_remove_d3_delay);
Andy Shevchenko5feac342017-04-04 19:32:34 +00003145DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c00, quirk_remove_d3_delay);
Todd E Brandtb8cac702013-09-10 16:10:43 -07003146DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x0c0c, quirk_remove_d3_delay);
Andy Shevchenko5feac342017-04-04 19:32:34 +00003147/* Lynxpoint-H PCH devices do not need 10ms d3_delay */
3148DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c02, quirk_remove_d3_delay);
3149DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c18, quirk_remove_d3_delay);
3150DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c1c, quirk_remove_d3_delay);
3151DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c20, quirk_remove_d3_delay);
3152DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c22, quirk_remove_d3_delay);
3153DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c26, quirk_remove_d3_delay);
3154DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c2d, quirk_remove_d3_delay);
Todd E Brandtb8cac702013-09-10 16:10:43 -07003155DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c31, quirk_remove_d3_delay);
3156DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3a, quirk_remove_d3_delay);
3157DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c3d, quirk_remove_d3_delay);
Todd E Brandtb8cac702013-09-10 16:10:43 -07003158DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x8c4e, quirk_remove_d3_delay);
Srinidhi Kasagar4a118752015-06-19 11:52:46 +05303159/* Intel Cherrytrail devices do not need 10ms d3_delay */
3160DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2280, quirk_remove_d3_delay);
Andy Shevchenko5feac342017-04-04 19:32:34 +00003161DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x2298, quirk_remove_d3_delay);
3162DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x229c, quirk_remove_d3_delay);
Srinidhi Kasagar4a118752015-06-19 11:52:46 +05303163DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b0, quirk_remove_d3_delay);
Andy Shevchenko5feac342017-04-04 19:32:34 +00003164DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b5, quirk_remove_d3_delay);
3165DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b7, quirk_remove_d3_delay);
Srinidhi Kasagar4a118752015-06-19 11:52:46 +05303166DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22b8, quirk_remove_d3_delay);
3167DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22d8, quirk_remove_d3_delay);
3168DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x22dc, quirk_remove_d3_delay);
Noa Osheroviche28229042016-11-15 09:59:59 +02003169
Todd E Brandtb8cac702013-09-10 16:10:43 -07003170/*
Noa Osheroviche28229042016-11-15 09:59:59 +02003171 * Some devices may pass our check in pci_intx_mask_supported() if
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003172 * PCI_COMMAND_INTX_DISABLE works though they actually do not properly
3173 * support this feature.
3174 */
Bill Pemberton15856ad2012-11-21 15:35:00 -05003175static void quirk_broken_intx_masking(struct pci_dev *dev)
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003176{
3177 dev->broken_intx_masking = 1;
3178}
Noa Osherovich89066152016-11-15 09:59:58 +02003179DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, 0x0030,
3180 quirk_broken_intx_masking);
3181DECLARE_PCI_FIXUP_FINAL(0x1814, 0x0601, /* Ralink RT2800 802.11n PCI */
3182 quirk_broken_intx_masking);
Noa Osheroviche28229042016-11-15 09:59:59 +02003183
Alex Williamson3cb30b72014-05-01 14:36:31 -06003184/*
3185 * Realtek RTL8169 PCI Gigabit Ethernet Controller (rev 10)
3186 * Subsystem: Realtek RTL8169/8110 Family PCI Gigabit Ethernet NIC
3187 *
3188 * RTL8110SC - Fails under PCI device assignment using DisINTx masking.
3189 */
Noa Osherovich89066152016-11-15 09:59:58 +02003190DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_REALTEK, 0x8169,
3191 quirk_broken_intx_masking);
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003192
Alex Williamson8bcf4522016-03-24 13:03:49 -06003193/*
3194 * Intel i40e (XL710/X710) 10/20/40GbE NICs all have broken INTx masking,
3195 * DisINTx can be set but the interrupt status bit is non-functional.
3196 */
Noa Osherovich89066152016-11-15 09:59:58 +02003197DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1572,
3198 quirk_broken_intx_masking);
3199DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1574,
3200 quirk_broken_intx_masking);
3201DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1580,
3202 quirk_broken_intx_masking);
3203DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1581,
3204 quirk_broken_intx_masking);
3205DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1583,
3206 quirk_broken_intx_masking);
3207DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1584,
3208 quirk_broken_intx_masking);
3209DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1585,
3210 quirk_broken_intx_masking);
3211DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1586,
3212 quirk_broken_intx_masking);
3213DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1587,
3214 quirk_broken_intx_masking);
3215DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1588,
3216 quirk_broken_intx_masking);
3217DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x1589,
3218 quirk_broken_intx_masking);
3219DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d0,
3220 quirk_broken_intx_masking);
3221DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d1,
3222 quirk_broken_intx_masking);
3223DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, 0x37d2,
3224 quirk_broken_intx_masking);
Alex Williamson8bcf4522016-03-24 13:03:49 -06003225
Noa Osheroviche28229042016-11-15 09:59:59 +02003226static u16 mellanox_broken_intx_devs[] = {
3227 PCI_DEVICE_ID_MELLANOX_HERMON_SDR,
3228 PCI_DEVICE_ID_MELLANOX_HERMON_DDR,
3229 PCI_DEVICE_ID_MELLANOX_HERMON_QDR,
3230 PCI_DEVICE_ID_MELLANOX_HERMON_DDR_GEN2,
3231 PCI_DEVICE_ID_MELLANOX_HERMON_QDR_GEN2,
3232 PCI_DEVICE_ID_MELLANOX_HERMON_EN,
3233 PCI_DEVICE_ID_MELLANOX_HERMON_EN_GEN2,
3234 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN,
3235 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_T_GEN2,
3236 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_GEN2,
3237 PCI_DEVICE_ID_MELLANOX_CONNECTX_EN_5_GEN2,
3238 PCI_DEVICE_ID_MELLANOX_CONNECTX2,
3239 PCI_DEVICE_ID_MELLANOX_CONNECTX3,
3240 PCI_DEVICE_ID_MELLANOX_CONNECTX3_PRO,
Noa Osheroviche28229042016-11-15 09:59:59 +02003241};
3242
Noa Osherovichc444cc32016-11-15 10:00:00 +02003243#define CONNECTX_4_CURR_MAX_MINOR 99
3244#define CONNECTX_4_INTX_SUPPORT_MINOR 14
3245
3246/*
3247 * Check ConnectX-4/LX FW version to see if it supports legacy interrupts.
3248 * If so, don't mark it as broken.
3249 * FW minor > 99 means older FW version format and no INTx masking support.
3250 * FW minor < 14 means new FW version format and no INTx masking support.
3251 */
Noa Osheroviche28229042016-11-15 09:59:59 +02003252static void mellanox_check_broken_intx_masking(struct pci_dev *pdev)
3253{
Noa Osherovichc444cc32016-11-15 10:00:00 +02003254 __be32 __iomem *fw_ver;
3255 u16 fw_major;
3256 u16 fw_minor;
3257 u16 fw_subminor;
3258 u32 fw_maj_min;
3259 u32 fw_sub_min;
Noa Osheroviche28229042016-11-15 09:59:59 +02003260 int i;
3261
3262 for (i = 0; i < ARRAY_SIZE(mellanox_broken_intx_devs); i++) {
3263 if (pdev->device == mellanox_broken_intx_devs[i]) {
3264 pdev->broken_intx_masking = 1;
3265 return;
3266 }
3267 }
Noa Osherovichc444cc32016-11-15 10:00:00 +02003268
3269 /* Getting here means Connect-IB cards and up. Connect-IB has no INTx
3270 * support so shouldn't be checked further
3271 */
3272 if (pdev->device == PCI_DEVICE_ID_MELLANOX_CONNECTIB)
3273 return;
3274
3275 if (pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4 &&
3276 pdev->device != PCI_DEVICE_ID_MELLANOX_CONNECTX4_LX)
3277 return;
3278
3279 /* For ConnectX-4 and ConnectX-4LX, need to check FW support */
3280 if (pci_enable_device_mem(pdev)) {
3281 dev_warn(&pdev->dev, "Can't enable device memory\n");
3282 return;
3283 }
3284
3285 fw_ver = ioremap(pci_resource_start(pdev, 0), 4);
3286 if (!fw_ver) {
3287 dev_warn(&pdev->dev, "Can't map ConnectX-4 initialization segment\n");
3288 goto out;
3289 }
3290
3291 /* Reading from resource space should be 32b aligned */
3292 fw_maj_min = ioread32be(fw_ver);
3293 fw_sub_min = ioread32be(fw_ver + 1);
3294 fw_major = fw_maj_min & 0xffff;
3295 fw_minor = fw_maj_min >> 16;
3296 fw_subminor = fw_sub_min & 0xffff;
3297 if (fw_minor > CONNECTX_4_CURR_MAX_MINOR ||
3298 fw_minor < CONNECTX_4_INTX_SUPPORT_MINOR) {
3299 dev_warn(&pdev->dev, "ConnectX-4: FW %u.%u.%u doesn't support INTx masking, disabling. Please upgrade FW to %d.14.1100 and up for INTx support\n",
3300 fw_major, fw_minor, fw_subminor, pdev->device ==
3301 PCI_DEVICE_ID_MELLANOX_CONNECTX4 ? 12 : 14);
3302 pdev->broken_intx_masking = 1;
3303 }
3304
3305 iounmap(fw_ver);
3306
3307out:
3308 pci_disable_device(pdev);
Noa Osheroviche28229042016-11-15 09:59:59 +02003309}
3310DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MELLANOX, PCI_ANY_ID,
3311 mellanox_check_broken_intx_masking);
3312
Alex Williamsonc3e59ee2015-01-15 18:17:12 -06003313static void quirk_no_bus_reset(struct pci_dev *dev)
3314{
3315 dev->dev_flags |= PCI_DEV_FLAGS_NO_BUS_RESET;
3316}
3317
3318/*
Chris Blake9ac01082016-05-30 07:26:37 -05003319 * Some Atheros AR9xxx and QCA988x chips do not behave after a bus reset.
3320 * The device will throw a Link Down error on AER-capable systems and
3321 * regardless of AER, config space of the device is never accessible again
3322 * and typically causes the system to hang or reset when access is attempted.
Alex Williamsonc3e59ee2015-01-15 18:17:12 -06003323 * http://www.spinics.net/lists/linux-pci/msg34797.html
3324 */
3325DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0030, quirk_no_bus_reset);
Chris Blake9ac01082016-05-30 07:26:37 -05003326DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0032, quirk_no_bus_reset);
3327DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x003c, quirk_no_bus_reset);
Maik Broemme8e2e0312016-08-09 16:41:31 +02003328DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ATHEROS, 0x0033, quirk_no_bus_reset);
Alex Williamsonc3e59ee2015-01-15 18:17:12 -06003329
Alex Williamsond84f3172014-11-21 11:24:14 -07003330static void quirk_no_pm_reset(struct pci_dev *dev)
3331{
3332 /*
3333 * We can't do a bus reset on root bus devices, but an ineffective
3334 * PM reset may be better than nothing.
3335 */
3336 if (!pci_is_root_bus(dev->bus))
3337 dev->dev_flags |= PCI_DEV_FLAGS_NO_PM_RESET;
3338}
3339
3340/*
3341 * Some AMD/ATI GPUS (HD8570 - Oland) report that a D3hot->D0 transition
3342 * causes a reset (i.e., they advertise NoSoftRst-). This transition seems
3343 * to have no effect on the device: it retains the framebuffer contents and
3344 * monitor sync. Advertising this support makes other layers, like VFIO,
3345 * assume pci_reset_function() is viable for this device. Mark it as
3346 * unavailable to skip it when testing reset methods.
3347 */
3348DECLARE_PCI_FIXUP_CLASS_HEADER(PCI_VENDOR_ID_ATI, PCI_ANY_ID,
3349 PCI_CLASS_DISPLAY_VGA, 8, quirk_no_pm_reset);
3350
Lukas Wunner19bf4d42016-03-20 13:57:20 +01003351/*
3352 * Thunderbolt controllers with broken MSI hotplug signaling:
3353 * Entire 1st generation (Light Ridge, Eagle Ridge, Light Peak) and part
3354 * of the 2nd generation (Cactus Ridge 4C up to revision 1, Port Ridge).
3355 */
3356static void quirk_thunderbolt_hotplug_msi(struct pci_dev *pdev)
3357{
3358 if (pdev->is_hotplug_bridge &&
3359 (pdev->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C ||
3360 pdev->revision <= 1))
3361 pdev->no_msi = 1;
3362}
3363DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
3364 quirk_thunderbolt_hotplug_msi);
3365DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EAGLE_RIDGE,
3366 quirk_thunderbolt_hotplug_msi);
3367DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LIGHT_PEAK,
3368 quirk_thunderbolt_hotplug_msi);
3369DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
3370 quirk_thunderbolt_hotplug_msi);
3371DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PORT_RIDGE,
3372 quirk_thunderbolt_hotplug_msi);
3373
Alexey Kardashevskiy1aaa7772016-10-24 18:04:17 +11003374static void quirk_chelsio_extend_vpd(struct pci_dev *dev)
3375{
Casey Leedomc529ff42018-02-15 20:03:18 +05303376 int chip = (dev->device & 0xf000) >> 12;
3377 int func = (dev->device & 0x0f00) >> 8;
3378 int prod = (dev->device & 0x00ff) >> 0;
3379
3380 /*
3381 * If this is a T3-based adapter, there's a 1KB VPD area at offset
3382 * 0xc00 which contains the preferred VPD values. If this is a T4 or
3383 * later based adapter, the special VPD is at offset 0x400 for the
3384 * Physical Functions (the SR-IOV Virtual Functions have no VPD
3385 * Capabilities). The PCI VPD Access core routines will normally
3386 * compute the size of the VPD by parsing the VPD Data Structure at
3387 * offset 0x000. This will result in silent failures when attempting
3388 * to accesses these other VPD areas which are beyond those computed
3389 * limits.
3390 */
3391 if (chip == 0x0 && prod >= 0x20)
3392 pci_set_vpd_size(dev, 8192);
3393 else if (chip >= 0x4 && func < 0x8)
3394 pci_set_vpd_size(dev, 2048);
Alexey Kardashevskiy1aaa7772016-10-24 18:04:17 +11003395}
3396
Casey Leedomc529ff42018-02-15 20:03:18 +05303397DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3398 quirk_chelsio_extend_vpd);
Alexey Kardashevskiy1aaa7772016-10-24 18:04:17 +11003399
Andreas Noever1df51722014-06-03 22:04:10 +02003400#ifdef CONFIG_ACPI
3401/*
3402 * Apple: Shutdown Cactus Ridge Thunderbolt controller.
3403 *
3404 * On Apple hardware the Cactus Ridge Thunderbolt controller needs to be
3405 * shutdown before suspend. Otherwise the native host interface (NHI) will not
3406 * be present after resume if a device was plugged in before suspend.
3407 *
3408 * The thunderbolt controller consists of a pcie switch with downstream
3409 * bridges leading to the NHI and to the tunnel pci bridges.
3410 *
3411 * This quirk cuts power to the whole chip. Therefore we have to apply it
3412 * during suspend_noirq of the upstream bridge.
3413 *
3414 * Power is automagically restored before resume. No action is needed.
3415 */
3416static void quirk_apple_poweroff_thunderbolt(struct pci_dev *dev)
3417{
3418 acpi_handle bridge, SXIO, SXFP, SXLV;
3419
3420 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3421 return;
3422 if (pci_pcie_type(dev) != PCI_EXP_TYPE_UPSTREAM)
3423 return;
3424 bridge = ACPI_HANDLE(&dev->dev);
3425 if (!bridge)
3426 return;
3427 /*
3428 * SXIO and SXLV are present only on machines requiring this quirk.
3429 * TB bridges in external devices might have the same device id as those
3430 * on the host, but they will not have the associated ACPI methods. This
3431 * implicitly checks that we are at the right bridge.
3432 */
3433 if (ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXIO", &SXIO))
3434 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXFP", &SXFP))
3435 || ACPI_FAILURE(acpi_get_handle(bridge, "DSB0.NHI0.SXLV", &SXLV)))
3436 return;
3437 dev_info(&dev->dev, "quirk: cutting power to thunderbolt controller...\n");
3438
3439 /* magic sequence */
3440 acpi_execute_simple_method(SXIO, NULL, 1);
3441 acpi_execute_simple_method(SXFP, NULL, 0);
3442 msleep(300);
3443 acpi_execute_simple_method(SXLV, NULL, 0);
3444 acpi_execute_simple_method(SXIO, NULL, 0);
3445 acpi_execute_simple_method(SXLV, NULL, 0);
3446}
Lukas Wunner1d111402016-03-20 13:57:20 +01003447DECLARE_PCI_FIXUP_SUSPEND_LATE(PCI_VENDOR_ID_INTEL,
3448 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
Andreas Noever1df51722014-06-03 22:04:10 +02003449 quirk_apple_poweroff_thunderbolt);
3450
3451/*
3452 * Apple: Wait for the thunderbolt controller to reestablish pci tunnels.
3453 *
3454 * During suspend the thunderbolt controller is reset and all pci
3455 * tunnels are lost. The NHI driver will try to reestablish all tunnels
3456 * during resume. We have to manually wait for the NHI since there is
3457 * no parent child relationship between the NHI and the tunneled
3458 * bridges.
3459 */
3460static void quirk_apple_wait_for_thunderbolt(struct pci_dev *dev)
3461{
3462 struct pci_dev *sibling = NULL;
3463 struct pci_dev *nhi = NULL;
3464
3465 if (!dmi_match(DMI_BOARD_VENDOR, "Apple Inc."))
3466 return;
3467 if (pci_pcie_type(dev) != PCI_EXP_TYPE_DOWNSTREAM)
3468 return;
3469 /*
3470 * Find the NHI and confirm that we are a bridge on the tb host
3471 * controller and not on a tb endpoint.
3472 */
3473 sibling = pci_get_slot(dev->bus, 0x0);
3474 if (sibling == dev)
3475 goto out; /* we are the downstream bridge to the NHI */
3476 if (!sibling || !sibling->subordinate)
3477 goto out;
3478 nhi = pci_get_slot(sibling->subordinate, 0x0);
3479 if (!nhi)
3480 goto out;
3481 if (nhi->vendor != PCI_VENDOR_ID_INTEL
Lukas Wunner19bf4d42016-03-20 13:57:20 +01003482 || (nhi->device != PCI_DEVICE_ID_INTEL_LIGHT_RIDGE &&
3483 nhi->device != PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C &&
Xavier Gnata82a6a812016-07-26 18:40:38 +02003484 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI &&
Lukas Wunner1d111402016-03-20 13:57:20 +01003485 nhi->device != PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI)
Andreas Noever25eb7e52016-07-26 18:40:37 +02003486 || nhi->class != PCI_CLASS_SYSTEM_OTHER << 8)
Andreas Noever1df51722014-06-03 22:04:10 +02003487 goto out;
Darrick J. Wongc89ac442015-03-31 19:38:38 -07003488 dev_info(&dev->dev, "quirk: waiting for thunderbolt to reestablish PCI tunnels...\n");
Andreas Noever1df51722014-06-03 22:04:10 +02003489 device_pm_wait_for_dev(&dev->dev, &nhi->dev);
3490out:
3491 pci_dev_put(nhi);
3492 pci_dev_put(sibling);
3493}
Lukas Wunner1d111402016-03-20 13:57:20 +01003494DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
Lukas Wunner19bf4d42016-03-20 13:57:20 +01003495 PCI_DEVICE_ID_INTEL_LIGHT_RIDGE,
Andreas Noever1df51722014-06-03 22:04:10 +02003496 quirk_apple_wait_for_thunderbolt);
Lukas Wunner19bf4d42016-03-20 13:57:20 +01003497DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
Lukas Wunner1d111402016-03-20 13:57:20 +01003498 PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C,
Andreas Noever1df51722014-06-03 22:04:10 +02003499 quirk_apple_wait_for_thunderbolt);
Lukas Wunner1d111402016-03-20 13:57:20 +01003500DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
Xavier Gnata82a6a812016-07-26 18:40:38 +02003501 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_BRIDGE,
3502 quirk_apple_wait_for_thunderbolt);
3503DECLARE_PCI_FIXUP_RESUME_EARLY(PCI_VENDOR_ID_INTEL,
Lukas Wunner1d111402016-03-20 13:57:20 +01003504 PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_BRIDGE,
Andreas Noever1df51722014-06-03 22:04:10 +02003505 quirk_apple_wait_for_thunderbolt);
3506#endif
3507
Jesse Barnesbfb0f332008-10-27 17:50:21 -07003508static void pci_do_fixups(struct pci_dev *dev, struct pci_fixup *f,
3509 struct pci_fixup *end)
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003510{
Myron Stowe2729d5b2012-07-09 15:36:02 -06003511 ktime_t calltime;
3512
Yinghai Luf4ca5c62012-02-23 23:46:49 -08003513 for (; f < end; f++)
3514 if ((f->class == (u32) (dev->class >> f->class_shift) ||
3515 f->class == (u32) PCI_ANY_ID) &&
3516 (f->vendor == dev->vendor ||
3517 f->vendor == (u16) PCI_ANY_ID) &&
3518 (f->device == dev->device ||
3519 f->device == (u16) PCI_ANY_ID)) {
Myron Stowe2729d5b2012-07-09 15:36:02 -06003520 calltime = fixup_debug_start(dev, f->hook);
3521 f->hook(dev);
3522 fixup_debug_report(dev, calltime, f->hook);
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003523 }
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003524}
3525
3526extern struct pci_fixup __start_pci_fixups_early[];
3527extern struct pci_fixup __end_pci_fixups_early[];
3528extern struct pci_fixup __start_pci_fixups_header[];
3529extern struct pci_fixup __end_pci_fixups_header[];
3530extern struct pci_fixup __start_pci_fixups_final[];
3531extern struct pci_fixup __end_pci_fixups_final[];
3532extern struct pci_fixup __start_pci_fixups_enable[];
3533extern struct pci_fixup __end_pci_fixups_enable[];
3534extern struct pci_fixup __start_pci_fixups_resume[];
3535extern struct pci_fixup __end_pci_fixups_resume[];
3536extern struct pci_fixup __start_pci_fixups_resume_early[];
3537extern struct pci_fixup __end_pci_fixups_resume_early[];
3538extern struct pci_fixup __start_pci_fixups_suspend[];
3539extern struct pci_fixup __end_pci_fixups_suspend[];
Andreas Noever7d2a01b2014-06-03 22:04:09 +02003540extern struct pci_fixup __start_pci_fixups_suspend_late[];
3541extern struct pci_fixup __end_pci_fixups_suspend_late[];
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003542
Myron Stowe95df8b82012-07-13 14:29:00 -06003543static bool pci_apply_fixup_final_quirks;
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003544
3545void pci_fixup_device(enum pci_fixup_pass pass, struct pci_dev *dev)
3546{
3547 struct pci_fixup *start, *end;
3548
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003549 switch (pass) {
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003550 case pci_fixup_early:
3551 start = __start_pci_fixups_early;
3552 end = __end_pci_fixups_early;
3553 break;
3554
3555 case pci_fixup_header:
3556 start = __start_pci_fixups_header;
3557 end = __end_pci_fixups_header;
3558 break;
3559
3560 case pci_fixup_final:
Myron Stowe95df8b82012-07-13 14:29:00 -06003561 if (!pci_apply_fixup_final_quirks)
3562 return;
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003563 start = __start_pci_fixups_final;
3564 end = __end_pci_fixups_final;
3565 break;
3566
3567 case pci_fixup_enable:
3568 start = __start_pci_fixups_enable;
3569 end = __end_pci_fixups_enable;
3570 break;
3571
3572 case pci_fixup_resume:
3573 start = __start_pci_fixups_resume;
3574 end = __end_pci_fixups_resume;
3575 break;
3576
3577 case pci_fixup_resume_early:
3578 start = __start_pci_fixups_resume_early;
3579 end = __end_pci_fixups_resume_early;
3580 break;
3581
3582 case pci_fixup_suspend:
3583 start = __start_pci_fixups_suspend;
3584 end = __end_pci_fixups_suspend;
3585 break;
3586
Andreas Noever7d2a01b2014-06-03 22:04:09 +02003587 case pci_fixup_suspend_late:
3588 start = __start_pci_fixups_suspend_late;
3589 end = __end_pci_fixups_suspend_late;
3590 break;
3591
Thomas Petazzoni3d137312008-08-19 10:28:24 +02003592 default:
3593 /* stupid compiler warning, you would think with an enum... */
3594 return;
3595 }
3596 pci_do_fixups(dev, start, end);
3597}
Rafael J. Wysocki93177a72010-01-02 22:57:24 +01003598EXPORT_SYMBOL(pci_fixup_device);
David Woodhouse8d86fb22009-10-12 12:48:43 +01003599
Myron Stowe735bff12012-07-09 15:36:46 -06003600
David Woodhouse00010262009-10-12 12:50:34 +01003601static int __init pci_apply_final_quirks(void)
David Woodhouse8d86fb22009-10-12 12:48:43 +01003602{
3603 struct pci_dev *dev = NULL;
Jesse Barnesac1aa472009-10-26 13:20:44 -07003604 u8 cls = 0;
3605 u8 tmp;
3606
3607 if (pci_cache_line_size)
3608 printk(KERN_DEBUG "PCI: CLS %u bytes\n",
3609 pci_cache_line_size << 2);
David Woodhouse8d86fb22009-10-12 12:48:43 +01003610
Myron Stowe95df8b82012-07-13 14:29:00 -06003611 pci_apply_fixup_final_quirks = true;
Kulikov Vasiliy4e344b12010-07-03 20:04:39 +04003612 for_each_pci_dev(dev) {
David Woodhouse8d86fb22009-10-12 12:48:43 +01003613 pci_fixup_device(pci_fixup_final, dev);
Jesse Barnesac1aa472009-10-26 13:20:44 -07003614 /*
3615 * If arch hasn't set it explicitly yet, use the CLS
3616 * value shared by all PCI devices. If there's a
3617 * mismatch, fall back to the default value.
3618 */
3619 if (!pci_cache_line_size) {
3620 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &tmp);
3621 if (!cls)
3622 cls = tmp;
3623 if (!tmp || cls == tmp)
3624 continue;
3625
Ryan Desfosses227f0642014-04-18 20:13:50 -04003626 printk(KERN_DEBUG "PCI: CLS mismatch (%u != %u), using %u bytes\n",
3627 cls << 2, tmp << 2,
Jesse Barnesac1aa472009-10-26 13:20:44 -07003628 pci_dfl_cache_line_size << 2);
3629 pci_cache_line_size = pci_dfl_cache_line_size;
3630 }
3631 }
Myron Stowe735bff12012-07-09 15:36:46 -06003632
Jesse Barnesac1aa472009-10-26 13:20:44 -07003633 if (!pci_cache_line_size) {
3634 printk(KERN_DEBUG "PCI: CLS %u bytes, default %u\n",
3635 cls << 2, pci_dfl_cache_line_size << 2);
Csaba Henk2820f332009-12-15 17:55:25 +05303636 pci_cache_line_size = cls ? cls : pci_dfl_cache_line_size;
David Woodhouse8d86fb22009-10-12 12:48:43 +01003637 }
3638
3639 return 0;
3640}
3641
David Woodhousecf6f3bf2009-10-12 12:51:22 +01003642fs_initcall_sync(pci_apply_final_quirks);
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003643
3644/*
3645 * Followings are device-specific reset methods which can be used to
3646 * reset a single function if other methods (e.g. FLR, PM D0->D3) are
3647 * not available.
3648 */
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003649static int reset_intel_82599_sfp_virtfn(struct pci_dev *dev, int probe)
3650{
Bjorn Helgaas76b57c62012-08-22 09:41:27 -06003651 /*
3652 * http://www.intel.com/content/dam/doc/datasheet/82599-10-gbe-controller-datasheet.pdf
3653 *
3654 * The 82599 supports FLR on VFs, but FLR support is reported only
3655 * in the PF DEVCAP (sec 9.3.10.4), not in the VF DEVCAP (sec 9.5).
3656 * Therefore, we can't use pcie_flr(), which checks the VF DEVCAP.
3657 */
3658
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003659 if (probe)
3660 return 0;
3661
Casey Leedom4d708ab2013-08-06 15:48:39 +05303662 if (!pci_wait_for_pending_transaction(dev))
3663 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
Bjorn Helgaas76b57c62012-08-22 09:41:27 -06003664
Bjorn Helgaas76b57c62012-08-22 09:41:27 -06003665 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3666
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003667 msleep(100);
3668
3669 return 0;
3670}
3671
Ville Syrjäläaba72dd2015-11-04 23:19:49 +02003672#define SOUTH_CHICKEN2 0xc2004
3673#define PCH_PP_STATUS 0xc7200
3674#define PCH_PP_CONTROL 0xc7204
Xudong Haodf558de2012-04-27 09:16:46 -06003675#define MSG_CTL 0x45010
3676#define NSDE_PWR_STATE 0xd0100
3677#define IGD_OPERATION_TIMEOUT 10000 /* set timeout 10 seconds */
3678
3679static int reset_ivb_igd(struct pci_dev *dev, int probe)
3680{
3681 void __iomem *mmio_base;
3682 unsigned long timeout;
3683 u32 val;
3684
3685 if (probe)
3686 return 0;
3687
3688 mmio_base = pci_iomap(dev, 0, 0);
3689 if (!mmio_base)
3690 return -ENOMEM;
3691
3692 iowrite32(0x00000002, mmio_base + MSG_CTL);
3693
3694 /*
3695 * Clobbering SOUTH_CHICKEN2 register is fine only if the next
3696 * driver loaded sets the right bits. However, this's a reset and
3697 * the bits have been set by i915 previously, so we clobber
3698 * SOUTH_CHICKEN2 register directly here.
3699 */
3700 iowrite32(0x00000005, mmio_base + SOUTH_CHICKEN2);
3701
3702 val = ioread32(mmio_base + PCH_PP_CONTROL) & 0xfffffffe;
3703 iowrite32(val, mmio_base + PCH_PP_CONTROL);
3704
3705 timeout = jiffies + msecs_to_jiffies(IGD_OPERATION_TIMEOUT);
3706 do {
3707 val = ioread32(mmio_base + PCH_PP_STATUS);
3708 if ((val & 0xb0000000) == 0)
3709 goto reset_complete;
3710 msleep(10);
3711 } while (time_before(jiffies, timeout));
3712 dev_warn(&dev->dev, "timeout during reset\n");
3713
3714reset_complete:
3715 iowrite32(0x00000002, mmio_base + NSDE_PWR_STATE);
3716
3717 pci_iounmap(dev, mmio_base);
3718 return 0;
3719}
3720
Casey Leedom2c6217e2013-08-06 15:48:37 +05303721/*
3722 * Device-specific reset method for Chelsio T4-based adapters.
3723 */
3724static int reset_chelsio_generic_dev(struct pci_dev *dev, int probe)
3725{
3726 u16 old_command;
3727 u16 msix_flags;
3728
3729 /*
3730 * If this isn't a Chelsio T4-based device, return -ENOTTY indicating
3731 * that we have no device-specific reset method.
3732 */
3733 if ((dev->device & 0xf000) != 0x4000)
3734 return -ENOTTY;
3735
3736 /*
3737 * If this is the "probe" phase, return 0 indicating that we can
3738 * reset this device.
3739 */
3740 if (probe)
3741 return 0;
3742
3743 /*
3744 * T4 can wedge if there are DMAs in flight within the chip and Bus
3745 * Master has been disabled. We need to have it on till the Function
3746 * Level Reset completes. (BUS_MASTER is disabled in
3747 * pci_reset_function()).
3748 */
3749 pci_read_config_word(dev, PCI_COMMAND, &old_command);
3750 pci_write_config_word(dev, PCI_COMMAND,
3751 old_command | PCI_COMMAND_MASTER);
3752
3753 /*
3754 * Perform the actual device function reset, saving and restoring
3755 * configuration information around the reset.
3756 */
3757 pci_save_state(dev);
3758
3759 /*
3760 * T4 also suffers a Head-Of-Line blocking problem if MSI-X interrupts
3761 * are disabled when an MSI-X interrupt message needs to be delivered.
3762 * So we briefly re-enable MSI-X interrupts for the duration of the
3763 * FLR. The pci_restore_state() below will restore the original
3764 * MSI-X state.
3765 */
3766 pci_read_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS, &msix_flags);
3767 if ((msix_flags & PCI_MSIX_FLAGS_ENABLE) == 0)
3768 pci_write_config_word(dev, dev->msix_cap+PCI_MSIX_FLAGS,
3769 msix_flags |
3770 PCI_MSIX_FLAGS_ENABLE |
3771 PCI_MSIX_FLAGS_MASKALL);
3772
3773 /*
3774 * Start of pcie_flr() code sequence. This reset code is a copy of
3775 * the guts of pcie_flr() because that's not an exported function.
3776 */
3777
3778 if (!pci_wait_for_pending_transaction(dev))
3779 dev_err(&dev->dev, "transaction is not cleared; proceeding with reset anyway\n");
3780
3781 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
3782 msleep(100);
3783
3784 /*
3785 * End of pcie_flr() code sequence.
3786 */
3787
3788 /*
3789 * Restore the configuration information (BAR values, etc.) including
3790 * the original PCI Configuration Space Command word, and return
3791 * success.
3792 */
3793 pci_restore_state(dev);
3794 pci_write_config_word(dev, PCI_COMMAND, old_command);
3795 return 0;
3796}
3797
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003798#define PCI_DEVICE_ID_INTEL_82599_SFP_VF 0x10ed
Xudong Haodf558de2012-04-27 09:16:46 -06003799#define PCI_DEVICE_ID_INTEL_IVB_M_VGA 0x0156
3800#define PCI_DEVICE_ID_INTEL_IVB_M2_VGA 0x0166
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003801
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003802static const struct pci_dev_reset_methods pci_dev_reset_methods[] = {
Dexuan Cuic763e7b2009-12-07 13:03:23 +08003803 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82599_SFP_VF,
3804 reset_intel_82599_sfp_virtfn },
Xudong Haodf558de2012-04-27 09:16:46 -06003805 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M_VGA,
3806 reset_ivb_igd },
3807 { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_IVB_M2_VGA,
3808 reset_ivb_igd },
Casey Leedom2c6217e2013-08-06 15:48:37 +05303809 { PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
3810 reset_chelsio_generic_dev },
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003811 { 0 }
3812};
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003813
Xudong Haodf558de2012-04-27 09:16:46 -06003814/*
3815 * These device-specific reset methods are here rather than in a driver
3816 * because when a host assigns a device to a guest VM, the host may need
3817 * to reset the device but probably doesn't have a driver for it.
3818 */
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003819int pci_dev_specific_reset(struct pci_dev *dev, int probe)
3820{
Linus Torvaldsdf9d1e82009-12-31 16:44:43 -08003821 const struct pci_dev_reset_methods *i;
Rafael J. Wysocki5b889bf2009-12-31 19:06:35 +01003822
3823 for (i = pci_dev_reset_methods; i->reset; i++) {
3824 if ((i->vendor == dev->vendor ||
3825 i->vendor == (u16)PCI_ANY_ID) &&
3826 (i->device == dev->device ||
3827 i->device == (u16)PCI_ANY_ID))
3828 return i->reset(dev, probe);
3829 }
3830
3831 return -ENOTTY;
3832}
Alex Williamson12ea6ca2012-06-11 05:26:55 +00003833
Alex Williamsonec637fb2014-05-22 17:07:49 -06003834static void quirk_dma_func0_alias(struct pci_dev *dev)
3835{
Bjorn Helgaasf0af9592016-02-24 13:43:45 -06003836 if (PCI_FUNC(dev->devfn) != 0)
3837 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 0));
Alex Williamsonec637fb2014-05-22 17:07:49 -06003838}
3839
3840/*
3841 * https://bugzilla.redhat.com/show_bug.cgi?id=605888
3842 *
3843 * Some Ricoh devices use function 0 as the PCIe requester ID for DMA.
3844 */
3845DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe832, quirk_dma_func0_alias);
3846DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_RICOH, 0xe476, quirk_dma_func0_alias);
3847
Alex Williamsoncc346a42014-05-28 14:54:00 -06003848static void quirk_dma_func1_alias(struct pci_dev *dev)
3849{
Bjorn Helgaasf0af9592016-02-24 13:43:45 -06003850 if (PCI_FUNC(dev->devfn) != 1)
3851 pci_add_dma_alias(dev, PCI_DEVFN(PCI_SLOT(dev->devfn), 1));
Alex Williamsoncc346a42014-05-28 14:54:00 -06003852}
3853
3854/*
3855 * Marvell 88SE9123 uses function 1 as the requester ID for DMA. In some
3856 * SKUs function 1 is present and is a legacy IDE controller, in other
3857 * SKUs this function is not present, making this a ghost requester.
3858 * https://bugzilla.kernel.org/show_bug.cgi?id=42679
3859 */
Sakari Ailus247de692015-05-22 00:03:38 +03003860DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9120,
3861 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003862DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9123,
3863 quirk_dma_func1_alias);
Alex Williamson9c1a1a92018-01-16 10:05:26 -07003864DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9128,
3865 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003866/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c14 */
3867DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9130,
3868 quirk_dma_func1_alias);
Andre Przywara5b86e012019-04-05 16:20:47 +01003869DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9170,
3870 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003871/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c47 + c57 */
3872DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9172,
3873 quirk_dma_func1_alias);
3874/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c59 */
3875DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x917a,
3876 quirk_dma_func1_alias);
Aaron Sierra00456b32016-05-18 09:04:19 -05003877/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c78 */
3878DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9182,
3879 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003880/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c46 */
3881DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x91a0,
3882 quirk_dma_func1_alias);
Thomas Vincent-Cross71047caf2018-02-27 20:20:36 +11003883/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c127 */
3884DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9220,
3885 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003886/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c49 */
3887DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_MARVELL_EXT, 0x9230,
3888 quirk_dma_func1_alias);
Jérôme Carreteroc2e0fb92014-06-03 15:41:56 -04003889DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0642,
3890 quirk_dma_func1_alias);
Hans de Goeded2327a25e2018-03-02 11:36:33 +01003891DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_TTI, 0x0645,
3892 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003893/* https://bugs.gentoo.org/show_bug.cgi?id=497630 */
3894DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_JMICRON,
3895 PCI_DEVICE_ID_JMICRON_JMB388_ESD,
3896 quirk_dma_func1_alias);
Tim Sander8b9b9632016-01-19 14:32:29 -06003897/* https://bugzilla.kernel.org/show_bug.cgi?id=42679#c117 */
3898DECLARE_PCI_FIXUP_HEADER(0x1c28, /* Lite-On */
3899 0x0122, /* Plextor M6E (Marvell 88SS9183)*/
3900 quirk_dma_func1_alias);
Alex Williamsoncc346a42014-05-28 14:54:00 -06003901
Alex Williamsonebdb51e2014-05-22 17:08:07 -06003902/*
Alex Williamsond3d2ab42015-01-13 11:26:50 -07003903 * Some devices DMA with the wrong devfn, not just the wrong function.
3904 * quirk_fixed_dma_alias() uses this table to create fixed aliases, where
3905 * the alias is "fixed" and independent of the device devfn.
3906 *
3907 * For example, the Adaptec 3405 is a PCIe card with an Intel 80333 I/O
3908 * processor. To software, this appears as a PCIe-to-PCI/X bridge with a
3909 * single device on the secondary bus. In reality, the single exposed
3910 * device at 0e.0 is the Address Translation Unit (ATU) of the controller
3911 * that provides a bridge to the internal bus of the I/O processor. The
3912 * controller supports private devices, which can be hidden from PCI config
3913 * space. In the case of the Adaptec 3405, a private device at 01.0
3914 * appears to be the DMA engine, which therefore needs to become a DMA
3915 * alias for the device.
3916 */
3917static const struct pci_device_id fixed_dma_alias_tbl[] = {
3918 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3919 PCI_VENDOR_ID_ADAPTEC2, 0x02bb), /* Adaptec 3405 */
3920 .driver_data = PCI_DEVFN(1, 0) },
Alex Williamsondb83f872016-07-18 08:32:45 -06003921 { PCI_DEVICE_SUB(PCI_VENDOR_ID_ADAPTEC2, 0x0285,
3922 PCI_VENDOR_ID_ADAPTEC2, 0x02bc), /* Adaptec 3805 */
3923 .driver_data = PCI_DEVFN(1, 0) },
Alex Williamsond3d2ab42015-01-13 11:26:50 -07003924 { 0 }
3925};
3926
3927static void quirk_fixed_dma_alias(struct pci_dev *dev)
3928{
3929 const struct pci_device_id *id;
3930
3931 id = pci_match_id(fixed_dma_alias_tbl, dev);
Bjorn Helgaas48c83082016-02-24 13:43:54 -06003932 if (id)
Bjorn Helgaasf0af9592016-02-24 13:43:45 -06003933 pci_add_dma_alias(dev, id->driver_data);
Alex Williamsond3d2ab42015-01-13 11:26:50 -07003934}
3935
3936DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ADAPTEC2, 0x0285, quirk_fixed_dma_alias);
3937
3938/*
Alex Williamsonebdb51e2014-05-22 17:08:07 -06003939 * A few PCIe-to-PCI bridges fail to expose a PCIe capability, resulting in
3940 * using the wrong DMA alias for the device. Some of these devices can be
3941 * used as either forward or reverse bridges, so we need to test whether the
3942 * device is operating in the correct mode. We could probably apply this
3943 * quirk to PCI_ANY_ID, but for now we'll just use known offenders. The test
3944 * is for a non-root, non-PCIe bridge where the upstream device is PCIe and
3945 * is not a PCIe-to-PCI bridge, then @pdev is actually a PCIe-to-PCI bridge.
3946 */
3947static void quirk_use_pcie_bridge_dma_alias(struct pci_dev *pdev)
3948{
3949 if (!pci_is_root_bus(pdev->bus) &&
3950 pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
3951 !pci_is_pcie(pdev) && pci_is_pcie(pdev->bus->self) &&
3952 pci_pcie_type(pdev->bus->self) != PCI_EXP_TYPE_PCI_BRIDGE)
3953 pdev->dev_flags |= PCI_DEV_FLAG_PCIE_BRIDGE_ALIAS;
3954}
3955/* ASM1083/1085, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c46 */
3956DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_ASMEDIA, 0x1080,
3957 quirk_use_pcie_bridge_dma_alias);
3958/* Tundra 8113, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c43 */
3959DECLARE_PCI_FIXUP_HEADER(0x10e3, 0x8113, quirk_use_pcie_bridge_dma_alias);
Alex Williamson98ca50d2014-06-09 12:43:25 -06003960/* ITE 8892, https://bugzilla.kernel.org/show_bug.cgi?id=73551 */
3961DECLARE_PCI_FIXUP_HEADER(0x1283, 0x8892, quirk_use_pcie_bridge_dma_alias);
Alex Williamson8ab4abb2014-07-05 15:26:52 -06003962/* Intel 82801, https://bugzilla.kernel.org/show_bug.cgi?id=44881#c49 */
3963DECLARE_PCI_FIXUP_HEADER(0x8086, 0x244e, quirk_use_pcie_bridge_dma_alias);
Alex Williamsonebdb51e2014-05-22 17:08:07 -06003964
Alex Williamson15b100d2013-06-27 16:40:00 -06003965/*
Jacek Lawrynowiczb1a928c2016-03-03 15:53:20 +01003966 * MIC x200 NTB forwards PCIe traffic using multiple alien RIDs. They have to
3967 * be added as aliases to the DMA device in order to allow buffer access
3968 * when IOMMU is enabled. Following devfns have to match RIT-LUT table
3969 * programmed in the EEPROM.
3970 */
3971static void quirk_mic_x200_dma_alias(struct pci_dev *pdev)
3972{
3973 pci_add_dma_alias(pdev, PCI_DEVFN(0x10, 0x0));
3974 pci_add_dma_alias(pdev, PCI_DEVFN(0x11, 0x0));
3975 pci_add_dma_alias(pdev, PCI_DEVFN(0x12, 0x3));
3976}
3977DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2260, quirk_mic_x200_dma_alias);
3978DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, 0x2264, quirk_mic_x200_dma_alias);
3979
3980/*
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003981 * Intersil/Techwell TW686[4589]-based video capture cards have an empty (zero)
3982 * class code. Fix it.
3983 */
3984static void quirk_tw686x_class(struct pci_dev *pdev)
3985{
3986 u32 class = pdev->class;
3987
3988 /* Use "Multimedia controller" class */
3989 pdev->class = (PCI_CLASS_MULTIMEDIA_OTHER << 8) | 0x01;
3990 dev_info(&pdev->dev, "TW686x PCI class overridden (%#08x -> %#08x)\n",
3991 class, pdev->class);
3992}
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05003993DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6864, PCI_CLASS_NOT_DEFINED, 8,
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003994 quirk_tw686x_class);
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05003995DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6865, PCI_CLASS_NOT_DEFINED, 8,
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003996 quirk_tw686x_class);
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05003997DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6868, PCI_CLASS_NOT_DEFINED, 8,
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02003998 quirk_tw686x_class);
Bjorn Helgaas2b4aed12015-06-19 16:20:58 -05003999DECLARE_PCI_FIXUP_CLASS_EARLY(0x1797, 0x6869, PCI_CLASS_NOT_DEFINED, 8,
Krzysztof =?utf-8?Q?Ha=C5=82asa?=3657ceb2015-06-19 10:00:15 +02004000 quirk_tw686x_class);
4001
4002/*
Hariprasad Shenaic56d4452015-10-18 19:55:04 +05304003 * Per PCIe r3.0, sec 2.2.9, "Completion headers must supply the same
4004 * values for the Attribute as were supplied in the header of the
4005 * corresponding Request, except as explicitly allowed when IDO is used."
4006 *
4007 * If a non-compliant device generates a completion with a different
4008 * attribute than the request, the receiver may accept it (which itself
4009 * seems non-compliant based on sec 2.3.2), or it may handle it as a
4010 * Malformed TLP or an Unexpected Completion, which will probably lead to a
4011 * device access timeout.
4012 *
4013 * If the non-compliant device generates completions with zero attributes
4014 * (instead of copying the attributes from the request), we can work around
4015 * this by disabling the "Relaxed Ordering" and "No Snoop" attributes in
4016 * upstream devices so they always generate requests with zero attributes.
4017 *
4018 * This affects other devices under the same Root Port, but since these
4019 * attributes are performance hints, there should be no functional problem.
4020 *
4021 * Note that Configuration Space accesses are never supposed to have TLP
4022 * Attributes, so we're safe waiting till after any Configuration Space
4023 * accesses to do the Root Port fixup.
4024 */
4025static void quirk_disable_root_port_attributes(struct pci_dev *pdev)
4026{
4027 struct pci_dev *root_port = pci_find_pcie_root_port(pdev);
4028
4029 if (!root_port) {
4030 dev_warn(&pdev->dev, "PCIe Completion erratum may cause device errors\n");
4031 return;
4032 }
4033
4034 dev_info(&root_port->dev, "Disabling No Snoop/Relaxed Ordering Attributes to avoid PCIe Completion erratum in %s\n",
4035 dev_name(&pdev->dev));
4036 pcie_capability_clear_and_set_word(root_port, PCI_EXP_DEVCTL,
4037 PCI_EXP_DEVCTL_RELAX_EN |
4038 PCI_EXP_DEVCTL_NOSNOOP_EN, 0);
4039}
4040
4041/*
4042 * The Chelsio T5 chip fails to copy TLP Attributes from a Request to the
4043 * Completion it generates.
4044 */
4045static void quirk_chelsio_T5_disable_root_port_attributes(struct pci_dev *pdev)
4046{
4047 /*
4048 * This mask/compare operation selects for Physical Function 4 on a
4049 * T5. We only need to fix up the Root Port once for any of the
4050 * PFs. PF[0..3] have PCI Device IDs of 0x50xx, but PF4 is uniquely
4051 * 0x54xx so we use that one,
4052 */
4053 if ((pdev->device & 0xff00) == 0x5400)
4054 quirk_disable_root_port_attributes(pdev);
4055}
4056DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_CHELSIO, PCI_ANY_ID,
4057 quirk_chelsio_T5_disable_root_port_attributes);
4058
4059/*
Alex Williamson15b100d2013-06-27 16:40:00 -06004060 * AMD has indicated that the devices below do not support peer-to-peer
4061 * in any system where they are found in the southbridge with an AMD
4062 * IOMMU in the system. Multifunction devices that do not support
4063 * peer-to-peer between functions can claim to support a subset of ACS.
4064 * Such devices effectively enable request redirect (RR) and completion
4065 * redirect (CR) since all transactions are redirected to the upstream
4066 * root complex.
4067 *
4068 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94086
4069 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/94102
4070 * http://permalink.gmane.org/gmane.comp.emulators.kvm.devel/99402
4071 *
4072 * 1002:4385 SBx00 SMBus Controller
4073 * 1002:439c SB7x0/SB8x0/SB9x0 IDE Controller
4074 * 1002:4383 SBx00 Azalia (Intel HDA)
4075 * 1002:439d SB7x0/SB8x0/SB9x0 LPC host controller
4076 * 1002:4384 SBx00 PCI to PCI Bridge
4077 * 1002:4399 SB7x0/SB8x0/SB9x0 USB OHCI2 Controller
Marti Raudsepp3587e622014-10-02 08:50:31 -06004078 *
4079 * https://bugzilla.kernel.org/show_bug.cgi?id=81841#c15
4080 *
4081 * 1022:780f [AMD] FCH PCI Bridge
4082 * 1022:7809 [AMD] FCH USB OHCI Controller
Alex Williamson15b100d2013-06-27 16:40:00 -06004083 */
4084static int pci_quirk_amd_sb_acs(struct pci_dev *dev, u16 acs_flags)
4085{
4086#ifdef CONFIG_ACPI
4087 struct acpi_table_header *header = NULL;
4088 acpi_status status;
4089
4090 /* Targeting multifunction devices on the SB (appears on root bus) */
4091 if (!dev->multifunction || !pci_is_root_bus(dev->bus))
4092 return -ENODEV;
4093
4094 /* The IVRS table describes the AMD IOMMU */
4095 status = acpi_get_table("IVRS", 0, &header);
4096 if (ACPI_FAILURE(status))
4097 return -ENODEV;
4098
4099 /* Filter out flags not applicable to multifunction */
4100 acs_flags &= (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_EC | PCI_ACS_DT);
4101
4102 return acs_flags & ~(PCI_ACS_RR | PCI_ACS_CR) ? 0 : 1;
4103#else
4104 return -ENODEV;
4105#endif
4106}
4107
Manish Jaggib404bcf2016-01-30 01:33:58 +05304108static int pci_quirk_cavium_acs(struct pci_dev *dev, u16 acs_flags)
4109{
4110 /*
Vadim Lomovtsev3194d872017-10-17 05:47:38 -07004111 * Cavium root ports don't advertise an ACS capability. However,
4112 * the RTL internally implements similar protection as if ACS had
4113 * Request Redirection, Completion Redirection, Source Validation,
4114 * and Upstream Forwarding features enabled. Assert that the
4115 * hardware implements and enables equivalent ACS functionality for
4116 * these flags.
Manish Jaggib404bcf2016-01-30 01:33:58 +05304117 */
Vadim Lomovtsev3194d872017-10-17 05:47:38 -07004118 acs_flags &= ~(PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_SV | PCI_ACS_UF);
Manish Jaggib404bcf2016-01-30 01:33:58 +05304119
Manish Jaggiaad6cca2017-03-30 18:47:14 -05004120 if (!((dev->device >= 0xa000) && (dev->device <= 0xa0ff)))
4121 return -ENOTTY;
4122
Manish Jaggib404bcf2016-01-30 01:33:58 +05304123 return acs_flags ? 0 : 1;
4124}
4125
Alex Williamsond99321b2014-02-03 14:27:46 -07004126/*
4127 * Many Intel PCH root ports do provide ACS-like features to disable peer
4128 * transactions and validate bus numbers in requests, but do not provide an
4129 * actual PCIe ACS capability. This is the list of device IDs known to fall
4130 * into that category as provided by Intel in Red Hat bugzilla 1037684.
4131 */
4132static const u16 pci_quirk_intel_pch_acs_ids[] = {
4133 /* Ibexpeak PCH */
4134 0x3b42, 0x3b43, 0x3b44, 0x3b45, 0x3b46, 0x3b47, 0x3b48, 0x3b49,
4135 0x3b4a, 0x3b4b, 0x3b4c, 0x3b4d, 0x3b4e, 0x3b4f, 0x3b50, 0x3b51,
4136 /* Cougarpoint PCH */
4137 0x1c10, 0x1c11, 0x1c12, 0x1c13, 0x1c14, 0x1c15, 0x1c16, 0x1c17,
4138 0x1c18, 0x1c19, 0x1c1a, 0x1c1b, 0x1c1c, 0x1c1d, 0x1c1e, 0x1c1f,
4139 /* Pantherpoint PCH */
4140 0x1e10, 0x1e11, 0x1e12, 0x1e13, 0x1e14, 0x1e15, 0x1e16, 0x1e17,
4141 0x1e18, 0x1e19, 0x1e1a, 0x1e1b, 0x1e1c, 0x1e1d, 0x1e1e, 0x1e1f,
4142 /* Lynxpoint-H PCH */
4143 0x8c10, 0x8c11, 0x8c12, 0x8c13, 0x8c14, 0x8c15, 0x8c16, 0x8c17,
4144 0x8c18, 0x8c19, 0x8c1a, 0x8c1b, 0x8c1c, 0x8c1d, 0x8c1e, 0x8c1f,
4145 /* Lynxpoint-LP PCH */
4146 0x9c10, 0x9c11, 0x9c12, 0x9c13, 0x9c14, 0x9c15, 0x9c16, 0x9c17,
4147 0x9c18, 0x9c19, 0x9c1a, 0x9c1b,
4148 /* Wildcat PCH */
4149 0x9c90, 0x9c91, 0x9c92, 0x9c93, 0x9c94, 0x9c95, 0x9c96, 0x9c97,
4150 0x9c98, 0x9c99, 0x9c9a, 0x9c9b,
Alex Williamson1a30fd02014-03-31 12:21:38 -06004151 /* Patsburg (X79) PCH */
4152 0x1d10, 0x1d12, 0x1d14, 0x1d16, 0x1d18, 0x1d1a, 0x1d1c, 0x1d1e,
Alex Williamson78e88352015-01-22 11:15:43 -07004153 /* Wellsburg (X99) PCH */
4154 0x8d10, 0x8d11, 0x8d12, 0x8d13, 0x8d14, 0x8d15, 0x8d16, 0x8d17,
4155 0x8d18, 0x8d19, 0x8d1a, 0x8d1b, 0x8d1c, 0x8d1d, 0x8d1e,
Alex Williamsondca230d2015-05-01 13:20:13 -06004156 /* Lynx Point (9 series) PCH */
4157 0x8c90, 0x8c92, 0x8c94, 0x8c96, 0x8c98, 0x8c9a, 0x8c9c, 0x8c9e,
Alex Williamsond99321b2014-02-03 14:27:46 -07004158};
4159
4160static bool pci_quirk_intel_pch_acs_match(struct pci_dev *dev)
4161{
4162 int i;
4163
4164 /* Filter out a few obvious non-matches first */
4165 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4166 return false;
4167
4168 for (i = 0; i < ARRAY_SIZE(pci_quirk_intel_pch_acs_ids); i++)
4169 if (pci_quirk_intel_pch_acs_ids[i] == dev->device)
4170 return true;
4171
4172 return false;
4173}
4174
4175#define INTEL_PCH_ACS_FLAGS (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV)
4176
4177static int pci_quirk_intel_pch_acs(struct pci_dev *dev, u16 acs_flags)
4178{
4179 u16 flags = dev->dev_flags & PCI_DEV_FLAGS_ACS_ENABLED_QUIRK ?
4180 INTEL_PCH_ACS_FLAGS : 0;
4181
4182 if (!pci_quirk_intel_pch_acs_match(dev))
4183 return -ENOTTY;
4184
4185 return acs_flags & ~flags ? 0 : 1;
4186}
4187
Alex Williamson1bf2bf22016-03-31 16:34:37 -06004188/*
Sinan Kayab18877f2017-04-04 19:32:34 +00004189 * These QCOM root ports do provide ACS-like features to disable peer
4190 * transactions and validate bus numbers in requests, but do not provide an
4191 * actual PCIe ACS capability. Hardware supports source validation but it
4192 * will report the issue as Completer Abort instead of ACS Violation.
4193 * Hardware doesn't support peer-to-peer and each root port is a root
4194 * complex with unique segment numbers. It is not possible for one root
4195 * port to pass traffic to another root port. All PCIe transactions are
4196 * terminated inside the root port.
4197 */
4198static int pci_quirk_qcom_rp_acs(struct pci_dev *dev, u16 acs_flags)
4199{
4200 u16 flags = (PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_SV);
4201 int ret = acs_flags & ~flags ? 0 : 1;
4202
4203 dev_info(&dev->dev, "Using QCOM ACS Quirk (%d)\n", ret);
4204
4205 return ret;
4206}
4207
4208/*
Alex Williamson1bf2bf22016-03-31 16:34:37 -06004209 * Sunrise Point PCH root ports implement ACS, but unfortunately as shown in
4210 * the datasheet (Intel 100 Series Chipset Family PCH Datasheet, Vol. 2,
4211 * 12.1.46, 12.1.47)[1] this chipset uses dwords for the ACS capability and
4212 * control registers whereas the PCIe spec packs them into words (Rev 3.0,
4213 * 7.16 ACS Extended Capability). The bit definitions are correct, but the
4214 * control register is at offset 8 instead of 6 and we should probably use
4215 * dword accesses to them. This applies to the following PCI Device IDs, as
4216 * found in volume 1 of the datasheet[2]:
4217 *
4218 * 0xa110-0xa11f Sunrise Point-H PCI Express Root Port #{0-16}
4219 * 0xa167-0xa16a Sunrise Point-H PCI Express Root Port #{17-20}
4220 *
4221 * N.B. This doesn't fix what lspci shows.
4222 *
Alex Williamsonf36d3f12017-04-04 19:32:26 +00004223 * The 100 series chipset specification update includes this as errata #23[3].
4224 *
4225 * The 200 series chipset (Union Point) has the same bug according to the
4226 * specification update (Intel 200 Series Chipset Family Platform Controller
4227 * Hub, Specification Update, January 2017, Revision 001, Document# 335194-001,
4228 * Errata 22)[4]. Per the datasheet[5], root port PCI Device IDs for this
4229 * chipset include:
4230 *
4231 * 0xa290-0xa29f PCI Express Root port #{0-16}
4232 * 0xa2e7-0xa2ee PCI Express Root port #{17-24}
4233 *
Alex Williamson5e1dead2018-04-25 14:27:37 -06004234 * Mobile chipsets are also affected, 7th & 8th Generation
4235 * Specification update confirms ACS errata 22, status no fix: (7th Generation
4236 * Intel Processor Family I/O for U/Y Platforms and 8th Generation Intel
4237 * Processor Family I/O for U Quad Core Platforms Specification Update,
4238 * August 2017, Revision 002, Document#: 334660-002)[6]
4239 * Device IDs from I/O datasheet: (7th Generation Intel Processor Family I/O
4240 * for U/Y Platforms and 8th Generation Intel ® Processor Family I/O for U
4241 * Quad Core Platforms, Vol 1 of 2, August 2017, Document#: 334658-003)[7]
4242 *
4243 * 0x9d10-0x9d1b PCI Express Root port #{1-12}
4244 *
Alex Williamson1bf2bf22016-03-31 16:34:37 -06004245 * [1] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-2.html
4246 * [2] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-datasheet-vol-1.html
Alex Williamsonf36d3f12017-04-04 19:32:26 +00004247 * [3] http://www.intel.com/content/www/us/en/chipsets/100-series-chipset-spec-update.html
4248 * [4] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-spec-update.html
4249 * [5] http://www.intel.com/content/www/us/en/chipsets/200-series-chipset-pch-datasheet-vol-1.html
Alex Williamson5e1dead2018-04-25 14:27:37 -06004250 * [6] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-spec-update.html
4251 * [7] https://www.intel.com/content/www/us/en/processors/core/7th-gen-core-family-mobile-u-y-processor-lines-i-o-datasheet-vol-1.html
Alex Williamson1bf2bf22016-03-31 16:34:37 -06004252 */
4253static bool pci_quirk_intel_spt_pch_acs_match(struct pci_dev *dev)
4254{
Alex Williamsonf36d3f12017-04-04 19:32:26 +00004255 if (!pci_is_pcie(dev) || pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
4256 return false;
4257
4258 switch (dev->device) {
4259 case 0xa110 ... 0xa11f: case 0xa167 ... 0xa16a: /* Sunrise Point */
4260 case 0xa290 ... 0xa29f: case 0xa2e7 ... 0xa2ee: /* Union Point */
Alex Williamson5e1dead2018-04-25 14:27:37 -06004261 case 0x9d10 ... 0x9d1b: /* 7th & 8th Gen Mobile */
Alex Williamsonf36d3f12017-04-04 19:32:26 +00004262 return true;
4263 }
4264
4265 return false;
Alex Williamson1bf2bf22016-03-31 16:34:37 -06004266}
4267
4268#define INTEL_SPT_ACS_CTRL (PCI_ACS_CAP + 4)
4269
4270static int pci_quirk_intel_spt_pch_acs(struct pci_dev *dev, u16 acs_flags)
4271{
4272 int pos;
4273 u32 cap, ctrl;
4274
4275 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4276 return -ENOTTY;
4277
4278 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4279 if (!pos)
4280 return -ENOTTY;
4281
4282 /* see pci_acs_flags_enabled() */
4283 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4284 acs_flags &= (cap | PCI_ACS_EC);
4285
4286 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4287
4288 return acs_flags & ~ctrl ? 0 : 1;
4289}
4290
Alex Williamson100ebb22014-09-26 17:07:59 -06004291static int pci_quirk_mf_endpoint_acs(struct pci_dev *dev, u16 acs_flags)
Alex Williamson89b51cb2014-09-17 08:59:36 -06004292{
4293 /*
4294 * SV, TB, and UF are not relevant to multifunction endpoints.
4295 *
Alex Williamson100ebb22014-09-26 17:07:59 -06004296 * Multifunction devices are only required to implement RR, CR, and DT
4297 * in their ACS capability if they support peer-to-peer transactions.
4298 * Devices matching this quirk have been verified by the vendor to not
4299 * perform peer-to-peer with other functions, allowing us to mask out
4300 * these bits as if they were unimplemented in the ACS capability.
Alex Williamson89b51cb2014-09-17 08:59:36 -06004301 */
4302 acs_flags &= ~(PCI_ACS_SV | PCI_ACS_TB | PCI_ACS_RR |
4303 PCI_ACS_CR | PCI_ACS_UF | PCI_ACS_DT);
4304
4305 return acs_flags ? 0 : 1;
4306}
4307
Alex Williamsonad805752012-06-11 05:27:07 +00004308static const struct pci_dev_acs_enabled {
4309 u16 vendor;
4310 u16 device;
4311 int (*acs_enabled)(struct pci_dev *dev, u16 acs_flags);
4312} pci_dev_acs_enabled[] = {
Alex Williamson15b100d2013-06-27 16:40:00 -06004313 { PCI_VENDOR_ID_ATI, 0x4385, pci_quirk_amd_sb_acs },
4314 { PCI_VENDOR_ID_ATI, 0x439c, pci_quirk_amd_sb_acs },
4315 { PCI_VENDOR_ID_ATI, 0x4383, pci_quirk_amd_sb_acs },
4316 { PCI_VENDOR_ID_ATI, 0x439d, pci_quirk_amd_sb_acs },
4317 { PCI_VENDOR_ID_ATI, 0x4384, pci_quirk_amd_sb_acs },
4318 { PCI_VENDOR_ID_ATI, 0x4399, pci_quirk_amd_sb_acs },
Marti Raudsepp3587e622014-10-02 08:50:31 -06004319 { PCI_VENDOR_ID_AMD, 0x780f, pci_quirk_amd_sb_acs },
4320 { PCI_VENDOR_ID_AMD, 0x7809, pci_quirk_amd_sb_acs },
Alex Williamson100ebb22014-09-26 17:07:59 -06004321 { PCI_VENDOR_ID_SOLARFLARE, 0x0903, pci_quirk_mf_endpoint_acs },
4322 { PCI_VENDOR_ID_SOLARFLARE, 0x0923, pci_quirk_mf_endpoint_acs },
Edward Cree9fad4012016-07-28 18:13:56 +01004323 { PCI_VENDOR_ID_SOLARFLARE, 0x0A03, pci_quirk_mf_endpoint_acs },
Alex Williamson100ebb22014-09-26 17:07:59 -06004324 { PCI_VENDOR_ID_INTEL, 0x10C6, pci_quirk_mf_endpoint_acs },
4325 { PCI_VENDOR_ID_INTEL, 0x10DB, pci_quirk_mf_endpoint_acs },
4326 { PCI_VENDOR_ID_INTEL, 0x10DD, pci_quirk_mf_endpoint_acs },
4327 { PCI_VENDOR_ID_INTEL, 0x10E1, pci_quirk_mf_endpoint_acs },
4328 { PCI_VENDOR_ID_INTEL, 0x10F1, pci_quirk_mf_endpoint_acs },
4329 { PCI_VENDOR_ID_INTEL, 0x10F7, pci_quirk_mf_endpoint_acs },
4330 { PCI_VENDOR_ID_INTEL, 0x10F8, pci_quirk_mf_endpoint_acs },
4331 { PCI_VENDOR_ID_INTEL, 0x10F9, pci_quirk_mf_endpoint_acs },
4332 { PCI_VENDOR_ID_INTEL, 0x10FA, pci_quirk_mf_endpoint_acs },
4333 { PCI_VENDOR_ID_INTEL, 0x10FB, pci_quirk_mf_endpoint_acs },
4334 { PCI_VENDOR_ID_INTEL, 0x10FC, pci_quirk_mf_endpoint_acs },
4335 { PCI_VENDOR_ID_INTEL, 0x1507, pci_quirk_mf_endpoint_acs },
4336 { PCI_VENDOR_ID_INTEL, 0x1514, pci_quirk_mf_endpoint_acs },
4337 { PCI_VENDOR_ID_INTEL, 0x151C, pci_quirk_mf_endpoint_acs },
4338 { PCI_VENDOR_ID_INTEL, 0x1529, pci_quirk_mf_endpoint_acs },
4339 { PCI_VENDOR_ID_INTEL, 0x152A, pci_quirk_mf_endpoint_acs },
4340 { PCI_VENDOR_ID_INTEL, 0x154D, pci_quirk_mf_endpoint_acs },
4341 { PCI_VENDOR_ID_INTEL, 0x154F, pci_quirk_mf_endpoint_acs },
4342 { PCI_VENDOR_ID_INTEL, 0x1551, pci_quirk_mf_endpoint_acs },
4343 { PCI_VENDOR_ID_INTEL, 0x1558, pci_quirk_mf_endpoint_acs },
Alex Williamsond7488042015-03-20 12:27:57 -06004344 /* 82580 */
4345 { PCI_VENDOR_ID_INTEL, 0x1509, pci_quirk_mf_endpoint_acs },
4346 { PCI_VENDOR_ID_INTEL, 0x150E, pci_quirk_mf_endpoint_acs },
4347 { PCI_VENDOR_ID_INTEL, 0x150F, pci_quirk_mf_endpoint_acs },
4348 { PCI_VENDOR_ID_INTEL, 0x1510, pci_quirk_mf_endpoint_acs },
4349 { PCI_VENDOR_ID_INTEL, 0x1511, pci_quirk_mf_endpoint_acs },
4350 { PCI_VENDOR_ID_INTEL, 0x1516, pci_quirk_mf_endpoint_acs },
4351 { PCI_VENDOR_ID_INTEL, 0x1527, pci_quirk_mf_endpoint_acs },
4352 /* 82576 */
4353 { PCI_VENDOR_ID_INTEL, 0x10C9, pci_quirk_mf_endpoint_acs },
4354 { PCI_VENDOR_ID_INTEL, 0x10E6, pci_quirk_mf_endpoint_acs },
4355 { PCI_VENDOR_ID_INTEL, 0x10E7, pci_quirk_mf_endpoint_acs },
4356 { PCI_VENDOR_ID_INTEL, 0x10E8, pci_quirk_mf_endpoint_acs },
4357 { PCI_VENDOR_ID_INTEL, 0x150A, pci_quirk_mf_endpoint_acs },
4358 { PCI_VENDOR_ID_INTEL, 0x150D, pci_quirk_mf_endpoint_acs },
4359 { PCI_VENDOR_ID_INTEL, 0x1518, pci_quirk_mf_endpoint_acs },
4360 { PCI_VENDOR_ID_INTEL, 0x1526, pci_quirk_mf_endpoint_acs },
4361 /* 82575 */
4362 { PCI_VENDOR_ID_INTEL, 0x10A7, pci_quirk_mf_endpoint_acs },
4363 { PCI_VENDOR_ID_INTEL, 0x10A9, pci_quirk_mf_endpoint_acs },
4364 { PCI_VENDOR_ID_INTEL, 0x10D6, pci_quirk_mf_endpoint_acs },
4365 /* I350 */
4366 { PCI_VENDOR_ID_INTEL, 0x1521, pci_quirk_mf_endpoint_acs },
4367 { PCI_VENDOR_ID_INTEL, 0x1522, pci_quirk_mf_endpoint_acs },
4368 { PCI_VENDOR_ID_INTEL, 0x1523, pci_quirk_mf_endpoint_acs },
4369 { PCI_VENDOR_ID_INTEL, 0x1524, pci_quirk_mf_endpoint_acs },
4370 /* 82571 (Quads omitted due to non-ACS switch) */
4371 { PCI_VENDOR_ID_INTEL, 0x105E, pci_quirk_mf_endpoint_acs },
4372 { PCI_VENDOR_ID_INTEL, 0x105F, pci_quirk_mf_endpoint_acs },
4373 { PCI_VENDOR_ID_INTEL, 0x1060, pci_quirk_mf_endpoint_acs },
4374 { PCI_VENDOR_ID_INTEL, 0x10D9, pci_quirk_mf_endpoint_acs },
Alex Williamson95e16582015-08-10 12:32:04 -06004375 /* I219 */
4376 { PCI_VENDOR_ID_INTEL, 0x15b7, pci_quirk_mf_endpoint_acs },
4377 { PCI_VENDOR_ID_INTEL, 0x15b8, pci_quirk_mf_endpoint_acs },
Sinan Kayab18877f2017-04-04 19:32:34 +00004378 /* QCOM QDF2xxx root ports */
4379 { 0x17cb, 0x400, pci_quirk_qcom_rp_acs },
4380 { 0x17cb, 0x401, pci_quirk_qcom_rp_acs },
Alex Williamsond7488042015-03-20 12:27:57 -06004381 /* Intel PCH root ports */
Alex Williamsond99321b2014-02-03 14:27:46 -07004382 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_pch_acs },
Alex Williamson1bf2bf22016-03-31 16:34:37 -06004383 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_intel_spt_pch_acs },
Vasundhara Volam6a3763d2015-01-13 01:22:23 -05004384 { 0x19a2, 0x710, pci_quirk_mf_endpoint_acs }, /* Emulex BE3-R */
4385 { 0x10df, 0x720, pci_quirk_mf_endpoint_acs }, /* Emulex Skyhawk-R */
Manish Jaggib404bcf2016-01-30 01:33:58 +05304386 /* Cavium ThunderX */
4387 { PCI_VENDOR_ID_CAVIUM, PCI_ANY_ID, pci_quirk_cavium_acs },
Alex Williamsonad805752012-06-11 05:27:07 +00004388 { 0 }
4389};
4390
4391int pci_dev_specific_acs_enabled(struct pci_dev *dev, u16 acs_flags)
4392{
4393 const struct pci_dev_acs_enabled *i;
4394 int ret;
4395
4396 /*
4397 * Allow devices that do not expose standard PCIe ACS capabilities
4398 * or control to indicate their support here. Multi-function express
4399 * devices which do not allow internal peer-to-peer between functions,
4400 * but do not implement PCIe ACS may wish to return true here.
4401 */
4402 for (i = pci_dev_acs_enabled; i->acs_enabled; i++) {
4403 if ((i->vendor == dev->vendor ||
4404 i->vendor == (u16)PCI_ANY_ID) &&
4405 (i->device == dev->device ||
4406 i->device == (u16)PCI_ANY_ID)) {
4407 ret = i->acs_enabled(dev, acs_flags);
4408 if (ret >= 0)
4409 return ret;
4410 }
4411 }
4412
4413 return -ENOTTY;
4414}
Alex Williamson2c744242014-02-03 14:27:33 -07004415
Alex Williamsond99321b2014-02-03 14:27:46 -07004416/* Config space offset of Root Complex Base Address register */
4417#define INTEL_LPC_RCBA_REG 0xf0
4418/* 31:14 RCBA address */
4419#define INTEL_LPC_RCBA_MASK 0xffffc000
4420/* RCBA Enable */
4421#define INTEL_LPC_RCBA_ENABLE (1 << 0)
4422
4423/* Backbone Scratch Pad Register */
4424#define INTEL_BSPR_REG 0x1104
4425/* Backbone Peer Non-Posted Disable */
4426#define INTEL_BSPR_REG_BPNPD (1 << 8)
4427/* Backbone Peer Posted Disable */
4428#define INTEL_BSPR_REG_BPPD (1 << 9)
4429
4430/* Upstream Peer Decode Configuration Register */
4431#define INTEL_UPDCR_REG 0x1114
4432/* 5:0 Peer Decode Enable bits */
4433#define INTEL_UPDCR_REG_MASK 0x3f
4434
4435static int pci_quirk_enable_intel_lpc_acs(struct pci_dev *dev)
4436{
4437 u32 rcba, bspr, updcr;
4438 void __iomem *rcba_mem;
4439
4440 /*
4441 * Read the RCBA register from the LPC (D31:F0). PCH root ports
4442 * are D28:F* and therefore get probed before LPC, thus we can't
4443 * use pci_get_slot/pci_read_config_dword here.
4444 */
4445 pci_bus_read_config_dword(dev->bus, PCI_DEVFN(31, 0),
4446 INTEL_LPC_RCBA_REG, &rcba);
4447 if (!(rcba & INTEL_LPC_RCBA_ENABLE))
4448 return -EINVAL;
4449
4450 rcba_mem = ioremap_nocache(rcba & INTEL_LPC_RCBA_MASK,
4451 PAGE_ALIGN(INTEL_UPDCR_REG));
4452 if (!rcba_mem)
4453 return -ENOMEM;
4454
4455 /*
4456 * The BSPR can disallow peer cycles, but it's set by soft strap and
4457 * therefore read-only. If both posted and non-posted peer cycles are
4458 * disallowed, we're ok. If either are allowed, then we need to use
4459 * the UPDCR to disable peer decodes for each port. This provides the
4460 * PCIe ACS equivalent of PCI_ACS_RR | PCI_ACS_CR | PCI_ACS_UF
4461 */
4462 bspr = readl(rcba_mem + INTEL_BSPR_REG);
4463 bspr &= INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD;
4464 if (bspr != (INTEL_BSPR_REG_BPNPD | INTEL_BSPR_REG_BPPD)) {
4465 updcr = readl(rcba_mem + INTEL_UPDCR_REG);
4466 if (updcr & INTEL_UPDCR_REG_MASK) {
4467 dev_info(&dev->dev, "Disabling UPDCR peer decodes\n");
4468 updcr &= ~INTEL_UPDCR_REG_MASK;
4469 writel(updcr, rcba_mem + INTEL_UPDCR_REG);
4470 }
4471 }
4472
4473 iounmap(rcba_mem);
4474 return 0;
4475}
4476
4477/* Miscellaneous Port Configuration register */
4478#define INTEL_MPC_REG 0xd8
4479/* MPC: Invalid Receive Bus Number Check Enable */
4480#define INTEL_MPC_REG_IRBNCE (1 << 26)
4481
4482static void pci_quirk_enable_intel_rp_mpc_acs(struct pci_dev *dev)
4483{
4484 u32 mpc;
4485
4486 /*
4487 * When enabled, the IRBNCE bit of the MPC register enables the
4488 * equivalent of PCI ACS Source Validation (PCI_ACS_SV), which
4489 * ensures that requester IDs fall within the bus number range
4490 * of the bridge. Enable if not already.
4491 */
4492 pci_read_config_dword(dev, INTEL_MPC_REG, &mpc);
4493 if (!(mpc & INTEL_MPC_REG_IRBNCE)) {
4494 dev_info(&dev->dev, "Enabling MPC IRBNCE\n");
4495 mpc |= INTEL_MPC_REG_IRBNCE;
4496 pci_write_config_word(dev, INTEL_MPC_REG, mpc);
4497 }
4498}
4499
4500static int pci_quirk_enable_intel_pch_acs(struct pci_dev *dev)
4501{
4502 if (!pci_quirk_intel_pch_acs_match(dev))
4503 return -ENOTTY;
4504
4505 if (pci_quirk_enable_intel_lpc_acs(dev)) {
4506 dev_warn(&dev->dev, "Failed to enable Intel PCH ACS quirk\n");
4507 return 0;
4508 }
4509
4510 pci_quirk_enable_intel_rp_mpc_acs(dev);
4511
4512 dev->dev_flags |= PCI_DEV_FLAGS_ACS_ENABLED_QUIRK;
4513
4514 dev_info(&dev->dev, "Intel PCH root port ACS workaround enabled\n");
4515
4516 return 0;
4517}
4518
Alex Williamson1bf2bf22016-03-31 16:34:37 -06004519static int pci_quirk_enable_intel_spt_pch_acs(struct pci_dev *dev)
4520{
4521 int pos;
4522 u32 cap, ctrl;
4523
4524 if (!pci_quirk_intel_spt_pch_acs_match(dev))
4525 return -ENOTTY;
4526
4527 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
4528 if (!pos)
4529 return -ENOTTY;
4530
4531 pci_read_config_dword(dev, pos + PCI_ACS_CAP, &cap);
4532 pci_read_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, &ctrl);
4533
4534 ctrl |= (cap & PCI_ACS_SV);
4535 ctrl |= (cap & PCI_ACS_RR);
4536 ctrl |= (cap & PCI_ACS_CR);
4537 ctrl |= (cap & PCI_ACS_UF);
4538
4539 pci_write_config_dword(dev, pos + INTEL_SPT_ACS_CTRL, ctrl);
4540
4541 dev_info(&dev->dev, "Intel SPT PCH root port ACS workaround enabled\n");
4542
4543 return 0;
4544}
4545
Alex Williamson2c744242014-02-03 14:27:33 -07004546static const struct pci_dev_enable_acs {
4547 u16 vendor;
4548 u16 device;
4549 int (*enable_acs)(struct pci_dev *dev);
4550} pci_dev_enable_acs[] = {
Alex Williamsond99321b2014-02-03 14:27:46 -07004551 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_pch_acs },
Alex Williamson1bf2bf22016-03-31 16:34:37 -06004552 { PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_quirk_enable_intel_spt_pch_acs },
Alex Williamson2c744242014-02-03 14:27:33 -07004553 { 0 }
4554};
4555
Alex Williamsonc1d61c92016-03-31 16:34:32 -06004556int pci_dev_specific_enable_acs(struct pci_dev *dev)
Alex Williamson2c744242014-02-03 14:27:33 -07004557{
4558 const struct pci_dev_enable_acs *i;
4559 int ret;
4560
4561 for (i = pci_dev_enable_acs; i->enable_acs; i++) {
4562 if ((i->vendor == dev->vendor ||
4563 i->vendor == (u16)PCI_ANY_ID) &&
4564 (i->device == dev->device ||
4565 i->device == (u16)PCI_ANY_ID)) {
4566 ret = i->enable_acs(dev);
4567 if (ret >= 0)
Alex Williamsonc1d61c92016-03-31 16:34:32 -06004568 return ret;
Alex Williamson2c744242014-02-03 14:27:33 -07004569 }
4570 }
Alex Williamsonc1d61c92016-03-31 16:34:32 -06004571
4572 return -ENOTTY;
Alex Williamson2c744242014-02-03 14:27:33 -07004573}
Tadeusz Struk3388a612015-08-07 11:34:42 -07004574
4575/*
4576 * The PCI capabilities list for Intel DH895xCC VFs (device id 0x0443) with
4577 * QuickAssist Technology (QAT) is prematurely terminated in hardware. The
4578 * Next Capability pointer in the MSI Capability Structure should point to
4579 * the PCIe Capability Structure but is incorrectly hardwired as 0 terminating
4580 * the list.
4581 */
4582static void quirk_intel_qat_vf_cap(struct pci_dev *pdev)
4583{
4584 int pos, i = 0;
4585 u8 next_cap;
4586 u16 reg16, *cap;
4587 struct pci_cap_saved_state *state;
4588
4589 /* Bail if the hardware bug is fixed */
4590 if (pdev->pcie_cap || pci_find_capability(pdev, PCI_CAP_ID_EXP))
4591 return;
4592
4593 /* Bail if MSI Capability Structure is not found for some reason */
4594 pos = pci_find_capability(pdev, PCI_CAP_ID_MSI);
4595 if (!pos)
4596 return;
4597
4598 /*
4599 * Bail if Next Capability pointer in the MSI Capability Structure
4600 * is not the expected incorrect 0x00.
4601 */
4602 pci_read_config_byte(pdev, pos + 1, &next_cap);
4603 if (next_cap)
4604 return;
4605
4606 /*
4607 * PCIe Capability Structure is expected to be at 0x50 and should
4608 * terminate the list (Next Capability pointer is 0x00). Verify
4609 * Capability Id and Next Capability pointer is as expected.
4610 * Open-code some of set_pcie_port_type() and pci_cfg_space_size_ext()
4611 * to correctly set kernel data structures which have already been
4612 * set incorrectly due to the hardware bug.
4613 */
4614 pos = 0x50;
4615 pci_read_config_word(pdev, pos, &reg16);
4616 if (reg16 == (0x0000 | PCI_CAP_ID_EXP)) {
4617 u32 status;
4618#ifndef PCI_EXP_SAVE_REGS
4619#define PCI_EXP_SAVE_REGS 7
4620#endif
4621 int size = PCI_EXP_SAVE_REGS * sizeof(u16);
4622
4623 pdev->pcie_cap = pos;
4624 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, &reg16);
4625 pdev->pcie_flags_reg = reg16;
4626 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, &reg16);
4627 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
4628
4629 pdev->cfg_size = PCI_CFG_SPACE_EXP_SIZE;
4630 if (pci_read_config_dword(pdev, PCI_CFG_SPACE_SIZE, &status) !=
4631 PCIBIOS_SUCCESSFUL || (status == 0xffffffff))
4632 pdev->cfg_size = PCI_CFG_SPACE_SIZE;
4633
4634 if (pci_find_saved_cap(pdev, PCI_CAP_ID_EXP))
4635 return;
4636
4637 /*
4638 * Save PCIE cap
4639 */
4640 state = kzalloc(sizeof(*state) + size, GFP_KERNEL);
4641 if (!state)
4642 return;
4643
4644 state->cap.cap_nr = PCI_CAP_ID_EXP;
4645 state->cap.cap_extended = 0;
4646 state->cap.size = size;
4647 cap = (u16 *)&state->cap.data[0];
4648 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL, &cap[i++]);
4649 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &cap[i++]);
4650 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL, &cap[i++]);
4651 pcie_capability_read_word(pdev, PCI_EXP_RTCTL, &cap[i++]);
4652 pcie_capability_read_word(pdev, PCI_EXP_DEVCTL2, &cap[i++]);
4653 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL2, &cap[i++]);
4654 pcie_capability_read_word(pdev, PCI_EXP_SLTCTL2, &cap[i++]);
4655 hlist_add_head(&state->next, &pdev->saved_cap_space);
4656 }
4657}
4658DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x443, quirk_intel_qat_vf_cap);
Jon Derrick443b40b2016-09-06 14:15:24 -05004659
4660/*
4661 * VMD-enabled root ports will change the source ID for all messages
4662 * to the VMD device. Rather than doing device matching with the source
4663 * ID, the AER driver should traverse the child device tree, reading
4664 * AER registers to find the faulting device.
4665 */
4666static void quirk_no_aersid(struct pci_dev *pdev)
4667{
4668 /* VMD Domain */
4669 if (pdev->bus->sysdata && pci_domain_nr(pdev->bus) >= 0x10000)
4670 pdev->bus->bus_flags |= PCI_BUS_FLAGS_NO_AERSID;
4671}
4672DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2030, quirk_no_aersid);
4673DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2031, quirk_no_aersid);
4674DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2032, quirk_no_aersid);
4675DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_INTEL, 0x2033, quirk_no_aersid);