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Chaithrika U Sb67f4482009-06-05 06:28:40 -04001/*
2 * ALSA SoC McASP Audio Layer for TI DAVINCI processor
3 *
4 * Multi-channel Audio Serial Port Driver
5 *
6 * Author: Nirmal Pandey <n-pandey@ti.com>,
7 * Suresh Rajashekara <suresh.r@ti.com>
8 * Steve Chen <schen@.mvista.com>
9 *
10 * Copyright: (C) 2009 MontaVista Software, Inc., <source@mvista.com>
11 * Copyright: (C) 2009 Texas Instruments, India
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License version 2 as
15 * published by the Free Software Foundation.
16 */
17
18#include <linux/init.h>
19#include <linux/module.h>
20#include <linux/device.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090021#include <linux/slab.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040022#include <linux/delay.h>
23#include <linux/io.h>
Peter Ujfalusiae726e92013-11-14 11:35:35 +020024#include <linux/clk.h>
Hebbar, Gururaja10884342012-08-08 20:40:32 +053025#include <linux/pm_runtime.h>
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +053026#include <linux/of.h>
27#include <linux/of_platform.h>
28#include <linux/of_device.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040029
30#include <sound/core.h>
31#include <sound/pcm.h>
32#include <sound/pcm_params.h>
33#include <sound/initval.h>
34#include <sound/soc.h>
Peter Ujfalusi453c4992013-11-14 11:35:34 +020035#include <sound/dmaengine_pcm.h>
Chaithrika U Sb67f4482009-06-05 06:28:40 -040036
37#include "davinci-pcm.h"
38#include "davinci-mcasp.h"
39
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +030040#define MCASP_MAX_AFIFO_DEPTH 64
41
Peter Ujfalusi790bb942014-02-03 14:51:52 +020042struct davinci_mcasp_context {
43 u32 txfmtctl;
44 u32 rxfmtctl;
45 u32 txfmt;
46 u32 rxfmt;
47 u32 aclkxctl;
48 u32 aclkrctl;
49 u32 pdir;
50};
51
Peter Ujfalusi70091a32013-11-14 11:35:29 +020052struct davinci_mcasp {
Peter Ujfalusi21400a72013-11-14 11:35:26 +020053 struct davinci_pcm_dma_params dma_params[2];
Peter Ujfalusi453c4992013-11-14 11:35:34 +020054 struct snd_dmaengine_dai_dma_data dma_data[2];
Peter Ujfalusi21400a72013-11-14 11:35:26 +020055 void __iomem *base;
Peter Ujfalusi487dce82013-11-14 11:35:31 +020056 u32 fifo_base;
Peter Ujfalusi21400a72013-11-14 11:35:26 +020057 struct device *dev;
58
59 /* McASP specific data */
60 int tdm_slots;
61 u8 op_mode;
62 u8 num_serializer;
63 u8 *serial_dir;
64 u8 version;
65 u16 bclk_lrclk_ratio;
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +020066 int streams;
Peter Ujfalusi21400a72013-11-14 11:35:26 +020067
Jyri Sarhaab8b14b2014-01-27 17:37:52 +020068 int sysclk_freq;
69 bool bclk_master;
70
Peter Ujfalusi21400a72013-11-14 11:35:26 +020071 /* McASP FIFO related */
72 u8 txnumevt;
73 u8 rxnumevt;
74
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +020075 bool dat_port;
76
Peter Ujfalusi21400a72013-11-14 11:35:26 +020077#ifdef CONFIG_PM_SLEEP
Peter Ujfalusi790bb942014-02-03 14:51:52 +020078 struct davinci_mcasp_context context;
Peter Ujfalusi21400a72013-11-14 11:35:26 +020079#endif
80};
81
Peter Ujfalusif68205a2013-11-14 11:35:36 +020082static inline void mcasp_set_bits(struct davinci_mcasp *mcasp, u32 offset,
83 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -040084{
Peter Ujfalusif68205a2013-11-14 11:35:36 +020085 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -040086 __raw_writel(__raw_readl(reg) | val, reg);
87}
88
Peter Ujfalusif68205a2013-11-14 11:35:36 +020089static inline void mcasp_clr_bits(struct davinci_mcasp *mcasp, u32 offset,
90 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -040091{
Peter Ujfalusif68205a2013-11-14 11:35:36 +020092 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -040093 __raw_writel((__raw_readl(reg) & ~(val)), reg);
94}
95
Peter Ujfalusif68205a2013-11-14 11:35:36 +020096static inline void mcasp_mod_bits(struct davinci_mcasp *mcasp, u32 offset,
97 u32 val, u32 mask)
Chaithrika U Sb67f4482009-06-05 06:28:40 -040098{
Peter Ujfalusif68205a2013-11-14 11:35:36 +020099 void __iomem *reg = mcasp->base + offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400100 __raw_writel((__raw_readl(reg) & ~mask) | val, reg);
101}
102
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200103static inline void mcasp_set_reg(struct davinci_mcasp *mcasp, u32 offset,
104 u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400105{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200106 __raw_writel(val, mcasp->base + offset);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400107}
108
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200109static inline u32 mcasp_get_reg(struct davinci_mcasp *mcasp, u32 offset)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400110{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200111 return (u32)__raw_readl(mcasp->base + offset);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400112}
113
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200114static void mcasp_set_ctl_reg(struct davinci_mcasp *mcasp, u32 ctl_reg, u32 val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400115{
116 int i = 0;
117
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200118 mcasp_set_bits(mcasp, ctl_reg, val);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400119
120 /* programming GBLCTL needs to read back from GBLCTL and verfiy */
121 /* loop count is to avoid the lock-up */
122 for (i = 0; i < 1000; i++) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200123 if ((mcasp_get_reg(mcasp, ctl_reg) & val) == val)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400124 break;
125 }
126
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200127 if (i == 1000 && ((mcasp_get_reg(mcasp, ctl_reg) & val) != val))
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400128 printk(KERN_ERR "GBLCTL write error\n");
129}
130
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200131static bool mcasp_is_synchronous(struct davinci_mcasp *mcasp)
132{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200133 u32 rxfmctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
134 u32 aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200135
136 return !(aclkxctl & TX_ASYNC) && rxfmctl & AFSRE;
137}
138
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200139static void mcasp_start_rx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400140{
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200141 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXHCLKRST);
142 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXCLKRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200143
144 /*
145 * When ASYNC == 0 the transmit and receive sections operate
146 * synchronously from the transmit clock and frame sync. We need to make
147 * sure that the TX signlas are enabled when starting reception.
148 */
149 if (mcasp_is_synchronous(mcasp)) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200150 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
151 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200152 }
153
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200154 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSERCLR);
155 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400156
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200157 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
158 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
159 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXBUF_REG, 0);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400160
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200161 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXSMRST);
162 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, RXFSRST);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200163
164 if (mcasp_is_synchronous(mcasp))
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200165 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400166}
167
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200168static void mcasp_start_tx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400169{
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400170 u8 offset = 0, i;
171 u32 cnt;
172
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200173 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXHCLKRST);
174 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXCLKRST);
175 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSERCLR);
176 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400177
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200178 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXSMRST);
179 mcasp_set_ctl_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, TXFSRST);
180 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200181 for (i = 0; i < mcasp->num_serializer; i++) {
182 if (mcasp->serial_dir[i] == TX_MODE) {
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400183 offset = i;
184 break;
185 }
186 }
187
188 /* wait for TX ready */
189 cnt = 0;
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200190 while (!(mcasp_get_reg(mcasp, DAVINCI_MCASP_XRSRCTL_REG(offset)) &
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400191 TXSTATE) && (cnt < 100000))
192 cnt++;
193
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200194 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXBUF_REG, 0);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400195}
196
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200197static void davinci_mcasp_start(struct davinci_mcasp *mcasp, int stream)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400198{
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200199 u32 reg;
200
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200201 mcasp->streams++;
202
Chaithrika U S539d3d82009-09-23 10:12:08 -0400203 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200204 if (mcasp->txnumevt) { /* enable FIFO */
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200205 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200206 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
207 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
Vaibhav Bedia0d624272012-08-08 20:40:31 +0530208 }
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200209 mcasp_start_tx(mcasp);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400210 } else {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200211 if (mcasp->rxnumevt) { /* enable FIFO */
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200212 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200213 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
214 mcasp_set_bits(mcasp, reg, FIFO_ENABLE);
Vaibhav Bedia0d624272012-08-08 20:40:31 +0530215 }
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200216 mcasp_start_rx(mcasp);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400217 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400218}
219
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200220static void mcasp_stop_rx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400221{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200222 /*
223 * In synchronous mode stop the TX clocks if no other stream is
224 * running
225 */
226 if (mcasp_is_synchronous(mcasp) && !mcasp->streams)
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200227 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, 0);
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200228
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200229 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLR_REG, 0);
230 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400231}
232
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200233static void mcasp_stop_tx(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400234{
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200235 u32 val = 0;
236
237 /*
238 * In synchronous mode keep TX clocks running if the capture stream is
239 * still running.
240 */
241 if (mcasp_is_synchronous(mcasp) && mcasp->streams)
242 val = TXHCLKRST | TXCLKRST | TXFSRST;
243
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200244 mcasp_set_reg(mcasp, DAVINCI_MCASP_GBLCTLX_REG, val);
245 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400246}
247
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200248static void davinci_mcasp_stop(struct davinci_mcasp *mcasp, int stream)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400249{
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200250 u32 reg;
251
Peter Ujfalusi4dcb5a02013-11-14 11:35:33 +0200252 mcasp->streams--;
253
Chaithrika U S539d3d82009-09-23 10:12:08 -0400254 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200255 if (mcasp->txnumevt) { /* disable FIFO */
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200256 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200257 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530258 }
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200259 mcasp_stop_tx(mcasp);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400260 } else {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200261 if (mcasp->rxnumevt) { /* disable FIFO */
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200262 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200263 mcasp_clr_bits(mcasp, reg, FIFO_ENABLE);
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530264 }
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200265 mcasp_stop_rx(mcasp);
Chaithrika U S539d3d82009-09-23 10:12:08 -0400266 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400267}
268
269static int davinci_mcasp_set_dai_fmt(struct snd_soc_dai *cpu_dai,
270 unsigned int fmt)
271{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200272 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200273 int ret = 0;
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300274 u32 data_delay;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400275
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200276 pm_runtime_get_sync(mcasp->dev);
Daniel Mack5296cf22012-10-04 15:08:42 +0200277 switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
278 case SND_SOC_DAIFMT_DSP_B:
279 case SND_SOC_DAIFMT_AC97:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200280 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
281 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300282
283 /* No delay after FS */
284 data_delay = 0;
Daniel Mack5296cf22012-10-04 15:08:42 +0200285 break;
286 default:
287 /* configure a full-word SYNC pulse (LRCLK) */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200288 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXDUR);
289 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRDUR);
Daniel Mack5296cf22012-10-04 15:08:42 +0200290
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300291 /* 1st data bit occur one ACLK cycle after the frame sync */
292 data_delay = 1;
Daniel Mack5296cf22012-10-04 15:08:42 +0200293 break;
294 }
295
Peter Ujfalusi6dfa9a42014-04-04 14:31:42 +0300296 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, FSXDLY(data_delay),
297 FSXDLY(3));
298 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, FSRDLY(data_delay),
299 FSRDLY(3));
300
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400301 switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
302 case SND_SOC_DAIFMT_CBS_CFS:
303 /* codec is clock and frame slave */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200304 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
305 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400306
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200307 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
308 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400309
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200310 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
311 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200312 mcasp->bclk_master = 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400313 break;
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400314 case SND_SOC_DAIFMT_CBM_CFS:
315 /* codec is clock master and frame slave */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200316 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
317 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400318
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200319 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
320 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400321
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200322 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, ACLKX | ACLKR);
323 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AFSX | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200324 mcasp->bclk_master = 0;
Chaithrika U S517ee6c2009-08-11 16:59:12 -0400325 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400326 case SND_SOC_DAIFMT_CBM_CFM:
327 /* codec is clock and frame master */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200328 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE);
329 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400330
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200331 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRE);
332 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, AFSRE);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400333
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200334 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG,
335 ACLKX | AHCLKX | AFSX | ACLKR | AHCLKR | AFSR);
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200336 mcasp->bclk_master = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400337 break;
338
339 default:
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200340 ret = -EINVAL;
341 goto out;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400342 }
343
344 switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
345 case SND_SOC_DAIFMT_IB_NF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200346 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
347 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400348
Peter Ujfalusi74ddd8c2014-04-04 14:31:41 +0300349 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200350 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400351 break;
352
353 case SND_SOC_DAIFMT_NB_IF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200354 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
355 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400356
Peter Ujfalusi74ddd8c2014-04-04 14:31:41 +0300357 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200358 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400359 break;
360
361 case SND_SOC_DAIFMT_IB_IF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200362 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
363 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400364
Peter Ujfalusi74ddd8c2014-04-04 14:31:41 +0300365 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200366 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400367 break;
368
369 case SND_SOC_DAIFMT_NB_NF:
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200370 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXPOL);
371 mcasp_clr_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG, FSXPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400372
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200373 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, ACLKRPOL);
374 mcasp_clr_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG, FSRPOL);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400375 break;
376
377 default:
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200378 ret = -EINVAL;
379 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400380 }
Peter Ujfalusi1d17a042014-01-30 15:21:30 +0200381out:
382 pm_runtime_put_sync(mcasp->dev);
383 return ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400384}
385
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200386static int davinci_mcasp_set_clkdiv(struct snd_soc_dai *dai, int div_id, int div)
387{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200388 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200389
390 switch (div_id) {
391 case 0: /* MCLK divider */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200392 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200393 AHCLKXDIV(div - 1), AHCLKXDIV_MASK);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200394 mcasp_mod_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200395 AHCLKRDIV(div - 1), AHCLKRDIV_MASK);
396 break;
397
398 case 1: /* BCLK divider */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200399 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200400 ACLKXDIV(div - 1), ACLKXDIV_MASK);
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200401 mcasp_mod_bits(mcasp, DAVINCI_MCASP_ACLKRCTL_REG,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200402 ACLKRDIV(div - 1), ACLKRDIV_MASK);
403 break;
404
Daniel Mack1b3bc062012-12-05 18:20:38 +0100405 case 2: /* BCLK/LRCLK ratio */
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200406 mcasp->bclk_lrclk_ratio = div;
Daniel Mack1b3bc062012-12-05 18:20:38 +0100407 break;
408
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200409 default:
410 return -EINVAL;
411 }
412
413 return 0;
414}
415
Daniel Mack5b66aa22012-10-04 15:08:41 +0200416static int davinci_mcasp_set_sysclk(struct snd_soc_dai *dai, int clk_id,
417 unsigned int freq, int dir)
418{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200419 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200420
421 if (dir == SND_SOC_CLOCK_OUT) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200422 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
423 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
424 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200425 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200426 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXE);
427 mcasp_clr_bits(mcasp, DAVINCI_MCASP_AHCLKRCTL_REG, AHCLKRE);
428 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AHCLKX);
Daniel Mack5b66aa22012-10-04 15:08:41 +0200429 }
430
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200431 mcasp->sysclk_freq = freq;
432
Daniel Mack5b66aa22012-10-04 15:08:41 +0200433 return 0;
434}
435
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200436static int davinci_config_channel_size(struct davinci_mcasp *mcasp,
Daniel Mackba764b32012-12-05 18:20:37 +0100437 int word_length)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400438{
Daniel Mackba764b32012-12-05 18:20:37 +0100439 u32 fmt;
Daniel Mack79671892013-05-16 15:25:01 +0200440 u32 tx_rotate = (word_length / 4) & 0x7;
441 u32 rx_rotate = (32 - word_length) / 4;
Daniel Mackba764b32012-12-05 18:20:37 +0100442 u32 mask = (1ULL << word_length) - 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400443
Daniel Mack1b3bc062012-12-05 18:20:38 +0100444 /*
445 * if s BCLK-to-LRCLK ratio has been configured via the set_clkdiv()
446 * callback, take it into account here. That allows us to for example
447 * send 32 bits per channel to the codec, while only 16 of them carry
448 * audio payload.
Michal Bachratyd486fea2013-04-19 15:28:44 +0200449 * The clock ratio is given for a full period of data (for I2S format
450 * both left and right channels), so it has to be divided by number of
451 * tdm-slots (for I2S - divided by 2).
Daniel Mack1b3bc062012-12-05 18:20:38 +0100452 */
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200453 if (mcasp->bclk_lrclk_ratio)
454 word_length = mcasp->bclk_lrclk_ratio / mcasp->tdm_slots;
Daniel Mack1b3bc062012-12-05 18:20:38 +0100455
Daniel Mackba764b32012-12-05 18:20:37 +0100456 /* mapping of the XSSZ bit-field as described in the datasheet */
457 fmt = (word_length >> 1) - 1;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400458
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200459 if (mcasp->op_mode != DAVINCI_MCASP_DIT_MODE) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200460 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXSSZ(fmt),
461 RXSSZ(0x0F));
462 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXSSZ(fmt),
463 TXSSZ(0x0F));
464 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(tx_rotate),
465 TXROT(7));
466 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, RXROT(rx_rotate),
467 RXROT(7));
468 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXMASK_REG, mask);
Yegor Yefremovf5023af2013-04-04 16:13:20 +0200469 }
470
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200471 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXMASK_REG, mask);
Chaithrika U S0c31cf32009-09-15 18:13:29 -0400472
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400473 return 0;
474}
475
Peter Ujfalusi662ffae2014-01-30 15:15:22 +0200476static int mcasp_common_hw_param(struct davinci_mcasp *mcasp, int stream,
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300477 int period_words, int channels)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400478{
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300479 struct davinci_pcm_dma_params *dma_params = &mcasp->dma_params[stream];
480 struct snd_dmaengine_dai_dma_data *dma_data = &mcasp->dma_data[stream];
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400481 int i;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400482 u8 tx_ser = 0;
483 u8 rx_ser = 0;
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200484 u8 slots = mcasp->tdm_slots;
Michal Bachraty2952b272013-02-28 16:07:08 +0100485 u8 max_active_serializers = (channels + slots - 1) / slots;
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300486 int active_serializers, numevt, n;
Peter Ujfalusi487dce82013-11-14 11:35:31 +0200487 u32 reg;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400488 /* Default configuration */
Peter Ujfalusi453c4992013-11-14 11:35:34 +0200489 if (mcasp->version != MCASP_VERSION_4)
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200490 mcasp_set_bits(mcasp, DAVINCI_MCASP_PWREMUMGT_REG, MCASP_SOFT);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400491
492 /* All PINS as McASP */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200493 mcasp_set_reg(mcasp, DAVINCI_MCASP_PFUNC_REG, 0x00000000);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400494
495 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200496 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXSTAT_REG, 0xFFFFFFFF);
497 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400498 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200499 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXSTAT_REG, 0xFFFFFFFF);
500 mcasp_clr_bits(mcasp, DAVINCI_MCASP_REVTCTL_REG, RXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400501 }
502
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200503 for (i = 0; i < mcasp->num_serializer; i++) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200504 mcasp_set_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
505 mcasp->serial_dir[i]);
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200506 if (mcasp->serial_dir[i] == TX_MODE &&
Michal Bachraty2952b272013-02-28 16:07:08 +0100507 tx_ser < max_active_serializers) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200508 mcasp_set_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400509 tx_ser++;
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200510 } else if (mcasp->serial_dir[i] == RX_MODE &&
Michal Bachraty2952b272013-02-28 16:07:08 +0100511 rx_ser < max_active_serializers) {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200512 mcasp_clr_bits(mcasp, DAVINCI_MCASP_PDIR_REG, AXR(i));
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400513 rx_ser++;
Michal Bachraty2952b272013-02-28 16:07:08 +0100514 } else {
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200515 mcasp_mod_bits(mcasp, DAVINCI_MCASP_XRSRCTL_REG(i),
516 SRMOD_INACTIVE, SRMOD_MASK);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400517 }
518 }
519
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300520 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
521 active_serializers = tx_ser;
522 numevt = mcasp->txnumevt;
523 reg = mcasp->fifo_base + MCASP_WFIFOCTL_OFFSET;
524 } else {
525 active_serializers = rx_ser;
526 numevt = mcasp->rxnumevt;
527 reg = mcasp->fifo_base + MCASP_RFIFOCTL_OFFSET;
528 }
Daniel Mackecf327c2013-03-08 14:19:38 +0100529
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300530 if (active_serializers < max_active_serializers) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200531 dev_warn(mcasp->dev, "stream has more channels (%d) than are "
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300532 "enabled in mcasp (%d)\n", channels,
533 active_serializers * slots);
Daniel Mackecf327c2013-03-08 14:19:38 +0100534 return -EINVAL;
535 }
536
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300537 /* AFIFO is not in use */
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300538 if (!numevt) {
539 /* Configure the burst size for platform drivers */
Peter Ujfalusi33445642014-04-01 15:55:12 +0300540 if (active_serializers > 1) {
541 /*
542 * If more than one serializers are in use we have one
543 * DMA request to provide data for all serializers.
544 * For example if three serializers are enabled the DMA
545 * need to transfer three words per DMA request.
546 */
547 dma_params->fifo_level = active_serializers;
548 dma_data->maxburst = active_serializers;
549 } else {
550 dma_params->fifo_level = 0;
551 dma_data->maxburst = 0;
552 }
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300553 return 0;
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300554 }
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400555
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300556 if (period_words % active_serializers) {
557 dev_err(mcasp->dev, "Invalid combination of period words and "
558 "active serializers: %d, %d\n", period_words,
559 active_serializers);
560 return -EINVAL;
561 }
562
563 /*
564 * Calculate the optimal AFIFO depth for platform side:
565 * The number of words for numevt need to be in steps of active
566 * serializers.
567 */
568 n = numevt % active_serializers;
569 if (n)
570 numevt += (active_serializers - n);
571 while (period_words % numevt && numevt > 0)
572 numevt -= active_serializers;
573 if (numevt <= 0)
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300574 numevt = active_serializers;
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400575
Peter Ujfalusi0bf0e8a2014-04-01 15:55:09 +0300576 mcasp_mod_bits(mcasp, reg, active_serializers, NUMDMA_MASK);
577 mcasp_mod_bits(mcasp, reg, NUMEVT(numevt), NUMEVT_MASK);
Michal Bachraty2952b272013-02-28 16:07:08 +0100578
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300579 /* Configure the burst size for platform drivers */
Peter Ujfalusi33445642014-04-01 15:55:12 +0300580 if (numevt == 1)
581 numevt = 0;
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300582 dma_params->fifo_level = numevt;
583 dma_data->maxburst = numevt;
584
Michal Bachraty2952b272013-02-28 16:07:08 +0100585 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400586}
587
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200588static int mcasp_i2s_hw_param(struct davinci_mcasp *mcasp, int stream)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400589{
590 int i, active_slots;
591 u32 mask = 0;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200592 u32 busel = 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400593
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200594 if ((mcasp->tdm_slots < 2) || (mcasp->tdm_slots > 32)) {
595 dev_err(mcasp->dev, "tdm slot %d not supported\n",
596 mcasp->tdm_slots);
597 return -EINVAL;
598 }
599
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200600 active_slots = (mcasp->tdm_slots > 31) ? 32 : mcasp->tdm_slots;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400601 for (i = 0; i < active_slots; i++)
602 mask |= (1 << i);
603
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200604 mcasp_clr_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, TX_ASYNC);
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400605
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +0200606 if (!mcasp->dat_port)
607 busel = TXSEL;
608
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200609 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, mask);
610 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, busel | TXORD);
611 mcasp_mod_bits(mcasp, DAVINCI_MCASP_TXFMCTL_REG,
612 FSXMOD(mcasp->tdm_slots), FSXMOD(0x1FF));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400613
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200614 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXTDM_REG, mask);
615 mcasp_set_bits(mcasp, DAVINCI_MCASP_RXFMT_REG, busel | RXORD);
616 mcasp_mod_bits(mcasp, DAVINCI_MCASP_RXFMCTL_REG,
617 FSRMOD(mcasp->tdm_slots), FSRMOD(0x1FF));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400618
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200619 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400620}
621
622/* S/PDIF */
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200623static int mcasp_dit_hw_param(struct davinci_mcasp *mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400624{
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400625 /* Set the TX format : 24 bit right rotation, 32 bit slot, Pad 0
626 and LSB first */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200627 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXFMT_REG, TXROT(6) | TXSSZ(15));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400628
629 /* Set TX frame synch : DIT Mode, 1 bit width, internal, rising edge */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200630 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, AFSXE | FSXMOD(0x180));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400631
632 /* Set the TX tdm : for all the slots */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200633 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXTDM_REG, 0xFFFFFFFF);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400634
635 /* Set the TX clock controls : div = 1 and internal */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200636 mcasp_set_bits(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, ACLKXE | TX_ASYNC);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400637
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200638 mcasp_clr_bits(mcasp, DAVINCI_MCASP_XEVTCTL_REG, TXDATADMADIS);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400639
640 /* Only 44100 and 48000 are valid, both have the same setting */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200641 mcasp_set_bits(mcasp, DAVINCI_MCASP_AHCLKXCTL_REG, AHCLKXDIV(3));
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400642
643 /* Enable the DIT */
Peter Ujfalusif68205a2013-11-14 11:35:36 +0200644 mcasp_set_bits(mcasp, DAVINCI_MCASP_TXDITCTL_REG, DITEN);
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200645
646 return 0;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400647}
648
649static int davinci_mcasp_hw_params(struct snd_pcm_substream *substream,
650 struct snd_pcm_hw_params *params,
651 struct snd_soc_dai *cpu_dai)
652{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200653 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400654 struct davinci_pcm_dma_params *dma_params =
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200655 &mcasp->dma_params[substream->stream];
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400656 int word_length;
Peter Ujfalusia7e46bd2014-02-03 14:51:50 +0200657 int channels = params_channels(params);
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300658 int period_size = params_period_size(params);
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200659 int ret;
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200660
661 /* If mcasp is BCLK master we need to set BCLK divider */
662 if (mcasp->bclk_master) {
663 unsigned int bclk_freq = snd_soc_params_to_bclk(params);
664 if (mcasp->sysclk_freq % bclk_freq != 0) {
Peter Ujfalusif5b02b42014-04-01 15:55:08 +0300665 dev_err(mcasp->dev, "Can't produce required BCLK\n");
Jyri Sarhaab8b14b2014-01-27 17:37:52 +0200666 return -EINVAL;
667 }
668 davinci_mcasp_set_clkdiv(
669 cpu_dai, 1, mcasp->sysclk_freq / bclk_freq);
670 }
671
Peter Ujfalusidd093a02014-04-01 15:55:11 +0300672 ret = mcasp_common_hw_param(mcasp, substream->stream,
673 period_size * channels, channels);
Peter Ujfalusi0f7d9a62014-01-30 15:15:24 +0200674 if (ret)
675 return ret;
676
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200677 if (mcasp->op_mode == DAVINCI_MCASP_DIT_MODE)
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200678 ret = mcasp_dit_hw_param(mcasp);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400679 else
Peter Ujfalusi2c56c4c2014-01-30 15:15:23 +0200680 ret = mcasp_i2s_hw_param(mcasp, substream->stream);
681
682 if (ret)
683 return ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400684
685 switch (params_format(params)) {
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400686 case SNDRV_PCM_FORMAT_U8:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400687 case SNDRV_PCM_FORMAT_S8:
688 dma_params->data_type = 1;
Daniel Mackba764b32012-12-05 18:20:37 +0100689 word_length = 8;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400690 break;
691
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400692 case SNDRV_PCM_FORMAT_U16_LE:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400693 case SNDRV_PCM_FORMAT_S16_LE:
694 dma_params->data_type = 2;
Daniel Mackba764b32012-12-05 18:20:37 +0100695 word_length = 16;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400696 break;
697
Daniel Mack21eb24d2012-10-09 09:35:16 +0200698 case SNDRV_PCM_FORMAT_U24_3LE:
699 case SNDRV_PCM_FORMAT_S24_3LE:
Daniel Mack21eb24d2012-10-09 09:35:16 +0200700 dma_params->data_type = 3;
Daniel Mackba764b32012-12-05 18:20:37 +0100701 word_length = 24;
Daniel Mack21eb24d2012-10-09 09:35:16 +0200702 break;
703
Daniel Mack6b7fa012012-10-09 11:56:40 +0200704 case SNDRV_PCM_FORMAT_U24_LE:
705 case SNDRV_PCM_FORMAT_S24_LE:
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400706 case SNDRV_PCM_FORMAT_U32_LE:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400707 case SNDRV_PCM_FORMAT_S32_LE:
708 dma_params->data_type = 4;
Daniel Mackba764b32012-12-05 18:20:37 +0100709 word_length = 32;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400710 break;
711
712 default:
713 printk(KERN_WARNING "davinci-mcasp: unsupported PCM format");
714 return -EINVAL;
715 }
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400716
Peter Ujfalusi5f04c602014-04-01 15:55:10 +0300717 if (mcasp->version == MCASP_VERSION_2 && !dma_params->fifo_level)
Chaithrika U S4fa9c1a2009-09-30 17:32:27 -0400718 dma_params->acnt = 4;
719 else
Chaithrika U S6a99fb52009-08-11 16:58:52 -0400720 dma_params->acnt = dma_params->data_type;
721
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200722 davinci_config_channel_size(mcasp, word_length);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400723
724 return 0;
725}
726
727static int davinci_mcasp_trigger(struct snd_pcm_substream *substream,
728 int cmd, struct snd_soc_dai *cpu_dai)
729{
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200730 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(cpu_dai);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400731 int ret = 0;
732
733 switch (cmd) {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400734 case SNDRV_PCM_TRIGGER_RESUME:
Chaithrika U Se473b842010-01-20 17:06:33 +0530735 case SNDRV_PCM_TRIGGER_START:
736 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200737 davinci_mcasp_start(mcasp, substream->stream);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400738 break;
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400739 case SNDRV_PCM_TRIGGER_SUSPEND:
Chaithrika U Sa47979b2009-12-03 18:56:56 +0530740 case SNDRV_PCM_TRIGGER_STOP:
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400741 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
Peter Ujfalusi70091a32013-11-14 11:35:29 +0200742 davinci_mcasp_stop(mcasp, substream->stream);
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400743 break;
744
745 default:
746 ret = -EINVAL;
747 }
748
749 return ret;
750}
751
Lars-Peter Clausen85e76522011-11-23 11:40:40 +0100752static const struct snd_soc_dai_ops davinci_mcasp_dai_ops = {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400753 .trigger = davinci_mcasp_trigger,
754 .hw_params = davinci_mcasp_hw_params,
755 .set_fmt = davinci_mcasp_set_dai_fmt,
Daniel Mack4ed8c9b2012-10-04 15:08:39 +0200756 .set_clkdiv = davinci_mcasp_set_clkdiv,
Daniel Mack5b66aa22012-10-04 15:08:41 +0200757 .set_sysclk = davinci_mcasp_set_sysclk,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400758};
759
Peter Ujfalusid5902f62014-04-01 15:55:07 +0300760static int davinci_mcasp_dai_probe(struct snd_soc_dai *dai)
761{
762 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
763
764 if (mcasp->version == MCASP_VERSION_4) {
765 /* Using dmaengine PCM */
766 dai->playback_dma_data =
767 &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
768 dai->capture_dma_data =
769 &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
770 } else {
771 /* Using davinci-pcm */
772 dai->playback_dma_data = mcasp->dma_params;
773 dai->capture_dma_data = mcasp->dma_params;
774 }
775
776 return 0;
777}
778
Peter Ujfalusi135014a2014-01-30 15:21:32 +0200779#ifdef CONFIG_PM_SLEEP
780static int davinci_mcasp_suspend(struct snd_soc_dai *dai)
781{
782 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Peter Ujfalusi790bb942014-02-03 14:51:52 +0200783 struct davinci_mcasp_context *context = &mcasp->context;
Peter Ujfalusi135014a2014-01-30 15:21:32 +0200784
Peter Ujfalusi790bb942014-02-03 14:51:52 +0200785 context->txfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG);
786 context->rxfmtctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG);
787 context->txfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_TXFMT_REG);
788 context->rxfmt = mcasp_get_reg(mcasp, DAVINCI_MCASP_RXFMT_REG);
789 context->aclkxctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG);
790 context->aclkrctl = mcasp_get_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG);
791 context->pdir = mcasp_get_reg(mcasp, DAVINCI_MCASP_PDIR_REG);
Peter Ujfalusi135014a2014-01-30 15:21:32 +0200792
793 return 0;
794}
795
796static int davinci_mcasp_resume(struct snd_soc_dai *dai)
797{
798 struct davinci_mcasp *mcasp = snd_soc_dai_get_drvdata(dai);
Peter Ujfalusi790bb942014-02-03 14:51:52 +0200799 struct davinci_mcasp_context *context = &mcasp->context;
Peter Ujfalusi135014a2014-01-30 15:21:32 +0200800
Peter Ujfalusi790bb942014-02-03 14:51:52 +0200801 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMCTL_REG, context->txfmtctl);
802 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMCTL_REG, context->rxfmtctl);
803 mcasp_set_reg(mcasp, DAVINCI_MCASP_TXFMT_REG, context->txfmt);
804 mcasp_set_reg(mcasp, DAVINCI_MCASP_RXFMT_REG, context->rxfmt);
805 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKXCTL_REG, context->aclkxctl);
806 mcasp_set_reg(mcasp, DAVINCI_MCASP_ACLKRCTL_REG, context->aclkrctl);
807 mcasp_set_reg(mcasp, DAVINCI_MCASP_PDIR_REG, context->pdir);
Peter Ujfalusi135014a2014-01-30 15:21:32 +0200808
809 return 0;
810}
811#else
812#define davinci_mcasp_suspend NULL
813#define davinci_mcasp_resume NULL
814#endif
815
Peter Ujfalusied29cd52013-11-14 11:35:22 +0200816#define DAVINCI_MCASP_RATES SNDRV_PCM_RATE_8000_192000
817
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400818#define DAVINCI_MCASP_PCM_FMTS (SNDRV_PCM_FMTBIT_S8 | \
819 SNDRV_PCM_FMTBIT_U8 | \
820 SNDRV_PCM_FMTBIT_S16_LE | \
821 SNDRV_PCM_FMTBIT_U16_LE | \
Daniel Mack21eb24d2012-10-09 09:35:16 +0200822 SNDRV_PCM_FMTBIT_S24_LE | \
823 SNDRV_PCM_FMTBIT_U24_LE | \
824 SNDRV_PCM_FMTBIT_S24_3LE | \
825 SNDRV_PCM_FMTBIT_U24_3LE | \
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400826 SNDRV_PCM_FMTBIT_S32_LE | \
827 SNDRV_PCM_FMTBIT_U32_LE)
828
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000829static struct snd_soc_dai_driver davinci_mcasp_dai[] = {
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400830 {
Liam Girdwoodf0fba2a2010-03-17 20:15:21 +0000831 .name = "davinci-mcasp.0",
Peter Ujfalusid5902f62014-04-01 15:55:07 +0300832 .probe = davinci_mcasp_dai_probe,
Peter Ujfalusi135014a2014-01-30 15:21:32 +0200833 .suspend = davinci_mcasp_suspend,
834 .resume = davinci_mcasp_resume,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400835 .playback = {
836 .channels_min = 2,
Michal Bachraty2952b272013-02-28 16:07:08 +0100837 .channels_max = 32 * 16,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400838 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400839 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400840 },
841 .capture = {
842 .channels_min = 2,
Michal Bachraty2952b272013-02-28 16:07:08 +0100843 .channels_max = 32 * 16,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400844 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400845 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400846 },
847 .ops = &davinci_mcasp_dai_ops,
848
849 },
850 {
Peter Ujfalusi58e48d92013-11-14 11:35:24 +0200851 .name = "davinci-mcasp.1",
Peter Ujfalusid5902f62014-04-01 15:55:07 +0300852 .probe = davinci_mcasp_dai_probe,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400853 .playback = {
854 .channels_min = 1,
855 .channels_max = 384,
856 .rates = DAVINCI_MCASP_RATES,
Ben Gardiner0a9d1382011-08-26 12:02:44 -0400857 .formats = DAVINCI_MCASP_PCM_FMTS,
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400858 },
859 .ops = &davinci_mcasp_dai_ops,
860 },
861
862};
Chaithrika U Sb67f4482009-06-05 06:28:40 -0400863
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -0700864static const struct snd_soc_component_driver davinci_mcasp_component = {
865 .name = "davinci-mcasp",
866};
867
Jyri Sarha256ba182013-10-18 18:37:42 +0300868/* Some HW specific values and defaults. The rest is filled in from DT. */
Peter Ujfalusid1debaf2014-02-03 14:51:51 +0200869static struct davinci_mcasp_pdata dm646x_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +0300870 .tx_dma_offset = 0x400,
871 .rx_dma_offset = 0x400,
872 .asp_chan_q = EVENTQ_0,
873 .version = MCASP_VERSION_1,
874};
875
Peter Ujfalusid1debaf2014-02-03 14:51:51 +0200876static struct davinci_mcasp_pdata da830_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +0300877 .tx_dma_offset = 0x2000,
878 .rx_dma_offset = 0x2000,
879 .asp_chan_q = EVENTQ_0,
880 .version = MCASP_VERSION_2,
881};
882
Peter Ujfalusid1debaf2014-02-03 14:51:51 +0200883static struct davinci_mcasp_pdata am33xx_mcasp_pdata = {
Jyri Sarha256ba182013-10-18 18:37:42 +0300884 .tx_dma_offset = 0,
885 .rx_dma_offset = 0,
886 .asp_chan_q = EVENTQ_0,
887 .version = MCASP_VERSION_3,
888};
889
Peter Ujfalusid1debaf2014-02-03 14:51:51 +0200890static struct davinci_mcasp_pdata dra7_mcasp_pdata = {
Peter Ujfalusi453c4992013-11-14 11:35:34 +0200891 .tx_dma_offset = 0x200,
892 .rx_dma_offset = 0x284,
893 .asp_chan_q = EVENTQ_0,
894 .version = MCASP_VERSION_4,
895};
896
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530897static const struct of_device_id mcasp_dt_ids[] = {
898 {
899 .compatible = "ti,dm646x-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +0300900 .data = &dm646x_mcasp_pdata,
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530901 },
902 {
903 .compatible = "ti,da830-mcasp-audio",
Jyri Sarha256ba182013-10-18 18:37:42 +0300904 .data = &da830_mcasp_pdata,
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530905 },
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530906 {
Jyri Sarha3af9e032013-10-18 18:37:44 +0300907 .compatible = "ti,am33xx-mcasp-audio",
Peter Ujfalusib14899d2013-11-14 11:35:37 +0200908 .data = &am33xx_mcasp_pdata,
Hebbar, Gururajae5ec69d2012-09-03 13:40:40 +0530909 },
Peter Ujfalusi453c4992013-11-14 11:35:34 +0200910 {
911 .compatible = "ti,dra7-mcasp-audio",
912 .data = &dra7_mcasp_pdata,
913 },
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530914 { /* sentinel */ }
915};
916MODULE_DEVICE_TABLE(of, mcasp_dt_ids);
917
Peter Ujfalusiae726e92013-11-14 11:35:35 +0200918static int mcasp_reparent_fck(struct platform_device *pdev)
919{
920 struct device_node *node = pdev->dev.of_node;
921 struct clk *gfclk, *parent_clk;
922 const char *parent_name;
923 int ret;
924
925 if (!node)
926 return 0;
927
928 parent_name = of_get_property(node, "fck_parent", NULL);
929 if (!parent_name)
930 return 0;
931
932 gfclk = clk_get(&pdev->dev, "fck");
933 if (IS_ERR(gfclk)) {
934 dev_err(&pdev->dev, "failed to get fck\n");
935 return PTR_ERR(gfclk);
936 }
937
938 parent_clk = clk_get(NULL, parent_name);
939 if (IS_ERR(parent_clk)) {
940 dev_err(&pdev->dev, "failed to get parent clock\n");
941 ret = PTR_ERR(parent_clk);
942 goto err1;
943 }
944
945 ret = clk_set_parent(gfclk, parent_clk);
946 if (ret) {
947 dev_err(&pdev->dev, "failed to reparent fck\n");
948 goto err2;
949 }
950
951err2:
952 clk_put(parent_clk);
953err1:
954 clk_put(gfclk);
955 return ret;
956}
957
Peter Ujfalusid1debaf2014-02-03 14:51:51 +0200958static struct davinci_mcasp_pdata *davinci_mcasp_set_pdata_from_of(
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530959 struct platform_device *pdev)
960{
961 struct device_node *np = pdev->dev.of_node;
Peter Ujfalusid1debaf2014-02-03 14:51:51 +0200962 struct davinci_mcasp_pdata *pdata = NULL;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530963 const struct of_device_id *match =
Sachin Kamatea421eb2013-05-22 16:53:37 +0530964 of_match_device(mcasp_dt_ids, &pdev->dev);
Jyri Sarha4023fe62013-10-18 18:37:43 +0300965 struct of_phandle_args dma_spec;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530966
967 const u32 *of_serial_dir32;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530968 u32 val;
969 int i, ret = 0;
970
971 if (pdev->dev.platform_data) {
972 pdata = pdev->dev.platform_data;
973 return pdata;
974 } else if (match) {
Peter Ujfalusid1debaf2014-02-03 14:51:51 +0200975 pdata = (struct davinci_mcasp_pdata*) match->data;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530976 } else {
977 /* control shouldn't reach here. something is wrong */
978 ret = -EINVAL;
979 goto nodata;
980 }
981
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530982 ret = of_property_read_u32(np, "op-mode", &val);
983 if (ret >= 0)
984 pdata->op_mode = val;
985
986 ret = of_property_read_u32(np, "tdm-slots", &val);
Michal Bachraty2952b272013-02-28 16:07:08 +0100987 if (ret >= 0) {
988 if (val < 2 || val > 32) {
989 dev_err(&pdev->dev,
990 "tdm-slots must be in rage [2-32]\n");
991 ret = -EINVAL;
992 goto nodata;
993 }
994
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530995 pdata->tdm_slots = val;
Michal Bachraty2952b272013-02-28 16:07:08 +0100996 }
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530997
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +0530998 of_serial_dir32 = of_get_property(np, "serial-dir", &val);
999 val /= sizeof(u32);
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301000 if (of_serial_dir32) {
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001001 u8 *of_serial_dir = devm_kzalloc(&pdev->dev,
1002 (sizeof(*of_serial_dir) * val),
1003 GFP_KERNEL);
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301004 if (!of_serial_dir) {
1005 ret = -ENOMEM;
1006 goto nodata;
1007 }
1008
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001009 for (i = 0; i < val; i++)
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301010 of_serial_dir[i] = be32_to_cpup(&of_serial_dir32[i]);
1011
Peter Ujfalusi1427e662013-10-18 18:37:46 +03001012 pdata->num_serializer = val;
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301013 pdata->serial_dir = of_serial_dir;
1014 }
1015
Jyri Sarha4023fe62013-10-18 18:37:43 +03001016 ret = of_property_match_string(np, "dma-names", "tx");
1017 if (ret < 0)
1018 goto nodata;
1019
1020 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1021 &dma_spec);
1022 if (ret < 0)
1023 goto nodata;
1024
1025 pdata->tx_dma_channel = dma_spec.args[0];
1026
1027 ret = of_property_match_string(np, "dma-names", "rx");
1028 if (ret < 0)
1029 goto nodata;
1030
1031 ret = of_parse_phandle_with_args(np, "dmas", "#dma-cells", ret,
1032 &dma_spec);
1033 if (ret < 0)
1034 goto nodata;
1035
1036 pdata->rx_dma_channel = dma_spec.args[0];
1037
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301038 ret = of_property_read_u32(np, "tx-num-evt", &val);
1039 if (ret >= 0)
1040 pdata->txnumevt = val;
1041
1042 ret = of_property_read_u32(np, "rx-num-evt", &val);
1043 if (ret >= 0)
1044 pdata->rxnumevt = val;
1045
1046 ret = of_property_read_u32(np, "sram-size-playback", &val);
1047 if (ret >= 0)
1048 pdata->sram_size_playback = val;
1049
1050 ret = of_property_read_u32(np, "sram-size-capture", &val);
1051 if (ret >= 0)
1052 pdata->sram_size_capture = val;
1053
1054 return pdata;
1055
1056nodata:
1057 if (ret < 0) {
1058 dev_err(&pdev->dev, "Error populating platform data, err %d\n",
1059 ret);
1060 pdata = NULL;
1061 }
1062 return pdata;
1063}
1064
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001065static int davinci_mcasp_probe(struct platform_device *pdev)
1066{
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001067 struct davinci_pcm_dma_params *dma_params;
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001068 struct snd_dmaengine_dai_dma_data *dma_data;
Jyri Sarha256ba182013-10-18 18:37:42 +03001069 struct resource *mem, *ioarea, *res, *dat;
Peter Ujfalusid1debaf2014-02-03 14:51:51 +02001070 struct davinci_mcasp_pdata *pdata;
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001071 struct davinci_mcasp *mcasp;
Julia Lawall96d31e22011-12-29 17:51:21 +01001072 int ret;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001073
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301074 if (!pdev->dev.platform_data && !pdev->dev.of_node) {
1075 dev_err(&pdev->dev, "No platform data supplied\n");
1076 return -EINVAL;
1077 }
1078
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001079 mcasp = devm_kzalloc(&pdev->dev, sizeof(struct davinci_mcasp),
Julia Lawall96d31e22011-12-29 17:51:21 +01001080 GFP_KERNEL);
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001081 if (!mcasp)
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001082 return -ENOMEM;
1083
Hebbar, Gururaja3e3b8c32012-08-27 18:56:42 +05301084 pdata = davinci_mcasp_set_pdata_from_of(pdev);
1085 if (!pdata) {
1086 dev_err(&pdev->dev, "no platform data\n");
1087 return -EINVAL;
1088 }
1089
Jyri Sarha256ba182013-10-18 18:37:42 +03001090 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "mpu");
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001091 if (!mem) {
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001092 dev_warn(mcasp->dev,
Jyri Sarha256ba182013-10-18 18:37:42 +03001093 "\"mpu\" mem resource not found, using index 0\n");
1094 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1095 if (!mem) {
1096 dev_err(&pdev->dev, "no mem resource?\n");
1097 return -ENODEV;
1098 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001099 }
1100
Julia Lawall96d31e22011-12-29 17:51:21 +01001101 ioarea = devm_request_mem_region(&pdev->dev, mem->start,
Vaibhav Bediad852f4462011-02-09 18:39:52 +05301102 resource_size(mem), pdev->name);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001103 if (!ioarea) {
1104 dev_err(&pdev->dev, "Audio region already claimed\n");
Julia Lawall96d31e22011-12-29 17:51:21 +01001105 return -EBUSY;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001106 }
1107
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301108 pm_runtime_enable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001109
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301110 ret = pm_runtime_get_sync(&pdev->dev);
1111 if (IS_ERR_VALUE(ret)) {
1112 dev_err(&pdev->dev, "pm_runtime_get_sync() failed\n");
1113 return ret;
1114 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001115
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001116 mcasp->base = devm_ioremap(&pdev->dev, mem->start, resource_size(mem));
1117 if (!mcasp->base) {
Vaibhav Bedia4f82f022011-02-09 18:39:54 +05301118 dev_err(&pdev->dev, "ioremap failed\n");
1119 ret = -ENOMEM;
1120 goto err_release_clk;
1121 }
1122
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001123 mcasp->op_mode = pdata->op_mode;
1124 mcasp->tdm_slots = pdata->tdm_slots;
1125 mcasp->num_serializer = pdata->num_serializer;
1126 mcasp->serial_dir = pdata->serial_dir;
1127 mcasp->version = pdata->version;
1128 mcasp->txnumevt = pdata->txnumevt;
1129 mcasp->rxnumevt = pdata->rxnumevt;
Peter Ujfalusi487dce82013-11-14 11:35:31 +02001130
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001131 mcasp->dev = &pdev->dev;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001132
Jyri Sarha256ba182013-10-18 18:37:42 +03001133 dat = platform_get_resource_byname(pdev, IORESOURCE_MEM, "dat");
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001134 if (dat)
1135 mcasp->dat_port = true;
Jyri Sarha256ba182013-10-18 18:37:42 +03001136
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001137 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_PLAYBACK];
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001138 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_PLAYBACK];
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001139 dma_params->asp_chan_q = pdata->asp_chan_q;
1140 dma_params->ram_chan_q = pdata->ram_chan_q;
1141 dma_params->sram_pool = pdata->sram_pool;
1142 dma_params->sram_size = pdata->sram_size_playback;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001143 if (dat)
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001144 dma_params->dma_addr = dat->start;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001145 else
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001146 dma_params->dma_addr = mem->start + pdata->tx_dma_offset;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001147
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001148 /* Unconditional dmaengine stuff */
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001149 dma_data->addr = dma_params->dma_addr;
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001150
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001151 res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001152 if (res)
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001153 dma_params->channel = res->start;
Jyri Sarha4023fe62013-10-18 18:37:43 +03001154 else
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001155 dma_params->channel = pdata->tx_dma_channel;
Troy Kisky92e2a6f2009-09-11 14:29:03 -07001156
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001157 /* dmaengine filter data for DT and non-DT boot */
1158 if (pdev->dev.of_node)
1159 dma_data->filter_data = "tx";
1160 else
1161 dma_data->filter_data = &dma_params->channel;
1162
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001163 dma_params = &mcasp->dma_params[SNDRV_PCM_STREAM_CAPTURE];
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001164 dma_data = &mcasp->dma_data[SNDRV_PCM_STREAM_CAPTURE];
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001165 dma_params->asp_chan_q = pdata->asp_chan_q;
1166 dma_params->ram_chan_q = pdata->ram_chan_q;
1167 dma_params->sram_pool = pdata->sram_pool;
1168 dma_params->sram_size = pdata->sram_size_capture;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001169 if (dat)
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001170 dma_params->dma_addr = dat->start;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001171 else
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001172 dma_params->dma_addr = mem->start + pdata->rx_dma_offset;
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001173
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001174 /* Unconditional dmaengine stuff */
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001175 dma_data->addr = dma_params->dma_addr;
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001176
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001177 if (mcasp->version < MCASP_VERSION_3) {
1178 mcasp->fifo_base = DAVINCI_MCASP_V2_AFIFO_BASE;
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001179 /* dma_params->dma_addr is pointing to the data port address */
Peter Ujfalusicbc7956c2013-11-14 11:35:32 +02001180 mcasp->dat_port = true;
1181 } else {
1182 mcasp->fifo_base = DAVINCI_MCASP_V3_AFIFO_BASE;
1183 }
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001184
1185 res = platform_get_resource(pdev, IORESOURCE_DMA, 1);
Jyri Sarha4023fe62013-10-18 18:37:43 +03001186 if (res)
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001187 dma_params->channel = res->start;
Jyri Sarha4023fe62013-10-18 18:37:43 +03001188 else
Peter Ujfalusi64ebdec2014-03-07 15:03:55 +02001189 dma_params->channel = pdata->rx_dma_channel;
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001190
Peter Ujfalusi8de131f2014-03-14 16:42:46 +02001191 /* dmaengine filter data for DT and non-DT boot */
1192 if (pdev->dev.of_node)
1193 dma_data->filter_data = "rx";
1194 else
1195 dma_data->filter_data = &dma_params->channel;
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001196
Peter Ujfalusi70091a32013-11-14 11:35:29 +02001197 dev_set_drvdata(&pdev->dev, mcasp);
Peter Ujfalusiae726e92013-11-14 11:35:35 +02001198
1199 mcasp_reparent_fck(pdev);
1200
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001201 ret = snd_soc_register_component(&pdev->dev, &davinci_mcasp_component,
1202 &davinci_mcasp_dai[pdata->op_mode], 1);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001203
1204 if (ret != 0)
Julia Lawall96d31e22011-12-29 17:51:21 +01001205 goto err_release_clk;
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301206
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001207 if (mcasp->version != MCASP_VERSION_4) {
1208 ret = davinci_soc_platform_register(&pdev->dev);
1209 if (ret) {
1210 dev_err(&pdev->dev, "register PCM failed: %d\n", ret);
1211 goto err_unregister_component;
1212 }
Hebbar, Gururajaf08095a2012-08-27 18:56:39 +05301213 }
1214
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001215 return 0;
1216
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001217err_unregister_component:
1218 snd_soc_unregister_component(&pdev->dev);
Vaibhav Bediaeef6d7b2011-02-09 18:39:53 +05301219err_release_clk:
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301220 pm_runtime_put_sync(&pdev->dev);
1221 pm_runtime_disable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001222 return ret;
1223}
1224
1225static int davinci_mcasp_remove(struct platform_device *pdev)
1226{
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001227 struct davinci_mcasp *mcasp = dev_get_drvdata(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001228
Kuninori Morimotoeeef0ed2013-03-21 03:31:19 -07001229 snd_soc_unregister_component(&pdev->dev);
Peter Ujfalusi453c4992013-11-14 11:35:34 +02001230 if (mcasp->version != MCASP_VERSION_4)
1231 davinci_soc_platform_unregister(&pdev->dev);
Hebbar, Gururaja10884342012-08-08 20:40:32 +05301232
1233 pm_runtime_put_sync(&pdev->dev);
1234 pm_runtime_disable(&pdev->dev);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001235
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001236 return 0;
1237}
1238
1239static struct platform_driver davinci_mcasp_driver = {
1240 .probe = davinci_mcasp_probe,
1241 .remove = davinci_mcasp_remove,
1242 .driver = {
1243 .name = "davinci-mcasp",
1244 .owner = THIS_MODULE,
Sachin Kamatea421eb2013-05-22 16:53:37 +05301245 .of_match_table = mcasp_dt_ids,
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001246 },
1247};
1248
Axel Linf9b8a512011-11-25 10:09:27 +08001249module_platform_driver(davinci_mcasp_driver);
Chaithrika U Sb67f4482009-06-05 06:28:40 -04001250
1251MODULE_AUTHOR("Steve Chen");
1252MODULE_DESCRIPTION("TI DAVINCI McASP SoC Interface");
1253MODULE_LICENSE("GPL");