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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * Driver for Motorola IMX serial ports
3 *
4 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
5 *
6 * Author: Sascha Hauer <sascha@saschahauer.de>
7 * Copyright (C) 2004 Pengutronix
8 *
Fabian Godehardtb6e49132009-06-11 14:53:18 +01009 * Copyright (C) 2009 emlix GmbH
10 * Author: Fabian Godehardt (added IrDA support for iMX)
11 *
Linus Torvalds1da177e2005-04-16 15:20:36 -070012 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 * [29-Mar-2005] Mike Lee
27 * Added hardware handshake
28 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070029
30#if defined(CONFIG_SERIAL_IMX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
31#define SUPPORT_SYSRQ
32#endif
33
34#include <linux/module.h>
35#include <linux/ioport.h>
36#include <linux/init.h>
37#include <linux/console.h>
38#include <linux/sysrq.h>
Russell Kingd052d1b2005-10-29 19:07:23 +010039#include <linux/platform_device.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070040#include <linux/tty.h>
41#include <linux/tty_flip.h>
42#include <linux/serial_core.h>
43#include <linux/serial.h>
Sascha Hauer38a41fd2008-07-05 10:02:46 +020044#include <linux/clk.h>
Fabian Godehardtb6e49132009-06-11 14:53:18 +010045#include <linux/delay.h>
Oskar Schirmer534fca02009-06-11 14:52:23 +010046#include <linux/rational.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090047#include <linux/slab.h>
Shawn Guo22698aa2011-06-25 02:04:34 +080048#include <linux/of.h>
49#include <linux/of_device.h>
Sachin Kamate32a9f82013-01-07 10:25:03 +053050#include <linux/io.h>
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080051#include <linux/dma-mapping.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070052
Linus Torvalds1da177e2005-04-16 15:20:36 -070053#include <asm/irq.h>
Arnd Bergmann82906b12012-08-24 15:14:29 +020054#include <linux/platform_data/serial-imx.h>
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080055#include <linux/platform_data/dma-imx.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070056
Sascha Hauerff4bfb22007-04-26 08:26:13 +010057/* Register definitions */
58#define URXD0 0x0 /* Receiver Register */
59#define URTX0 0x40 /* Transmitter Register */
60#define UCR1 0x80 /* Control Register 1 */
61#define UCR2 0x84 /* Control Register 2 */
62#define UCR3 0x88 /* Control Register 3 */
63#define UCR4 0x8c /* Control Register 4 */
64#define UFCR 0x90 /* FIFO Control Register */
65#define USR1 0x94 /* Status Register 1 */
66#define USR2 0x98 /* Status Register 2 */
67#define UESC 0x9c /* Escape Character Register */
68#define UTIM 0xa0 /* Escape Timer Register */
69#define UBIR 0xa4 /* BRM Incremental Register */
70#define UBMR 0xa8 /* BRM Modulator Register */
71#define UBRC 0xac /* Baud Rate Count Register */
Shawn Guofe6b5402011-06-25 02:04:33 +080072#define IMX21_ONEMS 0xb0 /* One Millisecond register */
73#define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
74#define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
Sascha Hauerff4bfb22007-04-26 08:26:13 +010075
76/* UART Control Register Bit Fields.*/
Jiada Wang55d86932014-12-09 18:11:22 +090077#define URXD_DUMMY_READ (1<<16)
Sachin Kamat82313e62013-01-07 10:25:02 +053078#define URXD_CHARRDY (1<<15)
79#define URXD_ERR (1<<14)
80#define URXD_OVRRUN (1<<13)
81#define URXD_FRMERR (1<<12)
82#define URXD_BRK (1<<11)
83#define URXD_PRERR (1<<10)
Dirk Behme26c47412014-09-03 12:33:53 +010084#define URXD_RX_DATA (0xFF<<0)
Sachin Kamat82313e62013-01-07 10:25:02 +053085#define UCR1_ADEN (1<<15) /* Auto detect interrupt */
86#define UCR1_ADBR (1<<14) /* Auto detect baud rate */
87#define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
88#define UCR1_IDEN (1<<12) /* Idle condition interrupt */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080089#define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
Sachin Kamat82313e62013-01-07 10:25:02 +053090#define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
91#define UCR1_RDMAEN (1<<8) /* Recv ready DMA enable */
92#define UCR1_IREN (1<<7) /* Infrared interface enable */
93#define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
94#define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
95#define UCR1_SNDBRK (1<<4) /* Send break */
96#define UCR1_TDMAEN (1<<3) /* Transmitter ready DMA enable */
97#define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +080098#define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
Sachin Kamat82313e62013-01-07 10:25:02 +053099#define UCR1_DOZE (1<<1) /* Doze */
100#define UCR1_UARTEN (1<<0) /* UART enabled */
101#define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
102#define UCR2_IRTS (1<<14) /* Ignore RTS pin */
103#define UCR2_CTSC (1<<13) /* CTS pin control */
104#define UCR2_CTS (1<<12) /* Clear to send */
105#define UCR2_ESCEN (1<<11) /* Escape enable */
106#define UCR2_PREN (1<<8) /* Parity enable */
107#define UCR2_PROE (1<<7) /* Parity odd/even */
108#define UCR2_STPB (1<<6) /* Stop */
109#define UCR2_WS (1<<5) /* Word size */
110#define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
111#define UCR2_ATEN (1<<3) /* Aging Timer Enable */
112#define UCR2_TXEN (1<<2) /* Transmitter enabled */
113#define UCR2_RXEN (1<<1) /* Receiver enabled */
114#define UCR2_SRST (1<<0) /* SW reset */
115#define UCR3_DTREN (1<<13) /* DTR interrupt enable */
116#define UCR3_PARERREN (1<<12) /* Parity enable */
117#define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
118#define UCR3_DSR (1<<10) /* Data set ready */
119#define UCR3_DCD (1<<9) /* Data carrier detect */
120#define UCR3_RI (1<<8) /* Ring indicator */
Fabio Estevamb38cb7d2014-05-14 15:55:03 -0300121#define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
Sachin Kamat82313e62013-01-07 10:25:02 +0530122#define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
123#define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
124#define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
125#define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
126#define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
127#define UCR3_BPEN (1<<0) /* Preset registers enable */
128#define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
129#define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
130#define UCR4_INVR (1<<9) /* Inverted infrared reception */
131#define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
132#define UCR4_WKEN (1<<7) /* Wake interrupt enable */
133#define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800134#define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
Sachin Kamat82313e62013-01-07 10:25:02 +0530135#define UCR4_IRSC (1<<5) /* IR special case */
136#define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
137#define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
138#define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
139#define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
140#define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
141#define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
142#define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
143#define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
144#define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
145#define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
146#define USR1_RTSS (1<<14) /* RTS pin status */
147#define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
148#define USR1_RTSD (1<<12) /* RTS delta */
149#define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
150#define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
151#define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
152#define USR1_TIMEOUT (1<<7) /* Receive timeout interrupt status */
153#define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
154#define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
155#define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
156#define USR2_ADET (1<<15) /* Auto baud rate detect complete */
157#define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
158#define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
159#define USR2_IDLE (1<<12) /* Idle condition */
160#define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
161#define USR2_WAKE (1<<7) /* Wake */
162#define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
163#define USR2_TXDC (1<<3) /* Transmitter complete */
164#define USR2_BRCD (1<<2) /* Break condition */
165#define USR2_ORE (1<<1) /* Overrun error */
166#define USR2_RDR (1<<0) /* Recv data ready */
167#define UTS_FRCPERR (1<<13) /* Force parity error */
168#define UTS_LOOP (1<<12) /* Loop tx and rx */
169#define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
170#define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
171#define UTS_TXFULL (1<<4) /* TxFIFO full */
172#define UTS_RXFULL (1<<3) /* RxFIFO full */
173#define UTS_SOFTRST (1<<0) /* Software reset */
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100174
Linus Torvalds1da177e2005-04-16 15:20:36 -0700175/* We've been assigned a range on the "Low-density serial ports" major */
Sachin Kamat82313e62013-01-07 10:25:02 +0530176#define SERIAL_IMX_MAJOR 207
177#define MINOR_START 16
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200178#define DEV_NAME "ttymxc"
Linus Torvalds1da177e2005-04-16 15:20:36 -0700179
Linus Torvalds1da177e2005-04-16 15:20:36 -0700180/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700181 * This determines how often we check the modem status signals
182 * for any change. They generally aren't connected to an IRQ
183 * so we have to poll them. We also check immediately before
184 * filling the TX fifo incase CTS has been dropped.
185 */
186#define MCTRL_TIMEOUT (250*HZ/1000)
187
188#define DRIVER_NAME "IMX-uart"
189
Sascha Hauerdbff4e92008-07-05 10:02:45 +0200190#define UART_NR 8
191
Shawn Guofe6b5402011-06-25 02:04:33 +0800192/* i.mx21 type uart runs on all i.mx except i.mx1 */
193enum imx_uart_type {
194 IMX1_UART,
195 IMX21_UART,
Huang Shijiea496e622013-07-08 17:14:17 +0800196 IMX6Q_UART,
Shawn Guofe6b5402011-06-25 02:04:33 +0800197};
198
199/* device type dependent stuff */
200struct imx_uart_data {
201 unsigned uts_reg;
202 enum imx_uart_type devtype;
203};
204
Linus Torvalds1da177e2005-04-16 15:20:36 -0700205struct imx_port {
206 struct uart_port port;
207 struct timer_list timer;
208 unsigned int old_status;
Sachin Kamat82313e62013-01-07 10:25:02 +0530209 int txirq, rxirq, rtsirq;
Daniel Glöckner26bbb3f2009-06-11 14:36:29 +0100210 unsigned int have_rtscts:1;
Huang Shijie20ff2fe2013-05-30 14:07:12 +0800211 unsigned int dte_mode:1;
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100212 unsigned int use_irda:1;
213 unsigned int irda_inv_rx:1;
214 unsigned int irda_inv_tx:1;
215 unsigned short trcv_delay; /* transceiver delay */
Sascha Hauer3a9465f2012-03-07 09:31:43 +0100216 struct clk *clk_ipg;
217 struct clk *clk_per;
Uwe Kleine-König7d0b0662012-05-21 21:57:39 +0200218 const struct imx_uart_data *devdata;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800219
220 /* DMA fields */
221 unsigned int dma_is_inited:1;
222 unsigned int dma_is_enabled:1;
223 unsigned int dma_is_rxing:1;
224 unsigned int dma_is_txing:1;
225 struct dma_chan *dma_chan_rx, *dma_chan_tx;
226 struct scatterlist rx_sgl, tx_sgl[2];
227 void *rx_buf;
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800228 unsigned int tx_bytes;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800229 unsigned int dma_tx_nents;
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700230 wait_queue_head_t dma_wait;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700231};
232
Dirk Behme0ad5a812011-12-22 09:57:52 +0100233struct imx_port_ucrs {
234 unsigned int ucr1;
235 unsigned int ucr2;
236 unsigned int ucr3;
237};
238
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100239#ifdef CONFIG_IRDA
240#define USE_IRDA(sport) ((sport)->use_irda)
241#else
242#define USE_IRDA(sport) (0)
243#endif
244
Shawn Guofe6b5402011-06-25 02:04:33 +0800245static struct imx_uart_data imx_uart_devdata[] = {
246 [IMX1_UART] = {
247 .uts_reg = IMX1_UTS,
248 .devtype = IMX1_UART,
249 },
250 [IMX21_UART] = {
251 .uts_reg = IMX21_UTS,
252 .devtype = IMX21_UART,
253 },
Huang Shijiea496e622013-07-08 17:14:17 +0800254 [IMX6Q_UART] = {
255 .uts_reg = IMX21_UTS,
256 .devtype = IMX6Q_UART,
257 },
Shawn Guofe6b5402011-06-25 02:04:33 +0800258};
259
260static struct platform_device_id imx_uart_devtype[] = {
261 {
262 .name = "imx1-uart",
263 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX1_UART],
264 }, {
265 .name = "imx21-uart",
266 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX21_UART],
267 }, {
Huang Shijiea496e622013-07-08 17:14:17 +0800268 .name = "imx6q-uart",
269 .driver_data = (kernel_ulong_t) &imx_uart_devdata[IMX6Q_UART],
270 }, {
Shawn Guofe6b5402011-06-25 02:04:33 +0800271 /* sentinel */
272 }
273};
274MODULE_DEVICE_TABLE(platform, imx_uart_devtype);
275
Shawn Guo22698aa2011-06-25 02:04:34 +0800276static struct of_device_id imx_uart_dt_ids[] = {
Huang Shijiea496e622013-07-08 17:14:17 +0800277 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
Shawn Guo22698aa2011-06-25 02:04:34 +0800278 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
279 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
280 { /* sentinel */ }
281};
282MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
283
Shawn Guofe6b5402011-06-25 02:04:33 +0800284static inline unsigned uts_reg(struct imx_port *sport)
285{
286 return sport->devdata->uts_reg;
287}
288
289static inline int is_imx1_uart(struct imx_port *sport)
290{
291 return sport->devdata->devtype == IMX1_UART;
292}
293
294static inline int is_imx21_uart(struct imx_port *sport)
295{
296 return sport->devdata->devtype == IMX21_UART;
297}
298
Huang Shijiea496e622013-07-08 17:14:17 +0800299static inline int is_imx6q_uart(struct imx_port *sport)
300{
301 return sport->devdata->devtype == IMX6Q_UART;
302}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700303/*
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200304 * Save and restore functions for UCR1, UCR2 and UCR3 registers
305 */
Fabio Estevam93d94b32014-11-12 15:55:07 -0200306#if defined(CONFIG_SERIAL_IMX_CONSOLE)
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200307static void imx_port_ucrs_save(struct uart_port *port,
308 struct imx_port_ucrs *ucr)
309{
310 /* save control registers */
311 ucr->ucr1 = readl(port->membase + UCR1);
312 ucr->ucr2 = readl(port->membase + UCR2);
313 ucr->ucr3 = readl(port->membase + UCR3);
314}
315
316static void imx_port_ucrs_restore(struct uart_port *port,
317 struct imx_port_ucrs *ucr)
318{
319 /* restore control registers */
320 writel(ucr->ucr1, port->membase + UCR1);
321 writel(ucr->ucr2, port->membase + UCR2);
322 writel(ucr->ucr3, port->membase + UCR3);
323}
Fabio Estevame8bfa762013-06-05 00:58:46 -0300324#endif
fabio.estevam@freescale.com44a75412013-02-06 19:00:02 -0200325
326/*
Linus Torvalds1da177e2005-04-16 15:20:36 -0700327 * Handle any change of modem status signal since we were last called.
328 */
329static void imx_mctrl_check(struct imx_port *sport)
330{
331 unsigned int status, changed;
332
333 status = sport->port.ops->get_mctrl(&sport->port);
334 changed = status ^ sport->old_status;
335
336 if (changed == 0)
337 return;
338
339 sport->old_status = status;
340
341 if (changed & TIOCM_RI)
342 sport->port.icount.rng++;
343 if (changed & TIOCM_DSR)
344 sport->port.icount.dsr++;
345 if (changed & TIOCM_CAR)
346 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
347 if (changed & TIOCM_CTS)
348 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
349
Alan Coxbdc04e32009-09-19 13:13:31 -0700350 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351}
352
353/*
354 * This is our per-port timeout handler, for checking the
355 * modem status signals.
356 */
357static void imx_timeout(unsigned long data)
358{
359 struct imx_port *sport = (struct imx_port *)data;
360 unsigned long flags;
361
Alan Coxebd2c8f2009-09-19 13:13:28 -0700362 if (sport->port.state) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700363 spin_lock_irqsave(&sport->port.lock, flags);
364 imx_mctrl_check(sport);
365 spin_unlock_irqrestore(&sport->port.lock, flags);
366
367 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
368 }
369}
370
371/*
372 * interrupts disabled on entry
373 */
Russell Kingb129a8c2005-08-31 10:12:14 +0100374static void imx_stop_tx(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700375{
376 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100377 unsigned long temp;
378
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100379 if (USE_IRDA(sport)) {
380 /* half duplex - wait for end of transmission */
381 int n = 256;
382 while ((--n > 0) &&
383 !(readl(sport->port.membase + USR2) & USR2_TXDC)) {
384 udelay(5);
385 barrier();
386 }
387 /*
388 * irda transceiver - wait a bit more to avoid
389 * cutoff, hardware dependent
390 */
391 udelay(sport->trcv_delay);
392
393 /*
394 * half duplex - reactivate receive mode,
395 * flush receive pipe echo crap
396 */
397 if (readl(sport->port.membase + USR2) & USR2_TXDC) {
398 temp = readl(sport->port.membase + UCR1);
399 temp &= ~(UCR1_TXMPTYEN | UCR1_TRDYEN);
400 writel(temp, sport->port.membase + UCR1);
401
402 temp = readl(sport->port.membase + UCR4);
403 temp &= ~(UCR4_TCEN);
404 writel(temp, sport->port.membase + UCR4);
405
406 while (readl(sport->port.membase + URXD0) &
407 URXD_CHARRDY)
408 barrier();
409
410 temp = readl(sport->port.membase + UCR1);
411 temp |= UCR1_RRDYEN;
412 writel(temp, sport->port.membase + UCR1);
413
414 temp = readl(sport->port.membase + UCR4);
415 temp |= UCR4_DREN;
416 writel(temp, sport->port.membase + UCR4);
417 }
418 return;
419 }
420
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700421 /*
422 * We are maybe in the SMP context, so if the DMA TX thread is running
423 * on other cpu, we have to wait for it to finish.
424 */
425 if (sport->dma_is_enabled && sport->dma_is_txing)
426 return;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800427
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100428 temp = readl(sport->port.membase + UCR1);
429 writel(temp & ~UCR1_TXMPTYEN, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700430}
431
432/*
433 * interrupts disabled on entry
434 */
435static void imx_stop_rx(struct uart_port *port)
436{
437 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100438 unsigned long temp;
439
Huang Shijie45564a62014-09-19 15:33:12 +0800440 if (sport->dma_is_enabled && sport->dma_is_rxing) {
441 if (sport->port.suspended) {
442 dmaengine_terminate_all(sport->dma_chan_rx);
443 sport->dma_is_rxing = 0;
444 } else {
445 return;
446 }
447 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800448
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100449 temp = readl(sport->port.membase + UCR2);
Sachin Kamat82313e62013-01-07 10:25:02 +0530450 writel(temp & ~UCR2_RXEN, sport->port.membase + UCR2);
Huang Shijie85878392014-05-23 12:32:54 +0800451
452 /* disable the `Receiver Ready Interrrupt` */
453 temp = readl(sport->port.membase + UCR1);
454 writel(temp & ~UCR1_RRDYEN, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455}
456
457/*
458 * Set the modem control timer to fire immediately.
459 */
460static void imx_enable_ms(struct uart_port *port)
461{
462 struct imx_port *sport = (struct imx_port *)port;
463
464 mod_timer(&sport->timer, jiffies);
465}
466
467static inline void imx_transmit_buffer(struct imx_port *sport)
468{
Alan Coxebd2c8f2009-09-19 13:13:28 -0700469 struct circ_buf *xmit = &sport->port.state->xmit;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700470
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400471 if (sport->port.x_char) {
472 /* Send next char */
473 writel(sport->port.x_char, sport->port.membase + URTX0);
474 return;
475 }
476
477 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
478 imx_stop_tx(&sport->port);
479 return;
480 }
481
Volker Ernst4e4e6602010-10-13 11:03:57 +0200482 while (!uart_circ_empty(xmit) &&
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400483 !(readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700484 /* send xmit->buf[xmit->tail]
485 * out the port here */
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100486 writel(xmit->buf[xmit->tail], sport->port.membase + URTX0);
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100487 xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700488 sport->port.icount.tx++;
Sascha Hauer8c0b2542007-02-05 16:10:16 -0800489 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700490
Fabian Godehardt977757312009-06-11 14:37:19 +0100491 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
492 uart_write_wakeup(&sport->port);
493
Linus Torvalds1da177e2005-04-16 15:20:36 -0700494 if (uart_circ_empty(xmit))
Russell Kingb129a8c2005-08-31 10:12:14 +0100495 imx_stop_tx(&sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700496}
497
Jiada Wang0bbc9b82014-12-09 18:11:30 +0900498static void imx_dma_tx(struct imx_port *sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800499static void dma_tx_callback(void *data)
500{
501 struct imx_port *sport = data;
502 struct scatterlist *sgl = &sport->tx_sgl[0];
503 struct circ_buf *xmit = &sport->port.state->xmit;
504 unsigned long flags;
Dirk Behmea2c718c2014-12-09 18:11:31 +0900505 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800506
Dirk Behme42f752b2014-12-09 18:11:28 +0900507 spin_lock_irqsave(&sport->port.lock, flags);
508
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800509 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
510
Dirk Behmea2c718c2014-12-09 18:11:31 +0900511 temp = readl(sport->port.membase + UCR1);
512 temp &= ~UCR1_TDMAEN;
513 writel(temp, sport->port.membase + UCR1);
514
Dirk Behme42f752b2014-12-09 18:11:28 +0900515 /* update the stat */
516 xmit->tail = (xmit->tail + sport->tx_bytes) & (UART_XMIT_SIZE - 1);
517 sport->port.icount.tx += sport->tx_bytes;
518
519 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
520
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800521 sport->dma_is_txing = 0;
522
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800523 spin_unlock_irqrestore(&sport->port.lock, flags);
524
Jiada Wangd64b8602014-12-09 18:11:29 +0900525 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
526 uart_write_wakeup(&sport->port);
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700527
528 if (waitqueue_active(&sport->dma_wait)) {
529 wake_up(&sport->dma_wait);
530 dev_dbg(sport->port.dev, "exit in %s.\n", __func__);
531 return;
532 }
Jiada Wang0bbc9b82014-12-09 18:11:30 +0900533
534 spin_lock_irqsave(&sport->port.lock, flags);
535 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
536 imx_dma_tx(sport);
537 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800538}
539
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800540static void imx_dma_tx(struct imx_port *sport)
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800541{
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800542 struct circ_buf *xmit = &sport->port.state->xmit;
543 struct scatterlist *sgl = sport->tx_sgl;
544 struct dma_async_tx_descriptor *desc;
545 struct dma_chan *chan = sport->dma_chan_tx;
546 struct device *dev = sport->port.dev;
Dirk Behmea2c718c2014-12-09 18:11:31 +0900547 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800548 int ret;
549
Dirk Behme42f752b2014-12-09 18:11:28 +0900550 if (sport->dma_is_txing)
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800551 return;
552
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800553 sport->tx_bytes = uart_circ_chars_pending(xmit);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800554
Dirk Behme7942f852014-12-09 18:11:25 +0900555 if (xmit->tail < xmit->head) {
556 sport->dma_tx_nents = 1;
557 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
558 } else {
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800559 sport->dma_tx_nents = 2;
560 sg_init_table(sgl, 2);
561 sg_set_buf(sgl, xmit->buf + xmit->tail,
562 UART_XMIT_SIZE - xmit->tail);
563 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800564 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800565
566 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
567 if (ret == 0) {
568 dev_err(dev, "DMA mapping error for TX.\n");
569 return;
570 }
571 desc = dmaengine_prep_slave_sg(chan, sgl, sport->dma_tx_nents,
572 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
573 if (!desc) {
Dirk Behme24649822014-12-09 18:11:26 +0900574 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
575 DMA_TO_DEVICE);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800576 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
577 return;
578 }
579 desc->callback = dma_tx_callback;
580 desc->callback_param = sport;
581
582 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
583 uart_circ_chars_pending(xmit));
Dirk Behmea2c718c2014-12-09 18:11:31 +0900584
585 temp = readl(sport->port.membase + UCR1);
586 temp |= UCR1_TDMAEN;
587 writel(temp, sport->port.membase + UCR1);
588
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800589 /* fire it */
590 sport->dma_is_txing = 1;
591 dmaengine_submit(desc);
592 dma_async_issue_pending(chan);
593 return;
594}
595
Linus Torvalds1da177e2005-04-16 15:20:36 -0700596/*
597 * interrupts disabled on entry
598 */
Russell Kingb129a8c2005-08-31 10:12:14 +0100599static void imx_start_tx(struct uart_port *port)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700600{
601 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100602 unsigned long temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700603
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100604 if (USE_IRDA(sport)) {
605 /* half duplex in IrDA mode; have to disable receive mode */
606 temp = readl(sport->port.membase + UCR4);
607 temp &= ~(UCR4_DREN);
608 writel(temp, sport->port.membase + UCR4);
609
610 temp = readl(sport->port.membase + UCR1);
611 temp &= ~(UCR1_RRDYEN);
612 writel(temp, sport->port.membase + UCR1);
613 }
614
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800615 if (!sport->dma_is_enabled) {
616 temp = readl(sport->port.membase + UCR1);
617 writel(temp | UCR1_TXMPTYEN, sport->port.membase + UCR1);
618 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700619
Fabian Godehardtb6e49132009-06-11 14:53:18 +0100620 if (USE_IRDA(sport)) {
621 temp = readl(sport->port.membase + UCR1);
622 temp |= UCR1_TRDYEN;
623 writel(temp, sport->port.membase + UCR1);
624
625 temp = readl(sport->port.membase + UCR4);
626 temp |= UCR4_TCEN;
627 writel(temp, sport->port.membase + UCR4);
628 }
629
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800630 if (sport->dma_is_enabled) {
Peter Hurley5e42e9a2014-09-02 17:39:12 -0400631 /* FIXME: port->x_char must be transmitted if != 0 */
632 if (!uart_circ_empty(&port->state->xmit) &&
633 !uart_tx_stopped(port))
634 imx_dma_tx(sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800635 return;
636 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700637}
638
David Howells7d12e782006-10-05 14:55:46 +0100639static irqreturn_t imx_rtsint(int irq, void *dev_id)
Sascha Hauerceca6292005-10-12 19:58:08 +0100640{
Jeff Garzik15aafa22008-02-06 01:36:20 -0800641 struct imx_port *sport = dev_id;
Uwe Kleine-König5680e942011-04-11 10:59:09 +0200642 unsigned int val;
Sascha Hauerceca6292005-10-12 19:58:08 +0100643 unsigned long flags;
644
645 spin_lock_irqsave(&sport->port.lock, flags);
646
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100647 writel(USR1_RTSD, sport->port.membase + USR1);
Uwe Kleine-König5680e942011-04-11 10:59:09 +0200648 val = readl(sport->port.membase + USR1) & USR1_RTSS;
Sascha Hauerceca6292005-10-12 19:58:08 +0100649 uart_handle_cts_change(&sport->port, !!val);
Alan Coxbdc04e32009-09-19 13:13:31 -0700650 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
Sascha Hauerceca6292005-10-12 19:58:08 +0100651
652 spin_unlock_irqrestore(&sport->port.lock, flags);
653 return IRQ_HANDLED;
654}
655
David Howells7d12e782006-10-05 14:55:46 +0100656static irqreturn_t imx_txint(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700657{
Jeff Garzik15aafa22008-02-06 01:36:20 -0800658 struct imx_port *sport = dev_id;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700659 unsigned long flags;
660
Sachin Kamat82313e62013-01-07 10:25:02 +0530661 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700662 imx_transmit_buffer(sport);
Sachin Kamat82313e62013-01-07 10:25:02 +0530663 spin_unlock_irqrestore(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700664 return IRQ_HANDLED;
665}
666
David Howells7d12e782006-10-05 14:55:46 +0100667static irqreturn_t imx_rxint(int irq, void *dev_id)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700668{
669 struct imx_port *sport = dev_id;
Sachin Kamat82313e62013-01-07 10:25:02 +0530670 unsigned int rx, flg, ignored = 0;
Jiri Slaby92a19f92013-01-03 15:53:03 +0100671 struct tty_port *port = &sport->port.state->port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100672 unsigned long flags, temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700673
Sachin Kamat82313e62013-01-07 10:25:02 +0530674 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700675
Sascha Hauer0d3c3932008-04-17 08:43:14 +0100676 while (readl(sport->port.membase + USR2) & USR2_RDR) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700677 flg = TTY_NORMAL;
678 sport->port.icount.rx++;
679
Sascha Hauer0d3c3932008-04-17 08:43:14 +0100680 rx = readl(sport->port.membase + URXD0);
681
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100682 temp = readl(sport->port.membase + USR2);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100683 if (temp & USR2_BRCD) {
Andy Green94d32f92010-02-01 13:28:54 +0100684 writel(USR2_BRCD, sport->port.membase + USR2);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100685 if (uart_handle_break(&sport->port))
686 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700687 }
688
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100689 if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx))
Sascha Hauer864eeed2008-04-17 08:39:22 +0100690 continue;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700691
Hui Wang019dc9e2011-08-24 17:41:47 +0800692 if (unlikely(rx & URXD_ERR)) {
693 if (rx & URXD_BRK)
694 sport->port.icount.brk++;
695 else if (rx & URXD_PRERR)
Sascha Hauer864eeed2008-04-17 08:39:22 +0100696 sport->port.icount.parity++;
697 else if (rx & URXD_FRMERR)
698 sport->port.icount.frame++;
699 if (rx & URXD_OVRRUN)
700 sport->port.icount.overrun++;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700701
Sascha Hauer864eeed2008-04-17 08:39:22 +0100702 if (rx & sport->port.ignore_status_mask) {
703 if (++ignored > 100)
704 goto out;
705 continue;
706 }
707
708 rx &= sport->port.read_status_mask;
709
Hui Wang019dc9e2011-08-24 17:41:47 +0800710 if (rx & URXD_BRK)
711 flg = TTY_BREAK;
712 else if (rx & URXD_PRERR)
Sascha Hauer864eeed2008-04-17 08:39:22 +0100713 flg = TTY_PARITY;
714 else if (rx & URXD_FRMERR)
715 flg = TTY_FRAME;
716 if (rx & URXD_OVRRUN)
717 flg = TTY_OVERRUN;
718
719#ifdef SUPPORT_SYSRQ
720 sport->port.sysrq = 0;
721#endif
722 }
723
Jiada Wang55d86932014-12-09 18:11:22 +0900724 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
725 goto out;
726
Jiri Slaby92a19f92013-01-03 15:53:03 +0100727 tty_insert_flip_char(port, rx, flg);
Sascha Hauer864eeed2008-04-17 08:39:22 +0100728 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700729
730out:
Sachin Kamat82313e62013-01-07 10:25:02 +0530731 spin_unlock_irqrestore(&sport->port.lock, flags);
Jiri Slaby2e124b42013-01-03 15:53:06 +0100732 tty_flip_buffer_push(port);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700733 return IRQ_HANDLED;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700734}
735
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800736static int start_rx_dma(struct imx_port *sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800737/*
738 * If the RXFIFO is filled with some data, and then we
739 * arise a DMA operation to receive them.
740 */
741static void imx_dma_rxint(struct imx_port *sport)
742{
743 unsigned long temp;
Jiada Wang73631812014-12-09 18:11:23 +0900744 unsigned long flags;
745
746 spin_lock_irqsave(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800747
748 temp = readl(sport->port.membase + USR2);
749 if ((temp & USR2_RDR) && !sport->dma_is_rxing) {
750 sport->dma_is_rxing = 1;
751
752 /* disable the `Recerver Ready Interrrupt` */
753 temp = readl(sport->port.membase + UCR1);
754 temp &= ~(UCR1_RRDYEN);
755 writel(temp, sport->port.membase + UCR1);
756
757 /* tell the DMA to receive the data. */
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800758 start_rx_dma(sport);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800759 }
Jiada Wang73631812014-12-09 18:11:23 +0900760
761 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800762}
763
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200764static irqreturn_t imx_int(int irq, void *dev_id)
765{
766 struct imx_port *sport = dev_id;
767 unsigned int sts;
Alexander Steinf1f836e2013-05-14 17:06:07 +0200768 unsigned int sts2;
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200769
770 sts = readl(sport->port.membase + USR1);
771
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800772 if (sts & USR1_RRDY) {
773 if (sport->dma_is_enabled)
774 imx_dma_rxint(sport);
775 else
776 imx_rxint(irq, dev_id);
777 }
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200778
779 if (sts & USR1_TRDY &&
780 readl(sport->port.membase + UCR1) & UCR1_TXMPTYEN)
781 imx_txint(irq, dev_id);
782
Marc Kleine-Budde9fbe6042008-07-28 21:26:01 +0200783 if (sts & USR1_RTSD)
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200784 imx_rtsint(irq, dev_id);
785
Fabio Estevamdb1a9b52011-12-13 01:23:48 -0200786 if (sts & USR1_AWAKE)
787 writel(USR1_AWAKE, sport->port.membase + USR1);
788
Alexander Steinf1f836e2013-05-14 17:06:07 +0200789 sts2 = readl(sport->port.membase + USR2);
790 if (sts2 & USR2_ORE) {
791 dev_err(sport->port.dev, "Rx FIFO overrun\n");
792 sport->port.icount.overrun++;
793 writel(sts2 | USR2_ORE, sport->port.membase + USR2);
794 }
795
Sascha Hauere3d13ff2008-07-05 10:02:48 +0200796 return IRQ_HANDLED;
797}
798
Linus Torvalds1da177e2005-04-16 15:20:36 -0700799/*
800 * Return TIOCSER_TEMT when transmitter is not busy.
801 */
802static unsigned int imx_tx_empty(struct uart_port *port)
803{
804 struct imx_port *sport = (struct imx_port *)port;
Huang Shijie1ce43e52013-10-11 18:30:59 +0800805 unsigned int ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700806
Huang Shijie1ce43e52013-10-11 18:30:59 +0800807 ret = (readl(sport->port.membase + USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
808
809 /* If the TX DMA is working, return 0. */
810 if (sport->dma_is_enabled && sport->dma_is_txing)
811 ret = 0;
812
813 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700814}
815
Sascha Hauer0f302dc2005-08-31 21:48:47 +0100816/*
817 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
818 */
Linus Torvalds1da177e2005-04-16 15:20:36 -0700819static unsigned int imx_get_mctrl(struct uart_port *port)
820{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100821 struct imx_port *sport = (struct imx_port *)port;
822 unsigned int tmp = TIOCM_DSR | TIOCM_CAR;
Sascha Hauer0f302dc2005-08-31 21:48:47 +0100823
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100824 if (readl(sport->port.membase + USR1) & USR1_RTSS)
825 tmp |= TIOCM_CTS;
Sascha Hauer0f302dc2005-08-31 21:48:47 +0100826
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100827 if (readl(sport->port.membase + UCR2) & UCR2_CTS)
828 tmp |= TIOCM_RTS;
Sascha Hauer0f302dc2005-08-31 21:48:47 +0100829
Huang Shijie6b471a92013-11-29 17:29:24 +0800830 if (readl(sport->port.membase + uts_reg(sport)) & UTS_LOOP)
831 tmp |= TIOCM_LOOP;
832
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100833 return tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700834}
835
836static void imx_set_mctrl(struct uart_port *port, unsigned int mctrl)
837{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100838 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100839 unsigned long temp;
840
Fugang Duanbb2f8612014-09-19 15:26:40 +0800841 temp = readl(sport->port.membase + UCR2) & ~(UCR2_CTS | UCR2_CTSC);
Oskar Schirmerd3810cd2009-06-11 14:35:01 +0100842 if (mctrl & TIOCM_RTS)
Fugang Duanbb2f8612014-09-19 15:26:40 +0800843 temp |= UCR2_CTS | UCR2_CTSC;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100844
845 writel(temp, sport->port.membase + UCR2);
Huang Shijie6b471a92013-11-29 17:29:24 +0800846
847 temp = readl(sport->port.membase + uts_reg(sport)) & ~UTS_LOOP;
848 if (mctrl & TIOCM_LOOP)
849 temp |= UTS_LOOP;
850 writel(temp, sport->port.membase + uts_reg(sport));
Linus Torvalds1da177e2005-04-16 15:20:36 -0700851}
852
853/*
854 * Interrupts always disabled.
855 */
856static void imx_break_ctl(struct uart_port *port, int break_state)
857{
858 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100859 unsigned long flags, temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700860
861 spin_lock_irqsave(&sport->port.lock, flags);
862
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100863 temp = readl(sport->port.membase + UCR1) & ~UCR1_SNDBRK;
864
Sachin Kamat82313e62013-01-07 10:25:02 +0530865 if (break_state != 0)
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100866 temp |= UCR1_SNDBRK;
867
868 writel(temp, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700869
870 spin_unlock_irqrestore(&sport->port.lock, flags);
871}
872
873#define TXTL 2 /* reset default */
874#define RXTL 1 /* reset default */
875
Sascha Hauer587897f2005-04-29 22:46:40 +0100876static int imx_setup_ufcr(struct imx_port *sport, unsigned int mode)
877{
878 unsigned int val;
Sascha Hauer587897f2005-04-29 22:46:40 +0100879
Dirk Behme7be06702012-08-31 10:02:47 +0200880 /* set receiver / transmitter trigger level */
881 val = readl(sport->port.membase + UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
882 val |= TXTL << UFCR_TXTL_SHF | RXTL;
Sascha Hauerff4bfb22007-04-26 08:26:13 +0100883 writel(val, sport->port.membase + UFCR);
Sascha Hauer587897f2005-04-29 22:46:40 +0100884 return 0;
885}
886
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800887#define RX_BUF_SIZE (PAGE_SIZE)
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800888static void imx_rx_dma_done(struct imx_port *sport)
889{
890 unsigned long temp;
Jiada Wang73631812014-12-09 18:11:23 +0900891 unsigned long flags;
892
893 spin_lock_irqsave(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800894
895 /* Enable this interrupt when the RXFIFO is empty. */
896 temp = readl(sport->port.membase + UCR1);
897 temp |= UCR1_RRDYEN;
898 writel(temp, sport->port.membase + UCR1);
899
900 sport->dma_is_rxing = 0;
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -0700901
902 /* Is the shutdown waiting for us? */
903 if (waitqueue_active(&sport->dma_wait))
904 wake_up(&sport->dma_wait);
Jiada Wang73631812014-12-09 18:11:23 +0900905
906 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800907}
908
909/*
910 * There are three kinds of RX DMA interrupts(such as in the MX6Q):
911 * [1] the RX DMA buffer is full.
912 * [2] the Aging timer expires(wait for 8 bytes long)
913 * [3] the Idle Condition Detect(enabled the UCR4_IDDMAEN).
914 *
915 * The [2] is trigger when a character was been sitting in the FIFO
916 * meanwhile [3] can wait for 32 bytes long when the RX line is
917 * on IDLE state and RxFIFO is empty.
918 */
919static void dma_rx_callback(void *data)
920{
921 struct imx_port *sport = data;
922 struct dma_chan *chan = sport->dma_chan_rx;
923 struct scatterlist *sgl = &sport->rx_sgl;
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800924 struct tty_port *port = &sport->port.state->port;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800925 struct dma_tx_state state;
926 enum dma_status status;
927 unsigned int count;
928
929 /* unmap it first */
930 dma_unmap_sg(sport->port.dev, sgl, 1, DMA_FROM_DEVICE);
931
Huang Shijief0ef8832013-10-11 18:31:01 +0800932 status = dmaengine_tx_status(chan, (dma_cookie_t)0, &state);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800933 count = RX_BUF_SIZE - state.residue;
934 dev_dbg(sport->port.dev, "We get %d bytes.\n", count);
935
936 if (count) {
Jiada Wang55d86932014-12-09 18:11:22 +0900937 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ))
938 tty_insert_flip_string(port, sport->rx_buf, count);
Huang Shijie7cb92fd2013-10-15 15:23:40 +0800939 tty_flip_buffer_push(port);
940
941 start_rx_dma(sport);
Robin Gongee5e7c12014-12-09 18:11:33 +0900942 } else if (readl(sport->port.membase + USR2) & USR2_RDR) {
943 /*
944 * start rx_dma directly once data in RXFIFO, more efficient
945 * than before:
946 * 1. call imx_rx_dma_done to stop dma if no data received
947 * 2. wait next RDR interrupt to start dma transfer.
948 */
949 start_rx_dma(sport);
950 } else {
951 /*
952 * stop dma to prevent too many IDLE event trigged if no data
953 * in RXFIFO
954 */
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800955 imx_rx_dma_done(sport);
Robin Gongee5e7c12014-12-09 18:11:33 +0900956 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800957}
958
959static int start_rx_dma(struct imx_port *sport)
960{
961 struct scatterlist *sgl = &sport->rx_sgl;
962 struct dma_chan *chan = sport->dma_chan_rx;
963 struct device *dev = sport->port.dev;
964 struct dma_async_tx_descriptor *desc;
965 int ret;
966
967 sg_init_one(sgl, sport->rx_buf, RX_BUF_SIZE);
968 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
969 if (ret == 0) {
970 dev_err(dev, "DMA mapping error for RX.\n");
971 return -EINVAL;
972 }
973 desc = dmaengine_prep_slave_sg(chan, sgl, 1, DMA_DEV_TO_MEM,
974 DMA_PREP_INTERRUPT);
975 if (!desc) {
Dirk Behme24649822014-12-09 18:11:26 +0900976 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +0800977 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
978 return -EINVAL;
979 }
980 desc->callback = dma_rx_callback;
981 desc->callback_param = sport;
982
983 dev_dbg(dev, "RX: prepare for the DMA.\n");
984 dmaengine_submit(desc);
985 dma_async_issue_pending(chan);
986 return 0;
987}
988
989static void imx_uart_dma_exit(struct imx_port *sport)
990{
991 if (sport->dma_chan_rx) {
992 dma_release_channel(sport->dma_chan_rx);
993 sport->dma_chan_rx = NULL;
994
995 kfree(sport->rx_buf);
996 sport->rx_buf = NULL;
997 }
998
999 if (sport->dma_chan_tx) {
1000 dma_release_channel(sport->dma_chan_tx);
1001 sport->dma_chan_tx = NULL;
1002 }
1003
1004 sport->dma_is_inited = 0;
1005}
1006
1007static int imx_uart_dma_init(struct imx_port *sport)
1008{
Huang Shijieb09c74a2013-08-29 16:29:25 +08001009 struct dma_slave_config slave_config = {};
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001010 struct device *dev = sport->port.dev;
1011 int ret;
1012
1013 /* Prepare for RX : */
1014 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1015 if (!sport->dma_chan_rx) {
1016 dev_dbg(dev, "cannot get the DMA channel.\n");
1017 ret = -EINVAL;
1018 goto err;
1019 }
1020
1021 slave_config.direction = DMA_DEV_TO_MEM;
1022 slave_config.src_addr = sport->port.mapbase + URXD0;
1023 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1024 slave_config.src_maxburst = RXTL;
1025 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1026 if (ret) {
1027 dev_err(dev, "error in RX dma configuration.\n");
1028 goto err;
1029 }
1030
1031 sport->rx_buf = kzalloc(PAGE_SIZE, GFP_KERNEL);
1032 if (!sport->rx_buf) {
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001033 ret = -ENOMEM;
1034 goto err;
1035 }
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001036
1037 /* Prepare for TX : */
1038 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1039 if (!sport->dma_chan_tx) {
1040 dev_err(dev, "cannot get the TX DMA channel!\n");
1041 ret = -EINVAL;
1042 goto err;
1043 }
1044
1045 slave_config.direction = DMA_MEM_TO_DEV;
1046 slave_config.dst_addr = sport->port.mapbase + URTX0;
1047 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1048 slave_config.dst_maxburst = TXTL;
1049 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1050 if (ret) {
1051 dev_err(dev, "error in TX dma configuration.");
1052 goto err;
1053 }
1054
1055 sport->dma_is_inited = 1;
1056
1057 return 0;
1058err:
1059 imx_uart_dma_exit(sport);
1060 return ret;
1061}
1062
1063static void imx_enable_dma(struct imx_port *sport)
1064{
1065 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001066
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -07001067 init_waitqueue_head(&sport->dma_wait);
1068
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001069 /* set UCR1 */
1070 temp = readl(sport->port.membase + UCR1);
1071 temp |= UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN |
1072 /* wait for 32 idle frames for IDDMA interrupt */
1073 UCR1_ICD_REG(3);
1074 writel(temp, sport->port.membase + UCR1);
1075
1076 /* set UCR4 */
1077 temp = readl(sport->port.membase + UCR4);
1078 temp |= UCR4_IDDMAEN;
1079 writel(temp, sport->port.membase + UCR4);
1080
1081 sport->dma_is_enabled = 1;
1082}
1083
1084static void imx_disable_dma(struct imx_port *sport)
1085{
1086 unsigned long temp;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001087
1088 /* clear UCR1 */
1089 temp = readl(sport->port.membase + UCR1);
1090 temp &= ~(UCR1_RDMAEN | UCR1_TDMAEN | UCR1_ATDMAEN);
1091 writel(temp, sport->port.membase + UCR1);
1092
1093 /* clear UCR2 */
1094 temp = readl(sport->port.membase + UCR2);
1095 temp &= ~(UCR2_CTSC | UCR2_CTS);
1096 writel(temp, sport->port.membase + UCR2);
1097
1098 /* clear UCR4 */
1099 temp = readl(sport->port.membase + UCR4);
1100 temp &= ~UCR4_IDDMAEN;
1101 writel(temp, sport->port.membase + UCR4);
1102
1103 sport->dma_is_enabled = 0;
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001104}
1105
Valentin Longchamp1c5250d2010-05-05 11:47:07 +02001106/* half the RX buffer size */
1107#define CTSTL 16
1108
Linus Torvalds1da177e2005-04-16 15:20:36 -07001109static int imx_startup(struct uart_port *port)
1110{
1111 struct imx_port *sport = (struct imx_port *)port;
Huang Shijie772f8992014-05-21 08:56:28 +08001112 int retval, i;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001113 unsigned long flags, temp;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001114
Huang Shijie1cf93e02013-06-28 13:39:42 +08001115 retval = clk_prepare_enable(sport->clk_per);
1116 if (retval)
Fabio Estevamcb0f0a52014-10-27 14:49:38 -02001117 return retval;
Huang Shijie1cf93e02013-06-28 13:39:42 +08001118 retval = clk_prepare_enable(sport->clk_ipg);
1119 if (retval) {
1120 clk_disable_unprepare(sport->clk_per);
Fabio Estevamcb0f0a52014-10-27 14:49:38 -02001121 return retval;
Huang Shijie0c375502013-06-09 10:01:19 +08001122 }
Huang Shijie28eb4272013-06-04 09:59:33 +08001123
Sascha Hauer587897f2005-04-29 22:46:40 +01001124 imx_setup_ufcr(sport, 0);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001125
1126 /* disable the DREN bit (Data Ready interrupt enable) before
1127 * requesting IRQs
1128 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001129 temp = readl(sport->port.membase + UCR4);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001130
1131 if (USE_IRDA(sport))
1132 temp |= UCR4_IRSC;
1133
Valentin Longchamp1c5250d2010-05-05 11:47:07 +02001134 /* set the trigger level for CTS */
Sachin Kamat82313e62013-01-07 10:25:02 +05301135 temp &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1136 temp |= CTSTL << UCR4_CTSTL_SHF;
Valentin Longchamp1c5250d2010-05-05 11:47:07 +02001137
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001138 writel(temp & ~UCR4_DREN, sport->port.membase + UCR4);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001139
Huang Shijie772f8992014-05-21 08:56:28 +08001140 /* Reset fifo's and state machines */
1141 i = 100;
1142
1143 temp = readl(sport->port.membase + UCR2);
1144 temp &= ~UCR2_SRST;
1145 writel(temp, sport->port.membase + UCR2);
1146
1147 while (!(readl(sport->port.membase + UCR2) & UCR2_SRST) && (--i > 0))
1148 udelay(1);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001149
Anton Bondarenko068500e2014-12-09 18:11:32 +09001150 /* Can we enable the DMA support? */
1151 if (is_imx6q_uart(sport) && !uart_console(port) &&
1152 !sport->dma_is_inited)
1153 imx_uart_dma_init(sport);
1154
Xinyu Chen9ec18822012-08-27 09:36:51 +02001155 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001156 /*
1157 * Finally, clear and enable interrupts
1158 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001159 writel(USR1_RTSD, sport->port.membase + USR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001160
Anton Bondarenko068500e2014-12-09 18:11:32 +09001161 if (sport->dma_is_inited && !sport->dma_is_enabled)
1162 imx_enable_dma(sport);
1163
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001164 temp = readl(sport->port.membase + UCR1);
Sascha Hauer789d5252008-04-17 08:44:47 +01001165 temp |= UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN;
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001166
1167 if (USE_IRDA(sport)) {
1168 temp |= UCR1_IREN;
1169 temp &= ~(UCR1_RTSDEN);
1170 }
1171
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001172 writel(temp, sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001173
Jiada Wang6f026d6b2014-12-09 18:11:34 +09001174 /* Clear any pending ORE flag before enabling interrupt */
1175 temp = readl(sport->port.membase + USR2);
1176 writel(temp | USR2_ORE, sport->port.membase + USR2);
1177
1178 temp = readl(sport->port.membase + UCR4);
1179 temp |= UCR4_OREN;
1180 writel(temp, sport->port.membase + UCR4);
1181
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001182 temp = readl(sport->port.membase + UCR2);
1183 temp |= (UCR2_RXEN | UCR2_TXEN);
Lucas Stachbff09b02013-05-30 15:47:04 +02001184 if (!sport->have_rtscts)
1185 temp |= UCR2_IRTS;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001186 writel(temp, sport->port.membase + UCR2);
1187
Huang Shijiea496e622013-07-08 17:14:17 +08001188 if (!is_imx1_uart(sport)) {
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001189 temp = readl(sport->port.membase + UCR3);
Fabio Estevamb38cb7d2014-05-14 15:55:03 -03001190 temp |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001191 writel(temp, sport->port.membase + UCR3);
1192 }
Marc Kleine-Budde44118052008-07-28 12:10:34 +02001193
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001194 if (USE_IRDA(sport)) {
1195 temp = readl(sport->port.membase + UCR4);
1196 if (sport->irda_inv_rx)
1197 temp |= UCR4_INVR;
1198 else
1199 temp &= ~(UCR4_INVR);
1200 writel(temp | UCR4_DREN, sport->port.membase + UCR4);
1201
1202 temp = readl(sport->port.membase + UCR3);
1203 if (sport->irda_inv_tx)
1204 temp |= UCR3_INVT;
1205 else
1206 temp &= ~(UCR3_INVT);
1207 writel(temp, sport->port.membase + UCR3);
1208 }
1209
Linus Torvalds1da177e2005-04-16 15:20:36 -07001210 /*
1211 * Enable modem status interrupts
1212 */
Linus Torvalds1da177e2005-04-16 15:20:36 -07001213 imx_enable_ms(&sport->port);
Sachin Kamat82313e62013-01-07 10:25:02 +05301214 spin_unlock_irqrestore(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001215
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001216 if (USE_IRDA(sport)) {
1217 struct imxuart_platform_data *pdata;
Jingoo Han574de552013-07-30 17:06:57 +09001218 pdata = dev_get_platdata(sport->port.dev);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001219 sport->irda_inv_rx = pdata->irda_inv_rx;
1220 sport->irda_inv_tx = pdata->irda_inv_tx;
1221 sport->trcv_delay = pdata->transceiver_delay;
1222 if (pdata->irda_enable)
1223 pdata->irda_enable(1);
1224 }
1225
Linus Torvalds1da177e2005-04-16 15:20:36 -07001226 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001227}
1228
1229static void imx_shutdown(struct uart_port *port)
1230{
1231 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001232 unsigned long temp;
Xinyu Chen9ec18822012-08-27 09:36:51 +02001233 unsigned long flags;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001234
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001235 if (sport->dma_is_enabled) {
Huang Shijiea4688bc2014-09-19 15:42:57 +08001236 int ret;
1237
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -07001238 /* We have to wait for the DMA to finish. */
Huang Shijiea4688bc2014-09-19 15:42:57 +08001239 ret = wait_event_interruptible(sport->dma_wait,
Greg Kroah-Hartman9ce4f8f2014-05-29 19:30:54 -07001240 !sport->dma_is_rxing && !sport->dma_is_txing);
Huang Shijiea4688bc2014-09-19 15:42:57 +08001241 if (ret != 0) {
1242 sport->dma_is_rxing = 0;
1243 sport->dma_is_txing = 0;
1244 dmaengine_terminate_all(sport->dma_chan_tx);
1245 dmaengine_terminate_all(sport->dma_chan_rx);
1246 }
Jiada Wang73631812014-12-09 18:11:23 +09001247 spin_lock_irqsave(&sport->port.lock, flags);
Huang Shijiea4688bc2014-09-19 15:42:57 +08001248 imx_stop_tx(port);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001249 imx_stop_rx(port);
1250 imx_disable_dma(sport);
Jiada Wang73631812014-12-09 18:11:23 +09001251 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijieb4cdc8f2013-07-08 17:14:18 +08001252 imx_uart_dma_exit(sport);
1253 }
1254
Xinyu Chen9ec18822012-08-27 09:36:51 +02001255 spin_lock_irqsave(&sport->port.lock, flags);
Fabian Godehardt2e146392009-06-11 14:38:38 +01001256 temp = readl(sport->port.membase + UCR2);
1257 temp &= ~(UCR2_TXEN);
1258 writel(temp, sport->port.membase + UCR2);
Xinyu Chen9ec18822012-08-27 09:36:51 +02001259 spin_unlock_irqrestore(&sport->port.lock, flags);
Fabian Godehardt2e146392009-06-11 14:38:38 +01001260
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001261 if (USE_IRDA(sport)) {
1262 struct imxuart_platform_data *pdata;
Jingoo Han574de552013-07-30 17:06:57 +09001263 pdata = dev_get_platdata(sport->port.dev);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001264 if (pdata->irda_enable)
1265 pdata->irda_enable(0);
1266 }
1267
Linus Torvalds1da177e2005-04-16 15:20:36 -07001268 /*
1269 * Stop our timer.
1270 */
1271 del_timer_sync(&sport->timer);
1272
1273 /*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001274 * Disable all interrupts, port and break condition.
1275 */
1276
Xinyu Chen9ec18822012-08-27 09:36:51 +02001277 spin_lock_irqsave(&sport->port.lock, flags);
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001278 temp = readl(sport->port.membase + UCR1);
1279 temp &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_UARTEN);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001280 if (USE_IRDA(sport))
1281 temp &= ~(UCR1_IREN);
1282
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001283 writel(temp, sport->port.membase + UCR1);
Xinyu Chen9ec18822012-08-27 09:36:51 +02001284 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijie28eb4272013-06-04 09:59:33 +08001285
Huang Shijie1cf93e02013-06-28 13:39:42 +08001286 clk_disable_unprepare(sport->clk_per);
1287 clk_disable_unprepare(sport->clk_ipg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001288}
1289
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001290static void imx_flush_buffer(struct uart_port *port)
1291{
1292 struct imx_port *sport = (struct imx_port *)port;
Dirk Behme82e86ae2014-12-09 18:11:27 +09001293 struct scatterlist *sgl = &sport->tx_sgl[0];
Dirk Behmea2c718c2014-12-09 18:11:31 +09001294 unsigned long temp;
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001295
Dirk Behme82e86ae2014-12-09 18:11:27 +09001296 if (!sport->dma_chan_tx)
1297 return;
1298
1299 sport->tx_bytes = 0;
1300 dmaengine_terminate_all(sport->dma_chan_tx);
1301 if (sport->dma_is_txing) {
1302 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1303 DMA_TO_DEVICE);
Dirk Behmea2c718c2014-12-09 18:11:31 +09001304 temp = readl(sport->port.membase + UCR1);
1305 temp &= ~UCR1_TDMAEN;
1306 writel(temp, sport->port.membase + UCR1);
Dirk Behme82e86ae2014-12-09 18:11:27 +09001307 sport->dma_is_txing = false;
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001308 }
1309}
1310
Linus Torvalds1da177e2005-04-16 15:20:36 -07001311static void
Alan Cox606d0992006-12-08 02:38:45 -08001312imx_set_termios(struct uart_port *port, struct ktermios *termios,
1313 struct ktermios *old)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001314{
1315 struct imx_port *sport = (struct imx_port *)port;
1316 unsigned long flags;
1317 unsigned int ucr2, old_ucr1, old_txrxen, baud, quot;
1318 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
Oskar Schirmer534fca02009-06-11 14:52:23 +01001319 unsigned int div, ufcr;
1320 unsigned long num, denom;
Oskar Schirmerd7f8d432009-06-11 14:55:22 +01001321 uint64_t tdiv64;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001322
1323 /*
1324 * If we don't support modem control lines, don't allow
1325 * these to be set.
1326 */
1327 if (0) {
1328 termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
1329 termios->c_cflag |= CLOCAL;
1330 }
1331
1332 /*
1333 * We only support CS7 and CS8.
1334 */
1335 while ((termios->c_cflag & CSIZE) != CS7 &&
1336 (termios->c_cflag & CSIZE) != CS8) {
1337 termios->c_cflag &= ~CSIZE;
1338 termios->c_cflag |= old_csize;
1339 old_csize = CS8;
1340 }
1341
1342 if ((termios->c_cflag & CSIZE) == CS8)
1343 ucr2 = UCR2_WS | UCR2_SRST | UCR2_IRTS;
1344 else
1345 ucr2 = UCR2_SRST | UCR2_IRTS;
1346
1347 if (termios->c_cflag & CRTSCTS) {
Sachin Kamat82313e62013-01-07 10:25:02 +05301348 if (sport->have_rtscts) {
Sascha Hauer5b802342006-05-04 14:07:42 +01001349 ucr2 &= ~UCR2_IRTS;
1350 ucr2 |= UCR2_CTSC;
1351 } else {
1352 termios->c_cflag &= ~CRTSCTS;
1353 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07001354 }
1355
1356 if (termios->c_cflag & CSTOPB)
1357 ucr2 |= UCR2_STPB;
1358 if (termios->c_cflag & PARENB) {
1359 ucr2 |= UCR2_PREN;
Matt Reimer3261e362006-01-13 20:51:44 +00001360 if (termios->c_cflag & PARODD)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001361 ucr2 |= UCR2_PROE;
1362 }
1363
Eric Miao995234d2011-12-23 05:39:27 +08001364 del_timer_sync(&sport->timer);
1365
Linus Torvalds1da177e2005-04-16 15:20:36 -07001366 /*
1367 * Ask the core to calculate the divisor for us.
1368 */
Sascha Hauer036bb152008-07-05 10:02:44 +02001369 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001370 quot = uart_get_divisor(port, baud);
1371
1372 spin_lock_irqsave(&sport->port.lock, flags);
1373
1374 sport->port.read_status_mask = 0;
1375 if (termios->c_iflag & INPCK)
1376 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1377 if (termios->c_iflag & (BRKINT | PARMRK))
1378 sport->port.read_status_mask |= URXD_BRK;
1379
1380 /*
1381 * Characters to ignore
1382 */
1383 sport->port.ignore_status_mask = 0;
1384 if (termios->c_iflag & IGNPAR)
1385 sport->port.ignore_status_mask |= URXD_PRERR;
1386 if (termios->c_iflag & IGNBRK) {
1387 sport->port.ignore_status_mask |= URXD_BRK;
1388 /*
1389 * If we're ignoring parity and break indicators,
1390 * ignore overruns too (for real raw support).
1391 */
1392 if (termios->c_iflag & IGNPAR)
1393 sport->port.ignore_status_mask |= URXD_OVRRUN;
1394 }
1395
Jiada Wang55d86932014-12-09 18:11:22 +09001396 if ((termios->c_cflag & CREAD) == 0)
1397 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1398
Linus Torvalds1da177e2005-04-16 15:20:36 -07001399 /*
1400 * Update the per-port timeout.
1401 */
1402 uart_update_timeout(port, termios->c_cflag, baud);
1403
1404 /*
1405 * disable interrupts and drain transmitter
1406 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001407 old_ucr1 = readl(sport->port.membase + UCR1);
1408 writel(old_ucr1 & ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN),
1409 sport->port.membase + UCR1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001410
Sachin Kamat82313e62013-01-07 10:25:02 +05301411 while (!(readl(sport->port.membase + USR2) & USR2_TXDC))
Linus Torvalds1da177e2005-04-16 15:20:36 -07001412 barrier();
1413
1414 /* then, disable everything */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001415 old_txrxen = readl(sport->port.membase + UCR2);
Sachin Kamat82313e62013-01-07 10:25:02 +05301416 writel(old_txrxen & ~(UCR2_TXEN | UCR2_RXEN),
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001417 sport->port.membase + UCR2);
1418 old_txrxen &= (UCR2_TXEN | UCR2_RXEN);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001419
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001420 if (USE_IRDA(sport)) {
1421 /*
1422 * use maximum available submodule frequency to
1423 * avoid missing short pulses due to low sampling rate
1424 */
Sascha Hauer036bb152008-07-05 10:02:44 +02001425 div = 1;
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001426 } else {
Hubert Feurstein09bd00f2013-07-18 18:52:49 +02001427 /* custom-baudrate handling */
1428 div = sport->port.uartclk / (baud * 16);
1429 if (baud == 38400 && quot != div)
1430 baud = sport->port.uartclk / (quot * 16);
1431
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001432 div = sport->port.uartclk / (baud * 16);
1433 if (div > 7)
1434 div = 7;
1435 if (!div)
1436 div = 1;
1437 }
Sascha Hauer036bb152008-07-05 10:02:44 +02001438
Oskar Schirmer534fca02009-06-11 14:52:23 +01001439 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1440 1 << 16, 1 << 16, &num, &denom);
Sascha Hauer036bb152008-07-05 10:02:44 +02001441
Alan Coxeab4f5a2010-06-01 22:52:52 +02001442 tdiv64 = sport->port.uartclk;
1443 tdiv64 *= num;
1444 do_div(tdiv64, denom * 16 * div);
1445 tty_termios_encode_baud_rate(termios,
Sascha Hauer1a2c4b32009-06-16 17:02:15 +01001446 (speed_t)tdiv64, (speed_t)tdiv64);
Oskar Schirmerd7f8d432009-06-11 14:55:22 +01001447
Oskar Schirmer534fca02009-06-11 14:52:23 +01001448 num -= 1;
1449 denom -= 1;
Sascha Hauer036bb152008-07-05 10:02:44 +02001450
1451 ufcr = readl(sport->port.membase + UFCR);
Fabian Godehardtb6e49132009-06-11 14:53:18 +01001452 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
Huang Shijie20ff2fe2013-05-30 14:07:12 +08001453 if (sport->dte_mode)
1454 ufcr |= UFCR_DCEDTE;
Sascha Hauer036bb152008-07-05 10:02:44 +02001455 writel(ufcr, sport->port.membase + UFCR);
1456
Oskar Schirmer534fca02009-06-11 14:52:23 +01001457 writel(num, sport->port.membase + UBIR);
1458 writel(denom, sport->port.membase + UBMR);
1459
Huang Shijiea496e622013-07-08 17:14:17 +08001460 if (!is_imx1_uart(sport))
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001461 writel(sport->port.uartclk / div / 1000,
Shawn Guofe6b5402011-06-25 02:04:33 +08001462 sport->port.membase + IMX21_ONEMS);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001463
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001464 writel(old_ucr1, sport->port.membase + UCR1);
1465
1466 /* set the parity, stop bits and data size */
1467 writel(ucr2 | old_txrxen, sport->port.membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001468
1469 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1470 imx_enable_ms(&sport->port);
1471
1472 spin_unlock_irqrestore(&sport->port.lock, flags);
1473}
1474
1475static const char *imx_type(struct uart_port *port)
1476{
1477 struct imx_port *sport = (struct imx_port *)port;
1478
1479 return sport->port.type == PORT_IMX ? "IMX" : NULL;
1480}
1481
1482/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07001483 * Configure/autoconfigure the port.
1484 */
1485static void imx_config_port(struct uart_port *port, int flags)
1486{
1487 struct imx_port *sport = (struct imx_port *)port;
1488
Alexander Shiyanda82f992014-02-22 16:01:33 +04001489 if (flags & UART_CONFIG_TYPE)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001490 sport->port.type = PORT_IMX;
1491}
1492
1493/*
1494 * Verify the new serial_struct (for TIOCSSERIAL).
1495 * The only change we allow are to the flags and type, and
1496 * even then only between PORT_IMX and PORT_UNKNOWN
1497 */
1498static int
1499imx_verify_port(struct uart_port *port, struct serial_struct *ser)
1500{
1501 struct imx_port *sport = (struct imx_port *)port;
1502 int ret = 0;
1503
1504 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1505 ret = -EINVAL;
1506 if (sport->port.irq != ser->irq)
1507 ret = -EINVAL;
1508 if (ser->io_type != UPIO_MEM)
1509 ret = -EINVAL;
1510 if (sport->port.uartclk / 16 != ser->baud_base)
1511 ret = -EINVAL;
Olof Johanssona50c44c2013-09-11 21:27:53 -07001512 if (sport->port.mapbase != (unsigned long)ser->iomem_base)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001513 ret = -EINVAL;
1514 if (sport->port.iobase != ser->port)
1515 ret = -EINVAL;
1516 if (ser->hub6 != 0)
1517 ret = -EINVAL;
1518 return ret;
1519}
1520
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001521#if defined(CONFIG_CONSOLE_POLL)
Daniel Thompson6b8bdad2014-10-28 09:28:08 +01001522
1523static int imx_poll_init(struct uart_port *port)
1524{
1525 struct imx_port *sport = (struct imx_port *)port;
1526 unsigned long flags;
1527 unsigned long temp;
1528 int retval;
1529
1530 retval = clk_prepare_enable(sport->clk_ipg);
1531 if (retval)
1532 return retval;
1533 retval = clk_prepare_enable(sport->clk_per);
1534 if (retval)
1535 clk_disable_unprepare(sport->clk_ipg);
1536
1537 imx_setup_ufcr(sport, 0);
1538
1539 spin_lock_irqsave(&sport->port.lock, flags);
1540
1541 temp = readl(sport->port.membase + UCR1);
1542 if (is_imx1_uart(sport))
1543 temp |= IMX1_UCR1_UARTCLKEN;
1544 temp |= UCR1_UARTEN | UCR1_RRDYEN;
1545 temp &= ~(UCR1_TXMPTYEN | UCR1_RTSDEN);
1546 writel(temp, sport->port.membase + UCR1);
1547
1548 temp = readl(sport->port.membase + UCR2);
1549 temp |= UCR2_RXEN;
1550 writel(temp, sport->port.membase + UCR2);
1551
1552 spin_unlock_irqrestore(&sport->port.lock, flags);
1553
1554 return 0;
1555}
1556
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001557static int imx_poll_get_char(struct uart_port *port)
1558{
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001559 if (!(readl_relaxed(port->membase + USR2) & USR2_RDR))
Dirk Behme26c47412014-09-03 12:33:53 +01001560 return NO_POLL_CHAR;
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001561
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001562 return readl_relaxed(port->membase + URXD0) & URXD_RX_DATA;
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001563}
1564
1565static void imx_poll_put_char(struct uart_port *port, unsigned char c)
1566{
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001567 unsigned int status;
1568
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001569 /* drain */
1570 do {
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001571 status = readl_relaxed(port->membase + USR1);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001572 } while (~status & USR1_TRDY);
1573
1574 /* write */
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001575 writel_relaxed(c, port->membase + URTX0);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001576
1577 /* flush */
1578 do {
Daniel Thompsonf968ef32014-10-28 09:28:07 +01001579 status = readl_relaxed(port->membase + USR2);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001580 } while (~status & USR2_TXDC);
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001581}
1582#endif
1583
Linus Torvalds1da177e2005-04-16 15:20:36 -07001584static struct uart_ops imx_pops = {
1585 .tx_empty = imx_tx_empty,
1586 .set_mctrl = imx_set_mctrl,
1587 .get_mctrl = imx_get_mctrl,
1588 .stop_tx = imx_stop_tx,
1589 .start_tx = imx_start_tx,
1590 .stop_rx = imx_stop_rx,
1591 .enable_ms = imx_enable_ms,
1592 .break_ctl = imx_break_ctl,
1593 .startup = imx_startup,
1594 .shutdown = imx_shutdown,
Huang Shijieeb56b7e2013-10-11 18:30:58 +08001595 .flush_buffer = imx_flush_buffer,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001596 .set_termios = imx_set_termios,
1597 .type = imx_type,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001598 .config_port = imx_config_port,
1599 .verify_port = imx_verify_port,
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001600#if defined(CONFIG_CONSOLE_POLL)
Daniel Thompson6b8bdad2014-10-28 09:28:08 +01001601 .poll_init = imx_poll_init,
Saleem Abdulrasool01f56ab2011-12-22 09:57:53 +01001602 .poll_get_char = imx_poll_get_char,
1603 .poll_put_char = imx_poll_put_char,
1604#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07001605};
1606
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001607static struct imx_port *imx_ports[UART_NR];
Linus Torvalds1da177e2005-04-16 15:20:36 -07001608
1609#ifdef CONFIG_SERIAL_IMX_CONSOLE
Russell Kingd3587882006-03-20 20:00:09 +00001610static void imx_console_putchar(struct uart_port *port, int ch)
1611{
1612 struct imx_port *sport = (struct imx_port *)port;
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001613
Shawn Guofe6b5402011-06-25 02:04:33 +08001614 while (readl(sport->port.membase + uts_reg(sport)) & UTS_TXFULL)
Russell Kingd3587882006-03-20 20:00:09 +00001615 barrier();
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001616
1617 writel(ch, sport->port.membase + URTX0);
Russell Kingd3587882006-03-20 20:00:09 +00001618}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001619
1620/*
1621 * Interrupts are disabled on entering
1622 */
1623static void
1624imx_console_write(struct console *co, const char *s, unsigned int count)
1625{
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001626 struct imx_port *sport = imx_ports[co->index];
Dirk Behme0ad5a812011-12-22 09:57:52 +01001627 struct imx_port_ucrs old_ucr;
1628 unsigned int ucr1;
Shawn Guof30e8262013-02-18 13:15:36 +08001629 unsigned long flags = 0;
Thomas Gleixner677fe552013-02-14 21:01:06 +01001630 int locked = 1;
Huang Shijie1cf93e02013-06-28 13:39:42 +08001631 int retval;
1632
1633 retval = clk_enable(sport->clk_per);
1634 if (retval)
1635 return;
1636 retval = clk_enable(sport->clk_ipg);
1637 if (retval) {
1638 clk_disable(sport->clk_per);
1639 return;
1640 }
Xinyu Chen9ec18822012-08-27 09:36:51 +02001641
Thomas Gleixner677fe552013-02-14 21:01:06 +01001642 if (sport->port.sysrq)
1643 locked = 0;
1644 else if (oops_in_progress)
1645 locked = spin_trylock_irqsave(&sport->port.lock, flags);
1646 else
1647 spin_lock_irqsave(&sport->port.lock, flags);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001648
1649 /*
Dirk Behme0ad5a812011-12-22 09:57:52 +01001650 * First, save UCR1/2/3 and then disable interrupts
Linus Torvalds1da177e2005-04-16 15:20:36 -07001651 */
Dirk Behme0ad5a812011-12-22 09:57:52 +01001652 imx_port_ucrs_save(&sport->port, &old_ucr);
1653 ucr1 = old_ucr.ucr1;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001654
Shawn Guofe6b5402011-06-25 02:04:33 +08001655 if (is_imx1_uart(sport))
1656 ucr1 |= IMX1_UCR1_UARTCLKEN;
Sascha Hauer37d6fb62009-05-27 18:23:48 +02001657 ucr1 |= UCR1_UARTEN;
1658 ucr1 &= ~(UCR1_TXMPTYEN | UCR1_RRDYEN | UCR1_RTSDEN);
1659
1660 writel(ucr1, sport->port.membase + UCR1);
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001661
Dirk Behme0ad5a812011-12-22 09:57:52 +01001662 writel(old_ucr.ucr2 | UCR2_TXEN, sport->port.membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001663
Russell Kingd3587882006-03-20 20:00:09 +00001664 uart_console_write(&sport->port, s, count, imx_console_putchar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001665
1666 /*
1667 * Finally, wait for transmitter to become empty
Dirk Behme0ad5a812011-12-22 09:57:52 +01001668 * and restore UCR1/2/3
Linus Torvalds1da177e2005-04-16 15:20:36 -07001669 */
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001670 while (!(readl(sport->port.membase + USR2) & USR2_TXDC));
Linus Torvalds1da177e2005-04-16 15:20:36 -07001671
Dirk Behme0ad5a812011-12-22 09:57:52 +01001672 imx_port_ucrs_restore(&sport->port, &old_ucr);
Xinyu Chen9ec18822012-08-27 09:36:51 +02001673
Thomas Gleixner677fe552013-02-14 21:01:06 +01001674 if (locked)
1675 spin_unlock_irqrestore(&sport->port.lock, flags);
Huang Shijie1cf93e02013-06-28 13:39:42 +08001676
1677 clk_disable(sport->clk_ipg);
1678 clk_disable(sport->clk_per);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001679}
1680
1681/*
1682 * If the port was already initialised (eg, by a boot loader),
1683 * try to determine the current setup.
1684 */
1685static void __init
1686imx_console_get_options(struct imx_port *sport, int *baud,
1687 int *parity, int *bits)
1688{
Sascha Hauer587897f2005-04-29 22:46:40 +01001689
Roel Kluin2e2eb502009-12-09 12:31:36 -08001690 if (readl(sport->port.membase + UCR1) & UCR1_UARTEN) {
Linus Torvalds1da177e2005-04-16 15:20:36 -07001691 /* ok, the port was enabled */
Sachin Kamat82313e62013-01-07 10:25:02 +05301692 unsigned int ucr2, ubir, ubmr, uartclk;
Sascha Hauer587897f2005-04-29 22:46:40 +01001693 unsigned int baud_raw;
1694 unsigned int ucfr_rfdiv;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001695
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001696 ucr2 = readl(sport->port.membase + UCR2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001697
1698 *parity = 'n';
1699 if (ucr2 & UCR2_PREN) {
1700 if (ucr2 & UCR2_PROE)
1701 *parity = 'o';
1702 else
1703 *parity = 'e';
1704 }
1705
1706 if (ucr2 & UCR2_WS)
1707 *bits = 8;
1708 else
1709 *bits = 7;
1710
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001711 ubir = readl(sport->port.membase + UBIR) & 0xffff;
1712 ubmr = readl(sport->port.membase + UBMR) & 0xffff;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001713
Sascha Hauerff4bfb22007-04-26 08:26:13 +01001714 ucfr_rfdiv = (readl(sport->port.membase + UFCR) & UFCR_RFDIV) >> 7;
Sascha Hauer587897f2005-04-29 22:46:40 +01001715 if (ucfr_rfdiv == 6)
1716 ucfr_rfdiv = 7;
1717 else
1718 ucfr_rfdiv = 6 - ucfr_rfdiv;
1719
Sascha Hauer3a9465f2012-03-07 09:31:43 +01001720 uartclk = clk_get_rate(sport->clk_per);
Sascha Hauer587897f2005-04-29 22:46:40 +01001721 uartclk /= ucfr_rfdiv;
1722
1723 { /*
1724 * The next code provides exact computation of
1725 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
1726 * without need of float support or long long division,
1727 * which would be required to prevent 32bit arithmetic overflow
1728 */
1729 unsigned int mul = ubir + 1;
1730 unsigned int div = 16 * (ubmr + 1);
1731 unsigned int rem = uartclk % div;
1732
1733 baud_raw = (uartclk / div) * mul;
1734 baud_raw += (rem * mul + div / 2) / div;
1735 *baud = (baud_raw + 50) / 100 * 100;
1736 }
1737
Sachin Kamat82313e62013-01-07 10:25:02 +05301738 if (*baud != baud_raw)
Sachin Kamat50bbdba2013-01-07 10:25:05 +05301739 pr_info("Console IMX rounded baud rate from %d to %d\n",
Sascha Hauer587897f2005-04-29 22:46:40 +01001740 baud_raw, *baud);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001741 }
1742}
1743
1744static int __init
1745imx_console_setup(struct console *co, char *options)
1746{
1747 struct imx_port *sport;
1748 int baud = 9600;
1749 int bits = 8;
1750 int parity = 'n';
1751 int flow = 'n';
Huang Shijie1cf93e02013-06-28 13:39:42 +08001752 int retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001753
1754 /*
1755 * Check whether an invalid uart number has been specified, and
1756 * if so, search for the first available port that does have
1757 * console support.
1758 */
1759 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_ports))
1760 co->index = 0;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001761 sport = imx_ports[co->index];
Sachin Kamat82313e62013-01-07 10:25:02 +05301762 if (sport == NULL)
Eric Lammertse76afc42009-05-19 20:53:20 -04001763 return -ENODEV;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001764
Huang Shijie1cf93e02013-06-28 13:39:42 +08001765 /* For setting the registers, we only need to enable the ipg clock. */
1766 retval = clk_prepare_enable(sport->clk_ipg);
1767 if (retval)
1768 goto error_console;
1769
Linus Torvalds1da177e2005-04-16 15:20:36 -07001770 if (options)
1771 uart_parse_options(options, &baud, &parity, &bits, &flow);
1772 else
1773 imx_console_get_options(sport, &baud, &parity, &bits);
1774
Sascha Hauer587897f2005-04-29 22:46:40 +01001775 imx_setup_ufcr(sport, 0);
1776
Huang Shijie1cf93e02013-06-28 13:39:42 +08001777 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
1778
1779 clk_disable(sport->clk_ipg);
1780 if (retval) {
1781 clk_unprepare(sport->clk_ipg);
1782 goto error_console;
1783 }
1784
1785 retval = clk_prepare(sport->clk_per);
1786 if (retval)
1787 clk_disable_unprepare(sport->clk_ipg);
1788
1789error_console:
1790 return retval;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001791}
1792
Vincent Sanders9f4426d2005-10-01 22:56:34 +01001793static struct uart_driver imx_reg;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001794static struct console imx_console = {
Sascha Hauere3d13ff2008-07-05 10:02:48 +02001795 .name = DEV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001796 .write = imx_console_write,
1797 .device = uart_console_device,
1798 .setup = imx_console_setup,
1799 .flags = CON_PRINTBUFFER,
1800 .index = -1,
1801 .data = &imx_reg,
1802};
1803
Linus Torvalds1da177e2005-04-16 15:20:36 -07001804#define IMX_CONSOLE &imx_console
1805#else
1806#define IMX_CONSOLE NULL
1807#endif
1808
1809static struct uart_driver imx_reg = {
1810 .owner = THIS_MODULE,
1811 .driver_name = DRIVER_NAME,
Sascha Hauere3d13ff2008-07-05 10:02:48 +02001812 .dev_name = DEV_NAME,
Linus Torvalds1da177e2005-04-16 15:20:36 -07001813 .major = SERIAL_IMX_MAJOR,
1814 .minor = MINOR_START,
1815 .nr = ARRAY_SIZE(imx_ports),
1816 .cons = IMX_CONSOLE,
1817};
1818
Russell King3ae5eae2005-11-09 22:32:44 +00001819static int serial_imx_suspend(struct platform_device *dev, pm_message_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001820{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001821 struct imx_port *sport = platform_get_drvdata(dev);
Fabio Estevamdb1a9b52011-12-13 01:23:48 -02001822 unsigned int val;
1823
1824 /* enable wakeup from i.MX UART */
1825 val = readl(sport->port.membase + UCR3);
1826 val |= UCR3_AWAKEN;
1827 writel(val, sport->port.membase + UCR3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001828
Richard Zhao034dc4d2012-09-18 16:14:59 +08001829 uart_suspend_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001830
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001831 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001832}
1833
Russell King3ae5eae2005-11-09 22:32:44 +00001834static int serial_imx_resume(struct platform_device *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001835{
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001836 struct imx_port *sport = platform_get_drvdata(dev);
Fabio Estevamdb1a9b52011-12-13 01:23:48 -02001837 unsigned int val;
1838
1839 /* disable wakeup from i.MX UART */
1840 val = readl(sport->port.membase + UCR3);
1841 val &= ~UCR3_AWAKEN;
1842 writel(val, sport->port.membase + UCR3);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001843
Richard Zhao034dc4d2012-09-18 16:14:59 +08001844 uart_resume_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001845
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01001846 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001847}
1848
Shawn Guo22698aa2011-06-25 02:04:34 +08001849#ifdef CONFIG_OF
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001850/*
1851 * This function returns 1 iff pdev isn't a device instatiated by dt, 0 iff it
1852 * could successfully get all information from dt or a negative errno.
1853 */
Shawn Guo22698aa2011-06-25 02:04:34 +08001854static int serial_imx_probe_dt(struct imx_port *sport,
1855 struct platform_device *pdev)
1856{
1857 struct device_node *np = pdev->dev.of_node;
1858 const struct of_device_id *of_id =
1859 of_match_device(imx_uart_dt_ids, &pdev->dev);
Shawn Guoff059672011-09-22 14:48:13 +08001860 int ret;
Shawn Guo22698aa2011-06-25 02:04:34 +08001861
1862 if (!np)
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001863 /* no device tree device */
1864 return 1;
Shawn Guo22698aa2011-06-25 02:04:34 +08001865
Shawn Guoff059672011-09-22 14:48:13 +08001866 ret = of_alias_get_id(np, "serial");
1867 if (ret < 0) {
1868 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
Uwe Kleine-Königa197a192011-12-14 21:26:51 +01001869 return ret;
Shawn Guoff059672011-09-22 14:48:13 +08001870 }
1871 sport->port.line = ret;
Shawn Guo22698aa2011-06-25 02:04:34 +08001872
1873 if (of_get_property(np, "fsl,uart-has-rtscts", NULL))
1874 sport->have_rtscts = 1;
1875
1876 if (of_get_property(np, "fsl,irda-mode", NULL))
1877 sport->use_irda = 1;
1878
Huang Shijie20ff2fe2013-05-30 14:07:12 +08001879 if (of_get_property(np, "fsl,dte-mode", NULL))
1880 sport->dte_mode = 1;
1881
Shawn Guo22698aa2011-06-25 02:04:34 +08001882 sport->devdata = of_id->data;
1883
1884 return 0;
1885}
1886#else
1887static inline int serial_imx_probe_dt(struct imx_port *sport,
1888 struct platform_device *pdev)
1889{
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001890 return 1;
Shawn Guo22698aa2011-06-25 02:04:34 +08001891}
1892#endif
1893
1894static void serial_imx_probe_pdata(struct imx_port *sport,
1895 struct platform_device *pdev)
1896{
Jingoo Han574de552013-07-30 17:06:57 +09001897 struct imxuart_platform_data *pdata = dev_get_platdata(&pdev->dev);
Shawn Guo22698aa2011-06-25 02:04:34 +08001898
1899 sport->port.line = pdev->id;
1900 sport->devdata = (struct imx_uart_data *) pdev->id_entry->driver_data;
1901
1902 if (!pdata)
1903 return;
1904
1905 if (pdata->flags & IMXUART_HAVE_RTSCTS)
1906 sport->have_rtscts = 1;
1907
1908 if (pdata->flags & IMXUART_IRDA)
1909 sport->use_irda = 1;
1910}
1911
Sascha Hauer2582d8c2008-07-05 10:02:45 +02001912static int serial_imx_probe(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001913{
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001914 struct imx_port *sport;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001915 void __iomem *base;
1916 int ret = 0;
1917 struct resource *res;
Sascha Hauer5b802342006-05-04 14:07:42 +01001918
Sachin Kamat42d34192013-01-07 10:25:06 +05301919 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001920 if (!sport)
1921 return -ENOMEM;
1922
Shawn Guo22698aa2011-06-25 02:04:34 +08001923 ret = serial_imx_probe_dt(sport, pdev);
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001924 if (ret > 0)
Shawn Guo22698aa2011-06-25 02:04:34 +08001925 serial_imx_probe_pdata(sport, pdev);
Uwe Kleine-König20bb8092011-12-15 09:16:34 +01001926 else if (ret < 0)
Sachin Kamat42d34192013-01-07 10:25:06 +05301927 return ret;
Shawn Guo22698aa2011-06-25 02:04:34 +08001928
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001929 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
Alexander Shiyanda82f992014-02-22 16:01:33 +04001930 base = devm_ioremap_resource(&pdev->dev, res);
1931 if (IS_ERR(base))
1932 return PTR_ERR(base);
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001933
1934 sport->port.dev = &pdev->dev;
1935 sport->port.mapbase = res->start;
1936 sport->port.membase = base;
1937 sport->port.type = PORT_IMX,
1938 sport->port.iotype = UPIO_MEM;
1939 sport->port.irq = platform_get_irq(pdev, 0);
1940 sport->rxirq = platform_get_irq(pdev, 0);
1941 sport->txirq = platform_get_irq(pdev, 1);
1942 sport->rtsirq = platform_get_irq(pdev, 2);
1943 sport->port.fifosize = 32;
1944 sport->port.ops = &imx_pops;
1945 sport->port.flags = UPF_BOOT_AUTOCONF;
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001946 init_timer(&sport->timer);
1947 sport->timer.function = imx_timeout;
1948 sport->timer.data = (unsigned long)sport;
Sascha Hauer38a41fd2008-07-05 10:02:46 +02001949
Sascha Hauer3a9465f2012-03-07 09:31:43 +01001950 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
1951 if (IS_ERR(sport->clk_ipg)) {
1952 ret = PTR_ERR(sport->clk_ipg);
Uwe Kleine-König833462e2012-08-20 09:57:04 +02001953 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
Sachin Kamat42d34192013-01-07 10:25:06 +05301954 return ret;
Sascha Hauer38a41fd2008-07-05 10:02:46 +02001955 }
Sascha Hauer38a41fd2008-07-05 10:02:46 +02001956
Sascha Hauer3a9465f2012-03-07 09:31:43 +01001957 sport->clk_per = devm_clk_get(&pdev->dev, "per");
1958 if (IS_ERR(sport->clk_per)) {
1959 ret = PTR_ERR(sport->clk_per);
Uwe Kleine-König833462e2012-08-20 09:57:04 +02001960 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
Sachin Kamat42d34192013-01-07 10:25:06 +05301961 return ret;
Sascha Hauer3a9465f2012-03-07 09:31:43 +01001962 }
1963
Sascha Hauer3a9465f2012-03-07 09:31:43 +01001964 sport->port.uartclk = clk_get_rate(sport->clk_per);
Sascha Hauerdbff4e92008-07-05 10:02:45 +02001965
Fabio Estevamc0d1c6b2014-10-27 14:49:37 -02001966 /*
1967 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
1968 * chips only have one interrupt.
1969 */
1970 if (sport->txirq > 0) {
1971 ret = devm_request_irq(&pdev->dev, sport->rxirq, imx_rxint, 0,
1972 dev_name(&pdev->dev), sport);
1973 if (ret)
1974 return ret;
1975
1976 ret = devm_request_irq(&pdev->dev, sport->txirq, imx_txint, 0,
1977 dev_name(&pdev->dev), sport);
1978 if (ret)
1979 return ret;
1980
1981 /* do not use RTS IRQ on IrDA */
1982 if (!USE_IRDA(sport)) {
1983 ret = devm_request_irq(&pdev->dev, sport->rtsirq,
1984 imx_rtsint, 0,
1985 dev_name(&pdev->dev), sport);
1986 if (ret)
1987 return ret;
1988 }
1989 } else {
1990 ret = devm_request_irq(&pdev->dev, sport->port.irq, imx_int, 0,
1991 dev_name(&pdev->dev), sport);
1992 if (ret)
1993 return ret;
1994 }
1995
Shawn Guo22698aa2011-06-25 02:04:34 +08001996 imx_ports[sport->port.line] = sport;
Sascha Hauer5b802342006-05-04 14:07:42 +01001997
Richard Zhao0a86a862012-09-18 16:14:58 +08001998 platform_set_drvdata(pdev, sport);
Sascha Hauer2582d8c2008-07-05 10:02:45 +02001999
Alexander Shiyan45af7802014-02-22 16:01:35 +04002000 return uart_add_one_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002001}
2002
Sascha Hauer2582d8c2008-07-05 10:02:45 +02002003static int serial_imx_remove(struct platform_device *pdev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002004{
Sascha Hauer2582d8c2008-07-05 10:02:45 +02002005 struct imx_port *sport = platform_get_drvdata(pdev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002006
Alexander Shiyan45af7802014-02-22 16:01:35 +04002007 return uart_remove_one_port(&imx_reg, &sport->port);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002008}
2009
Russell King3ae5eae2005-11-09 22:32:44 +00002010static struct platform_driver serial_imx_driver = {
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01002011 .probe = serial_imx_probe,
2012 .remove = serial_imx_remove,
Linus Torvalds1da177e2005-04-16 15:20:36 -07002013
2014 .suspend = serial_imx_suspend,
2015 .resume = serial_imx_resume,
Shawn Guofe6b5402011-06-25 02:04:33 +08002016 .id_table = imx_uart_devtype,
Russell King3ae5eae2005-11-09 22:32:44 +00002017 .driver = {
Oskar Schirmerd3810cd2009-06-11 14:35:01 +01002018 .name = "imx-uart",
Shawn Guo22698aa2011-06-25 02:04:34 +08002019 .of_match_table = imx_uart_dt_ids,
Russell King3ae5eae2005-11-09 22:32:44 +00002020 },
Linus Torvalds1da177e2005-04-16 15:20:36 -07002021};
2022
2023static int __init imx_serial_init(void)
2024{
Fabio Estevamf0fd1b72014-10-27 14:49:40 -02002025 int ret = uart_register_driver(&imx_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002026
Linus Torvalds1da177e2005-04-16 15:20:36 -07002027 if (ret)
2028 return ret;
2029
Russell King3ae5eae2005-11-09 22:32:44 +00002030 ret = platform_driver_register(&serial_imx_driver);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002031 if (ret != 0)
2032 uart_unregister_driver(&imx_reg);
2033
Uwe Kleine-Königf2278242011-11-22 14:22:55 +01002034 return ret;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002035}
2036
2037static void __exit imx_serial_exit(void)
2038{
Russell Kingc889b892005-11-21 17:05:21 +00002039 platform_driver_unregister(&serial_imx_driver);
Sascha Hauer4b300c32007-07-17 13:35:46 +01002040 uart_unregister_driver(&imx_reg);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002041}
2042
2043module_init(imx_serial_init);
2044module_exit(imx_serial_exit);
2045
2046MODULE_AUTHOR("Sascha Hauer");
2047MODULE_DESCRIPTION("IMX generic serial port driver");
2048MODULE_LICENSE("GPL");
Kay Sieverse169c132008-04-15 14:34:35 -07002049MODULE_ALIAS("platform:imx-uart");