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gerrit-public.fairphone.software / kernel / msm-4.9 / 77bf6f71a7e4e83a69b3785f2123c8e31f381a63 / . / arch / arm64 / boot / dts / qcom / sdm670-sde-display.dtsi
blob: a3f7b8e71393417b373153022bee78cfaf6f47db [file] [log] [blame]
Sandeep Panda91de3d82018-01-02 17:53:40 +0530[diff] [blame]1/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]2 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "dsi-panel-sim-video.dtsi"
14#include "dsi-panel-sim-cmd.dtsi"
15#include "dsi-panel-sim-dsc375-cmd.dtsi"
16#include "dsi-panel-sim-dualmipi-video.dtsi"
17#include "dsi-panel-sim-dualmipi-cmd.dtsi"
18#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
19#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
20#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
21#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi"
22#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi"
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]23#include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi"
24#include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi"
25#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
26#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
27#include "dsi-panel-rm67195-amoled-fhd-cmd.dtsi"
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame]28#include "dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi"
Yuan Zhaoccd2d3d2017-11-23 13:09:10 +0800[diff] [blame]29#include "dsi-panel-hx8399-truly-singlemipi-fhd-video.dtsi"
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]30#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
31
32&soc {
33 dsi_panel_pwr_supply: dsi_panel_pwr_supply {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 qcom,panel-supply-entry@0 {
38 reg = <0>;
39 qcom,supply-name = "vddio";
40 qcom,supply-min-voltage = <1800000>;
41 qcom,supply-max-voltage = <1800000>;
42 qcom,supply-enable-load = <62000>;
43 qcom,supply-disable-load = <80>;
44 qcom,supply-post-on-sleep = <20>;
45 };
46
47 qcom,panel-supply-entry@1 {
48 reg = <1>;
49 qcom,supply-name = "lab";
50 qcom,supply-min-voltage = <4600000>;
51 qcom,supply-max-voltage = <6000000>;
52 qcom,supply-enable-load = <100000>;
53 qcom,supply-disable-load = <100>;
54 };
55
56 qcom,panel-supply-entry@2 {
57 reg = <2>;
58 qcom,supply-name = "ibb";
59 qcom,supply-min-voltage = <4600000>;
60 qcom,supply-max-voltage = <6000000>;
61 qcom,supply-enable-load = <100000>;
62 qcom,supply-disable-load = <100>;
63 qcom,supply-post-on-sleep = <20>;
64 };
65 };
66
67 dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 qcom,panel-supply-entry@0 {
72 reg = <0>;
73 qcom,supply-name = "vddio";
74 qcom,supply-min-voltage = <1800000>;
75 qcom,supply-max-voltage = <1800000>;
76 qcom,supply-enable-load = <62000>;
77 qcom,supply-disable-load = <80>;
78 qcom,supply-post-on-sleep = <20>;
79 };
80 };
81
82 dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb {
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 qcom,panel-supply-entry@0 {
87 reg = <0>;
88 qcom,supply-name = "vddio";
89 qcom,supply-min-voltage = <1800000>;
90 qcom,supply-max-voltage = <1800000>;
91 qcom,supply-enable-load = <62000>;
92 qcom,supply-disable-load = <80>;
93 qcom,supply-post-on-sleep = <20>;
94 };
95
96 qcom,panel-supply-entry@1 {
97 reg = <1>;
98 qcom,supply-name = "vdd";
99 qcom,supply-min-voltage = <3000000>;
100 qcom,supply-max-voltage = <3000000>;
101 qcom,supply-enable-load = <857000>;
102 qcom,supply-disable-load = <0>;
103 qcom,supply-post-on-sleep = <0>;
104 };
105 };
106
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]107 dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {
108 #address-cells = <1>;
109 #size-cells = <0>;
110
111 qcom,panel-supply-entry@0 {
112 reg = <0>;
Vishnuvardhan Prodduturid5fb0802017-11-08 14:49:31 +0530[diff] [blame]113 qcom,supply-name = "vddio";
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]114 qcom,supply-min-voltage = <1800000>;
Vishnuvardhan Prodduturid5fb0802017-11-08 14:49:31 +0530[diff] [blame]115 qcom,supply-max-voltage = <1800000>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]116 qcom,supply-enable-load = <32000>;
117 qcom,supply-disable-load = <80>;
118 };
119
120 qcom,panel-supply-entry@1 {
121 reg = <1>;
122 qcom,supply-name = "vdda-3p3";
123 qcom,supply-min-voltage = <3300000>;
124 qcom,supply-max-voltage = <3300000>;
125 qcom,supply-enable-load = <13200>;
126 qcom,supply-disable-load = <80>;
127 };
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]128 };
129
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]130 dsi_dual_nt35597_truly_video_display: qcom,dsi-display@0 {
131 compatible = "qcom,dsi-display";
132 label = "dsi_dual_nt35597_truly_video_display";
133 qcom,display-type = "primary";
134
135 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
136 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
137 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
138 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
139 clock-names = "src_byte_clk", "src_pixel_clk";
140
141 pinctrl-names = "panel_active", "panel_suspend";
142 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
143 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
144 qcom,platform-reset-gpio = <&tlmm 75 0>;
145 qcom,panel-mode-gpio = <&tlmm 76 0>;
146
147 qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>;
148 vddio-supply = <&pm660_l11>;
149 lab-supply = <&lcdb_ldo_vreg>;
150 ibb-supply = <&lcdb_ncp_vreg>;
151 };
152
153 dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@1 {
154 compatible = "qcom,dsi-display";
155 label = "dsi_dual_nt35597_truly_cmd_display";
156 qcom,display-type = "primary";
157
158 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
159 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
160 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
161 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
162 clock-names = "src_byte_clk", "src_pixel_clk";
163
164 pinctrl-names = "panel_active", "panel_suspend";
165 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
166 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
167 qcom,platform-te-gpio = <&tlmm 10 0>;
168 qcom,platform-reset-gpio = <&tlmm 75 0>;
169 qcom,panel-mode-gpio = <&tlmm 76 0>;
170
171 qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>;
172 vddio-supply = <&pm660_l11>;
173 lab-supply = <&lcdb_ldo_vreg>;
174 ibb-supply = <&lcdb_ncp_vreg>;
175 };
176
177 dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@2 {
178 compatible = "qcom,dsi-display";
179 label = "dsi_nt35597_truly_dsc_cmd_display";
180 qcom,display-type = "primary";
181
182 qcom,dsi-ctrl = <&mdss_dsi1>;
183 qcom,dsi-phy = <&mdss_dsi_phy1>;
184 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
185 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
186 clock-names = "src_byte_clk", "src_pixel_clk";
187
188 pinctrl-names = "panel_active", "panel_suspend";
189 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
190 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
191 qcom,platform-te-gpio = <&tlmm 10 0>;
192 qcom,platform-reset-gpio = <&tlmm 75 0>;
193 qcom,panel-mode-gpio = <&tlmm 76 0>;
194
195 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>;
196 vddio-supply = <&pm660_l11>;
197 lab-supply = <&lcdb_ldo_vreg>;
198 ibb-supply = <&lcdb_ncp_vreg>;
199 };
200
201 dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@3 {
202 compatible = "qcom,dsi-display";
203 label = "dsi_nt35597_truly_dsc_video_display";
204 qcom,display-type = "primary";
205
206 qcom,dsi-ctrl = <&mdss_dsi1>;
207 qcom,dsi-phy = <&mdss_dsi_phy1>;
208 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
209 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
210 clock-names = "src_byte_clk", "src_pixel_clk";
211
212 pinctrl-names = "panel_active", "panel_suspend";
213 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
214 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
215 qcom,platform-te-gpio = <&tlmm 10 0>;
216 qcom,platform-reset-gpio = <&tlmm 75 0>;
217 qcom,panel-mode-gpio = <&tlmm 76 0>;
218
219 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>;
220 vddio-supply = <&pm660_l11>;
221 lab-supply = <&lcdb_ldo_vreg>;
222 ibb-supply = <&lcdb_ncp_vreg>;
223 };
224
225 dsi_sim_vid_display: qcom,dsi-display@4 {
226 compatible = "qcom,dsi-display";
227 label = "dsi_sim_vid_display";
228 qcom,display-type = "primary";
229
230 qcom,dsi-ctrl = <&mdss_dsi0>;
231 qcom,dsi-phy = <&mdss_dsi_phy0>;
232 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
233 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
234 clock-names = "src_byte_clk", "src_pixel_clk";
235
236 pinctrl-names = "panel_active", "panel_suspend";
237 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
238 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
239
240 qcom,dsi-panel = <&dsi_sim_vid>;
241 };
242
243 dsi_dual_sim_vid_display: qcom,dsi-display@5 {
244 compatible = "qcom,dsi-display";
245 label = "dsi_dual_sim_vid_display";
246 qcom,display-type = "primary";
247
248 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
249 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
250 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
251 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
252 clock-names = "src_byte_clk", "src_pixel_clk";
253
254 pinctrl-names = "panel_active", "panel_suspend";
255 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
256 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
257
258 qcom,dsi-panel = <&dsi_dual_sim_vid>;
259 };
260
261 dsi_sim_cmd_display: qcom,dsi-display@6 {
262 compatible = "qcom,dsi-display";
263 label = "dsi_sim_cmd_display";
264 qcom,display-type = "primary";
265
266 qcom,dsi-ctrl = <&mdss_dsi0>;
267 qcom,dsi-phy = <&mdss_dsi_phy0>;
268 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
269 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
270 clock-names = "src_byte_clk", "src_pixel_clk";
271
272 pinctrl-names = "panel_active", "panel_suspend";
273 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
274 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
275
276 qcom,dsi-panel = <&dsi_sim_cmd>;
277 };
278
279 dsi_dual_sim_cmd_display: qcom,dsi-display@7 {
280 compatible = "qcom,dsi-display";
281 label = "dsi_dual_sim_cmd_display";
282 qcom,display-type = "primary";
283
284 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
285 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
286 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
287 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
288 clock-names = "src_byte_clk", "src_pixel_clk";
289
290 pinctrl-names = "panel_active", "panel_suspend";
291 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
292 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
293
294 qcom,dsi-panel = <&dsi_dual_sim_cmd>;
295 };
296
297 dsi_sim_dsc_375_cmd_display: qcom,dsi-display@8 {
298 compatible = "qcom,dsi-display";
299 label = "dsi_sim_dsc_375_cmd_display";
300 qcom,display-type = "primary";
301
302 qcom,dsi-ctrl = <&mdss_dsi0>;
303 qcom,dsi-phy = <&mdss_dsi_phy0>;
304 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
305 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
306 clock-names = "src_byte_clk", "src_pixel_clk";
307
308 pinctrl-names = "panel_active", "panel_suspend";
309 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
310 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
311
312 qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>;
313 };
314
315 dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@9 {
316 compatible = "qcom,dsi-display";
317 label = "dsi_dual_sim_dsc_375_cmd_display";
318 qcom,display-type = "primary";
319
320 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
321 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
322 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
323 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
324 clock-names = "src_byte_clk", "src_pixel_clk";
325
326 pinctrl-names = "panel_active", "panel_suspend";
327 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
328 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
329
330 qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>;
331 };
332
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]333 dsi_dual_nt35597_video_display: qcom,dsi-display@10 {
334 compatible = "qcom,dsi-display";
335 label = "dsi_dual_nt35597_video_display";
336 qcom,display-type = "primary";
337
338 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
339 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
340 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
341 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
342 clock-names = "src_byte_clk", "src_pixel_clk";
343
344 pinctrl-names = "panel_active", "panel_suspend";
345 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
346 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
347 qcom,platform-reset-gpio = <&tlmm 75 0>;
348 qcom,panel-mode-gpio = <&tlmm 76 0>;
349
350 qcom,dsi-panel = <&dsi_dual_nt35597_video>;
351 vddio-supply = <&pm660_l11>;
352 lab-supply = <&lcdb_ldo_vreg>;
353 ibb-supply = <&lcdb_ncp_vreg>;
354 };
355
356 dsi_dual_nt35597_cmd_display: qcom,dsi-display@11 {
357 compatible = "qcom,dsi-display";
358 label = "dsi_dual_nt35597_cmd_display";
359 qcom,display-type = "primary";
360
361 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
362 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
363 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
364 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
365 clock-names = "src_byte_clk", "src_pixel_clk";
366
367 pinctrl-names = "panel_active", "panel_suspend";
368 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
369 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
370 qcom,platform-reset-gpio = <&tlmm 75 0>;
371 qcom,panel-mode-gpio = <&tlmm 76 0>;
372
373 qcom,dsi-panel = <&dsi_dual_nt35597_cmd>;
374 vddio-supply = <&pm660_l11>;
375 lab-supply = <&lcdb_ldo_vreg>;
376 ibb-supply = <&lcdb_ncp_vreg>;
377 };
378
379 dsi_rm67195_amoled_fhd_cmd_display: qcom,dsi-display@12 {
380 compatible = "qcom,dsi-display";
381 label = "dsi_rm67195_amoled_fhd_cmd_display";
382 qcom,display-type = "primary";
383
384 qcom,dsi-ctrl = <&mdss_dsi0>;
385 qcom,dsi-phy = <&mdss_dsi_phy0>;
386 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
387 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
388 clock-names = "src_byte_clk", "src_pixel_clk";
389
390 pinctrl-names = "panel_active", "panel_suspend";
391 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
392 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
393 qcom,platform-te-gpio = <&tlmm 10 0>;
394 qcom,platform-reset-gpio = <&tlmm 75 0>;
395
396 qcom,dsi-panel = <&dsi_rm67195_amoled_fhd_cmd>;
397 vddio-supply = <&pm660_l11>;
Vishnuvardhan Prodduturid5fb0802017-11-08 14:49:31 +0530[diff] [blame]398 vdda-3p3-supply = <&pm660l_l6>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]399 };
400
401 dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@13 {
402 compatible = "qcom,dsi-display";
403 label = "dsi_nt35695b_truly_fhd_video_display";
404 qcom,display-type = "primary";
405
406 qcom,dsi-ctrl = <&mdss_dsi0>;
407 qcom,dsi-phy = <&mdss_dsi_phy0>;
408 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
409 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
410 clock-names = "src_byte_clk", "src_pixel_clk";
411
412 pinctrl-names = "panel_active", "panel_suspend";
413 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
414 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
415 qcom,platform-reset-gpio = <&tlmm 75 0>;
416
417 qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>;
418 vddio-supply = <&pm660_l11>;
419 lab-supply = <&lcdb_ldo_vreg>;
420 ibb-supply = <&lcdb_ncp_vreg>;
421 };
422
423 dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@14 {
424 compatible = "qcom,dsi-display";
425 label = "dsi_nt35695b_truly_fhd_cmd_display";
426 qcom,display-type = "primary";
427
428 qcom,dsi-ctrl = <&mdss_dsi0>;
429 qcom,dsi-phy = <&mdss_dsi_phy0>;
430 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
431 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
432 clock-names = "src_byte_clk", "src_pixel_clk";
433
434 pinctrl-names = "panel_active", "panel_suspend";
435 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
436 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
437 qcom,platform-te-gpio = <&tlmm 10 0>;
438 qcom,platform-reset-gpio = <&tlmm 75 0>;
439
440 qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>;
441 vddio-supply = <&pm660_l11>;
442 lab-supply = <&lcdb_ldo_vreg>;
443 ibb-supply = <&lcdb_ncp_vreg>;
444 };
445
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame]446 dsi_dual_nt36850_truly_cmd_display: qcom,dsi-display@15 {
447 compatible = "qcom,dsi-display";
448 label = "dsi_dual_nt36850_truly_cmd_display";
449 qcom,display-type = "primary";
450
451 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
452 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
453 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
454 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
455 clock-names = "src_byte_clk", "src_pixel_clk";
456
457 pinctrl-names = "panel_active", "panel_suspend";
458 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
459 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
460 qcom,platform-te-gpio = <&tlmm 10 0>;
461 qcom,platform-reset-gpio = <&tlmm 75 0>;
462
463 qcom,dsi-panel = <&dsi_dual_nt36850_truly_cmd>;
464 vddio-supply = <&pm660_l11>;
465 lab-supply = <&lcdb_ldo_vreg>;
466 ibb-supply = <&lcdb_ncp_vreg>;
467 };
468
Yuan Zhaoccd2d3d2017-11-23 13:09:10 +0800[diff] [blame]469 dsi_hx8399_truly_cmd_display: qcom,dsi-display@16 {
470 compatible = "qcom,dsi-display";
471 label = "dsi_hx8399_truly_cmd_display";
472 qcom,display-type = "primary";
473
474 qcom,dsi-ctrl = <&mdss_dsi0>;
475 qcom,dsi-phy = <&mdss_dsi_phy0>;
476 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
477 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
478 clock-names = "src_byte_clk", "src_pixel_clk";
479
480 pinctrl-names = "panel_active", "panel_suspend";
481 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
482 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
483 qcom,platform-te-gpio = <&tlmm 10 0>;
484 qcom,platform-reset-gpio = <&tlmm 75 0>;
485
486 qcom,dsi-panel = <&dsi_hx8399_truly_cmd>;
487 vddio-supply = <&pm660_l11>;
488 lab-supply = <&lcdb_ldo_vreg>;
489 ibb-supply = <&lcdb_ncp_vreg>;
490 };
491
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]492 sde_wb: qcom,wb-display@0 {
493 compatible = "qcom,wb-display";
494 cell-index = <0>;
495 label = "wb_display";
496 };
497
498 ext_disp: qcom,msm-ext-disp {
499 compatible = "qcom,msm-ext-disp";
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]500
501 ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
502 compatible = "qcom,msm-ext-disp-audio-codec-rx";
503 };
504 };
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]505};
506
507&sde_dp {
Padmanabhan Komanduruf3838e42017-10-20 12:50:47 +0530[diff] [blame]508 qcom,dp-usbpd-detection = <&pm660_pdphy>;
509 qcom,ext-disp = <&ext_disp>;
510
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]511 pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
512 pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;
513 pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;
514 qcom,aux-en-gpio = <&tlmm 50 0>;
515 qcom,aux-sel-gpio = <&tlmm 40 0>;
516 qcom,usbplug-cc-gpio = <&tlmm 38 0>;
517};
518
519&mdss_mdp {
Padmanabhan Komandurud03f38f2017-10-10 15:34:41 +0530[diff] [blame]520 connectors = <&sde_rscc &sde_wb &sde_dp>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]521};
522
523&dsi_dual_nt35597_truly_video {
524 qcom,mdss-dsi-t-clk-post = <0x0D>;
525 qcom,mdss-dsi-t-clk-pre = <0x2D>;
Raviteja Tamatam52a580f2017-10-31 11:29:06 +0530[diff] [blame]526 qcom,mdss-dsi-min-refresh-rate = <53>;
527 qcom,mdss-dsi-max-refresh-rate = <60>;
528 qcom,mdss-dsi-pan-enable-dynamic-fps;
529 qcom,mdss-dsi-pan-fps-update =
530 "dfps_immediate_porch_mode_vfp";
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530[diff] [blame]531 qcom,esd-check-enabled;
532 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
533 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
534 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
535 qcom,mdss-dsi-panel-status-value = <0x9c>;
536 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
537 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]538 qcom,mdss-dsi-display-timings {
539 timing@0{
540 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
541 07 05 03 04 00];
542 qcom,display-topology = <2 0 2>,
543 <1 0 2>;
544 qcom,default-topology-index = <0>;
545 };
546 };
547};
548
549&dsi_dual_nt35597_truly_cmd {
550 qcom,mdss-dsi-t-clk-post = <0x0D>;
551 qcom,mdss-dsi-t-clk-pre = <0x2D>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530[diff] [blame]552 qcom,ulps-enabled;
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530[diff] [blame]553 qcom,esd-check-enabled;
554 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
555 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
556 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
557 qcom,mdss-dsi-panel-status-value = <0x9c>;
558 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
559 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]560 qcom,mdss-dsi-display-timings {
561 timing@0{
562 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
563 07 05 03 04 00];
564 qcom,display-topology = <2 0 2>,
565 <1 0 2>;
566 qcom,default-topology-index = <0>;
Sandeep Pandae34dcd72017-11-23 18:33:00 +0530[diff] [blame]567 qcom,partial-update-enabled = "single_roi";
568 qcom,panel-roi-alignment = <720 128 720 128 1440 128>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]569 };
570 };
571};
572
573&dsi_nt35597_truly_dsc_cmd {
574 qcom,mdss-dsi-t-clk-post = <0x0b>;
575 qcom,mdss-dsi-t-clk-pre = <0x23>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530[diff] [blame]576 qcom,ulps-enabled;
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530[diff] [blame]577 qcom,esd-check-enabled;
578 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
579 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
580 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
581 qcom,mdss-dsi-panel-status-value = <0x9c>;
582 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
583 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]584 qcom,mdss-dsi-display-timings {
585 timing@0{
586 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
587 05 03 03 04 00];
588 qcom,display-topology = <1 1 1>,
589 <2 2 1>, /* dsc merge */
590 <2 1 1>; /* 3d mux */
591 qcom,default-topology-index = <1>;
592 };
593 };
594};
595
596&dsi_nt35597_truly_dsc_video {
597 qcom,mdss-dsi-t-clk-post = <0x0b>;
598 qcom,mdss-dsi-t-clk-pre = <0x23>;
Raviteja Tamatam52a580f2017-10-31 11:29:06 +0530[diff] [blame]599 qcom,mdss-dsi-min-refresh-rate = <53>;
600 qcom,mdss-dsi-max-refresh-rate = <60>;
601 qcom,mdss-dsi-pan-enable-dynamic-fps;
602 qcom,mdss-dsi-pan-fps-update =
603 "dfps_immediate_porch_mode_vfp";
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530[diff] [blame]604 qcom,esd-check-enabled;
605 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
606 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
607 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
608 qcom,mdss-dsi-panel-status-value = <0x9c>;
609 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
610 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]611 qcom,mdss-dsi-display-timings {
612 timing@0{
613 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
614 04 03 03 04 00];
615 qcom,display-topology = <1 1 1>,
616 <2 2 1>, /* dsc merge */
617 <2 1 1>; /* 3d mux */
618 qcom,default-topology-index = <1>;
619 };
620 };
621};
622
623&dsi_sim_vid {
624 qcom,mdss-dsi-t-clk-post = <0x0d>;
625 qcom,mdss-dsi-t-clk-pre = <0x2d>;
626 qcom,mdss-dsi-display-timings {
627 timing@0{
628 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
629 07 05 03 04 00];
630 qcom,display-topology = <1 0 1>,
631 <2 0 1>;
632 qcom,default-topology-index = <0>;
633 };
634 };
635};
636
637&dsi_dual_sim_vid {
638 qcom,mdss-dsi-t-clk-post = <0x0d>;
639 qcom,mdss-dsi-t-clk-pre = <0x2d>;
640 qcom,mdss-dsi-display-timings {
641 timing@0{
642 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
643 07 05 03 04 00];
644 qcom,display-topology = <2 0 2>,
645 <1 0 2>;
646 qcom,default-topology-index = <0>;
647 };
648 };
649};
650
651&dsi_sim_cmd {
Sandeep Panda665a5352017-12-22 16:08:48 +0530[diff] [blame]652 qcom,mdss-dsi-t-clk-post = <0x0c>;
653 qcom,mdss-dsi-t-clk-pre = <0x29>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]654 qcom,mdss-dsi-display-timings {
655 timing@0{
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]656 qcom,display-topology = <1 0 1>,
Sandeep Panda665a5352017-12-22 16:08:48 +0530[diff] [blame]657 <2 2 1>;
658 qcom,default-topology-index = <1>;
659 qcom,panel-roi-alignment = <720 40 720 40 720 40>;
660 qcom,partial-update-enabled = "single_roi";
661 qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
662 07 04 03 04 00];
663 };
664 timing@1{
665 qcom,display-topology = <1 0 1>,
666 <2 2 1>;
667 qcom,default-topology-index = <1>;
668 qcom,panel-roi-alignment = <540 40 540 40 540 40>;
669 qcom,partial-update-enabled = "single_roi";
670 qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
671 07 04 03 04 00];
672 };
673 timing@2{
674 qcom,display-topology = <1 0 1>,
675 <2 2 1>;
676 qcom,default-topology-index = <1>;
677 qcom,panel-roi-alignment = <360 40 360 40 360 40>;
678 qcom,partial-update-enabled = "single_roi";
679 qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
680 07 04 03 04 00];
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530[diff] [blame]681 };
682 };
683};
684
685&dsi_dual_sim_cmd {
686 qcom,mdss-dsi-t-clk-post = <0x0d>;
687 qcom,mdss-dsi-t-clk-pre = <0x2d>;
688 qcom,mdss-dsi-display-timings {
689 timing@0{
690 qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
691 09 06 03 04 00];
692 qcom,display-topology = <2 0 2>;
693 qcom,default-topology-index = <0>;
694 };
695 timing@1{
696 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
697 07 05 03 04 00];
698 qcom,display-topology = <2 0 2>,
699 <1 0 2>;
700 qcom,default-topology-index = <0>;
701 };
702 timing@2{
703 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
704 06 04 03 04 00];
705 qcom,display-topology = <2 0 2>;
706 qcom,default-topology-index = <0>;
707 };
708 };
709};
710
711&dsi_sim_dsc_375_cmd {
712 qcom,mdss-dsi-t-clk-post = <0x0d>;
713 qcom,mdss-dsi-t-clk-pre = <0x2d>;
714 qcom,mdss-dsi-display-timings {
715 timing@0 { /* 1080p */
716 qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07
717 07 04 03 04 00];
718 qcom,display-topology = <1 1 1>;
719 qcom,default-topology-index = <0>;
720 };
721 timing@1 { /* qhd */
722 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
723 05 03 03 04 00];
724 qcom,display-topology = <1 1 1>,
725 <2 2 1>, /* dsc merge */
726 <2 1 1>; /* 3d mux */
727 qcom,default-topology-index = <0>;
728 };
729 };
730};
731
732&dsi_dual_sim_dsc_375_cmd {
733 qcom,mdss-dsi-t-clk-post = <0x0d>;
734 qcom,mdss-dsi-t-clk-pre = <0x2d>;
735 qcom,mdss-dsi-display-timings {
736 timing@0 { /* qhd */
737 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
738 07 05 03 04 00];
739 qcom,display-topology = <2 2 2>;
740 qcom,default-topology-index = <0>;
741 };
742 timing@1 { /* 4k */
743 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
744 06 04 03 04 00];
745 qcom,display-topology = <2 2 2>;
746 qcom,default-topology-index = <0>;
747 };
748 };
749};
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]750
751&dsi_dual_nt35597_video {
752 qcom,mdss-dsi-t-clk-post = <0x0d>;
753 qcom,mdss-dsi-t-clk-pre = <0x2d>;
754 qcom,mdss-dsi-display-timings {
755 timing@0 {
Sandeep Panda4443ddb2017-12-15 15:56:17 +0530[diff] [blame]756 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
757 07 05 03 04 00];
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]758 qcom,display-topology = <2 0 2>,
759 <1 0 2>;
760 qcom,default-topology-index = <0>;
761 };
762 };
763};
764
765&dsi_dual_nt35597_cmd {
766 qcom,mdss-dsi-t-clk-post = <0x0d>;
767 qcom,mdss-dsi-t-clk-pre = <0x2d>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530[diff] [blame]768 qcom,ulps-enabled;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]769 qcom,mdss-dsi-display-timings {
770 timing@0 {
Sandeep Panda4443ddb2017-12-15 15:56:17 +0530[diff] [blame]771 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
772 07 05 03 04 00];
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]773 qcom,display-topology = <2 0 2>,
774 <1 0 2>;
775 qcom,default-topology-index = <0>;
Sandeep Pandae34dcd72017-11-23 18:33:00 +0530[diff] [blame]776 qcom,partial-update-enabled = "single_roi";
777 qcom,panel-roi-alignment = <720 128 720 128 1440 128>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]778 };
779 };
780};
781
782&dsi_rm67195_amoled_fhd_cmd {
783 qcom,mdss-dsi-t-clk-post = <0x07>;
784 qcom,mdss-dsi-t-clk-pre = <0x1c>;
785 qcom,mdss-dsi-display-timings {
786 timing@0 {
787 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
788 05 07 05 03 04 00];
789 qcom,display-topology = <1 0 1>;
790 qcom,default-topology-index = <0>;
791 };
792 };
793};
794
795&dsi_nt35695b_truly_fhd_video {
796 qcom,mdss-dsi-t-clk-post = <0x07>;
797 qcom,mdss-dsi-t-clk-pre = <0x1c>;
Raviteja Tamatamd5ca1b82017-11-30 13:23:54 +0530[diff] [blame]798 qcom,mdss-dsi-min-refresh-rate = <48>;
799 qcom,mdss-dsi-max-refresh-rate = <60>;
800 qcom,mdss-dsi-pan-enable-dynamic-fps;
801 qcom,mdss-dsi-pan-fps-update =
802 "dfps_immediate_porch_mode_vfp";
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]803 qcom,mdss-dsi-display-timings {
804 timing@0 {
805 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
806 05 07 05 03 04 00];
807 qcom,display-topology = <1 0 1>;
808 qcom,default-topology-index = <0>;
809 };
810 };
811};
812
813&dsi_nt35695b_truly_fhd_cmd {
Sandeep Panda91de3d82018-01-02 17:53:40 +0530[diff] [blame]814 qcom,mdss-dsi-t-clk-post = <0x0d>;
815 qcom,mdss-dsi-t-clk-pre = <0x2d>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530[diff] [blame]816 qcom,ulps-enabled;
Jayant Shekhar4812b012018-01-03 18:47:24 +0530[diff] [blame]817 qcom,mdss-mdp-transfer-time-us = <14500>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]818 qcom,mdss-dsi-display-timings {
819 timing@0 {
Sandeep Panda91de3d82018-01-02 17:53:40 +0530[diff] [blame]820 qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22
821 07 07 05 03 04 00];
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530[diff] [blame]822 qcom,display-topology = <1 0 1>;
823 qcom,default-topology-index = <0>;
824 };
825 };
826};
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame]827
828&dsi_dual_nt36850_truly_cmd {
Yuan Zhao33c507a2018-01-04 19:39:07 +0800[diff] [blame]829 qcom,mdss-dsi-t-clk-post = <0x28>;
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame]830 qcom,mdss-dsi-t-clk-pre = <0x30>;
Yuan Zhao33c507a2018-01-04 19:39:07 +0800[diff] [blame]831 qcom,esd-check-enabled;
832 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
833 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
Yuan Zhao77bf6f72018-02-08 14:32:50 +0800[diff] [blame^]834 qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
Yuan Zhao33c507a2018-01-04 19:39:07 +0800[diff] [blame]835 qcom,mdss-dsi-panel-status-value = <0x9c>;
836 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
837 qcom,mdss-dsi-panel-status-read-length = <1>;
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800[diff] [blame]838 qcom,mdss-dsi-display-timings {
839 timing@0{
840 qcom,mdss-dsi-panel-phy-timings = [00 1f 08 08 24 23 08
841 08 05 03 04 00];
842 qcom,display-topology = <2 0 2>,
843 <1 0 2>;
844 qcom,default-topology-index = <0>;
845 };
846 };
847};
Yuan Zhaoccd2d3d2017-11-23 13:09:10 +0800[diff] [blame]848
849&dsi_hx8399_truly_cmd {
850 qcom,mdss-dsi-t-clk-post = <0x0E>;
851 qcom,mdss-dsi-t-clk-pre = <0x30>;
Yuan Zhao77bf6f72018-02-08 14:32:50 +0800[diff] [blame^]852 qcom,mdss-dsi-min-refresh-rate = <55>;
853 qcom,mdss-dsi-max-refresh-rate = <60>;
854 qcom,mdss-dsi-pan-enable-dynamic-fps;
855 qcom,mdss-dsi-pan-fps-update =
856 "dfps_immediate_porch_mode_vfp";
857 qcom,esd-check-enabled;
858 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
859 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
860 qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
861 qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>;
862 qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>;
863 qcom,mdss-dsi-panel-status-read-length = <4>;
Yuan Zhaoccd2d3d2017-11-23 13:09:10 +0800[diff] [blame]864 qcom,mdss-dsi-display-timings {
865 timing@0 {
866 qcom,mdss-dsi-panel-phy-timings = [00 1f 08 08 24 22 08
867 08 05 03 04 00];
868 qcom,display-topology = <1 0 1>;
869 qcom,default-topology-index = <0>;
870 };
871 };
872};