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gerrit-public.fairphone.software / kernel / msm-4.9 / c7aa12a62c61d3be99c17faefa4f4f35cfef45e4 / . / arch / arm / boot / dts / imx6qdl.dtsi
blob: 11dfe5b8c08617c79d6e10fca85b296c30c9973d [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
Shawn Guo36dffd82013-04-07 10:49:34 +0800[diff] [blame]13#include "skeleton.dtsi"
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]14
15/ {
16 aliases {
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]17 gpio0 = &gpio1;
18 gpio1 = &gpio2;
19 gpio2 = &gpio3;
20 gpio3 = &gpio4;
21 gpio4 = &gpio5;
22 gpio5 = &gpio6;
23 gpio6 = &gpio7;
Sascha Hauer80fa0582013-06-25 15:51:57 +0200[diff] [blame]24 i2c0 = &i2c1;
25 i2c1 = &i2c2;
26 i2c2 = &i2c3;
27 serial0 = &uart1;
28 serial1 = &uart2;
29 serial2 = &uart3;
30 serial3 = &uart4;
31 serial4 = &uart5;
32 spi0 = &ecspi1;
33 spi1 = &ecspi2;
34 spi2 = &ecspi3;
35 spi3 = &ecspi4;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]36 };
37
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]38 intc: interrupt-controller@00a01000 {
39 compatible = "arm,cortex-a9-gic";
40 #interrupt-cells = <3>;
41 #address-cells = <1>;
42 #size-cells = <1>;
43 interrupt-controller;
44 reg = <0x00a01000 0x1000>,
45 <0x00a00100 0x100>;
46 };
47
48 clocks {
49 #address-cells = <1>;
50 #size-cells = <0>;
51
52 ckil {
53 compatible = "fsl,imx-ckil", "fixed-clock";
54 clock-frequency = <32768>;
55 };
56
57 ckih1 {
58 compatible = "fsl,imx-ckih1", "fixed-clock";
59 clock-frequency = <0>;
60 };
61
62 osc {
63 compatible = "fsl,imx-osc", "fixed-clock";
64 clock-frequency = <24000000>;
65 };
66 };
67
68 soc {
69 #address-cells = <1>;
70 #size-cells = <1>;
71 compatible = "simple-bus";
72 interrupt-parent = <&intc>;
73 ranges;
74
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]75 dma_apbh: dma-apbh@00110000 {
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]76 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
77 reg = <0x00110000 0x2000>;
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]78 interrupts = <0 13 0x04>, <0 13 0x04>, <0 13 0x04>, <0 13 0x04>;
79 interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
80 #dma-cells = <1>;
81 dma-channels = <4>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]82 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]83 };
84
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]85 gpmi: gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]86 compatible = "fsl,imx6q-gpmi-nand";
87 #address-cells = <1>;
88 #size-cells = <1>;
89 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
90 reg-names = "gpmi-nand", "bch";
Shawn Guoc7aa12a2013-07-16 17:13:00 +0800[diff] [blame^]91 interrupts = <0 15 0x04>;
92 interrupt-names = "bch";
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]93 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
94 <&clks 150>, <&clks 149>;
95 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
96 "gpmi_bch_apb", "per1_bch";
Shawn Guof30fb032013-02-25 21:56:56 +0800[diff] [blame]97 dmas = <&dma_apbh 0>;
98 dma-names = "rx-tx";
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]99 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]100 };
101
Philipp Zabel481fbe12013-07-01 11:06:09 +0200[diff] [blame]102 ocram: sram@00900000 {
103 compatible = "mmio-sram";
104 reg = <0x00900000 0x3f000>;
105 clocks = <&clks 142>;
106 };
107
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]108 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]109 compatible = "arm,cortex-a9-twd-timer";
110 reg = <0x00a00600 0x20>;
111 interrupts = <1 13 0xf01>;
Shawn Guo2bb4b702013-04-03 23:50:09 +0800[diff] [blame]112 clocks = <&clks 15>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]113 };
114
115 L2: l2-cache@00a02000 {
116 compatible = "arm,pl310-cache";
117 reg = <0x00a02000 0x1000>;
118 interrupts = <0 92 0x04>;
119 cache-unified;
120 cache-level = <2>;
Dirk Behme5a5ca562013-04-26 10:13:55 +0200[diff] [blame]121 arm,tag-latency = <4 2 3>;
122 arm,data-latency = <4 2 3>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]123 };
124
Dirk Behme218abe62013-02-15 15:10:01 +0100[diff] [blame]125 pmu {
126 compatible = "arm,cortex-a9-pmu";
127 interrupts = <0 94 0x04>;
128 };
129
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]130 aips-bus@02000000 { /* AIPS1 */
131 compatible = "fsl,aips-bus", "simple-bus";
132 #address-cells = <1>;
133 #size-cells = <1>;
134 reg = <0x02000000 0x100000>;
135 ranges;
136
137 spba-bus@02000000 {
138 compatible = "fsl,spba-bus", "simple-bus";
139 #address-cells = <1>;
140 #size-cells = <1>;
141 reg = <0x02000000 0x40000>;
142 ranges;
143
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]144 spdif: spdif@02004000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]145 reg = <0x02004000 0x4000>;
146 interrupts = <0 52 0x04>;
147 };
148
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]149 ecspi1: ecspi@02008000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]150 #address-cells = <1>;
151 #size-cells = <0>;
152 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
153 reg = <0x02008000 0x4000>;
154 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]155 clocks = <&clks 112>, <&clks 112>;
156 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]157 status = "disabled";
158 };
159
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]160 ecspi2: ecspi@0200c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
164 reg = <0x0200c000 0x4000>;
165 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]166 clocks = <&clks 113>, <&clks 113>;
167 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]168 status = "disabled";
169 };
170
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]171 ecspi3: ecspi@02010000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
175 reg = <0x02010000 0x4000>;
176 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]177 clocks = <&clks 114>, <&clks 114>;
178 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]179 status = "disabled";
180 };
181
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]182 ecspi4: ecspi@02014000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
186 reg = <0x02014000 0x4000>;
187 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]188 clocks = <&clks 115>, <&clks 115>;
189 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]190 status = "disabled";
191 };
192
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]193 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]194 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
195 reg = <0x02020000 0x4000>;
196 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]197 clocks = <&clks 160>, <&clks 161>;
198 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]199 dmas = <&sdma 25 4 0>, <&sdma 26 4 0>;
200 dma-names = "rx", "tx";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]201 status = "disabled";
202 };
203
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]204 esai: esai@02024000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]205 reg = <0x02024000 0x4000>;
206 interrupts = <0 51 0x04>;
207 };
208
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]209 ssi1: ssi@02028000 {
210 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]211 reg = <0x02028000 0x4000>;
212 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]213 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]214 fsl,fifo-depth = <15>;
215 fsl,ssi-dma-events = <38 37>;
216 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]217 };
218
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]219 ssi2: ssi@0202c000 {
220 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]221 reg = <0x0202c000 0x4000>;
222 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]223 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]224 fsl,fifo-depth = <15>;
225 fsl,ssi-dma-events = <42 41>;
226 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]227 };
228
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]229 ssi3: ssi@02030000 {
230 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]231 reg = <0x02030000 0x4000>;
232 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]233 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]234 fsl,fifo-depth = <15>;
235 fsl,ssi-dma-events = <46 45>;
236 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]237 };
238
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]239 asrc: asrc@02034000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]240 reg = <0x02034000 0x4000>;
241 interrupts = <0 50 0x04>;
242 };
243
244 spba@0203c000 {
245 reg = <0x0203c000 0x4000>;
246 };
247 };
248
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]249 vpu: vpu@02040000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]250 reg = <0x02040000 0x3c000>;
251 interrupts = <0 3 0x04 0 12 0x04>;
252 };
253
254 aipstz@0207c000 { /* AIPSTZ1 */
255 reg = <0x0207c000 0x4000>;
256 };
257
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]258 pwm1: pwm@02080000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]259 #pwm-cells = <2>;
260 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]261 reg = <0x02080000 0x4000>;
262 interrupts = <0 83 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]263 clocks = <&clks 62>, <&clks 145>;
264 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]265 };
266
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]267 pwm2: pwm@02084000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]268 #pwm-cells = <2>;
269 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]270 reg = <0x02084000 0x4000>;
271 interrupts = <0 84 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]272 clocks = <&clks 62>, <&clks 146>;
273 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]274 };
275
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]276 pwm3: pwm@02088000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]277 #pwm-cells = <2>;
278 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]279 reg = <0x02088000 0x4000>;
280 interrupts = <0 85 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]281 clocks = <&clks 62>, <&clks 147>;
282 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]283 };
284
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]285 pwm4: pwm@0208c000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]286 #pwm-cells = <2>;
287 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]288 reg = <0x0208c000 0x4000>;
289 interrupts = <0 86 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]290 clocks = <&clks 62>, <&clks 148>;
291 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]292 };
293
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]294 can1: flexcan@02090000 {
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]295 compatible = "fsl,imx6q-flexcan";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]296 reg = <0x02090000 0x4000>;
297 interrupts = <0 110 0x04>;
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]298 clocks = <&clks 108>, <&clks 109>;
299 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]300 };
301
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]302 can2: flexcan@02094000 {
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]303 compatible = "fsl,imx6q-flexcan";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]304 reg = <0x02094000 0x4000>;
305 interrupts = <0 111 0x04>;
Sascha Hauer0f225212013-06-25 15:51:46 +0200[diff] [blame]306 clocks = <&clks 110>, <&clks 111>;
307 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]308 };
309
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]310 gpt: gpt@02098000 {
Sascha Hauer97b108f2013-06-25 15:51:47 +0200[diff] [blame]311 compatible = "fsl,imx6q-gpt", "fsl,imx31-gpt";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]312 reg = <0x02098000 0x4000>;
313 interrupts = <0 55 0x04>;
Sascha Hauer4efccad2013-03-14 13:09:01 +0100[diff] [blame]314 clocks = <&clks 119>, <&clks 120>;
315 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]316 };
317
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]318 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]319 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]320 reg = <0x0209c000 0x4000>;
321 interrupts = <0 66 0x04 0 67 0x04>;
322 gpio-controller;
323 #gpio-cells = <2>;
324 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]325 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]326 };
327
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]328 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]329 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]330 reg = <0x020a0000 0x4000>;
331 interrupts = <0 68 0x04 0 69 0x04>;
332 gpio-controller;
333 #gpio-cells = <2>;
334 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]335 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]336 };
337
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]338 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]339 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]340 reg = <0x020a4000 0x4000>;
341 interrupts = <0 70 0x04 0 71 0x04>;
342 gpio-controller;
343 #gpio-cells = <2>;
344 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]345 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]346 };
347
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]348 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]349 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]350 reg = <0x020a8000 0x4000>;
351 interrupts = <0 72 0x04 0 73 0x04>;
352 gpio-controller;
353 #gpio-cells = <2>;
354 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]355 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]356 };
357
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]358 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]359 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]360 reg = <0x020ac000 0x4000>;
361 interrupts = <0 74 0x04 0 75 0x04>;
362 gpio-controller;
363 #gpio-cells = <2>;
364 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]365 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]366 };
367
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]368 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]369 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]370 reg = <0x020b0000 0x4000>;
371 interrupts = <0 76 0x04 0 77 0x04>;
372 gpio-controller;
373 #gpio-cells = <2>;
374 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]375 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]376 };
377
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]378 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]379 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]380 reg = <0x020b4000 0x4000>;
381 interrupts = <0 78 0x04 0 79 0x04>;
382 gpio-controller;
383 #gpio-cells = <2>;
384 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]385 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]386 };
387
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]388 kpp: kpp@020b8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]389 reg = <0x020b8000 0x4000>;
390 interrupts = <0 82 0x04>;
391 };
392
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]393 wdog1: wdog@020bc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]394 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
395 reg = <0x020bc000 0x4000>;
396 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]397 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]398 };
399
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]400 wdog2: wdog@020c0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]401 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
402 reg = <0x020c0000 0x4000>;
403 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]404 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]405 status = "disabled";
406 };
407
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]408 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]409 compatible = "fsl,imx6q-ccm";
410 reg = <0x020c4000 0x4000>;
411 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]412 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]413 };
414
Dong Aishengbaa64152012-09-05 10:57:15 +0800[diff] [blame]415 anatop: anatop@020c8000 {
416 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]417 reg = <0x020c8000 0x1000>;
418 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]419
420 regulator-1p1@110 {
421 compatible = "fsl,anatop-regulator";
422 regulator-name = "vdd1p1";
423 regulator-min-microvolt = <800000>;
424 regulator-max-microvolt = <1375000>;
425 regulator-always-on;
426 anatop-reg-offset = <0x110>;
427 anatop-vol-bit-shift = <8>;
428 anatop-vol-bit-width = <5>;
429 anatop-min-bit-val = <4>;
430 anatop-min-voltage = <800000>;
431 anatop-max-voltage = <1375000>;
432 };
433
434 regulator-3p0@120 {
435 compatible = "fsl,anatop-regulator";
436 regulator-name = "vdd3p0";
437 regulator-min-microvolt = <2800000>;
438 regulator-max-microvolt = <3150000>;
439 regulator-always-on;
440 anatop-reg-offset = <0x120>;
441 anatop-vol-bit-shift = <8>;
442 anatop-vol-bit-width = <5>;
443 anatop-min-bit-val = <0>;
444 anatop-min-voltage = <2625000>;
445 anatop-max-voltage = <3400000>;
446 };
447
448 regulator-2p5@130 {
449 compatible = "fsl,anatop-regulator";
450 regulator-name = "vdd2p5";
451 regulator-min-microvolt = <2000000>;
452 regulator-max-microvolt = <2750000>;
453 regulator-always-on;
454 anatop-reg-offset = <0x130>;
455 anatop-vol-bit-shift = <8>;
456 anatop-vol-bit-width = <5>;
457 anatop-min-bit-val = <0>;
458 anatop-min-voltage = <2000000>;
459 anatop-max-voltage = <2750000>;
460 };
461
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]462 reg_arm: regulator-vddcore@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]463 compatible = "fsl,anatop-regulator";
464 regulator-name = "cpu";
465 regulator-min-microvolt = <725000>;
466 regulator-max-microvolt = <1450000>;
467 regulator-always-on;
468 anatop-reg-offset = <0x140>;
469 anatop-vol-bit-shift = <0>;
470 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]471 anatop-delay-reg-offset = <0x170>;
472 anatop-delay-bit-shift = <24>;
473 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]474 anatop-min-bit-val = <1>;
475 anatop-min-voltage = <725000>;
476 anatop-max-voltage = <1450000>;
477 };
478
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]479 reg_pu: regulator-vddpu@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]480 compatible = "fsl,anatop-regulator";
481 regulator-name = "vddpu";
482 regulator-min-microvolt = <725000>;
483 regulator-max-microvolt = <1450000>;
484 regulator-always-on;
485 anatop-reg-offset = <0x140>;
486 anatop-vol-bit-shift = <9>;
487 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]488 anatop-delay-reg-offset = <0x170>;
489 anatop-delay-bit-shift = <26>;
490 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]491 anatop-min-bit-val = <1>;
492 anatop-min-voltage = <725000>;
493 anatop-max-voltage = <1450000>;
494 };
495
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]496 reg_soc: regulator-vddsoc@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]497 compatible = "fsl,anatop-regulator";
498 regulator-name = "vddsoc";
499 regulator-min-microvolt = <725000>;
500 regulator-max-microvolt = <1450000>;
501 regulator-always-on;
502 anatop-reg-offset = <0x140>;
503 anatop-vol-bit-shift = <18>;
504 anatop-vol-bit-width = <5>;
Anson Huang46743dd2013-01-30 17:33:44 -0500[diff] [blame]505 anatop-delay-reg-offset = <0x170>;
506 anatop-delay-bit-shift = <28>;
507 anatop-delay-bit-width = <2>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]508 anatop-min-bit-val = <1>;
509 anatop-min-voltage = <725000>;
510 anatop-max-voltage = <1450000>;
511 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]512 };
513
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]514 usbphy1: usbphy@020c9000 {
515 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]516 reg = <0x020c9000 0x1000>;
517 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]518 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]519 };
520
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]521 usbphy2: usbphy@020ca000 {
522 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]523 reg = <0x020ca000 0x1000>;
524 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]525 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]526 };
527
528 snvs@020cc000 {
Shawn Guoc9250382012-07-02 20:13:03 +0800[diff] [blame]529 compatible = "fsl,sec-v4.0-mon", "simple-bus";
530 #address-cells = <1>;
531 #size-cells = <1>;
532 ranges = <0 0x020cc000 0x4000>;
533
534 snvs-rtc-lp@34 {
535 compatible = "fsl,sec-v4.0-mon-rtc-lp";
536 reg = <0x34 0x58>;
537 interrupts = <0 19 0x04 0 20 0x04>;
538 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]539 };
540
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]541 epit1: epit@020d0000 { /* EPIT1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]542 reg = <0x020d0000 0x4000>;
543 interrupts = <0 56 0x04>;
544 };
545
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]546 epit2: epit@020d4000 { /* EPIT2 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]547 reg = <0x020d4000 0x4000>;
548 interrupts = <0 57 0x04>;
549 };
550
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]551 src: src@020d8000 {
Philipp Zabelbd3d9242013-03-28 17:35:22 +0100[diff] [blame]552 compatible = "fsl,imx6q-src", "fsl,imx51-src";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]553 reg = <0x020d8000 0x4000>;
554 interrupts = <0 91 0x04 0 96 0x04>;
Philipp Zabel09ebf362013-03-28 17:35:20 +0100[diff] [blame]555 #reset-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]556 };
557
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]558 gpc: gpc@020dc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]559 compatible = "fsl,imx6q-gpc";
560 reg = <0x020dc000 0x4000>;
561 interrupts = <0 89 0x04 0 90 0x04>;
562 };
563
Dong Aishengdf37e0c2012-09-05 10:57:14 +0800[diff] [blame]564 gpr: iomuxc-gpr@020e0000 {
565 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
566 reg = <0x020e0000 0x38>;
567 };
568
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]569 iomuxc: iomuxc@020e0000 {
570 compatible = "fsl,imx6dl-iomuxc", "fsl,imx6q-iomuxc";
571 reg = <0x020e0000 0x4000>;
572
573 audmux {
574 pinctrl_audmux_1: audmux-1 {
575 fsl,pins = <
576 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x80000000
577 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x80000000
578 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x80000000
579 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x80000000
580 >;
581 };
582
583 pinctrl_audmux_2: audmux-2 {
584 fsl,pins = <
585 MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x80000000
586 MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x80000000
587 MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x80000000
588 MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x80000000
589 >;
590 };
Shawn Guob72ce922013-07-12 11:38:50 +0800[diff] [blame]591
592 pinctrl_audmux_3: audmux-3 {
593 fsl,pins = <
594 MX6QDL_PAD_DISP0_DAT16__AUD5_TXC 0x80000000
595 MX6QDL_PAD_DISP0_DAT18__AUD5_TXFS 0x80000000
596 MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x80000000
597 >;
598 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]599 };
600
601 ecspi1 {
602 pinctrl_ecspi1_1: ecspi1grp-1 {
603 fsl,pins = <
604 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
605 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
606 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
607 >;
608 };
609
610 pinctrl_ecspi1_2: ecspi1grp-2 {
611 fsl,pins = <
612 MX6QDL_PAD_KEY_COL1__ECSPI1_MISO 0x100b1
613 MX6QDL_PAD_KEY_ROW0__ECSPI1_MOSI 0x100b1
614 MX6QDL_PAD_KEY_COL0__ECSPI1_SCLK 0x100b1
615 >;
616 };
617 };
618
619 ecspi3 {
620 pinctrl_ecspi3_1: ecspi3grp-1 {
621 fsl,pins = <
622 MX6QDL_PAD_DISP0_DAT2__ECSPI3_MISO 0x100b1
623 MX6QDL_PAD_DISP0_DAT1__ECSPI3_MOSI 0x100b1
624 MX6QDL_PAD_DISP0_DAT0__ECSPI3_SCLK 0x100b1
625 >;
626 };
627 };
628
629 enet {
630 pinctrl_enet_1: enetgrp-1 {
631 fsl,pins = <
632 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
633 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
634 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
635 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
636 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
637 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
638 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
639 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
640 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
641 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
642 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
643 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
644 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
645 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
646 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
647 MX6QDL_PAD_GPIO_16__ENET_REF_CLK 0x4001b0a8
648 >;
649 };
650
651 pinctrl_enet_2: enetgrp-2 {
652 fsl,pins = <
653 MX6QDL_PAD_KEY_COL1__ENET_MDIO 0x1b0b0
654 MX6QDL_PAD_KEY_COL2__ENET_MDC 0x1b0b0
655 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
656 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
657 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
658 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
659 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
660 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
661 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
662 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
663 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
664 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
665 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
666 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
667 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
668 >;
669 };
670
671 pinctrl_enet_3: enetgrp-3 {
672 fsl,pins = <
673 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0
674 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0
675 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0
676 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0
677 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0
678 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0
679 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0
680 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0
681 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0
682 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0
683 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0
684 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0
685 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0
686 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0
687 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0
688 MX6QDL_PAD_ENET_TX_EN__ENET_TX_EN 0x1b0b0
689 >;
690 };
691 };
692
Shawn Guob72ce922013-07-12 11:38:50 +0800[diff] [blame]693 esai {
694 pinctrl_esai_1: esaigrp-1 {
695 fsl,pins = <
696 MX6QDL_PAD_ENET_RXD0__ESAI_TX_HF_CLK 0x1b030
697 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
698 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
699 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
700 MX6QDL_PAD_ENET_TXD1__ESAI_TX2_RX3 0x1b030
701 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
702 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
703 MX6QDL_PAD_NANDF_CS2__ESAI_TX0 0x1b030
704 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
705 >;
706 };
707
708 pinctrl_esai_2: esaigrp-2 {
709 fsl,pins = <
710 MX6QDL_PAD_ENET_CRS_DV__ESAI_TX_CLK 0x1b030
711 MX6QDL_PAD_ENET_RXD1__ESAI_TX_FS 0x1b030
712 MX6QDL_PAD_ENET_TX_EN__ESAI_TX3_RX2 0x1b030
713 MX6QDL_PAD_GPIO_5__ESAI_TX2_RX3 0x1b030
714 MX6QDL_PAD_ENET_TXD0__ESAI_TX4_RX1 0x1b030
715 MX6QDL_PAD_ENET_MDC__ESAI_TX5_RX0 0x1b030
716 MX6QDL_PAD_GPIO_17__ESAI_TX0 0x1b030
717 MX6QDL_PAD_NANDF_CS3__ESAI_TX1 0x1b030
718 MX6QDL_PAD_ENET_MDIO__ESAI_RX_CLK 0x1b030
719 MX6QDL_PAD_GPIO_9__ESAI_RX_FS 0x1b030
720 >;
721 };
722 };
723
724 flexcan1 {
725 pinctrl_flexcan1_1: flexcan1grp-1 {
726 fsl,pins = <
727 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
728 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x80000000
729 >;
730 };
731
732 pinctrl_flexcan1_2: flexcan1grp-2 {
733 fsl,pins = <
734 MX6QDL_PAD_GPIO_7__FLEXCAN1_TX 0x80000000
735 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x80000000
736 >;
737 };
738 };
739
740 flexcan2 {
741 pinctrl_flexcan2_1: flexcan2grp-1 {
742 fsl,pins = <
743 MX6QDL_PAD_KEY_COL4__FLEXCAN2_TX 0x80000000
744 MX6QDL_PAD_KEY_ROW4__FLEXCAN2_RX 0x80000000
745 >;
746 };
747 };
748
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]749 gpmi-nand {
750 pinctrl_gpmi_nand_1: gpmi-nand-1 {
751 fsl,pins = <
752 MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1
753 MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1
754 MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1
755 MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000
756 MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1
757 MX6QDL_PAD_NANDF_CS1__NAND_CE1_B 0xb0b1
758 MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1
759 MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1
760 MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1
761 MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1
762 MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1
763 MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1
764 MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1
765 MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1
766 MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1
767 MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1
768 MX6QDL_PAD_SD4_DAT0__NAND_DQS 0x00b1
769 >;
770 };
771 };
772
Shawn Guob72ce922013-07-12 11:38:50 +0800[diff] [blame]773 hdmi_hdcp {
774 pinctrl_hdmi_hdcp_1: hdmihdcpgrp-1 {
775 fsl,pins = <
776 MX6QDL_PAD_KEY_COL3__HDMI_TX_DDC_SCL 0x4001b8b1
777 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
778 >;
779 };
780
781 pinctrl_hdmi_hdcp_2: hdmihdcpgrp-2 {
782 fsl,pins = <
783 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
784 MX6QDL_PAD_EIM_D16__HDMI_TX_DDC_SDA 0x4001b8b1
785 >;
786 };
787
788 pinctrl_hdmi_hdcp_3: hdmihdcpgrp-3 {
789 fsl,pins = <
790 MX6QDL_PAD_EIM_EB2__HDMI_TX_DDC_SCL 0x4001b8b1
791 MX6QDL_PAD_KEY_ROW3__HDMI_TX_DDC_SDA 0x4001b8b1
792 >;
793 };
794 };
795
796 hdmi_cec {
797 pinctrl_hdmi_cec_1: hdmicecgrp-1 {
798 fsl,pins = <
799 MX6QDL_PAD_EIM_A25__HDMI_TX_CEC_LINE 0x1f8b0
800 >;
801 };
802
803 pinctrl_hdmi_cec_2: hdmicecgrp-2 {
804 fsl,pins = <
805 MX6QDL_PAD_KEY_ROW2__HDMI_TX_CEC_LINE 0x1f8b0
806 >;
807 };
808 };
809
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]810 i2c1 {
811 pinctrl_i2c1_1: i2c1grp-1 {
812 fsl,pins = <
813 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
814 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
815 >;
816 };
817
818 pinctrl_i2c1_2: i2c1grp-2 {
819 fsl,pins = <
820 MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1
821 MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1
822 >;
823 };
824 };
825
826 i2c2 {
827 pinctrl_i2c2_1: i2c2grp-1 {
828 fsl,pins = <
829 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
830 MX6QDL_PAD_EIM_D16__I2C2_SDA 0x4001b8b1
831 >;
832 };
833
834 pinctrl_i2c2_2: i2c2grp-2 {
835 fsl,pins = <
836 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
837 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
838 >;
839 };
Shawn Guob72ce922013-07-12 11:38:50 +0800[diff] [blame]840
841 pinctrl_i2c2_3: i2c2grp-3 {
842 fsl,pins = <
843 MX6QDL_PAD_EIM_EB2__I2C2_SCL 0x4001b8b1
844 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
845 >;
846 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]847 };
848
849 i2c3 {
850 pinctrl_i2c3_1: i2c3grp-1 {
851 fsl,pins = <
852 MX6QDL_PAD_EIM_D17__I2C3_SCL 0x4001b8b1
853 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
854 >;
855 };
Shawn Guob72ce922013-07-12 11:38:50 +0800[diff] [blame]856
857 pinctrl_i2c3_2: i2c3grp-2 {
858 fsl,pins = <
859 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
860 MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1
861 >;
862 };
863
864 pinctrl_i2c3_3: i2c3grp-3 {
865 fsl,pins = <
866 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
867 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
868 >;
869 };
870
871 pinctrl_i2c3_4: i2c3grp-4 {
872 fsl,pins = <
873 MX6QDL_PAD_GPIO_3__I2C3_SCL 0x4001b8b1
874 MX6QDL_PAD_EIM_D18__I2C3_SDA 0x4001b8b1
875 >;
876 };
877 };
878
879 ipu1 {
880 pinctrl_ipu1_1: ipu1grp-1 {
881 fsl,pins = <
882 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
883 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
884 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
885 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
886 MX6QDL_PAD_DI0_PIN4__IPU1_DI0_PIN04 0x80000000
887 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
888 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
889 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
890 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
891 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
892 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
893 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
894 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
895 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
896 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
897 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
898 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
899 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
900 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
901 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
902 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
903 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
904 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
905 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
906 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
907 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
908 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
909 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
910 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
911 >;
912 };
913
914 pinctrl_ipu1_2: ipu1grp-2 { /* parallel camera */
915 fsl,pins = <
916 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
917 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
918 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
919 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
920 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
921 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
922 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
923 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
924 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x80000000
925 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
926 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
927 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
928 >;
929 };
930
931 pinctrl_ipu1_3: ipu1grp-3 { /* parallel port 16-bit */
932 fsl,pins = <
933 MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x80000000
934 MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x80000000
935 MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x80000000
936 MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x80000000
937 MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x80000000
938 MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x80000000
939 MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x80000000
940 MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x80000000
941 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x80000000
942 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x80000000
943 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x80000000
944 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x80000000
945 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x80000000
946 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x80000000
947 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x80000000
948 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x80000000
949 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x80000000
950 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x80000000
951 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x80000000
952 >;
953 };
954 };
955
956 mlb {
957 pinctrl_mlb_1: mlbgrp-1 {
958 fsl,pins = <
959 MX6QDL_PAD_GPIO_3__MLB_CLK 0x71
960 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
961 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
962 >;
963 };
964
965 pinctrl_mlb_2: mlbgrp-2 {
966 fsl,pins = <
967 MX6QDL_PAD_ENET_TXD1__MLB_CLK 0x71
968 MX6QDL_PAD_GPIO_6__MLB_SIG 0x71
969 MX6QDL_PAD_GPIO_2__MLB_DATA 0x71
970 >;
971 };
972 };
973
974 pwm0 {
975 pinctrl_pwm0_1: pwm0grp-1 {
976 fsl,pins = <
977 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
978 >;
979 };
980 };
981
982 pwm3 {
983 pinctrl_pwm3_1: pwm3grp-1 {
984 fsl,pins = <
985 MX6QDL_PAD_SD4_DAT1__PWM3_OUT 0x1b0b1
986 >;
987 };
988 };
989
990 spdif {
991 pinctrl_spdif_1: spdifgrp-1 {
992 fsl,pins = <
993 MX6QDL_PAD_KEY_COL3__SPDIF_IN 0x1b0b0
994 >;
995 };
996
997 pinctrl_spdif_2: spdifgrp-2 {
998 fsl,pins = <
999 MX6QDL_PAD_GPIO_16__SPDIF_IN 0x1b0b0
1000 MX6QDL_PAD_GPIO_17__SPDIF_OUT 0x1b0b0
1001 >;
1002 };
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]1003 };
1004
1005 uart1 {
1006 pinctrl_uart1_1: uart1grp-1 {
1007 fsl,pins = <
1008 MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1
1009 MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1
1010 >;
1011 };
1012 };
1013
1014 uart2 {
1015 pinctrl_uart2_1: uart2grp-1 {
1016 fsl,pins = <
1017 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
1018 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
1019 >;
1020 };
1021
1022 pinctrl_uart2_2: uart2grp-2 { /* DTE mode */
1023 fsl,pins = <
1024 MX6QDL_PAD_EIM_D26__UART2_RX_DATA 0x1b0b1
1025 MX6QDL_PAD_EIM_D27__UART2_TX_DATA 0x1b0b1
1026 MX6QDL_PAD_EIM_D28__UART2_DTE_CTS_B 0x1b0b1
1027 MX6QDL_PAD_EIM_D29__UART2_DTE_RTS_B 0x1b0b1
1028 >;
1029 };
1030 };
1031
Huang Shijiec2797982013-07-12 15:56:11 +0800[diff] [blame]1032 uart3 {
1033 pinctrl_uart3_1: uart3grp-1 {
1034 fsl,pins = <
1035 MX6QDL_PAD_SD4_CLK__UART3_RX_DATA 0x1b0b1
1036 MX6QDL_PAD_SD4_CMD__UART3_TX_DATA 0x1b0b1
1037 MX6QDL_PAD_EIM_D30__UART3_CTS_B 0x1b0b1
1038 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1039 >;
1040 };
Fabio Estevam5ff883412013-07-12 09:49:31 -0300[diff] [blame]1041
1042 pinctrl_uart3_2: uart3grp-2 {
1043 fsl,pins = <
1044 MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1
1045 MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1
1046 MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1
1047 MX6QDL_PAD_EIM_EB3__UART3_RTS_B 0x1b0b1
1048 >;
1049 };
Huang Shijiec2797982013-07-12 15:56:11 +0800[diff] [blame]1050 };
1051
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]1052 uart4 {
1053 pinctrl_uart4_1: uart4grp-1 {
1054 fsl,pins = <
1055 MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1
1056 MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1
1057 >;
1058 };
1059 };
1060
1061 usbotg {
1062 pinctrl_usbotg_1: usbotggrp-1 {
1063 fsl,pins = <
1064 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
1065 >;
1066 };
1067
1068 pinctrl_usbotg_2: usbotggrp-2 {
1069 fsl,pins = <
1070 MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059
1071 >;
1072 };
1073 };
1074
Shawn Guob72ce922013-07-12 11:38:50 +0800[diff] [blame]1075 usbh2 {
1076 pinctrl_usbh2_1: usbh2grp-1 {
1077 fsl,pins = <
1078 MX6QDL_PAD_RGMII_TXC__USB_H2_DATA 0x40013030
1079 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40013030
1080 >;
1081 };
1082
1083 pinctrl_usbh2_2: usbh2grp-2 {
1084 fsl,pins = <
1085 MX6QDL_PAD_RGMII_TX_CTL__USB_H2_STROBE 0x40017030
1086 >;
1087 };
1088 };
1089
1090 usbh3 {
1091 pinctrl_usbh3_1: usbh3grp-1 {
1092 fsl,pins = <
1093 MX6QDL_PAD_RGMII_RX_CTL__USB_H3_DATA 0x40013030
1094 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40013030
1095 >;
1096 };
1097
1098 pinctrl_usbh3_2: usbh3grp-2 {
1099 fsl,pins = <
1100 MX6QDL_PAD_RGMII_RXC__USB_H3_STROBE 0x40017030
1101 >;
1102 };
1103 };
1104
Fabio Estevam26c3b652013-07-12 09:49:30 -0300[diff] [blame]1105 usdhc1 {
1106 pinctrl_usdhc1_1: usdhc1grp-1 {
1107 fsl,pins = <
1108 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1109 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1110 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1111 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1112 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1113 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1114 MX6QDL_PAD_NANDF_D0__SD1_DATA4 0x17059
1115 MX6QDL_PAD_NANDF_D1__SD1_DATA5 0x17059
1116 MX6QDL_PAD_NANDF_D2__SD1_DATA6 0x17059
1117 MX6QDL_PAD_NANDF_D3__SD1_DATA7 0x17059
1118 >;
1119 };
1120
1121 pinctrl_usdhc1_2: usdhc1grp-2 {
1122 fsl,pins = <
1123 MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059
1124 MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059
1125 MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059
1126 MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059
1127 MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059
1128 MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059
1129 >;
1130 };
1131 };
1132
Shawn Guoc56009b2f2013-07-11 13:58:36 +0800[diff] [blame]1133 usdhc2 {
1134 pinctrl_usdhc2_1: usdhc2grp-1 {
1135 fsl,pins = <
1136 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1137 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1138 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1139 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1140 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1141 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1142 MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059
1143 MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059
1144 MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059
1145 MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059
1146 >;
1147 };
1148
1149 pinctrl_usdhc2_2: usdhc2grp-2 {
1150 fsl,pins = <
1151 MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059
1152 MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059
1153 MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059
1154 MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059
1155 MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059
1156 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059
1157 >;
1158 };
1159 };
1160
1161 usdhc3 {
1162 pinctrl_usdhc3_1: usdhc3grp-1 {
1163 fsl,pins = <
1164 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1165 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1166 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1167 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1168 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1169 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1170 MX6QDL_PAD_SD3_DAT4__SD3_DATA4 0x17059
1171 MX6QDL_PAD_SD3_DAT5__SD3_DATA5 0x17059
1172 MX6QDL_PAD_SD3_DAT6__SD3_DATA6 0x17059
1173 MX6QDL_PAD_SD3_DAT7__SD3_DATA7 0x17059
1174 >;
1175 };
1176
1177 pinctrl_usdhc3_2: usdhc3grp-2 {
1178 fsl,pins = <
1179 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
1180 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
1181 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
1182 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
1183 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
1184 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
1185 >;
1186 };
1187 };
1188
1189 usdhc4 {
1190 pinctrl_usdhc4_1: usdhc4grp-1 {
1191 fsl,pins = <
1192 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1193 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1194 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1195 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1196 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1197 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1198 MX6QDL_PAD_SD4_DAT4__SD4_DATA4 0x17059
1199 MX6QDL_PAD_SD4_DAT5__SD4_DATA5 0x17059
1200 MX6QDL_PAD_SD4_DAT6__SD4_DATA6 0x17059
1201 MX6QDL_PAD_SD4_DAT7__SD4_DATA7 0x17059
1202 >;
1203 };
1204
1205 pinctrl_usdhc4_2: usdhc4grp-2 {
1206 fsl,pins = <
1207 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
1208 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
1209 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
1210 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
1211 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
1212 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
1213 >;
1214 };
1215 };
1216
1217 weim {
1218 pinctrl_weim_cs0_1: weim_cs0grp-1 {
1219 fsl,pins = <
1220 MX6QDL_PAD_EIM_CS0__EIM_CS0_B 0xb0b1
1221 >;
1222 };
1223
1224 pinctrl_weim_nor_1: weim_norgrp-1 {
1225 fsl,pins = <
1226 MX6QDL_PAD_EIM_OE__EIM_OE_B 0xb0b1
1227 MX6QDL_PAD_EIM_RW__EIM_RW 0xb0b1
1228 MX6QDL_PAD_EIM_WAIT__EIM_WAIT_B 0xb060
1229 /* data */
1230 MX6QDL_PAD_EIM_D16__EIM_DATA16 0x1b0b0
1231 MX6QDL_PAD_EIM_D17__EIM_DATA17 0x1b0b0
1232 MX6QDL_PAD_EIM_D18__EIM_DATA18 0x1b0b0
1233 MX6QDL_PAD_EIM_D19__EIM_DATA19 0x1b0b0
1234 MX6QDL_PAD_EIM_D20__EIM_DATA20 0x1b0b0
1235 MX6QDL_PAD_EIM_D21__EIM_DATA21 0x1b0b0
1236 MX6QDL_PAD_EIM_D22__EIM_DATA22 0x1b0b0
1237 MX6QDL_PAD_EIM_D23__EIM_DATA23 0x1b0b0
1238 MX6QDL_PAD_EIM_D24__EIM_DATA24 0x1b0b0
1239 MX6QDL_PAD_EIM_D25__EIM_DATA25 0x1b0b0
1240 MX6QDL_PAD_EIM_D26__EIM_DATA26 0x1b0b0
1241 MX6QDL_PAD_EIM_D27__EIM_DATA27 0x1b0b0
1242 MX6QDL_PAD_EIM_D28__EIM_DATA28 0x1b0b0
1243 MX6QDL_PAD_EIM_D29__EIM_DATA29 0x1b0b0
1244 MX6QDL_PAD_EIM_D30__EIM_DATA30 0x1b0b0
1245 MX6QDL_PAD_EIM_D31__EIM_DATA31 0x1b0b0
1246 /* address */
1247 MX6QDL_PAD_EIM_A23__EIM_ADDR23 0xb0b1
1248 MX6QDL_PAD_EIM_A22__EIM_ADDR22 0xb0b1
1249 MX6QDL_PAD_EIM_A21__EIM_ADDR21 0xb0b1
1250 MX6QDL_PAD_EIM_A20__EIM_ADDR20 0xb0b1
1251 MX6QDL_PAD_EIM_A19__EIM_ADDR19 0xb0b1
1252 MX6QDL_PAD_EIM_A18__EIM_ADDR18 0xb0b1
1253 MX6QDL_PAD_EIM_A17__EIM_ADDR17 0xb0b1
1254 MX6QDL_PAD_EIM_A16__EIM_ADDR16 0xb0b1
1255 MX6QDL_PAD_EIM_DA15__EIM_AD15 0xb0b1
1256 MX6QDL_PAD_EIM_DA14__EIM_AD14 0xb0b1
1257 MX6QDL_PAD_EIM_DA13__EIM_AD13 0xb0b1
1258 MX6QDL_PAD_EIM_DA12__EIM_AD12 0xb0b1
1259 MX6QDL_PAD_EIM_DA11__EIM_AD11 0xb0b1
1260 MX6QDL_PAD_EIM_DA10__EIM_AD10 0xb0b1
1261 MX6QDL_PAD_EIM_DA9__EIM_AD09 0xb0b1
1262 MX6QDL_PAD_EIM_DA8__EIM_AD08 0xb0b1
1263 MX6QDL_PAD_EIM_DA7__EIM_AD07 0xb0b1
1264 MX6QDL_PAD_EIM_DA6__EIM_AD06 0xb0b1
1265 MX6QDL_PAD_EIM_DA5__EIM_AD05 0xb0b1
1266 MX6QDL_PAD_EIM_DA4__EIM_AD04 0xb0b1
1267 MX6QDL_PAD_EIM_DA3__EIM_AD03 0xb0b1
1268 MX6QDL_PAD_EIM_DA2__EIM_AD02 0xb0b1
1269 MX6QDL_PAD_EIM_DA1__EIM_AD01 0xb0b1
1270 MX6QDL_PAD_EIM_DA0__EIM_AD00 0xb0b1
1271 >;
1272 };
1273 };
1274 };
1275
Steffen Trumtrar41c04342013-03-28 16:23:35 +0100[diff] [blame]1276 ldb: ldb@020e0008 {
1277 #address-cells = <1>;
1278 #size-cells = <0>;
1279 compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb";
1280 gpr = <&gpr>;
1281 status = "disabled";
1282
1283 lvds-channel@0 {
1284 reg = <0>;
Steffen Trumtrar41c04342013-03-28 16:23:35 +0100[diff] [blame]1285 status = "disabled";
1286 };
1287
1288 lvds-channel@1 {
1289 reg = <1>;
Steffen Trumtrar41c04342013-03-28 16:23:35 +0100[diff] [blame]1290 status = "disabled";
1291 };
1292 };
1293
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1294 dcic1: dcic@020e4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1295 reg = <0x020e4000 0x4000>;
1296 interrupts = <0 124 0x04>;
1297 };
1298
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1299 dcic2: dcic@020e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1300 reg = <0x020e8000 0x4000>;
1301 interrupts = <0 125 0x04>;
1302 };
1303
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1304 sdma: sdma@020ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1305 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
1306 reg = <0x020ec000 0x4000>;
1307 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1308 clocks = <&clks 155>, <&clks 155>;
1309 clock-names = "ipg", "ahb";
Huang Shijiefb72bb22013-07-02 10:15:29 +0800[diff] [blame]1310 #dma-cells = <3>;
Fabio Estevamd6b9c592013-01-17 12:13:25 -0200[diff] [blame]1311 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1312 };
1313 };
1314
1315 aips-bus@02100000 { /* AIPS2 */
1316 compatible = "fsl,aips-bus", "simple-bus";
1317 #address-cells = <1>;
1318 #size-cells = <1>;
1319 reg = <0x02100000 0x100000>;
1320 ranges;
1321
1322 caam@02100000 {
1323 reg = <0x02100000 0x40000>;
1324 interrupts = <0 105 0x04 0 106 0x04>;
1325 };
1326
1327 aipstz@0217c000 { /* AIPSTZ2 */
1328 reg = <0x0217c000 0x4000>;
1329 };
1330
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1331 usbotg: usb@02184000 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1332 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1333 reg = <0x02184000 0x200>;
1334 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1335 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1336 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]1337 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1338 status = "disabled";
1339 };
1340
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1341 usbh1: usb@02184200 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1342 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1343 reg = <0x02184200 0x200>;
1344 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1345 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1346 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]1347 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1348 status = "disabled";
1349 };
1350
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1351 usbh2: usb@02184400 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1352 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1353 reg = <0x02184400 0x200>;
1354 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1355 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]1356 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1357 status = "disabled";
1358 };
1359
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1360 usbh3: usb@02184600 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1361 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
1362 reg = <0x02184600 0x200>;
1363 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1364 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]1365 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]1366 status = "disabled";
1367 };
1368
Shawn Guo60984bd2013-04-28 09:59:54 +0800[diff] [blame]1369 usbmisc: usbmisc@02184800 {
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]1370 #index-cells = <1>;
1371 compatible = "fsl,imx6q-usbmisc";
1372 reg = <0x02184800 0x200>;
1373 clocks = <&clks 162>;
1374 };
1375
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1376 fec: ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1377 compatible = "fsl,imx6q-fec";
1378 reg = <0x02188000 0x4000>;
1379 interrupts = <0 118 0x04 0 119 0x04>;
Frank Li8dd5c662013-02-05 14:21:06 +0800[diff] [blame]1380 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
Frank Li76298382012-10-30 18:24:57 +0000[diff] [blame]1381 clock-names = "ipg", "ahb", "ptp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1382 status = "disabled";
1383 };
1384
1385 mlb@0218c000 {
1386 reg = <0x0218c000 0x4000>;
1387 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
1388 };
1389
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1390 usdhc1: usdhc@02190000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1391 compatible = "fsl,imx6q-usdhc";
1392 reg = <0x02190000 0x4000>;
1393 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1394 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
1395 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]1396 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1397 status = "disabled";
1398 };
1399
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1400 usdhc2: usdhc@02194000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1401 compatible = "fsl,imx6q-usdhc";
1402 reg = <0x02194000 0x4000>;
1403 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1404 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
1405 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]1406 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1407 status = "disabled";
1408 };
1409
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1410 usdhc3: usdhc@02198000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1411 compatible = "fsl,imx6q-usdhc";
1412 reg = <0x02198000 0x4000>;
1413 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1414 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
1415 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]1416 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1417 status = "disabled";
1418 };
1419
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1420 usdhc4: usdhc@0219c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1421 compatible = "fsl,imx6q-usdhc";
1422 reg = <0x0219c000 0x4000>;
1423 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1424 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
1425 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]1426 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1427 status = "disabled";
1428 };
1429
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1430 i2c1: i2c@021a0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1431 #address-cells = <1>;
1432 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]1433 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1434 reg = <0x021a0000 0x4000>;
1435 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1436 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1437 status = "disabled";
1438 };
1439
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1440 i2c2: i2c@021a4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1441 #address-cells = <1>;
1442 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]1443 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1444 reg = <0x021a4000 0x4000>;
1445 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1446 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1447 status = "disabled";
1448 };
1449
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1450 i2c3: i2c@021a8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1451 #address-cells = <1>;
1452 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]1453 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1454 reg = <0x021a8000 0x4000>;
1455 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1456 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1457 status = "disabled";
1458 };
1459
1460 romcp@021ac000 {
1461 reg = <0x021ac000 0x4000>;
1462 };
1463
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1464 mmdc0: mmdc@021b0000 { /* MMDC0 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1465 compatible = "fsl,imx6q-mmdc";
1466 reg = <0x021b0000 0x4000>;
1467 };
1468
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1469 mmdc1: mmdc@021b4000 { /* MMDC1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1470 reg = <0x021b4000 0x4000>;
1471 };
1472
Huang Shijie05e3f8e2013-05-28 14:20:09 +0800[diff] [blame]1473 weim: weim@021b8000 {
1474 compatible = "fsl,imx6q-weim";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1475 reg = <0x021b8000 0x4000>;
1476 interrupts = <0 14 0x04>;
Huang Shijie05e3f8e2013-05-28 14:20:09 +0800[diff] [blame]1477 clocks = <&clks 196>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1478 };
1479
1480 ocotp@021bc000 {
Shawn Guo96574a62013-01-08 14:25:14 +0800[diff] [blame]1481 compatible = "fsl,imx6q-ocotp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1482 reg = <0x021bc000 0x4000>;
1483 };
1484
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1485 tzasc@021d0000 { /* TZASC1 */
1486 reg = <0x021d0000 0x4000>;
1487 interrupts = <0 108 0x04>;
1488 };
1489
1490 tzasc@021d4000 { /* TZASC2 */
1491 reg = <0x021d4000 0x4000>;
1492 interrupts = <0 109 0x04>;
1493 };
1494
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]1495 audmux: audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]1496 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1497 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]1498 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1499 };
1500
1501 mipi@021dc000 { /* MIPI-CSI */
1502 reg = <0x021dc000 0x4000>;
1503 };
1504
1505 mipi@021e0000 { /* MIPI-DSI */
1506 reg = <0x021e0000 0x4000>;
1507 };
1508
1509 vdoa@021e4000 {
1510 reg = <0x021e4000 0x4000>;
1511 interrupts = <0 18 0x04>;
1512 };
1513
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1514 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1515 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1516 reg = <0x021e8000 0x4000>;
1517 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1518 clocks = <&clks 160>, <&clks 161>;
1519 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]1520 dmas = <&sdma 27 4 0>, <&sdma 28 4 0>;
1521 dma-names = "rx", "tx";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1522 status = "disabled";
1523 };
1524
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1525 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1526 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1527 reg = <0x021ec000 0x4000>;
1528 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1529 clocks = <&clks 160>, <&clks 161>;
1530 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]1531 dmas = <&sdma 29 4 0>, <&sdma 30 4 0>;
1532 dma-names = "rx", "tx";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1533 status = "disabled";
1534 };
1535
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1536 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1537 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1538 reg = <0x021f0000 0x4000>;
1539 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1540 clocks = <&clks 160>, <&clks 161>;
1541 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]1542 dmas = <&sdma 31 4 0>, <&sdma 32 4 0>;
1543 dma-names = "rx", "tx";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1544 status = "disabled";
1545 };
1546
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1547 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1548 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1549 reg = <0x021f4000 0x4000>;
1550 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1551 clocks = <&clks 160>, <&clks 161>;
1552 clock-names = "ipg", "per";
Huang Shijie72a5ceb2013-07-12 18:02:09 +0800[diff] [blame]1553 dmas = <&sdma 33 4 0>, <&sdma 34 4 0>;
1554 dma-names = "rx", "tx";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1555 status = "disabled";
1556 };
1557 };
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]1558
1559 ipu1: ipu@02400000 {
1560 #crtc-cells = <1>;
1561 compatible = "fsl,imx6q-ipu";
1562 reg = <0x02400000 0x400000>;
1563 interrupts = <0 6 0x4 0 5 0x4>;
1564 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1565 clock-names = "bus", "di0", "di1";
Philipp Zabel09ebf362013-03-28 17:35:20 +0100[diff] [blame]1566 resets = <&src 2>;
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]1567 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1568 };
1569};