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gerrit-public.fairphone.software / kernel / msm / 379070491e1e744a59e69e5bcf3765012d15ecb4 / . / include / asm-powerpc / cputable.h
blob: 4fd76898975b7998d1fd2b86a0bc5ebbe2b7e584 [file] [log] [blame]
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]1#ifndef __ASM_POWERPC_CPUTABLE_H
2#define __ASM_POWERPC_CPUTABLE_H
3
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]4#define PPC_FEATURE_32 0x80000000
5#define PPC_FEATURE_64 0x40000000
6#define PPC_FEATURE_601_INSTR 0x20000000
7#define PPC_FEATURE_HAS_ALTIVEC 0x10000000
8#define PPC_FEATURE_HAS_FPU 0x08000000
9#define PPC_FEATURE_HAS_MMU 0x04000000
10#define PPC_FEATURE_HAS_4xxMAC 0x02000000
11#define PPC_FEATURE_UNIFIED_CACHE 0x01000000
12#define PPC_FEATURE_HAS_SPE 0x00800000
13#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000
14#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000
Paul Mackerras98599012005-10-22 16:51:34 +1000[diff] [blame]15#define PPC_FEATURE_NO_TB 0x00100000
Paul Mackerrasa7ddc5e2005-11-10 14:29:18 +1100[diff] [blame]16#define PPC_FEATURE_POWER4 0x00080000
17#define PPC_FEATURE_POWER5 0x00040000
18#define PPC_FEATURE_POWER5_PLUS 0x00020000
19#define PPC_FEATURE_CELL 0x00010000
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]20#define PPC_FEATURE_BOOKE 0x00008000
Benjamin Herrenschmidtaa5cb022006-03-01 15:07:07 +1100[diff] [blame]21#define PPC_FEATURE_SMT 0x00004000
22#define PPC_FEATURE_ICACHE_SNOOP 0x00002000
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]23#define PPC_FEATURE_ARCH_2_05 0x00001000
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]24#define PPC_FEATURE_PA6T 0x00000800
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]25#define PPC_FEATURE_HAS_DFP 0x00000400
26#define PPC_FEATURE_POWER6_EXT 0x00000200
Michael Neulinge952e6c2008-06-18 10:47:26 +1000[diff] [blame]27#define PPC_FEATURE_ARCH_2_06 0x00000100
Michael Neulingb962ce92008-06-25 14:07:18 +1000[diff] [blame]28#define PPC_FEATURE_HAS_VSX 0x00000080
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]29
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]30#define PPC_FEATURE_TRUE_LE 0x00000002
31#define PPC_FEATURE_PPC_LE 0x00000001
32
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]33#ifdef __KERNEL__
Adrian Bunkd1cdcf22008-06-24 03:48:21 +1000[diff] [blame]34
35#include <asm/asm-compat.h>
Michael Ellermanc5157e52008-06-24 11:32:39 +1000[diff] [blame]36#include <asm/feature-fixups.h>
Adrian Bunkd1cdcf22008-06-24 03:48:21 +1000[diff] [blame]37
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]38#ifndef __ASSEMBLY__
39
40/* This structure can grow, it's real size is used by head.S code
41 * via the mkdefs mechanism.
42 */
43struct cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]44
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]45typedef void (*cpu_setup_t)(unsigned long offset, struct cpu_spec* spec);
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]46typedef void (*cpu_restore_t)(void);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]47
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]48enum powerpc_oprofile_type {
Andy Whitcroft7a45fb12006-01-13 12:35:49 +0000[diff] [blame]49 PPC_OPROFILE_INVALID = 0,
50 PPC_OPROFILE_RS64 = 1,
51 PPC_OPROFILE_POWER4 = 2,
52 PPC_OPROFILE_G4 = 3,
Andy Fleming39aef682008-02-04 18:27:55 -0600[diff] [blame]53 PPC_OPROFILE_FSL_EMB = 4,
Maynard Johnson18f21902006-11-20 18:45:16 +0100[diff] [blame]54 PPC_OPROFILE_CELL = 5,
Olof Johansson25fc5302007-04-18 16:38:21 +1000[diff] [blame]55 PPC_OPROFILE_PA6T = 6,
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]56};
57
Olof Johansson1bd2e5a2007-01-28 21:23:54 -0600[diff] [blame]58enum powerpc_pmc_type {
59 PPC_PMC_DEFAULT = 0,
60 PPC_PMC_IBM = 1,
61 PPC_PMC_PA6T = 2,
62};
63
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +1100[diff] [blame]64struct pt_regs;
65
66extern int machine_check_generic(struct pt_regs *regs);
67extern int machine_check_4xx(struct pt_regs *regs);
68extern int machine_check_440A(struct pt_regs *regs);
69extern int machine_check_e500(struct pt_regs *regs);
70extern int machine_check_e200(struct pt_regs *regs);
71
Paul Mackerras87a72f92007-10-04 14:18:01 +1000[diff] [blame]72/* NOTE WELL: Update identify_cpu() if fields are added or removed! */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]73struct cpu_spec {
74 /* CPU is matched via (PVR & pvr_mask) == pvr_value */
75 unsigned int pvr_mask;
76 unsigned int pvr_value;
77
78 char *cpu_name;
79 unsigned long cpu_features; /* Kernel features */
80 unsigned int cpu_user_features; /* Userland features */
81
82 /* cache line sizes */
83 unsigned int icache_bsize;
84 unsigned int dcache_bsize;
85
86 /* number of performance monitor counters */
87 unsigned int num_pmcs;
Olof Johansson1bd2e5a2007-01-28 21:23:54 -0600[diff] [blame]88 enum powerpc_pmc_type pmc_type;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]89
90 /* this is called to initialize various CPU bits like L1 cache,
91 * BHT, SPD, etc... from head.S before branching to identify_machine
92 */
93 cpu_setup_t cpu_setup;
Olof Johanssonf39b7a52006-08-11 00:07:08 -0500[diff] [blame]94 /* Used to restore cpu setup on secondary processors and at resume */
95 cpu_restore_t cpu_restore;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]96
97 /* Used by oprofile userspace to select the right counters */
98 char *oprofile_cpu_type;
99
100 /* Processor specific oprofile operations */
Anton Blanchard32a33992006-01-09 15:41:31 +1100[diff] [blame]101 enum powerpc_oprofile_type oprofile_type;
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]102
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]103 /* Bit locations inside the mmcra change */
104 unsigned long oprofile_mmcra_sihv;
105 unsigned long oprofile_mmcra_sipr;
106
107 /* Bits to clear during an oprofile exception */
108 unsigned long oprofile_mmcra_clear;
109
Paul Mackerras80f15dc2006-01-14 10:11:39 +1100[diff] [blame]110 /* Name of processor class, for the ELF AT_PLATFORM entry */
111 char *platform;
Benjamin Herrenschmidt47c0bd12007-12-21 15:39:21 +1100[diff] [blame]112
113 /* Processor specific machine check handling. Return negative
114 * if the error is fatal, 1 if it was fully recovered and 0 to
115 * pass up (not CPU originated) */
116 int (*machine_check)(struct pt_regs *regs);
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]117};
118
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]119extern struct cpu_spec *cur_cpu_spec;
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]120
Benjamin Herrenschmidt42c4aaa2006-10-24 16:42:40 +1000[diff] [blame]121extern unsigned int __start___ftr_fixup, __stop___ftr_fixup;
122
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]123extern struct cpu_spec *identify_cpu(unsigned long offset, unsigned int pvr);
Benjamin Herrenschmidt0909c8c2006-10-20 11:47:18 +1000[diff] [blame]124extern void do_feature_fixups(unsigned long value, void *fixup_start,
125 void *fixup_end);
Paul Mackerras9b6b5632005-10-06 12:06:20 +1000[diff] [blame]126
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]127#endif /* __ASSEMBLY__ */
128
129/* CPU kernel features */
130
131/* Retain the 32b definitions all use bottom half of word */
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]132#define CPU_FTR_COHERENT_ICACHE ASM_CONST(0x0000000000000001)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]133#define CPU_FTR_L2CR ASM_CONST(0x0000000000000002)
134#define CPU_FTR_SPEC7450 ASM_CONST(0x0000000000000004)
135#define CPU_FTR_ALTIVEC ASM_CONST(0x0000000000000008)
136#define CPU_FTR_TAU ASM_CONST(0x0000000000000010)
137#define CPU_FTR_CAN_DOZE ASM_CONST(0x0000000000000020)
138#define CPU_FTR_USE_TB ASM_CONST(0x0000000000000040)
Kumar Galaaba11fc2008-06-19 09:40:31 -0500[diff] [blame]139#define CPU_FTR_L2CSR ASM_CONST(0x0000000000000080)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]140#define CPU_FTR_601 ASM_CONST(0x0000000000000100)
141#define CPU_FTR_HPTE_TABLE ASM_CONST(0x0000000000000200)
142#define CPU_FTR_CAN_NAP ASM_CONST(0x0000000000000400)
143#define CPU_FTR_L3CR ASM_CONST(0x0000000000000800)
144#define CPU_FTR_L3_DISABLE_NAP ASM_CONST(0x0000000000001000)
145#define CPU_FTR_NAP_DISABLE_L2_PR ASM_CONST(0x0000000000002000)
146#define CPU_FTR_DUAL_PLL_750FX ASM_CONST(0x0000000000004000)
147#define CPU_FTR_NO_DPM ASM_CONST(0x0000000000008000)
148#define CPU_FTR_HAS_HIGH_BATS ASM_CONST(0x0000000000010000)
149#define CPU_FTR_NEED_COHERENT ASM_CONST(0x0000000000020000)
150#define CPU_FTR_NO_BTIC ASM_CONST(0x0000000000040000)
151#define CPU_FTR_BIG_PHYS ASM_CONST(0x0000000000080000)
Michael Ellerman3d159102006-03-21 20:45:58 +1100[diff] [blame]152#define CPU_FTR_NODSISRALIGN ASM_CONST(0x0000000000100000)
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]153#define CPU_FTR_PPC_LE ASM_CONST(0x0000000000200000)
154#define CPU_FTR_REAL_LE ASM_CONST(0x0000000000400000)
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame]155#define CPU_FTR_FPU_UNAVAILABLE ASM_CONST(0x0000000000800000)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]156#define CPU_FTR_UNIFIED_ID_CACHE ASM_CONST(0x0000000001000000)
Kumar Gala5e14d212007-09-13 01:44:20 -0500[diff] [blame]157#define CPU_FTR_SPE ASM_CONST(0x0000000002000000)
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]158#define CPU_FTR_NEED_PAIRED_STWCX ASM_CONST(0x0000000004000000)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]159#define CPU_FTR_LWSYNC ASM_CONST(0x0000000008000000)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]160
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]161/*
162 * Add the 64-bit processor unique features in the top half of the word;
163 * on 32-bit, make the names available but defined to be 0.
164 */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]165#ifdef __powerpc64__
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]166#define LONG_ASM_CONST(x) ASM_CONST(x)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]167#else
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]168#define LONG_ASM_CONST(x) 0
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]169#endif
170
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]171#define CPU_FTR_SLB LONG_ASM_CONST(0x0000000100000000)
172#define CPU_FTR_16M_PAGE LONG_ASM_CONST(0x0000000200000000)
173#define CPU_FTR_TLBIEL LONG_ASM_CONST(0x0000000400000000)
174#define CPU_FTR_NOEXECUTE LONG_ASM_CONST(0x0000000800000000)
175#define CPU_FTR_IABR LONG_ASM_CONST(0x0000002000000000)
176#define CPU_FTR_MMCRA LONG_ASM_CONST(0x0000004000000000)
177#define CPU_FTR_CTRL LONG_ASM_CONST(0x0000008000000000)
178#define CPU_FTR_SMT LONG_ASM_CONST(0x0000010000000000)
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]179#define CPU_FTR_LOCKLESS_TLBIE LONG_ASM_CONST(0x0000040000000000)
180#define CPU_FTR_CI_LARGE_PAGE LONG_ASM_CONST(0x0000100000000000)
181#define CPU_FTR_PAUSE_ZERO LONG_ASM_CONST(0x0000200000000000)
182#define CPU_FTR_PURR LONG_ASM_CONST(0x0000400000000000)
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]183#define CPU_FTR_CELL_TB_BUG LONG_ASM_CONST(0x0000800000000000)
Paul Mackerras974a76f2006-11-10 20:38:53 +1100[diff] [blame]184#define CPU_FTR_SPURR LONG_ASM_CONST(0x0001000000000000)
Anton Blanchard4c1985572006-12-08 17:46:58 +1100[diff] [blame]185#define CPU_FTR_DSCR LONG_ASM_CONST(0x0002000000000000)
Paul Mackerras1189be62007-10-11 20:37:10 +1000[diff] [blame]186#define CPU_FTR_1T_SEGMENT LONG_ASM_CONST(0x0004000000000000)
Olof Johanssonf66bce52007-10-16 00:58:59 +1000[diff] [blame]187#define CPU_FTR_NO_SLBIE_B LONG_ASM_CONST(0x0008000000000000)
Michael Neulingb962ce92008-06-25 14:07:18 +1000[diff] [blame]188#define CPU_FTR_VSX LONG_ASM_CONST(0x0010000000000000)
Dave Kleikamp37907042008-07-08 00:28:53 +1000[diff] [blame^]189#define CPU_FTR_SAO LONG_ASM_CONST(0x0020000000000000)
Paul Mackerras3965f8c2006-06-28 13:50:39 +1000[diff] [blame]190
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]191#ifndef __ASSEMBLY__
192
Stephen Rothwell04704662006-11-30 11:46:22 +1100[diff] [blame]193#define CPU_FTR_PPCAS_ARCH_V2 (CPU_FTR_SLB | \
194 CPU_FTR_TLBIEL | CPU_FTR_NOEXECUTE | \
195 CPU_FTR_NODSISRALIGN | CPU_FTR_16M_PAGE)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]196
197/* We only set the altivec features if the kernel was compiled with altivec
198 * support
199 */
200#ifdef CONFIG_ALTIVEC
201#define CPU_FTR_ALTIVEC_COMP CPU_FTR_ALTIVEC
202#define PPC_FEATURE_HAS_ALTIVEC_COMP PPC_FEATURE_HAS_ALTIVEC
203#else
204#define CPU_FTR_ALTIVEC_COMP 0
205#define PPC_FEATURE_HAS_ALTIVEC_COMP 0
206#endif
207
Michael Neulingb962ce92008-06-25 14:07:18 +1000[diff] [blame]208/* We only set the VSX features if the kernel was compiled with VSX
209 * support
210 */
211#ifdef CONFIG_VSX
212#define CPU_FTR_VSX_COMP CPU_FTR_VSX
213#define PPC_FEATURE_HAS_VSX_COMP PPC_FEATURE_HAS_VSX
214#else
215#define CPU_FTR_VSX_COMP 0
216#define PPC_FEATURE_HAS_VSX_COMP 0
217#endif
218
Kumar Gala5e14d212007-09-13 01:44:20 -0500[diff] [blame]219/* We only set the spe features if the kernel was compiled with spe
220 * support
221 */
222#ifdef CONFIG_SPE
223#define CPU_FTR_SPE_COMP CPU_FTR_SPE
224#define PPC_FEATURE_HAS_SPE_COMP PPC_FEATURE_HAS_SPE
225#define PPC_FEATURE_HAS_EFP_SINGLE_COMP PPC_FEATURE_HAS_EFP_SINGLE
226#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP PPC_FEATURE_HAS_EFP_DOUBLE
227#else
228#define CPU_FTR_SPE_COMP 0
229#define PPC_FEATURE_HAS_SPE_COMP 0
230#define PPC_FEATURE_HAS_EFP_SINGLE_COMP 0
231#define PPC_FEATURE_HAS_EFP_DOUBLE_COMP 0
232#endif
233
Scott Wood11af1192007-09-14 15:32:14 -0500[diff] [blame]234/* We need to mark all pages as being coherent if we're SMP or we have a
235 * 74[45]x and an MPC107 host bridge. Also 83xx and PowerQUICC II
236 * require it for PCI "streaming/prefetch" to work properly.
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]237 */
Kumar Gala1775dbb2006-02-22 09:46:02 -0600[diff] [blame]238#if defined(CONFIG_SMP) || defined(CONFIG_MPC10X_BRIDGE) \
Scott Wood11af1192007-09-14 15:32:14 -0500[diff] [blame]239 || defined(CONFIG_PPC_83xx) || defined(CONFIG_8260)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]240#define CPU_FTR_COMMON CPU_FTR_NEED_COHERENT
241#else
242#define CPU_FTR_COMMON 0
243#endif
244
245/* The powersave features NAP & DOZE seems to confuse BDI when
246 debugging. So if a BDI is used, disable theses
247 */
248#ifndef CONFIG_BDI_SWITCH
249#define CPU_FTR_MAYBE_CAN_DOZE CPU_FTR_CAN_DOZE
250#define CPU_FTR_MAYBE_CAN_NAP CPU_FTR_CAN_NAP
251#else
252#define CPU_FTR_MAYBE_CAN_DOZE 0
253#define CPU_FTR_MAYBE_CAN_NAP 0
254#endif
255
256#define CLASSIC_PPC (!defined(CONFIG_8xx) && !defined(CONFIG_4xx) && \
257 !defined(CONFIG_POWER3) && !defined(CONFIG_POWER4) && \
258 !defined(CONFIG_BOOKE))
259
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]260#define CPU_FTRS_PPC601 (CPU_FTR_COMMON | CPU_FTR_601 | CPU_FTR_HPTE_TABLE | \
261 CPU_FTR_COHERENT_ICACHE | CPU_FTR_UNIFIED_ID_CACHE)
262#define CPU_FTRS_603 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]263 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]264 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]265#define CPU_FTRS_604 (CPU_FTR_COMMON | \
Kumar Galaaba11fc2008-06-19 09:40:31 -0500[diff] [blame]266 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]267#define CPU_FTRS_740_NOTAU (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]268 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]269 CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]270#define CPU_FTRS_740 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]271 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]272 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
273 CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]274#define CPU_FTRS_750 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]275 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]276 CPU_FTR_TAU | CPU_FTR_HPTE_TABLE | CPU_FTR_MAYBE_CAN_NAP | \
277 CPU_FTR_PPC_LE)
Josh Boyerb6f41cc2007-07-03 02:06:53 +1000[diff] [blame]278#define CPU_FTRS_750CL (CPU_FTRS_750 | CPU_FTR_HAS_HIGH_BATS)
279#define CPU_FTRS_750FX1 (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | CPU_FTR_NO_DPM)
280#define CPU_FTRS_750FX2 (CPU_FTRS_750 | CPU_FTR_NO_DPM)
281#define CPU_FTRS_750FX (CPU_FTRS_750 | CPU_FTR_DUAL_PLL_750FX | \
282 CPU_FTR_HAS_HIGH_BATS)
283#define CPU_FTRS_750GX (CPU_FTRS_750FX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]284#define CPU_FTRS_7400_NOTAU (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]285 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
286 CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]287 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]288#define CPU_FTRS_7400 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]289 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | CPU_FTR_L2CR | \
290 CPU_FTR_TAU | CPU_FTR_ALTIVEC_COMP | CPU_FTR_HPTE_TABLE | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]291 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]292#define CPU_FTRS_7450_20 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]293 CPU_FTR_USE_TB | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
294 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]295 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]296#define CPU_FTRS_7450_21 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]297 CPU_FTR_USE_TB | \
298 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
299 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
300 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]301 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]302#define CPU_FTRS_7450_23 (CPU_FTR_COMMON | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]303 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]304 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
305 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]306 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]307#define CPU_FTRS_7455_1 (CPU_FTR_COMMON | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]308 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]309 CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | CPU_FTR_L3CR | \
310 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | CPU_FTR_HAS_HIGH_BATS | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]311 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]312#define CPU_FTRS_7455_20 (CPU_FTR_COMMON | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]313 CPU_FTR_USE_TB | CPU_FTR_NEED_PAIRED_STWCX | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]314 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
315 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
316 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_L3_DISABLE_NAP | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]317 CPU_FTR_NEED_COHERENT | CPU_FTR_HAS_HIGH_BATS | CPU_FTR_PPC_LE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]318#define CPU_FTRS_7455 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]319 CPU_FTR_USE_TB | \
320 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
321 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
322 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]323 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]324#define CPU_FTRS_7447_10 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]325 CPU_FTR_USE_TB | \
326 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
327 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
328 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]329 CPU_FTR_NEED_COHERENT | CPU_FTR_NO_BTIC | CPU_FTR_PPC_LE | \
330 CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]331#define CPU_FTRS_7447 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]332 CPU_FTR_USE_TB | \
333 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
334 CPU_FTR_L3CR | CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
335 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]336 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]337#define CPU_FTRS_7447A (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]338 CPU_FTR_USE_TB | \
339 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
340 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
341 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]342 CPU_FTR_NEED_COHERENT | CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]343#define CPU_FTRS_7448 (CPU_FTR_COMMON | \
James.Yang3d372542007-05-02 16:34:43 -0500[diff] [blame]344 CPU_FTR_USE_TB | \
345 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_L2CR | CPU_FTR_ALTIVEC_COMP | \
346 CPU_FTR_HPTE_TABLE | CPU_FTR_SPEC7450 | \
347 CPU_FTR_NAP_DISABLE_L2_PR | CPU_FTR_HAS_HIGH_BATS | \
Becky Bruceb64f87c2007-11-10 09:17:49 +1100[diff] [blame]348 CPU_FTR_PPC_LE | CPU_FTR_NEED_PAIRED_STWCX)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]349#define CPU_FTRS_82XX (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]350 CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB)
Scott Wood11af1192007-09-14 15:32:14 -0500[diff] [blame]351#define CPU_FTRS_G2_LE (CPU_FTR_COMMON | CPU_FTR_MAYBE_CAN_DOZE | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]352 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]353#define CPU_FTRS_E300 (CPU_FTR_MAYBE_CAN_DOZE | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]354 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
355 CPU_FTR_COMMON)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]356#define CPU_FTRS_E300C2 (CPU_FTR_MAYBE_CAN_DOZE | \
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame]357 CPU_FTR_USE_TB | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_HAS_HIGH_BATS | \
358 CPU_FTR_COMMON | CPU_FTR_FPU_UNAVAILABLE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]359#define CPU_FTRS_CLASSIC32 (CPU_FTR_COMMON | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]360 CPU_FTR_USE_TB | CPU_FTR_HPTE_TABLE)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]361#define CPU_FTRS_8XX (CPU_FTR_USE_TB)
362#define CPU_FTRS_40X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
363#define CPU_FTRS_44X (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN)
Kumar Gala5e14d212007-09-13 01:44:20 -0500[diff] [blame]364#define CPU_FTRS_E200 (CPU_FTR_USE_TB | CPU_FTR_SPE_COMP | \
365 CPU_FTR_NODSISRALIGN | CPU_FTR_COHERENT_ICACHE | \
366 CPU_FTR_UNIFIED_ID_CACHE)
Kumar Galafc4033b2008-06-18 16:26:52 -0500[diff] [blame]367#define CPU_FTRS_E500 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
368 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_NODSISRALIGN)
369#define CPU_FTRS_E500_2 (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
370 CPU_FTR_SPE_COMP | CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | \
Kumar Gala5e14d212007-09-13 01:44:20 -0500[diff] [blame]371 CPU_FTR_NODSISRALIGN)
Kumar Galafc4033b2008-06-18 16:26:52 -0500[diff] [blame]372#define CPU_FTRS_E500MC (CPU_FTR_MAYBE_CAN_DOZE | CPU_FTR_USE_TB | \
Kumar Galaaba11fc2008-06-19 09:40:31 -0500[diff] [blame]373 CPU_FTR_MAYBE_CAN_NAP | CPU_FTR_BIG_PHYS | CPU_FTR_NODSISRALIGN | \
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]374 CPU_FTR_L2CSR | CPU_FTR_LWSYNC)
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]375#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
Michael Ellerman0b8e2e12006-11-23 00:46:46 +0100[diff] [blame]376
377/* 64-bit CPUs */
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]378#define CPU_FTRS_POWER3 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Paul Mackerrasfab5db92006-06-07 16:14:40 +1000[diff] [blame]379 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | CPU_FTR_PPC_LE)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]380#define CPU_FTRS_RS64 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]381 CPU_FTR_HPTE_TABLE | CPU_FTR_IABR | \
382 CPU_FTR_MMCRA | CPU_FTR_CTRL)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]383#define CPU_FTRS_POWER4 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]384 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
385 CPU_FTR_MMCRA)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]386#define CPU_FTRS_PPC970 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]387 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]388 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CAN_NAP | CPU_FTR_MMCRA)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]389#define CPU_FTRS_POWER5 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]390 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]391 CPU_FTR_MMCRA | CPU_FTR_SMT | \
392 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Michael Neulinge78dbc82006-06-08 14:42:34 +1000[diff] [blame]393 CPU_FTR_PURR)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]394#define CPU_FTRS_POWER6 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]395 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]396 CPU_FTR_MMCRA | CPU_FTR_SMT | \
397 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
Anton Blanchard4c1985572006-12-08 17:46:58 +1100[diff] [blame]398 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
399 CPU_FTR_DSCR)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]400#define CPU_FTRS_POWER7 (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Michael Neulinge952e6c2008-06-18 10:47:26 +1000[diff] [blame]401 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
402 CPU_FTR_MMCRA | CPU_FTR_SMT | \
403 CPU_FTR_COHERENT_ICACHE | CPU_FTR_LOCKLESS_TLBIE | \
404 CPU_FTR_PURR | CPU_FTR_SPURR | CPU_FTR_REAL_LE | \
Dave Kleikamp37907042008-07-08 00:28:53 +1000[diff] [blame^]405 CPU_FTR_DSCR | CPU_FTR_SAO)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]406#define CPU_FTRS_CELL (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Olof Johansson00243002006-09-06 14:35:19 -0500[diff] [blame]407 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | CPU_FTR_CTRL | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]408 CPU_FTR_ALTIVEC_COMP | CPU_FTR_MMCRA | CPU_FTR_SMT | \
Benjamin Herrenschmidt859deea2006-10-20 14:37:05 +1000[diff] [blame]409 CPU_FTR_PAUSE_ZERO | CPU_FTR_CI_LARGE_PAGE | CPU_FTR_CELL_TB_BUG)
Kumar Gala2d1b2022008-07-02 01:16:40 +1000[diff] [blame]410#define CPU_FTRS_PA6T (CPU_FTR_USE_TB | CPU_FTR_LWSYNC | \
Olof Johanssonb3ebd1d2006-09-06 14:35:57 -0500[diff] [blame]411 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2 | \
412 CPU_FTR_ALTIVEC_COMP | CPU_FTR_CI_LARGE_PAGE | \
Olof Johanssonf66bce52007-10-16 00:58:59 +1000[diff] [blame]413 CPU_FTR_PURR | CPU_FTR_REAL_LE | CPU_FTR_NO_SLBIE_B)
David Gibson4508dc22007-06-13 14:52:57 +1000[diff] [blame]414#define CPU_FTRS_COMPATIBLE (CPU_FTR_USE_TB | \
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]415 CPU_FTR_HPTE_TABLE | CPU_FTR_PPCAS_ARCH_V2)
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]416
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]417#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]418#define CPU_FTRS_POSSIBLE \
419 (CPU_FTRS_POWER3 | CPU_FTRS_RS64 | CPU_FTRS_POWER4 | \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]420 CPU_FTRS_PPC970 | CPU_FTRS_POWER5 | CPU_FTRS_POWER6 | \
Michael Neulinge952e6c2008-06-18 10:47:26 +1000[diff] [blame]421 CPU_FTRS_POWER7 | CPU_FTRS_CELL | CPU_FTRS_PA6T | \
Michael Neulingb962ce92008-06-25 14:07:18 +1000[diff] [blame]422 CPU_FTR_1T_SEGMENT | CPU_FTR_VSX)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]423#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]424enum {
425 CPU_FTRS_POSSIBLE =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]426#if CLASSIC_PPC
427 CPU_FTRS_PPC601 | CPU_FTRS_603 | CPU_FTRS_604 | CPU_FTRS_740_NOTAU |
428 CPU_FTRS_740 | CPU_FTRS_750 | CPU_FTRS_750FX1 |
429 CPU_FTRS_750FX2 | CPU_FTRS_750FX | CPU_FTRS_750GX |
430 CPU_FTRS_7400_NOTAU | CPU_FTRS_7400 | CPU_FTRS_7450_20 |
431 CPU_FTRS_7450_21 | CPU_FTRS_7450_23 | CPU_FTRS_7455_1 |
432 CPU_FTRS_7455_20 | CPU_FTRS_7455 | CPU_FTRS_7447_10 |
433 CPU_FTRS_7447 | CPU_FTRS_7447A | CPU_FTRS_82XX |
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame]434 CPU_FTRS_G2_LE | CPU_FTRS_E300 | CPU_FTRS_E300C2 |
435 CPU_FTRS_CLASSIC32 |
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]436#else
437 CPU_FTRS_GENERIC_32 |
438#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]439#ifdef CONFIG_8xx
440 CPU_FTRS_8XX |
441#endif
442#ifdef CONFIG_40x
443 CPU_FTRS_40X |
444#endif
445#ifdef CONFIG_44x
446 CPU_FTRS_44X |
447#endif
448#ifdef CONFIG_E200
449 CPU_FTRS_E200 |
450#endif
451#ifdef CONFIG_E500
Kumar Gala3dfa8772008-06-16 09:41:32 -0500[diff] [blame]452 CPU_FTRS_E500 | CPU_FTRS_E500_2 | CPU_FTRS_E500MC |
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]453#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]454 0,
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]455};
456#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]457
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]458#ifdef __powerpc64__
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]459#define CPU_FTRS_ALWAYS \
460 (CPU_FTRS_POWER3 & CPU_FTRS_RS64 & CPU_FTRS_POWER4 & \
Anton Blanchard03054d52006-04-29 09:51:06 +1000[diff] [blame]461 CPU_FTRS_PPC970 & CPU_FTRS_POWER5 & CPU_FTRS_POWER6 & \
Michael Neulinge952e6c2008-06-18 10:47:26 +1000[diff] [blame]462 CPU_FTRS_POWER7 & CPU_FTRS_CELL & CPU_FTRS_PA6T & CPU_FTRS_POSSIBLE)
Anton Blanchard2406f602005-12-13 07:45:33 +1100[diff] [blame]463#else
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]464enum {
465 CPU_FTRS_ALWAYS =
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]466#if CLASSIC_PPC
467 CPU_FTRS_PPC601 & CPU_FTRS_603 & CPU_FTRS_604 & CPU_FTRS_740_NOTAU &
468 CPU_FTRS_740 & CPU_FTRS_750 & CPU_FTRS_750FX1 &
469 CPU_FTRS_750FX2 & CPU_FTRS_750FX & CPU_FTRS_750GX &
470 CPU_FTRS_7400_NOTAU & CPU_FTRS_7400 & CPU_FTRS_7450_20 &
471 CPU_FTRS_7450_21 & CPU_FTRS_7450_23 & CPU_FTRS_7455_1 &
472 CPU_FTRS_7455_20 & CPU_FTRS_7455 & CPU_FTRS_7447_10 &
473 CPU_FTRS_7447 & CPU_FTRS_7447A & CPU_FTRS_82XX &
Kim Phillipsaa42c692006-12-08 02:43:30 -0600[diff] [blame]474 CPU_FTRS_G2_LE & CPU_FTRS_E300 & CPU_FTRS_E300C2 &
475 CPU_FTRS_CLASSIC32 &
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]476#else
477 CPU_FTRS_GENERIC_32 &
478#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]479#ifdef CONFIG_8xx
480 CPU_FTRS_8XX &
481#endif
482#ifdef CONFIG_40x
483 CPU_FTRS_40X &
484#endif
485#ifdef CONFIG_44x
486 CPU_FTRS_44X &
487#endif
488#ifdef CONFIG_E200
489 CPU_FTRS_E200 &
490#endif
491#ifdef CONFIG_E500
Kumar Gala3dfa8772008-06-16 09:41:32 -0500[diff] [blame]492 CPU_FTRS_E500 & CPU_FTRS_E500_2 & CPU_FTRS_E500MC &
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]493#endif
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]494 CPU_FTRS_POSSIBLE,
495};
Stephen Rothwell7c929432006-03-23 17:36:59 +1100[diff] [blame]496#endif /* __powerpc64__ */
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]497
498static inline int cpu_has_feature(unsigned long feature)
499{
500 return (CPU_FTRS_ALWAYS & feature) ||
501 (CPU_FTRS_POSSIBLE
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]502 & cur_cpu_spec->cpu_features
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]503 & feature);
504}
505
506#endif /* !__ASSEMBLY__ */
507
Kumar Gala10b35d92005-09-23 14:08:58 -0500[diff] [blame]508#endif /* __KERNEL__ */
509#endif /* __ASM_POWERPC_CPUTABLE_H */