Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2012 The Android Open Source Project |
| 3 | * |
| 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | * you may not use this file except in compliance with the License. |
| 6 | * You may obtain a copy of the License at |
| 7 | * |
| 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | * |
| 10 | * Unless required by applicable law or agreed to in writing, software |
| 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | * See the License for the specific language governing permissions and |
| 14 | * limitations under the License. |
| 15 | */ |
| 16 | |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 17 | #include <cstdarg> |
Nicolas Geoffray | f3e2cc4 | 2014-02-18 18:37:26 +0000 | [diff] [blame] | 18 | #include <inttypes.h> |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 19 | #include <string> |
Nicolas Geoffray | f3e2cc4 | 2014-02-18 18:37:26 +0000 | [diff] [blame] | 20 | |
Andreas Gampe | 53c913b | 2014-08-12 23:19:23 -0700 | [diff] [blame] | 21 | #include "backend_x86.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 22 | #include "codegen_x86.h" |
| 23 | #include "dex/compiler_internals.h" |
| 24 | #include "dex/quick/mir_to_lir-inl.h" |
buzbee | b5860fb | 2014-06-21 15:31:01 -0700 | [diff] [blame] | 25 | #include "dex/reg_storage_eq.h" |
Mark Mendell | e19c91f | 2014-02-25 08:19:08 -0800 | [diff] [blame] | 26 | #include "mirror/array.h" |
| 27 | #include "mirror/string.h" |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 28 | #include "oat.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 29 | #include "x86_lir.h" |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 30 | #include "utils/dwarf_cfi.h" |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 31 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 32 | namespace art { |
| 33 | |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 34 | static constexpr RegStorage core_regs_arr_32[] = { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 35 | rs_rAX, rs_rCX, rs_rDX, rs_rBX, rs_rX86_SP_32, rs_rBP, rs_rSI, rs_rDI, |
| 36 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 37 | static constexpr RegStorage core_regs_arr_64[] = { |
Dmitry Petrochenko | 76af0d3 | 2014-06-05 21:15:08 +0700 | [diff] [blame] | 38 | rs_rAX, rs_rCX, rs_rDX, rs_rBX, rs_rX86_SP_32, rs_rBP, rs_rSI, rs_rDI, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 39 | rs_r8, rs_r9, rs_r10, rs_r11, rs_r12, rs_r13, rs_r14, rs_r15 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 40 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 41 | static constexpr RegStorage core_regs_arr_64q[] = { |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 42 | rs_r0q, rs_r1q, rs_r2q, rs_r3q, rs_rX86_SP_64, rs_r5q, rs_r6q, rs_r7q, |
Dmitry Petrochenko | a20468c | 2014-04-30 13:40:19 +0700 | [diff] [blame] | 43 | rs_r8q, rs_r9q, rs_r10q, rs_r11q, rs_r12q, rs_r13q, rs_r14q, rs_r15q |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 44 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 45 | static constexpr RegStorage sp_regs_arr_32[] = { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 46 | rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, |
| 47 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 48 | static constexpr RegStorage sp_regs_arr_64[] = { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 49 | rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 50 | rs_fr8, rs_fr9, rs_fr10, rs_fr11, rs_fr12, rs_fr13, rs_fr14, rs_fr15 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 51 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 52 | static constexpr RegStorage dp_regs_arr_32[] = { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 53 | rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, |
| 54 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 55 | static constexpr RegStorage dp_regs_arr_64[] = { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 56 | rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 57 | rs_dr8, rs_dr9, rs_dr10, rs_dr11, rs_dr12, rs_dr13, rs_dr14, rs_dr15 |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 58 | }; |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 59 | static constexpr RegStorage xp_regs_arr_32[] = { |
| 60 | rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, |
| 61 | }; |
| 62 | static constexpr RegStorage xp_regs_arr_64[] = { |
| 63 | rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, |
| 64 | rs_xr8, rs_xr9, rs_xr10, rs_xr11, rs_xr12, rs_xr13, rs_xr14, rs_xr15 |
| 65 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 66 | static constexpr RegStorage reserved_regs_arr_32[] = {rs_rX86_SP_32}; |
Dmitry Petrochenko | 76af0d3 | 2014-06-05 21:15:08 +0700 | [diff] [blame] | 67 | static constexpr RegStorage reserved_regs_arr_64[] = {rs_rX86_SP_32}; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 68 | static constexpr RegStorage reserved_regs_arr_64q[] = {rs_rX86_SP_64}; |
| 69 | static constexpr RegStorage core_temps_arr_32[] = {rs_rAX, rs_rCX, rs_rDX, rs_rBX}; |
| 70 | static constexpr RegStorage core_temps_arr_64[] = { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 71 | rs_rAX, rs_rCX, rs_rDX, rs_rSI, rs_rDI, |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 72 | rs_r8, rs_r9, rs_r10, rs_r11 |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 73 | }; |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 74 | |
| 75 | // How to add register to be available for promotion: |
| 76 | // 1) Remove register from array defining temp |
| 77 | // 2) Update ClobberCallerSave |
| 78 | // 3) Update JNI compiler ABI: |
| 79 | // 3.1) add reg in JniCallingConvention method |
| 80 | // 3.2) update CoreSpillMask/FpSpillMask |
| 81 | // 4) Update entrypoints |
| 82 | // 4.1) Update constants in asm_support_x86_64.h for new frame size |
| 83 | // 4.2) Remove entry in SmashCallerSaves |
| 84 | // 4.3) Update jni_entrypoints to spill/unspill new callee save reg |
| 85 | // 4.4) Update quick_entrypoints to spill/unspill new callee save reg |
| 86 | // 5) Update runtime ABI |
| 87 | // 5.1) Update quick_method_frame_info with new required spills |
| 88 | // 5.2) Update QuickArgumentVisitor with new offsets to gprs and xmms |
| 89 | // Note that you cannot use register corresponding to incoming args |
| 90 | // according to ABI and QCG needs one additional XMM temp for |
| 91 | // bulk copy in preparation to call. |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 92 | static constexpr RegStorage core_temps_arr_64q[] = { |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 93 | rs_r0q, rs_r1q, rs_r2q, rs_r6q, rs_r7q, |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 94 | rs_r8q, rs_r9q, rs_r10q, rs_r11q |
Dmitry Petrochenko | 0999a6f | 2014-05-22 12:26:50 +0700 | [diff] [blame] | 95 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 96 | static constexpr RegStorage sp_temps_arr_32[] = { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 97 | rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, |
| 98 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 99 | static constexpr RegStorage sp_temps_arr_64[] = { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 100 | rs_fr0, rs_fr1, rs_fr2, rs_fr3, rs_fr4, rs_fr5, rs_fr6, rs_fr7, |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 101 | rs_fr8, rs_fr9, rs_fr10, rs_fr11 |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 102 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 103 | static constexpr RegStorage dp_temps_arr_32[] = { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 104 | rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, |
| 105 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 106 | static constexpr RegStorage dp_temps_arr_64[] = { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 107 | rs_dr0, rs_dr1, rs_dr2, rs_dr3, rs_dr4, rs_dr5, rs_dr6, rs_dr7, |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 108 | rs_dr8, rs_dr9, rs_dr10, rs_dr11 |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 109 | }; |
| 110 | |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 111 | static constexpr RegStorage xp_temps_arr_32[] = { |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 112 | rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, |
| 113 | }; |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 114 | static constexpr RegStorage xp_temps_arr_64[] = { |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 115 | rs_xr0, rs_xr1, rs_xr2, rs_xr3, rs_xr4, rs_xr5, rs_xr6, rs_xr7, |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 116 | rs_xr8, rs_xr9, rs_xr10, rs_xr11 |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 117 | }; |
| 118 | |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 119 | static constexpr ArrayRef<const RegStorage> empty_pool; |
| 120 | static constexpr ArrayRef<const RegStorage> core_regs_32(core_regs_arr_32); |
| 121 | static constexpr ArrayRef<const RegStorage> core_regs_64(core_regs_arr_64); |
| 122 | static constexpr ArrayRef<const RegStorage> core_regs_64q(core_regs_arr_64q); |
| 123 | static constexpr ArrayRef<const RegStorage> sp_regs_32(sp_regs_arr_32); |
| 124 | static constexpr ArrayRef<const RegStorage> sp_regs_64(sp_regs_arr_64); |
| 125 | static constexpr ArrayRef<const RegStorage> dp_regs_32(dp_regs_arr_32); |
| 126 | static constexpr ArrayRef<const RegStorage> dp_regs_64(dp_regs_arr_64); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 127 | static constexpr ArrayRef<const RegStorage> xp_regs_32(xp_regs_arr_32); |
| 128 | static constexpr ArrayRef<const RegStorage> xp_regs_64(xp_regs_arr_64); |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 129 | static constexpr ArrayRef<const RegStorage> reserved_regs_32(reserved_regs_arr_32); |
| 130 | static constexpr ArrayRef<const RegStorage> reserved_regs_64(reserved_regs_arr_64); |
| 131 | static constexpr ArrayRef<const RegStorage> reserved_regs_64q(reserved_regs_arr_64q); |
| 132 | static constexpr ArrayRef<const RegStorage> core_temps_32(core_temps_arr_32); |
| 133 | static constexpr ArrayRef<const RegStorage> core_temps_64(core_temps_arr_64); |
| 134 | static constexpr ArrayRef<const RegStorage> core_temps_64q(core_temps_arr_64q); |
| 135 | static constexpr ArrayRef<const RegStorage> sp_temps_32(sp_temps_arr_32); |
| 136 | static constexpr ArrayRef<const RegStorage> sp_temps_64(sp_temps_arr_64); |
| 137 | static constexpr ArrayRef<const RegStorage> dp_temps_32(dp_temps_arr_32); |
| 138 | static constexpr ArrayRef<const RegStorage> dp_temps_64(dp_temps_arr_64); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 139 | |
Vladimir Marko | 089142c | 2014-06-05 10:57:05 +0100 | [diff] [blame] | 140 | static constexpr ArrayRef<const RegStorage> xp_temps_32(xp_temps_arr_32); |
| 141 | static constexpr ArrayRef<const RegStorage> xp_temps_64(xp_temps_arr_64); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 142 | |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 143 | RegStorage rs_rX86_SP; |
| 144 | |
| 145 | X86NativeRegisterPool rX86_ARG0; |
| 146 | X86NativeRegisterPool rX86_ARG1; |
| 147 | X86NativeRegisterPool rX86_ARG2; |
| 148 | X86NativeRegisterPool rX86_ARG3; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 149 | X86NativeRegisterPool rX86_ARG4; |
| 150 | X86NativeRegisterPool rX86_ARG5; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 151 | X86NativeRegisterPool rX86_FARG0; |
| 152 | X86NativeRegisterPool rX86_FARG1; |
| 153 | X86NativeRegisterPool rX86_FARG2; |
| 154 | X86NativeRegisterPool rX86_FARG3; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 155 | X86NativeRegisterPool rX86_FARG4; |
| 156 | X86NativeRegisterPool rX86_FARG5; |
| 157 | X86NativeRegisterPool rX86_FARG6; |
| 158 | X86NativeRegisterPool rX86_FARG7; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 159 | X86NativeRegisterPool rX86_RET0; |
| 160 | X86NativeRegisterPool rX86_RET1; |
| 161 | X86NativeRegisterPool rX86_INVOKE_TGT; |
| 162 | X86NativeRegisterPool rX86_COUNT; |
| 163 | |
| 164 | RegStorage rs_rX86_ARG0; |
| 165 | RegStorage rs_rX86_ARG1; |
| 166 | RegStorage rs_rX86_ARG2; |
| 167 | RegStorage rs_rX86_ARG3; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 168 | RegStorage rs_rX86_ARG4; |
| 169 | RegStorage rs_rX86_ARG5; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 170 | RegStorage rs_rX86_FARG0; |
| 171 | RegStorage rs_rX86_FARG1; |
| 172 | RegStorage rs_rX86_FARG2; |
| 173 | RegStorage rs_rX86_FARG3; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 174 | RegStorage rs_rX86_FARG4; |
| 175 | RegStorage rs_rX86_FARG5; |
| 176 | RegStorage rs_rX86_FARG6; |
| 177 | RegStorage rs_rX86_FARG7; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 178 | RegStorage rs_rX86_RET0; |
| 179 | RegStorage rs_rX86_RET1; |
| 180 | RegStorage rs_rX86_INVOKE_TGT; |
| 181 | RegStorage rs_rX86_COUNT; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 182 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 183 | RegLocation X86Mir2Lir::LocCReturn() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 184 | return x86_loc_c_return; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 185 | } |
| 186 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 187 | RegLocation X86Mir2Lir::LocCReturnRef() { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 188 | return cu_->target64 ? x86_64_loc_c_return_ref : x86_loc_c_return_ref; |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 189 | } |
| 190 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 191 | RegLocation X86Mir2Lir::LocCReturnWide() { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 192 | return cu_->target64 ? x86_64_loc_c_return_wide : x86_loc_c_return_wide; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 193 | } |
| 194 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 195 | RegLocation X86Mir2Lir::LocCReturnFloat() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 196 | return x86_loc_c_return_float; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 197 | } |
| 198 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 199 | RegLocation X86Mir2Lir::LocCReturnDouble() { |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 200 | return x86_loc_c_return_double; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 201 | } |
| 202 | |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 203 | // Return a target-dependent special register for 32-bit. |
| 204 | RegStorage X86Mir2Lir::TargetReg32(SpecialTargetRegister reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 205 | RegStorage res_reg = RegStorage::InvalidReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 206 | switch (reg) { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 207 | case kSelf: res_reg = RegStorage::InvalidReg(); break; |
| 208 | case kSuspend: res_reg = RegStorage::InvalidReg(); break; |
| 209 | case kLr: res_reg = RegStorage::InvalidReg(); break; |
| 210 | case kPc: res_reg = RegStorage::InvalidReg(); break; |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 211 | case kSp: res_reg = rs_rX86_SP_32; break; // This must be the concrete one, as _SP is target- |
| 212 | // specific size. |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 213 | case kArg0: res_reg = rs_rX86_ARG0; break; |
| 214 | case kArg1: res_reg = rs_rX86_ARG1; break; |
| 215 | case kArg2: res_reg = rs_rX86_ARG2; break; |
| 216 | case kArg3: res_reg = rs_rX86_ARG3; break; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 217 | case kArg4: res_reg = rs_rX86_ARG4; break; |
| 218 | case kArg5: res_reg = rs_rX86_ARG5; break; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 219 | case kFArg0: res_reg = rs_rX86_FARG0; break; |
| 220 | case kFArg1: res_reg = rs_rX86_FARG1; break; |
| 221 | case kFArg2: res_reg = rs_rX86_FARG2; break; |
| 222 | case kFArg3: res_reg = rs_rX86_FARG3; break; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 223 | case kFArg4: res_reg = rs_rX86_FARG4; break; |
| 224 | case kFArg5: res_reg = rs_rX86_FARG5; break; |
| 225 | case kFArg6: res_reg = rs_rX86_FARG6; break; |
| 226 | case kFArg7: res_reg = rs_rX86_FARG7; break; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 227 | case kRet0: res_reg = rs_rX86_RET0; break; |
| 228 | case kRet1: res_reg = rs_rX86_RET1; break; |
| 229 | case kInvokeTgt: res_reg = rs_rX86_INVOKE_TGT; break; |
| 230 | case kHiddenArg: res_reg = rs_rAX; break; |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 231 | case kHiddenFpArg: DCHECK(!cu_->target64); res_reg = rs_fr0; break; |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 232 | case kCount: res_reg = rs_rX86_COUNT; break; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 233 | default: res_reg = RegStorage::InvalidReg(); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 234 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 235 | return res_reg; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 236 | } |
| 237 | |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 238 | RegStorage X86Mir2Lir::TargetReg(SpecialTargetRegister reg) { |
| 239 | LOG(FATAL) << "Do not use this function!!!"; |
| 240 | return RegStorage::InvalidReg(); |
| 241 | } |
| 242 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 243 | /* |
| 244 | * Decode the register id. |
| 245 | */ |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 246 | ResourceMask X86Mir2Lir::GetRegMaskCommon(const RegStorage& reg) const { |
| 247 | /* Double registers in x86 are just a single FP register. This is always just a single bit. */ |
| 248 | return ResourceMask::Bit( |
| 249 | /* FP register starts at bit position 16 */ |
| 250 | ((reg.IsFloat() || reg.StorageSize() > 8) ? kX86FPReg0 : 0) + reg.GetRegNum()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 251 | } |
| 252 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 253 | ResourceMask X86Mir2Lir::GetPCUseDefEncoding() const { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 254 | return kEncodeNone; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 255 | } |
| 256 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 257 | void X86Mir2Lir::SetupTargetResourceMasks(LIR* lir, uint64_t flags, |
| 258 | ResourceMask* use_mask, ResourceMask* def_mask) { |
Dmitry Petrochenko | 6a58cb1 | 2014-04-02 17:27:59 +0700 | [diff] [blame] | 259 | DCHECK(cu_->instruction_set == kX86 || cu_->instruction_set == kX86_64); |
buzbee | b48819d | 2013-09-14 16:15:25 -0700 | [diff] [blame] | 260 | DCHECK(!lir->flags.use_def_invalid); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 261 | |
| 262 | // X86-specific resource map setup here. |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 263 | if (flags & REG_USE_SP) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 264 | use_mask->SetBit(kX86RegSP); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 265 | } |
| 266 | |
| 267 | if (flags & REG_DEF_SP) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 268 | def_mask->SetBit(kX86RegSP); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 269 | } |
| 270 | |
| 271 | if (flags & REG_DEFA) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 272 | SetupRegMask(def_mask, rs_rAX.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 273 | } |
| 274 | |
| 275 | if (flags & REG_DEFD) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 276 | SetupRegMask(def_mask, rs_rDX.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 277 | } |
| 278 | if (flags & REG_USEA) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 279 | SetupRegMask(use_mask, rs_rAX.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 280 | } |
| 281 | |
| 282 | if (flags & REG_USEC) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 283 | SetupRegMask(use_mask, rs_rCX.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 284 | } |
| 285 | |
| 286 | if (flags & REG_USED) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 287 | SetupRegMask(use_mask, rs_rDX.GetReg()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 288 | } |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 289 | |
| 290 | if (flags & REG_USEB) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 291 | SetupRegMask(use_mask, rs_rBX.GetReg()); |
Vladimir Marko | 70b797d | 2013-12-03 15:25:24 +0000 | [diff] [blame] | 292 | } |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 293 | |
| 294 | // Fixup hard to describe instruction: Uses rAX, rCX, rDI; sets rDI. |
| 295 | if (lir->opcode == kX86RepneScasw) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 296 | SetupRegMask(use_mask, rs_rAX.GetReg()); |
| 297 | SetupRegMask(use_mask, rs_rCX.GetReg()); |
| 298 | SetupRegMask(use_mask, rs_rDI.GetReg()); |
| 299 | SetupRegMask(def_mask, rs_rDI.GetReg()); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 300 | } |
Serguei Katkov | e90501d | 2014-03-12 15:56:54 +0700 | [diff] [blame] | 301 | |
| 302 | if (flags & USE_FP_STACK) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 303 | use_mask->SetBit(kX86FPStack); |
| 304 | def_mask->SetBit(kX86FPStack); |
Serguei Katkov | e90501d | 2014-03-12 15:56:54 +0700 | [diff] [blame] | 305 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 306 | } |
| 307 | |
| 308 | /* For dumping instructions */ |
| 309 | static const char* x86RegName[] = { |
| 310 | "rax", "rcx", "rdx", "rbx", "rsp", "rbp", "rsi", "rdi", |
| 311 | "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15" |
| 312 | }; |
| 313 | |
| 314 | static const char* x86CondName[] = { |
| 315 | "O", |
| 316 | "NO", |
| 317 | "B/NAE/C", |
| 318 | "NB/AE/NC", |
| 319 | "Z/EQ", |
| 320 | "NZ/NE", |
| 321 | "BE/NA", |
| 322 | "NBE/A", |
| 323 | "S", |
| 324 | "NS", |
| 325 | "P/PE", |
| 326 | "NP/PO", |
| 327 | "L/NGE", |
| 328 | "NL/GE", |
| 329 | "LE/NG", |
| 330 | "NLE/G" |
| 331 | }; |
| 332 | |
| 333 | /* |
| 334 | * Interpret a format string and build a string no longer than size |
| 335 | * See format key in Assemble.cc. |
| 336 | */ |
| 337 | std::string X86Mir2Lir::BuildInsnString(const char *fmt, LIR *lir, unsigned char* base_addr) { |
| 338 | std::string buf; |
| 339 | size_t i = 0; |
| 340 | size_t fmt_len = strlen(fmt); |
| 341 | while (i < fmt_len) { |
| 342 | if (fmt[i] != '!') { |
| 343 | buf += fmt[i]; |
| 344 | i++; |
| 345 | } else { |
| 346 | i++; |
| 347 | DCHECK_LT(i, fmt_len); |
| 348 | char operand_number_ch = fmt[i]; |
| 349 | i++; |
| 350 | if (operand_number_ch == '!') { |
| 351 | buf += "!"; |
| 352 | } else { |
| 353 | int operand_number = operand_number_ch - '0'; |
| 354 | DCHECK_LT(operand_number, 6); // Expect upto 6 LIR operands. |
| 355 | DCHECK_LT(i, fmt_len); |
| 356 | int operand = lir->operands[operand_number]; |
| 357 | switch (fmt[i]) { |
| 358 | case 'c': |
| 359 | DCHECK_LT(static_cast<size_t>(operand), sizeof(x86CondName)); |
| 360 | buf += x86CondName[operand]; |
| 361 | break; |
| 362 | case 'd': |
| 363 | buf += StringPrintf("%d", operand); |
| 364 | break; |
Yixin Shou | 5192cbb | 2014-07-01 13:48:17 -0400 | [diff] [blame] | 365 | case 'q': { |
| 366 | int64_t value = static_cast<int64_t>(static_cast<int64_t>(operand) << 32 | |
| 367 | static_cast<uint32_t>(lir->operands[operand_number+1])); |
| 368 | buf +=StringPrintf("%" PRId64, value); |
Haitao Feng | e70f179 | 2014-08-09 08:31:02 +0800 | [diff] [blame] | 369 | break; |
Yixin Shou | 5192cbb | 2014-07-01 13:48:17 -0400 | [diff] [blame] | 370 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 371 | case 'p': { |
buzbee | 0d82948 | 2013-10-11 15:24:55 -0700 | [diff] [blame] | 372 | EmbeddedData *tab_rec = reinterpret_cast<EmbeddedData*>(UnwrapPointer(operand)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 373 | buf += StringPrintf("0x%08x", tab_rec->offset); |
| 374 | break; |
| 375 | } |
| 376 | case 'r': |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 377 | if (RegStorage::IsFloat(operand)) { |
| 378 | int fp_reg = RegStorage::RegNum(operand); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 379 | buf += StringPrintf("xmm%d", fp_reg); |
| 380 | } else { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 381 | int reg_num = RegStorage::RegNum(operand); |
| 382 | DCHECK_LT(static_cast<size_t>(reg_num), sizeof(x86RegName)); |
| 383 | buf += x86RegName[reg_num]; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 384 | } |
| 385 | break; |
| 386 | case 't': |
Ian Rogers | 107c31e | 2014-01-23 20:55:29 -0800 | [diff] [blame] | 387 | buf += StringPrintf("0x%08" PRIxPTR " (L%p)", |
| 388 | reinterpret_cast<uintptr_t>(base_addr) + lir->offset + operand, |
| 389 | lir->target); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 390 | break; |
| 391 | default: |
| 392 | buf += StringPrintf("DecodeError '%c'", fmt[i]); |
| 393 | break; |
| 394 | } |
| 395 | i++; |
| 396 | } |
| 397 | } |
| 398 | } |
| 399 | return buf; |
| 400 | } |
| 401 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 402 | void X86Mir2Lir::DumpResourceMask(LIR *x86LIR, const ResourceMask& mask, const char *prefix) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 403 | char buf[256]; |
| 404 | buf[0] = 0; |
| 405 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 406 | if (mask.Equals(kEncodeAll)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 407 | strcpy(buf, "all"); |
| 408 | } else { |
| 409 | char num[8]; |
| 410 | int i; |
| 411 | |
| 412 | for (i = 0; i < kX86RegEnd; i++) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 413 | if (mask.HasBit(i)) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 414 | snprintf(num, arraysize(num), "%d ", i); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 415 | strcat(buf, num); |
| 416 | } |
| 417 | } |
| 418 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 419 | if (mask.HasBit(ResourceMask::kCCode)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 420 | strcat(buf, "cc "); |
| 421 | } |
| 422 | /* Memory bits */ |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 423 | if (x86LIR && (mask.HasBit(ResourceMask::kDalvikReg))) { |
Ian Rogers | 988e6ea | 2014-01-08 11:30:50 -0800 | [diff] [blame] | 424 | snprintf(buf + strlen(buf), arraysize(buf) - strlen(buf), "dr%d%s", |
| 425 | DECODE_ALIAS_INFO_REG(x86LIR->flags.alias_info), |
| 426 | (DECODE_ALIAS_INFO_WIDE(x86LIR->flags.alias_info)) ? "(+1)" : ""); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 427 | } |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 428 | if (mask.HasBit(ResourceMask::kLiteral)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 429 | strcat(buf, "lit "); |
| 430 | } |
| 431 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 432 | if (mask.HasBit(ResourceMask::kHeapRef)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 433 | strcat(buf, "heap "); |
| 434 | } |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 435 | if (mask.HasBit(ResourceMask::kMustNotAlias)) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 436 | strcat(buf, "noalias "); |
| 437 | } |
| 438 | } |
| 439 | if (buf[0]) { |
| 440 | LOG(INFO) << prefix << ": " << buf; |
| 441 | } |
| 442 | } |
| 443 | |
| 444 | void X86Mir2Lir::AdjustSpillMask() { |
| 445 | // Adjustment for LR spilling, x86 has no LR so nothing to do here |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 446 | core_spill_mask_ |= (1 << rs_rRET.GetRegNum()); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 447 | num_core_spills_++; |
| 448 | } |
| 449 | |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 450 | RegStorage X86Mir2Lir::AllocateByteRegister() { |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 451 | RegStorage reg = AllocTypedTemp(false, kCoreReg); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 452 | if (!cu_->target64) { |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 453 | DCHECK_LT(reg.GetRegNum(), rs_rX86_SP.GetRegNum()); |
| 454 | } |
| 455 | return reg; |
| 456 | } |
| 457 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 458 | RegStorage X86Mir2Lir::Get128BitRegister(RegStorage reg) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 459 | return GetRegInfo(reg)->Master()->GetReg(); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 460 | } |
| 461 | |
Chao-ying Fu | 7e399fd | 2014-06-10 18:11:11 -0700 | [diff] [blame] | 462 | bool X86Mir2Lir::IsByteRegister(RegStorage reg) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 463 | return cu_->target64 || reg.GetRegNum() < rs_rX86_SP.GetRegNum(); |
Mark Mendell | e87f9b5 | 2014-04-30 14:13:18 -0400 | [diff] [blame] | 464 | } |
| 465 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 466 | /* Clobber all regs that might be used by an external C call */ |
Vladimir Marko | 31c2aac | 2013-12-09 16:31:19 +0000 | [diff] [blame] | 467 | void X86Mir2Lir::ClobberCallerSave() { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 468 | if (cu_->target64) { |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 469 | Clobber(rs_rAX); |
| 470 | Clobber(rs_rCX); |
| 471 | Clobber(rs_rDX); |
| 472 | Clobber(rs_rSI); |
| 473 | Clobber(rs_rDI); |
| 474 | |
Chao-ying Fu | 35ec2b5 | 2014-06-16 16:40:31 -0700 | [diff] [blame] | 475 | Clobber(rs_r8); |
| 476 | Clobber(rs_r9); |
| 477 | Clobber(rs_r10); |
| 478 | Clobber(rs_r11); |
| 479 | |
| 480 | Clobber(rs_fr8); |
| 481 | Clobber(rs_fr9); |
| 482 | Clobber(rs_fr10); |
| 483 | Clobber(rs_fr11); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 484 | } else { |
| 485 | Clobber(rs_rAX); |
| 486 | Clobber(rs_rCX); |
| 487 | Clobber(rs_rDX); |
| 488 | Clobber(rs_rBX); |
Chao-ying Fu | 35ec2b5 | 2014-06-16 16:40:31 -0700 | [diff] [blame] | 489 | } |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 490 | |
| 491 | Clobber(rs_fr0); |
| 492 | Clobber(rs_fr1); |
| 493 | Clobber(rs_fr2); |
| 494 | Clobber(rs_fr3); |
| 495 | Clobber(rs_fr4); |
| 496 | Clobber(rs_fr5); |
| 497 | Clobber(rs_fr6); |
| 498 | Clobber(rs_fr7); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 499 | } |
| 500 | |
| 501 | RegLocation X86Mir2Lir::GetReturnWideAlt() { |
| 502 | RegLocation res = LocCReturnWide(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 503 | DCHECK(res.reg.GetLowReg() == rs_rAX.GetReg()); |
| 504 | DCHECK(res.reg.GetHighReg() == rs_rDX.GetReg()); |
| 505 | Clobber(rs_rAX); |
| 506 | Clobber(rs_rDX); |
| 507 | MarkInUse(rs_rAX); |
| 508 | MarkInUse(rs_rDX); |
| 509 | MarkWide(res.reg); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 510 | return res; |
| 511 | } |
| 512 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 513 | RegLocation X86Mir2Lir::GetReturnAlt() { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 514 | RegLocation res = LocCReturn(); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 515 | res.reg.SetReg(rs_rDX.GetReg()); |
| 516 | Clobber(rs_rDX); |
| 517 | MarkInUse(rs_rDX); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 518 | return res; |
| 519 | } |
| 520 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 521 | /* To be used when explicitly managing register use */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 522 | void X86Mir2Lir::LockCallTemps() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 523 | LockTemp(rs_rX86_ARG0); |
| 524 | LockTemp(rs_rX86_ARG1); |
| 525 | LockTemp(rs_rX86_ARG2); |
| 526 | LockTemp(rs_rX86_ARG3); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 527 | if (cu_->target64) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 528 | LockTemp(rs_rX86_ARG4); |
| 529 | LockTemp(rs_rX86_ARG5); |
| 530 | LockTemp(rs_rX86_FARG0); |
| 531 | LockTemp(rs_rX86_FARG1); |
| 532 | LockTemp(rs_rX86_FARG2); |
| 533 | LockTemp(rs_rX86_FARG3); |
| 534 | LockTemp(rs_rX86_FARG4); |
| 535 | LockTemp(rs_rX86_FARG5); |
| 536 | LockTemp(rs_rX86_FARG6); |
| 537 | LockTemp(rs_rX86_FARG7); |
| 538 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 539 | } |
| 540 | |
| 541 | /* To be used when explicitly managing register use */ |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 542 | void X86Mir2Lir::FreeCallTemps() { |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 543 | FreeTemp(rs_rX86_ARG0); |
| 544 | FreeTemp(rs_rX86_ARG1); |
| 545 | FreeTemp(rs_rX86_ARG2); |
| 546 | FreeTemp(rs_rX86_ARG3); |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 547 | if (cu_->target64) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 548 | FreeTemp(rs_rX86_ARG4); |
| 549 | FreeTemp(rs_rX86_ARG5); |
| 550 | FreeTemp(rs_rX86_FARG0); |
| 551 | FreeTemp(rs_rX86_FARG1); |
| 552 | FreeTemp(rs_rX86_FARG2); |
| 553 | FreeTemp(rs_rX86_FARG3); |
| 554 | FreeTemp(rs_rX86_FARG4); |
| 555 | FreeTemp(rs_rX86_FARG5); |
| 556 | FreeTemp(rs_rX86_FARG6); |
| 557 | FreeTemp(rs_rX86_FARG7); |
| 558 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 559 | } |
| 560 | |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 561 | bool X86Mir2Lir::ProvidesFullMemoryBarrier(X86OpCode opcode) { |
| 562 | switch (opcode) { |
| 563 | case kX86LockCmpxchgMR: |
| 564 | case kX86LockCmpxchgAR: |
Ian Rogers | 0f9b9c5 | 2014-06-09 01:32:12 -0700 | [diff] [blame] | 565 | case kX86LockCmpxchg64M: |
| 566 | case kX86LockCmpxchg64A: |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 567 | case kX86XchgMR: |
| 568 | case kX86Mfence: |
| 569 | // Atomic memory instructions provide full barrier. |
| 570 | return true; |
| 571 | default: |
| 572 | break; |
| 573 | } |
| 574 | |
| 575 | // Conservative if cannot prove it provides full barrier. |
| 576 | return false; |
| 577 | } |
| 578 | |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 579 | bool X86Mir2Lir::GenMemBarrier(MemBarrierKind barrier_kind) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 580 | #if ANDROID_SMP != 0 |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 581 | // Start off with using the last LIR as the barrier. If it is not enough, then we will update it. |
| 582 | LIR* mem_barrier = last_lir_insn_; |
| 583 | |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 584 | bool ret = false; |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 585 | /* |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 586 | * According to the JSR-133 Cookbook, for x86 only StoreLoad/AnyAny barriers need memory fence. |
| 587 | * All other barriers (LoadAny, AnyStore, StoreStore) are nops due to the x86 memory model. |
| 588 | * For those cases, all we need to ensure is that there is a scheduling barrier in place. |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 589 | */ |
Hans Boehm | 48f5c47 | 2014-06-27 14:50:10 -0700 | [diff] [blame] | 590 | if (barrier_kind == kAnyAny) { |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 591 | // If no LIR exists already that can be used a barrier, then generate an mfence. |
| 592 | if (mem_barrier == nullptr) { |
| 593 | mem_barrier = NewLIR0(kX86Mfence); |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 594 | ret = true; |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 595 | } |
| 596 | |
| 597 | // If last instruction does not provide full barrier, then insert an mfence. |
| 598 | if (ProvidesFullMemoryBarrier(static_cast<X86OpCode>(mem_barrier->opcode)) == false) { |
| 599 | mem_barrier = NewLIR0(kX86Mfence); |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 600 | ret = true; |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 601 | } |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame] | 602 | } else if (barrier_kind == kNTStoreStore) { |
| 603 | mem_barrier = NewLIR0(kX86Sfence); |
| 604 | ret = true; |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 605 | } |
| 606 | |
| 607 | // Now ensure that a scheduling barrier is in place. |
| 608 | if (mem_barrier == nullptr) { |
| 609 | GenBarrier(); |
| 610 | } else { |
| 611 | // Mark as a scheduling barrier. |
| 612 | DCHECK(!mem_barrier->flags.use_def_invalid); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 613 | mem_barrier->u.m.def_mask = &kEncodeAll; |
Razvan A Lupusoru | 99ad723 | 2014-02-25 17:41:08 -0800 | [diff] [blame] | 614 | } |
Andreas Gampe | b14329f | 2014-05-15 11:16:06 -0700 | [diff] [blame] | 615 | return ret; |
| 616 | #else |
| 617 | return false; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 618 | #endif |
| 619 | } |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 620 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 621 | void X86Mir2Lir::CompilerInitializeRegAlloc() { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 622 | if (cu_->target64) { |
Dmitry Petrochenko | 76af0d3 | 2014-06-05 21:15:08 +0700 | [diff] [blame] | 623 | reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs_64, core_regs_64q, sp_regs_64, |
| 624 | dp_regs_64, reserved_regs_64, reserved_regs_64q, |
| 625 | core_temps_64, core_temps_64q, sp_temps_64, dp_temps_64); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 626 | } else { |
buzbee | b01bf15 | 2014-05-13 15:59:07 -0700 | [diff] [blame] | 627 | reg_pool_ = new (arena_) RegisterPool(this, arena_, core_regs_32, empty_pool, sp_regs_32, |
| 628 | dp_regs_32, reserved_regs_32, empty_pool, |
| 629 | core_temps_32, empty_pool, sp_temps_32, dp_temps_32); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 630 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 631 | |
| 632 | // Target-specific adjustments. |
| 633 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 634 | // Add in XMM registers. |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 635 | const ArrayRef<const RegStorage> *xp_regs = cu_->target64 ? &xp_regs_64 : &xp_regs_32; |
| 636 | for (RegStorage reg : *xp_regs) { |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 637 | RegisterInfo* info = new (arena_) RegisterInfo(reg, GetRegMaskCommon(reg)); |
| 638 | reginfo_map_.Put(reg.GetReg(), info); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 639 | } |
| 640 | const ArrayRef<const RegStorage> *xp_temps = cu_->target64 ? &xp_temps_64 : &xp_temps_32; |
| 641 | for (RegStorage reg : *xp_temps) { |
| 642 | RegisterInfo* xp_reg_info = GetRegInfo(reg); |
| 643 | xp_reg_info->SetIsTemp(true); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 644 | } |
| 645 | |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 646 | // Alias single precision xmm to double xmms. |
| 647 | // TODO: as needed, add larger vector sizes - alias all to the largest. |
| 648 | GrowableArray<RegisterInfo*>::Iterator it(®_pool_->sp_regs_); |
| 649 | for (RegisterInfo* info = it.Next(); info != nullptr; info = it.Next()) { |
| 650 | int sp_reg_num = info->GetReg().GetRegNum(); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 651 | RegStorage xp_reg = RegStorage::Solo128(sp_reg_num); |
| 652 | RegisterInfo* xp_reg_info = GetRegInfo(xp_reg); |
| 653 | // 128-bit xmm vector register's master storage should refer to itself. |
| 654 | DCHECK_EQ(xp_reg_info, xp_reg_info->Master()); |
| 655 | |
| 656 | // Redirect 32-bit vector's master storage to 128-bit vector. |
| 657 | info->SetMaster(xp_reg_info); |
| 658 | |
Dmitry Petrochenko | 76af0d3 | 2014-06-05 21:15:08 +0700 | [diff] [blame] | 659 | RegStorage dp_reg = RegStorage::FloatSolo64(sp_reg_num); |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 660 | RegisterInfo* dp_reg_info = GetRegInfo(dp_reg); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 661 | // Redirect 64-bit vector's master storage to 128-bit vector. |
| 662 | dp_reg_info->SetMaster(xp_reg_info); |
Dmitry Petrochenko | 76af0d3 | 2014-06-05 21:15:08 +0700 | [diff] [blame] | 663 | // Singles should show a single 32-bit mask bit, at first referring to the low half. |
| 664 | DCHECK_EQ(info->StorageMask(), 0x1U); |
| 665 | } |
| 666 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 667 | if (cu_->target64) { |
Dmitry Petrochenko | 76af0d3 | 2014-06-05 21:15:08 +0700 | [diff] [blame] | 668 | // Alias 32bit W registers to corresponding 64bit X registers. |
| 669 | GrowableArray<RegisterInfo*>::Iterator w_it(®_pool_->core_regs_); |
| 670 | for (RegisterInfo* info = w_it.Next(); info != nullptr; info = w_it.Next()) { |
| 671 | int x_reg_num = info->GetReg().GetRegNum(); |
| 672 | RegStorage x_reg = RegStorage::Solo64(x_reg_num); |
| 673 | RegisterInfo* x_reg_info = GetRegInfo(x_reg); |
| 674 | // 64bit X register's master storage should refer to itself. |
| 675 | DCHECK_EQ(x_reg_info, x_reg_info->Master()); |
| 676 | // Redirect 32bit W master storage to 64bit X. |
| 677 | info->SetMaster(x_reg_info); |
| 678 | // 32bit W should show a single 32-bit mask bit, at first referring to the low half. |
| 679 | DCHECK_EQ(info->StorageMask(), 0x1U); |
| 680 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 681 | } |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 682 | |
| 683 | // Don't start allocating temps at r0/s0/d0 or you may clobber return regs in early-exit methods. |
| 684 | // TODO: adjust for x86/hard float calling convention. |
| 685 | reg_pool_->next_core_reg_ = 2; |
| 686 | reg_pool_->next_sp_reg_ = 2; |
| 687 | reg_pool_->next_dp_reg_ = 1; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 688 | } |
| 689 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 690 | int X86Mir2Lir::VectorRegisterSize() { |
| 691 | return 128; |
| 692 | } |
| 693 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 694 | int X86Mir2Lir::NumReservableVectorRegisters(bool long_or_fp) { |
| 695 | int num_vector_temps = cu_->target64 ? xp_temps_64.size() : xp_temps_32.size(); |
| 696 | |
| 697 | // Leave a few temps for use by backend as scratch. |
| 698 | return long_or_fp ? num_vector_temps - 2 : num_vector_temps - 1; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 699 | } |
| 700 | |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 701 | void X86Mir2Lir::SpillCoreRegs() { |
| 702 | if (num_core_spills_ == 0) { |
| 703 | return; |
| 704 | } |
| 705 | // Spill mask not including fake return address register |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 706 | uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 707 | int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 708 | OpSize size = cu_->target64 ? k64 : k32; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 709 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 710 | if (mask & 0x1) { |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 711 | StoreBaseDisp(rs_rX86_SP, offset, cu_->target64 ? RegStorage::Solo64(reg) : RegStorage::Solo32(reg), |
| 712 | size, kNotVolatile); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 713 | offset += GetInstructionSetPointerSize(cu_->instruction_set); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 714 | } |
| 715 | } |
| 716 | } |
| 717 | |
| 718 | void X86Mir2Lir::UnSpillCoreRegs() { |
| 719 | if (num_core_spills_ == 0) { |
| 720 | return; |
| 721 | } |
| 722 | // Spill mask not including fake return address register |
buzbee | 091cc40 | 2014-03-31 10:14:40 -0700 | [diff] [blame] | 723 | uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 724 | int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 725 | OpSize size = cu_->target64 ? k64 : k32; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 726 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 727 | if (mask & 0x1) { |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 728 | LoadBaseDisp(rs_rX86_SP, offset, cu_->target64 ? RegStorage::Solo64(reg) : RegStorage::Solo32(reg), |
| 729 | size, kNotVolatile); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 730 | offset += GetInstructionSetPointerSize(cu_->instruction_set); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 731 | } |
| 732 | } |
| 733 | } |
| 734 | |
Serguei Katkov | c380191 | 2014-07-08 17:21:53 +0700 | [diff] [blame] | 735 | void X86Mir2Lir::SpillFPRegs() { |
| 736 | if (num_fp_spills_ == 0) { |
| 737 | return; |
| 738 | } |
| 739 | uint32_t mask = fp_spill_mask_; |
| 740 | int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * (num_fp_spills_ + num_core_spills_)); |
| 741 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 742 | if (mask & 0x1) { |
| 743 | StoreBaseDisp(rs_rX86_SP, offset, RegStorage::FloatSolo64(reg), |
| 744 | k64, kNotVolatile); |
| 745 | offset += sizeof(double); |
| 746 | } |
| 747 | } |
| 748 | } |
| 749 | void X86Mir2Lir::UnSpillFPRegs() { |
| 750 | if (num_fp_spills_ == 0) { |
| 751 | return; |
| 752 | } |
| 753 | uint32_t mask = fp_spill_mask_; |
| 754 | int offset = frame_size_ - (GetInstructionSetPointerSize(cu_->instruction_set) * (num_fp_spills_ + num_core_spills_)); |
| 755 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 756 | if (mask & 0x1) { |
| 757 | LoadBaseDisp(rs_rX86_SP, offset, RegStorage::FloatSolo64(reg), |
| 758 | k64, kNotVolatile); |
| 759 | offset += sizeof(double); |
| 760 | } |
| 761 | } |
| 762 | } |
| 763 | |
| 764 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 765 | bool X86Mir2Lir::IsUnconditionalBranch(LIR* lir) { |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 766 | return (lir->opcode == kX86Jmp8 || lir->opcode == kX86Jmp32); |
| 767 | } |
| 768 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 769 | RegisterClass X86Mir2Lir::RegClassForFieldLoadStore(OpSize size, bool is_volatile) { |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 770 | // X86_64 can handle any size. |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 771 | if (cu_->target64) { |
Chao-ying Fu | 06839f8 | 2014-08-14 15:59:17 -0700 | [diff] [blame] | 772 | return RegClassBySize(size); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 773 | } |
| 774 | |
Vladimir Marko | 674744e | 2014-04-24 15:18:26 +0100 | [diff] [blame] | 775 | if (UNLIKELY(is_volatile)) { |
| 776 | // On x86, atomic 64-bit load/store requires an fp register. |
| 777 | // Smaller aligned load/store is atomic for both core and fp registers. |
| 778 | if (size == k64 || size == kDouble) { |
| 779 | return kFPReg; |
| 780 | } |
| 781 | } |
| 782 | return RegClassBySize(size); |
| 783 | } |
| 784 | |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 785 | X86Mir2Lir::X86Mir2Lir(CompilationUnit* cu, MIRGraph* mir_graph, ArenaAllocator* arena) |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 786 | : Mir2Lir(cu, mir_graph, arena), |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 787 | base_of_code_(nullptr), store_method_addr_(false), store_method_addr_used_(false), |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 788 | method_address_insns_(arena, 100, kGrowableArrayMisc), |
| 789 | class_type_address_insns_(arena, 100, kGrowableArrayMisc), |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 790 | call_method_insns_(arena, 100, kGrowableArrayMisc), |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 791 | stack_decrement_(nullptr), stack_increment_(nullptr), |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 792 | const_vectors_(nullptr) { |
| 793 | store_method_addr_used_ = false; |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 794 | if (kIsDebugBuild) { |
| 795 | for (int i = 0; i < kX86Last; i++) { |
| 796 | if (X86Mir2Lir::EncodingMap[i].opcode != i) { |
| 797 | LOG(FATAL) << "Encoding order for " << X86Mir2Lir::EncodingMap[i].name |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 798 | << " is wrong: expecting " << i << ", seeing " |
| 799 | << static_cast<int>(X86Mir2Lir::EncodingMap[i].opcode); |
Ian Rogers | dd7624d | 2014-03-14 17:43:00 -0700 | [diff] [blame] | 800 | } |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 801 | } |
| 802 | } |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 803 | if (cu_->target64) { |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 804 | rs_rX86_SP = rs_rX86_SP_64; |
| 805 | |
| 806 | rs_rX86_ARG0 = rs_rDI; |
| 807 | rs_rX86_ARG1 = rs_rSI; |
| 808 | rs_rX86_ARG2 = rs_rDX; |
| 809 | rs_rX86_ARG3 = rs_rCX; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 810 | rs_rX86_ARG4 = rs_r8; |
| 811 | rs_rX86_ARG5 = rs_r9; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 812 | rs_rX86_FARG0 = rs_fr0; |
| 813 | rs_rX86_FARG1 = rs_fr1; |
| 814 | rs_rX86_FARG2 = rs_fr2; |
| 815 | rs_rX86_FARG3 = rs_fr3; |
| 816 | rs_rX86_FARG4 = rs_fr4; |
| 817 | rs_rX86_FARG5 = rs_fr5; |
| 818 | rs_rX86_FARG6 = rs_fr6; |
| 819 | rs_rX86_FARG7 = rs_fr7; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 820 | rX86_ARG0 = rDI; |
| 821 | rX86_ARG1 = rSI; |
| 822 | rX86_ARG2 = rDX; |
| 823 | rX86_ARG3 = rCX; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 824 | rX86_ARG4 = r8; |
| 825 | rX86_ARG5 = r9; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 826 | rX86_FARG0 = fr0; |
| 827 | rX86_FARG1 = fr1; |
| 828 | rX86_FARG2 = fr2; |
| 829 | rX86_FARG3 = fr3; |
| 830 | rX86_FARG4 = fr4; |
| 831 | rX86_FARG5 = fr5; |
| 832 | rX86_FARG6 = fr6; |
| 833 | rX86_FARG7 = fr7; |
Mark Mendell | 55884bc | 2014-06-10 10:21:29 -0400 | [diff] [blame] | 834 | rs_rX86_INVOKE_TGT = rs_rDI; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 835 | } else { |
| 836 | rs_rX86_SP = rs_rX86_SP_32; |
| 837 | |
| 838 | rs_rX86_ARG0 = rs_rAX; |
| 839 | rs_rX86_ARG1 = rs_rCX; |
| 840 | rs_rX86_ARG2 = rs_rDX; |
| 841 | rs_rX86_ARG3 = rs_rBX; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 842 | rs_rX86_ARG4 = RegStorage::InvalidReg(); |
| 843 | rs_rX86_ARG5 = RegStorage::InvalidReg(); |
| 844 | rs_rX86_FARG0 = rs_rAX; |
| 845 | rs_rX86_FARG1 = rs_rCX; |
| 846 | rs_rX86_FARG2 = rs_rDX; |
| 847 | rs_rX86_FARG3 = rs_rBX; |
| 848 | rs_rX86_FARG4 = RegStorage::InvalidReg(); |
| 849 | rs_rX86_FARG5 = RegStorage::InvalidReg(); |
| 850 | rs_rX86_FARG6 = RegStorage::InvalidReg(); |
| 851 | rs_rX86_FARG7 = RegStorage::InvalidReg(); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 852 | rX86_ARG0 = rAX; |
| 853 | rX86_ARG1 = rCX; |
| 854 | rX86_ARG2 = rDX; |
| 855 | rX86_ARG3 = rBX; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 856 | rX86_FARG0 = rAX; |
| 857 | rX86_FARG1 = rCX; |
| 858 | rX86_FARG2 = rDX; |
| 859 | rX86_FARG3 = rBX; |
Mark Mendell | 55884bc | 2014-06-10 10:21:29 -0400 | [diff] [blame] | 860 | rs_rX86_INVOKE_TGT = rs_rAX; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 861 | // TODO(64): Initialize with invalid reg |
| 862 | // rX86_ARG4 = RegStorage::InvalidReg(); |
| 863 | // rX86_ARG5 = RegStorage::InvalidReg(); |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 864 | } |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 865 | rs_rX86_RET0 = rs_rAX; |
| 866 | rs_rX86_RET1 = rs_rDX; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 867 | rs_rX86_COUNT = rs_rCX; |
Dmitry Petrochenko | 9ee801f | 2014-05-12 11:31:37 +0700 | [diff] [blame] | 868 | rX86_RET0 = rAX; |
| 869 | rX86_RET1 = rDX; |
| 870 | rX86_INVOKE_TGT = rAX; |
| 871 | rX86_COUNT = rCX; |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 872 | } |
| 873 | |
| 874 | Mir2Lir* X86CodeGenerator(CompilationUnit* const cu, MIRGraph* const mir_graph, |
| 875 | ArenaAllocator* const arena) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 876 | return new X86Mir2Lir(cu, mir_graph, arena); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 877 | } |
| 878 | |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 879 | // Not used in x86(-64) |
| 880 | RegStorage X86Mir2Lir::LoadHelper(QuickEntrypointEnum trampoline) { |
Andreas Gampe | 2f244e9 | 2014-05-08 03:35:25 -0700 | [diff] [blame] | 881 | LOG(FATAL) << "Unexpected use of LoadHelper in x86"; |
| 882 | return RegStorage::InvalidReg(); |
| 883 | } |
| 884 | |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 885 | LIR* X86Mir2Lir::CheckSuspendUsingLoad() { |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 886 | // First load the pointer in fs:[suspend-trigger] into eax |
| 887 | // Then use a test instruction to indirect via that address. |
Dave Allison | dfd3b47 | 2014-07-16 16:04:32 -0700 | [diff] [blame] | 888 | if (cu_->target64) { |
| 889 | NewLIR2(kX86Mov64RT, rs_rAX.GetReg(), |
| 890 | Thread::ThreadSuspendTriggerOffset<8>().Int32Value()); |
| 891 | } else { |
| 892 | NewLIR2(kX86Mov32RT, rs_rAX.GetReg(), |
| 893 | Thread::ThreadSuspendTriggerOffset<4>().Int32Value()); |
| 894 | } |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 895 | return NewLIR3(kX86Test32RM, rs_rAX.GetReg(), rs_rAX.GetReg(), 0); |
Dave Allison | b373e09 | 2014-02-20 16:06:36 -0800 | [diff] [blame] | 896 | } |
| 897 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 898 | uint64_t X86Mir2Lir::GetTargetInstFlags(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 899 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 900 | return X86Mir2Lir::EncodingMap[opcode].flags; |
| 901 | } |
| 902 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 903 | const char* X86Mir2Lir::GetTargetInstName(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 904 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 905 | return X86Mir2Lir::EncodingMap[opcode].name; |
| 906 | } |
| 907 | |
Brian Carlstrom | 2ce745c | 2013-07-17 17:44:30 -0700 | [diff] [blame] | 908 | const char* X86Mir2Lir::GetTargetInstFmt(int opcode) { |
buzbee | 409fe94 | 2013-10-11 10:49:56 -0700 | [diff] [blame] | 909 | DCHECK(!IsPseudoLirOp(opcode)); |
Brian Carlstrom | 7940e44 | 2013-07-12 13:46:57 -0700 | [diff] [blame] | 910 | return X86Mir2Lir::EncodingMap[opcode].fmt; |
| 911 | } |
| 912 | |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 913 | void X86Mir2Lir::GenConstWide(RegLocation rl_dest, int64_t value) { |
| 914 | // Can we do this directly to memory? |
| 915 | rl_dest = UpdateLocWide(rl_dest); |
| 916 | if ((rl_dest.location == kLocDalvikFrame) || |
| 917 | (rl_dest.location == kLocCompilerTemp)) { |
| 918 | int32_t val_lo = Low32Bits(value); |
| 919 | int32_t val_hi = High32Bits(value); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 920 | int r_base = rs_rX86_SP.GetReg(); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 921 | int displacement = SRegOffset(rl_dest.s_reg_low); |
| 922 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 923 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 924 | LIR * store = NewLIR3(kX86Mov32MI, r_base, displacement + LOWORD_OFFSET, val_lo); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 925 | AnnotateDalvikRegAccess(store, (displacement + LOWORD_OFFSET) >> 2, |
| 926 | false /* is_load */, true /* is64bit */); |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 927 | store = NewLIR3(kX86Mov32MI, r_base, displacement + HIWORD_OFFSET, val_hi); |
Bill Buzbee | d61ba4b | 2014-01-13 21:44:01 +0000 | [diff] [blame] | 928 | AnnotateDalvikRegAccess(store, (displacement + HIWORD_OFFSET) >> 2, |
| 929 | false /* is_load */, true /* is64bit */); |
| 930 | return; |
| 931 | } |
| 932 | |
| 933 | // Just use the standard code to do the generation. |
| 934 | Mir2Lir::GenConstWide(rl_dest, value); |
| 935 | } |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 936 | |
| 937 | // TODO: Merge with existing RegLocation dumper in vreg_analysis.cc |
| 938 | void X86Mir2Lir::DumpRegLocation(RegLocation loc) { |
| 939 | LOG(INFO) << "location: " << loc.location << ',' |
| 940 | << (loc.wide ? " w" : " ") |
| 941 | << (loc.defined ? " D" : " ") |
| 942 | << (loc.is_const ? " c" : " ") |
| 943 | << (loc.fp ? " F" : " ") |
| 944 | << (loc.core ? " C" : " ") |
| 945 | << (loc.ref ? " r" : " ") |
| 946 | << (loc.high_word ? " h" : " ") |
| 947 | << (loc.home ? " H" : " ") |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 948 | << ", low: " << static_cast<int>(loc.reg.GetLowReg()) |
Bill Buzbee | 00e1ec6 | 2014-02-27 23:44:13 +0000 | [diff] [blame] | 949 | << ", high: " << static_cast<int>(loc.reg.GetHighReg()) |
Mark Mendell | e02d48f | 2014-01-15 11:19:23 -0800 | [diff] [blame] | 950 | << ", s_reg: " << loc.s_reg_low |
| 951 | << ", orig: " << loc.orig_sreg; |
| 952 | } |
| 953 | |
Mark Mendell | 67c39c4 | 2014-01-31 17:28:00 -0800 | [diff] [blame] | 954 | void X86Mir2Lir::Materialize() { |
| 955 | // A good place to put the analysis before starting. |
| 956 | AnalyzeMIR(); |
| 957 | |
| 958 | // Now continue with regular code generation. |
| 959 | Mir2Lir::Materialize(); |
| 960 | } |
| 961 | |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 962 | void X86Mir2Lir::LoadMethodAddress(const MethodReference& target_method, InvokeType type, |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 963 | SpecialTargetRegister symbolic_reg) { |
| 964 | /* |
| 965 | * For x86, just generate a 32 bit move immediate instruction, that will be filled |
| 966 | * in at 'link time'. For now, put a unique value based on target to ensure that |
| 967 | * code deduplication works. |
| 968 | */ |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 969 | int target_method_idx = target_method.dex_method_index; |
| 970 | const DexFile* target_dex_file = target_method.dex_file; |
| 971 | const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); |
| 972 | uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 973 | |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 974 | // Generate the move instruction with the unique pointer and save index, dex_file, and type. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 975 | LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, |
| 976 | TargetReg(symbolic_reg, kNotWide).GetReg(), |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 977 | static_cast<int>(target_method_id_ptr), target_method_idx, |
| 978 | WrapPointer(const_cast<DexFile*>(target_dex_file)), type); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 979 | AppendLIR(move); |
| 980 | method_address_insns_.Insert(move); |
| 981 | } |
| 982 | |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 983 | void X86Mir2Lir::LoadClassType(const DexFile& dex_file, uint32_t type_idx, |
| 984 | SpecialTargetRegister symbolic_reg) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 985 | /* |
| 986 | * For x86, just generate a 32 bit move immediate instruction, that will be filled |
| 987 | * in at 'link time'. For now, put a unique value based on target to ensure that |
| 988 | * code deduplication works. |
| 989 | */ |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 990 | const DexFile::TypeId& id = dex_file.GetTypeId(type_idx); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 991 | uintptr_t ptr = reinterpret_cast<uintptr_t>(&id); |
| 992 | |
| 993 | // Generate the move instruction with the unique pointer and save index and type. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 994 | LIR *move = RawLIR(current_dalvik_offset_, kX86Mov32RI, |
| 995 | TargetReg(symbolic_reg, kNotWide).GetReg(), |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 996 | static_cast<int>(ptr), type_idx, |
| 997 | WrapPointer(const_cast<DexFile*>(&dex_file))); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 998 | AppendLIR(move); |
| 999 | class_type_address_insns_.Insert(move); |
| 1000 | } |
| 1001 | |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 1002 | LIR *X86Mir2Lir::CallWithLinkerFixup(const MethodReference& target_method, InvokeType type) { |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1003 | /* |
| 1004 | * For x86, just generate a 32 bit call relative instruction, that will be filled |
| 1005 | * in at 'link time'. For now, put a unique value based on target to ensure that |
| 1006 | * code deduplication works. |
| 1007 | */ |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 1008 | int target_method_idx = target_method.dex_method_index; |
| 1009 | const DexFile* target_dex_file = target_method.dex_file; |
| 1010 | const DexFile::MethodId& target_method_id = target_dex_file->GetMethodId(target_method_idx); |
| 1011 | uintptr_t target_method_id_ptr = reinterpret_cast<uintptr_t>(&target_method_id); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1012 | |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 1013 | // Generate the call instruction with the unique pointer and save index, dex_file, and type. |
| 1014 | LIR *call = RawLIR(current_dalvik_offset_, kX86CallI, static_cast<int>(target_method_id_ptr), |
| 1015 | target_method_idx, WrapPointer(const_cast<DexFile*>(target_dex_file)), type); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1016 | AppendLIR(call); |
| 1017 | call_method_insns_.Insert(call); |
| 1018 | return call; |
| 1019 | } |
| 1020 | |
| 1021 | void X86Mir2Lir::InstallLiteralPools() { |
| 1022 | // These are handled differently for x86. |
| 1023 | DCHECK(code_literal_list_ == nullptr); |
| 1024 | DCHECK(method_literal_list_ == nullptr); |
| 1025 | DCHECK(class_literal_list_ == nullptr); |
| 1026 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1027 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1028 | if (const_vectors_ != nullptr) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1029 | // Vector literals must be 16-byte aligned. The header that is placed |
| 1030 | // in the code section causes misalignment so we take it into account. |
| 1031 | // Otherwise, we are sure that for x86 method is aligned to 16. |
| 1032 | DCHECK_EQ(GetInstructionSetAlignment(cu_->instruction_set), 16u); |
| 1033 | uint32_t bytes_to_fill = (0x10 - ((code_buffer_.size() + sizeof(OatQuickMethodHeader)) & 0xF)) & 0xF; |
| 1034 | while (bytes_to_fill > 0) { |
| 1035 | code_buffer_.push_back(0); |
| 1036 | bytes_to_fill--; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1037 | } |
| 1038 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1039 | for (LIR *p = const_vectors_; p != nullptr; p = p->next) { |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1040 | PushWord(&code_buffer_, p->operands[0]); |
| 1041 | PushWord(&code_buffer_, p->operands[1]); |
| 1042 | PushWord(&code_buffer_, p->operands[2]); |
| 1043 | PushWord(&code_buffer_, p->operands[3]); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1044 | } |
| 1045 | } |
| 1046 | |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1047 | // Handle the fixups for methods. |
| 1048 | for (uint32_t i = 0; i < method_address_insns_.Size(); i++) { |
| 1049 | LIR* p = method_address_insns_.Get(i); |
| 1050 | DCHECK_EQ(p->opcode, kX86Mov32RI); |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 1051 | uint32_t target_method_idx = p->operands[2]; |
| 1052 | const DexFile* target_dex_file = |
| 1053 | reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[3])); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1054 | |
| 1055 | // The offset to patch is the last 4 bytes of the instruction. |
| 1056 | int patch_offset = p->offset + p->flags.size - 4; |
| 1057 | cu_->compiler_driver->AddMethodPatch(cu_->dex_file, cu_->class_def_idx, |
| 1058 | cu_->method_idx, cu_->invoke_type, |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 1059 | target_method_idx, target_dex_file, |
| 1060 | static_cast<InvokeType>(p->operands[4]), |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1061 | patch_offset); |
| 1062 | } |
| 1063 | |
| 1064 | // Handle the fixups for class types. |
| 1065 | for (uint32_t i = 0; i < class_type_address_insns_.Size(); i++) { |
| 1066 | LIR* p = class_type_address_insns_.Get(i); |
| 1067 | DCHECK_EQ(p->opcode, kX86Mov32RI); |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 1068 | |
| 1069 | const DexFile* class_dex_file = |
| 1070 | reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[3])); |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 1071 | uint32_t target_method_idx = p->operands[2]; |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1072 | |
| 1073 | // The offset to patch is the last 4 bytes of the instruction. |
| 1074 | int patch_offset = p->offset + p->flags.size - 4; |
| 1075 | cu_->compiler_driver->AddClassPatch(cu_->dex_file, cu_->class_def_idx, |
Fred Shih | e7f82e2 | 2014-08-06 10:46:37 -0700 | [diff] [blame] | 1076 | cu_->method_idx, target_method_idx, class_dex_file, |
| 1077 | patch_offset); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1078 | } |
| 1079 | |
| 1080 | // And now the PC-relative calls to methods. |
| 1081 | for (uint32_t i = 0; i < call_method_insns_.Size(); i++) { |
| 1082 | LIR* p = call_method_insns_.Get(i); |
| 1083 | DCHECK_EQ(p->opcode, kX86CallI); |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 1084 | uint32_t target_method_idx = p->operands[1]; |
| 1085 | const DexFile* target_dex_file = |
| 1086 | reinterpret_cast<const DexFile*>(UnwrapPointer(p->operands[2])); |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1087 | |
| 1088 | // The offset to patch is the last 4 bytes of the instruction. |
| 1089 | int patch_offset = p->offset + p->flags.size - 4; |
| 1090 | cu_->compiler_driver->AddRelativeCodePatch(cu_->dex_file, cu_->class_def_idx, |
Jeff Hao | 49161ce | 2014-03-12 11:05:25 -0700 | [diff] [blame] | 1091 | cu_->method_idx, cu_->invoke_type, |
| 1092 | target_method_idx, target_dex_file, |
| 1093 | static_cast<InvokeType>(p->operands[3]), |
Mark Mendell | 55d0eac | 2014-02-06 11:02:52 -0800 | [diff] [blame] | 1094 | patch_offset, -4 /* offset */); |
| 1095 | } |
| 1096 | |
| 1097 | // And do the normal processing. |
| 1098 | Mir2Lir::InstallLiteralPools(); |
| 1099 | } |
| 1100 | |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1101 | bool X86Mir2Lir::GenInlinedArrayCopyCharArray(CallInfo* info) { |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1102 | RegLocation rl_src = info->args[0]; |
| 1103 | RegLocation rl_srcPos = info->args[1]; |
| 1104 | RegLocation rl_dst = info->args[2]; |
| 1105 | RegLocation rl_dstPos = info->args[3]; |
| 1106 | RegLocation rl_length = info->args[4]; |
| 1107 | if (rl_srcPos.is_const && (mir_graph_->ConstantValue(rl_srcPos) < 0)) { |
| 1108 | return false; |
| 1109 | } |
| 1110 | if (rl_dstPos.is_const && (mir_graph_->ConstantValue(rl_dstPos) < 0)) { |
| 1111 | return false; |
| 1112 | } |
| 1113 | ClobberCallerSave(); |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1114 | LockCallTemps(); // Using fixed registers. |
| 1115 | RegStorage tmp_reg = cu_->target64 ? rs_r11 : rs_rBX; |
| 1116 | LoadValueDirectFixed(rl_src, rs_rAX); |
| 1117 | LoadValueDirectFixed(rl_dst, rs_rCX); |
| 1118 | LIR* src_dst_same = OpCmpBranch(kCondEq, rs_rAX, rs_rCX, nullptr); |
| 1119 | LIR* src_null_branch = OpCmpImmBranch(kCondEq, rs_rAX, 0, nullptr); |
| 1120 | LIR* dst_null_branch = OpCmpImmBranch(kCondEq, rs_rCX, 0, nullptr); |
| 1121 | LoadValueDirectFixed(rl_length, rs_rDX); |
| 1122 | // If the length of the copy is > 128 characters (256 bytes) or negative then go slow path. |
| 1123 | LIR* len_too_big = OpCmpImmBranch(kCondHi, rs_rDX, 128, nullptr); |
| 1124 | LoadValueDirectFixed(rl_src, rs_rAX); |
| 1125 | LoadWordDisp(rs_rAX, mirror::Array::LengthOffset().Int32Value(), rs_rAX); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1126 | LIR* src_bad_len = nullptr; |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame^] | 1127 | LIR* src_bad_off = nullptr; |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1128 | LIR* srcPos_negative = nullptr; |
| 1129 | if (!rl_srcPos.is_const) { |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1130 | LoadValueDirectFixed(rl_srcPos, tmp_reg); |
| 1131 | srcPos_negative = OpCmpImmBranch(kCondLt, tmp_reg, 0, nullptr); |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame^] | 1132 | // src_pos < src_len |
| 1133 | src_bad_off = OpCmpBranch(kCondLt, rs_rAX, tmp_reg, nullptr); |
| 1134 | // src_len - src_pos < copy_len |
| 1135 | OpRegRegReg(kOpSub, tmp_reg, rs_rAX, tmp_reg); |
| 1136 | src_bad_len = OpCmpBranch(kCondLt, tmp_reg, rs_rDX, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1137 | } else { |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1138 | int32_t pos_val = mir_graph_->ConstantValue(rl_srcPos.orig_sreg); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1139 | if (pos_val == 0) { |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1140 | src_bad_len = OpCmpBranch(kCondLt, rs_rAX, rs_rDX, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1141 | } else { |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame^] | 1142 | // src_pos < src_len |
| 1143 | src_bad_off = OpCmpImmBranch(kCondLt, rs_rAX, pos_val, nullptr); |
| 1144 | // src_len - src_pos < copy_len |
| 1145 | OpRegRegImm(kOpSub, tmp_reg, rs_rAX, pos_val); |
| 1146 | src_bad_len = OpCmpBranch(kCondLt, tmp_reg, rs_rDX, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1147 | } |
| 1148 | } |
| 1149 | LIR* dstPos_negative = nullptr; |
| 1150 | LIR* dst_bad_len = nullptr; |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame^] | 1151 | LIR* dst_bad_off = nullptr; |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1152 | LoadValueDirectFixed(rl_dst, rs_rAX); |
| 1153 | LoadWordDisp(rs_rAX, mirror::Array::LengthOffset().Int32Value(), rs_rAX); |
| 1154 | if (!rl_dstPos.is_const) { |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1155 | LoadValueDirectFixed(rl_dstPos, tmp_reg); |
| 1156 | dstPos_negative = OpCmpImmBranch(kCondLt, tmp_reg, 0, nullptr); |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame^] | 1157 | // dst_pos < dst_len |
| 1158 | dst_bad_off = OpCmpBranch(kCondLt, rs_rAX, tmp_reg, nullptr); |
| 1159 | // dst_len - dst_pos < copy_len |
| 1160 | OpRegRegReg(kOpSub, tmp_reg, rs_rAX, tmp_reg); |
| 1161 | dst_bad_len = OpCmpBranch(kCondLt, tmp_reg, rs_rDX, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1162 | } else { |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1163 | int32_t pos_val = mir_graph_->ConstantValue(rl_dstPos.orig_sreg); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1164 | if (pos_val == 0) { |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1165 | dst_bad_len = OpCmpBranch(kCondLt, rs_rAX, rs_rDX, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1166 | } else { |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame^] | 1167 | // dst_pos < dst_len |
| 1168 | dst_bad_off = OpCmpImmBranch(kCondLt, rs_rAX, pos_val, nullptr); |
| 1169 | // dst_len - dst_pos < copy_len |
| 1170 | OpRegRegImm(kOpSub, tmp_reg, rs_rAX, pos_val); |
| 1171 | dst_bad_len = OpCmpBranch(kCondLt, tmp_reg, rs_rDX, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1172 | } |
| 1173 | } |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1174 | // Everything is checked now. |
| 1175 | LoadValueDirectFixed(rl_src, rs_rAX); |
| 1176 | LoadValueDirectFixed(rl_dst, tmp_reg); |
| 1177 | LoadValueDirectFixed(rl_srcPos, rs_rCX); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1178 | NewLIR5(kX86Lea32RA, rs_rAX.GetReg(), rs_rAX.GetReg(), |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1179 | rs_rCX.GetReg(), 1, mirror::Array::DataOffset(2).Int32Value()); |
| 1180 | // RAX now holds the address of the first src element to be copied. |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1181 | |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1182 | LoadValueDirectFixed(rl_dstPos, rs_rCX); |
| 1183 | NewLIR5(kX86Lea32RA, tmp_reg.GetReg(), tmp_reg.GetReg(), |
| 1184 | rs_rCX.GetReg(), 1, mirror::Array::DataOffset(2).Int32Value() ); |
| 1185 | // RBX now holds the address of the first dst element to be copied. |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1186 | |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1187 | // Check if the number of elements to be copied is odd or even. If odd |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1188 | // then copy the first element (so that the remaining number of elements |
| 1189 | // is even). |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1190 | LoadValueDirectFixed(rl_length, rs_rCX); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1191 | OpRegImm(kOpAnd, rs_rCX, 1); |
| 1192 | LIR* jmp_to_begin_loop = OpCmpImmBranch(kCondEq, rs_rCX, 0, nullptr); |
| 1193 | OpRegImm(kOpSub, rs_rDX, 1); |
| 1194 | LoadBaseIndexedDisp(rs_rAX, rs_rDX, 1, 0, rs_rCX, kSignedHalf); |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1195 | StoreBaseIndexedDisp(tmp_reg, rs_rDX, 1, 0, rs_rCX, kSignedHalf); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1196 | |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1197 | // Since the remaining number of elements is even, we will copy by |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1198 | // two elements at a time. |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1199 | LIR* beginLoop = NewLIR0(kPseudoTargetLabel); |
| 1200 | LIR* jmp_to_ret = OpCmpImmBranch(kCondEq, rs_rDX, 0, nullptr); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1201 | OpRegImm(kOpSub, rs_rDX, 2); |
| 1202 | LoadBaseIndexedDisp(rs_rAX, rs_rDX, 1, 0, rs_rCX, kSingle); |
DaniilSokolov | 5a5e856 | 2014-07-17 18:58:15 -0700 | [diff] [blame] | 1203 | StoreBaseIndexedDisp(tmp_reg, rs_rDX, 1, 0, rs_rCX, kSingle); |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1204 | OpUnconditionalBranch(beginLoop); |
| 1205 | LIR *check_failed = NewLIR0(kPseudoTargetLabel); |
| 1206 | LIR* launchpad_branch = OpUnconditionalBranch(nullptr); |
| 1207 | LIR *return_point = NewLIR0(kPseudoTargetLabel); |
| 1208 | jmp_to_ret->target = return_point; |
| 1209 | jmp_to_begin_loop->target = beginLoop; |
| 1210 | src_dst_same->target = check_failed; |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1211 | len_too_big->target = check_failed; |
| 1212 | src_null_branch->target = check_failed; |
| 1213 | if (srcPos_negative != nullptr) |
| 1214 | srcPos_negative ->target = check_failed; |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame^] | 1215 | if (src_bad_off != nullptr) |
| 1216 | src_bad_off->target = check_failed; |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1217 | if (src_bad_len != nullptr) |
| 1218 | src_bad_len->target = check_failed; |
| 1219 | dst_null_branch->target = check_failed; |
| 1220 | if (dstPos_negative != nullptr) |
| 1221 | dstPos_negative->target = check_failed; |
avignate | f9f0ed4 | 2014-09-17 22:35:07 +0700 | [diff] [blame^] | 1222 | if (dst_bad_off != nullptr) |
| 1223 | dst_bad_off->target = check_failed; |
DaniilSokolov | 70c4f06 | 2014-06-24 17:34:00 -0700 | [diff] [blame] | 1224 | if (dst_bad_len != nullptr) |
| 1225 | dst_bad_len->target = check_failed; |
| 1226 | AddIntrinsicSlowPath(info, launchpad_branch, return_point); |
| 1227 | return true; |
| 1228 | } |
| 1229 | |
| 1230 | |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1231 | /* |
| 1232 | * Fast string.index_of(I) & (II). Inline check for simple case of char <= 0xffff, |
| 1233 | * otherwise bails to standard library code. |
| 1234 | */ |
| 1235 | bool X86Mir2Lir::GenInlinedIndexOf(CallInfo* info, bool zero_based) { |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1236 | RegLocation rl_obj = info->args[0]; |
| 1237 | RegLocation rl_char = info->args[1]; |
buzbee | a44d4f5 | 2014-03-05 11:26:39 -0800 | [diff] [blame] | 1238 | RegLocation rl_start; // Note: only present in III flavor or IndexOf. |
nikolay serdjuk | 8bd698f | 2014-08-01 09:24:06 +0700 | [diff] [blame] | 1239 | // RBX is promotable in 64-bit mode. |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1240 | RegStorage rs_tmp = cu_->target64 ? rs_r11 : rs_rBX; |
| 1241 | int start_value = -1; |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1242 | |
| 1243 | uint32_t char_value = |
| 1244 | rl_char.is_const ? mir_graph_->ConstantValue(rl_char.orig_sreg) : 0; |
| 1245 | |
| 1246 | if (char_value > 0xFFFF) { |
| 1247 | // We have to punt to the real String.indexOf. |
| 1248 | return false; |
| 1249 | } |
| 1250 | |
| 1251 | // Okay, we are commited to inlining this. |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1252 | // EAX: 16 bit character being searched. |
| 1253 | // ECX: count: number of words to be searched. |
| 1254 | // EDI: String being searched. |
| 1255 | // EDX: temporary during execution. |
| 1256 | // EBX or R11: temporary during execution (depending on mode). |
| 1257 | // REP SCASW: search instruction. |
| 1258 | |
nikolay serdjuk | 8bd698f | 2014-08-01 09:24:06 +0700 | [diff] [blame] | 1259 | FlushAllRegs(); |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1260 | |
buzbee | a0cd2d7 | 2014-06-01 09:33:49 -0700 | [diff] [blame] | 1261 | RegLocation rl_return = GetReturn(kCoreReg); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1262 | RegLocation rl_dest = InlineTarget(info); |
| 1263 | |
| 1264 | // Is the string non-NULL? |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1265 | LoadValueDirectFixed(rl_obj, rs_rDX); |
| 1266 | GenNullCheck(rs_rDX, info->opt_flags); |
Vladimir Marko | 3bc8615 | 2014-03-13 14:11:28 +0000 | [diff] [blame] | 1267 | info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've null checked. |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1268 | |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1269 | LIR *slowpath_branch = nullptr, *length_compare = nullptr; |
| 1270 | |
| 1271 | // We need the value in EAX. |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1272 | if (rl_char.is_const) { |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1273 | LoadConstantNoClobber(rs_rAX, char_value); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1274 | } else { |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1275 | // Does the character fit in 16 bits? Compare it at runtime. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1276 | LoadValueDirectFixed(rl_char, rs_rAX); |
Mingyao Yang | 3a74d15 | 2014-04-21 15:39:44 -0700 | [diff] [blame] | 1277 | slowpath_branch = OpCmpImmBranch(kCondGt, rs_rAX, 0xFFFF, nullptr); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1278 | } |
| 1279 | |
| 1280 | // From here down, we know that we are looking for a char that fits in 16 bits. |
Mark Mendell | e19c91f | 2014-02-25 08:19:08 -0800 | [diff] [blame] | 1281 | // Location of reference to data array within the String object. |
| 1282 | int value_offset = mirror::String::ValueOffset().Int32Value(); |
| 1283 | // Location of count within the String object. |
| 1284 | int count_offset = mirror::String::CountOffset().Int32Value(); |
| 1285 | // Starting offset within data array. |
| 1286 | int offset_offset = mirror::String::OffsetOffset().Int32Value(); |
| 1287 | // Start of char data with array_. |
| 1288 | int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1289 | |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 1290 | // Compute the number of words to search in to rCX. |
| 1291 | Load32Disp(rs_rDX, count_offset, rs_rCX); |
| 1292 | |
Dave Allison | dfd3b47 | 2014-07-16 16:04:32 -0700 | [diff] [blame] | 1293 | // Possible signal here due to null pointer dereference. |
| 1294 | // Note that the signal handler will expect the top word of |
| 1295 | // the stack to be the ArtMethod*. If the PUSH edi instruction |
| 1296 | // below is ahead of the load above then this will not be true |
| 1297 | // and the signal handler will not work. |
| 1298 | MarkPossibleNullPointerException(0); |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 1299 | |
Dave Allison | dfd3b47 | 2014-07-16 16:04:32 -0700 | [diff] [blame] | 1300 | if (!cu_->target64) { |
nikolay serdjuk | 8bd698f | 2014-08-01 09:24:06 +0700 | [diff] [blame] | 1301 | // EDI is promotable in 32-bit mode. |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1302 | NewLIR1(kX86Push32R, rs_rDI.GetReg()); |
| 1303 | } |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1304 | |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1305 | if (zero_based) { |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1306 | // Start index is not present. |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1307 | // We have to handle an empty string. Use special instruction JECXZ. |
| 1308 | length_compare = NewLIR0(kX86Jecxz8); |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1309 | |
| 1310 | // Copy the number of words to search in a temporary register. |
| 1311 | // We will use the register at the end to calculate result. |
| 1312 | OpRegReg(kOpMov, rs_tmp, rs_rCX); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1313 | } else { |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1314 | // Start index is present. |
buzbee | a44d4f5 | 2014-03-05 11:26:39 -0800 | [diff] [blame] | 1315 | rl_start = info->args[2]; |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1316 | |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1317 | // We have to offset by the start index. |
| 1318 | if (rl_start.is_const) { |
| 1319 | start_value = mir_graph_->ConstantValue(rl_start.orig_sreg); |
| 1320 | start_value = std::max(start_value, 0); |
| 1321 | |
| 1322 | // Is the start > count? |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1323 | length_compare = OpCmpImmBranch(kCondLe, rs_rCX, start_value, nullptr); |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1324 | OpRegImm(kOpMov, rs_rDI, start_value); |
| 1325 | |
| 1326 | // Copy the number of words to search in a temporary register. |
| 1327 | // We will use the register at the end to calculate result. |
| 1328 | OpRegReg(kOpMov, rs_tmp, rs_rCX); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1329 | |
| 1330 | if (start_value != 0) { |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1331 | // Decrease the number of words to search by the start index. |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1332 | OpRegImm(kOpSub, rs_rCX, start_value); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1333 | } |
| 1334 | } else { |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1335 | // Handle "start index < 0" case. |
| 1336 | if (!cu_->target64 && rl_start.location != kLocPhysReg) { |
Alexei Zavjalov | a1758d8 | 2014-04-17 01:55:43 +0700 | [diff] [blame] | 1337 | // Load the start index from stack, remembering that we pushed EDI. |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1338 | int displacement = SRegOffset(rl_start.s_reg_low) + sizeof(uint32_t); |
Vladimir Marko | 74de63b | 2014-08-19 15:00:34 +0100 | [diff] [blame] | 1339 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 1340 | Load32Disp(rs_rX86_SP, displacement, rs_rDI); |
| 1341 | // Dalvik register annotation in LoadBaseIndexedDisp() used wrong offset. Fix it. |
| 1342 | DCHECK(!DECODE_ALIAS_INFO_WIDE(last_lir_insn_->flags.alias_info)); |
| 1343 | int reg_id = DECODE_ALIAS_INFO_REG(last_lir_insn_->flags.alias_info) - 1; |
| 1344 | AnnotateDalvikRegAccess(last_lir_insn_, reg_id, true, false); |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1345 | } else { |
| 1346 | LoadValueDirectFixed(rl_start, rs_rDI); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1347 | } |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1348 | OpRegReg(kOpXor, rs_tmp, rs_tmp); |
| 1349 | OpRegReg(kOpCmp, rs_rDI, rs_tmp); |
| 1350 | OpCondRegReg(kOpCmov, kCondLt, rs_rDI, rs_tmp); |
| 1351 | |
| 1352 | // The length of the string should be greater than the start index. |
| 1353 | length_compare = OpCmpBranch(kCondLe, rs_rCX, rs_rDI, nullptr); |
| 1354 | |
| 1355 | // Copy the number of words to search in a temporary register. |
| 1356 | // We will use the register at the end to calculate result. |
| 1357 | OpRegReg(kOpMov, rs_tmp, rs_rCX); |
| 1358 | |
| 1359 | // Decrease the number of words to search by the start index. |
| 1360 | OpRegReg(kOpSub, rs_rCX, rs_rDI); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1361 | } |
| 1362 | } |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1363 | |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1364 | // Load the address of the string into EDI. |
| 1365 | // In case of start index we have to add the address to existing value in EDI. |
Mark Mendell | e19c91f | 2014-02-25 08:19:08 -0800 | [diff] [blame] | 1366 | // The string starts at VALUE(String) + 2 * OFFSET(String) + DATA_OFFSET. |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1367 | if (zero_based || (!zero_based && rl_start.is_const && start_value == 0)) { |
| 1368 | Load32Disp(rs_rDX, offset_offset, rs_rDI); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1369 | } else { |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1370 | OpRegMem(kOpAdd, rs_rDI, rs_rDX, offset_offset); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1371 | } |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1372 | OpRegImm(kOpLsl, rs_rDI, 1); |
| 1373 | OpRegMem(kOpAdd, rs_rDI, rs_rDX, value_offset); |
| 1374 | OpRegImm(kOpAdd, rs_rDI, data_offset); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1375 | |
| 1376 | // EDI now contains the start of the string to be searched. |
| 1377 | // We are all prepared to do the search for the character. |
| 1378 | NewLIR0(kX86RepneScasw); |
| 1379 | |
| 1380 | // Did we find a match? |
| 1381 | LIR* failed_branch = OpCondBranch(kCondNe, nullptr); |
| 1382 | |
| 1383 | // yes, we matched. Compute the index of the result. |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1384 | OpRegReg(kOpSub, rs_tmp, rs_rCX); |
| 1385 | NewLIR3(kX86Lea32RM, rl_return.reg.GetReg(), rs_tmp.GetReg(), -1); |
| 1386 | |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1387 | LIR *all_done = NewLIR1(kX86Jmp8, 0); |
| 1388 | |
| 1389 | // Failed to match; return -1. |
| 1390 | LIR *not_found = NewLIR0(kPseudoTargetLabel); |
| 1391 | length_compare->target = not_found; |
| 1392 | failed_branch->target = not_found; |
buzbee | 2700f7e | 2014-03-07 09:46:20 -0800 | [diff] [blame] | 1393 | LoadConstantNoClobber(rl_return.reg, -1); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1394 | |
| 1395 | // And join up at the end. |
| 1396 | all_done->target = NewLIR0(kPseudoTargetLabel); |
nikolay serdjuk | c3561ae | 2014-07-18 12:35:46 +0700 | [diff] [blame] | 1397 | |
| 1398 | if (!cu_->target64) |
| 1399 | NewLIR1(kX86Pop32R, rs_rDI.GetReg()); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1400 | |
| 1401 | // Out of line code returns here. |
Mingyao Yang | 3a74d15 | 2014-04-21 15:39:44 -0700 | [diff] [blame] | 1402 | if (slowpath_branch != nullptr) { |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1403 | LIR *return_point = NewLIR0(kPseudoTargetLabel); |
Mingyao Yang | 3a74d15 | 2014-04-21 15:39:44 -0700 | [diff] [blame] | 1404 | AddIntrinsicSlowPath(info, slowpath_branch, return_point); |
Mark Mendell | 4028a6c | 2014-02-19 20:06:20 -0800 | [diff] [blame] | 1405 | } |
| 1406 | |
| 1407 | StoreValue(rl_dest, rl_return); |
| 1408 | return true; |
| 1409 | } |
| 1410 | |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1411 | static bool ARTRegIDToDWARFRegID(bool is_x86_64, int art_reg_id, int* dwarf_reg_id) { |
| 1412 | if (is_x86_64) { |
| 1413 | switch (art_reg_id) { |
Andreas Gampe | bda2722 | 2014-07-30 23:21:36 -0700 | [diff] [blame] | 1414 | case 3 : *dwarf_reg_id = 3; return true; // %rbx |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1415 | // This is the only discrepancy between ART & DWARF register numbering. |
Andreas Gampe | bda2722 | 2014-07-30 23:21:36 -0700 | [diff] [blame] | 1416 | case 5 : *dwarf_reg_id = 6; return true; // %rbp |
| 1417 | case 12: *dwarf_reg_id = 12; return true; // %r12 |
| 1418 | case 13: *dwarf_reg_id = 13; return true; // %r13 |
| 1419 | case 14: *dwarf_reg_id = 14; return true; // %r14 |
| 1420 | case 15: *dwarf_reg_id = 15; return true; // %r15 |
| 1421 | default: return false; // Should not get here |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1422 | } |
| 1423 | } else { |
| 1424 | switch (art_reg_id) { |
Andreas Gampe | bda2722 | 2014-07-30 23:21:36 -0700 | [diff] [blame] | 1425 | case 5: *dwarf_reg_id = 5; return true; // %ebp |
| 1426 | case 6: *dwarf_reg_id = 6; return true; // %esi |
| 1427 | case 7: *dwarf_reg_id = 7; return true; // %edi |
| 1428 | default: return false; // Should not get here |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1429 | } |
| 1430 | } |
| 1431 | } |
| 1432 | |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1433 | std::vector<uint8_t>* X86Mir2Lir::ReturnFrameDescriptionEntry() { |
| 1434 | std::vector<uint8_t>* cfi_info = new std::vector<uint8_t>; |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1435 | |
| 1436 | // Generate the FDE for the method. |
| 1437 | DCHECK_NE(data_offset_, 0U); |
| 1438 | |
Yevgeny Rouban | e3ea838 | 2014-08-08 16:29:38 +0700 | [diff] [blame] | 1439 | WriteFDEHeader(cfi_info, cu_->target64); |
| 1440 | WriteFDEAddressRange(cfi_info, data_offset_, cu_->target64); |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1441 | |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1442 | // The instructions in the FDE. |
| 1443 | if (stack_decrement_ != nullptr) { |
| 1444 | // Advance LOC to just past the stack decrement. |
| 1445 | uint32_t pc = NEXT_LIR(stack_decrement_)->offset; |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1446 | DW_CFA_advance_loc(cfi_info, pc); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1447 | |
| 1448 | // Now update the offset to the call frame: DW_CFA_def_cfa_offset frame_size. |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1449 | DW_CFA_def_cfa_offset(cfi_info, frame_size_); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1450 | |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1451 | // Handle register spills |
| 1452 | const uint32_t kSpillInstLen = (cu_->target64) ? 5 : 4; |
| 1453 | const int kDataAlignmentFactor = (cu_->target64) ? -8 : -4; |
| 1454 | uint32_t mask = core_spill_mask_ & ~(1 << rs_rRET.GetRegNum()); |
| 1455 | int offset = -(GetInstructionSetPointerSize(cu_->instruction_set) * num_core_spills_); |
| 1456 | for (int reg = 0; mask; mask >>= 1, reg++) { |
| 1457 | if (mask & 0x1) { |
| 1458 | pc += kSpillInstLen; |
| 1459 | |
| 1460 | // Advance LOC to pass this instruction |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1461 | DW_CFA_advance_loc(cfi_info, kSpillInstLen); |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1462 | |
| 1463 | int dwarf_reg_id; |
| 1464 | if (ARTRegIDToDWARFRegID(cu_->target64, reg, &dwarf_reg_id)) { |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1465 | // DW_CFA_offset_extended_sf reg offset |
| 1466 | DW_CFA_offset_extended_sf(cfi_info, dwarf_reg_id, offset / kDataAlignmentFactor); |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1467 | } |
| 1468 | |
| 1469 | offset += GetInstructionSetPointerSize(cu_->instruction_set); |
| 1470 | } |
| 1471 | } |
| 1472 | |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1473 | // We continue with that stack until the epilogue. |
| 1474 | if (stack_increment_ != nullptr) { |
| 1475 | uint32_t new_pc = NEXT_LIR(stack_increment_)->offset; |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1476 | DW_CFA_advance_loc(cfi_info, new_pc - pc); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1477 | |
| 1478 | // We probably have code snippets after the epilogue, so save the |
| 1479 | // current state: DW_CFA_remember_state. |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1480 | DW_CFA_remember_state(cfi_info); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1481 | |
Tong Shen | 35e1e6a | 2014-07-30 09:31:22 -0700 | [diff] [blame] | 1482 | // We have now popped the stack: DW_CFA_def_cfa_offset 4/8. |
| 1483 | // There is only the return PC on the stack now. |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1484 | DW_CFA_def_cfa_offset(cfi_info, GetInstructionSetPointerSize(cu_->instruction_set)); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1485 | |
| 1486 | // Everything after that is the same as before the epilogue. |
| 1487 | // Stack bump was followed by RET instruction. |
| 1488 | LIR *post_ret_insn = NEXT_LIR(NEXT_LIR(stack_increment_)); |
| 1489 | if (post_ret_insn != nullptr) { |
| 1490 | pc = new_pc; |
| 1491 | new_pc = post_ret_insn->offset; |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1492 | DW_CFA_advance_loc(cfi_info, new_pc - pc); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1493 | // Restore the state: DW_CFA_restore_state. |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1494 | DW_CFA_restore_state(cfi_info); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1495 | } |
| 1496 | } |
| 1497 | } |
| 1498 | |
Tong Shen | 547cdfd | 2014-08-05 01:54:19 -0700 | [diff] [blame] | 1499 | PadCFI(cfi_info); |
Yevgeny Rouban | e3ea838 | 2014-08-08 16:29:38 +0700 | [diff] [blame] | 1500 | WriteCFILength(cfi_info, cu_->target64); |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1501 | |
Mark Mendell | ae9fd93 | 2014-02-10 16:14:35 -0800 | [diff] [blame] | 1502 | return cfi_info; |
| 1503 | } |
| 1504 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1505 | void X86Mir2Lir::GenMachineSpecificExtendedMethodMIR(BasicBlock* bb, MIR* mir) { |
| 1506 | switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1507 | case kMirOpReserveVectorRegisters: |
| 1508 | ReserveVectorRegisters(mir); |
| 1509 | break; |
| 1510 | case kMirOpReturnVectorRegisters: |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1511 | ReturnVectorRegisters(mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1512 | break; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1513 | case kMirOpConstVector: |
| 1514 | GenConst128(bb, mir); |
| 1515 | break; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1516 | case kMirOpMoveVector: |
| 1517 | GenMoveVector(bb, mir); |
| 1518 | break; |
| 1519 | case kMirOpPackedMultiply: |
| 1520 | GenMultiplyVector(bb, mir); |
| 1521 | break; |
| 1522 | case kMirOpPackedAddition: |
| 1523 | GenAddVector(bb, mir); |
| 1524 | break; |
| 1525 | case kMirOpPackedSubtract: |
| 1526 | GenSubtractVector(bb, mir); |
| 1527 | break; |
| 1528 | case kMirOpPackedShiftLeft: |
| 1529 | GenShiftLeftVector(bb, mir); |
| 1530 | break; |
| 1531 | case kMirOpPackedSignedShiftRight: |
| 1532 | GenSignedShiftRightVector(bb, mir); |
| 1533 | break; |
| 1534 | case kMirOpPackedUnsignedShiftRight: |
| 1535 | GenUnsignedShiftRightVector(bb, mir); |
| 1536 | break; |
| 1537 | case kMirOpPackedAnd: |
| 1538 | GenAndVector(bb, mir); |
| 1539 | break; |
| 1540 | case kMirOpPackedOr: |
| 1541 | GenOrVector(bb, mir); |
| 1542 | break; |
| 1543 | case kMirOpPackedXor: |
| 1544 | GenXorVector(bb, mir); |
| 1545 | break; |
| 1546 | case kMirOpPackedAddReduce: |
| 1547 | GenAddReduceVector(bb, mir); |
| 1548 | break; |
| 1549 | case kMirOpPackedReduce: |
| 1550 | GenReduceVector(bb, mir); |
| 1551 | break; |
| 1552 | case kMirOpPackedSet: |
| 1553 | GenSetVector(bb, mir); |
| 1554 | break; |
Jean Christophe Beyler | b5bce7c | 2014-07-25 12:32:18 -0700 | [diff] [blame] | 1555 | case kMirOpMemBarrier: |
| 1556 | GenMemBarrier(static_cast<MemBarrierKind>(mir->dalvikInsn.vA)); |
| 1557 | break; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1558 | case kMirOpPackedArrayGet: |
| 1559 | GenPackedArrayGet(bb, mir); |
| 1560 | break; |
| 1561 | case kMirOpPackedArrayPut: |
| 1562 | GenPackedArrayPut(bb, mir); |
| 1563 | break; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1564 | default: |
| 1565 | break; |
| 1566 | } |
| 1567 | } |
| 1568 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1569 | void X86Mir2Lir::ReserveVectorRegisters(MIR* mir) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1570 | for (uint32_t i = mir->dalvikInsn.vA; i <= mir->dalvikInsn.vB; i++) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1571 | RegStorage xp_reg = RegStorage::Solo128(i); |
| 1572 | RegisterInfo *xp_reg_info = GetRegInfo(xp_reg); |
| 1573 | Clobber(xp_reg); |
| 1574 | |
| 1575 | for (RegisterInfo *info = xp_reg_info->GetAliasChain(); |
| 1576 | info != nullptr; |
| 1577 | info = info->GetAliasChain()) { |
| 1578 | if (info->GetReg().IsSingle()) { |
| 1579 | reg_pool_->sp_regs_.Delete(info); |
| 1580 | } else { |
| 1581 | reg_pool_->dp_regs_.Delete(info); |
| 1582 | } |
| 1583 | } |
| 1584 | } |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1585 | } |
| 1586 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1587 | void X86Mir2Lir::ReturnVectorRegisters(MIR* mir) { |
| 1588 | for (uint32_t i = mir->dalvikInsn.vA; i <= mir->dalvikInsn.vB; i++) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1589 | RegStorage xp_reg = RegStorage::Solo128(i); |
| 1590 | RegisterInfo *xp_reg_info = GetRegInfo(xp_reg); |
| 1591 | |
| 1592 | for (RegisterInfo *info = xp_reg_info->GetAliasChain(); |
| 1593 | info != nullptr; |
| 1594 | info = info->GetAliasChain()) { |
| 1595 | if (info->GetReg().IsSingle()) { |
| 1596 | reg_pool_->sp_regs_.Insert(info); |
| 1597 | } else { |
| 1598 | reg_pool_->dp_regs_.Insert(info); |
| 1599 | } |
| 1600 | } |
| 1601 | } |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1602 | } |
| 1603 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1604 | void X86Mir2Lir::GenConst128(BasicBlock* bb, MIR* mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1605 | RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1606 | Clobber(rs_dest); |
| 1607 | |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1608 | uint32_t *args = mir->dalvikInsn.arg; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1609 | int reg = rs_dest.GetReg(); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1610 | // Check for all 0 case. |
| 1611 | if (args[0] == 0 && args[1] == 0 && args[2] == 0 && args[3] == 0) { |
| 1612 | NewLIR2(kX86XorpsRR, reg, reg); |
| 1613 | return; |
| 1614 | } |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1615 | |
| 1616 | // Append the mov const vector to reg opcode. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1617 | AppendOpcodeWithConst(kX86MovdqaRM, reg, mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1618 | } |
| 1619 | |
| 1620 | void X86Mir2Lir::AppendOpcodeWithConst(X86OpCode opcode, int reg, MIR* mir) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1621 | // The literal pool needs position independent logic. |
| 1622 | store_method_addr_used_ = true; |
| 1623 | |
| 1624 | // To deal with correct memory ordering, reverse order of constants. |
| 1625 | int32_t constants[4]; |
| 1626 | constants[3] = mir->dalvikInsn.arg[0]; |
| 1627 | constants[2] = mir->dalvikInsn.arg[1]; |
| 1628 | constants[1] = mir->dalvikInsn.arg[2]; |
| 1629 | constants[0] = mir->dalvikInsn.arg[3]; |
| 1630 | |
| 1631 | // Search if there is already a constant in pool with this value. |
| 1632 | LIR *data_target = ScanVectorLiteral(constants); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1633 | if (data_target == nullptr) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1634 | data_target = AddVectorLiteral(constants); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1635 | } |
| 1636 | |
| 1637 | // Address the start of the method. |
| 1638 | RegLocation rl_method = mir_graph_->GetRegLocation(base_of_code_->s_reg_low); |
Chao-ying Fu | e0ccdc0 | 2014-06-06 17:32:37 -0700 | [diff] [blame] | 1639 | if (rl_method.wide) { |
| 1640 | rl_method = LoadValueWide(rl_method, kCoreReg); |
| 1641 | } else { |
| 1642 | rl_method = LoadValue(rl_method, kCoreReg); |
| 1643 | } |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1644 | |
| 1645 | // Load the proper value from the literal area. |
| 1646 | // We don't know the proper offset for the value, so pick one that will force |
| 1647 | // 4 byte offset. We will fix this up in the assembler later to have the right |
| 1648 | // value. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 1649 | ScopedMemRefType mem_ref_type(this, ResourceMask::kLiteral); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1650 | LIR *load = NewLIR3(opcode, reg, rl_method.reg.GetReg(), 256 /* bogus */); |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1651 | load->flags.fixup = kFixupLoad; |
| 1652 | load->target = data_target; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 1653 | } |
| 1654 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1655 | void X86Mir2Lir::GenMoveVector(BasicBlock *bb, MIR *mir) { |
| 1656 | // We only support 128 bit registers. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1657 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1658 | RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1659 | Clobber(rs_dest); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1660 | RegStorage rs_src = RegStorage::Solo128(mir->dalvikInsn.vB); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1661 | NewLIR2(kX86MovdqaRR, rs_dest.GetReg(), rs_src.GetReg()); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1662 | } |
| 1663 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1664 | void X86Mir2Lir::GenMultiplyVectorSignedByte(RegStorage rs_dest_src1, RegStorage rs_src2) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1665 | /* |
| 1666 | * Emulate the behavior of a kSignedByte by separating out the 16 values in the two XMM |
| 1667 | * and multiplying 8 at a time before recombining back into one XMM register. |
| 1668 | * |
| 1669 | * let xmm1, xmm2 be real srcs (keep low bits of 16bit lanes) |
| 1670 | * xmm3 is tmp (operate on high bits of 16bit lanes) |
| 1671 | * |
| 1672 | * xmm3 = xmm1 |
| 1673 | * xmm1 = xmm1 .* xmm2 |
| 1674 | * xmm1 = xmm1 & 0x00ff00ff00ff00ff00ff00ff00ff00ff // xmm1 now has low bits |
| 1675 | * xmm3 = xmm3 .>> 8 |
| 1676 | * xmm2 = xmm2 & 0xff00ff00ff00ff00ff00ff00ff00ff00 |
| 1677 | * xmm2 = xmm2 .* xmm3 // xmm2 now has high bits |
| 1678 | * xmm1 = xmm1 | xmm2 // combine results |
| 1679 | */ |
| 1680 | |
| 1681 | // Copy xmm1. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1682 | RegStorage rs_src1_high_tmp = Get128BitRegister(AllocTempDouble()); |
| 1683 | RegStorage rs_dest_high_tmp = Get128BitRegister(AllocTempDouble()); |
| 1684 | NewLIR2(kX86MovdqaRR, rs_src1_high_tmp.GetReg(), rs_src2.GetReg()); |
| 1685 | NewLIR2(kX86MovdqaRR, rs_dest_high_tmp.GetReg(), rs_dest_src1.GetReg()); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1686 | |
| 1687 | // Multiply low bits. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1688 | // x7 *= x3 |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1689 | NewLIR2(kX86PmullwRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 1690 | |
| 1691 | // xmm1 now has low bits. |
| 1692 | AndMaskVectorRegister(rs_dest_src1, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF, 0x00FF00FF); |
| 1693 | |
| 1694 | // Prepare high bits for multiplication. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1695 | NewLIR2(kX86PsrlwRI, rs_src1_high_tmp.GetReg(), 0x8); |
| 1696 | AndMaskVectorRegister(rs_dest_high_tmp, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00, 0xFF00FF00); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1697 | |
| 1698 | // Multiply high bits and xmm2 now has high bits. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1699 | NewLIR2(kX86PmullwRR, rs_src1_high_tmp.GetReg(), rs_dest_high_tmp.GetReg()); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1700 | |
| 1701 | // Combine back into dest XMM register. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1702 | NewLIR2(kX86PorRR, rs_dest_src1.GetReg(), rs_src1_high_tmp.GetReg()); |
| 1703 | } |
| 1704 | |
| 1705 | void X86Mir2Lir::GenMultiplyVectorLong(RegStorage rs_dest_src1, RegStorage rs_src2) { |
| 1706 | /* |
| 1707 | * We need to emulate the packed long multiply. |
| 1708 | * For kMirOpPackedMultiply xmm1, xmm0: |
| 1709 | * - xmm1 is src/dest |
| 1710 | * - xmm0 is src |
| 1711 | * - Get xmm2 and xmm3 as temp |
| 1712 | * - Idea is to multiply the lower 32 of each operand with the higher 32 of the other. |
| 1713 | * - Then add the two results. |
| 1714 | * - Move it to the upper 32 of the destination |
| 1715 | * - Then multiply the lower 32-bits of the operands and add the result to the destination. |
| 1716 | * |
| 1717 | * (op dest src ) |
| 1718 | * movdqa %xmm2, %xmm1 |
| 1719 | * movdqa %xmm3, %xmm0 |
| 1720 | * psrlq %xmm3, $0x20 |
| 1721 | * pmuludq %xmm3, %xmm2 |
| 1722 | * psrlq %xmm1, $0x20 |
| 1723 | * pmuludq %xmm1, %xmm0 |
| 1724 | * paddq %xmm1, %xmm3 |
| 1725 | * psllq %xmm1, $0x20 |
| 1726 | * pmuludq %xmm2, %xmm0 |
| 1727 | * paddq %xmm1, %xmm2 |
| 1728 | * |
| 1729 | * When both the operands are the same, then we need to calculate the lower-32 * higher-32 |
| 1730 | * calculation only once. Thus we don't need the xmm3 temp above. That sequence becomes: |
| 1731 | * |
| 1732 | * (op dest src ) |
| 1733 | * movdqa %xmm2, %xmm1 |
| 1734 | * psrlq %xmm1, $0x20 |
| 1735 | * pmuludq %xmm1, %xmm0 |
| 1736 | * paddq %xmm1, %xmm1 |
| 1737 | * psllq %xmm1, $0x20 |
| 1738 | * pmuludq %xmm2, %xmm0 |
| 1739 | * paddq %xmm1, %xmm2 |
| 1740 | * |
| 1741 | */ |
| 1742 | |
| 1743 | bool both_operands_same = (rs_dest_src1.GetReg() == rs_src2.GetReg()); |
| 1744 | |
| 1745 | RegStorage rs_tmp_vector_1; |
| 1746 | RegStorage rs_tmp_vector_2; |
| 1747 | rs_tmp_vector_1 = Get128BitRegister(AllocTempDouble()); |
| 1748 | NewLIR2(kX86MovdqaRR, rs_tmp_vector_1.GetReg(), rs_dest_src1.GetReg()); |
| 1749 | |
| 1750 | if (both_operands_same == false) { |
| 1751 | rs_tmp_vector_2 = Get128BitRegister(AllocTempDouble()); |
| 1752 | NewLIR2(kX86MovdqaRR, rs_tmp_vector_2.GetReg(), rs_src2.GetReg()); |
| 1753 | NewLIR2(kX86PsrlqRI, rs_tmp_vector_2.GetReg(), 0x20); |
| 1754 | NewLIR2(kX86PmuludqRR, rs_tmp_vector_2.GetReg(), rs_tmp_vector_1.GetReg()); |
| 1755 | } |
| 1756 | |
| 1757 | NewLIR2(kX86PsrlqRI, rs_dest_src1.GetReg(), 0x20); |
| 1758 | NewLIR2(kX86PmuludqRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 1759 | |
| 1760 | if (both_operands_same == false) { |
| 1761 | NewLIR2(kX86PaddqRR, rs_dest_src1.GetReg(), rs_tmp_vector_2.GetReg()); |
| 1762 | } else { |
| 1763 | NewLIR2(kX86PaddqRR, rs_dest_src1.GetReg(), rs_dest_src1.GetReg()); |
| 1764 | } |
| 1765 | |
| 1766 | NewLIR2(kX86PsllqRI, rs_dest_src1.GetReg(), 0x20); |
| 1767 | NewLIR2(kX86PmuludqRR, rs_tmp_vector_1.GetReg(), rs_src2.GetReg()); |
| 1768 | NewLIR2(kX86PaddqRR, rs_dest_src1.GetReg(), rs_tmp_vector_1.GetReg()); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1769 | } |
| 1770 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1771 | void X86Mir2Lir::GenMultiplyVector(BasicBlock *bb, MIR *mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1772 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1773 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 1774 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1775 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1776 | RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1777 | int opcode = 0; |
| 1778 | switch (opsize) { |
| 1779 | case k32: |
| 1780 | opcode = kX86PmulldRR; |
| 1781 | break; |
| 1782 | case kSignedHalf: |
| 1783 | opcode = kX86PmullwRR; |
| 1784 | break; |
| 1785 | case kSingle: |
| 1786 | opcode = kX86MulpsRR; |
| 1787 | break; |
| 1788 | case kDouble: |
| 1789 | opcode = kX86MulpdRR; |
| 1790 | break; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1791 | case kSignedByte: |
| 1792 | // HW doesn't support 16x16 byte multiplication so emulate it. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1793 | GenMultiplyVectorSignedByte(rs_dest_src1, rs_src2); |
| 1794 | return; |
| 1795 | case k64: |
| 1796 | GenMultiplyVectorLong(rs_dest_src1, rs_src2); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1797 | return; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1798 | default: |
| 1799 | LOG(FATAL) << "Unsupported vector multiply " << opsize; |
| 1800 | break; |
| 1801 | } |
| 1802 | NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 1803 | } |
| 1804 | |
| 1805 | void X86Mir2Lir::GenAddVector(BasicBlock *bb, MIR *mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1806 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1807 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 1808 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1809 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1810 | RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1811 | int opcode = 0; |
| 1812 | switch (opsize) { |
| 1813 | case k32: |
| 1814 | opcode = kX86PadddRR; |
| 1815 | break; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1816 | case k64: |
| 1817 | opcode = kX86PaddqRR; |
| 1818 | break; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1819 | case kSignedHalf: |
| 1820 | case kUnsignedHalf: |
| 1821 | opcode = kX86PaddwRR; |
| 1822 | break; |
| 1823 | case kUnsignedByte: |
| 1824 | case kSignedByte: |
| 1825 | opcode = kX86PaddbRR; |
| 1826 | break; |
| 1827 | case kSingle: |
| 1828 | opcode = kX86AddpsRR; |
| 1829 | break; |
| 1830 | case kDouble: |
| 1831 | opcode = kX86AddpdRR; |
| 1832 | break; |
| 1833 | default: |
| 1834 | LOG(FATAL) << "Unsupported vector addition " << opsize; |
| 1835 | break; |
| 1836 | } |
| 1837 | NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 1838 | } |
| 1839 | |
| 1840 | void X86Mir2Lir::GenSubtractVector(BasicBlock *bb, MIR *mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1841 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1842 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 1843 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1844 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1845 | RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1846 | int opcode = 0; |
| 1847 | switch (opsize) { |
| 1848 | case k32: |
| 1849 | opcode = kX86PsubdRR; |
| 1850 | break; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1851 | case k64: |
| 1852 | opcode = kX86PsubqRR; |
| 1853 | break; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1854 | case kSignedHalf: |
| 1855 | case kUnsignedHalf: |
| 1856 | opcode = kX86PsubwRR; |
| 1857 | break; |
| 1858 | case kUnsignedByte: |
| 1859 | case kSignedByte: |
| 1860 | opcode = kX86PsubbRR; |
| 1861 | break; |
| 1862 | case kSingle: |
| 1863 | opcode = kX86SubpsRR; |
| 1864 | break; |
| 1865 | case kDouble: |
| 1866 | opcode = kX86SubpdRR; |
| 1867 | break; |
| 1868 | default: |
| 1869 | LOG(FATAL) << "Unsupported vector subtraction " << opsize; |
| 1870 | break; |
| 1871 | } |
| 1872 | NewLIR2(opcode, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 1873 | } |
| 1874 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1875 | void X86Mir2Lir::GenShiftByteVector(BasicBlock *bb, MIR *mir) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1876 | // Destination does not need clobbered because it has already been as part |
| 1877 | // of the general packed shift handler (caller of this method). |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1878 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1879 | |
| 1880 | int opcode = 0; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1881 | switch (static_cast<ExtendedMIROpcode>(mir->dalvikInsn.opcode)) { |
| 1882 | case kMirOpPackedShiftLeft: |
| 1883 | opcode = kX86PsllwRI; |
| 1884 | break; |
| 1885 | case kMirOpPackedSignedShiftRight: |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1886 | case kMirOpPackedUnsignedShiftRight: |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1887 | // TODO Add support for emulated byte shifts. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1888 | default: |
| 1889 | LOG(FATAL) << "Unsupported shift operation on byte vector " << opcode; |
| 1890 | break; |
| 1891 | } |
| 1892 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1893 | // Clear xmm register and return if shift more than byte length. |
| 1894 | int imm = mir->dalvikInsn.vB; |
| 1895 | if (imm >= 8) { |
| 1896 | NewLIR2(kX86PxorRR, rs_dest_src1.GetReg(), rs_dest_src1.GetReg()); |
| 1897 | return; |
| 1898 | } |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1899 | |
| 1900 | // Shift lower values. |
| 1901 | NewLIR2(opcode, rs_dest_src1.GetReg(), imm); |
| 1902 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1903 | /* |
| 1904 | * The above shift will shift the whole word, but that means |
| 1905 | * both the bytes will shift as well. To emulate a byte level |
| 1906 | * shift, we can just throw away the lower (8 - N) bits of the |
| 1907 | * upper byte, and we are done. |
| 1908 | */ |
| 1909 | uint8_t byte_mask = 0xFF << imm; |
| 1910 | uint32_t int_mask = byte_mask; |
| 1911 | int_mask = int_mask << 8 | byte_mask; |
| 1912 | int_mask = int_mask << 8 | byte_mask; |
| 1913 | int_mask = int_mask << 8 | byte_mask; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1914 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1915 | // And the destination with the mask |
| 1916 | AndMaskVectorRegister(rs_dest_src1, int_mask, int_mask, int_mask, int_mask); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1917 | } |
| 1918 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1919 | void X86Mir2Lir::GenShiftLeftVector(BasicBlock *bb, MIR *mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1920 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1921 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 1922 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1923 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1924 | int imm = mir->dalvikInsn.vB; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1925 | int opcode = 0; |
| 1926 | switch (opsize) { |
| 1927 | case k32: |
| 1928 | opcode = kX86PslldRI; |
| 1929 | break; |
| 1930 | case k64: |
| 1931 | opcode = kX86PsllqRI; |
| 1932 | break; |
| 1933 | case kSignedHalf: |
| 1934 | case kUnsignedHalf: |
| 1935 | opcode = kX86PsllwRI; |
| 1936 | break; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1937 | case kSignedByte: |
| 1938 | case kUnsignedByte: |
| 1939 | GenShiftByteVector(bb, mir); |
| 1940 | return; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1941 | default: |
| 1942 | LOG(FATAL) << "Unsupported vector shift left " << opsize; |
| 1943 | break; |
| 1944 | } |
| 1945 | NewLIR2(opcode, rs_dest_src1.GetReg(), imm); |
| 1946 | } |
| 1947 | |
| 1948 | void X86Mir2Lir::GenSignedShiftRightVector(BasicBlock *bb, MIR *mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1949 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1950 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 1951 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1952 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1953 | int imm = mir->dalvikInsn.vB; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1954 | int opcode = 0; |
| 1955 | switch (opsize) { |
| 1956 | case k32: |
| 1957 | opcode = kX86PsradRI; |
| 1958 | break; |
| 1959 | case kSignedHalf: |
| 1960 | case kUnsignedHalf: |
| 1961 | opcode = kX86PsrawRI; |
| 1962 | break; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1963 | case kSignedByte: |
| 1964 | case kUnsignedByte: |
| 1965 | GenShiftByteVector(bb, mir); |
| 1966 | return; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1967 | case k64: |
| 1968 | // TODO Implement emulated shift algorithm. |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1969 | default: |
| 1970 | LOG(FATAL) << "Unsupported vector signed shift right " << opsize; |
| 1971 | break; |
| 1972 | } |
| 1973 | NewLIR2(opcode, rs_dest_src1.GetReg(), imm); |
| 1974 | } |
| 1975 | |
| 1976 | void X86Mir2Lir::GenUnsignedShiftRightVector(BasicBlock *bb, MIR *mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1977 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 1978 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 1979 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 1980 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1981 | int imm = mir->dalvikInsn.vB; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1982 | int opcode = 0; |
| 1983 | switch (opsize) { |
| 1984 | case k32: |
| 1985 | opcode = kX86PsrldRI; |
| 1986 | break; |
| 1987 | case k64: |
| 1988 | opcode = kX86PsrlqRI; |
| 1989 | break; |
| 1990 | case kSignedHalf: |
| 1991 | case kUnsignedHalf: |
| 1992 | opcode = kX86PsrlwRI; |
| 1993 | break; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 1994 | case kSignedByte: |
| 1995 | case kUnsignedByte: |
| 1996 | GenShiftByteVector(bb, mir); |
| 1997 | return; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 1998 | default: |
| 1999 | LOG(FATAL) << "Unsupported vector unsigned shift right " << opsize; |
| 2000 | break; |
| 2001 | } |
| 2002 | NewLIR2(opcode, rs_dest_src1.GetReg(), imm); |
| 2003 | } |
| 2004 | |
| 2005 | void X86Mir2Lir::GenAndVector(BasicBlock *bb, MIR *mir) { |
| 2006 | // We only support 128 bit registers. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2007 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 2008 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2009 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2010 | RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2011 | NewLIR2(kX86PandRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 2012 | } |
| 2013 | |
| 2014 | void X86Mir2Lir::GenOrVector(BasicBlock *bb, MIR *mir) { |
| 2015 | // We only support 128 bit registers. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2016 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 2017 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2018 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2019 | RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2020 | NewLIR2(kX86PorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 2021 | } |
| 2022 | |
| 2023 | void X86Mir2Lir::GenXorVector(BasicBlock *bb, MIR *mir) { |
| 2024 | // We only support 128 bit registers. |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2025 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 2026 | RegStorage rs_dest_src1 = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2027 | Clobber(rs_dest_src1); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2028 | RegStorage rs_src2 = RegStorage::Solo128(mir->dalvikInsn.vB); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2029 | NewLIR2(kX86PxorRR, rs_dest_src1.GetReg(), rs_src2.GetReg()); |
| 2030 | } |
| 2031 | |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2032 | void X86Mir2Lir::AndMaskVectorRegister(RegStorage rs_src1, uint32_t m1, uint32_t m2, uint32_t m3, uint32_t m4) { |
| 2033 | MaskVectorRegister(kX86PandRM, rs_src1, m1, m2, m3, m4); |
| 2034 | } |
| 2035 | |
| 2036 | void X86Mir2Lir::MaskVectorRegister(X86OpCode opcode, RegStorage rs_src1, uint32_t m0, uint32_t m1, uint32_t m2, uint32_t m3) { |
| 2037 | // Create temporary MIR as container for 128-bit binary mask. |
| 2038 | MIR const_mir; |
| 2039 | MIR* const_mirp = &const_mir; |
| 2040 | const_mirp->dalvikInsn.opcode = static_cast<Instruction::Code>(kMirOpConstVector); |
| 2041 | const_mirp->dalvikInsn.arg[0] = m0; |
| 2042 | const_mirp->dalvikInsn.arg[1] = m1; |
| 2043 | const_mirp->dalvikInsn.arg[2] = m2; |
| 2044 | const_mirp->dalvikInsn.arg[3] = m3; |
| 2045 | |
| 2046 | // Mask vector with const from literal pool. |
| 2047 | AppendOpcodeWithConst(opcode, rs_src1.GetReg(), const_mirp); |
| 2048 | } |
| 2049 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2050 | void X86Mir2Lir::GenAddReduceVector(BasicBlock *bb, MIR *mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2051 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2052 | RegStorage vector_src = RegStorage::Solo128(mir->dalvikInsn.vB); |
| 2053 | bool is_wide = opsize == k64 || opsize == kDouble; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2054 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2055 | // Get the location of the virtual register. Since this bytecode is overloaded |
| 2056 | // for different types (and sizes), we need different logic for each path. |
| 2057 | // The design of bytecode uses same VR for source and destination. |
| 2058 | RegLocation rl_src, rl_dest, rl_result; |
| 2059 | if (is_wide) { |
| 2060 | rl_src = mir_graph_->GetSrcWide(mir, 0); |
| 2061 | rl_dest = mir_graph_->GetDestWide(mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2062 | } else { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2063 | rl_src = mir_graph_->GetSrc(mir, 0); |
| 2064 | rl_dest = mir_graph_->GetDest(mir); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2065 | } |
| 2066 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2067 | // We need a temp for byte and short values |
| 2068 | RegStorage temp; |
| 2069 | |
| 2070 | // There is a different path depending on type and size. |
| 2071 | if (opsize == kSingle) { |
| 2072 | // Handle float case. |
| 2073 | // TODO Add support for fast math (not value safe) and do horizontal add in that case. |
| 2074 | |
| 2075 | rl_src = LoadValue(rl_src, kFPReg); |
| 2076 | rl_result = EvalLoc(rl_dest, kFPReg, true); |
| 2077 | |
| 2078 | // Since we are doing an add-reduce, we move the reg holding the VR |
| 2079 | // into the result so we include it in result. |
| 2080 | OpRegCopy(rl_result.reg, rl_src.reg); |
| 2081 | NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), vector_src.GetReg()); |
| 2082 | |
| 2083 | // Since FP must keep order of operation for value safety, we shift to low |
| 2084 | // 32-bits and add to result. |
| 2085 | for (int i = 0; i < 3; i++) { |
| 2086 | NewLIR3(kX86ShufpsRRI, vector_src.GetReg(), vector_src.GetReg(), 0x39); |
| 2087 | NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), vector_src.GetReg()); |
| 2088 | } |
| 2089 | |
| 2090 | StoreValue(rl_dest, rl_result); |
| 2091 | } else if (opsize == kDouble) { |
| 2092 | // Handle double case. |
| 2093 | rl_src = LoadValueWide(rl_src, kFPReg); |
| 2094 | rl_result = EvalLocWide(rl_dest, kFPReg, true); |
| 2095 | LOG(FATAL) << "Unsupported vector add reduce for double."; |
| 2096 | } else if (opsize == k64) { |
| 2097 | /* |
| 2098 | * Handle long case: |
| 2099 | * 1) Reduce the vector register to lower half (with addition). |
| 2100 | * 1-1) Get an xmm temp and fill it with vector register. |
| 2101 | * 1-2) Shift the xmm temp by 8-bytes. |
| 2102 | * 1-3) Add the xmm temp to vector register that is being reduced. |
| 2103 | * 2) Allocate temp GP / GP pair. |
| 2104 | * 2-1) In 64-bit case, use movq to move result to a 64-bit GP. |
| 2105 | * 2-2) In 32-bit case, use movd twice to move to 32-bit GP pair. |
| 2106 | * 3) Finish the add reduction by doing what add-long/2addr does, |
| 2107 | * but instead of having a VR as one of the sources, we have our temp GP. |
| 2108 | */ |
| 2109 | RegStorage rs_tmp_vector = Get128BitRegister(AllocTempDouble()); |
| 2110 | NewLIR2(kX86MovdqaRR, rs_tmp_vector.GetReg(), vector_src.GetReg()); |
| 2111 | NewLIR2(kX86PsrldqRI, rs_tmp_vector.GetReg(), 8); |
| 2112 | NewLIR2(kX86PaddqRR, vector_src.GetReg(), rs_tmp_vector.GetReg()); |
| 2113 | FreeTemp(rs_tmp_vector); |
| 2114 | |
| 2115 | // We would like to be able to reuse the add-long implementation, so set up a fake |
| 2116 | // register location to pass it. |
| 2117 | RegLocation temp_loc = mir_graph_->GetBadLoc(); |
| 2118 | temp_loc.core = 1; |
| 2119 | temp_loc.wide = 1; |
| 2120 | temp_loc.location = kLocPhysReg; |
| 2121 | temp_loc.reg = AllocTempWide(); |
| 2122 | |
| 2123 | if (cu_->target64) { |
| 2124 | DCHECK(!temp_loc.reg.IsPair()); |
| 2125 | NewLIR2(kX86MovqrxRR, temp_loc.reg.GetReg(), vector_src.GetReg()); |
| 2126 | } else { |
| 2127 | NewLIR2(kX86MovdrxRR, temp_loc.reg.GetLowReg(), vector_src.GetReg()); |
| 2128 | NewLIR2(kX86PsrlqRI, vector_src.GetReg(), 0x20); |
| 2129 | NewLIR2(kX86MovdrxRR, temp_loc.reg.GetHighReg(), vector_src.GetReg()); |
| 2130 | } |
| 2131 | |
| 2132 | GenArithOpLong(Instruction::ADD_LONG_2ADDR, rl_dest, temp_loc, temp_loc); |
| 2133 | } else if (opsize == kSignedByte || opsize == kUnsignedByte) { |
| 2134 | RegStorage rs_tmp = Get128BitRegister(AllocTempDouble()); |
| 2135 | NewLIR2(kX86PxorRR, rs_tmp.GetReg(), rs_tmp.GetReg()); |
| 2136 | NewLIR2(kX86PsadbwRR, vector_src.GetReg(), rs_tmp.GetReg()); |
| 2137 | NewLIR3(kX86PshufdRRI, rs_tmp.GetReg(), vector_src.GetReg(), 0x4e); |
| 2138 | NewLIR2(kX86PaddbRR, vector_src.GetReg(), rs_tmp.GetReg()); |
| 2139 | // Move to a GPR |
| 2140 | temp = AllocTemp(); |
| 2141 | NewLIR2(kX86MovdrxRR, temp.GetReg(), vector_src.GetReg()); |
| 2142 | } else { |
| 2143 | // Handle and the int and short cases together |
| 2144 | |
| 2145 | // Initialize as if we were handling int case. Below we update |
| 2146 | // the opcode if handling byte or short. |
| 2147 | int vec_bytes = (mir->dalvikInsn.vC & 0xFFFF) / 8; |
| 2148 | int vec_unit_size; |
| 2149 | int horizontal_add_opcode; |
| 2150 | int extract_opcode; |
| 2151 | |
| 2152 | if (opsize == kSignedHalf || opsize == kUnsignedHalf) { |
| 2153 | extract_opcode = kX86PextrwRRI; |
| 2154 | horizontal_add_opcode = kX86PhaddwRR; |
| 2155 | vec_unit_size = 2; |
| 2156 | } else if (opsize == k32) { |
| 2157 | vec_unit_size = 4; |
| 2158 | horizontal_add_opcode = kX86PhadddRR; |
| 2159 | extract_opcode = kX86PextrdRRI; |
| 2160 | } else { |
| 2161 | LOG(FATAL) << "Unsupported vector add reduce " << opsize; |
| 2162 | return; |
| 2163 | } |
| 2164 | |
| 2165 | int elems = vec_bytes / vec_unit_size; |
| 2166 | |
| 2167 | while (elems > 1) { |
| 2168 | NewLIR2(horizontal_add_opcode, vector_src.GetReg(), vector_src.GetReg()); |
| 2169 | elems >>= 1; |
| 2170 | } |
| 2171 | |
| 2172 | // Handle this as arithmetic unary case. |
| 2173 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 2174 | |
| 2175 | // Extract to a GP register because this is integral typed. |
| 2176 | temp = AllocTemp(); |
| 2177 | NewLIR3(extract_opcode, temp.GetReg(), vector_src.GetReg(), 0); |
| 2178 | } |
| 2179 | |
| 2180 | if (opsize != k64 && opsize != kSingle && opsize != kDouble) { |
| 2181 | // The logic below looks very similar to the handling of ADD_INT_2ADDR |
| 2182 | // except the rhs is not a VR but a physical register allocated above. |
| 2183 | // No load of source VR is done because it assumes that rl_result will |
| 2184 | // share physical register / memory location. |
| 2185 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
| 2186 | if (rl_result.location == kLocPhysReg) { |
| 2187 | // Ensure res is in a core reg. |
| 2188 | rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 2189 | OpRegReg(kOpAdd, rl_result.reg, temp); |
| 2190 | StoreFinalValue(rl_dest, rl_result); |
| 2191 | } else { |
| 2192 | // Do the addition directly to memory. |
| 2193 | OpMemReg(kOpAdd, rl_result, temp.GetReg()); |
| 2194 | } |
| 2195 | } |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2196 | } |
| 2197 | |
| 2198 | void X86Mir2Lir::GenReduceVector(BasicBlock *bb, MIR *mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2199 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 2200 | RegLocation rl_dest = mir_graph_->GetDest(mir); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2201 | RegStorage vector_src = RegStorage::Solo128(mir->dalvikInsn.vB); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2202 | int extract_index = mir->dalvikInsn.arg[0]; |
| 2203 | int extr_opcode = 0; |
| 2204 | RegLocation rl_result; |
| 2205 | bool is_wide = false; |
| 2206 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2207 | // There is a different path depending on type and size. |
| 2208 | if (opsize == kSingle) { |
| 2209 | // Handle float case. |
| 2210 | // TODO Add support for fast math (not value safe) and do horizontal add in that case. |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2211 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2212 | rl_result = EvalLoc(rl_dest, kFPReg, true); |
| 2213 | NewLIR2(kX86PxorRR, rl_result.reg.GetReg(), rl_result.reg.GetReg()); |
| 2214 | NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), vector_src.GetReg()); |
| 2215 | |
| 2216 | // Since FP must keep order of operation for value safety, we shift to low |
| 2217 | // 32-bits and add to result. |
| 2218 | for (int i = 0; i < 3; i++) { |
| 2219 | NewLIR3(kX86ShufpsRRI, vector_src.GetReg(), vector_src.GetReg(), 0x39); |
| 2220 | NewLIR2(kX86AddssRR, rl_result.reg.GetReg(), vector_src.GetReg()); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2221 | } |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2222 | |
| 2223 | StoreValue(rl_dest, rl_result); |
| 2224 | } else if (opsize == kDouble) { |
| 2225 | // TODO Handle double case. |
| 2226 | LOG(FATAL) << "Unsupported add reduce for double."; |
| 2227 | } else if (opsize == k64) { |
| 2228 | /* |
| 2229 | * Handle long case: |
| 2230 | * 1) Reduce the vector register to lower half (with addition). |
| 2231 | * 1-1) Get an xmm temp and fill it with vector register. |
| 2232 | * 1-2) Shift the xmm temp by 8-bytes. |
| 2233 | * 1-3) Add the xmm temp to vector register that is being reduced. |
| 2234 | * 2) Evaluate destination to a GP / GP pair. |
| 2235 | * 2-1) In 64-bit case, use movq to move result to a 64-bit GP. |
| 2236 | * 2-2) In 32-bit case, use movd twice to move to 32-bit GP pair. |
| 2237 | * 3) Store the result to the final destination. |
| 2238 | */ |
| 2239 | RegStorage rs_tmp_vector = Get128BitRegister(AllocTempDouble()); |
| 2240 | NewLIR2(kX86MovdqaRR, rs_tmp_vector.GetReg(), vector_src.GetReg()); |
| 2241 | NewLIR2(kX86PsrldqRI, rs_tmp_vector.GetReg(), 8); |
| 2242 | NewLIR2(kX86PaddqRR, vector_src.GetReg(), rs_tmp_vector.GetReg()); |
| 2243 | FreeTemp(rs_tmp_vector); |
| 2244 | |
| 2245 | rl_result = EvalLocWide(rl_dest, kCoreReg, true); |
| 2246 | if (cu_->target64) { |
| 2247 | DCHECK(!rl_result.reg.IsPair()); |
| 2248 | NewLIR2(kX86MovqrxRR, rl_result.reg.GetReg(), vector_src.GetReg()); |
| 2249 | } else { |
| 2250 | NewLIR2(kX86MovdrxRR, rl_result.reg.GetLowReg(), vector_src.GetReg()); |
| 2251 | NewLIR2(kX86PsrlqRI, vector_src.GetReg(), 0x20); |
| 2252 | NewLIR2(kX86MovdrxRR, rl_result.reg.GetHighReg(), vector_src.GetReg()); |
| 2253 | } |
| 2254 | |
| 2255 | StoreValueWide(rl_dest, rl_result); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2256 | } else { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2257 | // Handle the rest of integral types now. |
| 2258 | switch (opsize) { |
| 2259 | case k32: |
| 2260 | rl_result = UpdateLocTyped(rl_dest, kCoreReg); |
| 2261 | extr_opcode = (rl_result.location == kLocPhysReg) ? kX86PextrdMRI : kX86PextrdRRI; |
| 2262 | break; |
| 2263 | case kSignedHalf: |
| 2264 | case kUnsignedHalf: |
| 2265 | rl_result= UpdateLocTyped(rl_dest, kCoreReg); |
| 2266 | extr_opcode = (rl_result.location == kLocPhysReg) ? kX86PextrwMRI : kX86PextrwRRI; |
| 2267 | break; |
| 2268 | default: |
| 2269 | LOG(FATAL) << "Unsupported vector reduce " << opsize; |
| 2270 | return; |
| 2271 | } |
| 2272 | |
| 2273 | if (rl_result.location == kLocPhysReg) { |
| 2274 | NewLIR3(extr_opcode, rl_result.reg.GetReg(), vector_src.GetReg(), extract_index); |
| 2275 | if (is_wide == true) { |
| 2276 | StoreFinalValue(rl_dest, rl_result); |
| 2277 | } else { |
| 2278 | StoreFinalValueWide(rl_dest, rl_result); |
| 2279 | } |
| 2280 | } else { |
| 2281 | int displacement = SRegOffset(rl_result.s_reg_low); |
| 2282 | LIR *l = NewLIR3(extr_opcode, rs_rX86_SP.GetReg(), displacement, vector_src.GetReg()); |
| 2283 | AnnotateDalvikRegAccess(l, displacement >> 2, true /* is_load */, is_wide /* is_64bit */); |
| 2284 | AnnotateDalvikRegAccess(l, displacement >> 2, false /* is_load */, is_wide /* is_64bit */); |
| 2285 | } |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2286 | } |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2287 | } |
| 2288 | |
| 2289 | void X86Mir2Lir::GenSetVector(BasicBlock *bb, MIR *mir) { |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2290 | DCHECK_EQ(mir->dalvikInsn.vC & 0xFFFF, 128U); |
| 2291 | OpSize opsize = static_cast<OpSize>(mir->dalvikInsn.vC >> 16); |
| 2292 | RegStorage rs_dest = RegStorage::Solo128(mir->dalvikInsn.vA); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2293 | Clobber(rs_dest); |
| 2294 | int op_shuffle = 0, op_shuffle_high = 0, op_mov = kX86MovdxrRR; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2295 | RegisterClass reg_type = kCoreReg; |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2296 | bool is_wide = false; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2297 | |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2298 | switch (opsize) { |
| 2299 | case k32: |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2300 | op_shuffle = kX86PshufdRRI; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2301 | break; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2302 | case kSingle: |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2303 | op_shuffle = kX86PshufdRRI; |
| 2304 | op_mov = kX86MovdqaRR; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2305 | reg_type = kFPReg; |
| 2306 | break; |
| 2307 | case k64: |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2308 | op_shuffle = kX86PunpcklqdqRR; |
| 2309 | op_mov = kX86MovqrxRR; |
| 2310 | is_wide = true; |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2311 | break; |
| 2312 | case kSignedByte: |
| 2313 | case kUnsignedByte: |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2314 | // We will have the source loaded up in a |
| 2315 | // double-word before we use this shuffle |
| 2316 | op_shuffle = kX86PshufdRRI; |
| 2317 | break; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2318 | case kSignedHalf: |
| 2319 | case kUnsignedHalf: |
| 2320 | // Handles low quadword. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2321 | op_shuffle = kX86PshuflwRRI; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2322 | // Handles upper quadword. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2323 | op_shuffle_high = kX86PshufdRRI; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2324 | break; |
| 2325 | default: |
| 2326 | LOG(FATAL) << "Unsupported vector set " << opsize; |
| 2327 | break; |
| 2328 | } |
| 2329 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2330 | // Load the value from the VR into a physical register. |
| 2331 | RegLocation rl_src; |
| 2332 | if (!is_wide) { |
| 2333 | rl_src = mir_graph_->GetSrc(mir, 0); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2334 | rl_src = LoadValue(rl_src, reg_type); |
| 2335 | } else { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2336 | rl_src = mir_graph_->GetSrcWide(mir, 0); |
Udayan Banerji | 60bfe7b | 2014-07-08 19:59:43 -0700 | [diff] [blame] | 2337 | rl_src = LoadValueWide(rl_src, reg_type); |
| 2338 | } |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2339 | RegStorage reg_to_shuffle = rl_src.reg; |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2340 | |
| 2341 | // Load the value into the XMM register. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2342 | if (!cu_->target64 && opsize == k64) { |
| 2343 | // Logic assumes that longs are loaded in GP register pairs. |
| 2344 | NewLIR2(kX86MovdxrRR, rs_dest.GetReg(), reg_to_shuffle.GetLowReg()); |
| 2345 | RegStorage r_tmp = AllocTempDouble(); |
| 2346 | NewLIR2(kX86MovdxrRR, r_tmp.GetReg(), reg_to_shuffle.GetHighReg()); |
| 2347 | NewLIR2(kX86PunpckldqRR, rs_dest.GetReg(), r_tmp.GetReg()); |
| 2348 | FreeTemp(r_tmp); |
| 2349 | } else { |
| 2350 | NewLIR2(op_mov, rs_dest.GetReg(), reg_to_shuffle.GetReg()); |
| 2351 | } |
| 2352 | |
| 2353 | if (opsize == kSignedByte || opsize == kUnsignedByte) { |
| 2354 | // In the byte case, first duplicate it to be a word |
| 2355 | // Then duplicate it to be a double-word |
| 2356 | NewLIR2(kX86PunpcklbwRR, rs_dest.GetReg(), rs_dest.GetReg()); |
| 2357 | NewLIR2(kX86PunpcklwdRR, rs_dest.GetReg(), rs_dest.GetReg()); |
| 2358 | } |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2359 | |
| 2360 | // Now shuffle the value across the destination. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2361 | if (op_shuffle == kX86PunpcklqdqRR) { |
| 2362 | NewLIR2(op_shuffle, rs_dest.GetReg(), rs_dest.GetReg()); |
| 2363 | } else { |
| 2364 | NewLIR3(op_shuffle, rs_dest.GetReg(), rs_dest.GetReg(), 0); |
| 2365 | } |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2366 | |
| 2367 | // And then repeat as needed. |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2368 | if (op_shuffle_high != 0) { |
| 2369 | NewLIR3(op_shuffle_high, rs_dest.GetReg(), rs_dest.GetReg(), 0); |
Mark Mendell | fe94578 | 2014-05-22 09:52:36 -0400 | [diff] [blame] | 2370 | } |
| 2371 | } |
| 2372 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2373 | void X86Mir2Lir::GenPackedArrayGet(BasicBlock *bb, MIR *mir) { |
| 2374 | UNIMPLEMENTED(FATAL) << "Extended opcode kMirOpPackedArrayGet not supported."; |
| 2375 | } |
| 2376 | |
| 2377 | void X86Mir2Lir::GenPackedArrayPut(BasicBlock *bb, MIR *mir) { |
| 2378 | UNIMPLEMENTED(FATAL) << "Extended opcode kMirOpPackedArrayPut not supported."; |
| 2379 | } |
| 2380 | |
| 2381 | LIR* X86Mir2Lir::ScanVectorLiteral(int32_t* constants) { |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 2382 | for (LIR *p = const_vectors_; p != nullptr; p = p->next) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2383 | if (constants[0] == p->operands[0] && constants[1] == p->operands[1] && |
| 2384 | constants[2] == p->operands[2] && constants[3] == p->operands[3]) { |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 2385 | return p; |
| 2386 | } |
| 2387 | } |
| 2388 | return nullptr; |
| 2389 | } |
| 2390 | |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2391 | LIR* X86Mir2Lir::AddVectorLiteral(int32_t* constants) { |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 2392 | LIR* new_value = static_cast<LIR*>(arena_->Alloc(sizeof(LIR), kArenaAllocData)); |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2393 | new_value->operands[0] = constants[0]; |
| 2394 | new_value->operands[1] = constants[1]; |
| 2395 | new_value->operands[2] = constants[2]; |
| 2396 | new_value->operands[3] = constants[3]; |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 2397 | new_value->next = const_vectors_; |
| 2398 | if (const_vectors_ == nullptr) { |
Lupusoru, Razvan A | b3a84e2 | 2014-07-28 14:11:01 -0700 | [diff] [blame] | 2399 | estimated_native_code_size_ += 12; // Maximum needed to align to 16 byte boundary. |
Mark Mendell | d65c51a | 2014-04-29 16:55:20 -0400 | [diff] [blame] | 2400 | } |
| 2401 | estimated_native_code_size_ += 16; // Space for one vector. |
| 2402 | const_vectors_ = new_value; |
| 2403 | return new_value; |
| 2404 | } |
| 2405 | |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2406 | // ------------ ABI support: mapping of args to physical registers ------------- |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2407 | RegStorage X86Mir2Lir::InToRegStorageX86_64Mapper::GetNextReg(bool is_double_or_float, bool is_wide, |
| 2408 | bool is_ref) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2409 | const SpecialTargetRegister coreArgMappingToPhysicalReg[] = {kArg1, kArg2, kArg3, kArg4, kArg5}; |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2410 | const int coreArgMappingToPhysicalRegSize = sizeof(coreArgMappingToPhysicalReg) / |
| 2411 | sizeof(SpecialTargetRegister); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2412 | const SpecialTargetRegister fpArgMappingToPhysicalReg[] = {kFArg0, kFArg1, kFArg2, kFArg3, |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2413 | kFArg4, kFArg5, kFArg6, kFArg7}; |
| 2414 | const int fpArgMappingToPhysicalRegSize = sizeof(fpArgMappingToPhysicalReg) / |
| 2415 | sizeof(SpecialTargetRegister); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2416 | |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2417 | if (is_double_or_float) { |
| 2418 | if (cur_fp_reg_ < fpArgMappingToPhysicalRegSize) { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2419 | return ml_->TargetReg(fpArgMappingToPhysicalReg[cur_fp_reg_++], is_wide ? kWide : kNotWide); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2420 | } |
| 2421 | } else { |
| 2422 | if (cur_core_reg_ < coreArgMappingToPhysicalRegSize) { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2423 | return ml_->TargetReg(coreArgMappingToPhysicalReg[cur_core_reg_++], |
| 2424 | is_ref ? kRef : (is_wide ? kWide : kNotWide)); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2425 | } |
| 2426 | } |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2427 | return RegStorage::InvalidReg(); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2428 | } |
| 2429 | |
| 2430 | RegStorage X86Mir2Lir::InToRegStorageMapping::Get(int in_position) { |
| 2431 | DCHECK(IsInitialized()); |
| 2432 | auto res = mapping_.find(in_position); |
| 2433 | return res != mapping_.end() ? res->second : RegStorage::InvalidReg(); |
| 2434 | } |
| 2435 | |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2436 | void X86Mir2Lir::InToRegStorageMapping::Initialize(RegLocation* arg_locs, int count, |
| 2437 | InToRegStorageMapper* mapper) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2438 | DCHECK(mapper != nullptr); |
| 2439 | max_mapped_in_ = -1; |
| 2440 | is_there_stack_mapped_ = false; |
| 2441 | for (int in_position = 0; in_position < count; in_position++) { |
Serguei Katkov | 407a9d2 | 2014-07-05 03:09:32 +0700 | [diff] [blame] | 2442 | RegStorage reg = mapper->GetNextReg(arg_locs[in_position].fp, |
| 2443 | arg_locs[in_position].wide, arg_locs[in_position].ref); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2444 | if (reg.Valid()) { |
| 2445 | mapping_[in_position] = reg; |
| 2446 | max_mapped_in_ = std::max(max_mapped_in_, in_position); |
Serguei Katkov | 407a9d2 | 2014-07-05 03:09:32 +0700 | [diff] [blame] | 2447 | if (arg_locs[in_position].wide) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2448 | // We covered 2 args, so skip the next one |
| 2449 | in_position++; |
| 2450 | } |
| 2451 | } else { |
| 2452 | is_there_stack_mapped_ = true; |
| 2453 | } |
| 2454 | } |
| 2455 | initialized_ = true; |
| 2456 | } |
| 2457 | |
| 2458 | RegStorage X86Mir2Lir::GetArgMappingToPhysicalReg(int arg_num) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2459 | if (!cu_->target64) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2460 | return GetCoreArgMappingToPhysicalReg(arg_num); |
| 2461 | } |
| 2462 | |
| 2463 | if (!in_to_reg_storage_mapping_.IsInitialized()) { |
Razvan A Lupusoru | 8d0d03e | 2014-06-06 17:04:52 -0700 | [diff] [blame] | 2464 | int start_vreg = cu_->mir_graph->GetFirstInVR(); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2465 | RegLocation* arg_locs = &mir_graph_->reg_location_[start_vreg]; |
| 2466 | |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2467 | InToRegStorageX86_64Mapper mapper(this); |
Razvan A Lupusoru | 8d0d03e | 2014-06-06 17:04:52 -0700 | [diff] [blame] | 2468 | in_to_reg_storage_mapping_.Initialize(arg_locs, mir_graph_->GetNumOfInVRs(), &mapper); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2469 | } |
| 2470 | return in_to_reg_storage_mapping_.Get(arg_num); |
| 2471 | } |
| 2472 | |
| 2473 | RegStorage X86Mir2Lir::GetCoreArgMappingToPhysicalReg(int core_arg_num) { |
| 2474 | // For the 32-bit internal ABI, the first 3 arguments are passed in registers. |
| 2475 | // Not used for 64-bit, TODO: Move X86_32 to the same framework |
| 2476 | switch (core_arg_num) { |
| 2477 | case 0: |
| 2478 | return rs_rX86_ARG1; |
| 2479 | case 1: |
| 2480 | return rs_rX86_ARG2; |
| 2481 | case 2: |
| 2482 | return rs_rX86_ARG3; |
| 2483 | default: |
| 2484 | return RegStorage::InvalidReg(); |
| 2485 | } |
| 2486 | } |
| 2487 | |
| 2488 | // ---------End of ABI support: mapping of args to physical registers ------------- |
| 2489 | |
| 2490 | /* |
| 2491 | * If there are any ins passed in registers that have not been promoted |
| 2492 | * to a callee-save register, flush them to the frame. Perform initial |
| 2493 | * assignment of promoted arguments. |
| 2494 | * |
| 2495 | * ArgLocs is an array of location records describing the incoming arguments |
| 2496 | * with one location record per word of argument. |
| 2497 | */ |
| 2498 | void X86Mir2Lir::FlushIns(RegLocation* ArgLocs, RegLocation rl_method) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2499 | if (!cu_->target64) return Mir2Lir::FlushIns(ArgLocs, rl_method); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2500 | /* |
| 2501 | * Dummy up a RegLocation for the incoming Method* |
| 2502 | * It will attempt to keep kArg0 live (or copy it to home location |
| 2503 | * if promoted). |
| 2504 | */ |
| 2505 | |
| 2506 | RegLocation rl_src = rl_method; |
| 2507 | rl_src.location = kLocPhysReg; |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2508 | rl_src.reg = TargetReg(kArg0, kRef); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2509 | rl_src.home = false; |
| 2510 | MarkLive(rl_src); |
| 2511 | StoreValue(rl_method, rl_src); |
| 2512 | // If Method* has been promoted, explicitly flush |
| 2513 | if (rl_method.location == kLocPhysReg) { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2514 | StoreRefDisp(rs_rX86_SP, 0, As32BitReg(TargetReg(kArg0, kRef)), kNotVolatile); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2515 | } |
| 2516 | |
Razvan A Lupusoru | 8d0d03e | 2014-06-06 17:04:52 -0700 | [diff] [blame] | 2517 | if (mir_graph_->GetNumOfInVRs() == 0) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2518 | return; |
| 2519 | } |
| 2520 | |
Razvan A Lupusoru | 8d0d03e | 2014-06-06 17:04:52 -0700 | [diff] [blame] | 2521 | int start_vreg = cu_->mir_graph->GetFirstInVR(); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2522 | /* |
| 2523 | * Copy incoming arguments to their proper home locations. |
| 2524 | * NOTE: an older version of dx had an issue in which |
| 2525 | * it would reuse static method argument registers. |
| 2526 | * This could result in the same Dalvik virtual register |
| 2527 | * being promoted to both core and fp regs. To account for this, |
| 2528 | * we only copy to the corresponding promoted physical register |
| 2529 | * if it matches the type of the SSA name for the incoming |
| 2530 | * argument. It is also possible that long and double arguments |
| 2531 | * end up half-promoted. In those cases, we must flush the promoted |
| 2532 | * half to memory as well. |
| 2533 | */ |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2534 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Razvan A Lupusoru | 8d0d03e | 2014-06-06 17:04:52 -0700 | [diff] [blame] | 2535 | for (uint32_t i = 0; i < mir_graph_->GetNumOfInVRs(); i++) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2536 | // get reg corresponding to input |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2537 | RegStorage reg = GetArgMappingToPhysicalReg(i); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2538 | |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2539 | RegLocation* t_loc = &ArgLocs[i]; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2540 | if (reg.Valid()) { |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2541 | // If arriving in register. |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2542 | |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2543 | // We have already updated the arg location with promoted info |
| 2544 | // so we can be based on it. |
| 2545 | if (t_loc->location == kLocPhysReg) { |
| 2546 | // Just copy it. |
| 2547 | OpRegCopy(t_loc->reg, reg); |
| 2548 | } else { |
| 2549 | // Needs flush. |
| 2550 | if (t_loc->ref) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2551 | StoreRefDisp(rs_rX86_SP, SRegOffset(start_vreg + i), reg, kNotVolatile); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2552 | } else { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2553 | StoreBaseDisp(rs_rX86_SP, SRegOffset(start_vreg + i), reg, t_loc->wide ? k64 : k32, |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2554 | kNotVolatile); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2555 | } |
| 2556 | } |
| 2557 | } else { |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2558 | // If arriving in frame & promoted. |
| 2559 | if (t_loc->location == kLocPhysReg) { |
| 2560 | if (t_loc->ref) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2561 | LoadRefDisp(rs_rX86_SP, SRegOffset(start_vreg + i), t_loc->reg, kNotVolatile); |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2562 | } else { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2563 | LoadBaseDisp(rs_rX86_SP, SRegOffset(start_vreg + i), t_loc->reg, |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2564 | t_loc->wide ? k64 : k32, kNotVolatile); |
| 2565 | } |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2566 | } |
Dmitry Petrochenko | 4d5d794 | 2014-06-27 12:25:01 +0700 | [diff] [blame] | 2567 | } |
| 2568 | if (t_loc->wide) { |
| 2569 | // Increment i to skip the next one. |
| 2570 | i++; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2571 | } |
| 2572 | } |
| 2573 | } |
| 2574 | |
| 2575 | /* |
| 2576 | * Load up to 5 arguments, the first three of which will be in |
| 2577 | * kArg1 .. kArg3. On entry kArg0 contains the current method pointer, |
| 2578 | * and as part of the load sequence, it must be replaced with |
| 2579 | * the target method pointer. Note, this may also be called |
| 2580 | * for "range" variants if the number of arguments is 5 or fewer. |
| 2581 | */ |
| 2582 | int X86Mir2Lir::GenDalvikArgsNoRange(CallInfo* info, |
| 2583 | int call_state, LIR** pcrLabel, NextCallInsn next_call_insn, |
| 2584 | const MethodReference& target_method, |
| 2585 | uint32_t vtable_idx, uintptr_t direct_code, |
| 2586 | uintptr_t direct_method, InvokeType type, bool skip_this) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2587 | if (!cu_->target64) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2588 | return Mir2Lir::GenDalvikArgsNoRange(info, |
| 2589 | call_state, pcrLabel, next_call_insn, |
| 2590 | target_method, |
| 2591 | vtable_idx, direct_code, |
| 2592 | direct_method, type, skip_this); |
| 2593 | } |
| 2594 | return GenDalvikArgsRange(info, |
| 2595 | call_state, pcrLabel, next_call_insn, |
| 2596 | target_method, |
| 2597 | vtable_idx, direct_code, |
| 2598 | direct_method, type, skip_this); |
| 2599 | } |
| 2600 | |
| 2601 | /* |
| 2602 | * May have 0+ arguments (also used for jumbo). Note that |
| 2603 | * source virtual registers may be in physical registers, so may |
| 2604 | * need to be flushed to home location before copying. This |
| 2605 | * applies to arg3 and above (see below). |
| 2606 | * |
| 2607 | * Two general strategies: |
| 2608 | * If < 20 arguments |
| 2609 | * Pass args 3-18 using vldm/vstm block copy |
| 2610 | * Pass arg0, arg1 & arg2 in kArg1-kArg3 |
| 2611 | * If 20+ arguments |
| 2612 | * Pass args arg19+ using memcpy block copy |
| 2613 | * Pass arg0, arg1 & arg2 in kArg1-kArg3 |
| 2614 | * |
| 2615 | */ |
| 2616 | int X86Mir2Lir::GenDalvikArgsRange(CallInfo* info, int call_state, |
| 2617 | LIR** pcrLabel, NextCallInsn next_call_insn, |
| 2618 | const MethodReference& target_method, |
| 2619 | uint32_t vtable_idx, uintptr_t direct_code, uintptr_t direct_method, |
| 2620 | InvokeType type, bool skip_this) { |
Elena Sayapina | dd64450 | 2014-07-01 18:39:52 +0700 | [diff] [blame] | 2621 | if (!cu_->target64) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2622 | return Mir2Lir::GenDalvikArgsRange(info, call_state, |
| 2623 | pcrLabel, next_call_insn, |
| 2624 | target_method, |
| 2625 | vtable_idx, direct_code, direct_method, |
| 2626 | type, skip_this); |
| 2627 | } |
| 2628 | |
| 2629 | /* If no arguments, just return */ |
| 2630 | if (info->num_arg_words == 0) |
| 2631 | return call_state; |
| 2632 | |
| 2633 | const int start_index = skip_this ? 1 : 0; |
| 2634 | |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2635 | InToRegStorageX86_64Mapper mapper(this); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2636 | InToRegStorageMapping in_to_reg_storage_mapping; |
| 2637 | in_to_reg_storage_mapping.Initialize(info->args, info->num_arg_words, &mapper); |
| 2638 | const int last_mapped_in = in_to_reg_storage_mapping.GetMaxMappedIn(); |
| 2639 | const int size_of_the_last_mapped = last_mapped_in == -1 ? 1 : |
Serguei Katkov | 8e3acdd | 2014-07-15 12:01:00 +0700 | [diff] [blame] | 2640 | info->args[last_mapped_in].wide ? 2 : 1; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2641 | int regs_left_to_pass_via_stack = info->num_arg_words - (last_mapped_in + size_of_the_last_mapped); |
| 2642 | |
| 2643 | // Fisrt of all, check whether it make sense to use bulk copying |
| 2644 | // Optimization is aplicable only for range case |
| 2645 | // TODO: make a constant instead of 2 |
| 2646 | if (info->is_range && regs_left_to_pass_via_stack >= 2) { |
| 2647 | // Scan the rest of the args - if in phys_reg flush to memory |
| 2648 | for (int next_arg = last_mapped_in + size_of_the_last_mapped; next_arg < info->num_arg_words;) { |
| 2649 | RegLocation loc = info->args[next_arg]; |
| 2650 | if (loc.wide) { |
| 2651 | loc = UpdateLocWide(loc); |
| 2652 | if (loc.location == kLocPhysReg) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2653 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2654 | StoreBaseDisp(rs_rX86_SP, SRegOffset(loc.s_reg_low), loc.reg, k64, kNotVolatile); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2655 | } |
| 2656 | next_arg += 2; |
| 2657 | } else { |
| 2658 | loc = UpdateLoc(loc); |
| 2659 | if (loc.location == kLocPhysReg) { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2660 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2661 | StoreBaseDisp(rs_rX86_SP, SRegOffset(loc.s_reg_low), loc.reg, k32, kNotVolatile); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2662 | } |
| 2663 | next_arg++; |
| 2664 | } |
| 2665 | } |
| 2666 | |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2667 | // The rest can be copied together |
| 2668 | int start_offset = SRegOffset(info->args[last_mapped_in + size_of_the_last_mapped].s_reg_low); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2669 | int outs_offset = StackVisitor::GetOutVROffset(last_mapped_in + size_of_the_last_mapped, |
| 2670 | cu_->instruction_set); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2671 | |
| 2672 | int current_src_offset = start_offset; |
| 2673 | int current_dest_offset = outs_offset; |
| 2674 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2675 | // Only davik regs are accessed in this loop; no next_call_insn() calls. |
| 2676 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2677 | while (regs_left_to_pass_via_stack > 0) { |
| 2678 | // This is based on the knowledge that the stack itself is 16-byte aligned. |
| 2679 | bool src_is_16b_aligned = (current_src_offset & 0xF) == 0; |
| 2680 | bool dest_is_16b_aligned = (current_dest_offset & 0xF) == 0; |
| 2681 | size_t bytes_to_move; |
| 2682 | |
| 2683 | /* |
| 2684 | * The amount to move defaults to 32-bit. If there are 4 registers left to move, then do a |
| 2685 | * a 128-bit move because we won't get the chance to try to aligned. If there are more than |
| 2686 | * 4 registers left to move, consider doing a 128-bit only if either src or dest are aligned. |
| 2687 | * We do this because we could potentially do a smaller move to align. |
| 2688 | */ |
| 2689 | if (regs_left_to_pass_via_stack == 4 || |
| 2690 | (regs_left_to_pass_via_stack > 4 && (src_is_16b_aligned || dest_is_16b_aligned))) { |
| 2691 | // Moving 128-bits via xmm register. |
| 2692 | bytes_to_move = sizeof(uint32_t) * 4; |
| 2693 | |
| 2694 | // Allocate a free xmm temp. Since we are working through the calling sequence, |
| 2695 | // we expect to have an xmm temporary available. AllocTempDouble will abort if |
| 2696 | // there are no free registers. |
| 2697 | RegStorage temp = AllocTempDouble(); |
| 2698 | |
| 2699 | LIR* ld1 = nullptr; |
| 2700 | LIR* ld2 = nullptr; |
| 2701 | LIR* st1 = nullptr; |
| 2702 | LIR* st2 = nullptr; |
| 2703 | |
| 2704 | /* |
| 2705 | * The logic is similar for both loads and stores. If we have 16-byte alignment, |
| 2706 | * do an aligned move. If we have 8-byte alignment, then do the move in two |
| 2707 | * parts. This approach prevents possible cache line splits. Finally, fall back |
| 2708 | * to doing an unaligned move. In most cases we likely won't split the cache |
| 2709 | * line but we cannot prove it and thus take a conservative approach. |
| 2710 | */ |
| 2711 | bool src_is_8b_aligned = (current_src_offset & 0x7) == 0; |
| 2712 | bool dest_is_8b_aligned = (current_dest_offset & 0x7) == 0; |
| 2713 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2714 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2715 | if (src_is_16b_aligned) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2716 | ld1 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset, kMovA128FP); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2717 | } else if (src_is_8b_aligned) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2718 | ld1 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset, kMovLo128FP); |
| 2719 | ld2 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset + (bytes_to_move >> 1), |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2720 | kMovHi128FP); |
| 2721 | } else { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2722 | ld1 = OpMovRegMem(temp, rs_rX86_SP, current_src_offset, kMovU128FP); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2723 | } |
| 2724 | |
| 2725 | if (dest_is_16b_aligned) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2726 | st1 = OpMovMemReg(rs_rX86_SP, current_dest_offset, temp, kMovA128FP); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2727 | } else if (dest_is_8b_aligned) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2728 | st1 = OpMovMemReg(rs_rX86_SP, current_dest_offset, temp, kMovLo128FP); |
| 2729 | st2 = OpMovMemReg(rs_rX86_SP, current_dest_offset + (bytes_to_move >> 1), |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2730 | temp, kMovHi128FP); |
| 2731 | } else { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2732 | st1 = OpMovMemReg(rs_rX86_SP, current_dest_offset, temp, kMovU128FP); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2733 | } |
| 2734 | |
| 2735 | // TODO If we could keep track of aliasing information for memory accesses that are wider |
| 2736 | // than 64-bit, we wouldn't need to set up a barrier. |
| 2737 | if (ld1 != nullptr) { |
| 2738 | if (ld2 != nullptr) { |
| 2739 | // For 64-bit load we can actually set up the aliasing information. |
| 2740 | AnnotateDalvikRegAccess(ld1, current_src_offset >> 2, true, true); |
| 2741 | AnnotateDalvikRegAccess(ld2, (current_src_offset + (bytes_to_move >> 1)) >> 2, true, true); |
| 2742 | } else { |
| 2743 | // Set barrier for 128-bit load. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2744 | ld1->u.m.def_mask = &kEncodeAll; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2745 | } |
| 2746 | } |
| 2747 | if (st1 != nullptr) { |
| 2748 | if (st2 != nullptr) { |
| 2749 | // For 64-bit store we can actually set up the aliasing information. |
| 2750 | AnnotateDalvikRegAccess(st1, current_dest_offset >> 2, false, true); |
| 2751 | AnnotateDalvikRegAccess(st2, (current_dest_offset + (bytes_to_move >> 1)) >> 2, false, true); |
| 2752 | } else { |
| 2753 | // Set barrier for 128-bit store. |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2754 | st1->u.m.def_mask = &kEncodeAll; |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2755 | } |
| 2756 | } |
| 2757 | |
| 2758 | // Free the temporary used for the data movement. |
| 2759 | FreeTemp(temp); |
| 2760 | } else { |
| 2761 | // Moving 32-bits via general purpose register. |
| 2762 | bytes_to_move = sizeof(uint32_t); |
| 2763 | |
| 2764 | // Instead of allocating a new temp, simply reuse one of the registers being used |
| 2765 | // for argument passing. |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2766 | RegStorage temp = TargetReg(kArg3, kNotWide); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2767 | |
| 2768 | // Now load the argument VR and store to the outs. |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2769 | Load32Disp(rs_rX86_SP, current_src_offset, temp); |
| 2770 | Store32Disp(rs_rX86_SP, current_dest_offset, temp); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2771 | } |
| 2772 | |
| 2773 | current_src_offset += bytes_to_move; |
| 2774 | current_dest_offset += bytes_to_move; |
| 2775 | regs_left_to_pass_via_stack -= (bytes_to_move >> 2); |
| 2776 | } |
| 2777 | DCHECK_EQ(regs_left_to_pass_via_stack, 0); |
| 2778 | } |
| 2779 | |
| 2780 | // Now handle rest not registers if they are |
| 2781 | if (in_to_reg_storage_mapping.IsThereStackMapped()) { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2782 | RegStorage regSingle = TargetReg(kArg2, kNotWide); |
| 2783 | RegStorage regWide = TargetReg(kArg3, kWide); |
Chao-ying Fu | b6564c1 | 2014-06-24 13:24:36 -0700 | [diff] [blame] | 2784 | for (int i = start_index; |
| 2785 | i < last_mapped_in + size_of_the_last_mapped + regs_left_to_pass_via_stack; i++) { |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2786 | RegLocation rl_arg = info->args[i]; |
| 2787 | rl_arg = UpdateRawLoc(rl_arg); |
| 2788 | RegStorage reg = in_to_reg_storage_mapping.Get(i); |
| 2789 | if (!reg.Valid()) { |
| 2790 | int out_offset = StackVisitor::GetOutVROffset(i, cu_->instruction_set); |
| 2791 | |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2792 | { |
| 2793 | ScopedMemRefType mem_ref_type(this, ResourceMask::kDalvikReg); |
| 2794 | if (rl_arg.wide) { |
| 2795 | if (rl_arg.location == kLocPhysReg) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2796 | StoreBaseDisp(rs_rX86_SP, out_offset, rl_arg.reg, k64, kNotVolatile); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2797 | } else { |
| 2798 | LoadValueDirectWideFixed(rl_arg, regWide); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2799 | StoreBaseDisp(rs_rX86_SP, out_offset, regWide, k64, kNotVolatile); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2800 | } |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2801 | } else { |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2802 | if (rl_arg.location == kLocPhysReg) { |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2803 | StoreBaseDisp(rs_rX86_SP, out_offset, rl_arg.reg, k32, kNotVolatile); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2804 | } else { |
| 2805 | LoadValueDirectFixed(rl_arg, regSingle); |
Chao-ying Fu | a77ee51 | 2014-07-01 17:43:41 -0700 | [diff] [blame] | 2806 | StoreBaseDisp(rs_rX86_SP, out_offset, regSingle, k32, kNotVolatile); |
Vladimir Marko | 8dea81c | 2014-06-06 14:50:36 +0100 | [diff] [blame] | 2807 | } |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2808 | } |
| 2809 | } |
| 2810 | call_state = next_call_insn(cu_, info, call_state, target_method, |
| 2811 | vtable_idx, direct_code, direct_method, type); |
| 2812 | } |
Chao-ying Fu | b6564c1 | 2014-06-24 13:24:36 -0700 | [diff] [blame] | 2813 | if (rl_arg.wide) { |
| 2814 | i++; |
| 2815 | } |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2816 | } |
| 2817 | } |
| 2818 | |
| 2819 | // Finish with mapped registers |
| 2820 | for (int i = start_index; i <= last_mapped_in; i++) { |
| 2821 | RegLocation rl_arg = info->args[i]; |
| 2822 | rl_arg = UpdateRawLoc(rl_arg); |
| 2823 | RegStorage reg = in_to_reg_storage_mapping.Get(i); |
| 2824 | if (reg.Valid()) { |
| 2825 | if (rl_arg.wide) { |
| 2826 | LoadValueDirectWideFixed(rl_arg, reg); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2827 | } else { |
| 2828 | LoadValueDirectFixed(rl_arg, reg); |
| 2829 | } |
| 2830 | call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, |
| 2831 | direct_code, direct_method, type); |
| 2832 | } |
Chao-ying Fu | b6564c1 | 2014-06-24 13:24:36 -0700 | [diff] [blame] | 2833 | if (rl_arg.wide) { |
| 2834 | i++; |
| 2835 | } |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2836 | } |
| 2837 | |
| 2838 | call_state = next_call_insn(cu_, info, call_state, target_method, vtable_idx, |
| 2839 | direct_code, direct_method, type); |
| 2840 | if (pcrLabel) { |
Dave Allison | 69dfe51 | 2014-07-11 17:11:58 +0000 | [diff] [blame] | 2841 | if (!cu_->compiler_driver->GetCompilerOptions().GetImplicitNullChecks()) { |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2842 | *pcrLabel = GenExplicitNullCheck(TargetReg(kArg1, kRef), info->opt_flags); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2843 | } else { |
| 2844 | *pcrLabel = nullptr; |
| 2845 | // In lieu of generating a check for kArg1 being null, we need to |
| 2846 | // perform a load when doing implicit checks. |
| 2847 | RegStorage tmp = AllocTemp(); |
Andreas Gampe | ccc6026 | 2014-07-04 18:02:38 -0700 | [diff] [blame] | 2848 | Load32Disp(TargetReg(kArg1, kRef), 0, tmp); |
Dmitry Petrochenko | 58994cd | 2014-05-17 01:02:18 +0700 | [diff] [blame] | 2849 | MarkPossibleNullPointerException(info->opt_flags); |
| 2850 | FreeTemp(tmp); |
| 2851 | } |
| 2852 | } |
| 2853 | return call_state; |
| 2854 | } |
| 2855 | |
Andreas Gampe | 9843059 | 2014-07-27 19:44:50 -0700 | [diff] [blame] | 2856 | bool X86Mir2Lir::GenInlinedCharAt(CallInfo* info) { |
| 2857 | // Location of reference to data array |
| 2858 | int value_offset = mirror::String::ValueOffset().Int32Value(); |
| 2859 | // Location of count |
| 2860 | int count_offset = mirror::String::CountOffset().Int32Value(); |
| 2861 | // Starting offset within data array |
| 2862 | int offset_offset = mirror::String::OffsetOffset().Int32Value(); |
| 2863 | // Start of char data with array_ |
| 2864 | int data_offset = mirror::Array::DataOffset(sizeof(uint16_t)).Int32Value(); |
| 2865 | |
| 2866 | RegLocation rl_obj = info->args[0]; |
| 2867 | RegLocation rl_idx = info->args[1]; |
| 2868 | rl_obj = LoadValue(rl_obj, kRefReg); |
| 2869 | // X86 wants to avoid putting a constant index into a register. |
| 2870 | if (!rl_idx.is_const) { |
| 2871 | rl_idx = LoadValue(rl_idx, kCoreReg); |
| 2872 | } |
| 2873 | RegStorage reg_max; |
| 2874 | GenNullCheck(rl_obj.reg, info->opt_flags); |
| 2875 | bool range_check = (!(info->opt_flags & MIR_IGNORE_RANGE_CHECK)); |
| 2876 | LIR* range_check_branch = nullptr; |
| 2877 | RegStorage reg_off; |
| 2878 | RegStorage reg_ptr; |
| 2879 | if (range_check) { |
| 2880 | // On x86, we can compare to memory directly |
| 2881 | // Set up a launch pad to allow retry in case of bounds violation */ |
| 2882 | if (rl_idx.is_const) { |
| 2883 | LIR* comparison; |
| 2884 | range_check_branch = OpCmpMemImmBranch( |
| 2885 | kCondUlt, RegStorage::InvalidReg(), rl_obj.reg, count_offset, |
| 2886 | mir_graph_->ConstantValue(rl_idx.orig_sreg), nullptr, &comparison); |
| 2887 | MarkPossibleNullPointerExceptionAfter(0, comparison); |
| 2888 | } else { |
| 2889 | OpRegMem(kOpCmp, rl_idx.reg, rl_obj.reg, count_offset); |
| 2890 | MarkPossibleNullPointerException(0); |
| 2891 | range_check_branch = OpCondBranch(kCondUge, nullptr); |
| 2892 | } |
| 2893 | } |
| 2894 | reg_off = AllocTemp(); |
| 2895 | reg_ptr = AllocTempRef(); |
| 2896 | Load32Disp(rl_obj.reg, offset_offset, reg_off); |
| 2897 | LoadRefDisp(rl_obj.reg, value_offset, reg_ptr, kNotVolatile); |
| 2898 | if (rl_idx.is_const) { |
| 2899 | OpRegImm(kOpAdd, reg_off, mir_graph_->ConstantValue(rl_idx.orig_sreg)); |
| 2900 | } else { |
| 2901 | OpRegReg(kOpAdd, reg_off, rl_idx.reg); |
| 2902 | } |
| 2903 | FreeTemp(rl_obj.reg); |
| 2904 | if (rl_idx.location == kLocPhysReg) { |
| 2905 | FreeTemp(rl_idx.reg); |
| 2906 | } |
| 2907 | RegLocation rl_dest = InlineTarget(info); |
| 2908 | RegLocation rl_result = EvalLoc(rl_dest, kCoreReg, true); |
| 2909 | LoadBaseIndexedDisp(reg_ptr, reg_off, 1, data_offset, rl_result.reg, kUnsignedHalf); |
| 2910 | FreeTemp(reg_off); |
| 2911 | FreeTemp(reg_ptr); |
| 2912 | StoreValue(rl_dest, rl_result); |
| 2913 | if (range_check) { |
| 2914 | DCHECK(range_check_branch != nullptr); |
| 2915 | info->opt_flags |= MIR_IGNORE_NULL_CHECK; // Record that we've already null checked. |
| 2916 | AddIntrinsicSlowPath(info, range_check_branch); |
| 2917 | } |
| 2918 | return true; |
| 2919 | } |
| 2920 | |
Alexei Zavjalov | 6bbf096 | 2014-07-15 02:19:41 +0700 | [diff] [blame] | 2921 | bool X86Mir2Lir::GenInlinedCurrentThread(CallInfo* info) { |
| 2922 | RegLocation rl_dest = InlineTarget(info); |
| 2923 | |
| 2924 | // Early exit if the result is unused. |
| 2925 | if (rl_dest.orig_sreg < 0) { |
| 2926 | return true; |
| 2927 | } |
| 2928 | |
| 2929 | RegLocation rl_result = EvalLoc(rl_dest, kRefReg, true); |
| 2930 | |
| 2931 | if (cu_->target64) { |
| 2932 | OpRegThreadMem(kOpMov, rl_result.reg, Thread::PeerOffset<8>()); |
| 2933 | } else { |
| 2934 | OpRegThreadMem(kOpMov, rl_result.reg, Thread::PeerOffset<4>()); |
| 2935 | } |
| 2936 | |
| 2937 | StoreValue(rl_dest, rl_result); |
| 2938 | return true; |
| 2939 | } |
| 2940 | |
Maxim Kazantsev | 6dccdc2 | 2014-08-18 18:43:55 +0700 | [diff] [blame] | 2941 | /** |
| 2942 | * Lock temp registers for explicit usage. Registers will be freed in destructor. |
| 2943 | */ |
| 2944 | X86Mir2Lir::ExplicitTempRegisterLock::ExplicitTempRegisterLock(X86Mir2Lir* mir_to_lir, |
| 2945 | int n_regs, ...) : |
| 2946 | temp_regs_(n_regs), |
| 2947 | mir_to_lir_(mir_to_lir) { |
| 2948 | va_list regs; |
| 2949 | va_start(regs, n_regs); |
| 2950 | for (int i = 0; i < n_regs; i++) { |
| 2951 | RegStorage reg = *(va_arg(regs, RegStorage*)); |
| 2952 | RegisterInfo* info = mir_to_lir_->GetRegInfo(reg); |
| 2953 | |
| 2954 | // Make sure we don't have promoted register here. |
| 2955 | DCHECK(info->IsTemp()); |
| 2956 | |
| 2957 | temp_regs_.push_back(reg); |
| 2958 | mir_to_lir_->FlushReg(reg); |
| 2959 | |
| 2960 | if (reg.IsPair()) { |
| 2961 | RegStorage partner = info->Partner(); |
| 2962 | temp_regs_.push_back(partner); |
| 2963 | mir_to_lir_->FlushReg(partner); |
| 2964 | } |
| 2965 | |
| 2966 | mir_to_lir_->Clobber(reg); |
| 2967 | mir_to_lir_->LockTemp(reg); |
| 2968 | } |
| 2969 | |
| 2970 | va_end(regs); |
| 2971 | } |
| 2972 | |
| 2973 | /* |
| 2974 | * Free all locked registers. |
| 2975 | */ |
| 2976 | X86Mir2Lir::ExplicitTempRegisterLock::~ExplicitTempRegisterLock() { |
| 2977 | // Free all locked temps. |
| 2978 | for (auto it : temp_regs_) { |
| 2979 | mir_to_lir_->FreeTemp(it); |
| 2980 | } |
| 2981 | } |
| 2982 | |
Brian Carlstrom | 7934ac2 | 2013-07-26 10:54:15 -0700 | [diff] [blame] | 2983 | } // namespace art |