Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2009 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
| 21 | * DEALINGS IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Zhenyu Wang <zhenyu.z.wang@intel.com> |
| 25 | * Wu Fengguang <fengguang.wu@intel.com> |
| 26 | * |
| 27 | */ |
| 28 | |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 29 | #define _GNU_SOURCE |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 30 | #include <unistd.h> |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 31 | #include <stdlib.h> |
| 32 | #include <stdio.h> |
| 33 | #include <string.h> |
| 34 | #include <err.h> |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 35 | #include <arpa/inet.h> |
Daniel Vetter | c03c6ce | 2014-03-22 21:34:29 +0100 | [diff] [blame] | 36 | #include "intel_io.h" |
Daniel Vetter | 6cfcd71 | 2014-03-22 20:07:35 +0100 | [diff] [blame] | 37 | #include "intel_reg.h" |
| 38 | #include "intel_chipset.h" |
| 39 | #include "drmtest.h" |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 40 | |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 41 | static uint32_t devid; |
| 42 | |
Mengdong Lin | 92d3197 | 2014-03-03 11:04:39 -0500 | [diff] [blame] | 43 | static int aud_reg_base = 0; /* base address of audio registers */ |
| 44 | static int disp_reg_base = 0; /* base address of display registers */ |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 45 | |
Mengdong Lin | 1803f1e | 2014-02-28 16:18:11 -0500 | [diff] [blame] | 46 | #define IS_HASWELL_PLUS(devid) (IS_HASWELL(devid) || IS_BROADWELL(devid)) |
| 47 | |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 48 | #define BITSTO(n) (n >= sizeof(long) * 8 ? ~0 : (1UL << (n)) - 1) |
| 49 | #define BITMASK(high, low) (BITSTO(high+1) & ~BITSTO(low)) |
| 50 | #define BITS(reg, high, low) (((reg) & (BITMASK(high, low))) >> (low)) |
| 51 | #define BIT(reg, n) BITS(reg, n, n) |
| 52 | |
| 53 | #define min_t(type, x, y) ({ \ |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 54 | type __min1 = (x); \ |
| 55 | type __min2 = (y); \ |
| 56 | __min1 < __min2 ? __min1 : __min2; }) |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 57 | |
| 58 | #define OPNAME(names, index) \ |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 59 | names[min_t(unsigned int, index, ARRAY_SIZE(names) - 1)] |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 60 | |
Mengdong Lin | 92d3197 | 2014-03-03 11:04:39 -0500 | [diff] [blame] | 61 | #define set_aud_reg_base(base) (aud_reg_base = (base)) |
| 62 | |
| 63 | #define set_reg_base(base, audio_offset) \ |
| 64 | do { \ |
| 65 | disp_reg_base = (base); \ |
| 66 | set_aud_reg_base((base) + (audio_offset)); \ |
| 67 | } while (0) |
| 68 | |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 69 | #define dump_reg(reg, desc) \ |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 70 | do { \ |
| 71 | dword = INREG(reg); \ |
Yang, Libin | 9917744 | 2015-01-12 01:38:34 +0000 | [diff] [blame] | 72 | printf("%-21s(%#x) 0x%08x %s\n", # reg, reg, dword, desc); \ |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 73 | } while (0) |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 74 | |
Mengdong Lin | 92d3197 | 2014-03-03 11:04:39 -0500 | [diff] [blame] | 75 | #define dump_disp_reg(reg, desc) \ |
| 76 | do { \ |
| 77 | dword = INREG(disp_reg_base + reg); \ |
Yang, Libin | 9917744 | 2015-01-12 01:38:34 +0000 | [diff] [blame] | 78 | printf("%-21s(%#x) 0x%08x %s\n", # reg, reg, dword, desc); \ |
Mengdong Lin | 92d3197 | 2014-03-03 11:04:39 -0500 | [diff] [blame] | 79 | } while (0) |
| 80 | |
| 81 | #define dump_aud_reg(reg, desc) \ |
| 82 | do { \ |
| 83 | dword = INREG(aud_reg_base + reg); \ |
Yang, Libin | 9917744 | 2015-01-12 01:38:34 +0000 | [diff] [blame] | 84 | printf("%-21s(%#x) 0x%08x %s\n", # reg, reg, dword, desc); \ |
Mengdong Lin | 92d3197 | 2014-03-03 11:04:39 -0500 | [diff] [blame] | 85 | } while (0) |
| 86 | |
| 87 | #define read_aud_reg(reg) INREG(aud_reg_base + (reg)) |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 88 | |
Mengdong Lin | bae8a00 | 2014-03-03 13:23:50 -0500 | [diff] [blame] | 89 | static int get_num_pipes(void) |
| 90 | { |
| 91 | int num_pipes; |
| 92 | |
| 93 | if (IS_VALLEYVIEW(devid)) |
| 94 | num_pipes = 2; /* Valleyview is Gen 7 but only has 2 pipes */ |
| 95 | else if (IS_G4X(devid) || IS_GEN5(devid)) |
| 96 | num_pipes = 2; |
| 97 | else |
| 98 | num_pipes = 3; |
| 99 | |
| 100 | return num_pipes; |
| 101 | } |
| 102 | |
Mengdong Lin | 8fe0c50 | 2014-03-13 16:38:02 -0400 | [diff] [blame] | 103 | static const char * const cts_m_value_index[] = { |
| 104 | [0] = "CTS", |
| 105 | [1] = "M", |
| 106 | }; |
| 107 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 108 | static const char * const pixel_clock[] = { |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 109 | [0] = "25.2 / 1.001 MHz", |
| 110 | [1] = "25.2 MHz", |
| 111 | [2] = "27 MHz", |
| 112 | [3] = "27 * 1.001 MHz", |
| 113 | [4] = "54 MHz", |
| 114 | [5] = "54 * 1.001 MHz", |
| 115 | [6] = "74.25 / 1.001 MHz", |
| 116 | [7] = "74.25 MHz", |
| 117 | [8] = "148.5 / 1.001 MHz", |
| 118 | [9] = "148.5 MHz", |
| 119 | [10] = "Reserved", |
| 120 | }; |
| 121 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 122 | static const char * const power_state[] = { |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 123 | [0] = "D0", |
| 124 | [1] = "D1", |
| 125 | [2] = "D2", |
| 126 | [3] = "D3", |
| 127 | }; |
| 128 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 129 | static const char * const stream_type[] = { |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 130 | [0] = "default samples", |
| 131 | [1] = "one bit stream", |
| 132 | [2] = "DST stream", |
| 133 | [3] = "MLP stream", |
| 134 | [4] = "Reserved", |
| 135 | }; |
| 136 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 137 | static const char * const dip_port[] = { |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 138 | [0] = "Reserved", |
| 139 | [1] = "Digital Port B", |
| 140 | [2] = "Digital Port C", |
| 141 | [3] = "Digital Port D", |
| 142 | }; |
| 143 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 144 | static const char * const dip_type[] = { |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 145 | [0] = "Audio DIP Disabled", |
| 146 | [1] = "Audio DIP Enabled", |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 147 | }; |
| 148 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 149 | static const char * const dip_gen1_state[] = { |
| 150 | [0] = "Generic 1 (ACP) DIP Disabled", |
| 151 | [1] = "Generic 1 (ACP) DIP Enabled", |
| 152 | }; |
| 153 | |
| 154 | static const char * const dip_gen2_state[] = { |
| 155 | [0] = "Generic 2 DIP Disabled", |
| 156 | [1] = "Generic 2 DIP Enabled", |
| 157 | }; |
| 158 | |
| 159 | static const char * const dip_index[] = { |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 160 | [0] = "Audio DIP", |
| 161 | [1] = "ACP DIP", |
| 162 | [2] = "ISRC1 DIP", |
| 163 | [3] = "ISRC2 DIP", |
| 164 | [4] = "Reserved", |
| 165 | }; |
| 166 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 167 | static const char * const dip_trans[] = { |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 168 | [0] = "disabled", |
| 169 | [1] = "reserved", |
| 170 | [2] = "send once", |
| 171 | [3] = "best effort", |
| 172 | }; |
| 173 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 174 | static const char * const video_dip_index[] = { |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 175 | [0] = "AVI DIP", |
| 176 | [1] = "Vendor-specific DIP", |
Wu Fengguang | f3f84bb | 2011-11-12 11:12:55 +0800 | [diff] [blame] | 177 | [2] = "Gamut Metadata DIP", |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 178 | [3] = "Source Product Description DIP", |
| 179 | }; |
| 180 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 181 | static const char * const video_dip_trans[] = { |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 182 | [0] = "send once", |
| 183 | [1] = "send every vsync", |
| 184 | [2] = "send at least every other vsync", |
| 185 | [3] = "reserved", |
| 186 | }; |
| 187 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 188 | static const char * const trans_to_port_sel[] = { |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 189 | [0] = "no port", |
| 190 | [1] = "Digital Port B", |
Wang Xingchao | f9a2481 | 2012-08-15 16:13:37 +0800 | [diff] [blame] | 191 | [2] = "Digital Port C", |
| 192 | [3] = "Digital Port D", |
| 193 | [4] = "reserved", |
Alan Coopersmith | c461006 | 2012-01-06 14:37:19 -0800 | [diff] [blame] | 194 | [5] = "reserved", |
| 195 | [6] = "reserved", |
| 196 | [7] = "reserved", |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 197 | }; |
| 198 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 199 | static const char * const ddi_mode[] = { |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 200 | [0] = "HDMI mode", |
| 201 | [1] = "DVI mode", |
| 202 | [2] = "DP SST mode", |
| 203 | [3] = "DP MST mode", |
| 204 | [4] = "DP FDI mode", |
| 205 | [5] = "reserved", |
| 206 | [6] = "reserved", |
| 207 | [7] = "reserved", |
| 208 | }; |
| 209 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 210 | static const char * const bits_per_color[] = { |
| 211 | [0] = "8 bpc", |
| 212 | [1] = "10 bpc", |
| 213 | [2] = "6 bpc", |
| 214 | [3] = "12 bpc", |
| 215 | [4] = "reserved", |
| 216 | [5] = "reserved", |
| 217 | [6] = "reserved", |
| 218 | [7] = "reserved", |
| 219 | }; |
| 220 | |
| 221 | static const char * const transcoder_select[] = { |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 222 | [0] = "Transcoder A", |
| 223 | [1] = "Transcoder B", |
| 224 | [2] = "Transcoder C", |
| 225 | [3] = "reserved", |
| 226 | }; |
| 227 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 228 | static const char * const dp_port_width[] = { |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 229 | [0] = "x1 mode", |
| 230 | [1] = "x2 mode", |
Wu Fengguang | cf4c12f | 2011-11-12 11:12:46 +0800 | [diff] [blame] | 231 | [2] = "reserved", |
| 232 | [3] = "x4 mode", |
Alan Coopersmith | c461006 | 2012-01-06 14:37:19 -0800 | [diff] [blame] | 233 | [4] = "reserved", |
| 234 | [5] = "reserved", |
| 235 | [6] = "reserved", |
| 236 | [7] = "reserved", |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 237 | }; |
| 238 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 239 | static const char * const sample_base_rate[] = { |
| 240 | [0] = "48 kHz", |
| 241 | [1] = "44.1 kHz", |
| 242 | }; |
| 243 | |
| 244 | static const char * const sample_base_rate_mult[] = { |
| 245 | [0] = "x1 (48 kHz, 44.1 kHz or less)", |
| 246 | [1] = "x2 (96 kHz, 88.2 kHz, 32 kHz)", |
| 247 | [2] = "x3 (144 kHz)", |
| 248 | [3] = "x4 (192 kHz, 176.4 kHz)", |
| 249 | [4] = "Reserved", |
| 250 | }; |
| 251 | |
| 252 | static const char * const sample_base_rate_divisor[] = { |
| 253 | [0] = "Divided by 1 (48 kHz, 44.1 kHz)", |
| 254 | [1] = "Divided by 2 (24 kHz, 22.05 kHz)", |
| 255 | [2] = "Divided by 3 (16 kHz, 32 kHz)", |
| 256 | [3] = "Divided by 4 (11.025 kHz)", |
| 257 | [4] = "Divided by 5 (9.6 kHz)", |
| 258 | [5] = "Divided by 6 (8 kHz)", |
| 259 | [6] = "Divided by 7", |
| 260 | [7] = "Divided by 8 (6 kHz)", |
| 261 | }; |
| 262 | |
| 263 | static const char * const connect_list_form[] = { |
| 264 | [0] = "Short Form", |
| 265 | [1] = "Long Form", |
| 266 | }; |
| 267 | |
| 268 | |
| 269 | static const char * const bits_per_sample[] = { |
Wu Fengguang | 12861a9 | 2011-11-12 11:12:47 +0800 | [diff] [blame] | 270 | [0] = "reserved", |
| 271 | [1] = "16 bits", |
| 272 | [2] = "24 bits", |
| 273 | [3] = "32 bits", |
| 274 | [4] = "20 bits", |
| 275 | [5] = "reserved", |
| 276 | }; |
| 277 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 278 | static const char * const sdvo_hdmi_encoding[] = { |
Wu Fengguang | ee94958 | 2011-11-12 11:12:53 +0800 | [diff] [blame] | 279 | [0] = "SDVO", |
| 280 | [1] = "reserved", |
| 281 | [2] = "TMDS", |
| 282 | [3] = "reserved", |
| 283 | }; |
Wu Fengguang | 12861a9 | 2011-11-12 11:12:47 +0800 | [diff] [blame] | 284 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 285 | static const char * const n_index_value[] = { |
Wu Fengguang | e64abe5 | 2012-01-17 07:19:24 +0800 | [diff] [blame] | 286 | [0] = "HDMI", |
| 287 | [1] = "DisplayPort", |
| 288 | }; |
| 289 | |
Mengdong Lin | 8535720 | 2013-08-13 00:21:57 -0400 | [diff] [blame] | 290 | static const char * const immed_result_valid[] = { |
| 291 | [0] = "No immediate response is available", |
| 292 | [1] = "Immediate response is available", |
| 293 | }; |
| 294 | |
| 295 | static const char * const immed_cmd_busy[] = { |
| 296 | [0] = "Can accept an immediate command", |
| 297 | [1] = "Immediate command is available", |
| 298 | }; |
| 299 | |
Mengdong Lin | f075c3c | 2013-08-13 00:22:14 -0400 | [diff] [blame] | 300 | static const char * const vanilla_dp12_en[] = { |
| 301 | [0] = "DP 1.2 features are disabled", |
| 302 | [1] = "DP 1.2 features are enabled", |
| 303 | }; |
| 304 | |
| 305 | static const char * const vanilla_3_widgets_en[] = { |
| 306 | [0] = "2nd & 3rd pin/convertor widgets are disabled", |
| 307 | [1] = "All three pin/convertor widgets are enabled", |
| 308 | }; |
| 309 | |
| 310 | static const char * const block_audio[] = { |
| 311 | [0] = "Allow audio data to reach the port", |
| 312 | [1] = "Block audio data from reaching the port", |
| 313 | }; |
| 314 | |
| 315 | static const char * const dis_eld_valid_pulse_trans[] = { |
| 316 | [0] = "Enable ELD valid pulse transition when unsol is disabled", |
| 317 | [1] = "Disable ELD valid pulse transition when unsol is disabled", |
| 318 | }; |
| 319 | |
| 320 | static const char * const dis_pd_pulse_trans[] = { |
| 321 | [0] = "Enable Presense Detect pulse transition when unsol is disabled", |
| 322 | [1] = "Disable Presense Detect pulse transition when unsol is disabled", |
| 323 | }; |
| 324 | |
| 325 | static const char * const dis_ts_delta_err[] = { |
| 326 | [0] = "Enable timestamp delta error for 32/44 KHz", |
| 327 | [1] = "Disable timestamp delta error for 32/44 KHz", |
| 328 | }; |
| 329 | |
| 330 | static const char * const dis_ts_fix_dp_hbr[] = { |
| 331 | [0] = "Enable timestamp fix for DP HBR", |
| 332 | [1] = "Disable timestamp fix for DP HBR", |
| 333 | }; |
| 334 | |
| 335 | static const char * const pattern_gen_8_ch_en[] = { |
| 336 | [0] = "Disable 8-channel pattern generator", |
| 337 | [1] = "Enable 8-channel pattern generator", |
| 338 | }; |
| 339 | |
| 340 | static const char * const pattern_gen_2_ch_en[] = { |
| 341 | [0] = "Disable 2-channel pattern generator", |
| 342 | [1] = "Enable 2-channel pattern generator", |
| 343 | }; |
| 344 | |
| 345 | static const char * const fabric_32_44_dis[] = { |
| 346 | [0] = "Allow sample fabrication for 32/44 KHz", |
| 347 | [1] = "Disable sample fabrication for 32/44 KHz", |
| 348 | }; |
| 349 | |
| 350 | static const char * const epss_dis[] = { |
| 351 | [0] = "Allow audio EPSS", |
| 352 | [1] = "Disable audio EPSS", |
| 353 | }; |
| 354 | |
| 355 | static const char * const ts_test_mode[] = { |
| 356 | [0] = "Default time stamp mode", |
| 357 | [1] = "Audio time stamp test mode for audio only feature", |
| 358 | }; |
| 359 | |
| 360 | static const char * const en_mmio_program[] = { |
| 361 | [0] = "Programming by HD-Audio Azalia", |
| 362 | [1] = "Programming by MMIO debug registers", |
| 363 | }; |
| 364 | |
Lu, Han | e8e2893 | 2015-02-12 08:41:59 +0800 | [diff] [blame] | 365 | static const char * const sdi_operate_mode[] = { |
| 366 | [0] = "2T mode with sdi data held for 2 bit clocks", |
| 367 | [1] = "1T mode with sdi data held for 1 bit clock only", |
| 368 | }; |
| 369 | |
| 370 | static const char * const bclk_96mhz[] = { |
| 371 | [0] = "iDisplay audio link 96MHz bclk off", |
| 372 | [1] = "iDisplay audio link 96MHz bclk on", |
| 373 | }; |
| 374 | |
| 375 | static const char * const bclk_48mhz[] = { |
| 376 | [0] = "iDisplay audio link 48MHz bclk off", |
| 377 | [1] = "iDisplay audio link 48MHz bclk on", |
| 378 | }; |
| 379 | |
Mengdong Lin | 97e5cf6 | 2013-08-13 00:22:24 -0400 | [diff] [blame] | 380 | static const char * const audio_dp_dip_status[] = { |
| 381 | [0] = "audfc dp fifo full", |
| 382 | [1] = "audfc dp fifo empty", |
| 383 | [2] = "audfc dp fifo overrun", |
| 384 | [3] = "audfc dip fifo full", |
| 385 | [4] = "audfc dp fifo empty cd", |
| 386 | [5] = "audfb dp fifo full", |
| 387 | [6] = "audfb dp fifo empty", |
| 388 | [7] = "audfb dp fifo overrun", |
| 389 | [8] = "audfb dip fifo full", |
| 390 | [9] = "audfb dp fifo empty cd", |
| 391 | [10] = "audfa dp fifo full", |
| 392 | [11] = "audfa dp fifo empty", |
| 393 | [12] = "audfa dp fifo overrun", |
| 394 | [13] = "audfa dip fifo full", |
| 395 | [14] = "audfa dp fifo empty cd", |
| 396 | [15] = "Pipe c audio overflow", |
| 397 | [16] = "Pipe b audio overflow", |
| 398 | [17] = "Pipe a audio overflow", |
| 399 | [31] = 0, |
| 400 | }; |
| 401 | |
Mengdong Lin | ed38666 | 2014-02-28 13:25:27 -0500 | [diff] [blame] | 402 | #undef TRANSCODER_A |
| 403 | #undef TRANSCODER_B |
| 404 | #undef TRANSCODER_C |
| 405 | |
| 406 | enum { |
| 407 | TRANSCODER_A = 0, |
| 408 | TRANSCODER_B, |
| 409 | TRANSCODER_C, |
| 410 | }; |
| 411 | |
| 412 | enum { |
| 413 | PIPE_A = 0, |
| 414 | PIPE_B, |
| 415 | PIPE_C, |
| 416 | }; |
| 417 | |
| 418 | enum { |
| 419 | PORT_A = 0, |
| 420 | PORT_B, |
| 421 | PORT_C, |
| 422 | PORT_D, |
| 423 | PORT_E, |
| 424 | }; |
| 425 | |
| 426 | enum { |
| 427 | CONVERTER_1 = 0, |
| 428 | CONVERTER_2, |
| 429 | CONVERTER_3, |
| 430 | }; |
| 431 | |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 432 | static void do_self_tests(void) |
| 433 | { |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 434 | if (BIT(1, 0) != 1) |
| 435 | exit(1); |
| 436 | if (BIT(0x80000000, 31) != 1) |
| 437 | exit(2); |
| 438 | if (BITS(0xc0000000, 31, 30) != 3) |
| 439 | exit(3); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 440 | } |
| 441 | |
| 442 | /* |
| 443 | * EagleLake registers |
| 444 | */ |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 445 | #define AUD_CONFIG 0x62000 |
| 446 | #define AUD_DEBUG 0x62010 |
| 447 | #define AUD_VID_DID 0x62020 |
| 448 | #define AUD_RID 0x62024 |
| 449 | #define AUD_SUBN_CNT 0x62028 |
| 450 | #define AUD_FUNC_GRP 0x62040 |
| 451 | #define AUD_SUBN_CNT2 0x62044 |
| 452 | #define AUD_GRP_CAP 0x62048 |
| 453 | #define AUD_PWRST 0x6204c |
| 454 | #define AUD_SUPPWR 0x62050 |
| 455 | #define AUD_SID 0x62054 |
| 456 | #define AUD_OUT_CWCAP 0x62070 |
| 457 | #define AUD_OUT_PCMSIZE 0x62074 |
| 458 | #define AUD_OUT_STR 0x62078 |
| 459 | #define AUD_OUT_DIG_CNVT 0x6207c |
| 460 | #define AUD_OUT_CH_STR 0x62080 |
| 461 | #define AUD_OUT_STR_DESC 0x62084 |
| 462 | #define AUD_PINW_CAP 0x620a0 |
| 463 | #define AUD_PIN_CAP 0x620a4 |
| 464 | #define AUD_PINW_CONNLNG 0x620a8 |
| 465 | #define AUD_PINW_CONNLST 0x620ac |
| 466 | #define AUD_PINW_CNTR 0x620b0 |
| 467 | #define AUD_PINW_UNSOLRESP 0x620b8 |
| 468 | #define AUD_CNTL_ST 0x620b4 |
| 469 | #define AUD_PINW_CONFIG 0x620bc |
| 470 | #define AUD_HDMIW_STATUS 0x620d4 |
| 471 | #define AUD_HDMIW_HDMIEDID 0x6210c |
| 472 | #define AUD_HDMIW_INFOFR 0x62118 |
| 473 | #define AUD_CONV_CHCNT 0x62120 |
| 474 | #define AUD_CTS_ENABLE 0x62128 |
| 475 | |
| 476 | #define VIDEO_DIP_CTL 0x61170 |
| 477 | #define VIDEO_DIP_ENABLE (1<<31) |
| 478 | #define VIDEO_DIP_ENABLE_AVI (1<<21) |
| 479 | #define VIDEO_DIP_ENABLE_VENDOR (1<<22) |
| 480 | #define VIDEO_DIP_ENABLE_SPD (1<<24) |
| 481 | #define VIDEO_DIP_BUF_AVI (0<<19) |
| 482 | #define VIDEO_DIP_BUF_VENDOR (1<<19) |
| 483 | #define VIDEO_DIP_BUF_SPD (3<<19) |
| 484 | #define VIDEO_DIP_TRANS_ONCE (0<<16) |
| 485 | #define VIDEO_DIP_TRANS_1 (1<<16) |
| 486 | #define VIDEO_DIP_TRANS_2 (2<<16) |
| 487 | |
| 488 | #define AUDIO_HOTPLUG_EN (1<<24) |
| 489 | |
| 490 | |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 491 | static void dump_eaglelake(void) |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 492 | { |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 493 | uint32_t dword; |
| 494 | int i; |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 495 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 496 | /* printf("%-18s %8s %s\n\n", "register name", "raw value", "description"); */ |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 497 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 498 | dump_reg(VIDEO_DIP_CTL, "Video DIP Control"); |
| 499 | dump_reg(SDVOB, "Digital Display Port B Control Register"); |
| 500 | dump_reg(SDVOC, "Digital Display Port C Control Register"); |
| 501 | dump_reg(PORT_HOTPLUG_EN, "Hot Plug Detect Enable"); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 502 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 503 | dump_reg(AUD_CONFIG, "Audio Configuration"); |
| 504 | dump_reg(AUD_DEBUG, "Audio Debug"); |
| 505 | dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID"); |
| 506 | dump_reg(AUD_RID, "Audio Revision ID"); |
| 507 | dump_reg(AUD_SUBN_CNT, "Audio Subordinate Node Count"); |
| 508 | dump_reg(AUD_FUNC_GRP, "Audio Function Group Type"); |
| 509 | dump_reg(AUD_SUBN_CNT2, "Audio Subordinate Node Count"); |
| 510 | dump_reg(AUD_GRP_CAP, "Audio Function Group Capabilities"); |
| 511 | dump_reg(AUD_PWRST, "Audio Power State"); |
| 512 | dump_reg(AUD_SUPPWR, "Audio Supported Power States"); |
| 513 | dump_reg(AUD_SID, "Audio Root Node Subsystem ID"); |
| 514 | dump_reg(AUD_OUT_CWCAP, "Audio Output Converter Widget Capabilities"); |
| 515 | dump_reg(AUD_OUT_PCMSIZE, "Audio PCM Size and Rates"); |
| 516 | dump_reg(AUD_OUT_STR, "Audio Stream Formats"); |
| 517 | dump_reg(AUD_OUT_DIG_CNVT, "Audio Digital Converter"); |
| 518 | dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID"); |
| 519 | dump_reg(AUD_OUT_STR_DESC, "Audio Stream Descriptor Format"); |
| 520 | dump_reg(AUD_PINW_CAP, "Audio Pin Complex Widget Capabilities"); |
| 521 | dump_reg(AUD_PIN_CAP, "Audio Pin Capabilities"); |
| 522 | dump_reg(AUD_PINW_CONNLNG, "Audio Connection List Length"); |
| 523 | dump_reg(AUD_PINW_CONNLST, "Audio Connection List Entry"); |
| 524 | dump_reg(AUD_PINW_CNTR, "Audio Pin Widget Control"); |
| 525 | dump_reg(AUD_PINW_UNSOLRESP, "Audio Unsolicited Response Enable"); |
| 526 | dump_reg(AUD_CNTL_ST, "Audio Control State Register"); |
| 527 | dump_reg(AUD_PINW_CONFIG, "Audio Configuration Default"); |
| 528 | dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status"); |
| 529 | dump_reg(AUD_HDMIW_HDMIEDID, "Audio HDMI Data EDID Block"); |
| 530 | dump_reg(AUD_HDMIW_INFOFR, "Audio HDMI Widget Data Island Packet"); |
| 531 | dump_reg(AUD_CONV_CHCNT, "Audio Converter Channel Count"); |
| 532 | dump_reg(AUD_CTS_ENABLE, "Audio CTS Programming Enable"); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 533 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 534 | printf("\nDetails:\n\n"); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 535 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 536 | dword = INREG(AUD_VID_DID); |
| 537 | printf("AUD_VID_DID vendor id\t\t\t0x%x\n", dword >> 16); |
| 538 | printf("AUD_VID_DID device id\t\t\t0x%x\n", dword & 0xffff); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 539 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 540 | dword = INREG(AUD_RID); |
| 541 | printf("AUD_RID major revision\t\t\t0x%lx\n", BITS(dword, 23, 20)); |
| 542 | printf("AUD_RID minor revision\t\t\t0x%lx\n", BITS(dword, 19, 16)); |
| 543 | printf("AUD_RID revision id\t\t\t0x%lx\n", BITS(dword, 15, 8)); |
| 544 | printf("AUD_RID stepping id\t\t\t0x%lx\n", BITS(dword, 7, 0)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 545 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 546 | dword = INREG(SDVOB); |
| 547 | printf("SDVOB enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE)); |
| 548 | printf("SDVOB HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI)); |
| 549 | printf("SDVOB SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO)); |
| 550 | printf("SDVOB null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC)); |
| 551 | printf("SDVOB audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 552 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 553 | dword = INREG(SDVOC); |
| 554 | printf("SDVOC enable\t\t\t\t%u\n", !!(dword & SDVO_ENABLE)); |
| 555 | printf("SDVOC HDMI encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_HDMI)); |
| 556 | printf("SDVOC SDVO encoding\t\t\t%u\n", !!(dword & SDVO_ENCODING_SDVO)); |
| 557 | printf("SDVOC null packets\t\t\t%u\n", !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC)); |
| 558 | printf("SDVOC audio enabled\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 559 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 560 | dword = INREG(PORT_HOTPLUG_EN); |
| 561 | printf("PORT_HOTPLUG_EN DisplayPort/HDMI port B\t%ld\n", BIT(dword, 29)), |
| 562 | printf("PORT_HOTPLUG_EN DisplayPort/HDMI port C\t%ld\n", BIT(dword, 28)), |
| 563 | printf("PORT_HOTPLUG_EN DisplayPort port D\t%ld\n", BIT(dword, 27)), |
| 564 | printf("PORT_HOTPLUG_EN SDVOB\t\t\t%ld\n", BIT(dword, 26)), |
| 565 | printf("PORT_HOTPLUG_EN SDVOC\t\t\t%ld\n", BIT(dword, 25)), |
| 566 | printf("PORT_HOTPLUG_EN audio\t\t\t%ld\n", BIT(dword, 24)), |
| 567 | printf("PORT_HOTPLUG_EN TV\t\t\t%ld\n", BIT(dword, 23)), |
| 568 | printf("PORT_HOTPLUG_EN CRT\t\t\t%ld\n", BIT(dword, 9)), |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 569 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 570 | dword = INREG(VIDEO_DIP_CTL); |
| 571 | printf("VIDEO_DIP_CTL enable graphics DIP\t%ld\n", BIT(dword, 31)), |
| 572 | printf("VIDEO_DIP_CTL port select\t\t[0x%lx] %s\n", |
| 573 | BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]); |
| 574 | printf("VIDEO_DIP_CTL DIP buffer trans active\t%lu\n", BIT(dword, 28)); |
| 575 | printf("VIDEO_DIP_CTL AVI DIP enabled\t\t%lu\n", BIT(dword, 21)); |
| 576 | printf("VIDEO_DIP_CTL vendor DIP enabled\t%lu\n", BIT(dword, 22)); |
| 577 | printf("VIDEO_DIP_CTL SPD DIP enabled\t\t%lu\n", BIT(dword, 24)); |
| 578 | printf("VIDEO_DIP_CTL DIP buffer index\t\t[0x%lx] %s\n", |
| 579 | BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]); |
| 580 | printf("VIDEO_DIP_CTL DIP trans freq\t\t[0x%lx] %s\n", |
| 581 | BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]); |
| 582 | printf("VIDEO_DIP_CTL DIP buffer size\t\t%lu\n", BITS(dword, 11, 8)); |
| 583 | printf("VIDEO_DIP_CTL DIP address\t\t%lu\n", BITS(dword, 3, 0)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 584 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 585 | dword = INREG(AUD_CONFIG); |
| 586 | printf("AUD_CONFIG pixel clock\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16), |
| 587 | OPNAME(pixel_clock, BITS(dword, 19, 16))); |
| 588 | printf("AUD_CONFIG fabrication enabled\t\t%lu\n", BITS(dword, 2, 2)); |
| 589 | printf("AUD_CONFIG professional use allowed\t%lu\n", BIT(dword, 1)); |
| 590 | printf("AUD_CONFIG fuse enabled\t\t\t%lu\n", BIT(dword, 0)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 591 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 592 | dword = INREG(AUD_DEBUG); |
| 593 | printf("AUD_DEBUG function reset\t\t%lu\n", BIT(dword, 0)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 594 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 595 | dword = INREG(AUD_SUBN_CNT); |
| 596 | printf("AUD_SUBN_CNT starting node number\t0x%lx\n", BITS(dword, 23, 16)); |
| 597 | printf("AUD_SUBN_CNT total number of nodes\t0x%lx\n", BITS(dword, 7, 0)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 598 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 599 | dword = INREG(AUD_SUBN_CNT2); |
| 600 | printf("AUD_SUBN_CNT2 starting node number\t0x%lx\n", BITS(dword, 24, 16)); |
| 601 | printf("AUD_SUBN_CNT2 total number of nodes\t0x%lx\n", BITS(dword, 7, 0)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 602 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 603 | dword = INREG(AUD_FUNC_GRP); |
| 604 | printf("AUD_FUNC_GRP unsol capable\t\t%lu\n", BIT(dword, 8)); |
| 605 | printf("AUD_FUNC_GRP node type\t\t\t0x%lx\n", BITS(dword, 7, 0)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 606 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 607 | dword = INREG(AUD_GRP_CAP); |
| 608 | printf("AUD_GRP_CAP beep 0\t\t\t%lu\n", BIT(dword, 16)); |
| 609 | printf("AUD_GRP_CAP input delay\t\t\t%lu\n", BITS(dword, 11, 8)); |
| 610 | printf("AUD_GRP_CAP output delay\t\t%lu\n", BITS(dword, 3, 0)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 611 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 612 | dword = INREG(AUD_PWRST); |
| 613 | printf("AUD_PWRST device power state\t\t%s\n", |
| 614 | power_state[BITS(dword, 5, 4)]); |
| 615 | printf("AUD_PWRST device power state setting\t%s\n", |
| 616 | power_state[BITS(dword, 1, 0)]); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 617 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 618 | dword = INREG(AUD_SUPPWR); |
| 619 | printf("AUD_SUPPWR support D0\t\t\t%lu\n", BIT(dword, 0)); |
| 620 | printf("AUD_SUPPWR support D1\t\t\t%lu\n", BIT(dword, 1)); |
| 621 | printf("AUD_SUPPWR support D2\t\t\t%lu\n", BIT(dword, 2)); |
| 622 | printf("AUD_SUPPWR support D3\t\t\t%lu\n", BIT(dword, 3)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 623 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 624 | dword = INREG(AUD_OUT_CWCAP); |
| 625 | printf("AUD_OUT_CWCAP widget type\t\t0x%lx\n", BITS(dword, 23, 20)); |
| 626 | printf("AUD_OUT_CWCAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16)); |
| 627 | printf("AUD_OUT_CWCAP channel count\t\t%lu\n", |
| 628 | BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1); |
| 629 | printf("AUD_OUT_CWCAP L-R swap\t\t\t%lu\n", BIT(dword, 11)); |
| 630 | printf("AUD_OUT_CWCAP power control\t\t%lu\n", BIT(dword, 10)); |
| 631 | printf("AUD_OUT_CWCAP digital\t\t\t%lu\n", BIT(dword, 9)); |
| 632 | printf("AUD_OUT_CWCAP conn list\t\t\t%lu\n", BIT(dword, 8)); |
| 633 | printf("AUD_OUT_CWCAP unsol\t\t\t%lu\n", BIT(dword, 7)); |
| 634 | printf("AUD_OUT_CWCAP mute\t\t\t%lu\n", BIT(dword, 5)); |
| 635 | printf("AUD_OUT_CWCAP format override\t\t%lu\n", BIT(dword, 4)); |
| 636 | printf("AUD_OUT_CWCAP amp param override\t%lu\n", BIT(dword, 3)); |
| 637 | printf("AUD_OUT_CWCAP out amp present\t\t%lu\n", BIT(dword, 2)); |
| 638 | printf("AUD_OUT_CWCAP in amp present\t\t%lu\n", BIT(dword, 1)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 639 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 640 | dword = INREG(AUD_OUT_DIG_CNVT); |
| 641 | printf("AUD_OUT_DIG_CNVT SPDIF category\t\t0x%lx\n", BITS(dword, 14, 8)); |
| 642 | printf("AUD_OUT_DIG_CNVT SPDIF level\t\t%lu\n", BIT(dword, 7)); |
| 643 | printf("AUD_OUT_DIG_CNVT professional\t\t%lu\n", BIT(dword, 6)); |
| 644 | printf("AUD_OUT_DIG_CNVT non PCM\t\t%lu\n", BIT(dword, 5)); |
| 645 | printf("AUD_OUT_DIG_CNVT copyright asserted\t%lu\n", BIT(dword, 4)); |
| 646 | printf("AUD_OUT_DIG_CNVT filter preemphasis\t%lu\n", BIT(dword, 3)); |
| 647 | printf("AUD_OUT_DIG_CNVT validity config\t%lu\n", BIT(dword, 2)); |
| 648 | printf("AUD_OUT_DIG_CNVT validity flag\t\t%lu\n", BIT(dword, 1)); |
| 649 | printf("AUD_OUT_DIG_CNVT digital enable\t\t%lu\n", BIT(dword, 0)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 650 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 651 | dword = INREG(AUD_OUT_CH_STR); |
| 652 | printf("AUD_OUT_CH_STR stream id\t\t0x%lx\n", BITS(dword, 7, 4)); |
| 653 | printf("AUD_OUT_CH_STR lowest channel\t\t%lu\n", BITS(dword, 3, 0)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 654 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 655 | dword = INREG(AUD_OUT_STR_DESC); |
| 656 | printf("AUD_OUT_STR_DESC stream channels\t%lu\n", BITS(dword, 3, 0) + 1); |
| 657 | printf("AUD_OUT_STR_DESC Bits per Sample\t[%#lx] %s\n", |
| 658 | BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4))); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 659 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 660 | dword = INREG(AUD_PINW_CAP); |
| 661 | printf("AUD_PINW_CAP widget type\t\t0x%lx\n", BITS(dword, 23, 20)); |
| 662 | printf("AUD_PINW_CAP sample delay\t\t0x%lx\n", BITS(dword, 19, 16)); |
| 663 | printf("AUD_PINW_CAP channel count\t\t%lu\n", |
| 664 | BITS(dword, 15, 13) * 2 + BIT(dword, 0) + 1); |
| 665 | printf("AUD_PINW_CAP HDCP\t\t\t%lu\n", BIT(dword, 12)); |
| 666 | printf("AUD_PINW_CAP L-R swap\t\t\t%lu\n", BIT(dword, 11)); |
| 667 | printf("AUD_PINW_CAP power control\t\t%lu\n", BIT(dword, 10)); |
| 668 | printf("AUD_PINW_CAP digital\t\t\t%lu\n", BIT(dword, 9)); |
| 669 | printf("AUD_PINW_CAP conn list\t\t\t%lu\n", BIT(dword, 8)); |
| 670 | printf("AUD_PINW_CAP unsol\t\t\t%lu\n", BIT(dword, 7)); |
| 671 | printf("AUD_PINW_CAP mute\t\t\t%lu\n", BIT(dword, 5)); |
| 672 | printf("AUD_PINW_CAP format override\t\t%lu\n", BIT(dword, 4)); |
| 673 | printf("AUD_PINW_CAP amp param override\t\t%lu\n", BIT(dword, 3)); |
| 674 | printf("AUD_PINW_CAP out amp present\t\t%lu\n", BIT(dword, 2)); |
| 675 | printf("AUD_PINW_CAP in amp present\t\t%lu\n", BIT(dword, 1)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 676 | |
| 677 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 678 | dword = INREG(AUD_PIN_CAP); |
| 679 | printf("AUD_PIN_CAP EAPD\t\t\t%lu\n", BIT(dword, 16)); |
| 680 | printf("AUD_PIN_CAP HDMI\t\t\t%lu\n", BIT(dword, 7)); |
| 681 | printf("AUD_PIN_CAP output\t\t\t%lu\n", BIT(dword, 4)); |
| 682 | printf("AUD_PIN_CAP presence detect\t\t%lu\n", BIT(dword, 2)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 683 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 684 | dword = INREG(AUD_PINW_CNTR); |
| 685 | printf("AUD_PINW_CNTR mute status\t\t%lu\n", BIT(dword, 8)); |
| 686 | printf("AUD_PINW_CNTR out enable\t\t%lu\n", BIT(dword, 6)); |
| 687 | printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8)); |
| 688 | printf("AUD_PINW_CNTR amp mute status\t\t%lu\n", BIT(dword, 8)); |
| 689 | printf("AUD_PINW_CNTR stream type\t\t[0x%lx] %s\n", |
| 690 | BITS(dword, 2, 0), |
| 691 | OPNAME(stream_type, BITS(dword, 2, 0))); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 692 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 693 | dword = INREG(AUD_PINW_UNSOLRESP); |
| 694 | printf("AUD_PINW_UNSOLRESP enable unsol resp\t%lu\n", BIT(dword, 31)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 695 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 696 | dword = INREG(AUD_CNTL_ST); |
| 697 | printf("AUD_CNTL_ST DIP audio enabled\t\t%lu\n", BIT(dword, 21)); |
| 698 | printf("AUD_CNTL_ST DIP ACP enabled\t\t%lu\n", BIT(dword, 22)); |
| 699 | printf("AUD_CNTL_ST DIP ISRCx enabled\t\t%lu\n", BIT(dword, 23)); |
| 700 | printf("AUD_CNTL_ST DIP port select\t\t[0x%lx] %s\n", |
| 701 | BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]); |
| 702 | printf("AUD_CNTL_ST DIP buffer index\t\t[0x%lx] %s\n", |
| 703 | BITS(dword, 20, 18), OPNAME(dip_index, BITS(dword, 20, 18))); |
| 704 | printf("AUD_CNTL_ST DIP trans freq\t\t[0x%lx] %s\n", |
| 705 | BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]); |
| 706 | printf("AUD_CNTL_ST DIP address\t\t\t%lu\n", BITS(dword, 3, 0)); |
| 707 | printf("AUD_CNTL_ST CP ready\t\t\t%lu\n", BIT(dword, 15)); |
| 708 | printf("AUD_CNTL_ST ELD valid\t\t\t%lu\n", BIT(dword, 14)); |
| 709 | printf("AUD_CNTL_ST ELD ack\t\t\t%lu\n", BIT(dword, 4)); |
| 710 | printf("AUD_CNTL_ST ELD bufsize\t\t\t%lu\n", BITS(dword, 13, 9)); |
| 711 | printf("AUD_CNTL_ST ELD address\t\t\t%lu\n", BITS(dword, 8, 5)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 712 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 713 | dword = INREG(AUD_HDMIW_STATUS); |
| 714 | printf("AUD_HDMIW_STATUS CDCLK/DOTCLK underrun\t%lu\n", BIT(dword, 31)); |
| 715 | printf("AUD_HDMIW_STATUS CDCLK/DOTCLK overrun\t%lu\n", BIT(dword, 30)); |
| 716 | printf("AUD_HDMIW_STATUS BCLK/CDCLK underrun\t%lu\n", BIT(dword, 29)); |
| 717 | printf("AUD_HDMIW_STATUS BCLK/CDCLK overrun\t%lu\n", BIT(dword, 28)); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 718 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 719 | dword = INREG(AUD_CONV_CHCNT); |
| 720 | printf("AUD_CONV_CHCNT HDMI HBR enabled\t\t%lu\n", BITS(dword, 15, 14)); |
| 721 | printf("AUD_CONV_CHCNT HDMI channel count\t%lu\n", BITS(dword, 11, 8) + 1); |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 722 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 723 | printf("AUD_CONV_CHCNT HDMI channel mapping:\n"); |
| 724 | for (i = 0; i < 8; i++) { |
| 725 | OUTREG(AUD_CONV_CHCNT, i); |
| 726 | dword = INREG(AUD_CONV_CHCNT); |
| 727 | printf("\t\t\t\t\t[0x%x] %u => %lu\n", dword, i, BITS(dword, 7, 4)); |
| 728 | } |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 729 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 730 | printf("AUD_HDMIW_HDMIEDID HDMI ELD:\n\t"); |
| 731 | dword = INREG(AUD_CNTL_ST); |
| 732 | dword &= ~BITMASK(8, 5); |
| 733 | OUTREG(AUD_CNTL_ST, dword); |
| 734 | for (i = 0; i < BITS(dword, 14, 10) / 4; i++) |
| 735 | printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID))); |
| 736 | printf("\n"); |
Wu Fengguang | f32aecb | 2011-11-12 11:12:50 +0800 | [diff] [blame] | 737 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 738 | printf("AUD_HDMIW_INFOFR HDMI audio Infoframe:\n\t"); |
| 739 | dword = INREG(AUD_CNTL_ST); |
| 740 | dword &= ~BITMASK(20, 18); |
| 741 | dword &= ~BITMASK(3, 0); |
| 742 | OUTREG(AUD_CNTL_ST, dword); |
| 743 | for (i = 0; i < 8; i++) |
| 744 | printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR))); |
| 745 | printf("\n"); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 746 | } |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 747 | |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 748 | #undef AUD_RID |
| 749 | #undef AUD_VID_DID |
| 750 | #undef AUD_PWRST |
| 751 | #undef AUD_OUT_CH_STR |
| 752 | #undef AUD_HDMIW_STATUS |
| 753 | |
| 754 | /* |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 755 | * CougarPoint registers |
| 756 | */ |
Wu Fengguang | 97d2031 | 2011-11-12 11:12:45 +0800 | [diff] [blame] | 757 | #define DP_CTL_B 0xE4100 |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 758 | #define DP_CTL_C 0xE4200 |
| 759 | #define DP_AUX_CTL_C 0xE4210 |
| 760 | #define DP_AUX_TST_C 0xE4228 |
| 761 | #define SPORT_DDI_CRC_C 0xE4250 |
| 762 | #define SPORT_DDI_CRC_R 0xE4264 |
| 763 | #define DP_CTL_D 0xE4300 |
| 764 | #define DP_AUX_CTL_D 0xE4310 |
| 765 | #define DP_AUX_TST_D 0xE4328 |
| 766 | #define SPORT_DDI_CRC_CTL_D 0xE4350 |
| 767 | #define AUD_CONFIG_A 0xE5000 |
| 768 | #define AUD_MISC_CTRL_A 0xE5010 |
| 769 | #define AUD_VID_DID 0xE5020 |
| 770 | #define AUD_RID 0xE5024 |
| 771 | #define AUD_CTS_ENABLE_A 0xE5028 |
| 772 | #define AUD_PWRST 0xE504C |
| 773 | #define AUD_HDMIW_HDMIEDID_A 0xE5050 |
| 774 | #define AUD_HDMIW_INFOFR_A 0xE5054 |
| 775 | #define AUD_PORT_EN_HD_CFG 0xE507C |
| 776 | #define AUD_OUT_DIG_CNVT_A 0xE5080 |
| 777 | #define AUD_OUT_STR_DESC_A 0xE5084 |
| 778 | #define AUD_OUT_CH_STR 0xE5088 |
| 779 | #define AUD_PINW_CONNLNG_LIST 0xE50A8 |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 780 | #define AUD_PINW_CONNLNG_SEL 0xE50AC |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 781 | #define AUD_CNTL_ST_A 0xE50B4 |
| 782 | #define AUD_CNTRL_ST2 0xE50C0 |
| 783 | #define AUD_CNTRL_ST3 0xE50C4 |
| 784 | #define AUD_HDMIW_STATUS 0xE50D4 |
| 785 | #define AUD_CONFIG_B 0xE5100 |
| 786 | #define AUD_MISC_CTRL_B 0xE5110 |
| 787 | #define AUD_CTS_ENABLE_B 0xE5128 |
| 788 | #define AUD_HDMIW_HDMIEDID_B 0xE5150 |
| 789 | #define AUD_HDMIW_INFOFR_B 0xE5154 |
| 790 | #define AUD_OUT_DIG_CNVT_B 0xE5180 |
| 791 | #define AUD_OUT_STR_DESC_B 0xE5184 |
| 792 | #define AUD_CNTL_ST_B 0xE51B4 |
| 793 | #define AUD_CONFIG_C 0xE5200 |
| 794 | #define AUD_MISC_CTRL_C 0xE5210 |
| 795 | #define AUD_CTS_ENABLE_C 0xE5228 |
| 796 | #define AUD_HDMIW_HDMIEDID_C 0xE5250 |
| 797 | #define AUD_HDMIW_INFOFR_C 0xE5254 |
| 798 | #define AUD_OUT_DIG_CNVT_C 0xE5280 |
| 799 | #define AUD_OUT_STR_DESC_C 0xE5284 |
| 800 | #define AUD_CNTL_ST_C 0xE52B4 |
| 801 | #define AUD_CONFIG_D 0xE5300 |
| 802 | #define AUD_MISC_CTRL_D 0xE5310 |
| 803 | #define AUD_CTS_ENABLE_D 0xE5328 |
| 804 | #define AUD_HDMIW_HDMIEDID_D 0xE5350 |
| 805 | #define AUD_HDMIW_INFOFR_D 0xE5354 |
| 806 | #define AUD_OUT_DIG_CNVT_D 0xE5380 |
| 807 | #define AUD_OUT_STR_DESC_D 0xE5384 |
| 808 | #define AUD_CNTL_ST_D 0xE53B4 |
| 809 | |
Wu Fengguang | e321f13 | 2011-11-12 11:12:52 +0800 | [diff] [blame] | 810 | #define VIDEO_DIP_CTL_A 0xE0200 |
| 811 | #define VIDEO_DIP_CTL_B 0xE1200 |
| 812 | #define VIDEO_DIP_CTL_C 0xE2200 |
| 813 | #define VIDEO_DIP_CTL_D 0xE3200 |
| 814 | |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 815 | |
| 816 | static void dump_cpt(void) |
| 817 | { |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 818 | uint32_t dword; |
| 819 | int i; |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 820 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 821 | dump_reg(HDMIB, "sDVO/HDMI Port B Control"); |
| 822 | dump_reg(HDMIC, "HDMI Port C Control"); |
| 823 | dump_reg(HDMID, "HDMI Port D Control"); |
| 824 | dump_reg(DP_CTL_B, "DisplayPort B Control"); |
| 825 | dump_reg(DP_CTL_C, "DisplayPort C Control"); |
| 826 | dump_reg(DP_CTL_D, "DisplayPort D Control"); |
| 827 | dump_reg(TRANS_DP_CTL_A, "Transcoder A DisplayPort Control"); |
| 828 | dump_reg(TRANS_DP_CTL_B, "Transcoder B DisplayPort Control"); |
| 829 | dump_reg(TRANS_DP_CTL_C, "Transcoder C DisplayPort Control"); |
| 830 | dump_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A"); |
| 831 | dump_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B"); |
| 832 | dump_reg(AUD_CONFIG_C, "Audio Configuration - Transcoder C"); |
| 833 | dump_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A"); |
| 834 | dump_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B"); |
| 835 | dump_reg(AUD_CTS_ENABLE_C, "Audio CTS Programming Enable - Transcoder C"); |
| 836 | dump_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A"); |
| 837 | dump_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B"); |
| 838 | dump_reg(AUD_MISC_CTRL_C, "Audio MISC Control for Transcoder C"); |
| 839 | dump_reg(AUD_VID_DID, "Audio Vendor ID / Device ID"); |
| 840 | dump_reg(AUD_RID, "Audio Revision ID"); |
| 841 | dump_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)"); |
| 842 | dump_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config"); |
| 843 | dump_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A"); |
| 844 | dump_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B"); |
| 845 | dump_reg(AUD_OUT_DIG_CNVT_C, "Audio Digital Converter - Conv C"); |
| 846 | dump_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID"); |
| 847 | dump_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A"); |
| 848 | dump_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B"); |
| 849 | dump_reg(AUD_OUT_STR_DESC_C, "Audio Stream Descriptor Format - Conv C"); |
| 850 | dump_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List"); |
| 851 | dump_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select"); |
| 852 | dump_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A"); |
| 853 | dump_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B"); |
| 854 | dump_reg(AUD_CNTL_ST_C, "Audio Control State Register - Transcoder C"); |
| 855 | dump_reg(AUD_CNTRL_ST2, "Audio Control State 2"); |
| 856 | dump_reg(AUD_CNTRL_ST3, "Audio Control State 3"); |
| 857 | dump_reg(AUD_HDMIW_STATUS, "Audio HDMI Status"); |
| 858 | dump_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A"); |
| 859 | dump_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B"); |
| 860 | dump_reg(AUD_HDMIW_HDMIEDID_C, "HDMI Data EDID Block - Transcoder C"); |
| 861 | dump_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A"); |
| 862 | dump_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B"); |
| 863 | dump_reg(AUD_HDMIW_INFOFR_C, "Audio Widget Data Island Packet - Transcoder C"); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 864 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 865 | printf("\nDetails:\n\n"); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 866 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 867 | dword = INREG(VIDEO_DIP_CTL_A); |
| 868 | printf("VIDEO_DIP_CTL_A Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)), |
| 869 | printf("VIDEO_DIP_CTL_A GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)), |
| 870 | printf("VIDEO_DIP_CTL_A Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21)); |
| 871 | printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22)); |
| 872 | printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23)); |
| 873 | printf("VIDEO_DIP_CTL_A Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24)); |
| 874 | printf("VIDEO_DIP_CTL_A Video_DIP_buffer_index\t\t\t[0x%lx] %s\n", |
| 875 | BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]); |
| 876 | printf("VIDEO_DIP_CTL_A Video_DIP_frequency\t\t\t[0x%lx] %s\n", |
| 877 | BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]); |
| 878 | printf("VIDEO_DIP_CTL_A Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8)); |
| 879 | printf("VIDEO_DIP_CTL_A Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0)); |
Wu Fengguang | e321f13 | 2011-11-12 11:12:52 +0800 | [diff] [blame] | 880 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 881 | dword = INREG(VIDEO_DIP_CTL_B); |
| 882 | printf("VIDEO_DIP_CTL_B Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)), |
| 883 | printf("VIDEO_DIP_CTL_B GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)), |
| 884 | printf("VIDEO_DIP_CTL_B Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21)); |
| 885 | printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22)); |
| 886 | printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23)); |
| 887 | printf("VIDEO_DIP_CTL_B Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24)); |
| 888 | printf("VIDEO_DIP_CTL_B Video_DIP_buffer_index\t\t\t[0x%lx] %s\n", |
| 889 | BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]); |
| 890 | printf("VIDEO_DIP_CTL_B Video_DIP_frequency\t\t\t[0x%lx] %s\n", |
| 891 | BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]); |
| 892 | printf("VIDEO_DIP_CTL_B Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8)); |
| 893 | printf("VIDEO_DIP_CTL_B Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0)); |
Wu Fengguang | e321f13 | 2011-11-12 11:12:52 +0800 | [diff] [blame] | 894 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 895 | dword = INREG(VIDEO_DIP_CTL_C); |
| 896 | printf("VIDEO_DIP_CTL_C Enable_Graphics_DIP\t\t\t%ld\n", BIT(dword, 31)), |
| 897 | printf("VIDEO_DIP_CTL_C GCP_DIP_enable\t\t\t\t%ld\n", BIT(dword, 25)), |
| 898 | printf("VIDEO_DIP_CTL_C Video_DIP_type_enable AVI\t\t%lu\n", BIT(dword, 21)); |
| 899 | printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Vendor\t\t%lu\n", BIT(dword, 22)); |
| 900 | printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Gamut\t\t%lu\n", BIT(dword, 23)); |
| 901 | printf("VIDEO_DIP_CTL_C Video_DIP_type_enable Source \t\t%lu\n", BIT(dword, 24)); |
| 902 | printf("VIDEO_DIP_CTL_C Video_DIP_buffer_index\t\t\t[0x%lx] %s\n", |
| 903 | BITS(dword, 20, 19), video_dip_index[BITS(dword, 20, 19)]); |
| 904 | printf("VIDEO_DIP_CTL_C Video_DIP_frequency\t\t\t[0x%lx] %s\n", |
| 905 | BITS(dword, 17, 16), video_dip_trans[BITS(dword, 17, 16)]); |
| 906 | printf("VIDEO_DIP_CTL_C Video_DIP_buffer_size\t\t\t%lu\n", BITS(dword, 11, 8)); |
| 907 | printf("VIDEO_DIP_CTL_C Video_DIP_access_address\t\t%lu\n", BITS(dword, 3, 0)); |
Wu Fengguang | e321f13 | 2011-11-12 11:12:52 +0800 | [diff] [blame] | 908 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 909 | dword = INREG(AUD_VID_DID); |
| 910 | printf("AUD_VID_DID vendor id\t\t\t\t\t0x%x\n", dword >> 16); |
| 911 | printf("AUD_VID_DID device id\t\t\t\t\t0x%x\n", dword & 0xffff); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 912 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 913 | dword = INREG(AUD_RID); |
| 914 | printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20)); |
| 915 | printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16)); |
| 916 | printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8)); |
| 917 | printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 918 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 919 | dword = INREG(HDMIB); |
| 920 | printf("HDMIB Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE)); |
| 921 | printf("HDMIB Transcoder_Select\t\t\t\t\t[0x%lx] %s\n", |
| 922 | BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]); |
| 923 | printf("HDMIB sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7)); |
| 924 | printf("HDMIB HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5)); |
| 925 | printf("HDMIB SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", BIT(dword, 23)); |
| 926 | printf("HDMIB Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2)); |
| 927 | printf("HDMIB Encoding\t\t\t\t\t\t[0x%lx] %s\n", |
| 928 | BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]); |
| 929 | printf("HDMIB HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI"); |
| 930 | printf("HDMIB Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 931 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 932 | dword = INREG(HDMIC); |
| 933 | printf("HDMIC Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE)); |
| 934 | printf("HDMIC Transcoder_Select\t\t\t\t\t[0x%lx] %s\n", |
| 935 | BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]); |
| 936 | printf("HDMIC sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7)); |
| 937 | printf("HDMIC HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5)); |
| 938 | printf("HDMIC SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", BIT(dword, 23)); |
| 939 | printf("HDMIC Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2)); |
| 940 | printf("HDMIC Encoding\t\t\t\t\t\t[0x%lx] %s\n", |
| 941 | BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]); |
| 942 | printf("HDMIC HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI"); |
| 943 | printf("HDMIC Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 944 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 945 | dword = INREG(HDMID); |
| 946 | printf("HDMID Port_Enable\t\t\t\t\t%u\n", !!(dword & SDVO_ENABLE)); |
| 947 | printf("HDMID Transcoder_Select\t\t\t\t\t[0x%lx] %s\n", |
| 948 | BITS(dword, 30, 29), transcoder_select[BITS(dword, 30, 29)]); |
| 949 | printf("HDMID sDVO_Border_Enable\t\t\t\t%lu\n", BIT(dword, 7)); |
| 950 | printf("HDMID HDCP_Port_Select\t\t\t\t\t%lu\n", BIT(dword, 5)); |
| 951 | printf("HDMID SDVO_HPD_Interrupt_Enable\t\t\t\t%lu\n", BIT(dword, 23)); |
| 952 | printf("HDMID Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2)); |
| 953 | printf("HDMID Encoding\t\t\t\t\t\t[0x%lx] %s\n", |
| 954 | BITS(dword, 11, 10), sdvo_hdmi_encoding[BITS(dword, 11, 10)]); |
| 955 | printf("HDMID HDMI_or_DVI_Select\t\t\t\t%s\n", BIT(dword, 9) ? "HDMI" : "DVI"); |
| 956 | printf("HDMID Audio_Output_Enable\t\t\t\t%u\n", !!(dword & SDVO_AUDIO_ENABLE)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 957 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 958 | dword = INREG(DP_CTL_B); |
| 959 | printf("DP_CTL_B DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31)); |
| 960 | printf("DP_CTL_B Port_Width_Selection\t\t\t\t[0x%lx] %s\n", |
| 961 | BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]); |
| 962 | printf("DP_CTL_B Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2)); |
| 963 | printf("DP_CTL_B HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5)); |
| 964 | printf("DP_CTL_B Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 965 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 966 | dword = INREG(DP_CTL_C); |
| 967 | printf("DP_CTL_C DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31)); |
| 968 | printf("DP_CTL_C Port_Width_Selection\t\t\t\t[0x%lx] %s\n", |
| 969 | BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]); |
| 970 | printf("DP_CTL_C Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2)); |
| 971 | printf("DP_CTL_C HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5)); |
| 972 | printf("DP_CTL_C Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 973 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 974 | dword = INREG(DP_CTL_D); |
| 975 | printf("DP_CTL_D DisplayPort_Enable\t\t\t\t%lu\n", BIT(dword, 31)); |
| 976 | printf("DP_CTL_D Port_Width_Selection\t\t\t\t[0x%lx] %s\n", |
| 977 | BITS(dword, 21, 19), dp_port_width[BITS(dword, 21, 19)]); |
| 978 | printf("DP_CTL_D Port_Detected\t\t\t\t\t%lu\n", BIT(dword, 2)); |
| 979 | printf("DP_CTL_D HDCP_Port_Select\t\t\t\t%lu\n", BIT(dword, 5)); |
| 980 | printf("DP_CTL_D Audio_Output_Enable\t\t\t\t%lu\n", BIT(dword, 6)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 981 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 982 | dword = INREG(AUD_CONFIG_A); |
| 983 | printf("AUD_CONFIG_A N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29), |
| 984 | n_index_value[BIT(dword, 29)]); |
| 985 | printf("AUD_CONFIG_A N_programming_enable\t\t\t%lu\n", BIT(dword, 28)); |
| 986 | printf("AUD_CONFIG_A Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20)); |
| 987 | printf("AUD_CONFIG_A Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4)); |
| 988 | printf("AUD_CONFIG_A Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16), |
| 989 | OPNAME(pixel_clock, BITS(dword, 19, 16))); |
| 990 | printf("AUD_CONFIG_A Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3)); |
| 991 | dword = INREG(AUD_CONFIG_B); |
| 992 | printf("AUD_CONFIG_B N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29), |
| 993 | n_index_value[BIT(dword, 29)]); |
| 994 | printf("AUD_CONFIG_B N_programming_enable\t\t\t%lu\n", BIT(dword, 28)); |
| 995 | printf("AUD_CONFIG_B Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20)); |
| 996 | printf("AUD_CONFIG_B Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4)); |
| 997 | printf("AUD_CONFIG_B Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16), |
| 998 | OPNAME(pixel_clock, BITS(dword, 19, 16))); |
| 999 | printf("AUD_CONFIG_B Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3)); |
| 1000 | dword = INREG(AUD_CONFIG_C); |
| 1001 | printf("AUD_CONFIG_C N_index_value\t\t\t\t[0x%lx] %s\n", BIT(dword, 29), |
| 1002 | n_index_value[BIT(dword, 29)]); |
| 1003 | printf("AUD_CONFIG_C N_programming_enable\t\t\t%lu\n", BIT(dword, 28)); |
| 1004 | printf("AUD_CONFIG_C Upper_N_value\t\t\t\t0x%02lx\n", BITS(dword, 27, 20)); |
| 1005 | printf("AUD_CONFIG_C Lower_N_value\t\t\t\t0x%03lx\n", BITS(dword, 15, 4)); |
| 1006 | printf("AUD_CONFIG_C Pixel_Clock_HDMI\t\t\t\t[0x%lx] %s\n", BITS(dword, 19, 16), |
| 1007 | OPNAME(pixel_clock, BITS(dword, 19, 16))); |
| 1008 | printf("AUD_CONFIG_C Disable_NCTS\t\t\t\t%lu\n", BIT(dword, 3)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1009 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1010 | dword = INREG(AUD_CTS_ENABLE_A); |
| 1011 | printf("AUD_CTS_ENABLE_A Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20)); |
| 1012 | printf("AUD_CTS_ENABLE_A CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M"); |
| 1013 | printf("AUD_CTS_ENABLE_A CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0)); |
| 1014 | dword = INREG(AUD_CTS_ENABLE_B); |
| 1015 | printf("AUD_CTS_ENABLE_B Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20)); |
| 1016 | printf("AUD_CTS_ENABLE_B CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M"); |
| 1017 | printf("AUD_CTS_ENABLE_B CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0)); |
| 1018 | dword = INREG(AUD_CTS_ENABLE_C); |
| 1019 | printf("AUD_CTS_ENABLE_C Enable_CTS_or_M_programming\t\t%lu\n", BIT(dword, 20)); |
| 1020 | printf("AUD_CTS_ENABLE_C CTS_M value Index\t\t\t%s\n", BIT(dword, 21) ? "CTS" : "M"); |
| 1021 | printf("AUD_CTS_ENABLE_C CTS_programming\t\t\t%#lx\n", BITS(dword, 19, 0)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1022 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1023 | dword = INREG(AUD_MISC_CTRL_A); |
| 1024 | printf("AUD_MISC_CTRL_A Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2)); |
| 1025 | printf("AUD_MISC_CTRL_A Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8)); |
| 1026 | printf("AUD_MISC_CTRL_A Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4)); |
| 1027 | printf("AUD_MISC_CTRL_A Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1)); |
| 1028 | dword = INREG(AUD_MISC_CTRL_B); |
| 1029 | printf("AUD_MISC_CTRL_B Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2)); |
| 1030 | printf("AUD_MISC_CTRL_B Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8)); |
| 1031 | printf("AUD_MISC_CTRL_B Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4)); |
| 1032 | printf("AUD_MISC_CTRL_B Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1)); |
| 1033 | dword = INREG(AUD_MISC_CTRL_C); |
| 1034 | printf("AUD_MISC_CTRL_C Sample_Fabrication_EN_bit\t\t%lu\n", BIT(dword, 2)); |
| 1035 | printf("AUD_MISC_CTRL_C Sample_present_Disable\t\t\t%lu\n", BIT(dword, 8)); |
| 1036 | printf("AUD_MISC_CTRL_C Output_Delay\t\t\t\t%lu\n", BITS(dword, 7, 4)); |
| 1037 | printf("AUD_MISC_CTRL_C Pro_Allowed\t\t\t\t%lu\n", BIT(dword, 1)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1038 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1039 | dword = INREG(AUD_PWRST); |
| 1040 | printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 27, 26)]); |
| 1041 | printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 25, 24)]); |
| 1042 | printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]); |
| 1043 | printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]); |
| 1044 | printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]); |
| 1045 | printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]); |
| 1046 | printf("AUD_PWRST ConvC_Widget_PwrSt_Curr \t%s\n", power_state[BITS(dword, 23, 22)]); |
| 1047 | printf("AUD_PWRST ConvC_Widget_PwrSt_Req \t%s\n", power_state[BITS(dword, 21, 20)]); |
| 1048 | printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]); |
| 1049 | printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]); |
| 1050 | printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]); |
| 1051 | printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]); |
| 1052 | printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]); |
| 1053 | printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1054 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1055 | dword = INREG(AUD_PORT_EN_HD_CFG); |
| 1056 | printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0)); |
| 1057 | printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1)); |
| 1058 | printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", BIT(dword, 2)); |
| 1059 | printf("AUD_PORT_EN_HD_CFG ConvertorA_Stream_ID\t\t%lu\n", BITS(dword, 7, 4)); |
| 1060 | printf("AUD_PORT_EN_HD_CFG ConvertorB_Stream_ID\t\t%lu\n", BITS(dword, 11, 8)); |
| 1061 | printf("AUD_PORT_EN_HD_CFG ConvertorC_Stream_ID\t\t%lu\n", BITS(dword, 15, 12)); |
| 1062 | printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16)); |
| 1063 | printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17)); |
| 1064 | printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18)); |
| 1065 | printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20)); |
| 1066 | printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21)); |
| 1067 | printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1068 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1069 | dword = INREG(AUD_OUT_DIG_CNVT_A); |
| 1070 | printf("AUD_OUT_DIG_CNVT_A V\t\t\t\t\t%lu\n", BIT(dword, 1)); |
| 1071 | printf("AUD_OUT_DIG_CNVT_A VCFG\t\t\t\t%lu\n", BIT(dword, 2)); |
| 1072 | printf("AUD_OUT_DIG_CNVT_A PRE\t\t\t\t\t%lu\n", BIT(dword, 3)); |
| 1073 | printf("AUD_OUT_DIG_CNVT_A Copy\t\t\t\t%lu\n", BIT(dword, 4)); |
| 1074 | printf("AUD_OUT_DIG_CNVT_A NonAudio\t\t\t\t%lu\n", BIT(dword, 5)); |
| 1075 | printf("AUD_OUT_DIG_CNVT_A PRO\t\t\t\t\t%lu\n", BIT(dword, 6)); |
| 1076 | printf("AUD_OUT_DIG_CNVT_A Level\t\t\t\t%lu\n", BIT(dword, 7)); |
| 1077 | printf("AUD_OUT_DIG_CNVT_A Category_Code\t\t\t%lu\n", BITS(dword, 14, 8)); |
| 1078 | printf("AUD_OUT_DIG_CNVT_A Lowest_Channel_Number\t\t%lu\n", BITS(dword, 19, 16)); |
| 1079 | printf("AUD_OUT_DIG_CNVT_A Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1080 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1081 | dword = INREG(AUD_OUT_DIG_CNVT_B); |
| 1082 | printf("AUD_OUT_DIG_CNVT_B V\t\t\t\t\t%lu\n", BIT(dword, 1)); |
| 1083 | printf("AUD_OUT_DIG_CNVT_B VCFG\t\t\t\t%lu\n", BIT(dword, 2)); |
| 1084 | printf("AUD_OUT_DIG_CNVT_B PRE\t\t\t\t\t%lu\n", BIT(dword, 3)); |
| 1085 | printf("AUD_OUT_DIG_CNVT_B Copy\t\t\t\t%lu\n", BIT(dword, 4)); |
| 1086 | printf("AUD_OUT_DIG_CNVT_B NonAudio\t\t\t\t%lu\n", BIT(dword, 5)); |
| 1087 | printf("AUD_OUT_DIG_CNVT_B PRO\t\t\t\t\t%lu\n", BIT(dword, 6)); |
| 1088 | printf("AUD_OUT_DIG_CNVT_B Level\t\t\t\t%lu\n", BIT(dword, 7)); |
| 1089 | printf("AUD_OUT_DIG_CNVT_B Category_Code\t\t\t%lu\n", BITS(dword, 14, 8)); |
| 1090 | printf("AUD_OUT_DIG_CNVT_B Lowest_Channel_Number\t\t%lu\n", BITS(dword, 19, 16)); |
| 1091 | printf("AUD_OUT_DIG_CNVT_B Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1092 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1093 | dword = INREG(AUD_OUT_DIG_CNVT_C); |
| 1094 | printf("AUD_OUT_DIG_CNVT_C V\t\t\t\t\t%lu\n", BIT(dword, 1)); |
| 1095 | printf("AUD_OUT_DIG_CNVT_C VCFG\t\t\t\t%lu\n", BIT(dword, 2)); |
| 1096 | printf("AUD_OUT_DIG_CNVT_C PRE\t\t\t\t\t%lu\n", BIT(dword, 3)); |
| 1097 | printf("AUD_OUT_DIG_CNVT_C Copy\t\t\t\t%lu\n", BIT(dword, 4)); |
| 1098 | printf("AUD_OUT_DIG_CNVT_C NonAudio\t\t\t\t%lu\n", BIT(dword, 5)); |
| 1099 | printf("AUD_OUT_DIG_CNVT_C PRO\t\t\t\t\t%lu\n", BIT(dword, 6)); |
| 1100 | printf("AUD_OUT_DIG_CNVT_C Level\t\t\t\t%lu\n", BIT(dword, 7)); |
| 1101 | printf("AUD_OUT_DIG_CNVT_C Category_Code\t\t\t%lu\n", BITS(dword, 14, 8)); |
| 1102 | printf("AUD_OUT_DIG_CNVT_C Lowest_Channel_Number\t\t%lu\n", BITS(dword, 19, 16)); |
| 1103 | printf("AUD_OUT_DIG_CNVT_C Stream_ID\t\t\t\t%lu\n", BITS(dword, 23, 20)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1104 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1105 | printf("AUD_OUT_CH_STR Converter_Channel_MAP PORTB PORTC PORTD\n"); |
| 1106 | for (i = 0; i < 8; i++) { |
| 1107 | OUTREG(AUD_OUT_CH_STR, i | (i << 8) | (i << 16)); |
| 1108 | dword = INREG(AUD_OUT_CH_STR); |
| 1109 | printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n", |
| 1110 | 1 + BITS(dword, 3, 0), |
| 1111 | 1 + BITS(dword, 7, 4), |
| 1112 | 1 + BITS(dword, 15, 12), |
| 1113 | 1 + BITS(dword, 23, 20)); |
| 1114 | } |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1115 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1116 | dword = INREG(AUD_OUT_STR_DESC_A); |
| 1117 | printf("AUD_OUT_STR_DESC_A HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27)); |
| 1118 | printf("AUD_OUT_STR_DESC_A Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1); |
| 1119 | printf("AUD_OUT_STR_DESC_A Bits_per_Sample\t\t\t[%#lx] %s\n", |
| 1120 | BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4))); |
| 1121 | printf("AUD_OUT_STR_DESC_A Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1122 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1123 | dword = INREG(AUD_OUT_STR_DESC_B); |
| 1124 | printf("AUD_OUT_STR_DESC_B HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27)); |
| 1125 | printf("AUD_OUT_STR_DESC_B Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1); |
| 1126 | printf("AUD_OUT_STR_DESC_B Bits_per_Sample\t\t\t[%#lx] %s\n", |
| 1127 | BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4))); |
| 1128 | printf("AUD_OUT_STR_DESC_B Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1129 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1130 | dword = INREG(AUD_OUT_STR_DESC_C); |
| 1131 | printf("AUD_OUT_STR_DESC_C HBR_enable\t\t\t\t%lu\n", BITS(dword, 28, 27)); |
| 1132 | printf("AUD_OUT_STR_DESC_C Convertor_Channel_Count\t\t%lu\n", BITS(dword, 20, 16) + 1); |
| 1133 | printf("AUD_OUT_STR_DESC_C Bits_per_Sample\t\t\t[%#lx] %s\n", |
| 1134 | BITS(dword, 6, 4), OPNAME(bits_per_sample, BITS(dword, 6, 4))); |
| 1135 | printf("AUD_OUT_STR_DESC_C Number_of_Channels_in_a_Stream\t%lu\n", 1 + BITS(dword, 3, 0)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1136 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1137 | dword = INREG(AUD_PINW_CONNLNG_SEL); |
| 1138 | printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_B\t%#lx\n", BITS(dword, 7, 0)); |
| 1139 | printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_C\t%#lx\n", BITS(dword, 15, 8)); |
| 1140 | printf("AUD_PINW_CONNLNG_SEL Connection_select_Control_D\t%#lx\n", BITS(dword, 23, 16)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1141 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1142 | dword = INREG(AUD_CNTL_ST_A); |
| 1143 | printf("AUD_CNTL_ST_A DIP_Port_Select\t\t\t\t[%#lx] %s\n", |
| 1144 | BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]); |
| 1145 | printf("AUD_CNTL_ST_A DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21)); |
| 1146 | printf("AUD_CNTL_ST_A DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22)); |
| 1147 | printf("AUD_CNTL_ST_A DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23)); |
| 1148 | printf("AUD_CNTL_ST_A DIP_transmission_frequency\t\t[0x%lx] %s\n", |
| 1149 | BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]); |
| 1150 | printf("AUD_CNTL_ST_A ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4)); |
| 1151 | printf("AUD_CNTL_ST_A ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1152 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1153 | dword = INREG(AUD_CNTL_ST_B); |
| 1154 | printf("AUD_CNTL_ST_B DIP_Port_Select\t\t\t\t[%#lx] %s\n", |
| 1155 | BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]); |
| 1156 | printf("AUD_CNTL_ST_B DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21)); |
| 1157 | printf("AUD_CNTL_ST_B DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22)); |
| 1158 | printf("AUD_CNTL_ST_B DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23)); |
| 1159 | printf("AUD_CNTL_ST_B DIP_transmission_frequency\t\t[0x%lx] %s\n", |
| 1160 | BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]); |
| 1161 | printf("AUD_CNTL_ST_B ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4)); |
| 1162 | printf("AUD_CNTL_ST_B ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1163 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1164 | dword = INREG(AUD_CNTL_ST_C); |
| 1165 | printf("AUD_CNTL_ST_C DIP_Port_Select\t\t\t\t[%#lx] %s\n", |
| 1166 | BITS(dword, 30, 29), dip_port[BITS(dword, 30, 29)]); |
| 1167 | printf("AUD_CNTL_ST_C DIP_type_enable_status Audio DIP\t\t%lu\n", BIT(dword, 21)); |
| 1168 | printf("AUD_CNTL_ST_C DIP_type_enable_status ACP DIP\t\t%lu\n", BIT(dword, 22)); |
| 1169 | printf("AUD_CNTL_ST_C DIP_type_enable_status Generic 2 DIP\t%lu\n", BIT(dword, 23)); |
| 1170 | printf("AUD_CNTL_ST_C DIP_transmission_frequency\t\t[0x%lx] %s\n", |
| 1171 | BITS(dword, 17, 16), dip_trans[BITS(dword, 17, 16)]); |
| 1172 | printf("AUD_CNTL_ST_C ELD_ACK\t\t\t\t\t%lu\n", BIT(dword, 4)); |
| 1173 | printf("AUD_CNTL_ST_C ELD_buffer_size\t\t\t\t%lu\n", BITS(dword, 14, 10)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1174 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1175 | dword = INREG(AUD_CNTRL_ST2); |
| 1176 | printf("AUD_CNTRL_ST2 CP_ReadyB\t\t\t\t%lu\n", BIT(dword, 1)); |
| 1177 | printf("AUD_CNTRL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0)); |
| 1178 | printf("AUD_CNTRL_ST2 CP_ReadyC\t\t\t\t%lu\n", BIT(dword, 5)); |
| 1179 | printf("AUD_CNTRL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4)); |
| 1180 | printf("AUD_CNTRL_ST2 CP_ReadyD\t\t\t\t%lu\n", BIT(dword, 9)); |
| 1181 | printf("AUD_CNTRL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1182 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1183 | dword = INREG(AUD_CNTRL_ST3); |
| 1184 | printf("AUD_CNTRL_ST3 TransA_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 3)); |
| 1185 | printf("AUD_CNTRL_ST3 TransA_to_Port_Sel\t\t\t[%#lx] %s\n", |
| 1186 | BITS(dword, 2, 0), trans_to_port_sel[BITS(dword, 2, 0)]); |
| 1187 | printf("AUD_CNTRL_ST3 TransB_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 7)); |
| 1188 | printf("AUD_CNTRL_ST3 TransB_to_Port_Sel\t\t\t[%#lx] %s\n", |
| 1189 | BITS(dword, 6, 4), trans_to_port_sel[BITS(dword, 6, 4)]); |
| 1190 | printf("AUD_CNTRL_ST3 TransC_DPT_Audio_Output_En\t\t%lu\n", BIT(dword, 11)); |
| 1191 | printf("AUD_CNTRL_ST3 TransC_to_Port_Sel\t\t\t[%#lx] %s\n", |
| 1192 | BITS(dword, 10, 8), trans_to_port_sel[BITS(dword, 10, 8)]); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1193 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1194 | dword = INREG(AUD_HDMIW_STATUS); |
| 1195 | printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27)); |
| 1196 | printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 26)); |
| 1197 | printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29)); |
| 1198 | printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28)); |
| 1199 | printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31)); |
| 1200 | printf("AUD_HDMIW_STATUS Conv_C_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30)); |
| 1201 | printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25)); |
| 1202 | printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24)); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1203 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1204 | printf("AUD_HDMIW_HDMIEDID_A HDMI ELD:\n\t"); |
| 1205 | dword = INREG(AUD_CNTL_ST_A); |
| 1206 | dword &= ~BITMASK(9, 5); |
| 1207 | OUTREG(AUD_CNTL_ST_A, dword); |
| 1208 | for (i = 0; i < BITS(dword, 14, 10) / 4; i++) |
| 1209 | printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_A))); |
| 1210 | printf("\n"); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1211 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1212 | printf("AUD_HDMIW_HDMIEDID_B HDMI ELD:\n\t"); |
| 1213 | dword = INREG(AUD_CNTL_ST_B); |
| 1214 | dword &= ~BITMASK(9, 5); |
| 1215 | OUTREG(AUD_CNTL_ST_B, dword); |
| 1216 | for (i = 0; i < BITS(dword, 14, 10) / 4; i++) |
| 1217 | printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_B))); |
| 1218 | printf("\n"); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1219 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1220 | printf("AUD_HDMIW_HDMIEDID_C HDMI ELD:\n\t"); |
| 1221 | dword = INREG(AUD_CNTL_ST_C); |
| 1222 | dword &= ~BITMASK(9, 5); |
| 1223 | OUTREG(AUD_CNTL_ST_C, dword); |
| 1224 | for (i = 0; i < BITS(dword, 14, 10) / 4; i++) |
| 1225 | printf("%08x ", htonl(INREG(AUD_HDMIW_HDMIEDID_C))); |
| 1226 | printf("\n"); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1227 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1228 | printf("AUD_HDMIW_INFOFR_A HDMI audio Infoframe:\n\t"); |
| 1229 | dword = INREG(AUD_CNTL_ST_A); |
| 1230 | dword &= ~BITMASK(20, 18); |
| 1231 | dword &= ~BITMASK(3, 0); |
| 1232 | OUTREG(AUD_CNTL_ST_A, dword); |
| 1233 | for (i = 0; i < 8; i++) |
| 1234 | printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_A))); |
| 1235 | printf("\n"); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1236 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1237 | printf("AUD_HDMIW_INFOFR_B HDMI audio Infoframe:\n\t"); |
| 1238 | dword = INREG(AUD_CNTL_ST_B); |
| 1239 | dword &= ~BITMASK(20, 18); |
| 1240 | dword &= ~BITMASK(3, 0); |
| 1241 | OUTREG(AUD_CNTL_ST_B, dword); |
| 1242 | for (i = 0; i < 8; i++) |
| 1243 | printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_B))); |
| 1244 | printf("\n"); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1245 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 1246 | printf("AUD_HDMIW_INFOFR_C HDMI audio Infoframe:\n\t"); |
| 1247 | dword = INREG(AUD_CNTL_ST_C); |
| 1248 | dword &= ~BITMASK(20, 18); |
| 1249 | dword &= ~BITMASK(3, 0); |
| 1250 | OUTREG(AUD_CNTL_ST_C, dword); |
| 1251 | for (i = 0; i < 8; i++) |
| 1252 | printf("%08x ", htonl(INREG(AUD_HDMIW_INFOFR_C))); |
| 1253 | printf("\n"); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 1254 | |
| 1255 | } |
| 1256 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1257 | /* Audio config registers of Ironlake */ |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1258 | #undef AUD_CONFIG_A |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1259 | #undef AUD_CONFIG_B |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1260 | #undef AUD_MISC_CTRL_A |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1261 | #undef AUD_MISC_CTRL_B |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1262 | #undef AUD_VID_DID |
| 1263 | #undef AUD_RID |
| 1264 | #undef AUD_CTS_ENABLE_A |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1265 | #undef AUD_CTS_ENABLE_B |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1266 | #undef AUD_PWRST |
| 1267 | #undef AUD_HDMIW_HDMIEDID_A |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1268 | #undef AUD_HDMIW_HDMIEDID_B |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1269 | #undef AUD_HDMIW_INFOFR_A |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1270 | #undef AUD_HDMIW_INFOFR_B |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1271 | #undef AUD_PORT_EN_HD_CFG |
| 1272 | #undef AUD_OUT_DIG_CNVT_A |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1273 | #undef AUD_OUT_DIG_CNVT_B |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1274 | #undef AUD_OUT_STR_DESC_A |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1275 | #undef AUD_OUT_STR_DESC_B |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1276 | #undef AUD_OUT_CH_STR |
| 1277 | #undef AUD_PINW_CONNLNG_LIST |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1278 | #undef AUD_PINW_CONNLNG_SEL |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1279 | #undef AUD_CNTL_ST_A |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1280 | #undef AUD_CNTL_ST_B |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1281 | #undef AUD_CNTL_ST2 |
| 1282 | #undef AUD_HDMIW_STATUS |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1283 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1284 | #define PIPE_OFS 0x100 |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1285 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1286 | #define AUD_CONFIG_A 0x0 |
| 1287 | #define AUD_CONFIG_B (AUD_CONFIG_A + PIPE_OFS) |
| 1288 | #define AUD_MISC_CTRL_A 0x010 |
| 1289 | #define AUD_MISC_CTRL_B (AUD_MISC_CTRL_A + PIPE_OFS) |
| 1290 | #define AUD_VID_DID 0x020 |
| 1291 | #define AUD_RID 0x024 |
| 1292 | #define AUD_CTS_ENABLE_A 0x028 |
| 1293 | #define AUD_CTS_ENABLE_B (AUD_CTS_ENABLE_A + PIPE_OFS) |
| 1294 | #define AUD_PWRST 0x04C |
| 1295 | #define AUD_HDMIW_HDMIEDID_A 0x050 |
| 1296 | #define AUD_HDMIW_HDMIEDID_B (AUD_HDMIW_HDMIEDID_A + PIPE_OFS) |
| 1297 | #define AUD_HDMIW_INFOFR_A 0x054 |
| 1298 | #define AUD_HDMIW_INFOFR_B (AUD_HDMIW_INFOFR_A + PIPE_OFS) |
| 1299 | #define AUD_PORT_EN_HD_CFG 0x07c |
| 1300 | #define AUD_OUT_DIG_CNVT_A 0x080 |
| 1301 | #define AUD_OUT_DIG_CNVT_B (AUD_OUT_DIG_CNVT_A + PIPE_OFS) |
| 1302 | #define AUD_OUT_STR_DESC_A 0x084 |
| 1303 | #define AUD_OUT_STR_DESC_B (AUD_OUT_STR_DESC_A + PIPE_OFS) |
| 1304 | #define AUD_OUT_CH_STR 0x088 |
| 1305 | #define AUD_PINW_CONNLNG_LIST 0x0a8 |
| 1306 | #define AUD_PINW_CONNLNG_SEL 0x0aC |
| 1307 | #define AUD_CNTL_ST_A 0x0b4 |
| 1308 | #define AUD_CNTL_ST_B (AUD_CNTL_ST_A + PIPE_OFS) |
| 1309 | #define AUD_CNTL_ST2 0x0c0 |
| 1310 | #define AUD_HDMIW_STATUS 0x0d4 |
Lu, Han | e8e2893 | 2015-02-12 08:41:59 +0800 | [diff] [blame] | 1311 | #define AUD_FREQ_CNTRL 0x900 |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1312 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1313 | /* Audio config registers of Haswell+ */ |
| 1314 | #define AUD_TCA_CONFIG AUD_CONFIG_A |
| 1315 | #define AUD_TCB_CONFIG (AUD_TCA_CONFIG + PIPE_OFS) |
| 1316 | #define AUD_TCC_CONFIG (AUD_TCA_CONFIG + PIPE_OFS * 2) |
| 1317 | #define AUD_C1_MISC_CTRL AUD_MISC_CTRL_A |
| 1318 | #define AUD_C2_MISC_CTRL (AUD_MISC_CTRL_A + PIPE_OFS) |
| 1319 | #define AUD_C3_MISC_CTRL (AUD_MISC_CTRL_A + PIPE_OFS * 2) |
| 1320 | #define AUD_TCA_M_CTS_ENABLE AUD_CTS_ENABLE_A |
| 1321 | #define AUD_TCB_M_CTS_ENABLE (AUD_TCA_M_CTS_ENABLE + PIPE_OFS) |
| 1322 | #define AUD_TCC_M_CTS_ENABLE (AUD_TCA_M_CTS_ENABLE + PIPE_OFS * 2) |
| 1323 | #define AUD_TCA_EDID_DATA AUD_HDMIW_HDMIEDID_A |
| 1324 | #define AUD_TCB_EDID_DATA (AUD_TCA_EDID_DATA + PIPE_OFS) |
| 1325 | #define AUD_TCC_EDID_DATA (AUD_TCA_EDID_DATA + PIPE_OFS * 2) |
| 1326 | #define AUD_TCA_INFOFR AUD_HDMIW_INFOFR_A |
| 1327 | #define AUD_TCB_INFOFR (AUD_TCA_INFOFR + PIPE_OFS) |
| 1328 | #define AUD_TCC_INFOFR (AUD_TCA_INFOFR + PIPE_OFS * 2) |
| 1329 | #define AUD_PIPE_CONV_CFG AUD_PORT_EN_HD_CFG |
| 1330 | #define AUD_C1_DIG_CNVT AUD_OUT_DIG_CNVT_A |
| 1331 | #define AUD_C2_DIG_CNVT (AUD_C1_DIG_CNVT + PIPE_OFS) |
| 1332 | #define AUD_C3_DIG_CNVT (AUD_C1_DIG_CNVT + PIPE_OFS * 2) |
| 1333 | #define AUD_C1_STR_DESC AUD_OUT_STR_DESC_A |
| 1334 | #define AUD_C2_STR_DESC (AUD_C1_STR_DESC + PIPE_OFS) |
| 1335 | #define AUD_C3_STR_DESC (AUD_C1_STR_DESC + PIPE_OFS * 2) |
| 1336 | #define AUD_OUT_CHAN_MAP AUD_OUT_CH_STR |
| 1337 | #define AUD_TCA_PIN_PIPE_CONN_ENTRY_LNGTH AUD_PINW_CONNLNG_LIST |
| 1338 | #define AUD_TCB_PIN_PIPE_CONN_ENTRY_LNGTH (AUD_TCA_PIN_PIPE_CONN_ENTRY_LNGTH + PIPE_OFS) |
| 1339 | #define AUD_TCC_PIN_PIPE_CONN_ENTRY_LNGTH (AUD_TCA_PIN_PIPE_CONN_ENTRY_LNGTH + PIPE_OFS * 2) |
| 1340 | #define AUD_PIPE_CONN_SEL_CTRL AUD_PINW_CONNLNG_SEL |
| 1341 | #define AUD_TCA_DIP_ELD_CTRL_ST AUD_CNTL_ST_A |
| 1342 | #define AUD_TCB_DIP_ELD_CTRL_ST (AUD_TCA_DIP_ELD_CTRL_ST + PIPE_OFS) |
| 1343 | #define AUD_TCC_DIP_ELD_CTRL_ST (AUD_TCA_DIP_ELD_CTRL_ST + PIPE_OFS * 2) |
| 1344 | #define AUD_PIN_ELD_CP_VLD AUD_CNTL_ST2 |
| 1345 | #define AUD_HDMI_FIFO_STATUS AUD_HDMIW_STATUS |
| 1346 | #define AUD_ICOI 0xf00 |
| 1347 | #define AUD_IRII 0xf04 |
| 1348 | #define AUD_ICS 0xf08 |
| 1349 | #define AUD_CHICKENBIT_REG 0xf10 |
| 1350 | #define AUD_DP_DIP_STATUS 0xf20 |
| 1351 | #define AUD_TCA_M_CTS 0xf44 |
| 1352 | #define AUD_TCB_M_CTS 0xf54 |
| 1353 | #define AUD_TCC_M_CTS 0xf64 |
Lu, Han | e8e2893 | 2015-02-12 08:41:59 +0800 | [diff] [blame] | 1354 | #define AUD_HDA_DMA_REG 0xe00 |
| 1355 | #define AUD_HDA_LPIB0_REG 0xe04 |
| 1356 | #define AUD_HDA_LPIB1_REG 0xe08 |
| 1357 | #define AUD_HDA_LPIB2_REG 0xe0c |
| 1358 | #define AUD_HDA_EXTRA_REG 0xe10 |
| 1359 | #define AUD_FPGA_CRC_CTL_A 0xf14 |
| 1360 | #define AUD_FPGA_CRC_CTL_B 0xf24 |
| 1361 | #define AUD_FPGA_CRC_CTL_C 0xf34 |
| 1362 | #define AUD_FPGA_CRC_RESULT_A 0xf18 |
| 1363 | #define AUD_FPGA_CRC_RESULT_B 0xf28 |
| 1364 | #define AUD_FPGA_CRC_RESULT_C 0xf38 |
| 1365 | #define AUD_DFT_MVAL_REG 0xe20 |
| 1366 | #define AUD_DFT_NVAL_REG 0xe24 |
| 1367 | #define AUD_DFT_LOAD_REG 0xe28 |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 1368 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1369 | /* Common functions to dump audio registers */ |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1370 | #define MAX_PREFIX_SIZE 128 |
| 1371 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1372 | static void dump_aud_config(int index) |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1373 | { |
| 1374 | uint32_t dword; |
| 1375 | char prefix[MAX_PREFIX_SIZE]; |
| 1376 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1377 | if (!IS_HASWELL_PLUS(devid)) { |
| 1378 | dword = INREG(aud_reg_base + AUD_CONFIG_A + (index - PIPE_A) * 0x100); |
| 1379 | sprintf(prefix, "AUD_CONFIG_%c ", 'A' + index - PIPE_A); |
| 1380 | } else { |
| 1381 | dword = INREG(aud_reg_base + AUD_TCA_CONFIG + (index - TRANSCODER_A) * 0x100); |
| 1382 | sprintf(prefix, "AUD_TC%c_CONFIG", 'A' + index - TRANSCODER_A); |
| 1383 | } |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1384 | |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1385 | printf("%s Disable_NCTS\t\t\t\t%lu\n", prefix, BIT(dword, 3)); |
| 1386 | printf("%s Lower_N_value\t\t\t\t0x%03lx\n", prefix, BITS(dword, 15, 4)); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1387 | printf("%s Pixel_Clock_HDMI\t\t\t[0x%lx] %s\n", prefix, BITS(dword, 19, 16), |
| 1388 | OPNAME(pixel_clock, BITS(dword, 19, 16))); |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1389 | printf("%s Upper_N_value\t\t\t\t0x%02lx\n", prefix, BITS(dword, 27, 20)); |
| 1390 | printf("%s N_programming_enable\t\t\t%lu\n", prefix, BIT(dword, 28)); |
| 1391 | printf("%s N_index_value\t\t\t\t[0x%lx] %s\n", prefix, BIT(dword, 29), |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1392 | OPNAME(n_index_value, BIT(dword, 29))); |
| 1393 | } |
| 1394 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1395 | static void dump_aud_misc_control(int index) |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1396 | { |
| 1397 | uint32_t dword; |
| 1398 | char prefix[MAX_PREFIX_SIZE]; |
| 1399 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1400 | if (!IS_HASWELL_PLUS(devid)) { |
| 1401 | dword = INREG(aud_reg_base + AUD_MISC_CTRL_A + (index - PIPE_A) * 0x100); |
| 1402 | sprintf(prefix, "AUD_MISC_CTRL_%c ", 'A' + index - PIPE_A); |
| 1403 | } else { |
| 1404 | dword = INREG(aud_reg_base + AUD_C1_MISC_CTRL + (index - CONVERTER_1) * 0x100); |
| 1405 | sprintf(prefix, "AUD_C%c_MISC_CTRL", '1' + index - CONVERTER_1); |
| 1406 | } |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1407 | |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1408 | printf("%s Pro_Allowed\t\t\t\t%lu\n", prefix, BIT(dword, 1)); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1409 | printf("%s Sample_Fabrication_EN_bit\t\t%lu\n", prefix, BIT(dword, 2)); |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1410 | printf("%s Output_Delay\t\t\t\t%lu\n", prefix, BITS(dword, 7, 4)); |
| 1411 | printf("%s Sample_present_Disable\t\t%lu\n", prefix, BIT(dword, 8)); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1412 | } |
| 1413 | |
| 1414 | static void dump_aud_vendor_device_id(void) |
| 1415 | { |
| 1416 | uint32_t dword; |
| 1417 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1418 | dword = INREG(aud_reg_base + AUD_VID_DID); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1419 | printf("AUD_VID_DID device id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 0)); |
| 1420 | printf("AUD_VID_DID vendor id\t\t\t\t\t0x%lx\n", BITS(dword, 31, 16)); |
| 1421 | } |
| 1422 | |
| 1423 | static void dump_aud_revision_id(void) |
| 1424 | { |
| 1425 | uint32_t dword; |
| 1426 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1427 | dword = INREG(aud_reg_base + AUD_RID); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1428 | printf("AUD_RID Stepping_Id\t\t\t\t\t0x%lx\n", BITS(dword, 7, 0)); |
| 1429 | printf("AUD_RID Revision_Id\t\t\t\t\t0x%lx\n", BITS(dword, 15, 8)); |
| 1430 | printf("AUD_RID Minor_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 19, 16)); |
| 1431 | printf("AUD_RID Major_Revision\t\t\t\t\t0x%lx\n", BITS(dword, 23, 20)); |
| 1432 | } |
| 1433 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1434 | static void dump_aud_m_cts_enable(int index) |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1435 | { |
| 1436 | uint32_t dword; |
| 1437 | char prefix[MAX_PREFIX_SIZE]; |
| 1438 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1439 | if (!IS_HASWELL_PLUS(devid)) { |
| 1440 | dword = INREG(aud_reg_base + AUD_CTS_ENABLE_A + (index - PIPE_A) * 0x100); |
| 1441 | sprintf(prefix, "AUD_CTS_ENABLE_%c ", 'A' + index - PIPE_A); |
| 1442 | } else { |
| 1443 | dword = INREG(aud_reg_base + AUD_TCA_M_CTS_ENABLE + (index - TRANSCODER_A) * 0x100); |
| 1444 | sprintf(prefix, "AUD_TC%c_M_CTS_ENABLE", 'A' + index - TRANSCODER_A); |
| 1445 | } |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1446 | |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1447 | printf("%s CTS_programming\t\t\t%#lx\n", prefix, BITS(dword, 19, 0)); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1448 | printf("%s Enable_CTS_or_M_programming\t%lu\n", prefix, BIT(dword, 20)); |
Mengdong Lin | 8fe0c50 | 2014-03-13 16:38:02 -0400 | [diff] [blame] | 1449 | printf("%s CTS_M value Index\t\t\t[0x%lx] %s\n",prefix, BIT(dword, 21), |
| 1450 | OPNAME(cts_m_value_index, BIT(dword, 21))); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1451 | } |
| 1452 | |
| 1453 | static void dump_aud_power_state(void) |
| 1454 | { |
| 1455 | uint32_t dword; |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1456 | int num_pipes; |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1457 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1458 | dword = INREG(aud_reg_base + AUD_PWRST); |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1459 | printf("AUD_PWRST PinB_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 1, 0)]); |
| 1460 | printf("AUD_PWRST PinB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 3, 2)]); |
| 1461 | printf("AUD_PWRST PinC_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 5, 4)]); |
| 1462 | printf("AUD_PWRST PinC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 7, 6)]); |
| 1463 | printf("AUD_PWRST PinD_Widget_Power_State_Set \t%s\n", power_state[BITS(dword, 9, 8)]); |
| 1464 | printf("AUD_PWRST PinD_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 11, 10)]); |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1465 | |
| 1466 | if (!IS_HASWELL_PLUS(devid)) { |
| 1467 | printf("AUD_PWRST ConvertorA_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]); |
| 1468 | printf("AUD_PWRST ConvertorA_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]); |
| 1469 | printf("AUD_PWRST ConvertorB_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]); |
| 1470 | printf("AUD_PWRST ConvertorB_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]); |
| 1471 | } else { |
| 1472 | printf("AUD_PWRST Convertor1_Widget_Power_State_Requsted \t%s\n", power_state[BITS(dword, 13, 12)]); |
| 1473 | printf("AUD_PWRST Convertor1_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 15, 14)]); |
| 1474 | printf("AUD_PWRST Convertor2_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 17, 16)]); |
| 1475 | printf("AUD_PWRST Convertor2_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 19, 18)]); |
| 1476 | } |
| 1477 | |
| 1478 | num_pipes = get_num_pipes(); |
| 1479 | if (num_pipes == 2) { |
| 1480 | printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 21, 20)]); |
| 1481 | printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 23, 22)]); |
| 1482 | } else { /* 3 pipes */ |
| 1483 | if (!IS_HASWELL_PLUS(devid)) { |
| 1484 | printf("AUD_PWRST ConvertorC_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 21, 20)]); |
| 1485 | printf("AUD_PWRST ConvertorC_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 23, 22)]); |
| 1486 | } else { |
| 1487 | printf("AUD_PWRST Convertor3_Widget_Power_State_Requested \t%s\n", power_state[BITS(dword, 21, 20)]); |
| 1488 | printf("AUD_PWRST Convertor3_Widget_Power_State_Current \t%s\n", power_state[BITS(dword, 23, 22)]); |
| 1489 | } |
| 1490 | printf("AUD_PWRST Func_Grp_Dev_PwrSt_Set \t%s\n", power_state[BITS(dword, 25, 24)]); |
| 1491 | printf("AUD_PWRST Func_Grp_Dev_PwrSt_Curr \t%s\n", power_state[BITS(dword, 27, 26)]); |
| 1492 | } |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1493 | } |
| 1494 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1495 | static void dump_aud_edid_data(int index) |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1496 | { |
| 1497 | uint32_t dword; |
| 1498 | int i; |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1499 | int offset; |
| 1500 | int aud_ctrl_st, edid_data; |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1501 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1502 | if (IS_HASWELL_PLUS(devid)) { |
| 1503 | offset = (index - TRANSCODER_A) * 0x100; |
| 1504 | aud_ctrl_st = aud_reg_base + AUD_TCA_DIP_ELD_CTRL_ST + offset; |
| 1505 | edid_data = aud_reg_base + AUD_TCA_EDID_DATA + offset; |
| 1506 | printf("AUD_TC%c_EDID_DATA ELD:\n\t", 'A' + index - TRANSCODER_A); |
| 1507 | } else { |
| 1508 | offset = (index - PIPE_A) * 0x100; |
| 1509 | aud_ctrl_st = aud_reg_base + AUD_CNTL_ST_A + offset; |
| 1510 | edid_data = aud_reg_base + AUD_HDMIW_HDMIEDID_A + offset; |
| 1511 | printf("AUD_HDMIW_HDMIEDID_%c HDMI ELD:\n\t", 'A' + index - PIPE_A); |
| 1512 | } |
| 1513 | |
| 1514 | dword = INREG(aud_ctrl_st); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1515 | dword &= ~BITMASK(9, 5); |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1516 | OUTREG(aud_ctrl_st, dword); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1517 | for (i = 0; i < BITS(dword, 14, 10) / 4; i++) |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1518 | printf("%08x ", htonl(INREG(edid_data))); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1519 | printf("\n"); |
| 1520 | } |
| 1521 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1522 | static void dump_aud_infoframe(int index) |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1523 | { |
| 1524 | uint32_t dword; |
| 1525 | int i; |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1526 | int offset; |
| 1527 | int aud_ctrl_st, info_frm; |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1528 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1529 | if (IS_HASWELL_PLUS(devid)) { |
| 1530 | offset = (index - TRANSCODER_A) * 0x100; |
| 1531 | aud_ctrl_st = aud_reg_base + AUD_TCA_DIP_ELD_CTRL_ST + offset; |
| 1532 | info_frm = aud_reg_base + AUD_TCA_INFOFR + offset; |
| 1533 | printf("AUD_TC%c_INFOFR audio Infoframe:\n\t", 'A' + index - TRANSCODER_A); |
| 1534 | } else { |
| 1535 | offset = (index - PIPE_A) * 0x100; |
| 1536 | aud_ctrl_st = aud_reg_base + AUD_CNTL_ST_A + offset; |
| 1537 | info_frm = aud_reg_base + AUD_HDMIW_INFOFR_A + offset; |
| 1538 | printf("AUD_HDMIW_INFOFR_%c HDMI audio Infoframe:\n\t", 'A' + index - PIPE_A); |
| 1539 | } |
| 1540 | |
| 1541 | dword = INREG(aud_ctrl_st); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1542 | dword &= ~BITMASK(20, 18); |
| 1543 | dword &= ~BITMASK(3, 0); |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1544 | OUTREG(aud_ctrl_st, dword); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1545 | for (i = 0; i < 8; i++) |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1546 | printf("%08x ", htonl(INREG(info_frm))); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1547 | printf("\n"); |
| 1548 | } |
| 1549 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1550 | static void dump_aud_port_en_hd_cfg(void) |
| 1551 | { |
| 1552 | uint32_t dword; |
| 1553 | int num_pipes = get_num_pipes(); |
| 1554 | |
| 1555 | dword = INREG(aud_reg_base + AUD_PORT_EN_HD_CFG); |
| 1556 | if (num_pipes == 2) { |
| 1557 | printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0)); |
| 1558 | printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1)); |
| 1559 | printf("AUD_PORT_EN_HD_CFG Convertor_A_Stream_ID\t\t%lu\n", BITS(dword, 7, 4)); |
| 1560 | printf("AUD_PORT_EN_HD_CFG Convertor_B_Stream_ID\t\t%lu\n", BITS(dword, 11, 8)); |
| 1561 | |
| 1562 | printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 12)); |
| 1563 | printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 13)); |
| 1564 | printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 14)); |
| 1565 | printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 16)); |
| 1566 | printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 17)); |
| 1567 | printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 18)); |
| 1568 | } else { /* three pipes */ |
| 1569 | printf("AUD_PORT_EN_HD_CFG Convertor_A_Digen\t\t\t%lu\n", BIT(dword, 0)); |
| 1570 | printf("AUD_PORT_EN_HD_CFG Convertor_B_Digen\t\t\t%lu\n", BIT(dword, 1)); |
| 1571 | printf("AUD_PORT_EN_HD_CFG Convertor_C_Digen\t\t\t%lu\n", BIT(dword, 2)); |
| 1572 | printf("AUD_PORT_EN_HD_CFG Convertor_A_Stream_ID\t\t%lu\n", BITS(dword, 7, 4)); |
| 1573 | printf("AUD_PORT_EN_HD_CFG Convertor_B_Stream_ID\t\t%lu\n", BITS(dword, 11, 8)); |
| 1574 | printf("AUD_PORT_EN_HD_CFG Convertor_C_Stream_ID\t\t%lu\n", BITS(dword, 15, 12)); |
| 1575 | |
| 1576 | printf("AUD_PORT_EN_HD_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16)); |
| 1577 | printf("AUD_PORT_EN_HD_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17)); |
| 1578 | printf("AUD_PORT_EN_HD_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18)); |
| 1579 | printf("AUD_PORT_EN_HD_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20)); |
| 1580 | printf("AUD_PORT_EN_HD_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21)); |
| 1581 | printf("AUD_PORT_EN_HD_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22)); |
| 1582 | } |
| 1583 | } |
| 1584 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1585 | static void dump_aud_pipe_conv_cfg(void) |
| 1586 | { |
| 1587 | uint32_t dword; |
| 1588 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1589 | dword = INREG(aud_reg_base + AUD_PIPE_CONV_CFG); |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1590 | printf("AUD_PIPE_CONV_CFG Convertor_1_Digen\t\t\t%lu\n", BIT(dword, 0)); |
| 1591 | printf("AUD_PIPE_CONV_CFG Convertor_2_Digen\t\t\t%lu\n", BIT(dword, 1)); |
| 1592 | printf("AUD_PIPE_CONV_CFG Convertor_3_Digen\t\t\t%lu\n", BIT(dword, 2)); |
| 1593 | printf("AUD_PIPE_CONV_CFG Convertor_1_Stream_ID\t\t%lu\n", BITS(dword, 7, 4)); |
| 1594 | printf("AUD_PIPE_CONV_CFG Convertor_2_Stream_ID\t\t%lu\n", BITS(dword, 11, 8)); |
| 1595 | printf("AUD_PIPE_CONV_CFG Convertor_3_Stream_ID\t\t%lu\n", BITS(dword, 15, 12)); |
| 1596 | |
| 1597 | printf("AUD_PIPE_CONV_CFG Port_B_Out_Enable\t\t\t%lu\n", BIT(dword, 16)); |
| 1598 | printf("AUD_PIPE_CONV_CFG Port_C_Out_Enable\t\t\t%lu\n", BIT(dword, 17)); |
| 1599 | printf("AUD_PIPE_CONV_CFG Port_D_Out_Enable\t\t\t%lu\n", BIT(dword, 18)); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1600 | printf("AUD_PIPE_CONV_CFG Port_B_Amp_Mute_Status\t\t%lu\n", BIT(dword, 20)); |
| 1601 | printf("AUD_PIPE_CONV_CFG Port_C_Amp_Mute_Status\t\t%lu\n", BIT(dword, 21)); |
| 1602 | printf("AUD_PIPE_CONV_CFG Port_D_Amp_Mute_Status\t\t%lu\n", BIT(dword, 22)); |
| 1603 | } |
| 1604 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1605 | static void dump_aud_dig_cnvt(int index) |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1606 | { |
| 1607 | uint32_t dword; |
| 1608 | char prefix[MAX_PREFIX_SIZE]; |
| 1609 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1610 | if (!IS_HASWELL_PLUS(devid)) { |
| 1611 | dword = INREG(aud_reg_base + AUD_OUT_DIG_CNVT_A + (index - PIPE_A) * 0x100); |
| 1612 | sprintf(prefix, "AUD_OUT_DIG_CNVT_%c", 'A' + index - PIPE_A); |
| 1613 | } else { |
| 1614 | dword = INREG(aud_reg_base + AUD_C1_DIG_CNVT + (index - CONVERTER_1) * 0x100); |
| 1615 | sprintf(prefix, "AUD_C%c_DIG_CNVT ", '1' + index - CONVERTER_1); |
| 1616 | } |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1617 | |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1618 | printf("%s V\t\t\t\t\t%lu\n", prefix, BIT(dword, 1)); |
| 1619 | printf("%s VCFG\t\t\t\t%lu\n", prefix, BIT(dword, 2)); |
| 1620 | printf("%s PRE\t\t\t\t\t%lu\n", prefix, BIT(dword, 3)); |
| 1621 | printf("%s Copy\t\t\t\t%lu\n", prefix, BIT(dword, 4)); |
| 1622 | printf("%s NonAudio\t\t\t\t%lu\n", prefix, BIT(dword, 5)); |
| 1623 | printf("%s PRO\t\t\t\t\t%lu\n", prefix, BIT(dword, 6)); |
| 1624 | printf("%s Level\t\t\t\t%lu\n", prefix, BIT(dword, 7)); |
| 1625 | printf("%s Category_Code\t\t\t%lu\n", prefix, BITS(dword, 14, 8)); |
| 1626 | printf("%s Lowest_Channel_Number\t\t%lu\n", prefix, BITS(dword, 19, 16)); |
| 1627 | printf("%s Stream_ID\t\t\t\t%lu\n", prefix, BITS(dword, 23, 20)); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1628 | } |
| 1629 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1630 | static void dump_aud_str_desc(int index) |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1631 | { |
| 1632 | uint32_t dword; |
| 1633 | char prefix[MAX_PREFIX_SIZE]; |
| 1634 | uint32_t rate; |
| 1635 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1636 | if (!IS_HASWELL_PLUS(devid)) { |
| 1637 | dword = INREG(aud_reg_base + AUD_OUT_STR_DESC_A + (index - PIPE_A) * 0x100); |
| 1638 | sprintf(prefix, "AUD_OUT_STR_DESC_%c", 'A' + index - PIPE_A); |
| 1639 | } else { |
| 1640 | dword = INREG(aud_reg_base + AUD_C1_STR_DESC + (index - CONVERTER_1) * 0x100); |
| 1641 | sprintf(prefix, "AUD_C%c_STR_DESC ", '1' + index - CONVERTER_1); |
| 1642 | } |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1643 | |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1644 | printf("%s Number_of_Channels_in_a_Stream\t%lu\n", prefix, BITS(dword, 3, 0) + 1); |
| 1645 | printf("%s Bits_per_Sample\t\t\t[%#lx] %s\n", prefix, BITS(dword, 6, 4), |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1646 | OPNAME(bits_per_sample, BITS(dword, 6, 4))); |
| 1647 | |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1648 | printf("%s Sample_Base_Rate_Divisor\t\t[%#lx] %s\n", prefix, BITS(dword, 10, 8), |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1649 | OPNAME(sample_base_rate_divisor, BITS(dword, 10, 8))); |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1650 | printf("%s Sample_Base_Rate_Mult\t\t[%#lx] %s\n", prefix, BITS(dword, 13, 11), |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1651 | OPNAME(sample_base_rate_mult, BITS(dword, 13, 11))); |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1652 | printf("%s Sample_Base_Rate\t\t\t[%#lx] %s\t", prefix, BIT(dword, 14), |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1653 | OPNAME(sample_base_rate, BIT(dword, 14))); |
| 1654 | rate = (BIT(dword, 14) ? 44100 : 48000) * (BITS(dword, 13, 11) + 1) |
| 1655 | /(BITS(dword, 10, 8) + 1); |
| 1656 | printf("=> Sample Rate %d Hz\n", rate); |
| 1657 | |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1658 | printf("%s Convertor_Channel_Count\t\t%lu\n", prefix, BITS(dword, 20, 16) + 1); |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1659 | |
| 1660 | if (!IS_HASWELL_PLUS(devid)) |
| 1661 | printf("%s HBR_enable\t\t\t\t%lu\n", prefix, BITS(dword, 28, 27)); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1662 | } |
| 1663 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1664 | #define dump_aud_out_ch_str dump_aud_out_chan_map |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1665 | static void dump_aud_out_chan_map(void) |
| 1666 | { |
| 1667 | uint32_t dword; |
| 1668 | int i; |
| 1669 | |
| 1670 | printf("AUD_OUT_CHAN_MAP Converter_Channel_MAP PORTB PORTC PORTD\n"); |
| 1671 | for (i = 0; i < 8; i++) { |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1672 | OUTREG(aud_reg_base + AUD_OUT_CHAN_MAP, i | (i << 8) | (i << 16)); |
| 1673 | dword = INREG(aud_reg_base + AUD_OUT_CHAN_MAP); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1674 | printf("\t\t\t\t%lu\t%lu\t%lu\t%lu\n", |
| 1675 | 1 + BITS(dword, 3, 0), |
| 1676 | 1 + BITS(dword, 7, 4), |
| 1677 | 1 + BITS(dword, 15, 12), |
| 1678 | 1 + BITS(dword, 23, 20)); |
| 1679 | } |
| 1680 | } |
| 1681 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1682 | static void dump_aud_connect_list(void) |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1683 | { |
| 1684 | uint32_t dword; |
| 1685 | char prefix[MAX_PREFIX_SIZE]; |
| 1686 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1687 | dword = INREG(aud_reg_base + AUD_PINW_CONNLNG_LIST); |
| 1688 | sprintf(prefix, "AUD_PINW_CONNLNG_LIST"); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1689 | |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1690 | printf("%s Connect_List_Length\t\t%lu\n", prefix, BITS(dword, 6, 0)); |
| 1691 | printf("%s Form \t\t\t\t[%#lx] %s\n", prefix, BIT(dword, 7), |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1692 | OPNAME(connect_list_form, BIT(dword, 7))); |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1693 | printf("%s Connect_List_Entry\t\t%lu, %lu\n", prefix, BITS(dword, 15, 8), BITS(dword, 23, 16)); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1694 | } |
| 1695 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1696 | static void dump_aud_connect_select(void) |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1697 | { |
| 1698 | uint32_t dword; |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1699 | char prefix[MAX_PREFIX_SIZE]; |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1700 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1701 | if (IS_HASWELL_PLUS(devid)) { |
| 1702 | dword = INREG(aud_reg_base + AUD_PIPE_CONN_SEL_CTRL); |
| 1703 | sprintf(prefix, "AUD_PIPE_CONN_SEL_CTRL"); |
| 1704 | |
| 1705 | } else { |
| 1706 | dword = INREG(aud_reg_base + AUD_PINW_CONNLNG_SEL); |
| 1707 | sprintf(prefix, "AUD_PINW_CONNLNG_SEL "); |
| 1708 | } |
| 1709 | |
| 1710 | printf("%s Connection_select_Port_B\t%#lx\n", prefix, BITS(dword, 7, 0)); |
| 1711 | printf("%s Connection_select_Port_C\t%#lx\n", prefix, BITS(dword, 15, 8)); |
| 1712 | printf("%s Connection_select_Port_D\t%#lx\n", prefix, BITS(dword, 23, 16)); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1713 | } |
| 1714 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1715 | static void dump_aud_ctrl_state(int index) |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1716 | { |
| 1717 | uint32_t dword; |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1718 | int offset; |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1719 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1720 | if (IS_HASWELL_PLUS(devid)) { |
| 1721 | offset = (index - TRANSCODER_A) * 0x100; |
| 1722 | dword = INREG(aud_reg_base + AUD_TCA_DIP_ELD_CTRL_ST + offset); |
| 1723 | printf("Audio DIP and ELD control state for Transcoder %c\n", 'A' + index - TRANSCODER_A); |
| 1724 | } else { |
| 1725 | offset = (index - PIPE_A) * 0x100; |
| 1726 | dword = INREG(aud_reg_base + AUD_CNTL_ST_A + offset); |
| 1727 | printf("Audio control state - Pipe %c\n", 'A' + index - PIPE_A); |
| 1728 | } |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1729 | |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1730 | printf("\tELD_ACK\t\t\t\t\t\t%lu\n", BIT(dword, 4)); |
| 1731 | printf("\tELD_buffer_size\t\t\t\t\t%lu\n", BITS(dword, 14, 10)); |
| 1732 | printf("\tDIP_transmission_frequency\t\t\t[0x%lx] %s\n", BITS(dword, 17, 16), |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1733 | dip_trans[BITS(dword, 17, 16)]); |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1734 | printf("\tDIP Buffer Index \t\t\t\t[0x%lx] %s\n", BITS(dword, 20, 18), |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1735 | dip_index[BITS(dword, 20, 18)]); |
| 1736 | printf("\tAudio DIP type enable status\t\t\t[0x%04lx] %s, %s, %s\n", BITS(dword, 24, 21), |
| 1737 | dip_type[BIT(dword, 21)], dip_gen1_state[BIT(dword, 22)], dip_gen2_state[BIT(dword, 23)]); |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 1738 | printf("\tAudio DIP port select\t\t\t\t[0x%lx] %s\n", BITS(dword, 30, 29), |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1739 | dip_port[BITS(dword, 30, 29)]); |
| 1740 | printf("\n"); |
| 1741 | } |
| 1742 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1743 | static void dump_aud_ctrl_state2(void) |
| 1744 | { |
| 1745 | uint32_t dword; |
| 1746 | |
| 1747 | dword = INREG(aud_reg_base + AUD_CNTL_ST2); |
| 1748 | printf("AUD_CNTL_ST2 ELD_validB\t\t\t\t%lu\n", BIT(dword, 0)); |
| 1749 | printf("AUD_CNTL_ST2 CP_ReadyB\t\t\t\t\t%lu\n", BIT(dword, 1)); |
| 1750 | printf("AUD_CNTL_ST2 ELD_validC\t\t\t\t%lu\n", BIT(dword, 4)); |
| 1751 | printf("AUD_CNTL_ST2 CP_ReadyC\t\t\t\t\t%lu\n", BIT(dword, 5)); |
| 1752 | printf("AUD_CNTL_ST2 ELD_validD\t\t\t\t%lu\n", BIT(dword, 8)); |
| 1753 | printf("AUD_CNTL_ST2 CP_ReadyD\t\t\t\t\t%lu\n", BIT(dword, 9)); |
| 1754 | } |
| 1755 | |
| 1756 | /* for hsw+ */ |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1757 | static void dump_aud_eld_cp_vld(void) |
| 1758 | { |
| 1759 | uint32_t dword; |
| 1760 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1761 | dword = INREG(aud_reg_base + AUD_PIN_ELD_CP_VLD); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1762 | printf("AUD_PIN_ELD_CP_VLD Transcoder_A ELD_valid\t\t%lu\n", BIT(dword, 0)); |
| 1763 | printf("AUD_PIN_ELD_CP_VLD Transcoder_A CP_Ready \t\t%lu\n", BIT(dword, 1)); |
| 1764 | printf("AUD_PIN_ELD_CP_VLD Transcoder_A Out_enable\t\t%lu\n", BIT(dword, 2)); |
| 1765 | printf("AUD_PIN_ELD_CP_VLD Transcoder_A Inactive\t\t%lu\n", BIT(dword, 3)); |
| 1766 | printf("AUD_PIN_ELD_CP_VLD Transcoder_B ELD_valid\t\t%lu\n", BIT(dword, 4)); |
| 1767 | printf("AUD_PIN_ELD_CP_VLD Transcoder_B CP_Ready\t\t%lu\n", BIT(dword, 5)); |
| 1768 | printf("AUD_PIN_ELD_CP_VLD Transcoder_B OUT_enable\t\t%lu\n", BIT(dword, 6)); |
| 1769 | printf("AUD_PIN_ELD_CP_VLD Transcoder_B Inactive\t\t%lu\n", BIT(dword, 7)); |
| 1770 | printf("AUD_PIN_ELD_CP_VLD Transcoder_C ELD_valid\t\t%lu\n", BIT(dword, 8)); |
| 1771 | printf("AUD_PIN_ELD_CP_VLD Transcoder_C CP_Ready\t\t%lu\n", BIT(dword, 9)); |
| 1772 | printf("AUD_PIN_ELD_CP_VLD Transcoder_C OUT_enable\t\t%lu\n", BIT(dword, 10)); |
| 1773 | printf("AUD_PIN_ELD_CP_VLD Transcoder_C Inactive\t\t%lu\n", BIT(dword, 11)); |
| 1774 | } |
| 1775 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1776 | static void dump_aud_hdmi_status(void) |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 1777 | { |
| 1778 | uint32_t dword; |
| 1779 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1780 | dword = INREG(aud_reg_base + AUD_HDMIW_STATUS); |
| 1781 | printf("AUD_HDMIW_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24)); |
| 1782 | printf("AUD_HDMIW_STATUS BCLK/CDCLK_FIFO_Overrun\t\t%lu\n", BIT(dword, 25)); |
| 1783 | printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28)); |
| 1784 | printf("AUD_HDMIW_STATUS Conv_A_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29)); |
| 1785 | printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30)); |
| 1786 | printf("AUD_HDMIW_STATUS Conv_B_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31)); |
| 1787 | } |
| 1788 | |
| 1789 | /* |
Mengdong Lin | 449509d | 2014-03-03 17:03:02 -0500 | [diff] [blame] | 1790 | * Display registers of Ironlake and Valleyview |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1791 | */ |
| 1792 | #undef DP_CTL_B |
| 1793 | #undef DP_CTL_C |
| 1794 | #undef DP_CTL_D |
| 1795 | |
| 1796 | #define DP_CTL_B 0x4100 |
| 1797 | #define DP_CTL_C 0x4200 |
| 1798 | #define DP_CTL_D 0x4300 |
| 1799 | |
Mengdong Lin | 449509d | 2014-03-03 17:03:02 -0500 | [diff] [blame] | 1800 | /* ILK HDMI port ctrl */ |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1801 | #define HDMI_CTL_B 0x1140 |
| 1802 | #define HDMI_CTL_C 0x1150 |
| 1803 | #define HDMI_CTL_D 0x1160 |
Yang, Libin | 9917744 | 2015-01-12 01:38:34 +0000 | [diff] [blame] | 1804 | #define BSW_HDMI_CTL_B 0x1140 |
| 1805 | #define BSW_HDMI_CTL_C 0x1160 |
| 1806 | #define BSW_HDMI_CTL_D 0x116c |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1807 | |
Mengdong Lin | 449509d | 2014-03-03 17:03:02 -0500 | [diff] [blame] | 1808 | /* VLV HDMI port ctrl */ |
| 1809 | #define SDVO_HDMI_CTL_B 0x1140 |
| 1810 | #define SDVO_HDMI_CTL_C 0x1160 |
| 1811 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1812 | static void dump_dp_port_ctrl(int port) |
| 1813 | { |
| 1814 | uint32_t dword; |
| 1815 | int port_ctrl; |
| 1816 | char prefix[MAX_PREFIX_SIZE]; |
| 1817 | |
| 1818 | sprintf(prefix, "DP_%c", 'B' + port - PORT_B); |
| 1819 | |
| 1820 | port_ctrl = disp_reg_base + DP_CTL_B + (port - PORT_B) * 0x100; |
| 1821 | dword = INREG(port_ctrl); |
| 1822 | printf("%s DisplayPort_Enable\t\t\t\t\t%lu\n", prefix, BIT(dword, 31)); |
| 1823 | printf("%s Transcoder_Select\t\t\t\t\t%s\n", prefix, BIT(dword, 30) ? "Transcoder B" : "Transcoder A"); |
| 1824 | printf("%s Port_Width_Selection\t\t\t\t[0x%lx] %s\n", prefix, BITS(dword, 21, 19), |
| 1825 | dp_port_width[BITS(dword, 21, 19)]); |
| 1826 | printf("%s Port_Detected\t\t\t\t\t%lu\n", prefix, BIT(dword, 2)); |
| 1827 | printf("%s HDCP_Port_Select\t\t\t\t\t%lu\n", prefix, BIT(dword, 5)); |
| 1828 | printf("%s Audio_Output_Enable\t\t\t\t%lu\n", prefix, BIT(dword, 6)); |
| 1829 | } |
| 1830 | |
| 1831 | static void dump_hdmi_port_ctrl(int port) |
| 1832 | { |
| 1833 | uint32_t dword; |
| 1834 | int port_ctrl; |
| 1835 | char prefix[MAX_PREFIX_SIZE]; |
| 1836 | |
Mengdong Lin | 449509d | 2014-03-03 17:03:02 -0500 | [diff] [blame] | 1837 | if (IS_VALLEYVIEW(devid)) { |
| 1838 | sprintf(prefix, "SDVO/HDMI%c", 'B' + port - PORT_B); |
| 1839 | port_ctrl = disp_reg_base + SDVO_HDMI_CTL_B + (port - PORT_B) * 0x20; |
| 1840 | } else { |
| 1841 | sprintf(prefix, "HDMI%c ", 'B' + port - PORT_B); |
| 1842 | port_ctrl = disp_reg_base + HDMI_CTL_B + (port - PORT_B) * 0x10; |
| 1843 | } |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1844 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1845 | dword = INREG(port_ctrl); |
| 1846 | printf("%s HDMI_Enable\t\t\t\t\t%u\n", prefix, !!(dword & SDVO_ENABLE)); |
| 1847 | printf("%s Transcoder_Select\t\t\t\t%s\n", prefix, BIT(dword, 30) ? "Transcoder B" : "Transcoder A"); |
| 1848 | printf("%s HDCP_Port_Select\t\t\t\t%lu\n", prefix, BIT(dword, 5)); |
| 1849 | if (port == PORT_B) /* TODO: check spec, not found in Ibx b-spec, and only for port B? */ |
| 1850 | printf("%s SDVO Hot Plug Interrupt Detect Enable\t%lu\n", prefix, BIT(dword, 23)); |
| 1851 | printf("%s Digital_Port_Detected\t\t\t%lu\n", prefix, BIT(dword, 2)); |
| 1852 | printf("%s Encoding\t\t\t\t\t[0x%lx] %s\n", prefix, BITS(dword, 11, 10), |
| 1853 | sdvo_hdmi_encoding[BITS(dword, 11, 10)]); |
| 1854 | printf("%s Null_packets_enabled_during_Vsync\t\t%u\n", prefix, !!(dword & SDVO_NULL_PACKETS_DURING_VSYNC)); |
| 1855 | printf("%s Audio_Output_Enable\t\t\t\t%u\n", prefix, !!(dword & SDVO_AUDIO_ENABLE)); |
| 1856 | } |
| 1857 | |
| 1858 | static void dump_ironlake(void) |
| 1859 | { |
| 1860 | uint32_t dword; |
| 1861 | |
Mengdong Lin | 449509d | 2014-03-03 17:03:02 -0500 | [diff] [blame] | 1862 | if (!IS_VALLEYVIEW(devid)) |
| 1863 | set_reg_base(0xe0000, 0x2000); /* ironlake */ |
| 1864 | else |
| 1865 | set_reg_base(0x60000 + VLV_DISPLAY_BASE, 0x2000); |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1866 | |
Mengdong Lin | 449509d | 2014-03-03 17:03:02 -0500 | [diff] [blame] | 1867 | if (!IS_VALLEYVIEW(devid)) { |
| 1868 | dump_disp_reg(HDMI_CTL_B, "sDVO/HDMI Port B Control"); |
| 1869 | dump_disp_reg(HDMI_CTL_C, "HDMI Port C Control"); |
| 1870 | dump_disp_reg(HDMI_CTL_D, "HDMI Port D Control"); |
| 1871 | } else { |
| 1872 | dump_disp_reg(SDVO_HDMI_CTL_B, "sDVO/HDMI Port B Control"); |
| 1873 | dump_disp_reg(SDVO_HDMI_CTL_C, "sDVO/HDMI Port C Control"); |
| 1874 | } |
| 1875 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1876 | dump_disp_reg(DP_CTL_B, "DisplayPort B Control Register"); |
| 1877 | dump_disp_reg(DP_CTL_C, "DisplayPort C Control Register"); |
Mengdong Lin | 449509d | 2014-03-03 17:03:02 -0500 | [diff] [blame] | 1878 | if (!IS_VALLEYVIEW(devid)) |
| 1879 | dump_disp_reg(DP_CTL_D, "DisplayPort D Control Register"); |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1880 | |
| 1881 | dump_aud_reg(AUD_CONFIG_A, "Audio Configuration - Transcoder A"); |
| 1882 | dump_aud_reg(AUD_CONFIG_B, "Audio Configuration - Transcoder B"); |
| 1883 | dump_aud_reg(AUD_CTS_ENABLE_A, "Audio CTS Programming Enable - Transcoder A"); |
| 1884 | dump_aud_reg(AUD_CTS_ENABLE_B, "Audio CTS Programming Enable - Transcoder B"); |
| 1885 | dump_aud_reg(AUD_MISC_CTRL_A, "Audio MISC Control for Transcoder A"); |
| 1886 | dump_aud_reg(AUD_MISC_CTRL_B, "Audio MISC Control for Transcoder B"); |
| 1887 | dump_aud_reg(AUD_VID_DID, "Audio Vendor ID / Device ID"); |
| 1888 | dump_aud_reg(AUD_RID, "Audio Revision ID"); |
| 1889 | dump_aud_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)"); |
| 1890 | dump_aud_reg(AUD_PORT_EN_HD_CFG, "Audio Port Enable HDAudio Config"); |
| 1891 | dump_aud_reg(AUD_OUT_DIG_CNVT_A, "Audio Digital Converter - Conv A"); |
| 1892 | dump_aud_reg(AUD_OUT_DIG_CNVT_B, "Audio Digital Converter - Conv B"); |
| 1893 | dump_aud_reg(AUD_OUT_CH_STR, "Audio Channel ID and Stream ID"); |
| 1894 | dump_aud_reg(AUD_OUT_STR_DESC_A, "Audio Stream Descriptor Format - Conv A"); |
| 1895 | dump_aud_reg(AUD_OUT_STR_DESC_B, "Audio Stream Descriptor Format - Conv B"); |
| 1896 | dump_aud_reg(AUD_PINW_CONNLNG_LIST, "Audio Connection List"); |
| 1897 | dump_aud_reg(AUD_PINW_CONNLNG_SEL, "Audio Connection Select"); |
| 1898 | dump_aud_reg(AUD_CNTL_ST_A, "Audio Control State Register - Transcoder A"); |
| 1899 | dump_aud_reg(AUD_CNTL_ST_B, "Audio Control State Register - Transcoder B"); |
| 1900 | dump_aud_reg(AUD_CNTL_ST2, "Audio Control State 2"); |
| 1901 | dump_aud_reg(AUD_HDMIW_STATUS, "Audio HDMI Status"); |
| 1902 | dump_aud_reg(AUD_HDMIW_HDMIEDID_A, "HDMI Data EDID Block - Transcoder A"); |
| 1903 | dump_aud_reg(AUD_HDMIW_HDMIEDID_B, "HDMI Data EDID Block - Transcoder B"); |
| 1904 | dump_aud_reg(AUD_HDMIW_INFOFR_A, "Audio Widget Data Island Packet - Transcoder A"); |
| 1905 | dump_aud_reg(AUD_HDMIW_INFOFR_B, "Audio Widget Data Island Packet - Transcoder B"); |
| 1906 | |
| 1907 | printf("\nDetails:\n\n"); |
| 1908 | |
| 1909 | dump_aud_vendor_device_id(); |
| 1910 | dump_aud_revision_id(); |
| 1911 | |
| 1912 | dump_hdmi_port_ctrl(PORT_B); |
| 1913 | dump_hdmi_port_ctrl(PORT_C); |
Mengdong Lin | 449509d | 2014-03-03 17:03:02 -0500 | [diff] [blame] | 1914 | if (!IS_VALLEYVIEW(devid)) |
| 1915 | dump_hdmi_port_ctrl(PORT_D); |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1916 | |
| 1917 | dump_dp_port_ctrl(PORT_B); |
| 1918 | dump_dp_port_ctrl(PORT_C); |
Mengdong Lin | 449509d | 2014-03-03 17:03:02 -0500 | [diff] [blame] | 1919 | if (!IS_VALLEYVIEW(devid)) |
| 1920 | dump_dp_port_ctrl(PORT_D); |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 1921 | |
| 1922 | dump_aud_config(PIPE_A); |
| 1923 | dump_aud_config(PIPE_B); |
| 1924 | |
| 1925 | dump_aud_m_cts_enable(PIPE_A); |
| 1926 | dump_aud_m_cts_enable(PIPE_B); |
| 1927 | |
| 1928 | dump_aud_misc_control(PIPE_A); |
| 1929 | dump_aud_misc_control(PIPE_B); |
| 1930 | |
| 1931 | dump_aud_power_state(); |
| 1932 | dump_aud_port_en_hd_cfg(); |
| 1933 | |
| 1934 | dump_aud_dig_cnvt(PIPE_A); |
| 1935 | dump_aud_dig_cnvt(PIPE_B); |
| 1936 | |
| 1937 | dump_aud_out_ch_str(); |
| 1938 | |
| 1939 | dump_aud_str_desc(PIPE_A); |
| 1940 | dump_aud_str_desc(PIPE_B); |
| 1941 | |
| 1942 | dump_aud_connect_list(); |
| 1943 | dump_aud_connect_select(); |
| 1944 | |
| 1945 | dump_aud_ctrl_state(PIPE_A); |
| 1946 | dump_aud_ctrl_state(PIPE_B); |
| 1947 | dump_aud_ctrl_state2(); |
| 1948 | |
| 1949 | dump_aud_hdmi_status(); |
| 1950 | |
| 1951 | dump_aud_edid_data(PIPE_A); |
| 1952 | dump_aud_edid_data(PIPE_B); |
| 1953 | |
| 1954 | dump_aud_infoframe(PIPE_A); |
| 1955 | dump_aud_infoframe(PIPE_B); |
| 1956 | } |
| 1957 | |
| 1958 | #undef VIDEO_DIP_CTL_A |
| 1959 | #undef VIDEO_DIP_CTL_B |
| 1960 | #undef VIDEO_DIP_CTL_C |
| 1961 | #undef VIDEO_DIP_CTL_D |
| 1962 | #undef VIDEO_DIP_DATA |
| 1963 | |
| 1964 | /* |
| 1965 | * Haswell+ display registers |
| 1966 | */ |
| 1967 | |
| 1968 | /* DisplayPort Transport Control */ |
| 1969 | #define DP_TP_CTL_A 0x64040 |
| 1970 | #define DP_TP_CTL_B 0x64140 |
| 1971 | #define DP_TP_CTL_C 0x64240 |
| 1972 | #define DP_TP_CTL_D 0x64340 |
| 1973 | #define DP_TP_CTL_E 0x64440 |
| 1974 | |
| 1975 | /* DisplayPort Transport Status */ |
| 1976 | #define DP_TP_ST_A 0x64044 |
| 1977 | #define DP_TP_ST_B 0x64144 |
| 1978 | #define DP_TP_ST_C 0x64244 |
| 1979 | #define DP_TP_ST_D 0x64344 |
| 1980 | #define DP_TP_ST_E 0x64444 |
| 1981 | |
| 1982 | /* DDI Buffer Control */ |
| 1983 | #define DDI_BUF_CTL_A 0x64000 |
| 1984 | #define DDI_BUF_CTL_B 0x64100 |
| 1985 | #define DDI_BUF_CTL_C 0x64200 |
| 1986 | #define DDI_BUF_CTL_D 0x64300 |
| 1987 | #define DDI_BUF_CTL_E 0x64400 |
| 1988 | |
| 1989 | /* DDI Buffer Translation */ |
| 1990 | #define DDI_BUF_TRANS_A 0x64e00 |
| 1991 | #define DDI_BUF_TRANS_B 0x64e60 |
| 1992 | #define DDI_BUF_TRANS_C 0x64ec0 |
| 1993 | #define DDI_BUF_TRANS_D 0x64f20 |
| 1994 | #define DDI_BUF_TRANS_E 0x64f80 |
| 1995 | |
| 1996 | /* DDI Aux Channel */ |
| 1997 | #define DDI_AUX_CHANNEL_CTRL 0x64010 |
| 1998 | #define DDI_AUX_DATA 0x64014 |
| 1999 | #define DDI_AUX_TST 0x64028 |
| 2000 | |
| 2001 | /* DDI CRC Control */ |
| 2002 | #define DDI_CRC_CTL_A 0x64050 |
| 2003 | #define DDI_CRC_CTL_B 0x64150 |
| 2004 | #define DDI_CRC_CTL_C 0x64250 |
| 2005 | #define DDI_CRC_CTL_D 0x64350 |
| 2006 | #define DDI_CRC_CTL_E 0x64450 |
| 2007 | |
| 2008 | /* Pipe DDI Function Control */ |
| 2009 | #define PIPE_DDI_FUNC_CTL_A 0x60400 |
| 2010 | #define PIPE_DDI_FUNC_CTL_B 0x61400 |
| 2011 | #define PIPE_DDI_FUNC_CTL_C 0x62400 |
| 2012 | #define PIPE_DDI_FUNC_CTL_EDP 0x6F400 |
| 2013 | |
| 2014 | /* Pipe Configuration */ |
| 2015 | #define PIPE_CONF_A 0x70008 |
| 2016 | #define PIPE_CONF_B 0x71008 |
| 2017 | #define PIPE_CONF_C 0x72008 |
| 2018 | #define PIPE_CONF_EDP 0x7F008 |
| 2019 | |
| 2020 | /* Video DIP Control */ |
| 2021 | #define VIDEO_DIP_CTL_A 0x60200 |
| 2022 | #define VIDEO_DIP_CTL_B 0x61200 |
| 2023 | #define VIDEO_DIP_CTL_C 0x62200 |
| 2024 | #define VIDEO_DIP_CTL_D 0x63200 |
| 2025 | |
| 2026 | #define VIDEO_DIP_DATA 0x60220 |
| 2027 | #define VIDEO_DIP_ECC 0x60240 |
| 2028 | |
| 2029 | static void dump_ddi_buf_ctl(int port) |
| 2030 | { |
| 2031 | uint32_t dword; |
| 2032 | |
| 2033 | dword = INREG(DDI_BUF_CTL_A + (port - PORT_A) * 0x100); |
| 2034 | printf("DDI %c Buffer control\n", 'A' + port - PORT_A); |
| 2035 | |
| 2036 | printf("\tDP port width\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 3, 1), |
| 2037 | OPNAME(dp_port_width, BITS(dword, 3, 1))); |
| 2038 | printf("\tDDI Buffer Enable\t\t\t\t%ld\n", BIT(dword, 31)); |
| 2039 | } |
| 2040 | |
| 2041 | static void dump_ddi_func_ctl(int pipe) |
| 2042 | { |
| 2043 | uint32_t dword; |
| 2044 | |
| 2045 | dword = INREG(PIPE_DDI_FUNC_CTL_A + (pipe - PIPE_A) * 0x1000); |
| 2046 | printf("Pipe %c DDI Function Control\n", 'A' + pipe - PIPE_A); |
| 2047 | |
| 2048 | printf("\tBITS per color\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 22, 20), |
| 2049 | OPNAME(bits_per_color, BITS(dword, 22, 20))); |
| 2050 | printf("\tPIPE DDI Mode\t\t\t\t\t[0x%lx] %s\n", BITS(dword, 26, 24), |
| 2051 | OPNAME(ddi_mode, BITS(dword, 26, 24))); |
| 2052 | printf("\tPIPE DDI selection\t\t\t\t[0x%lx] %s\n", BITS(dword, 30, 28), |
| 2053 | OPNAME(trans_to_port_sel, BITS(dword, 30, 28))); |
| 2054 | printf("\tPIPE DDI Function Enable\t\t\t[0x%lx]\n", BIT(dword, 31)); |
| 2055 | } |
| 2056 | |
| 2057 | static void dump_aud_connect_list_entry_length(int transcoder) |
| 2058 | { |
| 2059 | uint32_t dword; |
| 2060 | char prefix[MAX_PREFIX_SIZE]; |
| 2061 | |
| 2062 | dword = INREG(aud_reg_base + AUD_TCA_PIN_PIPE_CONN_ENTRY_LNGTH + (transcoder - TRANSCODER_A) * 0x100); |
| 2063 | sprintf(prefix, "AUD_TC%c_PIN_PIPE_CONN_ENTRY_LNGTH", 'A' + transcoder - TRANSCODER_A); |
| 2064 | |
| 2065 | printf("%s Connect_List_Length\t%lu\n", prefix, BITS(dword, 6, 0)); |
| 2066 | printf("%s Form \t\t[%#lx] %s\n", prefix, BIT(dword, 7), |
| 2067 | OPNAME(connect_list_form, BIT(dword, 7))); |
| 2068 | printf("%s Connect_List_Entry\t%lu\n", prefix, BITS(dword, 15, 8)); |
| 2069 | } |
| 2070 | |
| 2071 | static void dump_aud_connect_select_ctrl(void) |
| 2072 | { |
| 2073 | uint32_t dword; |
| 2074 | |
| 2075 | dword = INREG(aud_reg_base + AUD_PIPE_CONN_SEL_CTRL); |
| 2076 | printf("AUD_PIPE_CONN_SEL_CTRL Connection_select_Port_B\t%#lx\n", BITS(dword, 7, 0)); |
| 2077 | printf("AUD_PIPE_CONN_SEL_CTRL Connection_select_Port_C\t%#lx\n", BITS(dword, 15, 8)); |
| 2078 | printf("AUD_PIPE_CONN_SEL_CTRL Connection_select_Port_D\t%#lx\n", BITS(dword, 23, 16)); |
| 2079 | } |
| 2080 | |
| 2081 | static void dump_aud_dip_eld_ctrl_st(int transcoder) |
| 2082 | { |
| 2083 | uint32_t dword; |
| 2084 | int offset = (transcoder - TRANSCODER_A) * 0x100; |
| 2085 | |
| 2086 | dword = INREG(aud_reg_base + AUD_TCA_DIP_ELD_CTRL_ST + offset); |
| 2087 | printf("Audio DIP and ELD control state for Transcoder %c\n", 'A' + transcoder - TRANSCODER_A); |
| 2088 | |
| 2089 | printf("\tELD_ACK\t\t\t\t\t\t%lu\n", BIT(dword, 4)); |
| 2090 | printf("\tELD_buffer_size\t\t\t\t\t%lu\n", BITS(dword, 14, 10)); |
| 2091 | printf("\tDIP_transmission_frequency\t\t\t[0x%lx] %s\n", BITS(dword, 17, 16), |
| 2092 | dip_trans[BITS(dword, 17, 16)]); |
| 2093 | printf("\tDIP Buffer Index \t\t\t\t[0x%lx] %s\n", BITS(dword, 20, 18), |
| 2094 | dip_index[BITS(dword, 20, 18)]); |
| 2095 | printf("\tAudio DIP type enable status\t\t\t[0x%04lx] %s, %s, %s\n", BITS(dword, 24, 21), |
| 2096 | dip_type[BIT(dword, 21)], dip_gen1_state[BIT(dword, 22)], dip_gen2_state[BIT(dword, 23)]); |
| 2097 | printf("\tAudio DIP port select\t\t\t\t[0x%lx] %s\n", BITS(dword, 30, 29), |
| 2098 | dip_port[BITS(dword, 30, 29)]); |
| 2099 | printf("\n"); |
| 2100 | } |
| 2101 | |
| 2102 | static void dump_aud_hdmi_fifo_status(void) |
| 2103 | { |
| 2104 | uint32_t dword; |
| 2105 | |
| 2106 | dword = INREG(aud_reg_base + AUD_HDMI_FIFO_STATUS); |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2107 | printf("AUD_HDMI_FIFO_STATUS Function_Reset\t\t\t%lu\n", BIT(dword, 24)); |
| 2108 | printf("AUD_HDMI_FIFO_STATUS Conv_1_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 26)); |
| 2109 | printf("AUD_HDMI_FIFO_STATUS Conv_1_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 27)); |
| 2110 | printf("AUD_HDMI_FIFO_STATUS Conv_2_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 28)); |
| 2111 | printf("AUD_HDMI_FIFO_STATUS Conv_2_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 29)); |
| 2112 | printf("AUD_HDMI_FIFO_STATUS Conv_3_CDCLK/DOTCLK_FIFO_Overrun\t%lu\n", BIT(dword, 30)); |
| 2113 | printf("AUD_HDMI_FIFO_STATUS Conv_3_CDCLK/DOTCLK_FIFO_Underrun\t%lu\n", BIT(dword, 31)); |
| 2114 | } |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2115 | |
Mengdong Lin | f075c3c | 2013-08-13 00:22:14 -0400 | [diff] [blame] | 2116 | static void parse_bdw_audio_chicken_bit_reg(uint32_t dword) |
| 2117 | { |
| 2118 | printf("\t"); |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 2119 | printf("%s\n\t", OPNAME(vanilla_dp12_en, BIT(dword, 31))); |
| 2120 | printf("%s\n\t", OPNAME(vanilla_3_widgets_en, BIT(dword, 30))); |
| 2121 | printf("%s\n\t", OPNAME(block_audio, BIT(dword, 10))); |
Mengdong Lin | f075c3c | 2013-08-13 00:22:14 -0400 | [diff] [blame] | 2122 | printf("%s\n\t", OPNAME(dis_eld_valid_pulse_trans, BIT(dword, 9))); |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 2123 | printf("%s\n\t", OPNAME(dis_pd_pulse_trans, BIT(dword, 8))); |
| 2124 | printf("%s\n\t", OPNAME(dis_ts_delta_err, BIT(dword, 7))); |
| 2125 | printf("%s\n\t", OPNAME(dis_ts_fix_dp_hbr, BIT(dword, 6))); |
| 2126 | printf("%s\n\t", OPNAME(pattern_gen_8_ch_en, BIT(dword, 5))); |
| 2127 | printf("%s\n\t", OPNAME(pattern_gen_2_ch_en, BIT(dword, 4))); |
| 2128 | printf("%s\n\t", OPNAME(fabric_32_44_dis, BIT(dword, 3))); |
| 2129 | printf("%s\n\t", OPNAME(epss_dis, BIT(dword, 2))); |
| 2130 | printf("%s\n\t", OPNAME(ts_test_mode, BIT(dword, 1))); |
| 2131 | printf("%s\n", OPNAME(en_mmio_program, BIT(dword, 0))); |
Mengdong Lin | f075c3c | 2013-08-13 00:22:14 -0400 | [diff] [blame] | 2132 | } |
| 2133 | |
Lu, Han | e8e2893 | 2015-02-12 08:41:59 +0800 | [diff] [blame] | 2134 | static void parse_skl_audio_freq_cntrl_reg(uint32_t dword) |
| 2135 | { |
| 2136 | printf("\t"); |
| 2137 | printf("%s\n\t", OPNAME(sdi_operate_mode, BIT(dword, 15))); |
| 2138 | printf("%s\n\t", OPNAME(bclk_96mhz, BIT(dword, 4))); |
| 2139 | printf("%s\n", OPNAME(bclk_48mhz, BIT(dword, 3))); |
| 2140 | } |
| 2141 | |
Mengdong Lin | 69cc00b | 2013-07-17 13:29:17 -0400 | [diff] [blame] | 2142 | /* Dump audio registers for Haswell and its successors (eg. Broadwell). |
| 2143 | * Their register layout are same in the north display engine. |
| 2144 | */ |
| 2145 | static void dump_hsw_plus(void) |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2146 | { |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 2147 | uint32_t dword; |
Mengdong Lin | 97e5cf6 | 2013-08-13 00:22:24 -0400 | [diff] [blame] | 2148 | int i; |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2149 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 2150 | set_aud_reg_base(0x65000); |
| 2151 | |
Yang, Libin | 9917744 | 2015-01-12 01:38:34 +0000 | [diff] [blame] | 2152 | dump_reg(PORT_HOTPLUG_EN, "port hotplug enable"); |
| 2153 | dump_reg(PORT_HOTPLUG_STAT, "port hotplug status"); |
| 2154 | dump_reg(DISPLAY_HOTPLUG_CTL, "display hotplug control"); |
| 2155 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 2156 | /* HSW DDI Buffer */ |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 2157 | dump_reg(DDI_BUF_CTL_A, "DDI Buffer Controler A"); |
| 2158 | dump_reg(DDI_BUF_CTL_B, "DDI Buffer Controler B"); |
| 2159 | dump_reg(DDI_BUF_CTL_C, "DDI Buffer Controler C"); |
| 2160 | dump_reg(DDI_BUF_CTL_D, "DDI Buffer Controler D"); |
| 2161 | dump_reg(DDI_BUF_CTL_E, "DDI Buffer Controler E"); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2162 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 2163 | /* HSW Pipe Function */ |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 2164 | dump_reg(PIPE_CONF_A, "PIPE Configuration A"); |
| 2165 | dump_reg(PIPE_CONF_B, "PIPE Configuration B"); |
| 2166 | dump_reg(PIPE_CONF_C, "PIPE Configuration C"); |
| 2167 | dump_reg(PIPE_CONF_EDP, "PIPE Configuration EDP"); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2168 | |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 2169 | dump_reg(PIPE_DDI_FUNC_CTL_A, "PIPE DDI Function Control A"); |
| 2170 | dump_reg(PIPE_DDI_FUNC_CTL_B, "PIPE DDI Function Control B"); |
| 2171 | dump_reg(PIPE_DDI_FUNC_CTL_C, "PIPE DDI Function Control C"); |
| 2172 | dump_reg(PIPE_DDI_FUNC_CTL_EDP, "PIPE DDI Function Control EDP"); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2173 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 2174 | /* HSW Display port */ |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 2175 | dump_reg(DP_TP_CTL_A, "DisplayPort Transport A Control"); |
| 2176 | dump_reg(DP_TP_CTL_B, "DisplayPort Transport B Control"); |
| 2177 | dump_reg(DP_TP_CTL_C, "DisplayPort Transport C Control"); |
| 2178 | dump_reg(DP_TP_CTL_D, "DisplayPort Transport D Control"); |
| 2179 | dump_reg(DP_TP_CTL_E, "DisplayPort Transport E Control"); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2180 | |
Mengdong Lin | fa8c750 | 2014-03-04 10:13:09 -0500 | [diff] [blame] | 2181 | dump_reg(DP_TP_ST_A, "DisplayPort Transport A Status"); |
| 2182 | dump_reg(DP_TP_ST_B, "DisplayPort Transport B Status"); |
| 2183 | dump_reg(DP_TP_ST_C, "DisplayPort Transport C Status"); |
| 2184 | dump_reg(DP_TP_ST_D, "DisplayPort Transport D Status"); |
| 2185 | dump_reg(DP_TP_ST_E, "DisplayPort Transport E Status"); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2186 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 2187 | /* HSW North Display Audio */ |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 2188 | dump_aud_reg(AUD_TCA_CONFIG, "Audio Configuration - Transcoder A"); |
| 2189 | dump_aud_reg(AUD_TCB_CONFIG, "Audio Configuration - Transcoder B"); |
| 2190 | dump_aud_reg(AUD_TCC_CONFIG, "Audio Configuration - Transcoder C"); |
| 2191 | dump_aud_reg(AUD_C1_MISC_CTRL, "Audio Converter 1 MISC Control"); |
| 2192 | dump_aud_reg(AUD_C2_MISC_CTRL, "Audio Converter 2 MISC Control"); |
| 2193 | dump_aud_reg(AUD_C3_MISC_CTRL, "Audio Converter 3 MISC Control"); |
| 2194 | dump_aud_reg(AUD_VID_DID, "Audio Vendor ID / Device ID"); |
| 2195 | dump_aud_reg(AUD_RID, "Audio Revision ID"); |
| 2196 | dump_aud_reg(AUD_TCA_M_CTS_ENABLE, "Audio M & CTS Programming Enable - Transcoder A"); |
| 2197 | dump_aud_reg(AUD_TCB_M_CTS_ENABLE, "Audio M & CTS Programming Enable - Transcoder B"); |
| 2198 | dump_aud_reg(AUD_TCC_M_CTS_ENABLE, "Audio M & CTS Programming Enable - Transcoder C"); |
| 2199 | dump_aud_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)"); |
| 2200 | dump_aud_reg(AUD_TCA_EDID_DATA, "Audio EDID Data Block - Transcoder A"); |
| 2201 | dump_aud_reg(AUD_TCB_EDID_DATA, "Audio EDID Data Block - Transcoder B"); |
| 2202 | dump_aud_reg(AUD_TCC_EDID_DATA, "Audio EDID Data Block - Transcoder C"); |
Lu, Han | 3e9726b | 2015-06-25 14:39:33 +0800 | [diff] [blame] | 2203 | if (IS_GEN9(devid)) |
Lu, Han | e8e2893 | 2015-02-12 08:41:59 +0800 | [diff] [blame] | 2204 | dump_aud_reg(AUD_FREQ_CNTRL, "Audio BCLK Frequency Control"); |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 2205 | dump_aud_reg(AUD_TCA_INFOFR, "Audio Widget Data Island Packet - Transcoder A"); |
| 2206 | dump_aud_reg(AUD_TCB_INFOFR, "Audio Widget Data Island Packet - Transcoder B"); |
| 2207 | dump_aud_reg(AUD_TCC_INFOFR, "Audio Widget Data Island Packet - Transcoder C"); |
| 2208 | dump_aud_reg(AUD_PIPE_CONV_CFG, "Audio Pipe and Converter Configs"); |
| 2209 | dump_aud_reg(AUD_C1_DIG_CNVT, "Audio Digital Converter - Converter 1"); |
| 2210 | dump_aud_reg(AUD_C2_DIG_CNVT, "Audio Digital Converter - Converter 2"); |
| 2211 | dump_aud_reg(AUD_C3_DIG_CNVT, "Audio Digital Converter - Converter 3"); |
| 2212 | dump_aud_reg(AUD_C1_STR_DESC, "Audio Stream Descriptor Format - Converter 1"); |
| 2213 | dump_aud_reg(AUD_C2_STR_DESC, "Audio Stream Descriptor Format - Converter 2"); |
| 2214 | dump_aud_reg(AUD_C3_STR_DESC, "Audio Stream Descriptor Format - Converter 3"); |
| 2215 | dump_aud_reg(AUD_OUT_CHAN_MAP, "Audio Output Channel Mapping"); |
| 2216 | dump_aud_reg(AUD_TCA_PIN_PIPE_CONN_ENTRY_LNGTH, "Audio Connection List entry and Length - Transcoder A"); |
| 2217 | dump_aud_reg(AUD_TCB_PIN_PIPE_CONN_ENTRY_LNGTH, "Audio Connection List entry and Length - Transcoder B"); |
| 2218 | dump_aud_reg(AUD_TCC_PIN_PIPE_CONN_ENTRY_LNGTH, "Audio Connection List entry and Length - Transcoder C"); |
| 2219 | dump_aud_reg(AUD_PIPE_CONN_SEL_CTRL, "Audio Pipe Connection Select Control"); |
| 2220 | dump_aud_reg(AUD_TCA_DIP_ELD_CTRL_ST, "Audio DIP and ELD control state - Transcoder A"); |
| 2221 | dump_aud_reg(AUD_TCB_DIP_ELD_CTRL_ST, "Audio DIP and ELD control state - Transcoder B"); |
| 2222 | dump_aud_reg(AUD_TCC_DIP_ELD_CTRL_ST, "Audio DIP and ELD control state - Transcoder C"); |
| 2223 | dump_aud_reg(AUD_PIN_ELD_CP_VLD, "Audio pin ELD valid and CP ready status"); |
| 2224 | dump_aud_reg(AUD_HDMI_FIFO_STATUS, "Audio HDMI FIFO Status"); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2225 | |
Mengdong Lin | 8535720 | 2013-08-13 00:21:57 -0400 | [diff] [blame] | 2226 | /* Audio debug registers */ |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 2227 | dump_aud_reg(AUD_ICOI, "Audio Immediate Command Output Interface"); |
| 2228 | dump_aud_reg(AUD_IRII, "Audio Immediate Response Input Interface"); |
| 2229 | dump_aud_reg(AUD_ICS, "Audio Immediate Command Status"); |
| 2230 | dump_aud_reg(AUD_CHICKENBIT_REG, "Audio Chicken Bit Register"); |
| 2231 | dump_aud_reg(AUD_DP_DIP_STATUS, "Audio DP and DIP FIFO Debug Status"); |
| 2232 | dump_aud_reg(AUD_TCA_M_CTS, "Audio M CTS Read Back Transcoder A"); |
| 2233 | dump_aud_reg(AUD_TCB_M_CTS, "Audio M CTS Read Back Transcoder B"); |
| 2234 | dump_aud_reg(AUD_TCC_M_CTS, "Audio M CTS Read Back Transcoder C"); |
Lu, Han | 3e9726b | 2015-06-25 14:39:33 +0800 | [diff] [blame] | 2235 | if (IS_GEN9(devid)) { |
Lu, Han | e8e2893 | 2015-02-12 08:41:59 +0800 | [diff] [blame] | 2236 | dump_aud_reg(AUD_HDA_DMA_REG, "Audio HD Audio DMA Control Register"); |
| 2237 | dump_aud_reg(AUD_HDA_LPIB0_REG, "Audio HD Audio Stream0 Link Position in Buffer"); |
| 2238 | dump_aud_reg(AUD_HDA_LPIB1_REG, "Audio HD Audio Stream1 Link Position in Buffer"); |
| 2239 | dump_aud_reg(AUD_HDA_LPIB2_REG, "Audio HD Audio Stream2 Link Position in Buffer"); |
| 2240 | dump_aud_reg(AUD_HDA_EXTRA_REG, "Audio HD Audio Extra Register"); |
| 2241 | dump_aud_reg(AUD_FPGA_CRC_CTL_A, "Audio FPGA Pipe A CRC Control"); |
| 2242 | dump_aud_reg(AUD_FPGA_CRC_CTL_B, "Audio FPGA Pipe B CRC Control"); |
| 2243 | dump_aud_reg(AUD_FPGA_CRC_CTL_C, "Audio FPGA Pipe C CRC Control"); |
| 2244 | dump_aud_reg(AUD_FPGA_CRC_RESULT_A, "Audio FPGA Pipe A CRC Result"); |
| 2245 | dump_aud_reg(AUD_FPGA_CRC_RESULT_B, "Audio FPGA Pipe B CRC Result"); |
| 2246 | dump_aud_reg(AUD_FPGA_CRC_RESULT_C, "Audio FPGA Pipe C CRC Result"); |
| 2247 | dump_aud_reg(AUD_DFT_MVAL_REG, "Audio DFT M Value Register"); |
| 2248 | dump_aud_reg(AUD_DFT_NVAL_REG, "Audio DFT N Value Register"); |
| 2249 | dump_aud_reg(AUD_DFT_LOAD_REG, "Audio DFT LOAD Register"); |
| 2250 | } |
Mengdong Lin | 8535720 | 2013-08-13 00:21:57 -0400 | [diff] [blame] | 2251 | |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 2252 | printf("\nDetails:\n\n"); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2253 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2254 | dump_ddi_buf_ctl(PORT_A); |
| 2255 | dump_ddi_buf_ctl(PORT_B); |
| 2256 | dump_ddi_buf_ctl(PORT_C); |
| 2257 | dump_ddi_buf_ctl(PORT_D); |
| 2258 | dump_ddi_buf_ctl(PORT_E); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2259 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2260 | dump_ddi_func_ctl(PIPE_A); |
| 2261 | dump_ddi_func_ctl(PIPE_B); |
| 2262 | dump_ddi_func_ctl(PIPE_C); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2263 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2264 | /* audio configuration - details */ |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 2265 | dump_aud_config(TRANSCODER_A); |
| 2266 | dump_aud_config(TRANSCODER_B); |
| 2267 | dump_aud_config(TRANSCODER_C); |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 2268 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2269 | dump_aud_misc_control(CONVERTER_1); |
| 2270 | dump_aud_misc_control(CONVERTER_2); |
| 2271 | dump_aud_misc_control(CONVERTER_3); |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 2272 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2273 | dump_aud_vendor_device_id(); |
| 2274 | dump_aud_revision_id(); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2275 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2276 | dump_aud_m_cts_enable(TRANSCODER_A); |
| 2277 | dump_aud_m_cts_enable(TRANSCODER_B); |
| 2278 | dump_aud_m_cts_enable(TRANSCODER_C); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2279 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2280 | dump_aud_power_state(); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2281 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2282 | dump_aud_edid_data(TRANSCODER_A); |
| 2283 | dump_aud_edid_data(TRANSCODER_B); |
| 2284 | dump_aud_edid_data(TRANSCODER_C); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2285 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2286 | dump_aud_infoframe(TRANSCODER_A); |
| 2287 | dump_aud_infoframe(TRANSCODER_B); |
| 2288 | dump_aud_infoframe(TRANSCODER_C); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2289 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2290 | dump_aud_pipe_conv_cfg(); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2291 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2292 | dump_aud_dig_cnvt(CONVERTER_1); |
| 2293 | dump_aud_dig_cnvt(CONVERTER_2); |
| 2294 | dump_aud_dig_cnvt(CONVERTER_3); |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 2295 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2296 | dump_aud_str_desc(CONVERTER_1); |
| 2297 | dump_aud_str_desc(CONVERTER_2); |
| 2298 | dump_aud_str_desc(CONVERTER_3); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2299 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2300 | dump_aud_out_chan_map(); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2301 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2302 | dump_aud_connect_list_entry_length(TRANSCODER_A); |
| 2303 | dump_aud_connect_list_entry_length(TRANSCODER_B); |
| 2304 | dump_aud_connect_list_entry_length(TRANSCODER_C); |
| 2305 | dump_aud_connect_select_ctrl(); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2306 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2307 | dump_aud_dip_eld_ctrl_st(TRANSCODER_A); |
| 2308 | dump_aud_dip_eld_ctrl_st(TRANSCODER_B); |
| 2309 | dump_aud_dip_eld_ctrl_st(TRANSCODER_C); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2310 | |
Mengdong Lin | deba868 | 2013-09-09 15:38:40 -0400 | [diff] [blame] | 2311 | dump_aud_eld_cp_vld(); |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 2312 | dump_aud_hdmi_fifo_status(); |
Mengdong Lin | 8535720 | 2013-08-13 00:21:57 -0400 | [diff] [blame] | 2313 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 2314 | dword = read_aud_reg(AUD_ICS); |
Mengdong Lin | 8535720 | 2013-08-13 00:21:57 -0400 | [diff] [blame] | 2315 | printf("IRV [%1lx] %s\t", BIT(dword, 1), |
| 2316 | OPNAME(immed_result_valid, BIT(dword, 1))); |
| 2317 | printf("ICB [%1lx] %s\n", BIT(dword, 1), |
| 2318 | OPNAME(immed_cmd_busy, BIT(dword, 0))); |
Mengdong Lin | f075c3c | 2013-08-13 00:22:14 -0400 | [diff] [blame] | 2319 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 2320 | dword = read_aud_reg(AUD_CHICKENBIT_REG); |
Mengdong Lin | f075c3c | 2013-08-13 00:22:14 -0400 | [diff] [blame] | 2321 | printf("AUD_CHICKENBIT_REG Audio Chicken Bits: %08x\n", dword); |
| 2322 | if (IS_BROADWELL(devid)) |
| 2323 | parse_bdw_audio_chicken_bit_reg(dword); |
| 2324 | |
Mengdong Lin | 86d15e0 | 2014-03-03 13:52:06 -0500 | [diff] [blame] | 2325 | dword = read_aud_reg(AUD_DP_DIP_STATUS); |
Mengdong Lin | 97e5cf6 | 2013-08-13 00:22:24 -0400 | [diff] [blame] | 2326 | printf("AUD_DP_DIP_STATUS Audio DP & DIP FIFO Status: %08x\n\t", dword); |
| 2327 | for (i = 31; i >= 0; i--) |
| 2328 | if (BIT(dword, i)) |
| 2329 | printf("%s\n\t", audio_dp_dip_status[i]); |
| 2330 | printf("\n"); |
Lu, Han | e8e2893 | 2015-02-12 08:41:59 +0800 | [diff] [blame] | 2331 | |
| 2332 | dword = read_aud_reg(AUD_FREQ_CNTRL); |
| 2333 | printf("AUD_FREQ_CNTRL Audio BCLK Frequency Control: %08x\n", dword); |
Lu, Han | 3e9726b | 2015-06-25 14:39:33 +0800 | [diff] [blame] | 2334 | if (IS_GEN9(devid)) |
Lu, Han | e8e2893 | 2015-02-12 08:41:59 +0800 | [diff] [blame] | 2335 | parse_skl_audio_freq_cntrl_reg(dword); |
Wang Xingchao | c407722 | 2012-08-15 16:13:38 +0800 | [diff] [blame] | 2336 | } |
| 2337 | |
Yang, Libin | 9917744 | 2015-01-12 01:38:34 +0000 | [diff] [blame] | 2338 | /* offset of hotplug enable */ |
| 2339 | #define PORT_HOTPLUG_EN_OFFSET 0x1110 |
| 2340 | /* offset of hotplug status */ |
| 2341 | #define PORT_HOTPLUG_STAT_OFFSET 0x1114 |
| 2342 | /* offset of hotplug control*/ |
| 2343 | #define DISPLAY_HOTPLUG_CTL_OFFSET 0x1164 |
| 2344 | /* dump the braswell registers for audio */ |
| 2345 | static void dump_braswell(void) |
| 2346 | { |
| 2347 | uint32_t dword; |
| 2348 | |
| 2349 | /* set_aud_reg_base(0x62000 + VLV_DISPLAY_BASE); */ |
| 2350 | set_reg_base(0x60000 + VLV_DISPLAY_BASE, 0x2000); |
| 2351 | |
| 2352 | |
| 2353 | dump_disp_reg(PORT_HOTPLUG_EN_OFFSET, "port hotplug enable"); |
| 2354 | dump_disp_reg(PORT_HOTPLUG_STAT_OFFSET, "port hotplug status"); |
| 2355 | dump_disp_reg(DISPLAY_HOTPLUG_CTL_OFFSET, "display hotplug control"); |
| 2356 | |
| 2357 | dump_disp_reg(BSW_HDMI_CTL_B, "sDVO/HDMI Port B Control"); |
| 2358 | dump_disp_reg(BSW_HDMI_CTL_C, "HDMI Port C Control"); // The address is wrong? |
| 2359 | dump_disp_reg(BSW_HDMI_CTL_D, "HDMI Port D Control"); |
| 2360 | |
| 2361 | dump_disp_reg(DP_CTL_B, "DisplayPort B Control Register"); |
| 2362 | dump_disp_reg(DP_CTL_C, "DisplayPort C Control Register"); |
| 2363 | dump_disp_reg(DP_CTL_D, "DisplayPort D Control Register"); |
| 2364 | |
| 2365 | /* HSW North Display Audio */ |
| 2366 | dump_aud_reg(AUD_TCA_CONFIG, "Audio Configuration - Transcoder A"); |
| 2367 | dump_aud_reg(AUD_TCB_CONFIG, "Audio Configuration - Transcoder B"); |
| 2368 | dump_aud_reg(AUD_TCC_CONFIG, "Audio Configuration - Transcoder C"); |
| 2369 | dump_aud_reg(AUD_C1_MISC_CTRL, "Audio Converter 1 MISC Control"); |
| 2370 | dump_aud_reg(AUD_C2_MISC_CTRL, "Audio Converter 2 MISC Control"); |
| 2371 | dump_aud_reg(AUD_C3_MISC_CTRL, "Audio Converter 3 MISC Control"); |
| 2372 | dump_aud_reg(AUD_VID_DID, "Audio Vendor ID / Device ID"); |
| 2373 | dump_aud_reg(AUD_RID, "Audio Revision ID"); |
| 2374 | dump_aud_reg(AUD_TCA_M_CTS_ENABLE, "Audio M & CTS Programming Enable - Transcoder A"); |
| 2375 | dump_aud_reg(AUD_TCB_M_CTS_ENABLE, "Audio M & CTS Programming Enable - Transcoder B"); |
| 2376 | dump_aud_reg(AUD_TCC_M_CTS_ENABLE, "Audio M & CTS Programming Enable - Transcoder C"); |
| 2377 | dump_aud_reg(AUD_PWRST, "Audio Power State (Function Group, Convertor, Pin Widget)"); |
| 2378 | dump_aud_reg(AUD_TCA_EDID_DATA, "Audio EDID Data Block - Transcoder A"); |
| 2379 | dump_aud_reg(AUD_TCB_EDID_DATA, "Audio EDID Data Block - Transcoder B"); |
| 2380 | dump_aud_reg(AUD_TCC_EDID_DATA, "Audio EDID Data Block - Transcoder C"); |
| 2381 | dump_aud_reg(AUD_TCA_INFOFR, "Audio Widget Data Island Packet - Transcoder A"); |
| 2382 | dump_aud_reg(AUD_TCB_INFOFR, "Audio Widget Data Island Packet - Transcoder B"); |
| 2383 | dump_aud_reg(AUD_TCC_INFOFR, "Audio Widget Data Island Packet - Transcoder C"); |
| 2384 | dump_aud_reg(AUD_PIPE_CONV_CFG, "Audio Pipe and Converter Configs"); |
| 2385 | dump_aud_reg(AUD_C1_DIG_CNVT, "Audio Digital Converter - Converter 1"); |
| 2386 | dump_aud_reg(AUD_C2_DIG_CNVT, "Audio Digital Converter - Converter 2"); |
| 2387 | dump_aud_reg(AUD_C3_DIG_CNVT, "Audio Digital Converter - Converter 3"); |
| 2388 | dump_aud_reg(AUD_C1_STR_DESC, "Audio Stream Descriptor Format - Converter 1"); |
| 2389 | dump_aud_reg(AUD_C2_STR_DESC, "Audio Stream Descriptor Format - Converter 2"); |
| 2390 | dump_aud_reg(AUD_C3_STR_DESC, "Audio Stream Descriptor Format - Converter 3"); |
| 2391 | dump_aud_reg(AUD_OUT_CHAN_MAP, "Audio Output Channel Mapping"); |
| 2392 | dump_aud_reg(AUD_TCA_PIN_PIPE_CONN_ENTRY_LNGTH, "Audio Connection List entry and Length - Transcoder A"); |
| 2393 | dump_aud_reg(AUD_TCB_PIN_PIPE_CONN_ENTRY_LNGTH, "Audio Connection List entry and Length - Transcoder B"); |
| 2394 | dump_aud_reg(AUD_TCC_PIN_PIPE_CONN_ENTRY_LNGTH, "Audio Connection List entry and Length - Transcoder C"); |
| 2395 | dump_aud_reg(AUD_PIPE_CONN_SEL_CTRL, "Audio Pipe Connection Select Control"); |
| 2396 | dump_aud_reg(AUD_TCA_DIP_ELD_CTRL_ST, "Audio DIP and ELD control state - Transcoder A"); |
| 2397 | dump_aud_reg(AUD_TCB_DIP_ELD_CTRL_ST, "Audio DIP and ELD control state - Transcoder B"); |
| 2398 | dump_aud_reg(AUD_TCC_DIP_ELD_CTRL_ST, "Audio DIP and ELD control state - Transcoder C"); |
| 2399 | dump_aud_reg(AUD_PIN_ELD_CP_VLD, "Audio pin ELD valid and CP ready status"); |
| 2400 | dump_aud_reg(AUD_HDMI_FIFO_STATUS, "Audio HDMI FIFO Status"); |
| 2401 | |
| 2402 | /* Audio debug registers */ |
| 2403 | dump_aud_reg(AUD_ICOI, "Audio Immediate Command Output Interface"); |
| 2404 | dump_aud_reg(AUD_IRII, "Audio Immediate Response Input Interface"); |
| 2405 | dump_aud_reg(AUD_ICS, "Audio Immediate Command Status"); |
| 2406 | dump_aud_reg(AUD_CHICKENBIT_REG, "Audio Chicken Bit Register"); |
| 2407 | dump_aud_reg(AUD_DP_DIP_STATUS, "Audio DP and DIP FIFO Debug Status"); |
| 2408 | dump_aud_reg(AUD_TCA_M_CTS, "Audio M CTS Read Back Transcoder A"); |
| 2409 | dump_aud_reg(AUD_TCB_M_CTS, "Audio M CTS Read Back Transcoder B"); |
| 2410 | dump_aud_reg(AUD_TCC_M_CTS, "Audio M CTS Read Back Transcoder C"); |
| 2411 | |
| 2412 | printf("\n"); |
Libin Yang | ebd8b32 | 2015-01-15 09:20:47 +0800 | [diff] [blame] | 2413 | |
| 2414 | printf("\nDetails:\n\n"); |
| 2415 | |
| 2416 | dump_aud_vendor_device_id(); |
| 2417 | dump_aud_revision_id(); |
| 2418 | |
| 2419 | dump_hdmi_port_ctrl(PORT_B); |
| 2420 | dump_hdmi_port_ctrl(PORT_C); |
| 2421 | if (!IS_VALLEYVIEW(devid)) |
| 2422 | dump_hdmi_port_ctrl(PORT_D); |
| 2423 | |
| 2424 | dump_dp_port_ctrl(PORT_B); |
| 2425 | dump_dp_port_ctrl(PORT_C); |
| 2426 | if (!IS_VALLEYVIEW(devid)) |
| 2427 | dump_dp_port_ctrl(PORT_D); |
| 2428 | |
| 2429 | dump_aud_config(PIPE_A); |
| 2430 | dump_aud_config(PIPE_B); |
| 2431 | |
| 2432 | dump_aud_m_cts_enable(PIPE_A); |
| 2433 | dump_aud_m_cts_enable(PIPE_B); |
| 2434 | |
| 2435 | dump_aud_misc_control(PIPE_A); |
| 2436 | dump_aud_misc_control(PIPE_B); |
| 2437 | |
| 2438 | dump_aud_power_state(); |
| 2439 | dump_aud_port_en_hd_cfg(); |
| 2440 | |
| 2441 | dump_aud_dig_cnvt(PIPE_A); |
| 2442 | dump_aud_dig_cnvt(PIPE_B); |
| 2443 | |
| 2444 | dump_aud_out_ch_str(); |
| 2445 | |
| 2446 | dump_aud_str_desc(PIPE_A); |
| 2447 | dump_aud_str_desc(PIPE_B); |
| 2448 | |
| 2449 | dump_aud_connect_list(); |
| 2450 | dump_aud_connect_select(); |
| 2451 | |
| 2452 | dump_aud_ctrl_state(PIPE_A); |
| 2453 | dump_aud_ctrl_state(PIPE_B); |
| 2454 | dump_aud_ctrl_state2(); |
| 2455 | |
| 2456 | dump_aud_hdmi_status(); |
| 2457 | |
| 2458 | dump_aud_edid_data(PIPE_A); |
| 2459 | dump_aud_edid_data(PIPE_B); |
| 2460 | |
| 2461 | dump_aud_infoframe(PIPE_A); |
| 2462 | dump_aud_infoframe(PIPE_B); |
Yang, Libin | 9917744 | 2015-01-12 01:38:34 +0000 | [diff] [blame] | 2463 | } |
| 2464 | |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 2465 | int main(int argc, char **argv) |
| 2466 | { |
| 2467 | struct pci_device *pci_dev; |
| 2468 | |
| 2469 | pci_dev = intel_get_pci_device(); |
| 2470 | devid = pci_dev->device_id; /* XXX not true when mapping! */ |
| 2471 | |
| 2472 | do_self_tests(); |
| 2473 | |
| 2474 | if (argc == 2) |
Daniel Vetter | 2d4656f | 2014-03-22 22:23:04 +0100 | [diff] [blame] | 2475 | intel_mmio_use_dump_file(argv[1]); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 2476 | else |
Daniel Vetter | 2d4656f | 2014-03-22 22:23:04 +0100 | [diff] [blame] | 2477 | intel_mmio_use_pci_bar(pci_dev); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 2478 | |
Mengdong Lin | 449509d | 2014-03-03 17:03:02 -0500 | [diff] [blame] | 2479 | if (IS_VALLEYVIEW(devid)) { |
| 2480 | printf("Valleyview audio registers:\n\n"); |
| 2481 | dump_ironlake(); |
Lu, Han | 3e9726b | 2015-06-25 14:39:33 +0800 | [diff] [blame] | 2482 | } else if (IS_GEN9(devid) |
Lu, Han | e8e2893 | 2015-02-12 08:41:59 +0800 | [diff] [blame] | 2483 | || IS_BROADWELL(devid) || IS_HASWELL(devid)) { |
Mengdong Lin | 69cc00b | 2013-07-17 13:29:17 -0400 | [diff] [blame] | 2484 | printf("%s audio registers:\n\n", |
Lu, Han | 3e9726b | 2015-06-25 14:39:33 +0800 | [diff] [blame] | 2485 | IS_BROXTON(devid) ? "Broxton" : |
| 2486 | (IS_SKYLAKE(devid) ? "Skylake" : |
| 2487 | (IS_BROADWELL(devid) ? "Broadwell" : "Haswell"))); |
Mengdong Lin | 69cc00b | 2013-07-17 13:29:17 -0400 | [diff] [blame] | 2488 | dump_hsw_plus(); |
| 2489 | } else if (IS_GEN6(devid) || IS_GEN7(devid) |
| 2490 | || getenv("HAS_PCH_SPLIT")) { |
Wu Fengguang | 6fcb5cd | 2011-11-12 11:12:49 +0800 | [diff] [blame] | 2491 | printf("%s audio registers:\n\n", |
Mengdong Lin | 3c7dc5c | 2013-09-09 15:38:32 -0400 | [diff] [blame] | 2492 | IS_GEN6(devid) ? "SandyBridge" : "IvyBridge"); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 2493 | intel_check_pch(); |
| 2494 | dump_cpt(); |
Wu Fengguang | 6fcb5cd | 2011-11-12 11:12:49 +0800 | [diff] [blame] | 2495 | } else if (IS_GEN5(devid)) { |
| 2496 | printf("Ironlake audio registers:\n\n"); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 2497 | dump_ironlake(); |
Wu Fengguang | 6fcb5cd | 2011-11-12 11:12:49 +0800 | [diff] [blame] | 2498 | } else if (IS_G4X(devid)) { |
| 2499 | printf("G45 audio registers:\n\n"); |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 2500 | dump_eaglelake(); |
Yang, Libin | 9917744 | 2015-01-12 01:38:34 +0000 | [diff] [blame] | 2501 | } else if (IS_CHERRYVIEW(devid)) { |
| 2502 | printf("Braswell audio registers:\n\n"); |
| 2503 | dump_braswell(); |
Wu Fengguang | 6fcb5cd | 2011-11-12 11:12:49 +0800 | [diff] [blame] | 2504 | } |
Wu Fengguang | 020abdb | 2010-04-19 13:13:06 +0800 | [diff] [blame] | 2505 | |
| 2506 | return 0; |
Wu Fengguang | 9e9c9f2 | 2009-11-06 11:06:22 +0800 | [diff] [blame] | 2507 | } |