sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 1 | |
| 2 | /*---------------------------------------------------------------*/ |
| 3 | /*--- ---*/ |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 4 | /*--- This file (main/vex_main.c) is ---*/ |
sewardj | dbcfae7 | 2005-08-02 11:14:04 +0000 | [diff] [blame] | 5 | /*--- Copyright (C) OpenWorks LLP. All rights reserved. ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 6 | /*--- ---*/ |
| 7 | /*---------------------------------------------------------------*/ |
| 8 | |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 9 | /* |
| 10 | This file is part of LibVEX, a library for dynamic binary |
| 11 | instrumentation and translation. |
| 12 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 13 | Copyright (C) 2004-2005 OpenWorks LLP. All rights reserved. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 14 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 15 | This library is made available under a dual licensing scheme. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 16 | |
sewardj | 7bd6ffe | 2005-08-03 16:07:36 +0000 | [diff] [blame] | 17 | If you link LibVEX against other code all of which is itself |
| 18 | licensed under the GNU General Public License, version 2 dated June |
| 19 | 1991 ("GPL v2"), then you may use LibVEX under the terms of the GPL |
| 20 | v2, as appearing in the file LICENSE.GPL. If the file LICENSE.GPL |
| 21 | is missing, you can obtain a copy of the GPL v2 from the Free |
| 22 | Software Foundation Inc., 51 Franklin St, Fifth Floor, Boston, MA |
| 23 | 02110-1301, USA. |
| 24 | |
| 25 | For any other uses of LibVEX, you must first obtain a commercial |
| 26 | license from OpenWorks LLP. Please contact info@open-works.co.uk |
| 27 | for information about commercial licensing. |
| 28 | |
| 29 | This software is provided by OpenWorks LLP "as is" and any express |
| 30 | or implied warranties, including, but not limited to, the implied |
| 31 | warranties of merchantability and fitness for a particular purpose |
| 32 | are disclaimed. In no event shall OpenWorks LLP be liable for any |
| 33 | direct, indirect, incidental, special, exemplary, or consequential |
| 34 | damages (including, but not limited to, procurement of substitute |
| 35 | goods or services; loss of use, data, or profits; or business |
| 36 | interruption) however caused and on any theory of liability, |
| 37 | whether in contract, strict liability, or tort (including |
| 38 | negligence or otherwise) arising in any way out of the use of this |
| 39 | software, even if advised of the possibility of such damage. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 40 | |
| 41 | Neither the names of the U.S. Department of Energy nor the |
| 42 | University of California nor the names of its contributors may be |
| 43 | used to endorse or promote products derived from this software |
| 44 | without prior written permission. |
sewardj | f8ed9d8 | 2004-11-12 17:40:23 +0000 | [diff] [blame] | 45 | */ |
| 46 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 47 | #include "libvex.h" |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 48 | #include "libvex_emwarn.h" |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 49 | #include "libvex_guest_x86.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 50 | #include "libvex_guest_amd64.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 51 | #include "libvex_guest_arm.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 52 | #include "libvex_guest_ppc32.h" |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 53 | #include "libvex_guest_ppc64.h" |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 54 | |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 55 | #include "main/vex_globals.h" |
| 56 | #include "main/vex_util.h" |
| 57 | #include "host-generic/h_generic_regs.h" |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 58 | #include "ir/iropt.h" |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 59 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 60 | #include "host-x86/hdefs.h" |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 61 | #include "host-amd64/hdefs.h" |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 62 | #include "host-ppc32/hdefs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 63 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 64 | #include "guest-generic/bb_to_IR.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 65 | #include "guest-x86/gdefs.h" |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 66 | #include "guest-amd64/gdefs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 67 | #include "guest-arm/gdefs.h" |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 68 | #include "guest-ppc32/gdefs.h" |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 69 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 70 | |
| 71 | /* This file contains the top level interface to the library. */ |
| 72 | |
| 73 | /* --------- Initialise the library. --------- */ |
| 74 | |
| 75 | /* Exported to library client. */ |
| 76 | |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 77 | const HChar* LibVEX_Version ( void ) |
sewardj | 80f5fce | 2004-12-20 04:37:50 +0000 | [diff] [blame] | 78 | { |
| 79 | return |
| 80 | #include "main/vex_svnversion.h" |
| 81 | ; |
| 82 | } |
| 83 | |
| 84 | |
| 85 | /* Exported to library client. */ |
| 86 | |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 87 | void LibVEX_default_VexControl ( /*OUT*/ VexControl* vcon ) |
| 88 | { |
| 89 | vcon->iropt_verbosity = 0; |
| 90 | vcon->iropt_level = 2; |
| 91 | vcon->iropt_precise_memory_exns = False; |
| 92 | vcon->iropt_unroll_thresh = 120; |
sewardj | 18b4bb7 | 2005-03-29 21:32:41 +0000 | [diff] [blame] | 93 | vcon->guest_max_insns = 60; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 94 | vcon->guest_chase_thresh = 10; |
| 95 | } |
| 96 | |
| 97 | |
| 98 | /* Exported to library client. */ |
| 99 | |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 100 | void LibVEX_Init ( |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 101 | /* failure exit function */ |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 102 | __attribute__ ((noreturn)) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 103 | void (*failure_exit) ( void ), |
| 104 | /* logging output function */ |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 105 | void (*log_bytes) ( HChar*, Int nbytes ), |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 106 | /* debug paranoia level */ |
| 107 | Int debuglevel, |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 108 | /* Are we supporting valgrind checking? */ |
| 109 | Bool valgrind_support, |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 110 | /* Control ... */ |
| 111 | /*READONLY*/VexControl* vcon |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 112 | ) |
| 113 | { |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 114 | /* First off, do enough minimal setup so that the following |
| 115 | assertions can fail in a sane fashion, if need be. */ |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 116 | vex_failure_exit = failure_exit; |
| 117 | vex_log_bytes = log_bytes; |
| 118 | |
| 119 | /* Now it's safe to check parameters for sanity. */ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 120 | vassert(!vex_initdone); |
| 121 | vassert(failure_exit); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 122 | vassert(log_bytes); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 123 | vassert(debuglevel >= 0); |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 124 | |
| 125 | vassert(vcon->iropt_verbosity >= 0); |
| 126 | vassert(vcon->iropt_level >= 0); |
| 127 | vassert(vcon->iropt_level <= 2); |
| 128 | vassert(vcon->iropt_unroll_thresh >= 0); |
| 129 | vassert(vcon->iropt_unroll_thresh <= 400); |
| 130 | vassert(vcon->guest_max_insns >= 1); |
| 131 | vassert(vcon->guest_max_insns <= 100); |
| 132 | vassert(vcon->guest_chase_thresh >= 0); |
| 133 | vassert(vcon->guest_chase_thresh < vcon->guest_max_insns); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 134 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 135 | /* Check that Vex has been built with sizes of basic types as |
| 136 | stated in priv/libvex_basictypes.h. Failure of any of these is |
| 137 | a serious configuration error and should be corrected |
| 138 | immediately. If any of these assertions fail you can fully |
| 139 | expect Vex not to work properly, if at all. */ |
| 140 | |
| 141 | vassert(1 == sizeof(UChar)); |
| 142 | vassert(1 == sizeof(Char)); |
| 143 | vassert(2 == sizeof(UShort)); |
| 144 | vassert(2 == sizeof(Short)); |
| 145 | vassert(4 == sizeof(UInt)); |
| 146 | vassert(4 == sizeof(Int)); |
| 147 | vassert(8 == sizeof(ULong)); |
| 148 | vassert(8 == sizeof(Long)); |
| 149 | vassert(4 == sizeof(Float)); |
| 150 | vassert(8 == sizeof(Double)); |
| 151 | vassert(1 == sizeof(Bool)); |
| 152 | vassert(4 == sizeof(Addr32)); |
| 153 | vassert(8 == sizeof(Addr64)); |
sewardj | c9a4366 | 2004-11-30 18:51:59 +0000 | [diff] [blame] | 154 | vassert(16 == sizeof(U128)); |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 155 | |
| 156 | vassert(sizeof(void*) == 4 || sizeof(void*) == 8); |
| 157 | vassert(sizeof(void*) == sizeof(int*)); |
| 158 | vassert(sizeof(void*) == sizeof(HWord)); |
| 159 | |
sewardj | 97e8793 | 2005-02-07 00:00:50 +0000 | [diff] [blame] | 160 | vassert(VEX_HOST_WORDSIZE == sizeof(void*)); |
| 161 | vassert(VEX_HOST_WORDSIZE == sizeof(HWord)); |
| 162 | |
sewardj | ea602bc | 2004-10-14 21:40:12 +0000 | [diff] [blame] | 163 | /* Really start up .. */ |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 164 | vex_debuglevel = debuglevel; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 165 | vex_valgrind_support = valgrind_support; |
sewardj | 0861374 | 2004-10-25 13:01:45 +0000 | [diff] [blame] | 166 | vex_control = *vcon; |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 167 | vex_initdone = True; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 168 | vexSetAllocMode ( VexAllocModeTEMP ); |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 169 | } |
| 170 | |
| 171 | |
| 172 | /* --------- Make a translation. --------- */ |
| 173 | |
| 174 | /* Exported to library client. */ |
| 175 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 176 | VexTranslateResult LibVEX_Translate ( VexTranslateArgs* vta ) |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 177 | { |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 178 | /* This the bundle of functions we need to do the back-end stuff |
| 179 | (insn selection, reg-alloc, assembly) whilst being insulated |
| 180 | from the target instruction set. */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 181 | HReg* available_real_regs; |
| 182 | Int n_available_real_regs; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 183 | Bool (*isMove) ( HInstr*, HReg*, HReg* ); |
| 184 | void (*getRegUsage) ( HRegUsage*, HInstr*, Bool ); |
| 185 | void (*mapRegs) ( HRegRemap*, HInstr*, Bool ); |
| 186 | HInstr* (*genSpill) ( HReg, Int, Bool ); |
| 187 | HInstr* (*genReload) ( HReg, Int, Bool ); |
| 188 | void (*ppInstr) ( HInstr*, Bool ); |
sewardj | 443cd9d | 2004-07-18 23:06:45 +0000 | [diff] [blame] | 189 | void (*ppReg) ( HReg ); |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 190 | HInstrArray* (*iselBB) ( IRBB*, VexArchInfo* ); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 191 | Int (*emit) ( UChar*, Int, HInstr*, Bool, void* ); |
sewardj | d976362 | 2005-02-07 03:12:19 +0000 | [diff] [blame] | 192 | IRExpr* (*specHelper) ( HChar*, IRExpr** ); |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 193 | Bool (*preciseMemExnsFn) ( Int, Int ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 194 | |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 195 | DisOneInstrFn disInstrFn; |
| 196 | |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 197 | VexGuestLayout* guest_layout; |
| 198 | Bool host_is_bigendian = False; |
| 199 | IRBB* irbb; |
| 200 | HInstrArray* vcode; |
| 201 | HInstrArray* rcode; |
| 202 | Int i, j, k, out_used, guest_sizeB; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 203 | Int offB_TISTART, offB_TILEN; |
sewardj | eeac841 | 2004-11-02 00:26:55 +0000 | [diff] [blame] | 204 | UChar insn_bytes[32]; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 205 | IRType guest_word_type; |
| 206 | IRType host_word_type; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 207 | Bool mode64; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 208 | |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 209 | guest_layout = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 210 | available_real_regs = NULL; |
| 211 | n_available_real_regs = 0; |
| 212 | isMove = NULL; |
| 213 | getRegUsage = NULL; |
| 214 | mapRegs = NULL; |
| 215 | genSpill = NULL; |
| 216 | genReload = NULL; |
| 217 | ppInstr = NULL; |
| 218 | ppReg = NULL; |
| 219 | iselBB = NULL; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 220 | emit = NULL; |
sewardj | 84ff065 | 2004-08-23 16:16:08 +0000 | [diff] [blame] | 221 | specHelper = NULL; |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 222 | preciseMemExnsFn = NULL; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 223 | disInstrFn = NULL; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 224 | guest_word_type = Ity_INVALID; |
| 225 | host_word_type = Ity_INVALID; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 226 | offB_TISTART = 0; |
| 227 | offB_TILEN = 0; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 228 | mode64 = False; |
sewardj | 36ca513 | 2004-07-24 13:12:23 +0000 | [diff] [blame] | 229 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 230 | vex_traceflags = vta->traceflags; |
sewardj | 58800ff | 2004-07-28 01:51:10 +0000 | [diff] [blame] | 231 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 232 | vassert(vex_initdone); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 233 | vexSetAllocModeTEMP_and_clear(); |
| 234 | vexAllocSanityCheck(); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 235 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 236 | /* First off, check that the guest and host insn sets |
| 237 | are supported. */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 238 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 239 | switch (vta->arch_host) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 240 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 241 | case VexArchX86: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 242 | mode64 = False; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 243 | getAllocableRegs_X86 ( &n_available_real_regs, |
| 244 | &available_real_regs ); |
| 245 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_X86Instr; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 246 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_X86Instr; |
| 247 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_X86Instr; |
| 248 | genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_X86; |
| 249 | genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_X86; |
| 250 | ppInstr = (void(*)(HInstr*, Bool)) ppX86Instr; |
sewardj | 2b51587 | 2004-07-05 20:50:45 +0000 | [diff] [blame] | 251 | ppReg = (void(*)(HReg)) ppHRegX86; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 252 | iselBB = iselBB_X86; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 253 | emit = emit_X86Instr; |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 254 | host_is_bigendian = False; |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 255 | host_word_type = Ity_I32; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 256 | vassert(vta->archinfo_host.subarch == VexSubArchX86_sse0 |
| 257 | || vta->archinfo_host.subarch == VexSubArchX86_sse1 |
| 258 | || vta->archinfo_host.subarch == VexSubArchX86_sse2); |
| 259 | vassert(vta->dispatch != NULL); /* jump-to-dispatcher scheme */ |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 260 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 261 | |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 262 | case VexArchAMD64: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 263 | mode64 = True; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 264 | getAllocableRegs_AMD64 ( &n_available_real_regs, |
| 265 | &available_real_regs ); |
| 266 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_AMD64Instr; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 267 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_AMD64Instr; |
| 268 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_AMD64Instr; |
| 269 | genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_AMD64; |
| 270 | genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_AMD64; |
| 271 | ppInstr = (void(*)(HInstr*, Bool)) ppAMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 272 | ppReg = (void(*)(HReg)) ppHRegAMD64; |
| 273 | iselBB = iselBB_AMD64; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 274 | emit = (Int(*)(UChar*,Int,HInstr*, Bool)) emit_AMD64Instr; |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 275 | host_is_bigendian = False; |
| 276 | host_word_type = Ity_I64; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 277 | vassert(vta->archinfo_host.subarch == VexSubArch_NONE); |
| 278 | vassert(vta->dispatch != NULL); /* jump-to-dispatcher scheme */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 279 | break; |
| 280 | |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 281 | case VexArchPPC32: |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 282 | mode64 = False; |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 283 | getAllocableRegs_PPC32 ( &n_available_real_regs, |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 284 | &available_real_regs, mode64 ); |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 285 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPC32Instr; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 286 | getRegUsage = (void(*)(HRegUsage*,HInstr*,Bool)) getRegUsage_PPC32Instr; |
| 287 | mapRegs = (void(*)(HRegRemap*,HInstr*,Bool)) mapRegs_PPC32Instr; |
| 288 | genSpill = (HInstr*(*)(HReg,Int,Bool)) genSpill_PPC32; |
| 289 | genReload = (HInstr*(*)(HReg,Int,Bool)) genReload_PPC32; |
| 290 | ppInstr = (void(*)(HInstr*,Bool)) ppPPC32Instr; |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 291 | ppReg = (void(*)(HReg)) ppHRegPPC32; |
| 292 | iselBB = iselBB_PPC32; |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 293 | emit = (Int(*)(UChar*,Int,HInstr*,Bool)) emit_PPC32Instr; |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 294 | host_is_bigendian = True; |
| 295 | host_word_type = Ity_I32; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 296 | vassert(vta->archinfo_guest.subarch == VexSubArchPPC32_I |
| 297 | || vta->archinfo_guest.subarch == VexSubArchPPC32_FI |
| 298 | || vta->archinfo_guest.subarch == VexSubArchPPC32_VFI); |
| 299 | vassert(vta->dispatch == NULL); /* return-to-dispatcher scheme */ |
cerion | 487e4c9 | 2005-02-04 16:28:19 +0000 | [diff] [blame] | 300 | break; |
| 301 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 302 | case VexArchPPC64: |
| 303 | mode64 = True; |
| 304 | getAllocableRegs_PPC32 ( &n_available_real_regs, |
| 305 | &available_real_regs, mode64 ); |
| 306 | isMove = (Bool(*)(HInstr*,HReg*,HReg*)) isMove_PPC32Instr; |
| 307 | getRegUsage = (void(*)(HRegUsage*,HInstr*, Bool)) getRegUsage_PPC32Instr; |
| 308 | mapRegs = (void(*)(HRegRemap*,HInstr*, Bool)) mapRegs_PPC32Instr; |
| 309 | genSpill = (HInstr*(*)(HReg,Int, Bool)) genSpill_PPC32; |
| 310 | genReload = (HInstr*(*)(HReg,Int, Bool)) genReload_PPC32; |
| 311 | ppInstr = (void(*)(HInstr*, Bool)) ppPPC32Instr; |
| 312 | ppReg = (void(*)(HReg)) ppHRegPPC32; |
| 313 | iselBB = iselBB_PPC32; |
| 314 | emit = (Int(*)(UChar*,Int,HInstr*, Bool)) emit_PPC32Instr; |
| 315 | host_is_bigendian = True; |
| 316 | host_word_type = Ity_I64; |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 317 | vassert(vta->archinfo_guest.subarch == VexSubArchPPC64_FI |
| 318 | || vta->archinfo_guest.subarch == VexSubArchPPC64_VFI); |
| 319 | vassert(vta->dispatch == NULL); /* return-to-dispatcher scheme */ |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 320 | break; |
| 321 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 322 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 323 | vpanic("LibVEX_Translate: unsupported target insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 324 | } |
| 325 | |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 326 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 327 | switch (vta->arch_guest) { |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 328 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 329 | case VexArchX86: |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 330 | preciseMemExnsFn = guest_x86_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 331 | disInstrFn = disInstr_X86; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 332 | specHelper = guest_x86_spechelper; |
sewardj | 81ec418 | 2004-10-25 23:15:52 +0000 | [diff] [blame] | 333 | guest_sizeB = sizeof(VexGuestX86State); |
sewardj | cf78790 | 2004-11-03 09:08:33 +0000 | [diff] [blame] | 334 | guest_word_type = Ity_I32; |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 335 | guest_layout = &x86guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 336 | offB_TISTART = offsetof(VexGuestX86State,guest_TISTART); |
| 337 | offB_TILEN = offsetof(VexGuestX86State,guest_TILEN); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 338 | vassert(vta->archinfo_guest.subarch == VexSubArchX86_sse0 |
| 339 | || vta->archinfo_guest.subarch == VexSubArchX86_sse1 |
| 340 | || vta->archinfo_guest.subarch == VexSubArchX86_sse2); |
sewardj | e74f6f7 | 2005-08-05 02:55:36 +0000 | [diff] [blame] | 341 | vassert(0 == sizeof(VexGuestX86State) % 8); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 342 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TISTART ) == 4); |
| 343 | vassert(sizeof( ((VexGuestX86State*)0)->guest_TILEN ) == 4); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 344 | break; |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 345 | |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 346 | case VexArchAMD64: |
| 347 | preciseMemExnsFn = guest_amd64_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 348 | disInstrFn = disInstr_AMD64; |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 349 | specHelper = guest_amd64_spechelper; |
| 350 | guest_sizeB = sizeof(VexGuestAMD64State); |
| 351 | guest_word_type = Ity_I64; |
| 352 | guest_layout = &amd64guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 353 | offB_TISTART = offsetof(VexGuestAMD64State,guest_TISTART); |
| 354 | offB_TILEN = offsetof(VexGuestAMD64State,guest_TILEN); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 355 | vassert(vta->archinfo_guest.subarch == VexSubArch_NONE); |
sewardj | e74f6f7 | 2005-08-05 02:55:36 +0000 | [diff] [blame] | 356 | vassert(0 == sizeof(VexGuestAMD64State) % 8); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 357 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TISTART ) == 8); |
| 358 | vassert(sizeof( ((VexGuestAMD64State*)0)->guest_TILEN ) == 8); |
sewardj | 44d494d | 2005-01-20 20:26:33 +0000 | [diff] [blame] | 359 | break; |
| 360 | |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 361 | case VexArchARM: |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 362 | preciseMemExnsFn = guest_arm_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 363 | disInstrFn = NULL; /* HACK */ |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 364 | specHelper = guest_arm_spechelper; |
| 365 | guest_sizeB = sizeof(VexGuestARMState); |
| 366 | guest_word_type = Ity_I32; |
| 367 | guest_layout = &armGuest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 368 | offB_TISTART = 0; /* hack ... arm has bitrot */ |
| 369 | offB_TILEN = 0; /* hack ... arm has bitrot */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 370 | vassert(vta->archinfo_guest.subarch == VexSubArchARM_v4); |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 371 | break; |
| 372 | |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 373 | case VexArchPPC32: |
| 374 | preciseMemExnsFn = guest_ppc32_state_requires_precise_mem_exns; |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 375 | disInstrFn = disInstr_PPC32; |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 376 | specHelper = guest_ppc32_spechelper; |
| 377 | guest_sizeB = sizeof(VexGuestPPC32State); |
| 378 | guest_word_type = Ity_I32; |
| 379 | guest_layout = &ppc32Guest_layout; |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 380 | offB_TISTART = offsetof(VexGuestPPC32State,guest_TISTART); |
| 381 | offB_TILEN = offsetof(VexGuestPPC32State,guest_TILEN); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 382 | vassert(vta->archinfo_guest.subarch == VexSubArchPPC32_I |
| 383 | || vta->archinfo_guest.subarch == VexSubArchPPC32_FI |
| 384 | || vta->archinfo_guest.subarch == VexSubArchPPC32_VFI); |
sewardj | e74f6f7 | 2005-08-05 02:55:36 +0000 | [diff] [blame] | 385 | vassert(0 == sizeof(VexGuestPPC32State) % 8); |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 386 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TISTART ) == 4); |
| 387 | vassert(sizeof( ((VexGuestPPC32State*)0)->guest_TILEN ) == 4); |
cerion | aabdfbf | 2005-01-29 12:56:15 +0000 | [diff] [blame] | 388 | break; |
| 389 | |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 390 | case VexArchPPC64: |
| 391 | preciseMemExnsFn = guest_ppc64_state_requires_precise_mem_exns; |
| 392 | disInstrFn = disInstr_PPC32; |
| 393 | specHelper = guest_ppc64_spechelper; |
| 394 | guest_sizeB = sizeof(VexGuestPPC64State); |
| 395 | guest_word_type = Ity_I64; |
| 396 | guest_layout = &ppc64Guest_layout; |
| 397 | offB_TISTART = offsetof(VexGuestPPC64State,guest_TISTART); |
| 398 | offB_TILEN = offsetof(VexGuestPPC64State,guest_TILEN); |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 399 | vassert(vta->archinfo_guest.subarch == VexSubArchPPC64_FI |
| 400 | || vta->archinfo_guest.subarch == VexSubArchPPC64_VFI); |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 401 | vassert(0 == sizeof(VexGuestPPC64State) % 16); |
| 402 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TISTART ) == 8); |
| 403 | vassert(sizeof( ((VexGuestPPC64State*)0)->guest_TILEN ) == 8); |
| 404 | break; |
| 405 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 406 | default: |
sewardj | 887a11a | 2004-07-05 17:26:47 +0000 | [diff] [blame] | 407 | vpanic("LibVEX_Translate: unsupported guest insn set"); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 408 | } |
| 409 | |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 410 | /* yet more sanity checks ... */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 411 | if (vta->arch_guest == vta->arch_host) { |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 412 | /* doesn't necessarily have to be true, but if it isn't it means |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 413 | we are simulating one flavour of an architecture a different |
| 414 | flavour of the same architecture, which is pretty strange. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 415 | vassert(vta->archinfo_guest.subarch == vta->archinfo_host.subarch); |
sewardj | 9df271d | 2004-12-31 22:37:42 +0000 | [diff] [blame] | 416 | } |
sewardj | 2a9ad02 | 2004-11-25 02:46:58 +0000 | [diff] [blame] | 417 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 418 | vexAllocSanityCheck(); |
| 419 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 420 | if (vex_traceflags & VEX_TRACE_FE) |
| 421 | vex_printf("\n------------------------" |
| 422 | " Front end " |
| 423 | "------------------------\n\n"); |
| 424 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 425 | irbb = bb_to_IR ( vta->guest_extents, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 426 | disInstrFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 427 | vta->guest_bytes, |
| 428 | vta->guest_bytes_addr, |
| 429 | vta->chase_into_ok, |
sewardj | 9e6491a | 2005-07-02 19:24:10 +0000 | [diff] [blame] | 430 | host_is_bigendian, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 431 | &vta->archinfo_guest, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 432 | guest_word_type, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 433 | vta->do_self_check, |
sewardj | db4738a | 2005-07-07 01:32:16 +0000 | [diff] [blame] | 434 | offB_TISTART, |
| 435 | offB_TILEN ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 436 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 437 | vexAllocSanityCheck(); |
| 438 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 439 | if (irbb == NULL) { |
| 440 | /* Access failure. */ |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 441 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 442 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 443 | return VexTransAccessFail; |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 444 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 445 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 446 | vassert(vta->guest_extents->n_used >= 1 && vta->guest_extents->n_used <= 3); |
| 447 | vassert(vta->guest_extents->base[0] == vta->guest_bytes_addr); |
| 448 | for (i = 0; i < vta->guest_extents->n_used; i++) { |
| 449 | vassert(vta->guest_extents->len[i] < 10000); /* sanity */ |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 450 | } |
| 451 | |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 452 | /* If debugging, show the raw guest bytes for this bb. */ |
sewardj | 109ffdb | 2004-12-10 21:45:38 +0000 | [diff] [blame] | 453 | if (0 || (vex_traceflags & VEX_TRACE_FE)) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 454 | if (vta->guest_extents->n_used > 1) { |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 455 | vex_printf("can't show code due to extents > 1\n"); |
| 456 | } else { |
| 457 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 458 | UChar* p = (UChar*)vta->guest_bytes; |
| 459 | UInt guest_bytes_read = (UInt)vta->guest_extents->len[0]; |
| 460 | vex_printf(". 0 %llx %u\n.", vta->guest_bytes_addr, guest_bytes_read ); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 461 | for (i = 0; i < guest_bytes_read; i++) |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 462 | vex_printf(" %02x", (Int)p[i] ); |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 463 | vex_printf("\n\n"); |
| 464 | } |
sewardj | aa59f94 | 2004-10-09 09:34:36 +0000 | [diff] [blame] | 465 | } |
| 466 | |
| 467 | /* Sanity check the initial IR. */ |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 468 | sanityCheckIRBB( irbb, "initial IR", |
| 469 | False/*can be non-flat*/, guest_word_type ); |
sewardj | e8e9d73 | 2004-07-16 21:03:45 +0000 | [diff] [blame] | 470 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 471 | vexAllocSanityCheck(); |
| 472 | |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 473 | /* Clean it up, hopefully a lot. */ |
sewardj | 8d2291c | 2004-10-25 14:50:21 +0000 | [diff] [blame] | 474 | irbb = do_iropt_BB ( irbb, specHelper, preciseMemExnsFn, |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 475 | vta->guest_bytes_addr ); |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 476 | sanityCheckIRBB( irbb, "after initial iropt", |
| 477 | True/*must be flat*/, guest_word_type ); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 478 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 479 | if (vex_traceflags & VEX_TRACE_OPT1) { |
| 480 | vex_printf("\n------------------------" |
| 481 | " After pre-instr IR optimisation " |
| 482 | "------------------------\n\n"); |
sewardj | edf4d69 | 2004-08-17 13:52:58 +0000 | [diff] [blame] | 483 | ppIRBB ( irbb ); |
| 484 | vex_printf("\n"); |
| 485 | } |
| 486 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 487 | vexAllocSanityCheck(); |
| 488 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 489 | /* Get the thing instrumented. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 490 | if (vta->instrument1) |
| 491 | irbb = vta->instrument1(irbb, guest_layout, |
| 492 | vta->guest_bytes_addr_noredir, |
| 493 | vta->guest_extents, |
| 494 | guest_word_type, host_word_type); |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 495 | vexAllocSanityCheck(); |
| 496 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 497 | if (vta->instrument2) |
| 498 | irbb = vta->instrument2(irbb, guest_layout, |
| 499 | vta->guest_bytes_addr_noredir, |
| 500 | vta->guest_extents, |
| 501 | guest_word_type, host_word_type); |
sewardj | 49651f4 | 2004-10-28 22:11:04 +0000 | [diff] [blame] | 502 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 503 | if (vex_traceflags & VEX_TRACE_INST) { |
| 504 | vex_printf("\n------------------------" |
| 505 | " After instrumentation " |
| 506 | "------------------------\n\n"); |
| 507 | ppIRBB ( irbb ); |
| 508 | vex_printf("\n"); |
| 509 | } |
| 510 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 511 | if (vta->instrument1 || vta->instrument2) |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 512 | sanityCheckIRBB( irbb, "after instrumentation", |
| 513 | True/*must be flat*/, guest_word_type ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 514 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 515 | /* Do a post-instrumentation cleanup pass. */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 516 | if (vta->instrument1 || vta->instrument2) { |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 517 | do_deadcode_BB( irbb ); |
| 518 | irbb = cprop_BB( irbb ); |
| 519 | do_deadcode_BB( irbb ); |
sewardj | b923075 | 2004-12-29 19:25:06 +0000 | [diff] [blame] | 520 | sanityCheckIRBB( irbb, "after post-instrumentation cleanup", |
| 521 | True/*must be flat*/, guest_word_type ); |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 522 | } |
| 523 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 524 | vexAllocSanityCheck(); |
| 525 | |
sewardj | 9578a8b | 2004-11-04 19:44:48 +0000 | [diff] [blame] | 526 | if (vex_traceflags & VEX_TRACE_OPT2) { |
| 527 | vex_printf("\n------------------------" |
| 528 | " After post-instr IR optimisation " |
| 529 | "------------------------\n\n"); |
| 530 | ppIRBB ( irbb ); |
| 531 | vex_printf("\n"); |
| 532 | } |
| 533 | |
sewardj | f9517d0 | 2005-11-28 13:39:37 +0000 | [diff] [blame] | 534 | /* Turn it into virtual-registerised code. Build trees -- this |
| 535 | also throws away any dead bindings. */ |
| 536 | ado_treebuild_BB( irbb ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 537 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 538 | vexAllocSanityCheck(); |
| 539 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 540 | if (vex_traceflags & VEX_TRACE_TREES) { |
| 541 | vex_printf("\n------------------------" |
| 542 | " After tree-building " |
| 543 | "------------------------\n\n"); |
| 544 | ppIRBB ( irbb ); |
| 545 | vex_printf("\n"); |
| 546 | } |
| 547 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 548 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 549 | if (0) { *(vta->host_bytes_used) = 0; return VexTransOK; } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 550 | /* end HACK */ |
sewardj | c33671d | 2005-02-01 20:30:00 +0000 | [diff] [blame] | 551 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 552 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 553 | vex_printf("\n------------------------" |
| 554 | " Instruction selection " |
| 555 | "------------------------\n"); |
| 556 | |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 557 | vcode = iselBB ( irbb, &vta->archinfo_host ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 558 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 559 | vexAllocSanityCheck(); |
| 560 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 561 | if (vex_traceflags & VEX_TRACE_VCODE) |
| 562 | vex_printf("\n"); |
| 563 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 564 | if (vex_traceflags & VEX_TRACE_VCODE) { |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 565 | for (i = 0; i < vcode->arr_used; i++) { |
| 566 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 567 | ppInstr(vcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 568 | vex_printf("\n"); |
| 569 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 570 | vex_printf("\n"); |
| 571 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 572 | |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 573 | /* Register allocate. */ |
| 574 | rcode = doRegisterAllocation ( vcode, available_real_regs, |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 575 | n_available_real_regs, |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 576 | isMove, getRegUsage, mapRegs, |
| 577 | genSpill, genReload, guest_sizeB, |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 578 | ppInstr, ppReg, mode64 ); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 579 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 580 | vexAllocSanityCheck(); |
| 581 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 582 | if (vex_traceflags & VEX_TRACE_RCODE) { |
| 583 | vex_printf("\n------------------------" |
| 584 | " Register-allocated code " |
| 585 | "------------------------\n\n"); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 586 | for (i = 0; i < rcode->arr_used; i++) { |
| 587 | vex_printf("%3d ", i); |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 588 | ppInstr(rcode->arr[i], mode64); |
sewardj | 1f40a0a | 2004-07-21 12:28:07 +0000 | [diff] [blame] | 589 | vex_printf("\n"); |
| 590 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 591 | vex_printf("\n"); |
| 592 | } |
sewardj | fbcaf33 | 2004-07-08 01:46:01 +0000 | [diff] [blame] | 593 | |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 594 | /* HACK */ |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 595 | if (0) { *(vta->host_bytes_used) = 0; return VexTransOK; } |
sewardj | e908c42 | 2005-02-04 21:18:16 +0000 | [diff] [blame] | 596 | /* end HACK */ |
| 597 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 598 | /* Assemble */ |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 599 | if (vex_traceflags & VEX_TRACE_ASM) { |
| 600 | vex_printf("\n------------------------" |
| 601 | " Assembly " |
| 602 | "------------------------\n\n"); |
| 603 | } |
| 604 | |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 605 | out_used = 0; /* tracks along the host_bytes array */ |
| 606 | for (i = 0; i < rcode->arr_used; i++) { |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 607 | if (vex_traceflags & VEX_TRACE_ASM) { |
cerion | 92b6436 | 2005-12-13 12:02:26 +0000 | [diff] [blame] | 608 | ppInstr(rcode->arr[i], mode64); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 609 | vex_printf("\n"); |
| 610 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 611 | j = (*emit)( insn_bytes, 32, rcode->arr[i], mode64, vta->dispatch ); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 612 | if (vex_traceflags & VEX_TRACE_ASM) { |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 613 | for (k = 0; k < j; k++) |
sewardj | 72c7281 | 2005-01-19 11:49:45 +0000 | [diff] [blame] | 614 | if (insn_bytes[k] < 16) |
sewardj | 86898e8 | 2004-07-22 17:26:12 +0000 | [diff] [blame] | 615 | vex_printf("0%x ", (UInt)insn_bytes[k]); |
| 616 | else |
| 617 | vex_printf("%x ", (UInt)insn_bytes[k]); |
sewardj | bad34a9 | 2004-07-22 01:14:11 +0000 | [diff] [blame] | 618 | vex_printf("\n\n"); |
| 619 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 620 | if (out_used + j > vta->host_bytes_size) { |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 621 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 622 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 623 | return VexTransOutputFull; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 624 | } |
| 625 | for (k = 0; k < j; k++) { |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 626 | vta->host_bytes[out_used] = insn_bytes[k]; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 627 | out_used++; |
| 628 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 629 | vassert(out_used <= vta->host_bytes_size); |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 630 | } |
sewardj | 17c7f95 | 2005-12-15 14:02:34 +0000 | [diff] [blame^] | 631 | *(vta->host_bytes_used) = out_used; |
sewardj | 81bd550 | 2004-07-21 18:49:27 +0000 | [diff] [blame] | 632 | |
sewardj | 2d6b14a | 2005-11-23 04:25:07 +0000 | [diff] [blame] | 633 | vexAllocSanityCheck(); |
| 634 | |
| 635 | vexSetAllocModeTEMP_and_clear(); |
sewardj | f13a16a | 2004-07-05 17:10:14 +0000 | [diff] [blame] | 636 | |
sewardj | f48ac19 | 2004-10-29 00:41:29 +0000 | [diff] [blame] | 637 | vex_traceflags = 0; |
sewardj | d887b86 | 2005-01-17 18:34:34 +0000 | [diff] [blame] | 638 | return VexTransOK; |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 639 | } |
| 640 | |
| 641 | |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 642 | /* --------- Emulation warnings. --------- */ |
| 643 | |
| 644 | HChar* LibVEX_EmWarn_string ( VexEmWarn ew ) |
| 645 | { |
| 646 | switch (ew) { |
| 647 | case EmWarn_NONE: |
| 648 | return "none"; |
| 649 | case EmWarn_X86_x87exns: |
| 650 | return "Unmasking x87 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 651 | case EmWarn_X86_x87precision: |
| 652 | return "Selection of non-80-bit x87 FP precision"; |
| 653 | case EmWarn_X86_sseExns: |
sewardj | 5edfc26 | 2004-12-15 12:13:52 +0000 | [diff] [blame] | 654 | return "Unmasking SSE FP exceptions"; |
| 655 | case EmWarn_X86_fz: |
| 656 | return "Setting %mxcsr.fz (SSE flush-underflows-to-zero mode)"; |
| 657 | case EmWarn_X86_daz: |
| 658 | return "Setting %mxcsr.daz (SSE treat-denormals-as-zero mode)"; |
sewardj | 6d26984 | 2005-08-06 11:45:02 +0000 | [diff] [blame] | 659 | case EmWarn_X86_acFlag: |
| 660 | return "Setting %eflags.ac (setting noted but ignored)"; |
cerion | 094d139 | 2005-06-20 13:45:57 +0000 | [diff] [blame] | 661 | case EmWarn_PPC32exns: |
| 662 | return "Unmasking PPC32 FP exceptions"; |
sewardj | 893aada | 2004-11-29 19:57:54 +0000 | [diff] [blame] | 663 | default: |
| 664 | vpanic("LibVEX_EmWarn_string: unknown warning"); |
| 665 | } |
| 666 | } |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 667 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 668 | /* --------- Arch/Subarch stuff. --------- */ |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 669 | |
| 670 | const HChar* LibVEX_ppVexArch ( VexArch arch ) |
| 671 | { |
| 672 | switch (arch) { |
| 673 | case VexArch_INVALID: return "INVALID"; |
| 674 | case VexArchX86: return "X86"; |
| 675 | case VexArchAMD64: return "AMD64"; |
| 676 | case VexArchARM: return "ARM"; |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 677 | case VexArchPPC32: return "PPC32"; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 678 | case VexArchPPC64: return "PPC64"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 679 | default: return "VexArch???"; |
| 680 | } |
| 681 | } |
| 682 | |
| 683 | const HChar* LibVEX_ppVexSubArch ( VexSubArch subarch ) |
| 684 | { |
| 685 | switch (subarch) { |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 686 | case VexSubArch_INVALID: return "INVALID"; |
| 687 | case VexSubArch_NONE: return "NONE"; |
| 688 | case VexSubArchX86_sse0: return "x86-sse0"; |
| 689 | case VexSubArchX86_sse1: return "x86-sse1"; |
| 690 | case VexSubArchX86_sse2: return "x86-sse2"; |
| 691 | case VexSubArchARM_v4: return "arm-v4"; |
sewardj | 059601a | 2005-11-13 00:53:05 +0000 | [diff] [blame] | 692 | case VexSubArchPPC32_I: return "ppc32-int-only"; |
| 693 | case VexSubArchPPC32_FI: return "ppc32-int-and-fp"; |
| 694 | case VexSubArchPPC32_VFI: return "ppc32-int-fp-and-AV"; |
cerion | f0de28c | 2005-12-13 20:21:11 +0000 | [diff] [blame] | 695 | case VexSubArchPPC64_FI: return "ppc64-int-and-fp"; |
| 696 | case VexSubArchPPC64_VFI: return "ppc64-int-fp-and-AV"; |
sewardj | 0ec57c5 | 2005-02-01 15:24:10 +0000 | [diff] [blame] | 697 | default: return "VexSubArch???"; |
sewardj | bef170b | 2004-12-21 01:23:00 +0000 | [diff] [blame] | 698 | } |
| 699 | } |
| 700 | |
sewardj | 27e1dd6 | 2005-06-30 11:49:14 +0000 | [diff] [blame] | 701 | /* Write default settings info *vai. */ |
| 702 | void LibVEX_default_VexArchInfo ( /*OUT*/VexArchInfo* vai ) |
| 703 | { |
| 704 | vai->subarch = VexSubArch_INVALID; |
| 705 | vai->ppc32_cache_line_szB = 0; |
| 706 | } |
| 707 | |
| 708 | |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 709 | /*---------------------------------------------------------------*/ |
sewardj | c0ee2ed | 2004-07-27 10:29:41 +0000 | [diff] [blame] | 710 | /*--- end main/vex_main.c ---*/ |
sewardj | 35421a3 | 2004-07-05 13:12:34 +0000 | [diff] [blame] | 711 | /*---------------------------------------------------------------*/ |