blob: 42ac7069b365e41bf0c6d801406ef86026ba3cbd [file] [log] [blame]
Chia-I Wub2755562014-08-20 13:38:52 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wub2755562014-08-20 13:38:52 +080027 */
28
Chia-I Wu9f039862014-08-20 15:39:56 +080029#include "genhw/genhw.h"
Chia-I Wu714df452015-01-01 07:55:04 +080030#include "buf.h"
Chia-I Wuf8385062015-01-04 16:27:24 +080031#include "desc.h"
Chia-I Wu7fae4e32014-08-21 11:39:44 +080032#include "img.h"
Chia-I Wub2755562014-08-20 13:38:52 +080033#include "mem.h"
Chia-I Wu018a3962014-08-21 10:37:52 +080034#include "pipeline.h"
Chia-I Wufc05a2e2014-10-07 00:34:13 +080035#include "sampler.h"
Chia-I Wu1f2fd292014-08-29 15:07:09 +080036#include "shader.h"
Chia-I Wub2755562014-08-20 13:38:52 +080037#include "state.h"
38#include "view.h"
39#include "cmd_priv.h"
Jon Ashburnc04b4dc2015-01-08 18:48:10 -070040#include "fb.h"
Chia-I Wub2755562014-08-20 13:38:52 +080041
Chia-I Wu59c097e2014-08-21 10:51:07 +080042static void gen6_3DPRIMITIVE(struct intel_cmd *cmd,
Chia-I Wu254db422014-08-21 11:54:29 +080043 int prim_type, bool indexed,
Chia-I Wu59c097e2014-08-21 10:51:07 +080044 uint32_t vertex_count,
45 uint32_t vertex_start,
46 uint32_t instance_count,
47 uint32_t instance_start,
48 uint32_t vertex_base)
49{
50 const uint8_t cmd_len = 6;
Chia-I Wu72292b72014-09-09 10:48:33 +080051 uint32_t dw0, *dw;
Chia-I Wu59c097e2014-08-21 10:51:07 +080052
53 CMD_ASSERT(cmd, 6, 6);
54
Chia-I Wu426072d2014-08-26 14:31:55 +080055 dw0 = GEN6_RENDER_CMD(3D, 3DPRIMITIVE) |
Chia-I Wu254db422014-08-21 11:54:29 +080056 prim_type << GEN6_3DPRIM_DW0_TYPE__SHIFT |
Chia-I Wu59c097e2014-08-21 10:51:07 +080057 (cmd_len - 2);
58
59 if (indexed)
60 dw0 |= GEN6_3DPRIM_DW0_ACCESS_RANDOM;
61
Chia-I Wu72292b72014-09-09 10:48:33 +080062 cmd_batch_pointer(cmd, cmd_len, &dw);
63 dw[0] = dw0;
64 dw[1] = vertex_count;
65 dw[2] = vertex_start;
66 dw[3] = instance_count;
67 dw[4] = instance_start;
68 dw[5] = vertex_base;
Chia-I Wu59c097e2014-08-21 10:51:07 +080069}
70
71static void gen7_3DPRIMITIVE(struct intel_cmd *cmd,
Chia-I Wu254db422014-08-21 11:54:29 +080072 int prim_type, bool indexed,
Chia-I Wu59c097e2014-08-21 10:51:07 +080073 uint32_t vertex_count,
74 uint32_t vertex_start,
75 uint32_t instance_count,
76 uint32_t instance_start,
77 uint32_t vertex_base)
78{
79 const uint8_t cmd_len = 7;
Chia-I Wu72292b72014-09-09 10:48:33 +080080 uint32_t dw0, dw1, *dw;
Chia-I Wu59c097e2014-08-21 10:51:07 +080081
82 CMD_ASSERT(cmd, 7, 7.5);
83
Chia-I Wu426072d2014-08-26 14:31:55 +080084 dw0 = GEN6_RENDER_CMD(3D, 3DPRIMITIVE) | (cmd_len - 2);
Chia-I Wu254db422014-08-21 11:54:29 +080085 dw1 = prim_type << GEN7_3DPRIM_DW1_TYPE__SHIFT;
Chia-I Wu59c097e2014-08-21 10:51:07 +080086
87 if (indexed)
88 dw1 |= GEN7_3DPRIM_DW1_ACCESS_RANDOM;
89
Chia-I Wu72292b72014-09-09 10:48:33 +080090 cmd_batch_pointer(cmd, cmd_len, &dw);
91 dw[0] = dw0;
92 dw[1] = dw1;
93 dw[2] = vertex_count;
94 dw[3] = vertex_start;
95 dw[4] = instance_count;
96 dw[5] = instance_start;
97 dw[6] = vertex_base;
Chia-I Wu59c097e2014-08-21 10:51:07 +080098}
99
Chia-I Wu270b1e82014-08-25 15:53:39 +0800100static void gen6_PIPE_CONTROL(struct intel_cmd *cmd, uint32_t dw1,
Chia-I Wud6d079d2014-08-31 13:14:21 +0800101 struct intel_bo *bo, uint32_t bo_offset,
102 uint64_t imm)
Chia-I Wu270b1e82014-08-25 15:53:39 +0800103{
104 const uint8_t cmd_len = 5;
Chia-I Wu426072d2014-08-26 14:31:55 +0800105 const uint32_t dw0 = GEN6_RENDER_CMD(3D, PIPE_CONTROL) |
Chia-I Wu270b1e82014-08-25 15:53:39 +0800106 (cmd_len - 2);
Chia-I Wu2caf7492014-08-31 12:28:38 +0800107 uint32_t reloc_flags = INTEL_RELOC_WRITE;
Chia-I Wu72292b72014-09-09 10:48:33 +0800108 uint32_t *dw;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600109 uint32_t pos;
Chia-I Wu270b1e82014-08-25 15:53:39 +0800110
111 CMD_ASSERT(cmd, 6, 7.5);
112
113 assert(bo_offset % 8 == 0);
114
115 if (dw1 & GEN6_PIPE_CONTROL_CS_STALL) {
116 /*
117 * From the Sandy Bridge PRM, volume 2 part 1, page 73:
118 *
119 * "1 of the following must also be set (when CS stall is set):
120 *
121 * * Depth Cache Flush Enable ([0] of DW1)
122 * * Stall at Pixel Scoreboard ([1] of DW1)
123 * * Depth Stall ([13] of DW1)
124 * * Post-Sync Operation ([13] of DW1)
125 * * Render Target Cache Flush Enable ([12] of DW1)
126 * * Notify Enable ([8] of DW1)"
127 *
128 * From the Ivy Bridge PRM, volume 2 part 1, page 61:
129 *
130 * "One of the following must also be set (when CS stall is set):
131 *
132 * * Render Target Cache Flush Enable ([12] of DW1)
133 * * Depth Cache Flush Enable ([0] of DW1)
134 * * Stall at Pixel Scoreboard ([1] of DW1)
135 * * Depth Stall ([13] of DW1)
136 * * Post-Sync Operation ([13] of DW1)"
137 */
138 uint32_t bit_test = GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
139 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
140 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL |
141 GEN6_PIPE_CONTROL_DEPTH_STALL;
142
143 /* post-sync op */
144 bit_test |= GEN6_PIPE_CONTROL_WRITE_IMM |
145 GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT |
146 GEN6_PIPE_CONTROL_WRITE_TIMESTAMP;
147
148 if (cmd_gen(cmd) == INTEL_GEN(6))
149 bit_test |= GEN6_PIPE_CONTROL_NOTIFY_ENABLE;
150
151 assert(dw1 & bit_test);
152 }
153
154 if (dw1 & GEN6_PIPE_CONTROL_DEPTH_STALL) {
155 /*
156 * From the Sandy Bridge PRM, volume 2 part 1, page 73:
157 *
158 * "Following bits must be clear (when Depth Stall is set):
159 *
160 * * Render Target Cache Flush Enable ([12] of DW1)
161 * * Depth Cache Flush Enable ([0] of DW1)"
162 */
163 assert(!(dw1 & (GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
164 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH)));
165 }
166
167 /*
168 * From the Sandy Bridge PRM, volume 1 part 3, page 19:
169 *
170 * "[DevSNB] PPGTT memory writes by MI_* (such as MI_STORE_DATA_IMM)
171 * and PIPE_CONTROL are not supported."
172 *
173 * The kernel will add the mapping automatically (when write domain is
174 * INTEL_DOMAIN_INSTRUCTION).
175 */
Chia-I Wu2caf7492014-08-31 12:28:38 +0800176 if (cmd_gen(cmd) == INTEL_GEN(6) && bo) {
Chia-I Wu270b1e82014-08-25 15:53:39 +0800177 bo_offset |= GEN6_PIPE_CONTROL_DW2_USE_GGTT;
Chia-I Wu2caf7492014-08-31 12:28:38 +0800178 reloc_flags |= INTEL_RELOC_GGTT;
179 }
Chia-I Wu270b1e82014-08-25 15:53:39 +0800180
Chia-I Wu72292b72014-09-09 10:48:33 +0800181 pos = cmd_batch_pointer(cmd, cmd_len, &dw);
182 dw[0] = dw0;
183 dw[1] = dw1;
184 dw[2] = 0;
185 dw[3] = (uint32_t) imm;
186 dw[4] = (uint32_t) (imm >> 32);
187
188 if (bo) {
189 cmd_reserve_reloc(cmd, 1);
190 cmd_batch_reloc(cmd, pos + 2, bo, bo_offset, reloc_flags);
191 }
Chia-I Wu270b1e82014-08-25 15:53:39 +0800192}
193
Chia-I Wu254db422014-08-21 11:54:29 +0800194static bool gen6_can_primitive_restart(const struct intel_cmd *cmd)
195{
196 const struct intel_pipeline *p = cmd->bind.pipeline.graphics;
197 bool supported;
198
199 CMD_ASSERT(cmd, 6, 7.5);
200
201 if (cmd_gen(cmd) >= INTEL_GEN(7.5))
202 return (p->prim_type != GEN6_3DPRIM_RECTLIST);
203
204 switch (p->prim_type) {
205 case GEN6_3DPRIM_POINTLIST:
206 case GEN6_3DPRIM_LINELIST:
207 case GEN6_3DPRIM_LINESTRIP:
208 case GEN6_3DPRIM_TRILIST:
209 case GEN6_3DPRIM_TRISTRIP:
210 supported = true;
211 break;
212 default:
213 supported = false;
214 break;
215 }
216
217 if (!supported)
218 return false;
219
220 switch (cmd->bind.index.type) {
221 case XGL_INDEX_8:
222 supported = (p->primitive_restart_index != 0xffu);
223 break;
224 case XGL_INDEX_16:
225 supported = (p->primitive_restart_index != 0xffffu);
226 break;
227 case XGL_INDEX_32:
228 supported = (p->primitive_restart_index != 0xffffffffu);
229 break;
230 default:
231 supported = false;
232 break;
233 }
234
235 return supported;
236}
237
Chia-I Wu59c097e2014-08-21 10:51:07 +0800238static void gen6_3DSTATE_INDEX_BUFFER(struct intel_cmd *cmd,
Chia-I Wu714df452015-01-01 07:55:04 +0800239 const struct intel_buf *buf,
Chia-I Wu59c097e2014-08-21 10:51:07 +0800240 XGL_GPU_SIZE offset,
241 XGL_INDEX_TYPE type,
242 bool enable_cut_index)
243{
244 const uint8_t cmd_len = 3;
Chia-I Wu72292b72014-09-09 10:48:33 +0800245 uint32_t dw0, end_offset, *dw;
Chia-I Wu59c097e2014-08-21 10:51:07 +0800246 unsigned offset_align;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600247 uint32_t pos;
Chia-I Wu59c097e2014-08-21 10:51:07 +0800248
249 CMD_ASSERT(cmd, 6, 7.5);
250
Chia-I Wu426072d2014-08-26 14:31:55 +0800251 dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_INDEX_BUFFER) | (cmd_len - 2);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800252
253 /* the bit is moved to 3DSTATE_VF */
254 if (cmd_gen(cmd) >= INTEL_GEN(7.5))
255 assert(!enable_cut_index);
256 if (enable_cut_index)
257 dw0 |= GEN6_IB_DW0_CUT_INDEX_ENABLE;
258
259 switch (type) {
260 case XGL_INDEX_8:
261 dw0 |= GEN6_IB_DW0_FORMAT_BYTE;
262 offset_align = 1;
263 break;
264 case XGL_INDEX_16:
265 dw0 |= GEN6_IB_DW0_FORMAT_WORD;
266 offset_align = 2;
267 break;
268 case XGL_INDEX_32:
269 dw0 |= GEN6_IB_DW0_FORMAT_DWORD;
270 offset_align = 4;
271 break;
272 default:
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700273 cmd_fail(cmd, XGL_ERROR_INVALID_VALUE);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800274 return;
275 break;
276 }
277
278 if (offset % offset_align) {
Chia-I Wu4e5577a2015-02-10 11:04:44 -0700279 cmd_fail(cmd, XGL_ERROR_INVALID_VALUE);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800280 return;
281 }
282
283 /* aligned and inclusive */
Chia-I Wu714df452015-01-01 07:55:04 +0800284 end_offset = buf->size - (buf->size % offset_align) - 1;
Chia-I Wu59c097e2014-08-21 10:51:07 +0800285
Chia-I Wu72292b72014-09-09 10:48:33 +0800286 pos = cmd_batch_pointer(cmd, cmd_len, &dw);
287 dw[0] = dw0;
288
289 cmd_reserve_reloc(cmd, 2);
Chia-I Wu714df452015-01-01 07:55:04 +0800290 cmd_batch_reloc(cmd, pos + 1, buf->obj.mem->bo, offset, 0);
291 cmd_batch_reloc(cmd, pos + 2, buf->obj.mem->bo, end_offset, 0);
Chia-I Wu59c097e2014-08-21 10:51:07 +0800292}
293
Chia-I Wu62a7f252014-08-29 11:31:16 +0800294static void gen75_3DSTATE_VF(struct intel_cmd *cmd,
295 bool enable_cut_index,
296 uint32_t cut_index)
Chia-I Wu254db422014-08-21 11:54:29 +0800297{
298 const uint8_t cmd_len = 2;
Chia-I Wu72292b72014-09-09 10:48:33 +0800299 uint32_t dw0, *dw;
Chia-I Wu254db422014-08-21 11:54:29 +0800300
301 CMD_ASSERT(cmd, 7.5, 7.5);
302
Chia-I Wu426072d2014-08-26 14:31:55 +0800303 dw0 = GEN75_RENDER_CMD(3D, 3DSTATE_VF) | (cmd_len - 2);
Chia-I Wu254db422014-08-21 11:54:29 +0800304 if (enable_cut_index)
305 dw0 |= GEN75_VF_DW0_CUT_INDEX_ENABLE;
306
Chia-I Wu72292b72014-09-09 10:48:33 +0800307 cmd_batch_pointer(cmd, cmd_len, &dw);
308 dw[0] = dw0;
309 dw[1] = cut_index;
Chia-I Wu254db422014-08-21 11:54:29 +0800310}
311
Courtney Goeltzenleuchter3d72e8c2014-08-29 16:27:47 -0600312
Chia-I Wud95aa2b2014-08-29 12:07:47 +0800313static void gen6_3DSTATE_GS(struct intel_cmd *cmd)
314{
315 const uint8_t cmd_len = 7;
316 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (cmd_len - 2);
Chia-I Wu72292b72014-09-09 10:48:33 +0800317 uint32_t *dw;
Chia-I Wud95aa2b2014-08-29 12:07:47 +0800318
319 CMD_ASSERT(cmd, 6, 6);
320
Chia-I Wu72292b72014-09-09 10:48:33 +0800321 cmd_batch_pointer(cmd, cmd_len, &dw);
322 dw[0] = dw0;
323 dw[1] = 0;
324 dw[2] = 0;
325 dw[3] = 0;
326 dw[4] = 1 << GEN6_GS_DW4_URB_READ_LEN__SHIFT;
327 dw[5] = GEN6_GS_DW5_STATISTICS;
328 dw[6] = 0;
Chia-I Wud95aa2b2014-08-29 12:07:47 +0800329}
330
Chia-I Wu62a7f252014-08-29 11:31:16 +0800331static void gen7_3DSTATE_GS(struct intel_cmd *cmd)
332{
333 const uint8_t cmd_len = 7;
334 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (cmd_len - 2);
Chia-I Wu72292b72014-09-09 10:48:33 +0800335 uint32_t *dw;
Chia-I Wu62a7f252014-08-29 11:31:16 +0800336
337 CMD_ASSERT(cmd, 7, 7.5);
338
Chia-I Wu72292b72014-09-09 10:48:33 +0800339 cmd_batch_pointer(cmd, cmd_len, &dw);
340 dw[0] = dw0;
341 dw[1] = 0;
342 dw[2] = 0;
343 dw[3] = 0;
344 dw[4] = 0;
345 dw[5] = GEN6_GS_DW5_STATISTICS;
346 dw[6] = 0;
Chia-I Wu62a7f252014-08-29 11:31:16 +0800347}
348
Chia-I Wud88e02d2014-08-25 10:56:13 +0800349static void gen6_3DSTATE_DRAWING_RECTANGLE(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600350 uint32_t width, uint32_t height)
Chia-I Wud88e02d2014-08-25 10:56:13 +0800351{
352 const uint8_t cmd_len = 4;
Chia-I Wu426072d2014-08-26 14:31:55 +0800353 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_DRAWING_RECTANGLE) |
Chia-I Wud88e02d2014-08-25 10:56:13 +0800354 (cmd_len - 2);
Chia-I Wu72292b72014-09-09 10:48:33 +0800355 uint32_t *dw;
Chia-I Wud88e02d2014-08-25 10:56:13 +0800356
357 CMD_ASSERT(cmd, 6, 7.5);
358
Chia-I Wu72292b72014-09-09 10:48:33 +0800359 cmd_batch_pointer(cmd, cmd_len, &dw);
360 dw[0] = dw0;
361
Chia-I Wud88e02d2014-08-25 10:56:13 +0800362 if (width && height) {
Chia-I Wu72292b72014-09-09 10:48:33 +0800363 dw[1] = 0;
364 dw[2] = (height - 1) << 16 |
365 (width - 1);
Chia-I Wud88e02d2014-08-25 10:56:13 +0800366 } else {
Chia-I Wu72292b72014-09-09 10:48:33 +0800367 dw[1] = 1;
368 dw[2] = 0;
Chia-I Wud88e02d2014-08-25 10:56:13 +0800369 }
Chia-I Wu72292b72014-09-09 10:48:33 +0800370
371 dw[3] = 0;
Chia-I Wud88e02d2014-08-25 10:56:13 +0800372}
373
Chia-I Wu8016a172014-08-29 18:31:32 +0800374static void gen7_fill_3DSTATE_SF_body(const struct intel_cmd *cmd,
375 uint32_t body[6])
376{
377 const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
Tony Barbourfa6cac72015-01-16 14:27:35 -0700378 const struct intel_dynamic_rs *raster = cmd->bind.state.raster;
Chia-I Wu8016a172014-08-29 18:31:32 +0800379 uint32_t dw1, dw2, dw3;
380 int point_width;
381
382 CMD_ASSERT(cmd, 6, 7.5);
383
384 dw1 = GEN7_SF_DW1_STATISTICS |
385 GEN7_SF_DW1_DEPTH_OFFSET_SOLID |
386 GEN7_SF_DW1_DEPTH_OFFSET_WIREFRAME |
387 GEN7_SF_DW1_DEPTH_OFFSET_POINT |
388 GEN7_SF_DW1_VIEWPORT_ENABLE |
Tony Barbourfa6cac72015-01-16 14:27:35 -0700389 pipeline->cmd_sf_fill;
Chia-I Wu8016a172014-08-29 18:31:32 +0800390
391 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
392 int format;
393
Jeremy Hayes2b7e88a2015-01-23 08:51:43 -0700394 switch (pipeline->db_format) {
395 case XGL_FMT_D16_UNORM:
Chia-I Wu8016a172014-08-29 18:31:32 +0800396 format = GEN6_ZFORMAT_D16_UNORM;
397 break;
Jeremy Hayes2b7e88a2015-01-23 08:51:43 -0700398 case XGL_FMT_D32_SFLOAT:
399 case XGL_FMT_D32_SFLOAT_S8_UINT:
Chia-I Wu8016a172014-08-29 18:31:32 +0800400 format = GEN6_ZFORMAT_D32_FLOAT;
401 break;
402 default:
Jeremy Hayese0c3b222015-01-14 16:17:08 -0700403 assert(!cmd->bind.render_pass->fb->ds); // Must have valid format if ds attached
Chia-I Wu8016a172014-08-29 18:31:32 +0800404 format = 0;
405 break;
406 }
407
408 dw1 |= format << GEN7_SF_DW1_DEPTH_FORMAT__SHIFT;
409 }
410
Tony Barbourfa6cac72015-01-16 14:27:35 -0700411 dw2 = pipeline->cmd_sf_cull;
Chia-I Wu8016a172014-08-29 18:31:32 +0800412
Tony Barbourfa6cac72015-01-16 14:27:35 -0700413 if (pipeline->sample_count > 1) {
Chia-I Wu8016a172014-08-29 18:31:32 +0800414 dw2 |= 128 << GEN7_SF_DW2_LINE_WIDTH__SHIFT |
415 GEN7_SF_DW2_MSRASTMODE_ON_PATTERN;
416 } else {
417 dw2 |= 0 << GEN7_SF_DW2_LINE_WIDTH__SHIFT |
418 GEN7_SF_DW2_MSRASTMODE_OFF_PIXEL;
419 }
420
Tony Barbourfa6cac72015-01-16 14:27:35 -0700421 if (pipeline->scissor_enable)
Chia-I Wu8016a172014-08-29 18:31:32 +0800422 dw2 |= GEN7_SF_DW2_SCISSOR_ENABLE;
423
424 /* in U8.3 */
Tony Barbourfa6cac72015-01-16 14:27:35 -0700425 point_width = (int) (raster->rs_info.pointSize * 8.0f + 0.5f);
Chia-I Wu8016a172014-08-29 18:31:32 +0800426 point_width = U_CLAMP(point_width, 1, 2047);
427
428 dw3 = pipeline->provoking_vertex_tri << GEN7_SF_DW3_TRI_PROVOKE__SHIFT |
429 pipeline->provoking_vertex_line << GEN7_SF_DW3_LINE_PROVOKE__SHIFT |
430 pipeline->provoking_vertex_trifan << GEN7_SF_DW3_TRIFAN_PROVOKE__SHIFT |
431 GEN7_SF_DW3_SUBPIXEL_8BITS |
432 GEN7_SF_DW3_USE_POINT_WIDTH |
433 point_width;
434
435 body[0] = dw1;
436 body[1] = dw2;
437 body[2] = dw3;
Tony Barbourfa6cac72015-01-16 14:27:35 -0700438 body[3] = u_fui((float) raster->rs_info.depthBias * 2.0f);
439 body[4] = u_fui(raster->rs_info.slopeScaledDepthBias);
440 body[5] = u_fui(raster->rs_info.depthBiasClamp);
Chia-I Wu8016a172014-08-29 18:31:32 +0800441}
442
Chia-I Wu8016a172014-08-29 18:31:32 +0800443static void gen6_3DSTATE_SF(struct intel_cmd *cmd)
444{
445 const uint8_t cmd_len = 20;
446 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SF) |
447 (cmd_len - 2);
Chia-I Wuf85def42015-01-29 00:34:24 +0800448 const uint32_t *sbe = cmd->bind.pipeline.graphics->cmd_3dstate_sbe;
Chia-I Wu8016a172014-08-29 18:31:32 +0800449 uint32_t sf[6];
Chia-I Wu72292b72014-09-09 10:48:33 +0800450 uint32_t *dw;
Chia-I Wu8016a172014-08-29 18:31:32 +0800451
452 CMD_ASSERT(cmd, 6, 6);
453
454 gen7_fill_3DSTATE_SF_body(cmd, sf);
Chia-I Wu8016a172014-08-29 18:31:32 +0800455
Chia-I Wu72292b72014-09-09 10:48:33 +0800456 cmd_batch_pointer(cmd, cmd_len, &dw);
457 dw[0] = dw0;
Chia-I Wuf85def42015-01-29 00:34:24 +0800458 dw[1] = sbe[1];
Chia-I Wu72292b72014-09-09 10:48:33 +0800459 memcpy(&dw[2], sf, sizeof(sf));
Chia-I Wuf85def42015-01-29 00:34:24 +0800460 memcpy(&dw[8], &sbe[2], 12);
Chia-I Wu8016a172014-08-29 18:31:32 +0800461}
462
463static void gen7_3DSTATE_SF(struct intel_cmd *cmd)
464{
465 const uint8_t cmd_len = 7;
Chia-I Wu72292b72014-09-09 10:48:33 +0800466 uint32_t *dw;
Chia-I Wu8016a172014-08-29 18:31:32 +0800467
468 CMD_ASSERT(cmd, 7, 7.5);
469
Chia-I Wu72292b72014-09-09 10:48:33 +0800470 cmd_batch_pointer(cmd, cmd_len, &dw);
Chia-I Wu8016a172014-08-29 18:31:32 +0800471 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SF) |
472 (cmd_len - 2);
473 gen7_fill_3DSTATE_SF_body(cmd, &dw[1]);
Chia-I Wu8016a172014-08-29 18:31:32 +0800474}
475
Chia-I Wuc3f9c092014-08-30 14:29:29 +0800476static void gen6_3DSTATE_CLIP(struct intel_cmd *cmd)
477{
478 const uint8_t cmd_len = 4;
479 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CLIP) |
480 (cmd_len - 2);
481 const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
GregFfd4c1f92014-11-07 15:32:52 -0700482 const struct intel_pipeline_shader *vs = &pipeline->vs;
Chia-I Wuf2b6d722014-09-02 08:52:27 +0800483 const struct intel_pipeline_shader *fs = &pipeline->fs;
Tony Barbourfa6cac72015-01-16 14:27:35 -0700484 const struct intel_dynamic_vp *viewport = cmd->bind.state.viewport;
Chia-I Wu72292b72014-09-09 10:48:33 +0800485 uint32_t dw1, dw2, dw3, *dw;
Chia-I Wuc3f9c092014-08-30 14:29:29 +0800486
487 CMD_ASSERT(cmd, 6, 7.5);
488
489 dw1 = GEN6_CLIP_DW1_STATISTICS;
490 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
491 dw1 |= GEN7_CLIP_DW1_SUBPIXEL_8BITS |
492 GEN7_CLIP_DW1_EARLY_CULL_ENABLE |
Tony Barbourfa6cac72015-01-16 14:27:35 -0700493 pipeline->cmd_clip_cull;
Chia-I Wuc3f9c092014-08-30 14:29:29 +0800494 }
495
496 dw2 = GEN6_CLIP_DW2_CLIP_ENABLE |
497 GEN6_CLIP_DW2_XY_TEST_ENABLE |
498 GEN6_CLIP_DW2_APIMODE_OGL |
GregFfd4c1f92014-11-07 15:32:52 -0700499 (vs->enable_user_clip ? 1 : 0) << GEN6_CLIP_DW2_UCP_CLIP_ENABLES__SHIFT |
Chia-I Wuc3f9c092014-08-30 14:29:29 +0800500 pipeline->provoking_vertex_tri << GEN6_CLIP_DW2_TRI_PROVOKE__SHIFT |
501 pipeline->provoking_vertex_line << GEN6_CLIP_DW2_LINE_PROVOKE__SHIFT |
502 pipeline->provoking_vertex_trifan << GEN6_CLIP_DW2_TRIFAN_PROVOKE__SHIFT;
503
504 if (pipeline->rasterizerDiscardEnable)
505 dw2 |= GEN6_CLIP_DW2_CLIPMODE_REJECT_ALL;
506 else
507 dw2 |= GEN6_CLIP_DW2_CLIPMODE_NORMAL;
508
509 if (pipeline->depthClipEnable)
510 dw2 |= GEN6_CLIP_DW2_Z_TEST_ENABLE;
511
512 if (fs->barycentric_interps & (GEN6_INTERP_NONPERSPECTIVE_PIXEL |
513 GEN6_INTERP_NONPERSPECTIVE_CENTROID |
514 GEN6_INTERP_NONPERSPECTIVE_SAMPLE))
515 dw2 |= GEN6_CLIP_DW2_NONPERSPECTIVE_BARYCENTRIC_ENABLE;
516
517 dw3 = 0x1 << GEN6_CLIP_DW3_MIN_POINT_WIDTH__SHIFT |
518 0x7ff << GEN6_CLIP_DW3_MAX_POINT_WIDTH__SHIFT |
519 (viewport->viewport_count - 1);
520
Mark Lobodzinski71fcc2d2015-01-27 13:24:03 -0600521 /* TODO: framebuffer requests layer_count > 1 */
522 if (cmd->bind.render_pass->fb->layer_count == 1) {
523 dw3 |= GEN6_CLIP_DW3_RTAINDEX_FORCED_ZERO;
524 }
525
Chia-I Wu72292b72014-09-09 10:48:33 +0800526 cmd_batch_pointer(cmd, cmd_len, &dw);
527 dw[0] = dw0;
528 dw[1] = dw1;
529 dw[2] = dw2;
530 dw[3] = dw3;
Chia-I Wuc3f9c092014-08-30 14:29:29 +0800531}
532
Chia-I Wu784d3042014-12-19 14:30:04 +0800533static void gen6_add_scratch_space(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600534 uint32_t batch_pos,
Chia-I Wu784d3042014-12-19 14:30:04 +0800535 const struct intel_pipeline *pipeline,
536 const struct intel_pipeline_shader *sh)
537{
538 int scratch_space;
539
540 CMD_ASSERT(cmd, 6, 7.5);
541
542 assert(sh->per_thread_scratch_size &&
543 sh->per_thread_scratch_size % 1024 == 0 &&
544 u_is_pow2(sh->per_thread_scratch_size) &&
545 sh->scratch_offset % 1024 == 0);
546 scratch_space = u_ffs(sh->per_thread_scratch_size) - 11;
547
548 cmd_reserve_reloc(cmd, 1);
549 cmd_batch_reloc(cmd, batch_pos, pipeline->obj.mem->bo,
550 sh->scratch_offset | scratch_space, INTEL_RELOC_WRITE);
551}
552
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800553static void gen6_3DSTATE_WM(struct intel_cmd *cmd)
554{
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800555 const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
Chia-I Wuf2b6d722014-09-02 08:52:27 +0800556 const struct intel_pipeline_shader *fs = &pipeline->fs;
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800557 const uint8_t cmd_len = 9;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600558 uint32_t pos;
Chia-I Wu72292b72014-09-09 10:48:33 +0800559 uint32_t dw0, dw2, dw4, dw5, dw6, *dw;
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800560
561 CMD_ASSERT(cmd, 6, 6);
562
563 dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
564
565 dw2 = (fs->sampler_count + 3) / 4 << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
566 fs->surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
567
568 dw4 = GEN6_WM_DW4_STATISTICS |
569 fs->urb_grf_start << GEN6_WM_DW4_URB_GRF_START0__SHIFT |
570 0 << GEN6_WM_DW4_URB_GRF_START1__SHIFT |
571 0 << GEN6_WM_DW4_URB_GRF_START2__SHIFT;
572
Chia-I Wu3f4bd102014-12-19 13:14:42 +0800573 dw5 = (fs->max_threads - 1) << GEN6_WM_DW5_MAX_THREADS__SHIFT |
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800574 GEN6_WM_DW5_PS_ENABLE |
575 GEN6_WM_DW5_8_PIXEL_DISPATCH;
576
577 if (fs->uses & INTEL_SHADER_USE_KILL ||
578 pipeline->cb_state.alphaToCoverageEnable)
579 dw5 |= GEN6_WM_DW5_PS_KILL;
580
Cody Northrope238deb2015-01-26 14:41:36 -0700581 if (fs->computed_depth_mode)
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800582 dw5 |= GEN6_WM_DW5_PS_COMPUTE_DEPTH;
583 if (fs->uses & INTEL_SHADER_USE_DEPTH)
584 dw5 |= GEN6_WM_DW5_PS_USE_DEPTH;
585 if (fs->uses & INTEL_SHADER_USE_W)
586 dw5 |= GEN6_WM_DW5_PS_USE_W;
587
588 if (pipeline->cb_state.dualSourceBlendEnable)
589 dw5 |= GEN6_WM_DW5_DUAL_SOURCE_BLEND;
590
591 dw6 = fs->in_count << GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT |
592 GEN6_WM_DW6_POSOFFSET_NONE |
593 GEN6_WM_DW6_ZW_INTERP_PIXEL |
594 fs->barycentric_interps << GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT |
595 GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT;
596
Tony Barbourfa6cac72015-01-16 14:27:35 -0700597 if (pipeline->sample_count > 1) {
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800598 dw6 |= GEN6_WM_DW6_MSRASTMODE_ON_PATTERN |
599 GEN6_WM_DW6_MSDISPMODE_PERPIXEL;
600 } else {
601 dw6 |= GEN6_WM_DW6_MSRASTMODE_OFF_PIXEL |
602 GEN6_WM_DW6_MSDISPMODE_PERSAMPLE;
603 }
604
Chia-I Wu784d3042014-12-19 14:30:04 +0800605 pos = cmd_batch_pointer(cmd, cmd_len, &dw);
Chia-I Wu72292b72014-09-09 10:48:33 +0800606 dw[0] = dw0;
Chia-I Wua57761b2014-10-14 14:27:44 +0800607 dw[1] = cmd->bind.pipeline.fs_offset;
Chia-I Wu72292b72014-09-09 10:48:33 +0800608 dw[2] = dw2;
609 dw[3] = 0; /* scratch */
610 dw[4] = dw4;
611 dw[5] = dw5;
612 dw[6] = dw6;
613 dw[7] = 0; /* kernel 1 */
614 dw[8] = 0; /* kernel 2 */
Chia-I Wu784d3042014-12-19 14:30:04 +0800615
616 if (fs->per_thread_scratch_size)
617 gen6_add_scratch_space(cmd, pos + 3, pipeline, fs);
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800618}
619
620static void gen7_3DSTATE_WM(struct intel_cmd *cmd)
621{
622 const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
Chia-I Wuf2b6d722014-09-02 08:52:27 +0800623 const struct intel_pipeline_shader *fs = &pipeline->fs;
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800624 const uint8_t cmd_len = 3;
Chia-I Wu72292b72014-09-09 10:48:33 +0800625 uint32_t dw0, dw1, dw2, *dw;
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800626
627 CMD_ASSERT(cmd, 7, 7.5);
628
629 dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (cmd_len - 2);
630
631 dw1 = GEN7_WM_DW1_STATISTICS |
632 GEN7_WM_DW1_PS_ENABLE |
633 GEN7_WM_DW1_ZW_INTERP_PIXEL |
634 fs->barycentric_interps << GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT |
635 GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT;
636
637 if (fs->uses & INTEL_SHADER_USE_KILL ||
638 pipeline->cb_state.alphaToCoverageEnable)
639 dw1 |= GEN7_WM_DW1_PS_KILL;
640
Cody Northrope238deb2015-01-26 14:41:36 -0700641 dw1 |= fs->computed_depth_mode << GEN7_WM_DW1_PSCDEPTH__SHIFT;
642
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800643 if (fs->uses & INTEL_SHADER_USE_DEPTH)
644 dw1 |= GEN7_WM_DW1_PS_USE_DEPTH;
645 if (fs->uses & INTEL_SHADER_USE_W)
646 dw1 |= GEN7_WM_DW1_PS_USE_W;
647
648 dw2 = 0;
649
Tony Barbourfa6cac72015-01-16 14:27:35 -0700650 if (pipeline->sample_count > 1) {
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800651 dw1 |= GEN7_WM_DW1_MSRASTMODE_ON_PATTERN;
652 dw2 |= GEN7_WM_DW2_MSDISPMODE_PERPIXEL;
653 } else {
654 dw1 |= GEN7_WM_DW1_MSRASTMODE_OFF_PIXEL;
655 dw2 |= GEN7_WM_DW2_MSDISPMODE_PERSAMPLE;
656 }
657
Chia-I Wu72292b72014-09-09 10:48:33 +0800658 cmd_batch_pointer(cmd, cmd_len, &dw);
659 dw[0] = dw0;
660 dw[1] = dw1;
661 dw[2] = dw2;
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800662}
663
664static void gen7_3DSTATE_PS(struct intel_cmd *cmd)
665{
666 const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
Chia-I Wuf2b6d722014-09-02 08:52:27 +0800667 const struct intel_pipeline_shader *fs = &pipeline->fs;
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800668 const uint8_t cmd_len = 8;
Chia-I Wu72292b72014-09-09 10:48:33 +0800669 uint32_t dw0, dw2, dw4, dw5, *dw;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600670 uint32_t pos;
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800671
672 CMD_ASSERT(cmd, 7, 7.5);
673
674 dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_PS) | (cmd_len - 2);
675
676 dw2 = (fs->sampler_count + 3) / 4 << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
677 fs->surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
678
679 dw4 = GEN7_PS_DW4_POSOFFSET_NONE |
680 GEN7_PS_DW4_8_PIXEL_DISPATCH;
681
682 if (cmd_gen(cmd) >= INTEL_GEN(7.5)) {
Chia-I Wu3f4bd102014-12-19 13:14:42 +0800683 dw4 |= (fs->max_threads - 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT;
Tony Barbourfa6cac72015-01-16 14:27:35 -0700684 dw4 |= pipeline->cmd_sample_mask << GEN75_PS_DW4_SAMPLE_MASK__SHIFT;
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800685 } else {
Chia-I Wu3f4bd102014-12-19 13:14:42 +0800686 dw4 |= (fs->max_threads - 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT;
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800687 }
688
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800689 if (fs->in_count)
690 dw4 |= GEN7_PS_DW4_ATTR_ENABLE;
691
692 if (pipeline->cb_state.dualSourceBlendEnable)
693 dw4 |= GEN7_PS_DW4_DUAL_SOURCE_BLEND;
694
695 dw5 = fs->urb_grf_start << GEN7_PS_DW5_URB_GRF_START0__SHIFT |
696 0 << GEN7_PS_DW5_URB_GRF_START1__SHIFT |
697 0 << GEN7_PS_DW5_URB_GRF_START2__SHIFT;
698
Chia-I Wu784d3042014-12-19 14:30:04 +0800699 pos = cmd_batch_pointer(cmd, cmd_len, &dw);
Chia-I Wu72292b72014-09-09 10:48:33 +0800700 dw[0] = dw0;
Chia-I Wua57761b2014-10-14 14:27:44 +0800701 dw[1] = cmd->bind.pipeline.fs_offset;
Chia-I Wu72292b72014-09-09 10:48:33 +0800702 dw[2] = dw2;
703 dw[3] = 0; /* scratch */
704 dw[4] = dw4;
705 dw[5] = dw5;
706 dw[6] = 0; /* kernel 1 */
707 dw[7] = 0; /* kernel 2 */
Chia-I Wu784d3042014-12-19 14:30:04 +0800708
709 if (fs->per_thread_scratch_size)
710 gen6_add_scratch_space(cmd, pos + 3, pipeline, fs);
Chia-I Wu1f2fd292014-08-29 15:07:09 +0800711}
712
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800713static void gen6_3DSTATE_DEPTH_BUFFER(struct intel_cmd *cmd,
714 const struct intel_ds_view *view)
715{
716 const uint8_t cmd_len = 7;
Chia-I Wu72292b72014-09-09 10:48:33 +0800717 uint32_t dw0, *dw;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600718 uint32_t pos;
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800719
720 CMD_ASSERT(cmd, 6, 7.5);
721
722 dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
Chia-I Wu426072d2014-08-26 14:31:55 +0800723 GEN7_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER) :
724 GEN6_RENDER_CMD(3D, 3DSTATE_DEPTH_BUFFER);
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800725 dw0 |= (cmd_len - 2);
726
Chia-I Wu72292b72014-09-09 10:48:33 +0800727 pos = cmd_batch_pointer(cmd, cmd_len, &dw);
728 dw[0] = dw0;
729 dw[1] = view->cmd[0];
730 dw[2] = 0;
731 dw[3] = view->cmd[2];
732 dw[4] = view->cmd[3];
733 dw[5] = view->cmd[4];
734 dw[6] = view->cmd[5];
735
Courtney Goeltzenleuchtere316d972014-08-22 16:25:24 -0600736 if (view->img) {
Chia-I Wu72292b72014-09-09 10:48:33 +0800737 cmd_reserve_reloc(cmd, 1);
738 cmd_batch_reloc(cmd, pos + 2, view->img->obj.mem->bo,
739 view->cmd[1], INTEL_RELOC_WRITE);
Courtney Goeltzenleuchtere316d972014-08-22 16:25:24 -0600740 }
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800741}
742
743static void gen6_3DSTATE_STENCIL_BUFFER(struct intel_cmd *cmd,
744 const struct intel_ds_view *view)
745{
746 const uint8_t cmd_len = 3;
Chia-I Wu72292b72014-09-09 10:48:33 +0800747 uint32_t dw0, *dw;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600748 uint32_t pos;
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800749
750 CMD_ASSERT(cmd, 6, 7.5);
751
752 dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
Chia-I Wu426072d2014-08-26 14:31:55 +0800753 GEN7_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER) :
754 GEN6_RENDER_CMD(3D, 3DSTATE_STENCIL_BUFFER);
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800755 dw0 |= (cmd_len - 2);
756
Chia-I Wu72292b72014-09-09 10:48:33 +0800757 pos = cmd_batch_pointer(cmd, cmd_len, &dw);
758 dw[0] = dw0;
759 dw[1] = view->cmd[6];
760 dw[2] = 0;
761
Courtney Goeltzenleuchtere316d972014-08-22 16:25:24 -0600762 if (view->img) {
Chia-I Wu72292b72014-09-09 10:48:33 +0800763 cmd_reserve_reloc(cmd, 1);
764 cmd_batch_reloc(cmd, pos + 2, view->img->obj.mem->bo,
765 view->cmd[7], INTEL_RELOC_WRITE);
Courtney Goeltzenleuchtere316d972014-08-22 16:25:24 -0600766 }
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800767}
768
769static void gen6_3DSTATE_HIER_DEPTH_BUFFER(struct intel_cmd *cmd,
770 const struct intel_ds_view *view)
771{
772 const uint8_t cmd_len = 3;
Chia-I Wu72292b72014-09-09 10:48:33 +0800773 uint32_t dw0, *dw;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -0600774 uint32_t pos;
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800775
776 CMD_ASSERT(cmd, 6, 7.5);
777
778 dw0 = (cmd_gen(cmd) >= INTEL_GEN(7)) ?
Chia-I Wu426072d2014-08-26 14:31:55 +0800779 GEN7_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER) :
780 GEN6_RENDER_CMD(3D, 3DSTATE_HIER_DEPTH_BUFFER);
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800781 dw0 |= (cmd_len - 2);
782
Chia-I Wu72292b72014-09-09 10:48:33 +0800783 pos = cmd_batch_pointer(cmd, cmd_len, &dw);
784 dw[0] = dw0;
785 dw[1] = view->cmd[8];
786 dw[2] = 0;
787
Courtney Goeltzenleuchtere316d972014-08-22 16:25:24 -0600788 if (view->img) {
Chia-I Wu72292b72014-09-09 10:48:33 +0800789 cmd_reserve_reloc(cmd, 1);
790 cmd_batch_reloc(cmd, pos + 2, view->img->obj.mem->bo,
791 view->cmd[9], INTEL_RELOC_WRITE);
Courtney Goeltzenleuchtere316d972014-08-22 16:25:24 -0600792 }
Chia-I Wu7fae4e32014-08-21 11:39:44 +0800793}
794
Chia-I Wuf8231032014-08-25 10:44:45 +0800795static void gen6_3DSTATE_CLEAR_PARAMS(struct intel_cmd *cmd,
796 uint32_t clear_val)
797{
798 const uint8_t cmd_len = 2;
Chia-I Wu426072d2014-08-26 14:31:55 +0800799 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) |
Chia-I Wuf8231032014-08-25 10:44:45 +0800800 GEN6_CLEAR_PARAMS_DW0_VALID |
801 (cmd_len - 2);
Chia-I Wu72292b72014-09-09 10:48:33 +0800802 uint32_t *dw;
Chia-I Wuf8231032014-08-25 10:44:45 +0800803
804 CMD_ASSERT(cmd, 6, 6);
805
Chia-I Wu72292b72014-09-09 10:48:33 +0800806 cmd_batch_pointer(cmd, cmd_len, &dw);
807 dw[0] = dw0;
808 dw[1] = clear_val;
Chia-I Wuf8231032014-08-25 10:44:45 +0800809}
810
811static void gen7_3DSTATE_CLEAR_PARAMS(struct intel_cmd *cmd,
812 uint32_t clear_val)
813{
814 const uint8_t cmd_len = 3;
Chia-I Wu426072d2014-08-26 14:31:55 +0800815 const uint32_t dw0 = GEN7_RENDER_CMD(3D, 3DSTATE_CLEAR_PARAMS) |
Chia-I Wuf8231032014-08-25 10:44:45 +0800816 (cmd_len - 2);
Chia-I Wu72292b72014-09-09 10:48:33 +0800817 uint32_t *dw;
Chia-I Wuf8231032014-08-25 10:44:45 +0800818
819 CMD_ASSERT(cmd, 7, 7.5);
820
Chia-I Wu72292b72014-09-09 10:48:33 +0800821 cmd_batch_pointer(cmd, cmd_len, &dw);
822 dw[0] = dw0;
823 dw[1] = clear_val;
824 dw[2] = 1;
Chia-I Wuf8231032014-08-25 10:44:45 +0800825}
826
Chia-I Wu302742d2014-08-22 10:28:29 +0800827static void gen6_3DSTATE_CC_STATE_POINTERS(struct intel_cmd *cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +0800828 uint32_t blend_offset,
829 uint32_t ds_offset,
830 uint32_t cc_offset)
Chia-I Wu302742d2014-08-22 10:28:29 +0800831{
832 const uint8_t cmd_len = 4;
Chia-I Wu72292b72014-09-09 10:48:33 +0800833 uint32_t dw0, *dw;
Chia-I Wu302742d2014-08-22 10:28:29 +0800834
835 CMD_ASSERT(cmd, 6, 6);
836
Chia-I Wu426072d2014-08-26 14:31:55 +0800837 dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_CC_STATE_POINTERS) |
Chia-I Wu302742d2014-08-22 10:28:29 +0800838 (cmd_len - 2);
839
Chia-I Wu72292b72014-09-09 10:48:33 +0800840 cmd_batch_pointer(cmd, cmd_len, &dw);
841 dw[0] = dw0;
842 dw[1] = blend_offset | 1;
843 dw[2] = ds_offset | 1;
844 dw[3] = cc_offset | 1;
Chia-I Wu302742d2014-08-22 10:28:29 +0800845}
846
Chia-I Wu1744cca2014-08-22 11:10:17 +0800847static void gen6_3DSTATE_VIEWPORT_STATE_POINTERS(struct intel_cmd *cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +0800848 uint32_t clip_offset,
849 uint32_t sf_offset,
850 uint32_t cc_offset)
Chia-I Wu1744cca2014-08-22 11:10:17 +0800851{
852 const uint8_t cmd_len = 4;
Chia-I Wu72292b72014-09-09 10:48:33 +0800853 uint32_t dw0, *dw;
Chia-I Wu1744cca2014-08-22 11:10:17 +0800854
855 CMD_ASSERT(cmd, 6, 6);
856
Chia-I Wu426072d2014-08-26 14:31:55 +0800857 dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_VIEWPORT_STATE_POINTERS) |
Chia-I Wu1744cca2014-08-22 11:10:17 +0800858 GEN6_PTR_VP_DW0_CLIP_CHANGED |
859 GEN6_PTR_VP_DW0_SF_CHANGED |
860 GEN6_PTR_VP_DW0_CC_CHANGED |
861 (cmd_len - 2);
862
Chia-I Wu72292b72014-09-09 10:48:33 +0800863 cmd_batch_pointer(cmd, cmd_len, &dw);
864 dw[0] = dw0;
865 dw[1] = clip_offset;
866 dw[2] = sf_offset;
867 dw[3] = cc_offset;
Chia-I Wu1744cca2014-08-22 11:10:17 +0800868}
869
870static void gen6_3DSTATE_SCISSOR_STATE_POINTERS(struct intel_cmd *cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +0800871 uint32_t scissor_offset)
Chia-I Wu1744cca2014-08-22 11:10:17 +0800872{
873 const uint8_t cmd_len = 2;
Chia-I Wu72292b72014-09-09 10:48:33 +0800874 uint32_t dw0, *dw;
Chia-I Wu1744cca2014-08-22 11:10:17 +0800875
876 CMD_ASSERT(cmd, 6, 6);
877
Chia-I Wu426072d2014-08-26 14:31:55 +0800878 dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SCISSOR_STATE_POINTERS) |
Chia-I Wu1744cca2014-08-22 11:10:17 +0800879 (cmd_len - 2);
880
Chia-I Wu72292b72014-09-09 10:48:33 +0800881 cmd_batch_pointer(cmd, cmd_len, &dw);
882 dw[0] = dw0;
883 dw[1] = scissor_offset;
Chia-I Wu1744cca2014-08-22 11:10:17 +0800884}
885
Chia-I Wu42a56202014-08-23 16:47:48 +0800886static void gen6_3DSTATE_BINDING_TABLE_POINTERS(struct intel_cmd *cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +0800887 uint32_t vs_offset,
888 uint32_t gs_offset,
889 uint32_t ps_offset)
Chia-I Wu42a56202014-08-23 16:47:48 +0800890{
891 const uint8_t cmd_len = 4;
Chia-I Wu72292b72014-09-09 10:48:33 +0800892 uint32_t dw0, *dw;
Chia-I Wu42a56202014-08-23 16:47:48 +0800893
894 CMD_ASSERT(cmd, 6, 6);
895
Chia-I Wu426072d2014-08-26 14:31:55 +0800896 dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_BINDING_TABLE_POINTERS) |
Chia-I Wu42a56202014-08-23 16:47:48 +0800897 GEN6_PTR_BINDING_TABLE_DW0_VS_CHANGED |
898 GEN6_PTR_BINDING_TABLE_DW0_GS_CHANGED |
899 GEN6_PTR_BINDING_TABLE_DW0_PS_CHANGED |
900 (cmd_len - 2);
901
Chia-I Wu72292b72014-09-09 10:48:33 +0800902 cmd_batch_pointer(cmd, cmd_len, &dw);
903 dw[0] = dw0;
904 dw[1] = vs_offset;
905 dw[2] = gs_offset;
906 dw[3] = ps_offset;
Chia-I Wu42a56202014-08-23 16:47:48 +0800907}
908
Chia-I Wu257e75e2014-08-29 14:06:35 +0800909static void gen6_3DSTATE_SAMPLER_STATE_POINTERS(struct intel_cmd *cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +0800910 uint32_t vs_offset,
911 uint32_t gs_offset,
912 uint32_t ps_offset)
Chia-I Wu257e75e2014-08-29 14:06:35 +0800913{
914 const uint8_t cmd_len = 4;
Chia-I Wu72292b72014-09-09 10:48:33 +0800915 uint32_t dw0, *dw;
Chia-I Wu257e75e2014-08-29 14:06:35 +0800916
917 CMD_ASSERT(cmd, 6, 6);
918
919 dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLER_STATE_POINTERS) |
920 GEN6_PTR_SAMPLER_DW0_VS_CHANGED |
921 GEN6_PTR_SAMPLER_DW0_GS_CHANGED |
922 GEN6_PTR_SAMPLER_DW0_PS_CHANGED |
923 (cmd_len - 2);
924
Chia-I Wu72292b72014-09-09 10:48:33 +0800925 cmd_batch_pointer(cmd, cmd_len, &dw);
926 dw[0] = dw0;
927 dw[1] = vs_offset;
928 dw[2] = gs_offset;
929 dw[3] = ps_offset;
Chia-I Wu257e75e2014-08-29 14:06:35 +0800930}
931
Chia-I Wu302742d2014-08-22 10:28:29 +0800932static void gen7_3dstate_pointer(struct intel_cmd *cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +0800933 int subop, uint32_t offset)
Chia-I Wu302742d2014-08-22 10:28:29 +0800934{
935 const uint8_t cmd_len = 2;
936 const uint32_t dw0 = GEN6_RENDER_TYPE_RENDER |
937 GEN6_RENDER_SUBTYPE_3D |
938 subop | (cmd_len - 2);
Chia-I Wu72292b72014-09-09 10:48:33 +0800939 uint32_t *dw;
Chia-I Wu302742d2014-08-22 10:28:29 +0800940
Chia-I Wu72292b72014-09-09 10:48:33 +0800941 cmd_batch_pointer(cmd, cmd_len, &dw);
942 dw[0] = dw0;
943 dw[1] = offset;
Chia-I Wu302742d2014-08-22 10:28:29 +0800944}
945
Chia-I Wua6c4f152014-12-02 04:19:58 +0800946static uint32_t gen6_BLEND_STATE(struct intel_cmd *cmd)
Chia-I Wu302742d2014-08-22 10:28:29 +0800947{
Chia-I Wue6073342014-11-30 09:43:42 +0800948 const uint8_t cmd_align = GEN6_ALIGNMENT_BLEND_STATE;
Tony Barbourfa6cac72015-01-16 14:27:35 -0700949 const uint8_t cmd_len = INTEL_MAX_RENDER_TARGETS * 2;
950 const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
Chia-I Wu302742d2014-08-22 10:28:29 +0800951
952 CMD_ASSERT(cmd, 6, 7.5);
Tony Barbourfa6cac72015-01-16 14:27:35 -0700953 STATIC_ASSERT(ARRAY_SIZE(pipeline->cmd_cb) >= INTEL_MAX_RENDER_TARGETS);
Chia-I Wu302742d2014-08-22 10:28:29 +0800954
Tony Barbourfa6cac72015-01-16 14:27:35 -0700955 return cmd_state_write(cmd, INTEL_CMD_ITEM_BLEND, cmd_align, cmd_len, pipeline->cmd_cb);
Chia-I Wu302742d2014-08-22 10:28:29 +0800956}
957
Chia-I Wu72292b72014-09-09 10:48:33 +0800958static uint32_t gen6_DEPTH_STENCIL_STATE(struct intel_cmd *cmd,
Tony Barbourfa6cac72015-01-16 14:27:35 -0700959 const struct intel_dynamic_ds *state)
Chia-I Wu302742d2014-08-22 10:28:29 +0800960{
Tony Barbourfa6cac72015-01-16 14:27:35 -0700961 const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
Chia-I Wue6073342014-11-30 09:43:42 +0800962 const uint8_t cmd_align = GEN6_ALIGNMENT_DEPTH_STENCIL_STATE;
Chia-I Wu302742d2014-08-22 10:28:29 +0800963 const uint8_t cmd_len = 3;
Tony Barbourfa6cac72015-01-16 14:27:35 -0700964 uint32_t dw[3];
965
966 dw[0] = pipeline->cmd_depth_stencil;
Courtney Goeltzenleuchter5a054a62015-01-23 15:21:37 -0700967 /* same read and write masks for both front and back faces */
Tony Barbourfa6cac72015-01-16 14:27:35 -0700968 dw[1] = (state->ds_info.stencilReadMask & 0xff) << 24 |
Courtney Goeltzenleuchter5a054a62015-01-23 15:21:37 -0700969 (state->ds_info.stencilWriteMask & 0xff) << 16 |
970 (state->ds_info.stencilReadMask & 0xff) << 8 |
971 (state->ds_info.stencilWriteMask & 0xff);
Tony Barbourfa6cac72015-01-16 14:27:35 -0700972 dw[2] = pipeline->cmd_depth_test;
Chia-I Wu302742d2014-08-22 10:28:29 +0800973
974 CMD_ASSERT(cmd, 6, 7.5);
Tony Barbourfa6cac72015-01-16 14:27:35 -0700975
976 if (state->ds_info.stencilWriteMask && pipeline->stencilTestEnable)
977 dw[0] |= 1 << 18;
Chia-I Wu302742d2014-08-22 10:28:29 +0800978
Chia-I Wu00b51a82014-09-09 12:07:37 +0800979 return cmd_state_write(cmd, INTEL_CMD_ITEM_DEPTH_STENCIL,
Tony Barbourfa6cac72015-01-16 14:27:35 -0700980 cmd_align, cmd_len, dw);
Chia-I Wu302742d2014-08-22 10:28:29 +0800981}
982
Chia-I Wu72292b72014-09-09 10:48:33 +0800983static uint32_t gen6_COLOR_CALC_STATE(struct intel_cmd *cmd,
Chia-I Wu302742d2014-08-22 10:28:29 +0800984 uint32_t stencil_ref,
985 const uint32_t blend_color[4])
986{
Chia-I Wue6073342014-11-30 09:43:42 +0800987 const uint8_t cmd_align = GEN6_ALIGNMENT_COLOR_CALC_STATE;
Chia-I Wu302742d2014-08-22 10:28:29 +0800988 const uint8_t cmd_len = 6;
Chia-I Wu72292b72014-09-09 10:48:33 +0800989 uint32_t offset, *dw;
Chia-I Wu302742d2014-08-22 10:28:29 +0800990
991 CMD_ASSERT(cmd, 6, 7.5);
992
Chia-I Wu00b51a82014-09-09 12:07:37 +0800993 offset = cmd_state_pointer(cmd, INTEL_CMD_ITEM_COLOR_CALC,
994 cmd_align, cmd_len, &dw);
Chia-I Wu302742d2014-08-22 10:28:29 +0800995 dw[0] = stencil_ref;
996 dw[1] = 0;
997 dw[2] = blend_color[0];
998 dw[3] = blend_color[1];
999 dw[4] = blend_color[2];
1000 dw[5] = blend_color[3];
Chia-I Wu302742d2014-08-22 10:28:29 +08001001
Chia-I Wu72292b72014-09-09 10:48:33 +08001002 return offset;
Chia-I Wu302742d2014-08-22 10:28:29 +08001003}
1004
Chia-I Wu8370b402014-08-29 12:28:37 +08001005static void cmd_wa_gen6_pre_depth_stall_write(struct intel_cmd *cmd)
Chia-I Wu48c283d2014-08-25 23:13:46 +08001006{
Chia-I Wu8370b402014-08-29 12:28:37 +08001007 CMD_ASSERT(cmd, 6, 7.5);
1008
Chia-I Wu707a29e2014-08-27 12:51:47 +08001009 if (!cmd->bind.draw_count)
1010 return;
1011
Chia-I Wu8370b402014-08-29 12:28:37 +08001012 if (cmd->bind.wa_flags & INTEL_CMD_WA_GEN6_PRE_DEPTH_STALL_WRITE)
Chia-I Wu48c283d2014-08-25 23:13:46 +08001013 return;
1014
Chia-I Wu8370b402014-08-29 12:28:37 +08001015 cmd->bind.wa_flags |= INTEL_CMD_WA_GEN6_PRE_DEPTH_STALL_WRITE;
Chia-I Wu48c283d2014-08-25 23:13:46 +08001016
1017 /*
1018 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
1019 *
1020 * "Pipe-control with CS-stall bit set must be sent BEFORE the
1021 * pipe-control with a post-sync op and no write-cache flushes."
1022 *
1023 * The workaround below necessitates this workaround.
1024 */
1025 gen6_PIPE_CONTROL(cmd,
1026 GEN6_PIPE_CONTROL_CS_STALL |
1027 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL,
Chia-I Wud6d079d2014-08-31 13:14:21 +08001028 NULL, 0, 0);
Chia-I Wu48c283d2014-08-25 23:13:46 +08001029
Chia-I Wud6d079d2014-08-31 13:14:21 +08001030 gen6_PIPE_CONTROL(cmd, GEN6_PIPE_CONTROL_WRITE_IMM,
1031 cmd->scratch_bo, 0, 0);
Chia-I Wu48c283d2014-08-25 23:13:46 +08001032}
1033
Chia-I Wu8370b402014-08-29 12:28:37 +08001034static void cmd_wa_gen6_pre_command_scoreboard_stall(struct intel_cmd *cmd)
Courtney Goeltzenleuchterf9e1a412014-08-27 13:59:36 -06001035{
Chia-I Wu48c283d2014-08-25 23:13:46 +08001036 CMD_ASSERT(cmd, 6, 7.5);
1037
Chia-I Wubb2d8ca2014-08-28 23:15:48 +08001038 if (!cmd->bind.draw_count)
1039 return;
1040
Chia-I Wud6d079d2014-08-31 13:14:21 +08001041 gen6_PIPE_CONTROL(cmd, GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL,
1042 NULL, 0, 0);
Chia-I Wu8370b402014-08-29 12:28:37 +08001043}
Chia-I Wubb2d8ca2014-08-28 23:15:48 +08001044
Chia-I Wu8370b402014-08-29 12:28:37 +08001045static void cmd_wa_gen7_pre_vs_depth_stall_write(struct intel_cmd *cmd)
1046{
Chia-I Wubb2d8ca2014-08-28 23:15:48 +08001047 CMD_ASSERT(cmd, 7, 7.5);
1048
Chia-I Wu8370b402014-08-29 12:28:37 +08001049 if (!cmd->bind.draw_count)
1050 return;
1051
1052 cmd_wa_gen6_pre_depth_stall_write(cmd);
Chia-I Wubb2d8ca2014-08-28 23:15:48 +08001053
1054 gen6_PIPE_CONTROL(cmd,
1055 GEN6_PIPE_CONTROL_DEPTH_STALL | GEN6_PIPE_CONTROL_WRITE_IMM,
Chia-I Wud6d079d2014-08-31 13:14:21 +08001056 cmd->scratch_bo, 0, 0);
Chia-I Wubb2d8ca2014-08-28 23:15:48 +08001057}
1058
Chia-I Wu8370b402014-08-29 12:28:37 +08001059static void cmd_wa_gen7_post_command_cs_stall(struct intel_cmd *cmd)
1060{
1061 CMD_ASSERT(cmd, 7, 7.5);
1062
Chia-I Wu8370b402014-08-29 12:28:37 +08001063 /*
1064 * From the Ivy Bridge PRM, volume 2 part 1, page 61:
1065 *
1066 * "One of the following must also be set (when CS stall is set):
1067 *
1068 * * Render Target Cache Flush Enable ([12] of DW1)
1069 * * Depth Cache Flush Enable ([0] of DW1)
1070 * * Stall at Pixel Scoreboard ([1] of DW1)
1071 * * Depth Stall ([13] of DW1)
1072 * * Post-Sync Operation ([13] of DW1)"
1073 */
1074 gen6_PIPE_CONTROL(cmd,
1075 GEN6_PIPE_CONTROL_CS_STALL |
1076 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL,
Chia-I Wud6d079d2014-08-31 13:14:21 +08001077 NULL, 0, 0);
Chia-I Wu8370b402014-08-29 12:28:37 +08001078}
1079
1080static void cmd_wa_gen7_post_command_depth_stall(struct intel_cmd *cmd)
1081{
1082 CMD_ASSERT(cmd, 7, 7.5);
1083
Chia-I Wu8370b402014-08-29 12:28:37 +08001084 cmd_wa_gen6_pre_depth_stall_write(cmd);
1085
Chia-I Wud6d079d2014-08-31 13:14:21 +08001086 gen6_PIPE_CONTROL(cmd, GEN6_PIPE_CONTROL_DEPTH_STALL, NULL, 0, 0);
Chia-I Wu8370b402014-08-29 12:28:37 +08001087}
1088
1089static void cmd_wa_gen6_pre_multisample_depth_flush(struct intel_cmd *cmd)
1090{
1091 CMD_ASSERT(cmd, 6, 7.5);
1092
1093 if (!cmd->bind.draw_count)
1094 return;
1095
1096 /*
1097 * From the Sandy Bridge PRM, volume 2 part 1, page 305:
1098 *
1099 * "Driver must guarentee that all the caches in the depth pipe are
1100 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
1101 * requires driver to send a PIPE_CONTROL with a CS stall along with
1102 * a Depth Flush prior to this command."
1103 *
1104 * From the Ivy Bridge PRM, volume 2 part 1, page 304:
1105 *
1106 * "Driver must ierarchi that all the caches in the depth pipe are
1107 * flushed before this command (3DSTATE_MULTISAMPLE) is parsed. This
1108 * requires driver to send a PIPE_CONTROL with a CS stall along with
1109 * a Depth Flush prior to this command.
1110 */
1111 gen6_PIPE_CONTROL(cmd,
1112 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1113 GEN6_PIPE_CONTROL_CS_STALL,
Chia-I Wud6d079d2014-08-31 13:14:21 +08001114 NULL, 0, 0);
Chia-I Wu8370b402014-08-29 12:28:37 +08001115}
1116
1117static void cmd_wa_gen6_pre_ds_flush(struct intel_cmd *cmd)
1118{
1119 CMD_ASSERT(cmd, 6, 7.5);
1120
1121 if (!cmd->bind.draw_count)
1122 return;
1123
1124 /*
1125 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
1126 *
1127 * "Driver must send a least one PIPE_CONTROL command with CS Stall
1128 * and a post sync operation prior to the group of depth
1129 * commands(3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
1130 * 3DSTATE_STENCIL_BUFFER, and 3DSTATE_HIER_DEPTH_BUFFER)."
1131 *
1132 * This workaround satifies all the conditions.
1133 */
1134 cmd_wa_gen6_pre_depth_stall_write(cmd);
1135
1136 /*
1137 * From the Ivy Bridge PRM, volume 2 part 1, page 315:
1138 *
1139 * "Restriction: Prior to changing Depth/Stencil Buffer state (i.e.,
1140 * any combination of 3DSTATE_DEPTH_BUFFER, 3DSTATE_CLEAR_PARAMS,
1141 * 3DSTATE_STENCIL_BUFFER, 3DSTATE_HIER_DEPTH_BUFFER) SW must first
1142 * issue a pipelined depth stall (PIPE_CONTROL with Depth Stall bit
1143 * set), followed by a pipelined depth cache flush (PIPE_CONTROL with
1144 * Depth Flush Bit set, followed by another pipelined depth stall
1145 * (PIPE_CONTROL with Depth Stall Bit set), unless SW can otherwise
1146 * guarantee that the pipeline from WM onwards is already flushed
1147 * (e.g., via a preceding MI_FLUSH)."
1148 */
Chia-I Wud6d079d2014-08-31 13:14:21 +08001149 gen6_PIPE_CONTROL(cmd, GEN6_PIPE_CONTROL_DEPTH_STALL, NULL, 0, 0);
1150 gen6_PIPE_CONTROL(cmd, GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH, NULL, 0, 0);
1151 gen6_PIPE_CONTROL(cmd, GEN6_PIPE_CONTROL_DEPTH_STALL, NULL, 0, 0);
Chia-I Wu8370b402014-08-29 12:28:37 +08001152}
1153
Chia-I Wu66bdcd72015-02-10 04:11:31 +08001154void cmd_batch_state_base_address(struct intel_cmd *cmd)
1155{
1156 const uint8_t cmd_len = 10;
1157 const uint32_t dw0 = GEN6_RENDER_CMD(COMMON, STATE_BASE_ADDRESS) |
1158 (cmd_len - 2);
1159 uint32_t pos;
1160 uint32_t *dw;
1161
1162 CMD_ASSERT(cmd, 6, 7.5);
1163
1164 pos = cmd_batch_pointer(cmd, cmd_len, &dw);
1165
1166 dw[0] = dw0;
1167 /* start offsets */
1168 dw[1] = 1;
1169 dw[2] = 1;
1170 dw[3] = 1;
1171 dw[4] = 1;
1172 dw[5] = 1;
1173 /* end offsets */
1174 dw[6] = 1;
1175 dw[7] = 1 + 0xfffff000;
1176 dw[8] = 1 + 0xfffff000;
1177 dw[9] = 1;
1178
1179 cmd_reserve_reloc(cmd, 3);
Chia-I Wuf98dd882015-02-10 04:17:47 +08001180 cmd_batch_reloc_writer(cmd, pos + 2, INTEL_CMD_WRITER_SURFACE,
1181 cmd->writers[INTEL_CMD_WRITER_SURFACE].sba_offset + 1);
1182 cmd_batch_reloc_writer(cmd, pos + 3, INTEL_CMD_WRITER_STATE,
1183 cmd->writers[INTEL_CMD_WRITER_STATE].sba_offset + 1);
1184 cmd_batch_reloc_writer(cmd, pos + 5, INTEL_CMD_WRITER_INSTRUCTION,
1185 cmd->writers[INTEL_CMD_WRITER_INSTRUCTION].sba_offset + 1);
Chia-I Wu66bdcd72015-02-10 04:11:31 +08001186}
1187
Chia-I Wu525c6602014-08-27 10:22:34 +08001188void cmd_batch_flush(struct intel_cmd *cmd, uint32_t pipe_control_dw0)
1189{
Mike Stroyan552fda42015-01-30 17:21:08 -07001190 if (pipe_control_dw0 == 0)
1191 return;
1192
Chia-I Wu525c6602014-08-27 10:22:34 +08001193 if (!cmd->bind.draw_count)
1194 return;
1195
1196 assert(!(pipe_control_dw0 & GEN6_PIPE_CONTROL_WRITE__MASK));
1197
Chia-I Wu8370b402014-08-29 12:28:37 +08001198 /*
1199 * From the Sandy Bridge PRM, volume 2 part 1, page 60:
1200 *
1201 * "Before a PIPE_CONTROL with Write Cache Flush Enable =1, a
1202 * PIPE_CONTROL with any non-zero post-sync-op is required."
1203 */
Chia-I Wu525c6602014-08-27 10:22:34 +08001204 if (pipe_control_dw0 & GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH)
Chia-I Wu8370b402014-08-29 12:28:37 +08001205 cmd_wa_gen6_pre_depth_stall_write(cmd);
Chia-I Wu525c6602014-08-27 10:22:34 +08001206
Chia-I Wu092279a2014-08-30 19:05:30 +08001207 /*
1208 * From the Ivy Bridge PRM, volume 2 part 1, page 61:
1209 *
1210 * "One of the following must also be set (when CS stall is set):
1211 *
1212 * * Render Target Cache Flush Enable ([12] of DW1)
1213 * * Depth Cache Flush Enable ([0] of DW1)
1214 * * Stall at Pixel Scoreboard ([1] of DW1)
1215 * * Depth Stall ([13] of DW1)
1216 * * Post-Sync Operation ([13] of DW1)"
1217 */
1218 if ((pipe_control_dw0 & GEN6_PIPE_CONTROL_CS_STALL) &&
1219 !(pipe_control_dw0 & (GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
1220 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1221 GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL |
1222 GEN6_PIPE_CONTROL_DEPTH_STALL)))
1223 pipe_control_dw0 |= GEN6_PIPE_CONTROL_PIXEL_SCOREBOARD_STALL;
1224
Chia-I Wud6d079d2014-08-31 13:14:21 +08001225 gen6_PIPE_CONTROL(cmd, pipe_control_dw0, NULL, 0, 0);
Chia-I Wu525c6602014-08-27 10:22:34 +08001226}
1227
Chia-I Wu3fb47ce2014-10-28 11:19:36 +08001228void cmd_batch_flush_all(struct intel_cmd *cmd)
1229{
1230 cmd_batch_flush(cmd, GEN6_PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE |
1231 GEN6_PIPE_CONTROL_RENDER_CACHE_FLUSH |
1232 GEN6_PIPE_CONTROL_DEPTH_CACHE_FLUSH |
1233 GEN6_PIPE_CONTROL_VF_CACHE_INVALIDATE |
1234 GEN6_PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
1235 GEN6_PIPE_CONTROL_CS_STALL);
1236}
1237
Chia-I Wu759fa2e2014-08-30 18:44:47 +08001238void cmd_batch_depth_count(struct intel_cmd *cmd,
1239 struct intel_bo *bo,
1240 XGL_GPU_SIZE offset)
1241{
1242 cmd_wa_gen6_pre_depth_stall_write(cmd);
1243
1244 gen6_PIPE_CONTROL(cmd,
1245 GEN6_PIPE_CONTROL_DEPTH_STALL |
1246 GEN6_PIPE_CONTROL_WRITE_PS_DEPTH_COUNT,
Chia-I Wud6d079d2014-08-31 13:14:21 +08001247 bo, offset, 0);
Chia-I Wu759fa2e2014-08-30 18:44:47 +08001248}
1249
Chia-I Wue8dbd5d2014-08-31 13:15:58 +08001250void cmd_batch_timestamp(struct intel_cmd *cmd,
1251 struct intel_bo *bo,
1252 XGL_GPU_SIZE offset)
1253{
1254 /* need any WA or stall? */
1255 gen6_PIPE_CONTROL(cmd, GEN6_PIPE_CONTROL_WRITE_TIMESTAMP, bo, offset, 0);
1256}
1257
1258void cmd_batch_immediate(struct intel_cmd *cmd,
Mike Stroyan55658c22014-12-04 11:08:39 +00001259 uint32_t pipe_control_flags,
Chia-I Wue8dbd5d2014-08-31 13:15:58 +08001260 struct intel_bo *bo,
1261 XGL_GPU_SIZE offset,
1262 uint64_t val)
1263{
1264 /* need any WA or stall? */
Mike Stroyan55658c22014-12-04 11:08:39 +00001265 gen6_PIPE_CONTROL(cmd,
1266 GEN6_PIPE_CONTROL_WRITE_IMM | pipe_control_flags,
1267 bo, offset, val);
Chia-I Wue8dbd5d2014-08-31 13:15:58 +08001268}
1269
Chia-I Wu302742d2014-08-22 10:28:29 +08001270static void gen6_cc_states(struct intel_cmd *cmd)
1271{
Tony Barbourfa6cac72015-01-16 14:27:35 -07001272 const struct intel_dynamic_cb *blend = cmd->bind.state.blend;
1273 const struct intel_dynamic_ds *ds = cmd->bind.state.ds;
Chia-I Wu72292b72014-09-09 10:48:33 +08001274 uint32_t blend_offset, ds_offset, cc_offset;
Chia-I Wuce9f11f2014-08-22 10:38:51 +08001275 uint32_t stencil_ref;
1276 uint32_t blend_color[4];
Chia-I Wu302742d2014-08-22 10:28:29 +08001277
1278 CMD_ASSERT(cmd, 6, 6);
1279
Chia-I Wua6c4f152014-12-02 04:19:58 +08001280 blend_offset = gen6_BLEND_STATE(cmd);
1281
1282 if (blend)
Tony Barbourfa6cac72015-01-16 14:27:35 -07001283 memcpy(blend_color, blend->cb_info.blendConst, sizeof(blend_color));
Chia-I Wua6c4f152014-12-02 04:19:58 +08001284 else
Chia-I Wuce9f11f2014-08-22 10:38:51 +08001285 memset(blend_color, 0, sizeof(blend_color));
Chia-I Wuce9f11f2014-08-22 10:38:51 +08001286
1287 if (ds) {
Chia-I Wu72292b72014-09-09 10:48:33 +08001288 ds_offset = gen6_DEPTH_STENCIL_STATE(cmd, ds);
Tony Barbourfa6cac72015-01-16 14:27:35 -07001289 stencil_ref = (ds->ds_info.stencilFrontRef && 0xff) << 24 |
1290 (ds->ds_info.stencilBackRef && 0xff) << 16;
Chia-I Wuce9f11f2014-08-22 10:38:51 +08001291 } else {
Chia-I Wu72292b72014-09-09 10:48:33 +08001292 ds_offset = 0;
Chia-I Wuce9f11f2014-08-22 10:38:51 +08001293 stencil_ref = 0;
1294 }
1295
Chia-I Wu72292b72014-09-09 10:48:33 +08001296 cc_offset = gen6_COLOR_CALC_STATE(cmd, stencil_ref, blend_color);
Chia-I Wu302742d2014-08-22 10:28:29 +08001297
Chia-I Wu72292b72014-09-09 10:48:33 +08001298 gen6_3DSTATE_CC_STATE_POINTERS(cmd, blend_offset, ds_offset, cc_offset);
Chia-I Wu302742d2014-08-22 10:28:29 +08001299}
1300
Chia-I Wu1744cca2014-08-22 11:10:17 +08001301static void gen6_viewport_states(struct intel_cmd *cmd)
1302{
Tony Barbourfa6cac72015-01-16 14:27:35 -07001303 const struct intel_dynamic_vp *viewport = cmd->bind.state.viewport;
Chia-I Wub1d450a2014-09-09 13:48:03 +08001304 uint32_t sf_offset, clip_offset, cc_offset, scissor_offset;
Chia-I Wu1744cca2014-08-22 11:10:17 +08001305
1306 if (!viewport)
1307 return;
1308
Tony Barbourfa6cac72015-01-16 14:27:35 -07001309 assert(viewport->cmd_len == (8 + 4 + 2) *
1310 viewport->viewport_count + (viewport->has_scissor_rects) ?
1311 (viewport->viewport_count * 2) : 0);
Chia-I Wub1d450a2014-09-09 13:48:03 +08001312
1313 sf_offset = cmd_state_write(cmd, INTEL_CMD_ITEM_SF_VIEWPORT,
Chia-I Wue6073342014-11-30 09:43:42 +08001314 GEN6_ALIGNMENT_SF_VIEWPORT, 8 * viewport->viewport_count,
Chia-I Wub1d450a2014-09-09 13:48:03 +08001315 viewport->cmd);
1316
1317 clip_offset = cmd_state_write(cmd, INTEL_CMD_ITEM_CLIP_VIEWPORT,
Chia-I Wue6073342014-11-30 09:43:42 +08001318 GEN6_ALIGNMENT_CLIP_VIEWPORT, 4 * viewport->viewport_count,
Chia-I Wub1d450a2014-09-09 13:48:03 +08001319 &viewport->cmd[viewport->cmd_clip_pos]);
1320
1321 cc_offset = cmd_state_write(cmd, INTEL_CMD_ITEM_CC_VIEWPORT,
Chia-I Wue6073342014-11-30 09:43:42 +08001322 GEN6_ALIGNMENT_SF_VIEWPORT, 2 * viewport->viewport_count,
Chia-I Wub1d450a2014-09-09 13:48:03 +08001323 &viewport->cmd[viewport->cmd_cc_pos]);
1324
Tony Barbourfa6cac72015-01-16 14:27:35 -07001325 if (viewport->has_scissor_rects) {
Chia-I Wub1d450a2014-09-09 13:48:03 +08001326 scissor_offset = cmd_state_write(cmd, INTEL_CMD_ITEM_SCISSOR_RECT,
Chia-I Wue6073342014-11-30 09:43:42 +08001327 GEN6_ALIGNMENT_SCISSOR_RECT, 2 * viewport->viewport_count,
Chia-I Wub1d450a2014-09-09 13:48:03 +08001328 &viewport->cmd[viewport->cmd_scissor_rect_pos]);
1329 } else {
1330 scissor_offset = 0;
1331 }
Chia-I Wu1744cca2014-08-22 11:10:17 +08001332
1333 gen6_3DSTATE_VIEWPORT_STATE_POINTERS(cmd,
Chia-I Wub1d450a2014-09-09 13:48:03 +08001334 clip_offset, sf_offset, cc_offset);
Chia-I Wu1744cca2014-08-22 11:10:17 +08001335
Chia-I Wub1d450a2014-09-09 13:48:03 +08001336 gen6_3DSTATE_SCISSOR_STATE_POINTERS(cmd, scissor_offset);
Chia-I Wu1744cca2014-08-22 11:10:17 +08001337}
1338
Chia-I Wu302742d2014-08-22 10:28:29 +08001339static void gen7_cc_states(struct intel_cmd *cmd)
1340{
Tony Barbourfa6cac72015-01-16 14:27:35 -07001341 const struct intel_dynamic_cb *blend = cmd->bind.state.blend;
1342 const struct intel_dynamic_ds *ds = cmd->bind.state.ds;
Chia-I Wuce9f11f2014-08-22 10:38:51 +08001343 uint32_t stencil_ref;
1344 uint32_t blend_color[4];
Chia-I Wu72292b72014-09-09 10:48:33 +08001345 uint32_t offset;
Chia-I Wu302742d2014-08-22 10:28:29 +08001346
1347 CMD_ASSERT(cmd, 7, 7.5);
1348
Chia-I Wuce9f11f2014-08-22 10:38:51 +08001349 if (!blend && !ds)
1350 return;
Chia-I Wu302742d2014-08-22 10:28:29 +08001351
Chia-I Wua6c4f152014-12-02 04:19:58 +08001352 offset = gen6_BLEND_STATE(cmd);
1353 gen7_3dstate_pointer(cmd,
1354 GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS, offset);
Chia-I Wu302742d2014-08-22 10:28:29 +08001355
Chia-I Wua6c4f152014-12-02 04:19:58 +08001356 if (blend)
Tony Barbourfa6cac72015-01-16 14:27:35 -07001357 memcpy(blend_color, blend->cb_info.blendConst, sizeof(blend_color));
Chia-I Wua6c4f152014-12-02 04:19:58 +08001358 else
Chia-I Wuce9f11f2014-08-22 10:38:51 +08001359 memset(blend_color, 0, sizeof(blend_color));
Chia-I Wuce9f11f2014-08-22 10:38:51 +08001360
1361 if (ds) {
Chia-I Wu72292b72014-09-09 10:48:33 +08001362 offset = gen6_DEPTH_STENCIL_STATE(cmd, ds);
Tony Barbourfa6cac72015-01-16 14:27:35 -07001363 stencil_ref = (ds->ds_info.stencilFrontRef && 0xff) << 24 |
1364 (ds->ds_info.stencilBackRef && 0xff) << 16;
Chia-I Wuce9f11f2014-08-22 10:38:51 +08001365 gen7_3dstate_pointer(cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +08001366 GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
1367 offset);
Tony Barbourfc2aba62015-01-22 18:01:18 -07001368 stencil_ref = (ds->ds_info.stencilFrontRef && 0xff) << 24 |
1369 (ds->ds_info.stencilBackRef && 0xff) << 16;
Chia-I Wuce9f11f2014-08-22 10:38:51 +08001370 } else {
1371 stencil_ref = 0;
1372 }
1373
Chia-I Wu72292b72014-09-09 10:48:33 +08001374 offset = gen6_COLOR_CALC_STATE(cmd, stencil_ref, blend_color);
Chia-I Wu302742d2014-08-22 10:28:29 +08001375 gen7_3dstate_pointer(cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +08001376 GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS, offset);
Chia-I Wu302742d2014-08-22 10:28:29 +08001377}
1378
Chia-I Wu1744cca2014-08-22 11:10:17 +08001379static void gen7_viewport_states(struct intel_cmd *cmd)
1380{
Tony Barbourfa6cac72015-01-16 14:27:35 -07001381 const struct intel_dynamic_vp *viewport = cmd->bind.state.viewport;
1382 const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
Chia-I Wu72292b72014-09-09 10:48:33 +08001383 uint32_t offset;
Chia-I Wu1744cca2014-08-22 11:10:17 +08001384
1385 if (!viewport)
1386 return;
1387
Tony Barbourfa6cac72015-01-16 14:27:35 -07001388 assert(viewport->cmd_len == (16 + 2 + 2 * pipeline->scissor_enable) *
Chia-I Wub1d450a2014-09-09 13:48:03 +08001389 viewport->viewport_count);
Chia-I Wu1744cca2014-08-22 11:10:17 +08001390
Chia-I Wub1d450a2014-09-09 13:48:03 +08001391 offset = cmd_state_write(cmd, INTEL_CMD_ITEM_SF_VIEWPORT,
Chia-I Wue6073342014-11-30 09:43:42 +08001392 GEN7_ALIGNMENT_SF_CLIP_VIEWPORT, 16 * viewport->viewport_count,
Chia-I Wub1d450a2014-09-09 13:48:03 +08001393 viewport->cmd);
Chia-I Wu1744cca2014-08-22 11:10:17 +08001394 gen7_3dstate_pointer(cmd,
Chia-I Wu72292b72014-09-09 10:48:33 +08001395 GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_SF_CLIP,
1396 offset);
Chia-I Wub1d450a2014-09-09 13:48:03 +08001397
1398 offset = cmd_state_write(cmd, INTEL_CMD_ITEM_CC_VIEWPORT,
Chia-I Wue6073342014-11-30 09:43:42 +08001399 GEN6_ALIGNMENT_CC_VIEWPORT, 2 * viewport->viewport_count,
Chia-I Wub1d450a2014-09-09 13:48:03 +08001400 &viewport->cmd[viewport->cmd_cc_pos]);
Chia-I Wu1744cca2014-08-22 11:10:17 +08001401 gen7_3dstate_pointer(cmd,
1402 GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
Chia-I Wub1d450a2014-09-09 13:48:03 +08001403 offset);
Chia-I Wu72292b72014-09-09 10:48:33 +08001404
Tony Barbourfa6cac72015-01-16 14:27:35 -07001405 if (pipeline->scissor_enable) {
Chia-I Wub1d450a2014-09-09 13:48:03 +08001406 offset = cmd_state_write(cmd, INTEL_CMD_ITEM_SCISSOR_RECT,
Chia-I Wue6073342014-11-30 09:43:42 +08001407 GEN6_ALIGNMENT_SCISSOR_RECT, 2 * viewport->viewport_count,
Chia-I Wub1d450a2014-09-09 13:48:03 +08001408 &viewport->cmd[viewport->cmd_scissor_rect_pos]);
Chia-I Wu1744cca2014-08-22 11:10:17 +08001409 gen7_3dstate_pointer(cmd,
1410 GEN6_RENDER_OPCODE_3DSTATE_SCISSOR_STATE_POINTERS,
Chia-I Wub1d450a2014-09-09 13:48:03 +08001411 offset);
Chia-I Wu1744cca2014-08-22 11:10:17 +08001412 }
1413}
1414
Chia-I Wu7fd5cac2014-08-27 13:19:29 +08001415static void gen6_pcb(struct intel_cmd *cmd, int subop,
Chia-I Wuf2b6d722014-09-02 08:52:27 +08001416 const struct intel_pipeline_shader *sh)
Chia-I Wu7fd5cac2014-08-27 13:19:29 +08001417{
1418 const uint8_t cmd_len = 5;
Chia-I Wu46809782014-10-07 15:40:38 +08001419 uint32_t *dw;
Chia-I Wu7fd5cac2014-08-27 13:19:29 +08001420
Chia-I Wu72292b72014-09-09 10:48:33 +08001421 cmd_batch_pointer(cmd, cmd_len, &dw);
Chia-I Wu46809782014-10-07 15:40:38 +08001422
1423 dw[0] = GEN6_RENDER_TYPE_RENDER |
1424 GEN6_RENDER_SUBTYPE_3D |
1425 subop | (cmd_len - 2);
1426 dw[1] = 0;
Chia-I Wu72292b72014-09-09 10:48:33 +08001427 dw[2] = 0;
1428 dw[3] = 0;
1429 dw[4] = 0;
Chia-I Wu7fd5cac2014-08-27 13:19:29 +08001430}
1431
1432static void gen7_pcb(struct intel_cmd *cmd, int subop,
Chia-I Wuf2b6d722014-09-02 08:52:27 +08001433 const struct intel_pipeline_shader *sh)
Chia-I Wu7fd5cac2014-08-27 13:19:29 +08001434{
1435 const uint8_t cmd_len = 7;
Chia-I Wu46809782014-10-07 15:40:38 +08001436 uint32_t *dw;
Chia-I Wuc3ddee62014-09-02 10:53:20 +08001437
Chia-I Wu72292b72014-09-09 10:48:33 +08001438 cmd_batch_pointer(cmd, cmd_len, &dw);
Chia-I Wu46809782014-10-07 15:40:38 +08001439
1440 dw[0] = GEN6_RENDER_TYPE_RENDER |
1441 GEN6_RENDER_SUBTYPE_3D |
1442 subop | (cmd_len - 2);
1443 dw[1] = 0;
Chia-I Wu72292b72014-09-09 10:48:33 +08001444 dw[2] = 0;
Chia-I Wu46809782014-10-07 15:40:38 +08001445 dw[3] = 0;
Chia-I Wu72292b72014-09-09 10:48:33 +08001446 dw[4] = 0;
1447 dw[5] = 0;
1448 dw[6] = 0;
Chia-I Wu7fd5cac2014-08-27 13:19:29 +08001449}
1450
Chia-I Wu625105f2014-10-13 15:35:29 +08001451static uint32_t emit_samplers(struct intel_cmd *cmd,
1452 const struct intel_pipeline_rmap *rmap)
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001453{
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06001454 const uint32_t border_len = (cmd_gen(cmd) >= INTEL_GEN(7)) ? 4 : 12;
1455 const uint32_t border_stride =
Chia-I Wue6073342014-11-30 09:43:42 +08001456 u_align(border_len, GEN6_ALIGNMENT_SAMPLER_BORDER_COLOR / 4);
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001457 uint32_t border_offset, *border_dw, sampler_offset, *sampler_dw;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06001458 uint32_t surface_count;
1459 uint32_t i;
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001460
1461 CMD_ASSERT(cmd, 6, 7.5);
1462
Chia-I Wu625105f2014-10-13 15:35:29 +08001463 if (!rmap || !rmap->sampler_count)
1464 return 0;
1465
Cody Northrop40316a32014-12-09 19:08:33 -07001466 surface_count = rmap->rt_count + rmap->texture_resource_count + rmap->resource_count + rmap->uav_count;
Chia-I Wu625105f2014-10-13 15:35:29 +08001467
Chia-I Wudcb509d2014-12-10 08:53:10 +08001468 /*
1469 * note that we cannot call cmd_state_pointer() here as the following
1470 * cmd_state_pointer() would invalidate the pointer
1471 */
1472 border_offset = cmd_state_reserve(cmd, INTEL_CMD_ITEM_BLOB,
Chia-I Wue6073342014-11-30 09:43:42 +08001473 GEN6_ALIGNMENT_SAMPLER_BORDER_COLOR,
Chia-I Wudcb509d2014-12-10 08:53:10 +08001474 border_stride * rmap->sampler_count);
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001475
1476 sampler_offset = cmd_state_pointer(cmd, INTEL_CMD_ITEM_SAMPLER,
Chia-I Wue6073342014-11-30 09:43:42 +08001477 GEN6_ALIGNMENT_SAMPLER_STATE,
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001478 4 * rmap->sampler_count, &sampler_dw);
1479
Chia-I Wudcb509d2014-12-10 08:53:10 +08001480 cmd_state_update(cmd, border_offset,
1481 border_stride * rmap->sampler_count, &border_dw);
1482
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001483 for (i = 0; i < rmap->sampler_count; i++) {
1484 const struct intel_pipeline_rmap_slot *slot =
1485 &rmap->slots[surface_count + i];
1486 const struct intel_sampler *sampler;
1487
Chia-I Wuf8385062015-01-04 16:27:24 +08001488 switch (slot->type) {
1489 case INTEL_PIPELINE_RMAP_SAMPLER:
1490 intel_desc_pool_read_sampler(cmd->dev->desc_pool,
1491 &slot->u.sampler, &sampler);
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001492 break;
Chia-I Wuf8385062015-01-04 16:27:24 +08001493 case INTEL_PIPELINE_RMAP_UNUSED:
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001494 sampler = NULL;
1495 break;
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001496 default:
Chia-I Wuf8385062015-01-04 16:27:24 +08001497 assert(!"unexpected rmap type");
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001498 sampler = NULL;
1499 break;
1500 }
1501
1502 if (sampler) {
1503 memcpy(border_dw, &sampler->cmd[3], border_len * 4);
1504
1505 sampler_dw[0] = sampler->cmd[0];
1506 sampler_dw[1] = sampler->cmd[1];
1507 sampler_dw[2] = border_offset;
1508 sampler_dw[3] = sampler->cmd[2];
1509 } else {
1510 sampler_dw[0] = GEN6_SAMPLER_DW0_DISABLE;
1511 sampler_dw[1] = 0;
1512 sampler_dw[2] = 0;
1513 sampler_dw[3] = 0;
1514 }
1515
1516 border_offset += border_stride * 4;
1517 border_dw += border_stride;
1518 sampler_dw += 4;
1519 }
1520
Chia-I Wu625105f2014-10-13 15:35:29 +08001521 return sampler_offset;
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001522}
1523
Chia-I Wu8f6043a2014-10-13 15:44:06 +08001524static uint32_t emit_binding_table(struct intel_cmd *cmd,
Cody Northrop7c76f302014-12-18 11:52:58 -07001525 const struct intel_pipeline_rmap *rmap,
1526 const XGL_PIPELINE_SHADER_STAGE stage)
Chia-I Wu42a56202014-08-23 16:47:48 +08001527{
Chia-I Wuf98dd882015-02-10 04:17:47 +08001528 const uint32_t sba_offset =
1529 cmd->writers[INTEL_CMD_WRITER_SURFACE].sba_offset;
Chia-I Wu72292b72014-09-09 10:48:33 +08001530 uint32_t binding_table[256], offset;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06001531 uint32_t surface_count, i;
Chia-I Wu42a56202014-08-23 16:47:48 +08001532
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001533 CMD_ASSERT(cmd, 6, 7.5);
1534
Chia-I Wu8f6043a2014-10-13 15:44:06 +08001535 surface_count = (rmap) ?
Cody Northrop40316a32014-12-09 19:08:33 -07001536 rmap->rt_count + rmap->texture_resource_count + rmap->resource_count + rmap->uav_count : 0;
Chia-I Wu8f6043a2014-10-13 15:44:06 +08001537 if (!surface_count)
1538 return 0;
1539
Chia-I Wu42a56202014-08-23 16:47:48 +08001540 assert(surface_count <= ARRAY_SIZE(binding_table));
1541
1542 for (i = 0; i < surface_count; i++) {
Chia-I Wu20983762014-09-02 12:07:28 +08001543 const struct intel_pipeline_rmap_slot *slot = &rmap->slots[i];
Chia-I Wuf8385062015-01-04 16:27:24 +08001544 struct intel_null_view null_view;
1545 bool need_null_view = false;
Chia-I Wu42a56202014-08-23 16:47:48 +08001546
Chia-I Wuf8385062015-01-04 16:27:24 +08001547 switch (slot->type) {
1548 case INTEL_PIPELINE_RMAP_RT:
Chia-I Wu42a56202014-08-23 16:47:48 +08001549 {
Chia-I Wu787a05b2014-12-05 11:02:20 +08001550 const struct intel_rt_view *view =
Chia-I Wuf8385062015-01-04 16:27:24 +08001551 (slot->u.rt < cmd->bind.render_pass->fb->rt_count) ?
1552 cmd->bind.render_pass->fb->rt[slot->u.rt] : NULL;
Chia-I Wu42a56202014-08-23 16:47:48 +08001553
Chia-I Wu787a05b2014-12-05 11:02:20 +08001554 if (view) {
1555 offset = cmd_surface_write(cmd, INTEL_CMD_ITEM_SURFACE,
1556 GEN6_ALIGNMENT_SURFACE_STATE,
1557 view->cmd_len, view->cmd);
Chia-I Wu42a56202014-08-23 16:47:48 +08001558
Chia-I Wu787a05b2014-12-05 11:02:20 +08001559 cmd_reserve_reloc(cmd, 1);
1560 cmd_surface_reloc(cmd, offset, 1, view->img->obj.mem->bo,
1561 view->cmd[1], INTEL_RELOC_WRITE);
1562 } else {
Chia-I Wuf8385062015-01-04 16:27:24 +08001563 need_null_view = true;
Chia-I Wu787a05b2014-12-05 11:02:20 +08001564 }
Chia-I Wu42a56202014-08-23 16:47:48 +08001565 }
1566 break;
Chia-I Wuf8385062015-01-04 16:27:24 +08001567 case INTEL_PIPELINE_RMAP_SURFACE:
Chia-I Wu42a56202014-08-23 16:47:48 +08001568 {
Chia-I Wuf8385062015-01-04 16:27:24 +08001569 const int32_t dyn_idx = slot->u.surface.dynamic_offset_index;
1570 const struct intel_mem *mem;
1571 bool read_only;
1572 const uint32_t *cmd_data;
1573 uint32_t cmd_len;
Chia-I Wu42a56202014-08-23 16:47:48 +08001574
Chia-I Wuf8385062015-01-04 16:27:24 +08001575 assert(dyn_idx < 0 || dyn_idx <
1576 cmd->bind.dset.graphics->layout->dynamic_desc_count);
Chia-I Wu42a56202014-08-23 16:47:48 +08001577
Chia-I Wuf8385062015-01-04 16:27:24 +08001578 intel_desc_pool_read_surface(cmd->dev->desc_pool,
1579 &slot->u.surface.offset, stage, &mem,
1580 &read_only, &cmd_data, &cmd_len);
1581 if (mem) {
1582 const uint32_t dynamic_offset = (dyn_idx >= 0) ?
1583 cmd->bind.dset.graphics_dynamic_offsets[dyn_idx] : 0;
1584 const uint32_t reloc_flags =
1585 (read_only) ? 0 : INTEL_RELOC_WRITE;
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001586
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001587 offset = cmd_surface_write(cmd, INTEL_CMD_ITEM_SURFACE,
Chia-I Wue6073342014-11-30 09:43:42 +08001588 GEN6_ALIGNMENT_SURFACE_STATE,
Chia-I Wuf8385062015-01-04 16:27:24 +08001589 cmd_len, cmd_data);
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001590
1591 cmd_reserve_reloc(cmd, 1);
Chia-I Wuf8385062015-01-04 16:27:24 +08001592 cmd_surface_reloc(cmd, offset, 1, mem->bo,
1593 cmd_data[1] + dynamic_offset, reloc_flags);
1594 } else {
1595 need_null_view = true;
Chia-I Wufc05a2e2014-10-07 00:34:13 +08001596 }
1597 }
1598 break;
Chia-I Wuf8385062015-01-04 16:27:24 +08001599 case INTEL_PIPELINE_RMAP_UNUSED:
1600 need_null_view = true;
Chia-I Wu42a56202014-08-23 16:47:48 +08001601 break;
Chia-I Wuf8385062015-01-04 16:27:24 +08001602 default:
1603 assert(!"unexpected rmap type");
1604 need_null_view = true;
1605 break;
1606 }
1607
1608 if (need_null_view) {
1609 intel_null_view_init(&null_view, cmd->dev);
1610 offset = cmd_surface_write(cmd, INTEL_CMD_ITEM_SURFACE,
1611 GEN6_ALIGNMENT_SURFACE_STATE,
1612 null_view.cmd_len, null_view.cmd);
Chia-I Wu42a56202014-08-23 16:47:48 +08001613 }
1614
Chia-I Wuf98dd882015-02-10 04:17:47 +08001615 binding_table[i] = offset - sba_offset;
Chia-I Wu42a56202014-08-23 16:47:48 +08001616 }
1617
Chia-I Wuf98dd882015-02-10 04:17:47 +08001618 offset = cmd_surface_write(cmd, INTEL_CMD_ITEM_BINDING_TABLE,
Chia-I Wue6073342014-11-30 09:43:42 +08001619 GEN6_ALIGNMENT_BINDING_TABLE_STATE,
Chia-I Wuf98dd882015-02-10 04:17:47 +08001620 surface_count, binding_table) - sba_offset;
1621
1622 /* there is a 64KB limit on BINIDNG_TABLE_STATEs */
1623 assert(offset + sizeof(uint32_t) * surface_count <= 64 * 1024);
1624
1625 return offset;
Chia-I Wu42a56202014-08-23 16:47:48 +08001626}
1627
Chia-I Wu1d125092014-10-08 08:49:38 +08001628static void gen6_3DSTATE_VERTEX_BUFFERS(struct intel_cmd *cmd)
1629{
1630 const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
Chia-I Wu1d125092014-10-08 08:49:38 +08001631 const uint8_t cmd_len = 1 + 4 * pipeline->vb_count;
1632 uint32_t *dw;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06001633 uint32_t pos, i;
Chia-I Wu1d125092014-10-08 08:49:38 +08001634
1635 CMD_ASSERT(cmd, 6, 7.5);
1636
1637 if (!pipeline->vb_count)
1638 return;
1639
1640 pos = cmd_batch_pointer(cmd, cmd_len, &dw);
1641
1642 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_BUFFERS) | (cmd_len - 2);
1643 dw++;
1644 pos++;
1645
1646 for (i = 0; i < pipeline->vb_count; i++) {
Chia-I Wu1d125092014-10-08 08:49:38 +08001647 assert(pipeline->vb[i].strideInBytes <= 2048);
1648
1649 dw[0] = i << GEN6_VB_STATE_DW0_INDEX__SHIFT |
1650 pipeline->vb[i].strideInBytes;
1651
1652 if (cmd_gen(cmd) >= INTEL_GEN(7))
1653 dw[0] |= GEN7_VB_STATE_DW0_ADDR_MODIFIED;
1654
1655 switch (pipeline->vb[i].stepRate) {
1656 case XGL_VERTEX_INPUT_STEP_RATE_VERTEX:
1657 dw[0] |= GEN6_VB_STATE_DW0_ACCESS_VERTEXDATA;
1658 dw[3] = 0;
1659 break;
1660 case XGL_VERTEX_INPUT_STEP_RATE_INSTANCE:
1661 dw[0] |= GEN6_VB_STATE_DW0_ACCESS_INSTANCEDATA;
1662 dw[3] = 1;
1663 break;
1664 case XGL_VERTEX_INPUT_STEP_RATE_DRAW:
1665 dw[0] |= GEN6_VB_STATE_DW0_ACCESS_INSTANCEDATA;
1666 dw[3] = 0;
1667 break;
1668 default:
1669 assert(!"unknown step rate");
1670 dw[0] |= GEN6_VB_STATE_DW0_ACCESS_VERTEXDATA;
1671 dw[3] = 0;
1672 break;
1673 }
1674
Chia-I Wu714df452015-01-01 07:55:04 +08001675 if (cmd->bind.vertex.buf[i]) {
1676 const struct intel_buf *buf = cmd->bind.vertex.buf[i];
Chia-I Wu3b04af52014-11-08 10:48:20 +08001677 const XGL_GPU_SIZE offset = cmd->bind.vertex.offset[i];
Chia-I Wu1d125092014-10-08 08:49:38 +08001678
1679 cmd_reserve_reloc(cmd, 2);
Chia-I Wu714df452015-01-01 07:55:04 +08001680 cmd_batch_reloc(cmd, pos + 1, buf->obj.mem->bo, offset, 0);
1681 cmd_batch_reloc(cmd, pos + 2, buf->obj.mem->bo, buf->size - 1, 0);
Chia-I Wu1d125092014-10-08 08:49:38 +08001682 } else {
1683 dw[0] |= GEN6_VB_STATE_DW0_IS_NULL;
1684 dw[1] = 0;
1685 dw[2] = 0;
1686 }
1687
1688 dw += 4;
1689 pos += 4;
1690 }
1691}
1692
Courtney Goeltzenleuchter3d72e8c2014-08-29 16:27:47 -06001693static void gen6_3DSTATE_VS(struct intel_cmd *cmd)
1694{
Chia-I Wu72f9b8d2014-09-02 13:27:48 +08001695 const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
1696 const struct intel_pipeline_shader *vs = &pipeline->vs;
1697 const uint8_t cmd_len = 6;
Courtney Goeltzenleuchter3d72e8c2014-08-29 16:27:47 -06001698 const uint32_t dw0 = GEN6_RENDER_CMD(3D, 3DSTATE_VS) | (cmd_len - 2);
Chia-I Wu72292b72014-09-09 10:48:33 +08001699 uint32_t dw2, dw4, dw5, *dw;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06001700 uint32_t pos;
Chia-I Wu05990612014-11-25 11:36:35 +08001701 int vue_read_len;
Courtney Goeltzenleuchter3d72e8c2014-08-29 16:27:47 -06001702
1703 CMD_ASSERT(cmd, 6, 7.5);
1704
Courtney Goeltzenleuchter3d72e8c2014-08-29 16:27:47 -06001705 /*
Chia-I Wu72f9b8d2014-09-02 13:27:48 +08001706 * From the Sandy Bridge PRM, volume 2 part 1, page 135:
1707 *
1708 * "(Vertex URB Entry Read Length) Specifies the number of pairs of
1709 * 128-bit vertex elements to be passed into the payload for each
1710 * vertex."
1711 *
1712 * "It is UNDEFINED to set this field to 0 indicating no Vertex URB
1713 * data to be read and passed to the thread."
Courtney Goeltzenleuchter3d72e8c2014-08-29 16:27:47 -06001714 */
Chia-I Wu72f9b8d2014-09-02 13:27:48 +08001715 vue_read_len = (vs->in_count + 1) / 2;
1716 if (!vue_read_len)
1717 vue_read_len = 1;
1718
1719 dw2 = (vs->sampler_count + 3) / 4 << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
1720 vs->surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
1721
1722 dw4 = vs->urb_grf_start << GEN6_VS_DW4_URB_GRF_START__SHIFT |
1723 vue_read_len << GEN6_VS_DW4_URB_READ_LEN__SHIFT |
1724 0 << GEN6_VS_DW4_URB_READ_OFFSET__SHIFT;
Courtney Goeltzenleuchter3d72e8c2014-08-29 16:27:47 -06001725
1726 dw5 = GEN6_VS_DW5_STATISTICS |
1727 GEN6_VS_DW5_VS_ENABLE;
Chia-I Wu72f9b8d2014-09-02 13:27:48 +08001728
Chia-I Wu72f9b8d2014-09-02 13:27:48 +08001729 if (cmd_gen(cmd) >= INTEL_GEN(7.5))
Chia-I Wu3f4bd102014-12-19 13:14:42 +08001730 dw5 |= (vs->max_threads - 1) << GEN75_VS_DW5_MAX_THREADS__SHIFT;
Chia-I Wu72f9b8d2014-09-02 13:27:48 +08001731 else
Chia-I Wu3f4bd102014-12-19 13:14:42 +08001732 dw5 |= (vs->max_threads - 1) << GEN6_VS_DW5_MAX_THREADS__SHIFT;
Chia-I Wu72f9b8d2014-09-02 13:27:48 +08001733
Chia-I Wube0a3d92014-09-02 13:20:59 +08001734 if (pipeline->disable_vs_cache)
1735 dw5 |= GEN6_VS_DW5_CACHE_DISABLE;
1736
Chia-I Wu784d3042014-12-19 14:30:04 +08001737 pos = cmd_batch_pointer(cmd, cmd_len, &dw);
Chia-I Wu72292b72014-09-09 10:48:33 +08001738 dw[0] = dw0;
Chia-I Wua57761b2014-10-14 14:27:44 +08001739 dw[1] = cmd->bind.pipeline.vs_offset;
Chia-I Wu72292b72014-09-09 10:48:33 +08001740 dw[2] = dw2;
1741 dw[3] = 0; /* scratch */
1742 dw[4] = dw4;
1743 dw[5] = dw5;
Chia-I Wu784d3042014-12-19 14:30:04 +08001744
1745 if (vs->per_thread_scratch_size)
1746 gen6_add_scratch_space(cmd, pos + 3, pipeline, vs);
Courtney Goeltzenleuchter3d72e8c2014-08-29 16:27:47 -06001747}
1748
Chia-I Wu625105f2014-10-13 15:35:29 +08001749static void emit_shader_resources(struct intel_cmd *cmd)
1750{
1751 /* five HW shader stages */
Chia-I Wu8f6043a2014-10-13 15:44:06 +08001752 uint32_t binding_tables[5], samplers[5];
Chia-I Wu625105f2014-10-13 15:35:29 +08001753
Chia-I Wu8f6043a2014-10-13 15:44:06 +08001754 binding_tables[0] = emit_binding_table(cmd,
Cody Northrop7c76f302014-12-18 11:52:58 -07001755 cmd->bind.pipeline.graphics->vs.rmap,
1756 XGL_SHADER_STAGE_VERTEX);
Chia-I Wu8f6043a2014-10-13 15:44:06 +08001757 binding_tables[1] = emit_binding_table(cmd,
Cody Northrop7c76f302014-12-18 11:52:58 -07001758 cmd->bind.pipeline.graphics->tcs.rmap,
1759 XGL_SHADER_STAGE_TESS_CONTROL);
Chia-I Wu8f6043a2014-10-13 15:44:06 +08001760 binding_tables[2] = emit_binding_table(cmd,
Cody Northrop7c76f302014-12-18 11:52:58 -07001761 cmd->bind.pipeline.graphics->tes.rmap,
1762 XGL_SHADER_STAGE_TESS_EVALUATION);
Chia-I Wu8f6043a2014-10-13 15:44:06 +08001763 binding_tables[3] = emit_binding_table(cmd,
Cody Northrop7c76f302014-12-18 11:52:58 -07001764 cmd->bind.pipeline.graphics->gs.rmap,
1765 XGL_SHADER_STAGE_GEOMETRY);
Chia-I Wu8f6043a2014-10-13 15:44:06 +08001766 binding_tables[4] = emit_binding_table(cmd,
Cody Northrop7c76f302014-12-18 11:52:58 -07001767 cmd->bind.pipeline.graphics->fs.rmap,
1768 XGL_SHADER_STAGE_FRAGMENT);
Chia-I Wu625105f2014-10-13 15:35:29 +08001769
1770 samplers[0] = emit_samplers(cmd, cmd->bind.pipeline.graphics->vs.rmap);
1771 samplers[1] = emit_samplers(cmd, cmd->bind.pipeline.graphics->tcs.rmap);
1772 samplers[2] = emit_samplers(cmd, cmd->bind.pipeline.graphics->tes.rmap);
1773 samplers[3] = emit_samplers(cmd, cmd->bind.pipeline.graphics->gs.rmap);
1774 samplers[4] = emit_samplers(cmd, cmd->bind.pipeline.graphics->fs.rmap);
1775
1776 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
1777 gen7_3dstate_pointer(cmd,
Chia-I Wu8f6043a2014-10-13 15:44:06 +08001778 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_VS,
1779 binding_tables[0]);
1780 gen7_3dstate_pointer(cmd,
1781 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_HS,
1782 binding_tables[1]);
1783 gen7_3dstate_pointer(cmd,
1784 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_DS,
1785 binding_tables[2]);
1786 gen7_3dstate_pointer(cmd,
1787 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_GS,
1788 binding_tables[3]);
1789 gen7_3dstate_pointer(cmd,
1790 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS,
1791 binding_tables[4]);
1792
1793 gen7_3dstate_pointer(cmd,
Chia-I Wu625105f2014-10-13 15:35:29 +08001794 GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_VS,
1795 samplers[0]);
1796 gen7_3dstate_pointer(cmd,
1797 GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_HS,
1798 samplers[1]);
1799 gen7_3dstate_pointer(cmd,
1800 GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_DS,
1801 samplers[2]);
1802 gen7_3dstate_pointer(cmd,
1803 GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_GS,
1804 samplers[3]);
1805 gen7_3dstate_pointer(cmd,
1806 GEN7_RENDER_OPCODE_3DSTATE_SAMPLER_STATE_POINTERS_PS,
1807 samplers[4]);
1808 } else {
Chia-I Wu8f6043a2014-10-13 15:44:06 +08001809 assert(!binding_tables[1] && !binding_tables[2]);
1810 gen6_3DSTATE_BINDING_TABLE_POINTERS(cmd,
1811 binding_tables[0], binding_tables[3], binding_tables[4]);
1812
Chia-I Wu625105f2014-10-13 15:35:29 +08001813 assert(!samplers[1] && !samplers[2]);
1814 gen6_3DSTATE_SAMPLER_STATE_POINTERS(cmd,
1815 samplers[0], samplers[3], samplers[4]);
1816 }
1817}
1818
Chia-I Wu2e5ec9b2014-10-14 13:37:21 +08001819static void emit_rt(struct intel_cmd *cmd)
1820{
1821 cmd_wa_gen6_pre_depth_stall_write(cmd);
Jon Ashburnc04b4dc2015-01-08 18:48:10 -07001822 gen6_3DSTATE_DRAWING_RECTANGLE(cmd, cmd->bind.render_pass->fb->width,
1823 cmd->bind.render_pass->fb->height);
Chia-I Wu2e5ec9b2014-10-14 13:37:21 +08001824}
1825
1826static void emit_ds(struct intel_cmd *cmd)
1827{
Jon Ashburnc04b4dc2015-01-08 18:48:10 -07001828 const struct intel_ds_view *ds = cmd->bind.render_pass->fb->ds;
Chia-I Wu2e5ec9b2014-10-14 13:37:21 +08001829
1830 if (!ds) {
1831 /* all zeros */
1832 static const struct intel_ds_view null_ds;
1833 ds = &null_ds;
1834 }
1835
1836 cmd_wa_gen6_pre_ds_flush(cmd);
1837 gen6_3DSTATE_DEPTH_BUFFER(cmd, ds);
1838 gen6_3DSTATE_STENCIL_BUFFER(cmd, ds);
1839 gen6_3DSTATE_HIER_DEPTH_BUFFER(cmd, ds);
1840
1841 if (cmd_gen(cmd) >= INTEL_GEN(7))
1842 gen7_3DSTATE_CLEAR_PARAMS(cmd, 0);
1843 else
1844 gen6_3DSTATE_CLEAR_PARAMS(cmd, 0);
1845}
1846
Chia-I Wua57761b2014-10-14 14:27:44 +08001847static uint32_t emit_shader(struct intel_cmd *cmd,
1848 const struct intel_pipeline_shader *shader)
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -06001849{
Chia-I Wua57761b2014-10-14 14:27:44 +08001850 struct intel_cmd_shader_cache *cache = &cmd->bind.shader_cache;
1851 uint32_t offset;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06001852 uint32_t i;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -06001853
Chia-I Wua57761b2014-10-14 14:27:44 +08001854 /* see if the shader is already in the cache */
1855 for (i = 0; i < cache->used; i++) {
1856 if (cache->entries[i].shader == (const void *) shader)
1857 return cache->entries[i].kernel_offset;
1858 }
1859
1860 offset = cmd_instruction_write(cmd, shader->codeSize, shader->pCode);
1861
1862 /* grow the cache if full */
1863 if (cache->used >= cache->count) {
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06001864 const uint32_t count = cache->count + 16;
Chia-I Wua57761b2014-10-14 14:27:44 +08001865 void *entries;
1866
1867 entries = icd_alloc(sizeof(cache->entries[0]) * count, 0,
1868 XGL_SYSTEM_ALLOC_INTERNAL);
1869 if (entries) {
1870 if (cache->entries) {
1871 memcpy(entries, cache->entries,
1872 sizeof(cache->entries[0]) * cache->used);
1873 icd_free(cache->entries);
1874 }
1875
1876 cache->entries = entries;
1877 cache->count = count;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -06001878 }
1879 }
1880
Chia-I Wua57761b2014-10-14 14:27:44 +08001881 /* add the shader to the cache */
1882 if (cache->used < cache->count) {
1883 cache->entries[cache->used].shader = (const void *) shader;
1884 cache->entries[cache->used].kernel_offset = offset;
1885 cache->used++;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -06001886 }
1887
Chia-I Wua57761b2014-10-14 14:27:44 +08001888 return offset;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -06001889}
1890
Chia-I Wuc29afdd2014-10-14 13:22:31 +08001891static void emit_graphics_pipeline(struct intel_cmd *cmd)
Chia-I Wu9f1722c2014-08-25 10:17:58 +08001892{
Chia-I Wuc29afdd2014-10-14 13:22:31 +08001893 const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
Chia-I Wubb2d8ca2014-08-28 23:15:48 +08001894
Chia-I Wu8370b402014-08-29 12:28:37 +08001895 if (pipeline->wa_flags & INTEL_CMD_WA_GEN6_PRE_DEPTH_STALL_WRITE)
1896 cmd_wa_gen6_pre_depth_stall_write(cmd);
1897 if (pipeline->wa_flags & INTEL_CMD_WA_GEN6_PRE_COMMAND_SCOREBOARD_STALL)
1898 cmd_wa_gen6_pre_command_scoreboard_stall(cmd);
1899 if (pipeline->wa_flags & INTEL_CMD_WA_GEN7_PRE_VS_DEPTH_STALL_WRITE)
1900 cmd_wa_gen7_pre_vs_depth_stall_write(cmd);
Chia-I Wubb2d8ca2014-08-28 23:15:48 +08001901
1902 /* 3DSTATE_URB_VS and etc. */
Courtney Goeltzenleuchter814cd292014-08-28 13:16:27 -06001903 assert(pipeline->cmd_len);
Chia-I Wu72292b72014-09-09 10:48:33 +08001904 cmd_batch_write(cmd, pipeline->cmd_len, pipeline->cmds);
Chia-I Wubb2d8ca2014-08-28 23:15:48 +08001905
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -06001906 if (pipeline->active_shaders & SHADER_VERTEX_FLAG) {
Chia-I Wua57761b2014-10-14 14:27:44 +08001907 cmd->bind.pipeline.vs_offset = emit_shader(cmd, &pipeline->vs);
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -06001908 }
1909 if (pipeline->active_shaders & SHADER_TESS_CONTROL_FLAG) {
Chia-I Wua57761b2014-10-14 14:27:44 +08001910 cmd->bind.pipeline.tcs_offset = emit_shader(cmd, &pipeline->tcs);
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -06001911 }
1912 if (pipeline->active_shaders & SHADER_TESS_EVAL_FLAG) {
Chia-I Wua57761b2014-10-14 14:27:44 +08001913 cmd->bind.pipeline.tes_offset = emit_shader(cmd, &pipeline->tes);
1914 }
1915 if (pipeline->active_shaders & SHADER_GEOMETRY_FLAG) {
1916 cmd->bind.pipeline.gs_offset = emit_shader(cmd, &pipeline->gs);
1917 }
1918 if (pipeline->active_shaders & SHADER_FRAGMENT_FLAG) {
1919 cmd->bind.pipeline.fs_offset = emit_shader(cmd, &pipeline->fs);
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -06001920 }
Courtney Goeltzenleuchter68d9bef2014-08-28 17:35:03 -06001921
Chia-I Wud95aa2b2014-08-29 12:07:47 +08001922 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
1923 gen7_3DSTATE_GS(cmd);
1924 } else {
1925 gen6_3DSTATE_GS(cmd);
1926 }
Courtney Goeltzenleuchterf782a852014-08-28 17:44:53 -06001927
Chia-I Wu8370b402014-08-29 12:28:37 +08001928 if (pipeline->wa_flags & INTEL_CMD_WA_GEN7_POST_COMMAND_CS_STALL)
1929 cmd_wa_gen7_post_command_cs_stall(cmd);
1930 if (pipeline->wa_flags & INTEL_CMD_WA_GEN7_POST_COMMAND_DEPTH_STALL)
1931 cmd_wa_gen7_post_command_depth_stall(cmd);
Chia-I Wu9f1722c2014-08-25 10:17:58 +08001932}
1933
Chia-I Wuc29afdd2014-10-14 13:22:31 +08001934static void emit_bounded_states(struct intel_cmd *cmd)
1935{
Chia-I Wuc29afdd2014-10-14 13:22:31 +08001936
1937 emit_graphics_pipeline(cmd);
1938
1939 emit_rt(cmd);
1940 emit_ds(cmd);
1941
1942 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
1943 gen7_cc_states(cmd);
1944 gen7_viewport_states(cmd);
1945
1946 gen7_pcb(cmd, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS,
1947 &cmd->bind.pipeline.graphics->vs);
1948 gen7_pcb(cmd, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS,
1949 &cmd->bind.pipeline.graphics->fs);
1950
1951 gen6_3DSTATE_CLIP(cmd);
1952 gen7_3DSTATE_SF(cmd);
Chia-I Wuc29afdd2014-10-14 13:22:31 +08001953 gen7_3DSTATE_WM(cmd);
1954 gen7_3DSTATE_PS(cmd);
1955 } else {
1956 gen6_cc_states(cmd);
1957 gen6_viewport_states(cmd);
1958
1959 gen6_pcb(cmd, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_VS,
1960 &cmd->bind.pipeline.graphics->vs);
1961 gen6_pcb(cmd, GEN6_RENDER_OPCODE_3DSTATE_CONSTANT_PS,
1962 &cmd->bind.pipeline.graphics->fs);
1963
1964 gen6_3DSTATE_CLIP(cmd);
1965 gen6_3DSTATE_SF(cmd);
1966 gen6_3DSTATE_WM(cmd);
1967 }
1968
1969 emit_shader_resources(cmd);
1970
1971 cmd_wa_gen6_pre_depth_stall_write(cmd);
1972 cmd_wa_gen6_pre_multisample_depth_flush(cmd);
1973
Chia-I Wuc29afdd2014-10-14 13:22:31 +08001974 gen6_3DSTATE_VERTEX_BUFFERS(cmd);
1975 gen6_3DSTATE_VS(cmd);
1976}
1977
Tony Barbourfa6cac72015-01-16 14:27:35 -07001978static uint32_t gen6_meta_DEPTH_STENCIL_STATE(struct intel_cmd *cmd,
1979 const struct intel_cmd_meta *meta)
1980{
1981 const uint8_t cmd_align = GEN6_ALIGNMENT_DEPTH_STENCIL_STATE;
1982 const uint8_t cmd_len = 3;
1983 uint32_t dw[3];
1984 uint32_t cmd_depth_stencil;
1985 uint32_t cmd_depth_test;
1986
1987 CMD_ASSERT(cmd, 6, 7.5);
1988
1989 cmd_depth_stencil = 0;
1990 cmd_depth_test = 0;
1991 if (meta->ds.aspect == XGL_IMAGE_ASPECT_DEPTH) {
1992 cmd_depth_test |= GEN6_ZS_DW2_DEPTH_WRITE_ENABLE |
1993 GEN6_COMPAREFUNCTION_ALWAYS << 27;
1994 }
1995 else if (meta->ds.aspect == XGL_IMAGE_ASPECT_STENCIL) {
1996 cmd_depth_stencil = 1 << 31 |
1997 (GEN6_COMPAREFUNCTION_ALWAYS) << 28 |
1998 (GEN6_STENCILOP_KEEP) << 25 |
1999 (GEN6_STENCILOP_KEEP) << 22 |
2000 (GEN6_STENCILOP_REPLACE) << 19 |
2001 1 << 15 |
2002 (GEN6_COMPAREFUNCTION_ALWAYS) << 12 |
2003 (GEN6_STENCILOP_KEEP) << 9 |
2004 (GEN6_STENCILOP_KEEP) << 6 |
2005 (GEN6_STENCILOP_REPLACE) << 3;
2006 }
2007
2008 cmd_depth_test |= GEN6_COMPAREFUNCTION_ALWAYS << 27;
2009 dw[0] = cmd_depth_stencil | 1 << 18;
2010 dw[1] = (0xff) << 24 | (0xff) << 16;
2011 dw[2] = cmd_depth_test;
2012
2013 return cmd_state_write(cmd, INTEL_CMD_ITEM_DEPTH_STENCIL,
2014 cmd_align, cmd_len, dw);
2015}
2016
Chia-I Wu6032b892014-10-17 14:47:18 +08002017static void gen6_meta_dynamic_states(struct intel_cmd *cmd)
2018{
2019 const struct intel_cmd_meta *meta = cmd->bind.meta;
2020 uint32_t blend_offset, ds_offset, cc_offset, cc_vp_offset, *dw;
2021
2022 CMD_ASSERT(cmd, 6, 7.5);
2023
2024 blend_offset = 0;
2025 ds_offset = 0;
2026 cc_offset = 0;
2027 cc_vp_offset = 0;
2028
Chia-I Wu29e6f502014-11-24 14:27:29 +08002029 if (meta->mode == INTEL_CMD_META_FS_RECT) {
Chia-I Wu6032b892014-10-17 14:47:18 +08002030 /* BLEND_STATE */
2031 blend_offset = cmd_state_pointer(cmd, INTEL_CMD_ITEM_BLEND,
Chia-I Wue6073342014-11-30 09:43:42 +08002032 GEN6_ALIGNMENT_BLEND_STATE, 2, &dw);
Chia-I Wu6032b892014-10-17 14:47:18 +08002033 dw[0] = 0;
2034 dw[1] = GEN6_BLEND_DW1_COLORCLAMP_RTFORMAT | 0x3;
2035 }
2036
Chia-I Wu29e6f502014-11-24 14:27:29 +08002037 if (meta->mode != INTEL_CMD_META_VS_POINTS) {
Tony Barbourfa6cac72015-01-16 14:27:35 -07002038 if (meta->ds.aspect != XGL_IMAGE_ASPECT_COLOR) {
Chia-I Wu29e6f502014-11-24 14:27:29 +08002039 const uint32_t blend_color[4] = { 0, 0, 0, 0 };
Tony Barbourfa6cac72015-01-16 14:27:35 -07002040 uint32_t stencil_ref = (meta->ds.stencil_ref && 0xff) << 24 |
2041 (meta->ds.stencil_ref && 0xff) << 16;
Chia-I Wu6032b892014-10-17 14:47:18 +08002042
Chia-I Wu29e6f502014-11-24 14:27:29 +08002043 /* DEPTH_STENCIL_STATE */
Tony Barbourfa6cac72015-01-16 14:27:35 -07002044 ds_offset = gen6_meta_DEPTH_STENCIL_STATE(cmd, meta);
Chia-I Wu6032b892014-10-17 14:47:18 +08002045
Chia-I Wu29e6f502014-11-24 14:27:29 +08002046 /* COLOR_CALC_STATE */
2047 cc_offset = gen6_COLOR_CALC_STATE(cmd,
Tony Barbourfa6cac72015-01-16 14:27:35 -07002048 stencil_ref, blend_color);
Chia-I Wu6032b892014-10-17 14:47:18 +08002049
Chia-I Wu29e6f502014-11-24 14:27:29 +08002050 /* CC_VIEWPORT */
2051 cc_vp_offset = cmd_state_pointer(cmd, INTEL_CMD_ITEM_CC_VIEWPORT,
Chia-I Wue6073342014-11-30 09:43:42 +08002052 GEN6_ALIGNMENT_CC_VIEWPORT, 2, &dw);
Chia-I Wu29e6f502014-11-24 14:27:29 +08002053 dw[0] = u_fui(0.0f);
2054 dw[1] = u_fui(1.0f);
2055 } else {
2056 /* DEPTH_STENCIL_STATE */
2057 ds_offset = cmd_state_pointer(cmd, INTEL_CMD_ITEM_DEPTH_STENCIL,
Chia-I Wue6073342014-11-30 09:43:42 +08002058 GEN6_ALIGNMENT_DEPTH_STENCIL_STATE,
Chia-I Wu29e6f502014-11-24 14:27:29 +08002059 GEN6_DEPTH_STENCIL_STATE__SIZE, &dw);
2060 memset(dw, 0, sizeof(*dw) * GEN6_DEPTH_STENCIL_STATE__SIZE);
2061 }
Chia-I Wu6032b892014-10-17 14:47:18 +08002062 }
2063
2064 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
2065 gen7_3dstate_pointer(cmd,
2066 GEN7_RENDER_OPCODE_3DSTATE_BLEND_STATE_POINTERS,
2067 blend_offset);
2068 gen7_3dstate_pointer(cmd,
2069 GEN7_RENDER_OPCODE_3DSTATE_DEPTH_STENCIL_STATE_POINTERS,
2070 ds_offset);
2071 gen7_3dstate_pointer(cmd,
2072 GEN6_RENDER_OPCODE_3DSTATE_CC_STATE_POINTERS, cc_offset);
2073
2074 gen7_3dstate_pointer(cmd,
2075 GEN7_RENDER_OPCODE_3DSTATE_VIEWPORT_STATE_POINTERS_CC,
2076 cc_vp_offset);
2077 } else {
2078 /* 3DSTATE_CC_STATE_POINTERS */
Chia-I Wu429a0aa2014-10-24 11:57:51 +08002079 gen6_3DSTATE_CC_STATE_POINTERS(cmd, blend_offset, ds_offset, cc_offset);
Chia-I Wu6032b892014-10-17 14:47:18 +08002080
2081 /* 3DSTATE_VIEWPORT_STATE_POINTERS */
2082 cmd_batch_pointer(cmd, 4, &dw);
2083 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VIEWPORT_STATE_POINTERS) | (4 - 2) |
2084 GEN6_PTR_VP_DW0_CC_CHANGED;
2085 dw[1] = 0;
2086 dw[2] = 0;
2087 dw[3] = cc_vp_offset;
2088 }
2089}
2090
2091static void gen6_meta_surface_states(struct intel_cmd *cmd)
2092{
2093 const struct intel_cmd_meta *meta = cmd->bind.meta;
Chia-I Wu005c47c2014-10-22 13:49:13 +08002094 uint32_t binding_table[2] = { 0, 0 };
Chia-I Wu6032b892014-10-17 14:47:18 +08002095 uint32_t offset;
Mike Stroyan9bfad482015-02-10 15:09:23 -07002096 const uint32_t sba_offset =
2097 cmd->writers[INTEL_CMD_WRITER_SURFACE].sba_offset;
Chia-I Wu6032b892014-10-17 14:47:18 +08002098
2099 CMD_ASSERT(cmd, 6, 7.5);
2100
Chia-I Wu29e6f502014-11-24 14:27:29 +08002101 if (meta->mode == INTEL_CMD_META_DEPTH_STENCIL_RECT)
2102 return;
2103
Chia-I Wu005c47c2014-10-22 13:49:13 +08002104 /* SURFACE_STATEs */
Chia-I Wu6032b892014-10-17 14:47:18 +08002105 if (meta->src.valid) {
2106 offset = cmd_surface_write(cmd, INTEL_CMD_ITEM_SURFACE,
Chia-I Wue6073342014-11-30 09:43:42 +08002107 GEN6_ALIGNMENT_SURFACE_STATE,
Chia-I Wu6032b892014-10-17 14:47:18 +08002108 meta->src.surface_len, meta->src.surface);
2109
2110 cmd_reserve_reloc(cmd, 1);
2111 if (meta->src.reloc_flags & INTEL_CMD_RELOC_TARGET_IS_WRITER) {
2112 cmd_surface_reloc_writer(cmd, offset, 1,
2113 meta->src.reloc_target, meta->src.reloc_offset);
2114 } else {
2115 cmd_surface_reloc(cmd, offset, 1,
2116 (struct intel_bo *) meta->src.reloc_target,
2117 meta->src.reloc_offset, meta->src.reloc_flags);
2118 }
2119
Mike Stroyan9bfad482015-02-10 15:09:23 -07002120 binding_table[0] = offset - sba_offset;
Chia-I Wu005c47c2014-10-22 13:49:13 +08002121 }
2122 if (meta->dst.valid) {
2123 offset = cmd_surface_write(cmd, INTEL_CMD_ITEM_SURFACE,
Chia-I Wue6073342014-11-30 09:43:42 +08002124 GEN6_ALIGNMENT_SURFACE_STATE,
Chia-I Wu005c47c2014-10-22 13:49:13 +08002125 meta->dst.surface_len, meta->dst.surface);
2126
2127 cmd_reserve_reloc(cmd, 1);
2128 cmd_surface_reloc(cmd, offset, 1,
2129 (struct intel_bo *) meta->dst.reloc_target,
2130 meta->dst.reloc_offset, meta->dst.reloc_flags);
2131
Mike Stroyan9bfad482015-02-10 15:09:23 -07002132 binding_table[1] = offset - sba_offset;
Chia-I Wu6032b892014-10-17 14:47:18 +08002133 }
2134
2135 /* BINDING_TABLE */
Chia-I Wu0b7b1a32015-02-10 04:07:29 +08002136 offset = cmd_surface_write(cmd, INTEL_CMD_ITEM_BINDING_TABLE,
Chia-I Wue6073342014-11-30 09:43:42 +08002137 GEN6_ALIGNMENT_BINDING_TABLE_STATE,
Chia-I Wu005c47c2014-10-22 13:49:13 +08002138 2, binding_table);
Chia-I Wu6032b892014-10-17 14:47:18 +08002139
2140 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
Chia-I Wu29e6f502014-11-24 14:27:29 +08002141 const int subop = (meta->mode == INTEL_CMD_META_VS_POINTS) ?
2142 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_VS :
2143 GEN7_RENDER_OPCODE_3DSTATE_BINDING_TABLE_POINTERS_PS;
Mike Stroyan9bfad482015-02-10 15:09:23 -07002144 gen7_3dstate_pointer(cmd, subop, offset - sba_offset);
Chia-I Wu6032b892014-10-17 14:47:18 +08002145 } else {
2146 /* 3DSTATE_BINDING_TABLE_POINTERS */
Chia-I Wu29e6f502014-11-24 14:27:29 +08002147 if (meta->mode == INTEL_CMD_META_VS_POINTS)
Mike Stroyan9bfad482015-02-10 15:09:23 -07002148 gen6_3DSTATE_BINDING_TABLE_POINTERS(cmd, offset - sba_offset, 0, 0);
Chia-I Wu29e6f502014-11-24 14:27:29 +08002149 else
Mike Stroyan9bfad482015-02-10 15:09:23 -07002150 gen6_3DSTATE_BINDING_TABLE_POINTERS(cmd, 0, 0, offset - sba_offset);
Chia-I Wu6032b892014-10-17 14:47:18 +08002151 }
2152}
2153
2154static void gen6_meta_urb(struct intel_cmd *cmd)
2155{
Chia-I Wu24aa1022014-11-25 11:53:19 +08002156 const int vs_entry_count = (cmd->dev->gpu->gt == 2) ? 256 : 128;
Chia-I Wu6032b892014-10-17 14:47:18 +08002157 uint32_t *dw;
2158
2159 CMD_ASSERT(cmd, 6, 6);
2160
2161 /* 3DSTATE_URB */
2162 cmd_batch_pointer(cmd, 3, &dw);
2163 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_URB) | (3 - 2);
Chia-I Wu24aa1022014-11-25 11:53:19 +08002164 dw[1] = vs_entry_count << GEN6_URB_DW1_VS_ENTRY_COUNT__SHIFT;
Chia-I Wu6032b892014-10-17 14:47:18 +08002165 dw[2] = 0;
2166}
2167
2168static void gen7_meta_urb(struct intel_cmd *cmd)
2169{
Chia-I Wu15dacac2015-02-05 11:14:01 -07002170 const int pcb_alloc = (cmd->dev->gpu->gt == 3) ? 16 : 8;
2171 const int urb_offset = pcb_alloc / 8;
Chia-I Wu24aa1022014-11-25 11:53:19 +08002172 int vs_entry_count;
Chia-I Wu6032b892014-10-17 14:47:18 +08002173 uint32_t *dw;
2174
2175 CMD_ASSERT(cmd, 7, 7.5);
2176
2177 /* 3DSTATE_PUSH_CONSTANT_ALLOC_x */
2178 cmd_batch_pointer(cmd, 10, &dw);
2179
2180 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_VS) | (2 - 2);
Chia-I Wu15dacac2015-02-05 11:14:01 -07002181 dw[1] = pcb_alloc << GEN7_PCB_ALLOC_ANY_DW1_SIZE__SHIFT;
2182 dw += 2;
2183
2184 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_PS) | (2 - 2);
2185 dw[1] = pcb_alloc << GEN7_PCB_ALLOC_ANY_DW1_OFFSET__SHIFT |
2186 pcb_alloc << GEN7_PCB_ALLOC_ANY_DW1_SIZE__SHIFT;
Chia-I Wu6032b892014-10-17 14:47:18 +08002187 dw += 2;
2188
2189 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_HS) | (2 - 2);
2190 dw[1] = 0;
2191 dw += 2;
2192
2193 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_DS) | (2 - 2);
2194 dw[1] = 0;
2195 dw += 2;
2196
2197 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PUSH_CONSTANT_ALLOC_GS) | (2 - 2);
2198 dw[1] = 0;
Chia-I Wu6032b892014-10-17 14:47:18 +08002199
Chia-I Wu15dacac2015-02-05 11:14:01 -07002200 cmd_wa_gen7_post_command_cs_stall(cmd);
Chia-I Wu6032b892014-10-17 14:47:18 +08002201
2202 cmd_wa_gen7_pre_vs_depth_stall_write(cmd);
2203
Chia-I Wu24aa1022014-11-25 11:53:19 +08002204 switch (cmd_gen(cmd)) {
2205 case INTEL_GEN(7.5):
2206 vs_entry_count = (cmd->dev->gpu->gt >= 2) ? 1664 : 640;
2207 break;
2208 case INTEL_GEN(7):
2209 default:
2210 vs_entry_count = (cmd->dev->gpu->gt == 2) ? 704 : 512;
2211 break;
2212 }
2213
Chia-I Wu6032b892014-10-17 14:47:18 +08002214 /* 3DSTATE_URB_x */
2215 cmd_batch_pointer(cmd, 8, &dw);
2216
2217 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_URB_VS) | (2 - 2);
Chia-I Wu15dacac2015-02-05 11:14:01 -07002218 dw[1] = urb_offset << GEN7_URB_ANY_DW1_OFFSET__SHIFT |
Chia-I Wu24aa1022014-11-25 11:53:19 +08002219 vs_entry_count;
Chia-I Wu6032b892014-10-17 14:47:18 +08002220 dw += 2;
2221
2222 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_URB_HS) | (2 - 2);
Chia-I Wu15dacac2015-02-05 11:14:01 -07002223 dw[1] = urb_offset << GEN7_URB_ANY_DW1_OFFSET__SHIFT;
Chia-I Wu6032b892014-10-17 14:47:18 +08002224 dw += 2;
2225
2226 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_URB_DS) | (2 - 2);
Chia-I Wu15dacac2015-02-05 11:14:01 -07002227 dw[1] = urb_offset << GEN7_URB_ANY_DW1_OFFSET__SHIFT;
Chia-I Wu6032b892014-10-17 14:47:18 +08002228 dw += 2;
2229
2230 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_URB_GS) | (2 - 2);
Chia-I Wu15dacac2015-02-05 11:14:01 -07002231 dw[1] = urb_offset << GEN7_URB_ANY_DW1_OFFSET__SHIFT;
Chia-I Wu6032b892014-10-17 14:47:18 +08002232 dw += 2;
2233}
2234
2235static void gen6_meta_vf(struct intel_cmd *cmd)
2236{
2237 const struct intel_cmd_meta *meta = cmd->bind.meta;
Chia-I Wu3adf7212014-10-24 15:34:07 +08002238 uint32_t vb_start, vb_end, vb_stride;
2239 int ve_format, ve_z_source;
2240 uint32_t *dw;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06002241 uint32_t pos;
Chia-I Wu6032b892014-10-17 14:47:18 +08002242
2243 CMD_ASSERT(cmd, 6, 7.5);
2244
Chia-I Wu29e6f502014-11-24 14:27:29 +08002245 switch (meta->mode) {
2246 case INTEL_CMD_META_VS_POINTS:
2247 cmd_batch_pointer(cmd, 3, &dw);
2248 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_ELEMENTS) | (3 - 2);
2249 dw[1] = GEN6_VE_STATE_DW0_VALID;
2250 dw[2] = GEN6_VFCOMP_STORE_VID << GEN6_VE_STATE_DW1_COMP0__SHIFT |
2251 GEN6_VFCOMP_NOSTORE << GEN6_VE_STATE_DW1_COMP1__SHIFT |
2252 GEN6_VFCOMP_NOSTORE << GEN6_VE_STATE_DW1_COMP2__SHIFT |
2253 GEN6_VFCOMP_NOSTORE << GEN6_VE_STATE_DW1_COMP3__SHIFT;
2254 return;
2255 break;
2256 case INTEL_CMD_META_FS_RECT:
2257 {
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06002258 uint32_t vertices[3][2];
Chia-I Wu3adf7212014-10-24 15:34:07 +08002259
Chia-I Wu29e6f502014-11-24 14:27:29 +08002260 vertices[0][0] = meta->dst.x + meta->width;
2261 vertices[0][1] = meta->dst.y + meta->height;
2262 vertices[1][0] = meta->dst.x;
2263 vertices[1][1] = meta->dst.y + meta->height;
2264 vertices[2][0] = meta->dst.x;
2265 vertices[2][1] = meta->dst.y;
Chia-I Wu3adf7212014-10-24 15:34:07 +08002266
Chia-I Wu29e6f502014-11-24 14:27:29 +08002267 vb_start = cmd_state_write(cmd, INTEL_CMD_ITEM_BLOB, 32,
2268 sizeof(vertices) / 4, (const uint32_t *) vertices);
Chia-I Wu3adf7212014-10-24 15:34:07 +08002269
Chia-I Wu29e6f502014-11-24 14:27:29 +08002270 vb_end = vb_start + sizeof(vertices) - 1;
2271 vb_stride = sizeof(vertices[0]);
2272 ve_z_source = GEN6_VFCOMP_STORE_0;
2273 ve_format = GEN6_FORMAT_R32G32_USCALED;
2274 }
2275 break;
2276 case INTEL_CMD_META_DEPTH_STENCIL_RECT:
2277 {
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06002278 float vertices[3][3];
Chia-I Wu3adf7212014-10-24 15:34:07 +08002279
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06002280 vertices[0][0] = (float) (meta->dst.x + meta->width);
2281 vertices[0][1] = (float) (meta->dst.y + meta->height);
Chia-I Wu29e6f502014-11-24 14:27:29 +08002282 vertices[0][2] = u_uif(meta->clear_val[0]);
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06002283 vertices[1][0] = (float) meta->dst.x;
2284 vertices[1][1] = (float) (meta->dst.y + meta->height);
Chia-I Wu29e6f502014-11-24 14:27:29 +08002285 vertices[1][2] = u_uif(meta->clear_val[0]);
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06002286 vertices[2][0] = (float) meta->dst.x;
2287 vertices[2][1] = (float) meta->dst.y;
Chia-I Wu29e6f502014-11-24 14:27:29 +08002288 vertices[2][2] = u_uif(meta->clear_val[0]);
Chia-I Wu3adf7212014-10-24 15:34:07 +08002289
Chia-I Wu29e6f502014-11-24 14:27:29 +08002290 vb_start = cmd_state_write(cmd, INTEL_CMD_ITEM_BLOB, 32,
2291 sizeof(vertices) / 4, (const uint32_t *) vertices);
Chia-I Wu3adf7212014-10-24 15:34:07 +08002292
Chia-I Wu29e6f502014-11-24 14:27:29 +08002293 vb_end = vb_start + sizeof(vertices) - 1;
2294 vb_stride = sizeof(vertices[0]);
2295 ve_z_source = GEN6_VFCOMP_STORE_SRC;
2296 ve_format = GEN6_FORMAT_R32G32B32_FLOAT;
2297 }
2298 break;
2299 default:
2300 assert(!"unknown meta mode");
2301 return;
2302 break;
Chia-I Wu3adf7212014-10-24 15:34:07 +08002303 }
Chia-I Wu6032b892014-10-17 14:47:18 +08002304
2305 /* 3DSTATE_VERTEX_BUFFERS */
2306 pos = cmd_batch_pointer(cmd, 5, &dw);
Chia-I Wu3adf7212014-10-24 15:34:07 +08002307
Chia-I Wu6032b892014-10-17 14:47:18 +08002308 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_BUFFERS) | (5 - 2);
Chia-I Wu3adf7212014-10-24 15:34:07 +08002309 dw[1] = vb_stride;
Chia-I Wu6032b892014-10-17 14:47:18 +08002310 if (cmd_gen(cmd) >= INTEL_GEN(7))
2311 dw[1] |= GEN7_VB_STATE_DW0_ADDR_MODIFIED;
2312
2313 cmd_reserve_reloc(cmd, 2);
Chia-I Wu3adf7212014-10-24 15:34:07 +08002314 cmd_batch_reloc_writer(cmd, pos + 2, INTEL_CMD_WRITER_STATE, vb_start);
2315 cmd_batch_reloc_writer(cmd, pos + 3, INTEL_CMD_WRITER_STATE, vb_end);
Chia-I Wu6032b892014-10-17 14:47:18 +08002316
2317 dw[4] = 0;
2318
2319 /* 3DSTATE_VERTEX_ELEMENTS */
2320 cmd_batch_pointer(cmd, 5, &dw);
2321 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VERTEX_ELEMENTS) | (5 - 2);
Chia-I Wu29e6f502014-11-24 14:27:29 +08002322 dw[1] = GEN6_VE_STATE_DW0_VALID;
Chia-I Wu6032b892014-10-17 14:47:18 +08002323 dw[2] = GEN6_VFCOMP_STORE_0 << GEN6_VE_STATE_DW1_COMP0__SHIFT | /* Reserved */
2324 GEN6_VFCOMP_STORE_0 << GEN6_VE_STATE_DW1_COMP1__SHIFT | /* Render Target Array Index */
2325 GEN6_VFCOMP_STORE_0 << GEN6_VE_STATE_DW1_COMP2__SHIFT | /* Viewport Index */
2326 GEN6_VFCOMP_STORE_0 << GEN6_VE_STATE_DW1_COMP3__SHIFT; /* Point Width */
2327 dw[3] = GEN6_VE_STATE_DW0_VALID |
Chia-I Wu3adf7212014-10-24 15:34:07 +08002328 ve_format << GEN6_VE_STATE_DW0_FORMAT__SHIFT;
Chia-I Wu6032b892014-10-17 14:47:18 +08002329 dw[4] = GEN6_VFCOMP_STORE_SRC << GEN6_VE_STATE_DW1_COMP0__SHIFT |
2330 GEN6_VFCOMP_STORE_SRC << GEN6_VE_STATE_DW1_COMP1__SHIFT |
Chia-I Wu3adf7212014-10-24 15:34:07 +08002331 ve_z_source << GEN6_VE_STATE_DW1_COMP2__SHIFT |
Chia-I Wu6032b892014-10-17 14:47:18 +08002332 GEN6_VFCOMP_STORE_1_FP << GEN6_VE_STATE_DW1_COMP3__SHIFT;
2333}
2334
Chia-I Wu29e6f502014-11-24 14:27:29 +08002335static uint32_t gen6_meta_vs_constants(struct intel_cmd *cmd)
Chia-I Wu6032b892014-10-17 14:47:18 +08002336{
Chia-I Wu3adf7212014-10-24 15:34:07 +08002337 const struct intel_cmd_meta *meta = cmd->bind.meta;
Chia-I Wu29e6f502014-11-24 14:27:29 +08002338 /* one GPR */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06002339 uint32_t consts[8];
2340 uint32_t const_count;
Chia-I Wu29e6f502014-11-24 14:27:29 +08002341
2342 CMD_ASSERT(cmd, 6, 7.5);
2343
2344 switch (meta->shader_id) {
Chia-I Wu0c87f472014-11-25 14:37:30 +08002345 case INTEL_DEV_META_VS_FILL_MEM:
2346 consts[0] = meta->dst.x;
2347 consts[1] = meta->clear_val[0];
2348 const_count = 2;
2349 break;
2350 case INTEL_DEV_META_VS_COPY_MEM:
2351 case INTEL_DEV_META_VS_COPY_MEM_UNALIGNED:
2352 consts[0] = meta->dst.x;
2353 consts[1] = meta->src.x;
2354 const_count = 2;
2355 break;
Chia-I Wu4d344e62014-12-20 21:06:04 +08002356 case INTEL_DEV_META_VS_COPY_R8_TO_MEM:
2357 case INTEL_DEV_META_VS_COPY_R16_TO_MEM:
2358 case INTEL_DEV_META_VS_COPY_R32_TO_MEM:
2359 case INTEL_DEV_META_VS_COPY_R32G32_TO_MEM:
2360 case INTEL_DEV_META_VS_COPY_R32G32B32A32_TO_MEM:
2361 consts[0] = meta->src.x;
2362 consts[1] = meta->src.y;
2363 consts[2] = meta->width;
2364 consts[3] = meta->dst.x;
2365 const_count = 4;
2366 break;
Chia-I Wu29e6f502014-11-24 14:27:29 +08002367 default:
2368 assert(!"unknown meta shader id");
2369 const_count = 0;
2370 break;
2371 }
2372
2373 /* this can be skipped but it makes state dumping prettier */
2374 memset(&consts[const_count], 0, sizeof(consts[0]) * (8 - const_count));
2375
2376 return cmd_state_write(cmd, INTEL_CMD_ITEM_BLOB, 32, 8, consts);
2377}
2378
2379static void gen6_meta_vs(struct intel_cmd *cmd)
2380{
2381 const struct intel_cmd_meta *meta = cmd->bind.meta;
2382 const struct intel_pipeline_shader *sh =
2383 intel_dev_get_meta_shader(cmd->dev, meta->shader_id);
2384 uint32_t offset, *dw;
2385
2386 CMD_ASSERT(cmd, 6, 7.5);
2387
2388 if (meta->mode != INTEL_CMD_META_VS_POINTS) {
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06002389 uint32_t cmd_len;
Chia-I Wu29e6f502014-11-24 14:27:29 +08002390
2391 /* 3DSTATE_CONSTANT_VS */
2392 cmd_len = (cmd_gen(cmd) >= INTEL_GEN(7)) ? 7 : 5;
2393 cmd_batch_pointer(cmd, cmd_len, &dw);
2394 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_VS) | (cmd_len - 2);
2395 memset(&dw[1], 0, sizeof(*dw) * (cmd_len - 1));
2396
2397 /* 3DSTATE_VS */
2398 cmd_batch_pointer(cmd, 6, &dw);
2399 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VS) | (6 - 2);
2400 memset(&dw[1], 0, sizeof(*dw) * (6 - 1));
2401
2402 return;
2403 }
2404
2405 assert(meta->dst.valid && sh->uses == INTEL_SHADER_USE_VID);
2406
2407 /* 3DSTATE_CONSTANT_VS */
2408 offset = gen6_meta_vs_constants(cmd);
2409 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
2410 cmd_batch_pointer(cmd, 7, &dw);
2411 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_VS) | (7 - 2);
2412 dw[1] = 1 << GEN7_PCB_ANY_DW1_PCB0_SIZE__SHIFT;
2413 dw[2] = 0;
2414 dw[3] = offset;
2415 dw[4] = 0;
2416 dw[5] = 0;
2417 dw[6] = 0;
2418 } else {
2419 cmd_batch_pointer(cmd, 5, &dw);
2420 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_VS) | (5 - 2) |
2421 GEN6_PCB_ANY_DW0_PCB0_VALID;
2422 dw[1] = offset;
2423 dw[2] = 0;
2424 dw[3] = 0;
2425 dw[4] = 0;
2426 }
2427
2428 /* 3DSTATE_VS */
2429 offset = emit_shader(cmd, sh);
2430 cmd_batch_pointer(cmd, 6, &dw);
2431 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_VS) | (6 - 2);
2432 dw[1] = offset;
2433 dw[2] = GEN6_THREADDISP_SPF |
2434 (sh->sampler_count + 3) / 4 << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
2435 sh->surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
Chia-I Wu784d3042014-12-19 14:30:04 +08002436 dw[3] = 0; /* scratch */
Chia-I Wu29e6f502014-11-24 14:27:29 +08002437 dw[4] = sh->urb_grf_start << GEN6_VS_DW4_URB_GRF_START__SHIFT |
2438 1 << GEN6_VS_DW4_URB_READ_LEN__SHIFT;
2439
2440 dw[5] = GEN6_VS_DW5_CACHE_DISABLE |
2441 GEN6_VS_DW5_VS_ENABLE;
2442 if (cmd_gen(cmd) >= INTEL_GEN(7.5))
Chia-I Wu3f4bd102014-12-19 13:14:42 +08002443 dw[5] |= (sh->max_threads - 1) << GEN75_VS_DW5_MAX_THREADS__SHIFT;
Chia-I Wu29e6f502014-11-24 14:27:29 +08002444 else
Chia-I Wu3f4bd102014-12-19 13:14:42 +08002445 dw[5] |= (sh->max_threads - 1) << GEN6_VS_DW5_MAX_THREADS__SHIFT;
Chia-I Wu784d3042014-12-19 14:30:04 +08002446
2447 assert(!sh->per_thread_scratch_size);
Chia-I Wu29e6f502014-11-24 14:27:29 +08002448}
2449
2450static void gen6_meta_disabled(struct intel_cmd *cmd)
2451{
Chia-I Wu6032b892014-10-17 14:47:18 +08002452 uint32_t *dw;
2453
2454 CMD_ASSERT(cmd, 6, 6);
2455
Chia-I Wu6032b892014-10-17 14:47:18 +08002456 /* 3DSTATE_CONSTANT_GS */
2457 cmd_batch_pointer(cmd, 5, &dw);
2458 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_GS) | (5 - 2);
2459 dw[1] = 0;
2460 dw[2] = 0;
2461 dw[3] = 0;
2462 dw[4] = 0;
2463
2464 /* 3DSTATE_GS */
2465 cmd_batch_pointer(cmd, 7, &dw);
2466 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (7 - 2);
2467 dw[1] = 0;
2468 dw[2] = 0;
2469 dw[3] = 0;
2470 dw[4] = 1 << GEN6_GS_DW4_URB_READ_LEN__SHIFT;
2471 dw[5] = GEN6_GS_DW5_STATISTICS;
2472 dw[6] = 0;
2473
Chia-I Wu6032b892014-10-17 14:47:18 +08002474 /* 3DSTATE_SF */
2475 cmd_batch_pointer(cmd, 20, &dw);
2476 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (20 - 2);
2477 dw[1] = 1 << GEN7_SBE_DW1_URB_READ_LEN__SHIFT;
2478 memset(&dw[2], 0, 18 * sizeof(*dw));
2479}
2480
2481static void gen7_meta_disabled(struct intel_cmd *cmd)
2482{
2483 uint32_t *dw;
2484
2485 CMD_ASSERT(cmd, 7, 7.5);
2486
Chia-I Wu6032b892014-10-17 14:47:18 +08002487 /* 3DSTATE_CONSTANT_HS */
2488 cmd_batch_pointer(cmd, 7, &dw);
2489 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_CONSTANT_HS) | (7 - 2);
2490 memset(&dw[1], 0, sizeof(*dw) * (7 - 1));
2491
2492 /* 3DSTATE_HS */
2493 cmd_batch_pointer(cmd, 7, &dw);
2494 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_HS) | (7 - 2);
2495 memset(&dw[1], 0, sizeof(*dw) * (7 - 1));
2496
2497 /* 3DSTATE_TE */
2498 cmd_batch_pointer(cmd, 4, &dw);
2499 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_TE) | (4 - 2);
2500 memset(&dw[1], 0, sizeof(*dw) * (4 - 1));
2501
2502 /* 3DSTATE_CONSTANT_DS */
2503 cmd_batch_pointer(cmd, 7, &dw);
2504 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_CONSTANT_DS) | (7 - 2);
2505 memset(&dw[1], 0, sizeof(*dw) * (7 - 1));
2506
2507 /* 3DSTATE_DS */
2508 cmd_batch_pointer(cmd, 6, &dw);
2509 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_DS) | (6 - 2);
2510 memset(&dw[1], 0, sizeof(*dw) * (6 - 1));
2511
2512 /* 3DSTATE_CONSTANT_GS */
2513 cmd_batch_pointer(cmd, 7, &dw);
2514 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_GS) | (7 - 2);
2515 memset(&dw[1], 0, sizeof(*dw) * (7 - 1));
2516
2517 /* 3DSTATE_GS */
2518 cmd_batch_pointer(cmd, 7, &dw);
2519 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_GS) | (7 - 2);
2520 memset(&dw[1], 0, sizeof(*dw) * (7 - 1));
2521
2522 /* 3DSTATE_STREAMOUT */
2523 cmd_batch_pointer(cmd, 3, &dw);
2524 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_STREAMOUT) | (3 - 2);
2525 memset(&dw[1], 0, sizeof(*dw) * (3 - 1));
2526
Chia-I Wu6032b892014-10-17 14:47:18 +08002527 /* 3DSTATE_SF */
2528 cmd_batch_pointer(cmd, 7, &dw);
2529 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SF) | (7 - 2);
2530 memset(&dw[1], 0, sizeof(*dw) * (7 - 1));
2531
2532 /* 3DSTATE_SBE */
2533 cmd_batch_pointer(cmd, 14, &dw);
2534 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_SBE) | (14 - 2);
2535 dw[1] = 1 << GEN7_SBE_DW1_URB_READ_LEN__SHIFT;
2536 memset(&dw[2], 0, sizeof(*dw) * (14 - 2));
Chia-I Wu29e6f502014-11-24 14:27:29 +08002537}
Chia-I Wu3adf7212014-10-24 15:34:07 +08002538
Chia-I Wu29e6f502014-11-24 14:27:29 +08002539static void gen6_meta_clip(struct intel_cmd *cmd)
2540{
2541 const struct intel_cmd_meta *meta = cmd->bind.meta;
2542 uint32_t *dw;
Chia-I Wu3adf7212014-10-24 15:34:07 +08002543
Chia-I Wu29e6f502014-11-24 14:27:29 +08002544 /* 3DSTATE_CLIP */
2545 cmd_batch_pointer(cmd, 4, &dw);
2546 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CLIP) | (4 - 2);
2547 dw[1] = 0;
2548 if (meta->mode == INTEL_CMD_META_VS_POINTS) {
2549 dw[2] = GEN6_CLIP_DW2_CLIP_ENABLE |
2550 GEN6_CLIP_DW2_CLIPMODE_REJECT_ALL;
2551 } else {
Chia-I Wu3adf7212014-10-24 15:34:07 +08002552 dw[2] = 0;
Chia-I Wu3adf7212014-10-24 15:34:07 +08002553 }
Chia-I Wu29e6f502014-11-24 14:27:29 +08002554 dw[3] = 0;
Chia-I Wu6032b892014-10-17 14:47:18 +08002555}
2556
2557static void gen6_meta_wm(struct intel_cmd *cmd)
2558{
2559 const struct intel_cmd_meta *meta = cmd->bind.meta;
2560 uint32_t *dw;
2561
2562 CMD_ASSERT(cmd, 6, 7.5);
2563
2564 cmd_wa_gen6_pre_multisample_depth_flush(cmd);
2565
2566 /* 3DSTATE_MULTISAMPLE */
2567 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
2568 cmd_batch_pointer(cmd, 4, &dw);
2569 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE) | (4 - 2);
2570 dw[1] = (meta->samples <= 1) ? GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1 :
2571 (meta->samples <= 4) ? GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4 :
2572 GEN7_MULTISAMPLE_DW1_NUMSAMPLES_8;
2573 dw[2] = 0;
2574 dw[3] = 0;
2575 } else {
2576 cmd_batch_pointer(cmd, 3, &dw);
2577 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_MULTISAMPLE) | (3 - 2);
2578 dw[1] = (meta->samples <= 1) ? GEN6_MULTISAMPLE_DW1_NUMSAMPLES_1 :
2579 GEN6_MULTISAMPLE_DW1_NUMSAMPLES_4;
2580 dw[2] = 0;
2581 }
2582
2583 /* 3DSTATE_SAMPLE_MASK */
2584 cmd_batch_pointer(cmd, 2, &dw);
2585 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_SAMPLE_MASK) | (2 - 2);
2586 dw[1] = (1 << meta->samples) - 1;
2587
2588 /* 3DSTATE_DRAWING_RECTANGLE */
2589 cmd_batch_pointer(cmd, 4, &dw);
2590 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_DRAWING_RECTANGLE) | (4 - 2);
Chia-I Wu7ee64472015-01-29 00:35:56 +08002591 if (meta->mode == INTEL_CMD_META_VS_POINTS) {
2592 /* unused */
2593 dw[1] = 0;
2594 dw[2] = 0;
2595 } else {
2596 dw[1] = meta->dst.y << 16 | meta->dst.x;
2597 dw[2] = (meta->dst.y + meta->height - 1) << 16 |
2598 (meta->dst.x + meta->width - 1);
2599 }
Chia-I Wu6032b892014-10-17 14:47:18 +08002600 dw[3] = 0;
2601}
2602
2603static uint32_t gen6_meta_ps_constants(struct intel_cmd *cmd)
2604{
2605 const struct intel_cmd_meta *meta = cmd->bind.meta;
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06002606 uint32_t offset_x, offset_y;
Chia-I Wu6032b892014-10-17 14:47:18 +08002607 /* one GPR */
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06002608 uint32_t consts[8];
2609 uint32_t const_count;
Chia-I Wu6032b892014-10-17 14:47:18 +08002610
2611 CMD_ASSERT(cmd, 6, 7.5);
2612
2613 /* underflow is fine here */
2614 offset_x = meta->src.x - meta->dst.x;
2615 offset_y = meta->src.y - meta->dst.y;
2616
2617 switch (meta->shader_id) {
2618 case INTEL_DEV_META_FS_COPY_MEM:
2619 case INTEL_DEV_META_FS_COPY_1D:
2620 case INTEL_DEV_META_FS_COPY_1D_ARRAY:
2621 case INTEL_DEV_META_FS_COPY_2D:
2622 case INTEL_DEV_META_FS_COPY_2D_ARRAY:
2623 case INTEL_DEV_META_FS_COPY_2D_MS:
2624 consts[0] = offset_x;
2625 consts[1] = offset_y;
2626 consts[2] = meta->src.layer;
2627 consts[3] = meta->src.lod;
2628 const_count = 4;
2629 break;
2630 case INTEL_DEV_META_FS_COPY_1D_TO_MEM:
2631 case INTEL_DEV_META_FS_COPY_1D_ARRAY_TO_MEM:
2632 case INTEL_DEV_META_FS_COPY_2D_TO_MEM:
2633 case INTEL_DEV_META_FS_COPY_2D_ARRAY_TO_MEM:
2634 case INTEL_DEV_META_FS_COPY_2D_MS_TO_MEM:
2635 consts[0] = offset_x;
2636 consts[1] = offset_y;
2637 consts[2] = meta->src.layer;
2638 consts[3] = meta->src.lod;
2639 consts[4] = meta->src.x;
2640 consts[5] = meta->width;
2641 const_count = 6;
2642 break;
2643 case INTEL_DEV_META_FS_COPY_MEM_TO_IMG:
2644 consts[0] = offset_x;
2645 consts[1] = offset_y;
2646 consts[2] = meta->width;
2647 const_count = 3;
2648 break;
2649 case INTEL_DEV_META_FS_CLEAR_COLOR:
2650 consts[0] = meta->clear_val[0];
2651 consts[1] = meta->clear_val[1];
2652 consts[2] = meta->clear_val[2];
2653 consts[3] = meta->clear_val[3];
2654 const_count = 4;
2655 break;
2656 case INTEL_DEV_META_FS_CLEAR_DEPTH:
2657 consts[0] = meta->clear_val[0];
Chia-I Wu429a0aa2014-10-24 11:57:51 +08002658 consts[1] = meta->clear_val[1];
2659 const_count = 2;
Chia-I Wu6032b892014-10-17 14:47:18 +08002660 break;
2661 case INTEL_DEV_META_FS_RESOLVE_2X:
2662 case INTEL_DEV_META_FS_RESOLVE_4X:
2663 case INTEL_DEV_META_FS_RESOLVE_8X:
2664 case INTEL_DEV_META_FS_RESOLVE_16X:
2665 consts[0] = offset_x;
2666 consts[1] = offset_y;
2667 const_count = 2;
2668 break;
2669 default:
2670 assert(!"unknown meta shader id");
2671 const_count = 0;
2672 break;
2673 }
2674
2675 /* this can be skipped but it makes state dumping prettier */
2676 memset(&consts[const_count], 0, sizeof(consts[0]) * (8 - const_count));
2677
2678 return cmd_state_write(cmd, INTEL_CMD_ITEM_BLOB, 32, 8, consts);
2679}
2680
2681static void gen6_meta_ps(struct intel_cmd *cmd)
2682{
2683 const struct intel_cmd_meta *meta = cmd->bind.meta;
2684 const struct intel_pipeline_shader *sh =
2685 intel_dev_get_meta_shader(cmd->dev, meta->shader_id);
2686 uint32_t offset, *dw;
2687
2688 CMD_ASSERT(cmd, 6, 6);
2689
Chia-I Wu29e6f502014-11-24 14:27:29 +08002690 if (meta->mode != INTEL_CMD_META_FS_RECT) {
2691 /* 3DSTATE_CONSTANT_PS */
2692 cmd_batch_pointer(cmd, 5, &dw);
2693 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_PS) | (5 - 2);
2694 dw[1] = 0;
2695 dw[2] = 0;
2696 dw[3] = 0;
2697 dw[4] = 0;
2698
2699 /* 3DSTATE_WM */
2700 cmd_batch_pointer(cmd, 9, &dw);
2701 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (9 - 2);
2702 dw[1] = 0;
2703 dw[2] = 0;
2704 dw[3] = 0;
2705 dw[4] = 0;
Chia-I Wu3f4bd102014-12-19 13:14:42 +08002706 dw[5] = (sh->max_threads - 1) << GEN6_WM_DW5_MAX_THREADS__SHIFT;
Chia-I Wu29e6f502014-11-24 14:27:29 +08002707 dw[6] = 0;
2708 dw[7] = 0;
2709 dw[8] = 0;
2710
Chia-I Wu3adf7212014-10-24 15:34:07 +08002711 return;
Chia-I Wu29e6f502014-11-24 14:27:29 +08002712 }
2713
Chia-I Wu3adf7212014-10-24 15:34:07 +08002714 /* a normal color write */
2715 assert(meta->dst.valid && !sh->uses);
2716
Chia-I Wu6032b892014-10-17 14:47:18 +08002717 /* 3DSTATE_CONSTANT_PS */
2718 offset = gen6_meta_ps_constants(cmd);
2719 cmd_batch_pointer(cmd, 5, &dw);
2720 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_PS) | (5 - 2) |
2721 GEN6_PCB_ANY_DW0_PCB0_VALID;
2722 dw[1] = offset;
2723 dw[2] = 0;
2724 dw[3] = 0;
2725 dw[4] = 0;
2726
2727 /* 3DSTATE_WM */
2728 offset = emit_shader(cmd, sh);
2729 cmd_batch_pointer(cmd, 9, &dw);
2730 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (9 - 2);
2731 dw[1] = offset;
2732 dw[2] = (sh->sampler_count + 3) / 4 << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
2733 sh->surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
Chia-I Wu784d3042014-12-19 14:30:04 +08002734 dw[3] = 0; /* scratch */
Chia-I Wu6032b892014-10-17 14:47:18 +08002735 dw[4] = sh->urb_grf_start << GEN6_WM_DW4_URB_GRF_START0__SHIFT;
Chia-I Wu3f4bd102014-12-19 13:14:42 +08002736 dw[5] = (sh->max_threads - 1) << GEN6_WM_DW5_MAX_THREADS__SHIFT |
Chia-I Wu6032b892014-10-17 14:47:18 +08002737 GEN6_WM_DW5_PS_ENABLE |
Chia-I Wu005c47c2014-10-22 13:49:13 +08002738 GEN6_WM_DW5_16_PIXEL_DISPATCH;
2739
Chia-I Wu6032b892014-10-17 14:47:18 +08002740 dw[6] = sh->in_count << GEN6_WM_DW6_SF_ATTR_COUNT__SHIFT |
2741 GEN6_WM_DW6_POSOFFSET_NONE |
2742 GEN6_WM_DW6_ZW_INTERP_PIXEL |
2743 sh->barycentric_interps << GEN6_WM_DW6_BARYCENTRIC_INTERP__SHIFT |
2744 GEN6_WM_DW6_POINT_RASTRULE_UPPER_RIGHT;
2745 if (meta->samples > 1) {
2746 dw[6] |= GEN6_WM_DW6_MSRASTMODE_ON_PATTERN |
2747 GEN6_WM_DW6_MSDISPMODE_PERPIXEL;
2748 } else {
2749 dw[6] |= GEN6_WM_DW6_MSRASTMODE_OFF_PIXEL |
2750 GEN6_WM_DW6_MSDISPMODE_PERSAMPLE;
2751 }
2752 dw[7] = 0;
2753 dw[8] = 0;
Chia-I Wu784d3042014-12-19 14:30:04 +08002754
2755 assert(!sh->per_thread_scratch_size);
Chia-I Wu6032b892014-10-17 14:47:18 +08002756}
2757
2758static void gen7_meta_ps(struct intel_cmd *cmd)
2759{
2760 const struct intel_cmd_meta *meta = cmd->bind.meta;
2761 const struct intel_pipeline_shader *sh =
2762 intel_dev_get_meta_shader(cmd->dev, meta->shader_id);
2763 uint32_t offset, *dw;
2764
2765 CMD_ASSERT(cmd, 7, 7.5);
2766
Chia-I Wu29e6f502014-11-24 14:27:29 +08002767 if (meta->mode != INTEL_CMD_META_FS_RECT) {
2768 /* 3DSTATE_WM */
2769 cmd_batch_pointer(cmd, 3, &dw);
2770 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (3 - 2);
2771 memset(&dw[1], 0, sizeof(*dw) * (3 - 1));
2772
2773 /* 3DSTATE_CONSTANT_GS */
2774 cmd_batch_pointer(cmd, 7, &dw);
2775 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_PS) | (7 - 2);
2776 memset(&dw[1], 0, sizeof(*dw) * (7 - 1));
2777
2778 /* 3DSTATE_PS */
2779 cmd_batch_pointer(cmd, 8, &dw);
2780 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PS) | (8 - 2);
2781 dw[1] = 0;
2782 dw[2] = 0;
2783 dw[3] = 0;
2784 dw[4] = GEN7_PS_DW4_8_PIXEL_DISPATCH | /* required to avoid hangs */
Chia-I Wu3f4bd102014-12-19 13:14:42 +08002785 (sh->max_threads - 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT;
Chia-I Wu29e6f502014-11-24 14:27:29 +08002786 dw[5] = 0;
2787 dw[6] = 0;
2788 dw[7] = 0;
2789
Chia-I Wu3adf7212014-10-24 15:34:07 +08002790 return;
Chia-I Wu29e6f502014-11-24 14:27:29 +08002791 }
2792
Chia-I Wu3adf7212014-10-24 15:34:07 +08002793 /* a normal color write */
2794 assert(meta->dst.valid && !sh->uses);
2795
Chia-I Wu6032b892014-10-17 14:47:18 +08002796 /* 3DSTATE_WM */
2797 cmd_batch_pointer(cmd, 3, &dw);
2798 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_WM) | (3 - 2);
2799 dw[1] = GEN7_WM_DW1_PS_ENABLE |
2800 GEN7_WM_DW1_ZW_INTERP_PIXEL |
2801 sh->barycentric_interps << GEN7_WM_DW1_BARYCENTRIC_INTERP__SHIFT |
2802 GEN7_WM_DW1_POINT_RASTRULE_UPPER_RIGHT;
2803 dw[2] = 0;
2804
2805 /* 3DSTATE_CONSTANT_PS */
2806 offset = gen6_meta_ps_constants(cmd);
2807 cmd_batch_pointer(cmd, 7, &dw);
2808 dw[0] = GEN6_RENDER_CMD(3D, 3DSTATE_CONSTANT_PS) | (7 - 2);
2809 dw[1] = 1 << GEN7_PCB_ANY_DW1_PCB0_SIZE__SHIFT;
2810 dw[2] = 0;
2811 dw[3] = offset;
2812 dw[4] = 0;
2813 dw[5] = 0;
2814 dw[6] = 0;
2815
2816 /* 3DSTATE_PS */
2817 offset = emit_shader(cmd, sh);
2818 cmd_batch_pointer(cmd, 8, &dw);
2819 dw[0] = GEN7_RENDER_CMD(3D, 3DSTATE_PS) | (8 - 2);
2820 dw[1] = offset;
2821 dw[2] = (sh->sampler_count + 3) / 4 << GEN6_THREADDISP_SAMPLER_COUNT__SHIFT |
2822 sh->surface_count << GEN6_THREADDISP_BINDING_TABLE_SIZE__SHIFT;
Chia-I Wu784d3042014-12-19 14:30:04 +08002823 dw[3] = 0; /* scratch */
Chia-I Wu6032b892014-10-17 14:47:18 +08002824
2825 dw[4] = GEN7_PS_DW4_PUSH_CONSTANT_ENABLE |
2826 GEN7_PS_DW4_POSOFFSET_NONE |
Chia-I Wu05990612014-11-25 11:36:35 +08002827 GEN7_PS_DW4_16_PIXEL_DISPATCH;
2828
2829 if (cmd_gen(cmd) >= INTEL_GEN(7.5)) {
Chia-I Wu3f4bd102014-12-19 13:14:42 +08002830 dw[4] |= (sh->max_threads - 1) << GEN75_PS_DW4_MAX_THREADS__SHIFT;
Chia-I Wu6032b892014-10-17 14:47:18 +08002831 dw[4] |= ((1 << meta->samples) - 1) << GEN75_PS_DW4_SAMPLE_MASK__SHIFT;
Chia-I Wu05990612014-11-25 11:36:35 +08002832 } else {
Chia-I Wu3f4bd102014-12-19 13:14:42 +08002833 dw[4] |= (sh->max_threads - 1) << GEN7_PS_DW4_MAX_THREADS__SHIFT;
Chia-I Wu05990612014-11-25 11:36:35 +08002834 }
Chia-I Wu6032b892014-10-17 14:47:18 +08002835
2836 dw[5] = sh->urb_grf_start << GEN7_PS_DW5_URB_GRF_START0__SHIFT;
2837 dw[6] = 0;
2838 dw[7] = 0;
Chia-I Wu784d3042014-12-19 14:30:04 +08002839
2840 assert(!sh->per_thread_scratch_size);
Chia-I Wu6032b892014-10-17 14:47:18 +08002841}
2842
2843static void gen6_meta_depth_buffer(struct intel_cmd *cmd)
2844{
2845 const struct intel_cmd_meta *meta = cmd->bind.meta;
Chia-I Wu429a0aa2014-10-24 11:57:51 +08002846 const struct intel_ds_view *ds = meta->ds.view;
Chia-I Wu6032b892014-10-17 14:47:18 +08002847
2848 CMD_ASSERT(cmd, 6, 7.5);
2849
Chia-I Wube2f0ad2014-10-24 09:49:50 +08002850 if (!ds) {
2851 /* all zeros */
2852 static const struct intel_ds_view null_ds;
2853 ds = &null_ds;
Chia-I Wu6032b892014-10-17 14:47:18 +08002854 }
Chia-I Wube2f0ad2014-10-24 09:49:50 +08002855
2856 cmd_wa_gen6_pre_ds_flush(cmd);
2857 gen6_3DSTATE_DEPTH_BUFFER(cmd, ds);
2858 gen6_3DSTATE_STENCIL_BUFFER(cmd, ds);
2859 gen6_3DSTATE_HIER_DEPTH_BUFFER(cmd, ds);
2860
2861 if (cmd_gen(cmd) >= INTEL_GEN(7))
2862 gen7_3DSTATE_CLEAR_PARAMS(cmd, 0);
2863 else
2864 gen6_3DSTATE_CLEAR_PARAMS(cmd, 0);
Chia-I Wu6032b892014-10-17 14:47:18 +08002865}
2866
Chia-I Wuc29afdd2014-10-14 13:22:31 +08002867static void cmd_bind_graphics_pipeline(struct intel_cmd *cmd,
2868 const struct intel_pipeline *pipeline)
2869{
2870 cmd->bind.pipeline.graphics = pipeline;
2871}
2872
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002873static void cmd_bind_compute_pipeline(struct intel_cmd *cmd,
2874 const struct intel_pipeline *pipeline)
2875{
2876 cmd->bind.pipeline.compute = pipeline;
2877}
2878
2879static void cmd_bind_graphics_delta(struct intel_cmd *cmd,
2880 const struct intel_pipeline_delta *delta)
2881{
2882 cmd->bind.pipeline.graphics_delta = delta;
2883}
2884
2885static void cmd_bind_compute_delta(struct intel_cmd *cmd,
2886 const struct intel_pipeline_delta *delta)
2887{
2888 cmd->bind.pipeline.compute_delta = delta;
2889}
2890
2891static void cmd_bind_graphics_dset(struct intel_cmd *cmd,
Chia-I Wuf8385062015-01-04 16:27:24 +08002892 const struct intel_desc_set *dset,
2893 const uint32_t *dynamic_offsets)
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002894{
Chia-I Wuf8385062015-01-04 16:27:24 +08002895 const uint32_t size = sizeof(*dynamic_offsets) *
2896 dset->layout->dynamic_desc_count;
2897
2898 if (size > cmd->bind.dset.graphics_dynamic_offset_size) {
2899 if (cmd->bind.dset.graphics_dynamic_offsets)
2900 icd_free(cmd->bind.dset.graphics_dynamic_offsets);
2901
2902 cmd->bind.dset.graphics_dynamic_offsets = icd_alloc(size,
2903 4, XGL_SYSTEM_ALLOC_INTERNAL);
2904 if (!cmd->bind.dset.graphics_dynamic_offsets) {
Chia-I Wu4e5577a2015-02-10 11:04:44 -07002905 cmd_fail(cmd, XGL_ERROR_OUT_OF_MEMORY);
Chia-I Wuf8385062015-01-04 16:27:24 +08002906 return;
2907 }
2908
2909 cmd->bind.dset.graphics_dynamic_offset_size = size;
2910 }
2911
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002912 cmd->bind.dset.graphics = dset;
Chia-I Wuf8385062015-01-04 16:27:24 +08002913 memcpy(cmd->bind.dset.graphics_dynamic_offsets, dynamic_offsets, size);
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002914}
2915
2916static void cmd_bind_compute_dset(struct intel_cmd *cmd,
Chia-I Wuf8385062015-01-04 16:27:24 +08002917 const struct intel_desc_set *dset,
2918 const uint32_t *dynamic_offsets)
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002919{
Chia-I Wuf8385062015-01-04 16:27:24 +08002920 const uint32_t size = sizeof(*dynamic_offsets) *
2921 dset->layout->dynamic_desc_count;
2922
2923 if (size > cmd->bind.dset.compute_dynamic_offset_size) {
2924 if (cmd->bind.dset.compute_dynamic_offsets)
2925 icd_free(cmd->bind.dset.compute_dynamic_offsets);
2926
2927 cmd->bind.dset.compute_dynamic_offsets = icd_alloc(size,
2928 4, XGL_SYSTEM_ALLOC_INTERNAL);
2929 if (!cmd->bind.dset.compute_dynamic_offsets) {
Chia-I Wu4e5577a2015-02-10 11:04:44 -07002930 cmd_fail(cmd, XGL_ERROR_OUT_OF_MEMORY);
Chia-I Wuf8385062015-01-04 16:27:24 +08002931 return;
2932 }
2933
2934 cmd->bind.dset.compute_dynamic_offset_size = size;
2935 }
2936
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002937 cmd->bind.dset.compute = dset;
Chia-I Wuf8385062015-01-04 16:27:24 +08002938 memcpy(cmd->bind.dset.compute_dynamic_offsets, dynamic_offsets, size);
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002939}
2940
Chia-I Wu3b04af52014-11-08 10:48:20 +08002941static void cmd_bind_vertex_data(struct intel_cmd *cmd,
Chia-I Wu714df452015-01-01 07:55:04 +08002942 const struct intel_buf *buf,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06002943 XGL_GPU_SIZE offset, uint32_t binding)
Chia-I Wu3b04af52014-11-08 10:48:20 +08002944{
Chia-I Wu714df452015-01-01 07:55:04 +08002945 if (binding >= ARRAY_SIZE(cmd->bind.vertex.buf)) {
Chia-I Wu4e5577a2015-02-10 11:04:44 -07002946 cmd_fail(cmd, XGL_ERROR_UNKNOWN);
Chia-I Wu3b04af52014-11-08 10:48:20 +08002947 return;
2948 }
2949
Chia-I Wu714df452015-01-01 07:55:04 +08002950 cmd->bind.vertex.buf[binding] = buf;
Chia-I Wu3b04af52014-11-08 10:48:20 +08002951 cmd->bind.vertex.offset[binding] = offset;
2952}
2953
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002954static void cmd_bind_index_data(struct intel_cmd *cmd,
Chia-I Wu714df452015-01-01 07:55:04 +08002955 const struct intel_buf *buf,
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002956 XGL_GPU_SIZE offset, XGL_INDEX_TYPE type)
2957{
Chia-I Wu714df452015-01-01 07:55:04 +08002958 cmd->bind.index.buf = buf;
Chia-I Wuc29afdd2014-10-14 13:22:31 +08002959 cmd->bind.index.offset = offset;
2960 cmd->bind.index.type = type;
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002961}
2962
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002963static void cmd_bind_viewport_state(struct intel_cmd *cmd,
Tony Barbourfa6cac72015-01-16 14:27:35 -07002964 const struct intel_dynamic_vp *state)
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002965{
2966 cmd->bind.state.viewport = state;
2967}
2968
2969static void cmd_bind_raster_state(struct intel_cmd *cmd,
Tony Barbourfa6cac72015-01-16 14:27:35 -07002970 const struct intel_dynamic_rs *state)
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002971{
2972 cmd->bind.state.raster = state;
2973}
2974
2975static void cmd_bind_ds_state(struct intel_cmd *cmd,
Tony Barbourfa6cac72015-01-16 14:27:35 -07002976 const struct intel_dynamic_ds *state)
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002977{
2978 cmd->bind.state.ds = state;
2979}
2980
2981static void cmd_bind_blend_state(struct intel_cmd *cmd,
Tony Barbourfa6cac72015-01-16 14:27:35 -07002982 const struct intel_dynamic_cb *state)
Chia-I Wu9f1722c2014-08-25 10:17:58 +08002983{
2984 cmd->bind.state.blend = state;
2985}
2986
Chia-I Wuf98dd882015-02-10 04:17:47 +08002987static uint32_t cmd_get_max_surface_write(const struct intel_cmd *cmd)
2988{
2989 const struct intel_pipeline *pipeline = cmd->bind.pipeline.graphics;
2990 struct intel_pipeline_rmap *rmaps[5] = {
2991 pipeline->vs.rmap,
2992 pipeline->tcs.rmap,
2993 pipeline->tes.rmap,
2994 pipeline->gs.rmap,
2995 pipeline->fs.rmap,
2996 };
2997 uint32_t max_write;
2998 int i;
2999
3000 STATIC_ASSERT(GEN6_ALIGNMENT_SURFACE_STATE >= GEN6_SURFACE_STATE__SIZE);
3001 STATIC_ASSERT(GEN6_ALIGNMENT_SURFACE_STATE >=
3002 GEN6_ALIGNMENT_BINDING_TABLE_STATE);
3003
3004 /* pad first */
3005 max_write = GEN6_ALIGNMENT_SURFACE_STATE;
3006
3007 for (i = 0; i < ARRAY_SIZE(rmaps); i++) {
3008 const struct intel_pipeline_rmap *rmap = rmaps[i];
3009 const uint32_t surface_count = (rmap) ?
3010 rmap->rt_count + rmap->texture_resource_count +
3011 rmap->resource_count + rmap->uav_count : 0;
3012
3013 if (surface_count) {
3014 /* SURFACE_STATEs */
3015 max_write += GEN6_ALIGNMENT_SURFACE_STATE * surface_count;
3016
3017 /* BINDING_TABLE_STATE */
3018 max_write += u_align(sizeof(uint32_t) * surface_count,
3019 GEN6_ALIGNMENT_SURFACE_STATE);
3020 }
3021 }
3022
3023 return max_write;
3024}
3025
3026static void cmd_adjust_state_base_address(struct intel_cmd *cmd)
3027{
3028 struct intel_cmd_writer *writer = &cmd->writers[INTEL_CMD_WRITER_SURFACE];
3029 const uint32_t cur_surface_offset = writer->used - writer->sba_offset;
3030 uint32_t max_surface_write;
3031
3032 /* enough for src and dst SURFACE_STATEs plus BINDING_TABLE_STATE */
3033 if (cmd->bind.meta)
3034 max_surface_write = 64 * sizeof(uint32_t);
3035 else
3036 max_surface_write = cmd_get_max_surface_write(cmd);
3037
3038 /* there is a 64KB limit on BINDING_TABLE_STATEs */
3039 if (cur_surface_offset + max_surface_write > 64 * 1024) {
3040 /* SBA expects page-aligned addresses */
3041 writer->sba_offset = writer->used & ~0xfff;
3042
3043 assert((writer->used & 0xfff) + max_surface_write <= 64 * 1024);
3044
3045 cmd_batch_state_base_address(cmd);
3046 }
3047}
3048
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003049static void cmd_draw(struct intel_cmd *cmd,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003050 uint32_t vertex_start,
3051 uint32_t vertex_count,
3052 uint32_t instance_start,
3053 uint32_t instance_count,
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003054 bool indexed,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003055 uint32_t vertex_base)
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003056{
3057 const struct intel_pipeline *p = cmd->bind.pipeline.graphics;
Chia-I Wu08cd6e92015-02-11 13:44:50 -07003058 const uint32_t surface_writer_used U_ASSERT_ONLY =
Chia-I Wuf98dd882015-02-10 04:17:47 +08003059 cmd->writers[INTEL_CMD_WRITER_SURFACE].used;
3060
3061 cmd_adjust_state_base_address(cmd);
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003062
3063 emit_bounded_states(cmd);
3064
Chia-I Wuf98dd882015-02-10 04:17:47 +08003065 /* sanity check on cmd_get_max_surface_write() */
3066 assert(cmd->writers[INTEL_CMD_WRITER_SURFACE].used -
3067 surface_writer_used <= cmd_get_max_surface_write(cmd));
3068
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003069 if (indexed) {
3070 if (p->primitive_restart && !gen6_can_primitive_restart(cmd))
Chia-I Wu4e5577a2015-02-10 11:04:44 -07003071 cmd_fail(cmd, XGL_ERROR_UNKNOWN);
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003072
3073 if (cmd_gen(cmd) >= INTEL_GEN(7.5)) {
3074 gen75_3DSTATE_VF(cmd, p->primitive_restart,
3075 p->primitive_restart_index);
Chia-I Wu714df452015-01-01 07:55:04 +08003076 gen6_3DSTATE_INDEX_BUFFER(cmd, cmd->bind.index.buf,
Chia-I Wuc29afdd2014-10-14 13:22:31 +08003077 cmd->bind.index.offset, cmd->bind.index.type,
3078 false);
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003079 } else {
Chia-I Wu714df452015-01-01 07:55:04 +08003080 gen6_3DSTATE_INDEX_BUFFER(cmd, cmd->bind.index.buf,
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003081 cmd->bind.index.offset, cmd->bind.index.type,
3082 p->primitive_restart);
3083 }
3084 } else {
3085 assert(!vertex_base);
3086 }
3087
3088 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
3089 gen7_3DPRIMITIVE(cmd, p->prim_type, indexed, vertex_count,
3090 vertex_start, instance_count, instance_start, vertex_base);
3091 } else {
3092 gen6_3DPRIMITIVE(cmd, p->prim_type, indexed, vertex_count,
3093 vertex_start, instance_count, instance_start, vertex_base);
3094 }
Chia-I Wu48c283d2014-08-25 23:13:46 +08003095
Chia-I Wu707a29e2014-08-27 12:51:47 +08003096 cmd->bind.draw_count++;
Chia-I Wu48c283d2014-08-25 23:13:46 +08003097 /* need to re-emit all workarounds */
3098 cmd->bind.wa_flags = 0;
Chia-I Wubeb07aa2014-11-22 02:58:40 +08003099
3100 if (intel_debug & INTEL_DEBUG_NOCACHE)
3101 cmd_batch_flush_all(cmd);
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003102}
3103
Chia-I Wuc14d1562014-10-17 09:49:22 +08003104void cmd_draw_meta(struct intel_cmd *cmd, const struct intel_cmd_meta *meta)
3105{
Chia-I Wu6032b892014-10-17 14:47:18 +08003106 cmd->bind.meta = meta;
3107
Chia-I Wuf98dd882015-02-10 04:17:47 +08003108 cmd_adjust_state_base_address(cmd);
3109
Chia-I Wu6032b892014-10-17 14:47:18 +08003110 cmd_wa_gen6_pre_depth_stall_write(cmd);
Chia-I Wub4077f92014-10-28 11:19:14 +08003111 cmd_wa_gen6_pre_command_scoreboard_stall(cmd);
Chia-I Wu6032b892014-10-17 14:47:18 +08003112
3113 gen6_meta_dynamic_states(cmd);
3114 gen6_meta_surface_states(cmd);
3115
3116 if (cmd_gen(cmd) >= INTEL_GEN(7)) {
3117 gen7_meta_urb(cmd);
3118 gen6_meta_vf(cmd);
Chia-I Wu29e6f502014-11-24 14:27:29 +08003119 gen6_meta_vs(cmd);
Chia-I Wu6032b892014-10-17 14:47:18 +08003120 gen7_meta_disabled(cmd);
Chia-I Wu29e6f502014-11-24 14:27:29 +08003121 gen6_meta_clip(cmd);
Chia-I Wu6032b892014-10-17 14:47:18 +08003122 gen6_meta_wm(cmd);
3123 gen7_meta_ps(cmd);
3124 gen6_meta_depth_buffer(cmd);
3125
3126 cmd_wa_gen7_post_command_cs_stall(cmd);
3127 cmd_wa_gen7_post_command_depth_stall(cmd);
3128
Chia-I Wu29e6f502014-11-24 14:27:29 +08003129 if (meta->mode == INTEL_CMD_META_VS_POINTS) {
3130 gen7_3DPRIMITIVE(cmd, GEN6_3DPRIM_POINTLIST, false,
Chia-I Wu4d344e62014-12-20 21:06:04 +08003131 meta->width * meta->height, 0, 1, 0, 0);
Chia-I Wu29e6f502014-11-24 14:27:29 +08003132 } else {
3133 gen7_3DPRIMITIVE(cmd, GEN6_3DPRIM_RECTLIST, false, 3, 0, 1, 0, 0);
3134 }
Chia-I Wu6032b892014-10-17 14:47:18 +08003135 } else {
3136 gen6_meta_urb(cmd);
3137 gen6_meta_vf(cmd);
Chia-I Wu29e6f502014-11-24 14:27:29 +08003138 gen6_meta_vs(cmd);
Chia-I Wu6032b892014-10-17 14:47:18 +08003139 gen6_meta_disabled(cmd);
Chia-I Wu29e6f502014-11-24 14:27:29 +08003140 gen6_meta_clip(cmd);
Chia-I Wu6032b892014-10-17 14:47:18 +08003141 gen6_meta_wm(cmd);
3142 gen6_meta_ps(cmd);
3143 gen6_meta_depth_buffer(cmd);
3144
Chia-I Wu29e6f502014-11-24 14:27:29 +08003145 if (meta->mode == INTEL_CMD_META_VS_POINTS) {
3146 gen6_3DPRIMITIVE(cmd, GEN6_3DPRIM_POINTLIST, false,
Chia-I Wu4d344e62014-12-20 21:06:04 +08003147 meta->width * meta->height, 0, 1, 0, 0);
Chia-I Wu29e6f502014-11-24 14:27:29 +08003148 } else {
3149 gen6_3DPRIMITIVE(cmd, GEN6_3DPRIM_RECTLIST, false, 3, 0, 1, 0, 0);
3150 }
Chia-I Wu6032b892014-10-17 14:47:18 +08003151 }
3152
3153 cmd->bind.draw_count++;
3154 /* need to re-emit all workarounds */
3155 cmd->bind.wa_flags = 0;
3156
3157 cmd->bind.meta = NULL;
Chia-I Wubeb07aa2014-11-22 02:58:40 +08003158
3159 if (intel_debug & INTEL_DEBUG_NOCACHE)
3160 cmd_batch_flush_all(cmd);
Chia-I Wuc14d1562014-10-17 09:49:22 +08003161}
3162
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003163ICD_EXPORT void XGLAPI xglCmdBindPipeline(
Chia-I Wub2755562014-08-20 13:38:52 +08003164 XGL_CMD_BUFFER cmdBuffer,
3165 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
3166 XGL_PIPELINE pipeline)
3167{
3168 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
3169
3170 switch (pipelineBindPoint) {
3171 case XGL_PIPELINE_BIND_POINT_COMPUTE:
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003172 cmd_bind_compute_pipeline(cmd, intel_pipeline(pipeline));
Chia-I Wub2755562014-08-20 13:38:52 +08003173 break;
3174 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003175 cmd_bind_graphics_pipeline(cmd, intel_pipeline(pipeline));
Chia-I Wub2755562014-08-20 13:38:52 +08003176 break;
3177 default:
Chia-I Wu4e5577a2015-02-10 11:04:44 -07003178 cmd_fail(cmd, XGL_ERROR_INVALID_VALUE);
Chia-I Wub2755562014-08-20 13:38:52 +08003179 break;
3180 }
3181}
3182
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003183ICD_EXPORT void XGLAPI xglCmdBindPipelineDelta(
Chia-I Wub2755562014-08-20 13:38:52 +08003184 XGL_CMD_BUFFER cmdBuffer,
3185 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
3186 XGL_PIPELINE_DELTA delta)
3187{
3188 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
3189
3190 switch (pipelineBindPoint) {
3191 case XGL_PIPELINE_BIND_POINT_COMPUTE:
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003192 cmd_bind_compute_delta(cmd, delta);
Chia-I Wub2755562014-08-20 13:38:52 +08003193 break;
3194 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003195 cmd_bind_graphics_delta(cmd, delta);
Chia-I Wub2755562014-08-20 13:38:52 +08003196 break;
3197 default:
Chia-I Wu4e5577a2015-02-10 11:04:44 -07003198 cmd_fail(cmd, XGL_ERROR_INVALID_VALUE);
Chia-I Wub2755562014-08-20 13:38:52 +08003199 break;
3200 }
3201}
3202
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003203ICD_EXPORT void XGLAPI xglCmdBindDynamicStateObject(
Chia-I Wub2755562014-08-20 13:38:52 +08003204 XGL_CMD_BUFFER cmdBuffer,
3205 XGL_STATE_BIND_POINT stateBindPoint,
Tony Barbourfa6cac72015-01-16 14:27:35 -07003206 XGL_DYNAMIC_STATE_OBJECT state)
Chia-I Wub2755562014-08-20 13:38:52 +08003207{
3208 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
3209
3210 switch (stateBindPoint) {
3211 case XGL_STATE_BIND_VIEWPORT:
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003212 cmd_bind_viewport_state(cmd,
Tony Barbourfa6cac72015-01-16 14:27:35 -07003213 intel_dynamic_vp((XGL_DYNAMIC_VP_STATE_OBJECT) state));
Chia-I Wub2755562014-08-20 13:38:52 +08003214 break;
3215 case XGL_STATE_BIND_RASTER:
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003216 cmd_bind_raster_state(cmd,
Tony Barbourfa6cac72015-01-16 14:27:35 -07003217 intel_dynamic_rs((XGL_DYNAMIC_RS_STATE_OBJECT) state));
Chia-I Wub2755562014-08-20 13:38:52 +08003218 break;
3219 case XGL_STATE_BIND_DEPTH_STENCIL:
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003220 cmd_bind_ds_state(cmd,
Tony Barbourfa6cac72015-01-16 14:27:35 -07003221 intel_dynamic_ds((XGL_DYNAMIC_DS_STATE_OBJECT) state));
Chia-I Wub2755562014-08-20 13:38:52 +08003222 break;
3223 case XGL_STATE_BIND_COLOR_BLEND:
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003224 cmd_bind_blend_state(cmd,
Tony Barbourfa6cac72015-01-16 14:27:35 -07003225 intel_dynamic_cb((XGL_DYNAMIC_CB_STATE_OBJECT) state));
Chia-I Wub2755562014-08-20 13:38:52 +08003226 break;
3227 default:
Chia-I Wu4e5577a2015-02-10 11:04:44 -07003228 cmd_fail(cmd, XGL_ERROR_INVALID_VALUE);
Chia-I Wub2755562014-08-20 13:38:52 +08003229 break;
3230 }
3231}
3232
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003233ICD_EXPORT void XGLAPI xglCmdBindDescriptorSet(
Chia-I Wub2755562014-08-20 13:38:52 +08003234 XGL_CMD_BUFFER cmdBuffer,
3235 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
Chia-I Wub2755562014-08-20 13:38:52 +08003236 XGL_DESCRIPTOR_SET descriptorSet,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003237 const uint32_t* pUserData)
Chia-I Wub2755562014-08-20 13:38:52 +08003238{
3239 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wuf8385062015-01-04 16:27:24 +08003240 struct intel_desc_set *dset = intel_desc_set(descriptorSet);
Chia-I Wub2755562014-08-20 13:38:52 +08003241
3242 switch (pipelineBindPoint) {
3243 case XGL_PIPELINE_BIND_POINT_COMPUTE:
Chia-I Wuf8385062015-01-04 16:27:24 +08003244 cmd_bind_compute_dset(cmd, dset, pUserData);
Chia-I Wub2755562014-08-20 13:38:52 +08003245 break;
3246 case XGL_PIPELINE_BIND_POINT_GRAPHICS:
Chia-I Wuf8385062015-01-04 16:27:24 +08003247 cmd_bind_graphics_dset(cmd, dset, pUserData);
Chia-I Wub2755562014-08-20 13:38:52 +08003248 break;
3249 default:
Chia-I Wu4e5577a2015-02-10 11:04:44 -07003250 cmd_fail(cmd, XGL_ERROR_INVALID_VALUE);
Chia-I Wub2755562014-08-20 13:38:52 +08003251 break;
3252 }
3253}
3254
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003255ICD_EXPORT void XGLAPI xglCmdBindVertexBuffer(
Chia-I Wu3b04af52014-11-08 10:48:20 +08003256 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +08003257 XGL_BUFFER buffer,
Chia-I Wu3b04af52014-11-08 10:48:20 +08003258 XGL_GPU_SIZE offset,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003259 uint32_t binding)
Chia-I Wu3b04af52014-11-08 10:48:20 +08003260{
3261 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu714df452015-01-01 07:55:04 +08003262 struct intel_buf *buf = intel_buf(buffer);
Chia-I Wu3b04af52014-11-08 10:48:20 +08003263
Chia-I Wu714df452015-01-01 07:55:04 +08003264 cmd_bind_vertex_data(cmd, buf, offset, binding);
Chia-I Wu3b04af52014-11-08 10:48:20 +08003265}
3266
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003267ICD_EXPORT void XGLAPI xglCmdBindIndexBuffer(
Chia-I Wub2755562014-08-20 13:38:52 +08003268 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +08003269 XGL_BUFFER buffer,
Chia-I Wub2755562014-08-20 13:38:52 +08003270 XGL_GPU_SIZE offset,
3271 XGL_INDEX_TYPE indexType)
3272{
3273 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu714df452015-01-01 07:55:04 +08003274 struct intel_buf *buf = intel_buf(buffer);
Chia-I Wub2755562014-08-20 13:38:52 +08003275
Chia-I Wu714df452015-01-01 07:55:04 +08003276 cmd_bind_index_data(cmd, buf, offset, indexType);
Chia-I Wub2755562014-08-20 13:38:52 +08003277}
3278
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003279ICD_EXPORT void XGLAPI xglCmdDraw(
Chia-I Wub2755562014-08-20 13:38:52 +08003280 XGL_CMD_BUFFER cmdBuffer,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003281 uint32_t firstVertex,
3282 uint32_t vertexCount,
3283 uint32_t firstInstance,
3284 uint32_t instanceCount)
Chia-I Wub2755562014-08-20 13:38:52 +08003285{
Chia-I Wu59c097e2014-08-21 10:51:07 +08003286 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu59c097e2014-08-21 10:51:07 +08003287
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003288 cmd_draw(cmd, firstVertex, vertexCount,
3289 firstInstance, instanceCount, false, 0);
Chia-I Wub2755562014-08-20 13:38:52 +08003290}
3291
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003292ICD_EXPORT void XGLAPI xglCmdDrawIndexed(
Chia-I Wub2755562014-08-20 13:38:52 +08003293 XGL_CMD_BUFFER cmdBuffer,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003294 uint32_t firstIndex,
3295 uint32_t indexCount,
3296 int32_t vertexOffset,
3297 uint32_t firstInstance,
3298 uint32_t instanceCount)
Chia-I Wub2755562014-08-20 13:38:52 +08003299{
Chia-I Wu59c097e2014-08-21 10:51:07 +08003300 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
Chia-I Wu59c097e2014-08-21 10:51:07 +08003301
Chia-I Wu9f1722c2014-08-25 10:17:58 +08003302 cmd_draw(cmd, firstIndex, indexCount,
3303 firstInstance, instanceCount, true, vertexOffset);
Chia-I Wub2755562014-08-20 13:38:52 +08003304}
3305
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003306ICD_EXPORT void XGLAPI xglCmdDrawIndirect(
Chia-I Wub2755562014-08-20 13:38:52 +08003307 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +08003308 XGL_BUFFER buffer,
Chia-I Wub2755562014-08-20 13:38:52 +08003309 XGL_GPU_SIZE offset,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003310 uint32_t count,
3311 uint32_t stride)
Chia-I Wub2755562014-08-20 13:38:52 +08003312{
Chia-I Wu59c097e2014-08-21 10:51:07 +08003313 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
3314
Chia-I Wu4e5577a2015-02-10 11:04:44 -07003315 cmd_fail(cmd, XGL_ERROR_UNKNOWN);
Chia-I Wub2755562014-08-20 13:38:52 +08003316}
3317
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003318ICD_EXPORT void XGLAPI xglCmdDrawIndexedIndirect(
Chia-I Wub2755562014-08-20 13:38:52 +08003319 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +08003320 XGL_BUFFER buffer,
Chia-I Wub2755562014-08-20 13:38:52 +08003321 XGL_GPU_SIZE offset,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003322 uint32_t count,
3323 uint32_t stride)
Chia-I Wub2755562014-08-20 13:38:52 +08003324{
Chia-I Wu59c097e2014-08-21 10:51:07 +08003325 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
3326
Chia-I Wu4e5577a2015-02-10 11:04:44 -07003327 cmd_fail(cmd, XGL_ERROR_UNKNOWN);
Chia-I Wub2755562014-08-20 13:38:52 +08003328}
3329
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003330ICD_EXPORT void XGLAPI xglCmdDispatch(
Chia-I Wub2755562014-08-20 13:38:52 +08003331 XGL_CMD_BUFFER cmdBuffer,
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003332 uint32_t x,
3333 uint32_t y,
3334 uint32_t z)
Chia-I Wub2755562014-08-20 13:38:52 +08003335{
Chia-I Wu59c097e2014-08-21 10:51:07 +08003336 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
3337
Chia-I Wu4e5577a2015-02-10 11:04:44 -07003338 cmd_fail(cmd, XGL_ERROR_UNKNOWN);
Chia-I Wub2755562014-08-20 13:38:52 +08003339}
3340
Mark Lobodzinskie2d07a52015-01-29 08:55:56 -06003341ICD_EXPORT void XGLAPI xglCmdDispatchIndirect(
Chia-I Wub2755562014-08-20 13:38:52 +08003342 XGL_CMD_BUFFER cmdBuffer,
Chia-I Wu714df452015-01-01 07:55:04 +08003343 XGL_BUFFER buffer,
Chia-I Wub2755562014-08-20 13:38:52 +08003344 XGL_GPU_SIZE offset)
3345{
Chia-I Wu59c097e2014-08-21 10:51:07 +08003346 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
3347
Chia-I Wu4e5577a2015-02-10 11:04:44 -07003348 cmd_fail(cmd, XGL_ERROR_UNKNOWN);
Chia-I Wub2755562014-08-20 13:38:52 +08003349}