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Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
Chia-I Wu44e42362014-09-02 08:32:09 +080023 *
24 * Authors:
25 * Chia-I Wu <olv@lunarg.com>
26 * Courtney Goeltzenleuchter <courtney@lunarg.com>
Chia-I Wu09142132014-08-11 15:42:55 +080027 */
28
Chia-I Wu730e5362014-08-19 12:15:09 +080029#include "genhw/genhw.h"
30#include "kmd/winsys.h"
31#include "dev.h"
Chia-I Wu343b1372014-08-20 16:39:20 +080032#include "mem.h"
Chia-I Wu730e5362014-08-19 12:15:09 +080033#include "obj.h"
Chia-I Wu00a23b22014-08-20 15:28:08 +080034#include "cmd_priv.h"
Chia-I Wu09142132014-08-11 15:42:55 +080035
Chia-I Wu3c3edc02014-09-09 10:32:59 +080036/**
37 * Free all resources used by a writer. Note that the initial size is not
38 * reset.
39 */
40static void cmd_writer_reset(struct intel_cmd *cmd,
41 enum intel_cmd_writer_type which)
Chia-I Wu730e5362014-08-19 12:15:09 +080042{
Chia-I Wu68f319d2014-09-09 09:43:21 +080043 struct intel_cmd_writer *writer = &cmd->writers[which];
Chia-I Wu730e5362014-08-19 12:15:09 +080044
Chia-I Wu3c3edc02014-09-09 10:32:59 +080045 if (writer->ptr) {
46 intel_bo_unmap(writer->bo);
47 writer->ptr = NULL;
Chia-I Wu730e5362014-08-19 12:15:09 +080048 }
49
Chia-I Wu3c3edc02014-09-09 10:32:59 +080050 if (writer->bo) {
51 intel_bo_unreference(writer->bo);
52 writer->bo = NULL;
53 }
54
Chia-I Wue24c3292014-08-21 14:05:23 +080055 writer->used = 0;
Chia-I Wu3c3edc02014-09-09 10:32:59 +080056}
57
58/**
59 * Discard everything written so far.
60 */
61static void cmd_writer_discard(struct intel_cmd *cmd,
62 enum intel_cmd_writer_type which)
63{
64 struct intel_cmd_writer *writer = &cmd->writers[which];
65
66 intel_bo_truncate_relocs(writer->bo, 0);
67 writer->used = 0;
68}
69
70static struct intel_bo *alloc_writer_bo(struct intel_winsys *winsys,
71 enum intel_cmd_writer_type which,
72 XGL_UINT size)
73{
74 static const char *writer_names[INTEL_CMD_WRITER_COUNT] = {
75 [INTEL_CMD_WRITER_BATCH] = "batch",
76 [INTEL_CMD_WRITER_INSTRUCTION] = "instruction",
77 };
78
79 return intel_winsys_alloc_buffer(winsys, writer_names[which],
80 sizeof(uint32_t) * size, true);
81}
82
83/**
84 * Allocate and map the buffer for writing.
85 */
86static XGL_RESULT cmd_writer_alloc_and_map(struct intel_cmd *cmd,
87 enum intel_cmd_writer_type which)
88{
89 struct intel_cmd_writer *writer = &cmd->writers[which];
90 struct intel_bo *bo;
91
92 bo = alloc_writer_bo(cmd->dev->winsys, which, writer->size);
93 if (bo) {
94 if (writer->bo)
95 intel_bo_unreference(writer->bo);
96 writer->bo = bo;
97 } else if (writer->bo) {
98 /* reuse the old bo */
99 cmd_writer_discard(cmd, which);
100 } else {
101 return XGL_ERROR_OUT_OF_GPU_MEMORY;
102 }
103
104 writer->used = 0;
105
106 writer->ptr = intel_bo_map(writer->bo, true);
107 if (!writer->ptr)
108 return XGL_ERROR_UNKNOWN;
Chia-I Wu730e5362014-08-19 12:15:09 +0800109
110 return XGL_SUCCESS;
111}
112
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800113/**
114 * Unmap the buffer for submission.
115 */
116static void cmd_writer_unmap(struct intel_cmd *cmd,
117 enum intel_cmd_writer_type which)
Chia-I Wu5e25c272014-08-21 20:19:12 +0800118{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800119 struct intel_cmd_writer *writer = &cmd->writers[which];
120
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800121 intel_bo_unmap(writer->bo);
122 writer->ptr = NULL;
123}
124
125/**
126 * Grow a mapped writer to at least \p new_size. Failures are handled
127 * silently.
128 */
129void cmd_writer_grow(struct intel_cmd *cmd,
130 enum intel_cmd_writer_type which,
131 XGL_UINT new_size)
132{
133 struct intel_cmd_writer *writer = &cmd->writers[which];
134 struct intel_bo *new_bo;
135 void *new_ptr;
136
137 if (new_size < writer->size << 1)
138 new_size = writer->size << 1;
139 /* STATE_BASE_ADDRESS requires page-aligned buffers */
140 new_size = u_align(new_size, 4096 / sizeof(uint32_t));
141
142 new_bo = alloc_writer_bo(cmd->dev->winsys, which, new_size);
143 if (!new_bo) {
144 cmd_writer_discard(cmd, which);
145 cmd->result = XGL_ERROR_OUT_OF_GPU_MEMORY;
146 return;
147 }
148
149 /* map and copy the data over */
150 new_ptr = intel_bo_map(new_bo, true);
151 if (!new_ptr) {
152 intel_bo_unreference(new_bo);
153 cmd_writer_discard(cmd, which);
154 cmd->result = XGL_ERROR_UNKNOWN;
155 return;
156 }
157
158 memcpy(new_ptr, writer->ptr, sizeof(uint32_t) * writer->used);
159
160 intel_bo_unmap(writer->bo);
161 intel_bo_unreference(writer->bo);
162
163 writer->size = new_size;
164 writer->bo = new_bo;
165 writer->ptr = new_ptr;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800166}
167
168static void cmd_writer_patch(struct intel_cmd *cmd,
Chia-I Wu68f319d2014-09-09 09:43:21 +0800169 enum intel_cmd_writer_type which,
Chia-I Wu5e25c272014-08-21 20:19:12 +0800170 XGL_UINT pos, uint32_t val)
171{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800172 struct intel_cmd_writer *writer = &cmd->writers[which];
173
Chia-I Wu5e25c272014-08-21 20:19:12 +0800174 assert(pos < writer->used);
Chia-I Wu0f50ba82014-09-09 10:25:46 +0800175 ((uint32_t *) writer->ptr)[pos] = val;
Chia-I Wu5e25c272014-08-21 20:19:12 +0800176}
177
Chia-I Wu730e5362014-08-19 12:15:09 +0800178static void cmd_reset(struct intel_cmd *cmd)
179{
Chia-I Wu68f319d2014-09-09 09:43:21 +0800180 XGL_UINT i;
181
182 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
183 cmd_writer_reset(cmd, i);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800184
Chia-I Wu338fe642014-08-28 10:43:04 +0800185 if (cmd->bind.shaderCache.shaderArray)
186 icd_free(cmd->bind.shaderCache.shaderArray);
Chia-I Wue97aa0e2014-08-27 12:51:26 +0800187 memset(&cmd->bind, 0, sizeof(cmd->bind));
188
Chia-I Wu343b1372014-08-20 16:39:20 +0800189 cmd->reloc_used = 0;
Chia-I Wu04966702014-08-20 15:05:03 +0800190 cmd->result = XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800191}
192
193static void cmd_destroy(struct intel_obj *obj)
194{
195 struct intel_cmd *cmd = intel_cmd_from_obj(obj);
196
197 intel_cmd_destroy(cmd);
198}
199
200XGL_RESULT intel_cmd_create(struct intel_dev *dev,
201 const XGL_CMD_BUFFER_CREATE_INFO *info,
202 struct intel_cmd **cmd_ret)
203{
Chia-I Wu63883292014-08-25 13:50:26 +0800204 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800205 struct intel_cmd *cmd;
206
Chia-I Wu63883292014-08-25 13:50:26 +0800207 switch (info->queueType) {
208 case XGL_QUEUE_TYPE_GRAPHICS:
209 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_3D;
210 break;
211 case XGL_QUEUE_TYPE_COMPUTE:
212 pipeline_select = GEN6_PIPELINE_SELECT_DW0_SELECT_MEDIA;
213 break;
214 case XGL_QUEUE_TYPE_DMA:
215 pipeline_select = -1;
216 break;
217 default:
218 return XGL_ERROR_INVALID_VALUE;
219 break;
220 }
221
Chia-I Wu730e5362014-08-19 12:15:09 +0800222 cmd = (struct intel_cmd *) intel_base_create(dev, sizeof(*cmd),
223 dev->base.dbg, XGL_DBG_OBJECT_CMD_BUFFER, info, 0);
224 if (!cmd)
225 return XGL_ERROR_OUT_OF_MEMORY;
226
227 cmd->obj.destroy = cmd_destroy;
228
229 cmd->dev = dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800230 cmd->scratch_bo = dev->cmd_scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800231 cmd->pipeline_select = pipeline_select;
Chia-I Wue24c3292014-08-21 14:05:23 +0800232
Chia-I Wue0cdd832014-08-25 12:38:56 +0800233 /*
234 * XXX This is not quite right. intel_gpu sets maxMemRefsPerSubmission to
235 * batch_buffer_reloc_count, but we may emit up to two relocs, for start
236 * and end offsets, for each referenced memories.
237 */
Chia-I Wu343b1372014-08-20 16:39:20 +0800238 cmd->reloc_count = dev->gpu->batch_buffer_reloc_count;
239 cmd->relocs = icd_alloc(sizeof(cmd->relocs[0]) * cmd->reloc_count,
240 4096, XGL_SYSTEM_ALLOC_INTERNAL);
241 if (!cmd->relocs) {
242 intel_cmd_destroy(cmd);
243 return XGL_ERROR_OUT_OF_MEMORY;
244 }
Chia-I Wu730e5362014-08-19 12:15:09 +0800245
246 *cmd_ret = cmd;
247
248 return XGL_SUCCESS;
249}
250
251void intel_cmd_destroy(struct intel_cmd *cmd)
252{
253 cmd_reset(cmd);
Chia-I Wue24c3292014-08-21 14:05:23 +0800254
255 icd_free(cmd->relocs);
Chia-I Wu730e5362014-08-19 12:15:09 +0800256 intel_base_destroy(&cmd->obj.base);
257}
258
259XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags)
260{
Chia-I Wu24565ee2014-08-21 20:24:31 +0800261 XGL_RESULT ret;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800262 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800263
264 cmd_reset(cmd);
265
Chia-I Wu24565ee2014-08-21 20:24:31 +0800266 if (cmd->flags != flags) {
Chia-I Wue24c3292014-08-21 14:05:23 +0800267 cmd->flags = flags;
Chia-I Wu68f319d2014-09-09 09:43:21 +0800268 cmd->writers[INTEL_CMD_WRITER_BATCH].size = 0;
Chia-I Wu730e5362014-08-19 12:15:09 +0800269 }
270
Chia-I Wu68f319d2014-09-09 09:43:21 +0800271 if (!cmd->writers[INTEL_CMD_WRITER_BATCH].size) {
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800272 const XGL_UINT size =
273 cmd->dev->gpu->max_batch_buffer_size / sizeof(uint32_t) / 2;
274 XGL_UINT divider = 1;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800275
276 if (flags & XGL_CMD_BUFFER_OPTIMIZE_GPU_SMALL_BATCH_BIT)
277 divider *= 4;
278
Chia-I Wu68f319d2014-09-09 09:43:21 +0800279 cmd->writers[INTEL_CMD_WRITER_BATCH].size = size / divider;
280 cmd->writers[INTEL_CMD_WRITER_STATE].size = size / divider;
281 cmd->writers[INTEL_CMD_WRITER_INSTRUCTION].size =
282 16384 / sizeof(uint32_t) / divider;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800283 }
284
Chia-I Wu68f319d2014-09-09 09:43:21 +0800285 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++) {
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800286 ret = cmd_writer_alloc_and_map(cmd, i);
Chia-I Wu68f319d2014-09-09 09:43:21 +0800287 if (ret != XGL_SUCCESS) {
288 cmd_reset(cmd);
289 return ret;
290 }
Chia-I Wu24565ee2014-08-21 20:24:31 +0800291 }
292
Chia-I Wu79dfbb32014-08-25 12:19:02 +0800293 cmd_batch_begin(cmd);
294
Chia-I Wu24565ee2014-08-21 20:24:31 +0800295 return XGL_SUCCESS;
Chia-I Wu730e5362014-08-19 12:15:09 +0800296}
297
298XGL_RESULT intel_cmd_end(struct intel_cmd *cmd)
299{
300 struct intel_winsys *winsys = cmd->dev->winsys;
Chia-I Wu343b1372014-08-20 16:39:20 +0800301 XGL_UINT i;
Chia-I Wu730e5362014-08-19 12:15:09 +0800302
Chia-I Wue24c3292014-08-21 14:05:23 +0800303 cmd_batch_end(cmd);
Chia-I Wu730e5362014-08-19 12:15:09 +0800304
Chia-I Wu343b1372014-08-20 16:39:20 +0800305 /* TODO we need a more "explicit" winsys */
Chia-I Wufdfb8ed2014-08-21 15:40:07 +0800306 for (i = 0; i < cmd->reloc_used; i++) {
Chia-I Wu343b1372014-08-20 16:39:20 +0800307 const struct intel_cmd_reloc *reloc = &cmd->relocs[i];
Chia-I Wu68f319d2014-09-09 09:43:21 +0800308 const struct intel_cmd_writer *writer = &cmd->writers[reloc->which];
Chia-I Wu343b1372014-08-20 16:39:20 +0800309 uint64_t presumed_offset;
310 int err;
311
Chia-I Wu68f319d2014-09-09 09:43:21 +0800312 err = intel_bo_add_reloc(writer->bo,
Chia-I Wu9ee38722014-08-25 12:11:36 +0800313 sizeof(uint32_t) * reloc->pos, reloc->bo, reloc->val,
Chia-I Wu32a22462014-08-26 14:13:46 +0800314 reloc->flags, &presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800315 if (err) {
316 cmd->result = XGL_ERROR_UNKNOWN;
317 break;
318 }
319
320 assert(presumed_offset == (uint64_t) (uint32_t) presumed_offset);
Chia-I Wu68f319d2014-09-09 09:43:21 +0800321 cmd_writer_patch(cmd, reloc->which, reloc->pos,
Chia-I Wue24c3292014-08-21 14:05:23 +0800322 (uint32_t) presumed_offset);
Chia-I Wu343b1372014-08-20 16:39:20 +0800323 }
324
Chia-I Wu3c3edc02014-09-09 10:32:59 +0800325 for (i = 0; i < INTEL_CMD_WRITER_COUNT; i++)
326 cmd_writer_unmap(cmd, i);
Chia-I Wu730e5362014-08-19 12:15:09 +0800327
Chia-I Wu04966702014-08-20 15:05:03 +0800328 if (cmd->result != XGL_SUCCESS)
329 return cmd->result;
Chia-I Wue24c3292014-08-21 14:05:23 +0800330
Chia-I Wu68f319d2014-09-09 09:43:21 +0800331 if (intel_winsys_can_submit_bo(winsys,
332 &cmd->writers[INTEL_CMD_WRITER_BATCH].bo, 1))
Chia-I Wu730e5362014-08-19 12:15:09 +0800333 return XGL_SUCCESS;
334 else
335 return XGL_ERROR_TOO_MANY_MEMORY_REFERENCES;
336}
337
Chia-I Wu09142132014-08-11 15:42:55 +0800338XGL_RESULT XGLAPI intelCreateCommandBuffer(
339 XGL_DEVICE device,
340 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
341 XGL_CMD_BUFFER* pCmdBuffer)
342{
Chia-I Wu730e5362014-08-19 12:15:09 +0800343 struct intel_dev *dev = intel_dev(device);
344
345 return intel_cmd_create(dev, pCreateInfo,
346 (struct intel_cmd **) pCmdBuffer);
Chia-I Wu09142132014-08-11 15:42:55 +0800347}
348
349XGL_RESULT XGLAPI intelBeginCommandBuffer(
350 XGL_CMD_BUFFER cmdBuffer,
351 XGL_FLAGS flags)
352{
Chia-I Wu730e5362014-08-19 12:15:09 +0800353 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
354
355 return intel_cmd_begin(cmd, flags);
Chia-I Wu09142132014-08-11 15:42:55 +0800356}
357
358XGL_RESULT XGLAPI intelEndCommandBuffer(
359 XGL_CMD_BUFFER cmdBuffer)
360{
Chia-I Wu730e5362014-08-19 12:15:09 +0800361 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
362
363 return intel_cmd_end(cmd);
Chia-I Wu09142132014-08-11 15:42:55 +0800364}
365
366XGL_RESULT XGLAPI intelResetCommandBuffer(
367 XGL_CMD_BUFFER cmdBuffer)
368{
Chia-I Wu730e5362014-08-19 12:15:09 +0800369 struct intel_cmd *cmd = intel_cmd(cmdBuffer);
370
371 cmd_reset(cmd);
372
373 return XGL_SUCCESS;
Chia-I Wu09142132014-08-11 15:42:55 +0800374}
375
Chia-I Wu09142132014-08-11 15:42:55 +0800376XGL_VOID XGLAPI intelCmdCopyMemory(
377 XGL_CMD_BUFFER cmdBuffer,
378 XGL_GPU_MEMORY srcMem,
379 XGL_GPU_MEMORY destMem,
380 XGL_UINT regionCount,
381 const XGL_MEMORY_COPY* pRegions)
382{
383}
384
385XGL_VOID XGLAPI intelCmdCopyImage(
386 XGL_CMD_BUFFER cmdBuffer,
387 XGL_IMAGE srcImage,
388 XGL_IMAGE destImage,
389 XGL_UINT regionCount,
390 const XGL_IMAGE_COPY* pRegions)
391{
392}
393
394XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
395 XGL_CMD_BUFFER cmdBuffer,
396 XGL_GPU_MEMORY srcMem,
397 XGL_IMAGE destImage,
398 XGL_UINT regionCount,
399 const XGL_MEMORY_IMAGE_COPY* pRegions)
400{
401}
402
403XGL_VOID XGLAPI intelCmdCopyImageToMemory(
404 XGL_CMD_BUFFER cmdBuffer,
405 XGL_IMAGE srcImage,
406 XGL_GPU_MEMORY destMem,
407 XGL_UINT regionCount,
408 const XGL_MEMORY_IMAGE_COPY* pRegions)
409{
410}
411
412XGL_VOID XGLAPI intelCmdCloneImageData(
413 XGL_CMD_BUFFER cmdBuffer,
414 XGL_IMAGE srcImage,
415 XGL_IMAGE_STATE srcImageState,
416 XGL_IMAGE destImage,
417 XGL_IMAGE_STATE destImageState)
418{
419}
420
421XGL_VOID XGLAPI intelCmdUpdateMemory(
422 XGL_CMD_BUFFER cmdBuffer,
423 XGL_GPU_MEMORY destMem,
424 XGL_GPU_SIZE destOffset,
425 XGL_GPU_SIZE dataSize,
426 const XGL_UINT32* pData)
427{
428}
429
430XGL_VOID XGLAPI intelCmdFillMemory(
431 XGL_CMD_BUFFER cmdBuffer,
432 XGL_GPU_MEMORY destMem,
433 XGL_GPU_SIZE destOffset,
434 XGL_GPU_SIZE fillSize,
435 XGL_UINT32 data)
436{
437}
438
439XGL_VOID XGLAPI intelCmdClearColorImage(
440 XGL_CMD_BUFFER cmdBuffer,
441 XGL_IMAGE image,
442 const XGL_FLOAT color[4],
443 XGL_UINT rangeCount,
444 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
445{
446}
447
448XGL_VOID XGLAPI intelCmdClearColorImageRaw(
449 XGL_CMD_BUFFER cmdBuffer,
450 XGL_IMAGE image,
451 const XGL_UINT32 color[4],
452 XGL_UINT rangeCount,
453 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
454{
455}
456
457XGL_VOID XGLAPI intelCmdClearDepthStencil(
458 XGL_CMD_BUFFER cmdBuffer,
459 XGL_IMAGE image,
460 XGL_FLOAT depth,
461 XGL_UINT32 stencil,
462 XGL_UINT rangeCount,
463 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges)
464{
465}
466
467XGL_VOID XGLAPI intelCmdResolveImage(
468 XGL_CMD_BUFFER cmdBuffer,
469 XGL_IMAGE srcImage,
470 XGL_IMAGE destImage,
471 XGL_UINT rectCount,
472 const XGL_IMAGE_RESOLVE* pRects)
473{
474}
475
Chia-I Wu09142132014-08-11 15:42:55 +0800476XGL_VOID XGLAPI intelCmdMemoryAtomic(
477 XGL_CMD_BUFFER cmdBuffer,
478 XGL_GPU_MEMORY destMem,
479 XGL_GPU_SIZE destOffset,
480 XGL_UINT64 srcData,
481 XGL_ATOMIC_OP atomicOp)
482{
483}
484
Chia-I Wu09142132014-08-11 15:42:55 +0800485XGL_VOID XGLAPI intelCmdInitAtomicCounters(
486 XGL_CMD_BUFFER cmdBuffer,
487 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
488 XGL_UINT startCounter,
489 XGL_UINT counterCount,
490 const XGL_UINT32* pData)
491{
492}
493
494XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
495 XGL_CMD_BUFFER cmdBuffer,
496 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
497 XGL_UINT startCounter,
498 XGL_UINT counterCount,
499 XGL_GPU_MEMORY srcMem,
500 XGL_GPU_SIZE srcOffset)
501{
502}
503
504XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
505 XGL_CMD_BUFFER cmdBuffer,
506 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
507 XGL_UINT startCounter,
508 XGL_UINT counterCount,
509 XGL_GPU_MEMORY destMem,
510 XGL_GPU_SIZE destOffset)
511{
512}
513
514XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
515 XGL_CMD_BUFFER cmdBuffer,
516 const XGL_CHAR* pMarker)
517{
518}
519
520XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
521 XGL_CMD_BUFFER cmdBuffer)
522{
523}