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Chia-I Wu09142132014-08-11 15:42:55 +08001/*
2 * XGL
3 *
4 * Copyright (C) 2014 LunarG, Inc.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included
14 * in all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25#ifndef CMD_H
26#define CMD_H
27
28#include "intel.h"
29#include "obj.h"
Chia-I Wub2755562014-08-20 13:38:52 +080030#include "view.h"
31
32struct intel_pipeline;
33struct intel_pipeline_delta;
34struct intel_viewport_state;
35struct intel_raster_state;
36struct intel_msaa_state;
37struct intel_blend_state;
38struct intel_ds_state;
39struct intel_dset;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -060040struct intel_pipe_shader;
Chia-I Wub2755562014-08-20 13:38:52 +080041
Chia-I Wu958d1b72014-08-21 11:28:11 +080042struct intel_cmd_reloc;
43
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -060044struct intel_cmd_shader {
Chia-I Wu338fe642014-08-28 10:43:04 +080045 const struct intel_pipe_shader *shader;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -060046 XGL_UINT kernel_pos;
47};
48
Chia-I Wub2755562014-08-20 13:38:52 +080049/*
50 * States bounded to the command buffer. We want to write states directly to
51 * the command buffer when possible, and reduce this struct.
52 */
53struct intel_cmd_bind {
54 struct {
55 const struct intel_pipeline *graphics;
56 const struct intel_pipeline *compute;
57 const struct intel_pipeline_delta *graphics_delta;
58 const struct intel_pipeline_delta *compute_delta;
59 } pipeline;
60
Courtney Goeltzenleuchterba305812014-08-28 17:27:47 -060061 /*
62 * Currently active shaders for this command buffer.
63 * Provides data only available after shaders are bound to
64 * a command buffer, such as the kernel position in the kernel BO
65 */
66 struct intel_cmd_shader vs;
67 struct intel_cmd_shader fs;
68 struct intel_cmd_shader gs;
69 struct intel_cmd_shader tess_control;
70 struct intel_cmd_shader tess_eval;
71 struct intel_cmd_shader compute;
72
Chia-I Wub2755562014-08-20 13:38:52 +080073 struct {
Chia-I Wu338fe642014-08-28 10:43:04 +080074 XGL_UINT count;
75 XGL_UINT used;
76 struct intel_cmd_shader *shaderArray;
Courtney Goeltzenleuchterd85c1d62014-08-27 14:04:53 -060077 } shaderCache;
78
79 struct {
Chia-I Wub2755562014-08-20 13:38:52 +080080 const struct intel_viewport_state *viewport;
81 const struct intel_raster_state *raster;
82 const struct intel_msaa_state *msaa;
83 const struct intel_blend_state *blend;
84 const struct intel_ds_state *ds;
85 } state;
86
87 struct {
88 const struct intel_dset *graphics;
89 XGL_UINT graphics_offset;
90 const struct intel_dset *compute;
91 XGL_UINT compute_offset;
92 } dset;
93
94 struct {
95 struct intel_mem_view graphics;
96 struct intel_mem_view compute;
Chia-I Wu9f1722c2014-08-25 10:17:58 +080097 } dyn_view;
Chia-I Wub2755562014-08-20 13:38:52 +080098
99 struct {
100 const struct intel_mem *mem;
101 XGL_GPU_SIZE offset;
102 XGL_INDEX_TYPE type;
103 } index;
104
105 struct {
106 const struct intel_rt_view *rt[XGL_MAX_COLOR_ATTACHMENTS];
107 XGL_UINT rt_count;
108
109 const struct intel_ds_view *ds;
110 } att;
Chia-I Wu48c283d2014-08-25 23:13:46 +0800111
Chia-I Wu707a29e2014-08-27 12:51:47 +0800112 XGL_UINT draw_count;
Chia-I Wu48c283d2014-08-25 23:13:46 +0800113 uint32_t wa_flags;
Chia-I Wub2755562014-08-20 13:38:52 +0800114};
Chia-I Wu09142132014-08-11 15:42:55 +0800115
Chia-I Wue24c3292014-08-21 14:05:23 +0800116struct intel_cmd_writer {
117 struct intel_bo *bo;
118 void *ptr_opaque;
119
120 /* in DWords */
121 XGL_UINT size;
122 XGL_UINT used;
123};
124
Chia-I Wu730e5362014-08-19 12:15:09 +0800125struct intel_cmd {
126 struct intel_obj obj;
127
128 struct intel_dev *dev;
Chia-I Wu0b784442014-08-25 22:54:16 +0800129 struct intel_bo *scratch_bo;
Chia-I Wu63883292014-08-25 13:50:26 +0800130 int pipeline_select;
Chia-I Wu730e5362014-08-19 12:15:09 +0800131
Chia-I Wu343b1372014-08-20 16:39:20 +0800132 struct intel_cmd_reloc *relocs;
133 XGL_UINT reloc_count;
134
Chia-I Wu730e5362014-08-19 12:15:09 +0800135 XGL_FLAGS flags;
136
Chia-I Wue24c3292014-08-21 14:05:23 +0800137 struct intel_cmd_writer batch;
Chia-I Wu24565ee2014-08-21 20:24:31 +0800138 struct intel_cmd_writer state;
Chia-I Wu1cbc0052014-08-25 09:50:12 +0800139 struct intel_cmd_writer kernel;
Chia-I Wu730e5362014-08-19 12:15:09 +0800140
Chia-I Wu343b1372014-08-20 16:39:20 +0800141 XGL_UINT reloc_used;
Chia-I Wu04966702014-08-20 15:05:03 +0800142 XGL_RESULT result;
Chia-I Wub2755562014-08-20 13:38:52 +0800143
144 struct intel_cmd_bind bind;
Chia-I Wu730e5362014-08-19 12:15:09 +0800145};
146
147static inline struct intel_cmd *intel_cmd(XGL_CMD_BUFFER cmd)
148{
149 return (struct intel_cmd *) cmd;
150}
151
152static inline struct intel_cmd *intel_cmd_from_obj(struct intel_obj *obj)
153{
154 return (struct intel_cmd *) obj;
155}
156
157XGL_RESULT intel_cmd_create(struct intel_dev *dev,
158 const XGL_CMD_BUFFER_CREATE_INFO *info,
159 struct intel_cmd **cmd_ret);
160void intel_cmd_destroy(struct intel_cmd *cmd);
161
162XGL_RESULT intel_cmd_begin(struct intel_cmd *cmd, XGL_FLAGS flags);
163XGL_RESULT intel_cmd_end(struct intel_cmd *cmd);
164
Chia-I Wue24c3292014-08-21 14:05:23 +0800165static inline struct intel_bo *intel_cmd_get_batch(const struct intel_cmd *cmd,
166 XGL_GPU_SIZE *used)
167{
168 const struct intel_cmd_writer *writer = &cmd->batch;
169
170 if (used)
171 *used = sizeof(uint32_t) * writer->used;
172
173 return writer->bo;
174}
175
Chia-I Wu09142132014-08-11 15:42:55 +0800176XGL_RESULT XGLAPI intelCreateCommandBuffer(
177 XGL_DEVICE device,
178 const XGL_CMD_BUFFER_CREATE_INFO* pCreateInfo,
179 XGL_CMD_BUFFER* pCmdBuffer);
180
181XGL_RESULT XGLAPI intelBeginCommandBuffer(
182 XGL_CMD_BUFFER cmdBuffer,
183 XGL_FLAGS flags);
184
185XGL_RESULT XGLAPI intelEndCommandBuffer(
186 XGL_CMD_BUFFER cmdBuffer);
187
188XGL_RESULT XGLAPI intelResetCommandBuffer(
189 XGL_CMD_BUFFER cmdBuffer);
190
191XGL_VOID XGLAPI intelCmdBindPipeline(
192 XGL_CMD_BUFFER cmdBuffer,
193 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
194 XGL_PIPELINE pipeline);
195
196XGL_VOID XGLAPI intelCmdBindPipelineDelta(
197 XGL_CMD_BUFFER cmdBuffer,
198 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
199 XGL_PIPELINE_DELTA delta);
200
201XGL_VOID XGLAPI intelCmdBindStateObject(
202 XGL_CMD_BUFFER cmdBuffer,
203 XGL_STATE_BIND_POINT stateBindPoint,
204 XGL_STATE_OBJECT state);
205
206XGL_VOID XGLAPI intelCmdBindDescriptorSet(
207 XGL_CMD_BUFFER cmdBuffer,
208 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
209 XGL_UINT index,
210 XGL_DESCRIPTOR_SET descriptorSet,
211 XGL_UINT slotOffset);
212
213XGL_VOID XGLAPI intelCmdBindDynamicMemoryView(
214 XGL_CMD_BUFFER cmdBuffer,
215 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
216 const XGL_MEMORY_VIEW_ATTACH_INFO* pMemView);
217
218XGL_VOID XGLAPI intelCmdBindIndexData(
219 XGL_CMD_BUFFER cmdBuffer,
220 XGL_GPU_MEMORY mem,
221 XGL_GPU_SIZE offset,
222 XGL_INDEX_TYPE indexType);
223
224XGL_VOID XGLAPI intelCmdBindAttachments(
225 XGL_CMD_BUFFER cmdBuffer,
226 XGL_UINT colorAttachmentCount,
227 const XGL_COLOR_ATTACHMENT_BIND_INFO* pColorAttachments,
228 const XGL_DEPTH_STENCIL_BIND_INFO* pDepthStencilAttachment);
229
230XGL_VOID XGLAPI intelCmdPrepareMemoryRegions(
231 XGL_CMD_BUFFER cmdBuffer,
232 XGL_UINT transitionCount,
233 const XGL_MEMORY_STATE_TRANSITION* pStateTransitions);
234
235XGL_VOID XGLAPI intelCmdPrepareImages(
236 XGL_CMD_BUFFER cmdBuffer,
237 XGL_UINT transitionCount,
238 const XGL_IMAGE_STATE_TRANSITION* pStateTransitions);
239
240XGL_VOID XGLAPI intelCmdDraw(
241 XGL_CMD_BUFFER cmdBuffer,
242 XGL_UINT firstVertex,
243 XGL_UINT vertexCount,
244 XGL_UINT firstInstance,
245 XGL_UINT instanceCount);
246
247XGL_VOID XGLAPI intelCmdDrawIndexed(
248 XGL_CMD_BUFFER cmdBuffer,
249 XGL_UINT firstIndex,
250 XGL_UINT indexCount,
251 XGL_INT vertexOffset,
252 XGL_UINT firstInstance,
253 XGL_UINT instanceCount);
254
255XGL_VOID XGLAPI intelCmdDrawIndirect(
256 XGL_CMD_BUFFER cmdBuffer,
257 XGL_GPU_MEMORY mem,
258 XGL_GPU_SIZE offset,
259 XGL_UINT32 count,
260 XGL_UINT32 stride);
261
262XGL_VOID XGLAPI intelCmdDrawIndexedIndirect(
263 XGL_CMD_BUFFER cmdBuffer,
264 XGL_GPU_MEMORY mem,
265 XGL_GPU_SIZE offset,
266 XGL_UINT32 count,
267 XGL_UINT32 stride);
268
269XGL_VOID XGLAPI intelCmdDispatch(
270 XGL_CMD_BUFFER cmdBuffer,
271 XGL_UINT x,
272 XGL_UINT y,
273 XGL_UINT z);
274
275XGL_VOID XGLAPI intelCmdDispatchIndirect(
276 XGL_CMD_BUFFER cmdBuffer,
277 XGL_GPU_MEMORY mem,
278 XGL_GPU_SIZE offset);
279
280XGL_VOID XGLAPI intelCmdCopyMemory(
281 XGL_CMD_BUFFER cmdBuffer,
282 XGL_GPU_MEMORY srcMem,
283 XGL_GPU_MEMORY destMem,
284 XGL_UINT regionCount,
285 const XGL_MEMORY_COPY* pRegions);
286
287XGL_VOID XGLAPI intelCmdCopyImage(
288 XGL_CMD_BUFFER cmdBuffer,
289 XGL_IMAGE srcImage,
290 XGL_IMAGE destImage,
291 XGL_UINT regionCount,
292 const XGL_IMAGE_COPY* pRegions);
293
294XGL_VOID XGLAPI intelCmdCopyMemoryToImage(
295 XGL_CMD_BUFFER cmdBuffer,
296 XGL_GPU_MEMORY srcMem,
297 XGL_IMAGE destImage,
298 XGL_UINT regionCount,
299 const XGL_MEMORY_IMAGE_COPY* pRegions);
300
301XGL_VOID XGLAPI intelCmdCopyImageToMemory(
302 XGL_CMD_BUFFER cmdBuffer,
303 XGL_IMAGE srcImage,
304 XGL_GPU_MEMORY destMem,
305 XGL_UINT regionCount,
306 const XGL_MEMORY_IMAGE_COPY* pRegions);
307
308XGL_VOID XGLAPI intelCmdCloneImageData(
309 XGL_CMD_BUFFER cmdBuffer,
310 XGL_IMAGE srcImage,
311 XGL_IMAGE_STATE srcImageState,
312 XGL_IMAGE destImage,
313 XGL_IMAGE_STATE destImageState);
314
315XGL_VOID XGLAPI intelCmdUpdateMemory(
316 XGL_CMD_BUFFER cmdBuffer,
317 XGL_GPU_MEMORY destMem,
318 XGL_GPU_SIZE destOffset,
319 XGL_GPU_SIZE dataSize,
320 const XGL_UINT32* pData);
321
322XGL_VOID XGLAPI intelCmdFillMemory(
323 XGL_CMD_BUFFER cmdBuffer,
324 XGL_GPU_MEMORY destMem,
325 XGL_GPU_SIZE destOffset,
326 XGL_GPU_SIZE fillSize,
327 XGL_UINT32 data);
328
329XGL_VOID XGLAPI intelCmdClearColorImage(
330 XGL_CMD_BUFFER cmdBuffer,
331 XGL_IMAGE image,
332 const XGL_FLOAT color[4],
333 XGL_UINT rangeCount,
334 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
335
336XGL_VOID XGLAPI intelCmdClearColorImageRaw(
337 XGL_CMD_BUFFER cmdBuffer,
338 XGL_IMAGE image,
339 const XGL_UINT32 color[4],
340 XGL_UINT rangeCount,
341 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
342
343XGL_VOID XGLAPI intelCmdClearDepthStencil(
344 XGL_CMD_BUFFER cmdBuffer,
345 XGL_IMAGE image,
346 XGL_FLOAT depth,
347 XGL_UINT32 stencil,
348 XGL_UINT rangeCount,
349 const XGL_IMAGE_SUBRESOURCE_RANGE* pRanges);
350
351XGL_VOID XGLAPI intelCmdResolveImage(
352 XGL_CMD_BUFFER cmdBuffer,
353 XGL_IMAGE srcImage,
354 XGL_IMAGE destImage,
355 XGL_UINT rectCount,
356 const XGL_IMAGE_RESOLVE* pRects);
357
358XGL_VOID XGLAPI intelCmdSetEvent(
359 XGL_CMD_BUFFER cmdBuffer,
360 XGL_EVENT event);
361
362XGL_VOID XGLAPI intelCmdResetEvent(
363 XGL_CMD_BUFFER cmdBuffer,
364 XGL_EVENT event);
365
366XGL_VOID XGLAPI intelCmdMemoryAtomic(
367 XGL_CMD_BUFFER cmdBuffer,
368 XGL_GPU_MEMORY destMem,
369 XGL_GPU_SIZE destOffset,
370 XGL_UINT64 srcData,
371 XGL_ATOMIC_OP atomicOp);
372
373XGL_VOID XGLAPI intelCmdBeginQuery(
374 XGL_CMD_BUFFER cmdBuffer,
375 XGL_QUERY_POOL queryPool,
376 XGL_UINT slot,
377 XGL_FLAGS flags);
378
379XGL_VOID XGLAPI intelCmdEndQuery(
380 XGL_CMD_BUFFER cmdBuffer,
381 XGL_QUERY_POOL queryPool,
382 XGL_UINT slot);
383
384XGL_VOID XGLAPI intelCmdResetQueryPool(
385 XGL_CMD_BUFFER cmdBuffer,
386 XGL_QUERY_POOL queryPool,
387 XGL_UINT startQuery,
388 XGL_UINT queryCount);
389
390XGL_VOID XGLAPI intelCmdWriteTimestamp(
391 XGL_CMD_BUFFER cmdBuffer,
392 XGL_TIMESTAMP_TYPE timestampType,
393 XGL_GPU_MEMORY destMem,
394 XGL_GPU_SIZE destOffset);
395
396XGL_VOID XGLAPI intelCmdInitAtomicCounters(
397 XGL_CMD_BUFFER cmdBuffer,
398 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
399 XGL_UINT startCounter,
400 XGL_UINT counterCount,
401 const XGL_UINT32* pData);
402
403XGL_VOID XGLAPI intelCmdLoadAtomicCounters(
404 XGL_CMD_BUFFER cmdBuffer,
405 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
406 XGL_UINT startCounter,
407 XGL_UINT counterCount,
408 XGL_GPU_MEMORY srcMem,
409 XGL_GPU_SIZE srcOffset);
410
411XGL_VOID XGLAPI intelCmdSaveAtomicCounters(
412 XGL_CMD_BUFFER cmdBuffer,
413 XGL_PIPELINE_BIND_POINT pipelineBindPoint,
414 XGL_UINT startCounter,
415 XGL_UINT counterCount,
416 XGL_GPU_MEMORY destMem,
417 XGL_GPU_SIZE destOffset);
418
419XGL_VOID XGLAPI intelCmdDbgMarkerBegin(
420 XGL_CMD_BUFFER cmdBuffer,
421 const XGL_CHAR* pMarker);
422
423XGL_VOID XGLAPI intelCmdDbgMarkerEnd(
424 XGL_CMD_BUFFER cmdBuffer);
425
426#endif /* CMD_H */