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gerrit-public.fairphone.software / toolchain / llvm-project / 0fe4632bd75339405dfdbcd1b0b69353244f3b9e / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: c783da0611c4aa180697c20ab789ead8f1d5caae [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]21#include "llvm/CodeGen/LivePhysRegs.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]22#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]23#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]24#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]25#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]26#include "llvm/CodeGen/MachineInstrBuilder.h"
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]27#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]28#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]29#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]30#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]31#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]32#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]33#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]34#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]35#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]36#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]37#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]40#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]41
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]42using namespace llvm;
43
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]44#define DEBUG_TYPE "x86-instr-info"
45
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]46#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]47#include "X86GenInstrInfo.inc"
48
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]49static cl::opt<bool>
50NoFusing("disable-spill-fusing",
51 cl::desc("Disable fusing of spill code into instructions"));
52static cl::opt<bool>
53PrintFailedFusing("print-failed-fuse-candidates",
54 cl::desc("Print instructions that the allocator wants to"
55 " fuse, but the X86 backend currently can't"),
56 cl::Hidden);
57static cl::opt<bool>
58ReMatPICStubLoad("remat-pic-stub-load",
59 cl::desc("Re-materialize load from stub in PIC mode"),
60 cl::init(false), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]61
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]62enum {
63 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]64 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]65 TB_INDEX_0 = 0,
66 TB_INDEX_1 = 1,
67 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]68 TB_INDEX_3 = 3,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]69 TB_INDEX_4 = 4,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]70 TB_INDEX_MASK = 0xf,
71
72 // Do not insert the reverse map (MemOp -> RegOp) into the table.
73 // This may be needed because there is a many -> one mapping.
74 TB_NO_REVERSE = 1 << 4,
75
76 // Do not insert the forward map (RegOp -> MemOp) into the table.
77 // This is needed for Native Client, which prohibits branch
78 // instructions from using a memory operand.
79 TB_NO_FORWARD = 1 << 5,
80
81 TB_FOLDED_LOAD = 1 << 6,
82 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]83
84 // Minimum alignment required for load/store.
85 // Used for RegOp->MemOp conversion.
86 // (stored in bits 8 - 15)
87 TB_ALIGN_SHIFT = 8,
88 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
89 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
90 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]91 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]92 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]93};
94
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]95struct X86MemoryFoldTableEntry {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]96 uint16_t RegOp;
97 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]98 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]99};
100
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]101// Pin the vtable to this file.
102void X86InstrInfo::anchor() {}
103
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]104X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
David Majnemerf828a0c2015-10-01 18:44:59 +0000[diff] [blame]105 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
106 : X86::ADJCALLSTACKDOWN32),
107 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
108 : X86::ADJCALLSTACKUP32),
109 X86::CATCHRET),
Eric Christophered6a4462015-03-12 17:54:19 +0000[diff] [blame]110 Subtarget(STI), RI(STI.getTargetTriple()) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]111
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]112 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]113 { X86::ADC32ri, X86::ADC32mi, 0 },
114 { X86::ADC32ri8, X86::ADC32mi8, 0 },
115 { X86::ADC32rr, X86::ADC32mr, 0 },
116 { X86::ADC64ri32, X86::ADC64mi32, 0 },
117 { X86::ADC64ri8, X86::ADC64mi8, 0 },
118 { X86::ADC64rr, X86::ADC64mr, 0 },
119 { X86::ADD16ri, X86::ADD16mi, 0 },
120 { X86::ADD16ri8, X86::ADD16mi8, 0 },
121 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
122 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
123 { X86::ADD16rr, X86::ADD16mr, 0 },
124 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
125 { X86::ADD32ri, X86::ADD32mi, 0 },
126 { X86::ADD32ri8, X86::ADD32mi8, 0 },
127 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
128 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
129 { X86::ADD32rr, X86::ADD32mr, 0 },
130 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
131 { X86::ADD64ri32, X86::ADD64mi32, 0 },
132 { X86::ADD64ri8, X86::ADD64mi8, 0 },
133 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
134 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
135 { X86::ADD64rr, X86::ADD64mr, 0 },
136 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
137 { X86::ADD8ri, X86::ADD8mi, 0 },
138 { X86::ADD8rr, X86::ADD8mr, 0 },
139 { X86::AND16ri, X86::AND16mi, 0 },
140 { X86::AND16ri8, X86::AND16mi8, 0 },
141 { X86::AND16rr, X86::AND16mr, 0 },
142 { X86::AND32ri, X86::AND32mi, 0 },
143 { X86::AND32ri8, X86::AND32mi8, 0 },
144 { X86::AND32rr, X86::AND32mr, 0 },
145 { X86::AND64ri32, X86::AND64mi32, 0 },
146 { X86::AND64ri8, X86::AND64mi8, 0 },
147 { X86::AND64rr, X86::AND64mr, 0 },
148 { X86::AND8ri, X86::AND8mi, 0 },
149 { X86::AND8rr, X86::AND8mr, 0 },
150 { X86::DEC16r, X86::DEC16m, 0 },
151 { X86::DEC32r, X86::DEC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]152 { X86::DEC64r, X86::DEC64m, 0 },
153 { X86::DEC8r, X86::DEC8m, 0 },
154 { X86::INC16r, X86::INC16m, 0 },
155 { X86::INC32r, X86::INC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]156 { X86::INC64r, X86::INC64m, 0 },
157 { X86::INC8r, X86::INC8m, 0 },
158 { X86::NEG16r, X86::NEG16m, 0 },
159 { X86::NEG32r, X86::NEG32m, 0 },
160 { X86::NEG64r, X86::NEG64m, 0 },
161 { X86::NEG8r, X86::NEG8m, 0 },
162 { X86::NOT16r, X86::NOT16m, 0 },
163 { X86::NOT32r, X86::NOT32m, 0 },
164 { X86::NOT64r, X86::NOT64m, 0 },
165 { X86::NOT8r, X86::NOT8m, 0 },
166 { X86::OR16ri, X86::OR16mi, 0 },
167 { X86::OR16ri8, X86::OR16mi8, 0 },
168 { X86::OR16rr, X86::OR16mr, 0 },
169 { X86::OR32ri, X86::OR32mi, 0 },
170 { X86::OR32ri8, X86::OR32mi8, 0 },
171 { X86::OR32rr, X86::OR32mr, 0 },
172 { X86::OR64ri32, X86::OR64mi32, 0 },
173 { X86::OR64ri8, X86::OR64mi8, 0 },
174 { X86::OR64rr, X86::OR64mr, 0 },
175 { X86::OR8ri, X86::OR8mi, 0 },
176 { X86::OR8rr, X86::OR8mr, 0 },
177 { X86::ROL16r1, X86::ROL16m1, 0 },
178 { X86::ROL16rCL, X86::ROL16mCL, 0 },
179 { X86::ROL16ri, X86::ROL16mi, 0 },
180 { X86::ROL32r1, X86::ROL32m1, 0 },
181 { X86::ROL32rCL, X86::ROL32mCL, 0 },
182 { X86::ROL32ri, X86::ROL32mi, 0 },
183 { X86::ROL64r1, X86::ROL64m1, 0 },
184 { X86::ROL64rCL, X86::ROL64mCL, 0 },
185 { X86::ROL64ri, X86::ROL64mi, 0 },
186 { X86::ROL8r1, X86::ROL8m1, 0 },
187 { X86::ROL8rCL, X86::ROL8mCL, 0 },
188 { X86::ROL8ri, X86::ROL8mi, 0 },
189 { X86::ROR16r1, X86::ROR16m1, 0 },
190 { X86::ROR16rCL, X86::ROR16mCL, 0 },
191 { X86::ROR16ri, X86::ROR16mi, 0 },
192 { X86::ROR32r1, X86::ROR32m1, 0 },
193 { X86::ROR32rCL, X86::ROR32mCL, 0 },
194 { X86::ROR32ri, X86::ROR32mi, 0 },
195 { X86::ROR64r1, X86::ROR64m1, 0 },
196 { X86::ROR64rCL, X86::ROR64mCL, 0 },
197 { X86::ROR64ri, X86::ROR64mi, 0 },
198 { X86::ROR8r1, X86::ROR8m1, 0 },
199 { X86::ROR8rCL, X86::ROR8mCL, 0 },
200 { X86::ROR8ri, X86::ROR8mi, 0 },
201 { X86::SAR16r1, X86::SAR16m1, 0 },
202 { X86::SAR16rCL, X86::SAR16mCL, 0 },
203 { X86::SAR16ri, X86::SAR16mi, 0 },
204 { X86::SAR32r1, X86::SAR32m1, 0 },
205 { X86::SAR32rCL, X86::SAR32mCL, 0 },
206 { X86::SAR32ri, X86::SAR32mi, 0 },
207 { X86::SAR64r1, X86::SAR64m1, 0 },
208 { X86::SAR64rCL, X86::SAR64mCL, 0 },
209 { X86::SAR64ri, X86::SAR64mi, 0 },
210 { X86::SAR8r1, X86::SAR8m1, 0 },
211 { X86::SAR8rCL, X86::SAR8mCL, 0 },
212 { X86::SAR8ri, X86::SAR8mi, 0 },
213 { X86::SBB32ri, X86::SBB32mi, 0 },
214 { X86::SBB32ri8, X86::SBB32mi8, 0 },
215 { X86::SBB32rr, X86::SBB32mr, 0 },
216 { X86::SBB64ri32, X86::SBB64mi32, 0 },
217 { X86::SBB64ri8, X86::SBB64mi8, 0 },
218 { X86::SBB64rr, X86::SBB64mr, 0 },
219 { X86::SHL16rCL, X86::SHL16mCL, 0 },
220 { X86::SHL16ri, X86::SHL16mi, 0 },
221 { X86::SHL32rCL, X86::SHL32mCL, 0 },
222 { X86::SHL32ri, X86::SHL32mi, 0 },
223 { X86::SHL64rCL, X86::SHL64mCL, 0 },
224 { X86::SHL64ri, X86::SHL64mi, 0 },
225 { X86::SHL8rCL, X86::SHL8mCL, 0 },
226 { X86::SHL8ri, X86::SHL8mi, 0 },
227 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
228 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
229 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
230 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
231 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
232 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
233 { X86::SHR16r1, X86::SHR16m1, 0 },
234 { X86::SHR16rCL, X86::SHR16mCL, 0 },
235 { X86::SHR16ri, X86::SHR16mi, 0 },
236 { X86::SHR32r1, X86::SHR32m1, 0 },
237 { X86::SHR32rCL, X86::SHR32mCL, 0 },
238 { X86::SHR32ri, X86::SHR32mi, 0 },
239 { X86::SHR64r1, X86::SHR64m1, 0 },
240 { X86::SHR64rCL, X86::SHR64mCL, 0 },
241 { X86::SHR64ri, X86::SHR64mi, 0 },
242 { X86::SHR8r1, X86::SHR8m1, 0 },
243 { X86::SHR8rCL, X86::SHR8mCL, 0 },
244 { X86::SHR8ri, X86::SHR8mi, 0 },
245 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
246 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
247 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
248 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
249 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
250 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
251 { X86::SUB16ri, X86::SUB16mi, 0 },
252 { X86::SUB16ri8, X86::SUB16mi8, 0 },
253 { X86::SUB16rr, X86::SUB16mr, 0 },
254 { X86::SUB32ri, X86::SUB32mi, 0 },
255 { X86::SUB32ri8, X86::SUB32mi8, 0 },
256 { X86::SUB32rr, X86::SUB32mr, 0 },
257 { X86::SUB64ri32, X86::SUB64mi32, 0 },
258 { X86::SUB64ri8, X86::SUB64mi8, 0 },
259 { X86::SUB64rr, X86::SUB64mr, 0 },
260 { X86::SUB8ri, X86::SUB8mi, 0 },
261 { X86::SUB8rr, X86::SUB8mr, 0 },
262 { X86::XOR16ri, X86::XOR16mi, 0 },
263 { X86::XOR16ri8, X86::XOR16mi8, 0 },
264 { X86::XOR16rr, X86::XOR16mr, 0 },
265 { X86::XOR32ri, X86::XOR32mi, 0 },
266 { X86::XOR32ri8, X86::XOR32mi8, 0 },
267 { X86::XOR32rr, X86::XOR32mr, 0 },
268 { X86::XOR64ri32, X86::XOR64mi32, 0 },
269 { X86::XOR64ri8, X86::XOR64mi8, 0 },
270 { X86::XOR64rr, X86::XOR64mr, 0 },
271 { X86::XOR8ri, X86::XOR8mi, 0 },
272 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]273 };
274
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]275 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]276 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]277 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]278 // Index 0, folded load and store, no alignment requirement.
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]279 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]280 }
281
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]282 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]283 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
284 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
285 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
286 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
287 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]288 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
289 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
290 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
291 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
292 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
293 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
294 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
295 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
296 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
297 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
298 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
299 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
300 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
301 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
302 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]303 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]304 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
305 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
306 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
307 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
308 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
309 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
310 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
311 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
312 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
313 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
314 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
315 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
316 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
317 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
318 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
319 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
320 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
321 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
322 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
324 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
325 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]326 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
327 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
328 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
329 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
330 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
331 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]332 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
333 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
334 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
335 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]336 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
337 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]338 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
339 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
340 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]341 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
342 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
343 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
344 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
345 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
346 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
347 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
348 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
349 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
350 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
351 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
352 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
353 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
354 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
355 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
356 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
357 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
358 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
Reid Klecknera580b6e2015-01-30 21:03:31 +0000[diff] [blame]359 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]360 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
361 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
362 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]363 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]364
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]365 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]366 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]367 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]368 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
369 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
370 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
371 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
372 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
373 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
374 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
375 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
376 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]377 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
378 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]379
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]380 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]381 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]382 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
383 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
384 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
385 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]386 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]387
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]388 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]389 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
390 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
391 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
392 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
393 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
394 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
395 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]396 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
397 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]398 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]399 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]400
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]401 // AVX-512 foldable instructions (256-bit versions)
402 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
403 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
404 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
405 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
406 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
407 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
408 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
409 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
410 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
411 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]412
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]413 // AVX-512 foldable instructions (128-bit versions)
414 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
415 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
416 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
417 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
418 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
419 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
420 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
421 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
422 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]423 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]424
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]425 // F16C foldable instructions
426 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
427 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]428 };
429
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]430 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]431 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]432 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]433 }
434
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]435 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
Simon Pilgrim3a771802015-06-07 18:34:25 +0000[diff] [blame]436 { X86::BSF16rr, X86::BSF16rm, 0 },
437 { X86::BSF32rr, X86::BSF32rm, 0 },
438 { X86::BSF64rr, X86::BSF64rm, 0 },
439 { X86::BSR16rr, X86::BSR16rm, 0 },
440 { X86::BSR32rr, X86::BSR32rm, 0 },
441 { X86::BSR64rr, X86::BSR64rm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]442 { X86::CMP16rr, X86::CMP16rm, 0 },
443 { X86::CMP32rr, X86::CMP32rm, 0 },
444 { X86::CMP64rr, X86::CMP64rm, 0 },
445 { X86::CMP8rr, X86::CMP8rm, 0 },
446 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
447 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
448 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
449 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
450 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
451 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
452 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
453 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
454 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
455 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]456 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
457 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
458 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
459 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
460 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
461 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
462 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
463 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]464 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
465 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]466 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
467 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]468 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]469 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]470 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]471 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]472 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]473 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]474 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
475 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
476 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
477 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
478 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
479 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
480 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
481 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]482 { X86::MOV16rr, X86::MOV16rm, 0 },
483 { X86::MOV32rr, X86::MOV32rm, 0 },
484 { X86::MOV64rr, X86::MOV64rm, 0 },
485 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
486 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
487 { X86::MOV8rr, X86::MOV8rm, 0 },
488 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
489 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]490 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
491 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
492 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
493 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]494 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
495 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
496 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
497 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
498 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
499 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
500 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
501 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
502 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
503 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]504 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
505 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
506 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
507 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
508 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]509 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
510 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
511 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]512 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
513 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
514 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
515 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
516 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
517 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
518 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
519 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
520 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
521 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
522 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
523 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
524 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
525 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
526 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
527 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
528 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]529 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
530 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
531 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]532 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]533 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]534 { X86::RCPSSr, X86::RCPSSm, 0 },
535 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]536 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
537 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]538 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]539 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
540 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
541 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]542 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]543 { X86::SQRTSDr, X86::SQRTSDm, 0 },
544 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
545 { X86::SQRTSSr, X86::SQRTSSm, 0 },
546 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
547 { X86::TEST16rr, X86::TEST16rm, 0 },
548 { X86::TEST32rr, X86::TEST32rm, 0 },
549 { X86::TEST64rr, X86::TEST64rm, 0 },
550 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]551 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]552 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
553 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]554
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]555 // MMX version of foldable instructions
556 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
557 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
558 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
559 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
560 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
561 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
562 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
563 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
564 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
565 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
566
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]567 // 3DNow! version of foldable instructions
568 { X86::PF2IDrr, X86::PF2IDrm, 0 },
569 { X86::PF2IWrr, X86::PF2IWrm, 0 },
570 { X86::PFRCPrr, X86::PFRCPrm, 0 },
571 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
572 { X86::PI2FDrr, X86::PI2FDrm, 0 },
573 { X86::PI2FWrr, X86::PI2FWrm, 0 },
574 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
575
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]576 // AVX 128-bit versions of foldable instructions
577 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
578 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]579 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
580 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]581 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
582 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]583 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]584 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
585 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
586 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
587 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
588 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
589 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
590 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
591 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
592 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]593 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]594 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]595 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]596 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]597 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]598 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]599 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
600 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]601 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
602 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
603 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
604 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
605 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
606 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
607 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
608 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]609 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
610 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]611 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]612 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]613 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]614 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
615 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
616 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]617 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
618 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
619 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
620 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
621 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]622 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
623 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]624 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
625 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
626 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
627 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
628 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
629 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
630 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
631 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
632 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
633 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
634 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
635 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]636 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
637 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
638 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]639 { X86::VPTESTrr, X86::VPTESTrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]640 { X86::VRCPPSr, X86::VRCPPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]641 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
642 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]643 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]644 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]645 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]646 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
647 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]648 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]649 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]650
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]651 // AVX 256-bit foldable instructions
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]652 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]653 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]654 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]655 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]656 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]657 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]658 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
659 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]660 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
661 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]662 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]663 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]664 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
665 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]666 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]667 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]668 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
669 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima2618672015-02-07 21:44:06 +0000[diff] [blame]670 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]671 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]672 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
673 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]674 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
675 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
676 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]677 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
678 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]679
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]680 // AVX2 foldable instructions
Sanjay Patel1a20fdf2015-02-17 22:09:54 +0000[diff] [blame]681
682 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
683 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
684 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
685 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
686 // so they don't need an equivalent limitation.
Simon Pilgrimd11b0132015-02-08 17:13:54 +0000[diff] [blame]687 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
688 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
689 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]690 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
691 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
692 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]693 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
694 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
695 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
696 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
697 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
698 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
699 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
700 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
701 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
702 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
703 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
704 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
705 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
706 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
707 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
708 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
709 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
710 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
711 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
712 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
713 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
714 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]715 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
716 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
717 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]718
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]719 // XOP foldable instructions
720 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
721 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
722 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
723 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
724 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
725 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
726 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
727 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
728 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
729 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
730 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
731 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
732 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
733 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
734 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
735 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
736 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
737 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
738 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
739 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
740 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
741 { X86::VPROTBri, X86::VPROTBmi, 0 },
742 { X86::VPROTBrr, X86::VPROTBmr, 0 },
743 { X86::VPROTDri, X86::VPROTDmi, 0 },
744 { X86::VPROTDrr, X86::VPROTDmr, 0 },
745 { X86::VPROTQri, X86::VPROTQmi, 0 },
746 { X86::VPROTQrr, X86::VPROTQmr, 0 },
747 { X86::VPROTWri, X86::VPROTWmi, 0 },
748 { X86::VPROTWrr, X86::VPROTWmr, 0 },
749 { X86::VPSHABrr, X86::VPSHABmr, 0 },
750 { X86::VPSHADrr, X86::VPSHADmr, 0 },
751 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
752 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
753 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
754 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
755 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
756 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
757
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]758 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]759 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
760 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]761 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
762 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
763 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
764 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
765 { X86::BLCI32rr, X86::BLCI32rm, 0 },
766 { X86::BLCI64rr, X86::BLCI64rm, 0 },
767 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
768 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
769 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
770 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
771 { X86::BLCS32rr, X86::BLCS32rm, 0 },
772 { X86::BLCS64rr, X86::BLCS64rm, 0 },
773 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
774 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]775 { X86::BLSI32rr, X86::BLSI32rm, 0 },
776 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]777 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
778 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]779 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
780 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
781 { X86::BLSR32rr, X86::BLSR32rm, 0 },
782 { X86::BLSR64rr, X86::BLSR64rm, 0 },
783 { X86::BZHI32rr, X86::BZHI32rm, 0 },
784 { X86::BZHI64rr, X86::BZHI64rm, 0 },
785 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
786 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
787 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
788 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
789 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
790 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]791 { X86::RORX32ri, X86::RORX32mi, 0 },
792 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]793 { X86::SARX32rr, X86::SARX32rm, 0 },
794 { X86::SARX64rr, X86::SARX64rm, 0 },
795 { X86::SHRX32rr, X86::SHRX32rm, 0 },
796 { X86::SHRX64rr, X86::SHRX64rm, 0 },
797 { X86::SHLX32rr, X86::SHLX32rm, 0 },
798 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]799 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
800 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]801 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
802 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
803 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]804 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
805 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]806
807 // AVX-512 foldable instructions
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]808 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
809 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
810 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
811 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
812 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
813 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
814 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
815 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
816 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
817 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
818 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
819 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
820 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
821 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
822 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
823 { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm, TB_NO_REVERSE },
824 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
825 { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]826
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]827 // AVX-512 foldable instructions (256-bit versions)
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]828 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
829 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
830 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
831 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
832 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
833 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
834 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
835 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
836 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
837 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
838 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
839 { X86::VBROADCASTSSZ256r_s, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
840 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
841 { X86::VBROADCASTSDZ256r_s, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]842
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]843 // AVX-512 foldable instructions (128-bit versions)
844 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
845 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
846 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
847 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
848 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
849 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
850 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
851 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
852 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
853 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
854 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
855 { X86::VBROADCASTSSZ128r_s, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]856 // F16C foldable instructions
857 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
858 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]859
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]860 // AES foldable instructions
861 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
862 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
Simon Pilgrim295eaad2015-02-12 20:01:03 +0000[diff] [blame]863 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
864 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]865 };
866
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]867 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]868 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]869 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]870 // Index 1, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]871 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]872 }
873
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]874 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]875 { X86::ADC32rr, X86::ADC32rm, 0 },
876 { X86::ADC64rr, X86::ADC64rm, 0 },
877 { X86::ADD16rr, X86::ADD16rm, 0 },
878 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
879 { X86::ADD32rr, X86::ADD32rm, 0 },
880 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
881 { X86::ADD64rr, X86::ADD64rm, 0 },
882 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
883 { X86::ADD8rr, X86::ADD8rm, 0 },
884 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
885 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
886 { X86::ADDSDrr, X86::ADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]887 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]888 { X86::ADDSSrr, X86::ADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]889 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]890 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
891 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
892 { X86::AND16rr, X86::AND16rm, 0 },
893 { X86::AND32rr, X86::AND32rm, 0 },
894 { X86::AND64rr, X86::AND64rm, 0 },
895 { X86::AND8rr, X86::AND8rm, 0 },
896 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
897 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
898 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
899 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]900 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
901 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
902 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
903 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]904 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
905 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
906 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
907 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
908 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
909 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
910 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
911 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
912 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
913 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
914 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
915 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
916 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
917 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
918 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
919 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
920 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
921 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
922 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
923 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
924 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
925 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
926 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
927 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
928 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
929 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
930 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
931 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
932 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
933 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
934 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
935 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
936 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
937 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
938 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
939 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
940 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
941 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
942 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
943 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
944 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
945 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
946 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
947 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
948 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
949 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
950 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
951 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
952 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
953 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
954 { X86::CMPSDrr, X86::CMPSDrm, 0 },
955 { X86::CMPSSrr, X86::CMPSSrm, 0 },
Simon Pilgrim01846222015-04-03 14:24:40 +0000[diff] [blame]956 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
957 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]958 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
959 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
960 { X86::DIVSDrr, X86::DIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]961 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]962 { X86::DIVSSrr, X86::DIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]963 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
964 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
965 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]966
Sanjay Patel8c13e362015-07-28 00:48:32 +0000[diff] [blame]967 // Do not fold Fs* scalar logical op loads because there are no scalar
968 // load variants for these instructions. When folded, the load is required
969 // to be 128-bits, so the load size would not match.
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]970
971 { X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 },
972 { X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 },
973 { X86::FvANDPDrr, X86::FvANDPDrm, TB_ALIGN_16 },
974 { X86::FvANDPSrr, X86::FvANDPSrm, TB_ALIGN_16 },
975 { X86::FvORPDrr, X86::FvORPDrm, TB_ALIGN_16 },
976 { X86::FvORPSrr, X86::FvORPSrm, TB_ALIGN_16 },
977 { X86::FvXORPDrr, X86::FvXORPDrm, TB_ALIGN_16 },
978 { X86::FvXORPSrr, X86::FvXORPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]979 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
980 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
981 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
982 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
983 { X86::IMUL16rr, X86::IMUL16rm, 0 },
984 { X86::IMUL32rr, X86::IMUL32rm, 0 },
985 { X86::IMUL64rr, X86::IMUL64rm, 0 },
986 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
987 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]988 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
989 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
990 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
991 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
992 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
993 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]994 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]995 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]996 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]997 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]998 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]999 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1000 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1001 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1002 { X86::MINSDrr, X86::MINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1003 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1004 { X86::MINSSrr, X86::MINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1005 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1006 { X86::MOVLHPSrr, X86::MOVHPSrm, TB_NO_REVERSE },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1007 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1008 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1009 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1010 { X86::MULSDrr, X86::MULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1011 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1012 { X86::MULSSrr, X86::MULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1013 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1014 { X86::OR16rr, X86::OR16rm, 0 },
1015 { X86::OR32rr, X86::OR32rm, 0 },
1016 { X86::OR64rr, X86::OR64rm, 0 },
1017 { X86::OR8rr, X86::OR8rm, 0 },
1018 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1019 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1020 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1021 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1022 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1023 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1024 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1025 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1026 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1027 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1028 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1029 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1030 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1031 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1032 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1033 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1034 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1035 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1036 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1037 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1038 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1039 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1040 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1041 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1042 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1043 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1044 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1045 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1046 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1047 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1048 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1049 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1050 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1051 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1052 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1053 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1054 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1055 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1056 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1057 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1058 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1059 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1060 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1061 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1062 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1063 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]1064 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1065 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1066 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1067 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1068 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1069 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1070 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1071 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1072 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1073 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1074 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1075 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1076 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1077 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1078 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1079 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1080 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1081 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1082 { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
1083 { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
1084 { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1085 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1086 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1087 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1088 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1089 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1090 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1091 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1092 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1093 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1094 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1095 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1096 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1097 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1098 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1099 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1100 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1101 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1102 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1103 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1104 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1105 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1106 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1107 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1108 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1109 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1110 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
1111 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1112 { X86::SBB32rr, X86::SBB32rm, 0 },
1113 { X86::SBB64rr, X86::SBB64rm, 0 },
1114 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1115 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1116 { X86::SUB16rr, X86::SUB16rm, 0 },
1117 { X86::SUB32rr, X86::SUB32rm, 0 },
1118 { X86::SUB64rr, X86::SUB64rm, 0 },
1119 { X86::SUB8rr, X86::SUB8rm, 0 },
1120 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1121 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1122 { X86::SUBSDrr, X86::SUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1123 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1124 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1125 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1126 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1127 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1128 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1129 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1130 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1131 { X86::XOR16rr, X86::XOR16rm, 0 },
1132 { X86::XOR32rr, X86::XOR32rm, 0 },
1133 { X86::XOR64rr, X86::XOR64rm, 0 },
1134 { X86::XOR8rr, X86::XOR8rm, 0 },
1135 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1136 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1137
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]1138 // MMX version of foldable instructions
1139 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1140 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1141 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1142 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1143 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1144 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1145 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1146 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1147 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1148 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1149 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1150 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1151 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1152 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1153 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1154 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1155 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1156 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1157 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1158 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1159 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1160 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1161 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1162 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1163 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1164 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1165 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1166 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1167 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1168 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1169 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1170 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1171 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1172 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1173 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1174 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1175 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1176 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1177 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1178 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1179 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1180 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1181 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1182 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1183 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1184 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1185 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1186 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1187 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1188 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1189 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1190 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1191 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1192 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1193 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1194 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1195 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1196 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1197 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1198 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1199 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1200 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1201 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1202 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1203 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1204 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1205 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1206 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1207 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1208 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1209
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]1210 // 3DNow! version of foldable instructions
1211 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1212 { X86::PFACCrr, X86::PFACCrm, 0 },
1213 { X86::PFADDrr, X86::PFADDrm, 0 },
1214 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1215 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1216 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1217 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1218 { X86::PFMINrr, X86::PFMINrm, 0 },
1219 { X86::PFMULrr, X86::PFMULrm, 0 },
1220 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1221 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1222 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1223 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1224 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1225 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1226 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1227 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1228
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1229 // AVX 128-bit versions of foldable instructions
1230 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1231 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1232 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1233 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1234 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1235 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1236 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1237 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1238 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1239 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]1240 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1241 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1242 { X86::VRCPSSr, X86::VRCPSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1243 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1244 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1245 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1246 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1247 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1248 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1249 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1250 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1251 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1252 { X86::VADDSDrr, X86::VADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1253 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1254 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1255 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1256 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1257 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1258 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1259 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1260 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1261 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1262 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1263 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1264 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1265 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1266 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1267 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1268 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1269 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1270 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1271 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1272 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1273 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1274 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1275 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1276 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1277 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]1278 // Do not fold VFs* loads because there are no scalar load variants for
1279 // these instructions. When folded, the load is required to be 128-bits, so
1280 // the load size would not match.
1281 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 },
1282 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 },
1283 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 },
1284 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 },
1285 { X86::VFvORPDrr, X86::VFvORPDrm, 0 },
1286 { X86::VFvORPSrr, X86::VFvORPSrm, 0 },
1287 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 },
1288 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1289 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1290 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1291 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1292 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1293 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1294 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1295 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1296 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1297 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1298 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1299 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1300 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1301 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1302 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1303 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1304 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1305 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1306 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1307 { X86::VMOVLHPSrr, X86::VMOVHPSrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1308 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1309 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1310 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1311 { X86::VMULSDrr, X86::VMULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1312 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1313 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1314 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1315 { X86::VORPDrr, X86::VORPDrm, 0 },
1316 { X86::VORPSrr, X86::VORPSrm, 0 },
1317 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1318 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1319 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1320 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1321 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1322 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1323 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1324 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1325 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1326 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1327 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1328 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1329 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
1330 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1331 { X86::VPANDrr, X86::VPANDrm, 0 },
1332 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1333 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1334 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1335 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1336 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1337 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1338 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1339 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1340 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1341 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1342 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1343 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1344 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1345 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1346 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1347 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1348 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1349 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1350 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1351 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1352 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1353 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1354 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1355 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1356 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1357 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1358 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1359 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1360 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1361 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1362 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1363 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1364 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1365 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1366 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1367 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1368 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1369 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1370 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1371 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1372 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1373 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1374 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1375 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1376 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1377 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1378 { X86::VPORrr, X86::VPORrm, 0 },
1379 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1380 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1381 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, 0 },
1382 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, 0 },
1383 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1384 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1385 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1386 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1387 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1388 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1389 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1390 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1391 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1392 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1393 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1394 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1395 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1396 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1397 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1398 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1399 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1400 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1401 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1402 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1403 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1404 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1405 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1406 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1407 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1408 { X86::VPXORrr, X86::VPXORrm, 0 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1409 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1410 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1411 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1412 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1413 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1414 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1415 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1416 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1417 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1418 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1419 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1420 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1421 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1422 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1423 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1424 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1425
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1426 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1427 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1428 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1429 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1430 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1431 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1432 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1433 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1434 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1435 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1436 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1437 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1438 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1439 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1440 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1441 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1442 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1443 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1444 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1445 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1446 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1447 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1448 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1449 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1450 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1451 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1452 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1453 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1454 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1455 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1456 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1457 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1458 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1459 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1460 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1461 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1462 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1463 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1464 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1465 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1466 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1467 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1468 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1469 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1470
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1471 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1472 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1473 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1474 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1475 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1476 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1477 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1478 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1479 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1480 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1481 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1482 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1483 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1484 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1485 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1486 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1487 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1488 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1489 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1490 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1491 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1492 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1493 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1494 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1495 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1496 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1497 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1498 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1499 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1500 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1501 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1502 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1503 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1504 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1505 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1506 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1507 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1508 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1509 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1510 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1511 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1512 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1513 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1514 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1515 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1516 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1517 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1518 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1519 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1520 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1521 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1522 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1523 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1524 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1525 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1526 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1527 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1528 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1529 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1530 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1531 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1532 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1533 { X86::VPORYrr, X86::VPORYrm, 0 },
1534 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1535 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1536 { X86::VPSIGNBYrr256, X86::VPSIGNBYrm256, 0 },
1537 { X86::VPSIGNWYrr256, X86::VPSIGNWYrm256, 0 },
1538 { X86::VPSIGNDYrr256, X86::VPSIGNDYrm256, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1539 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1540 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1541 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1542 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1543 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1544 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1545 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1546 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1547 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1548 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1549 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1550 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1551 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1552 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1553 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1554 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1555 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1556 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1557 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1558 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1559 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1560 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1561 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1562 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1563 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1564 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1565 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1566 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1567 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1568 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1569 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1570 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1571 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1572 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1573 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1574
1575 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1576 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE },
1577 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE },
1578 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE },
1579 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE },
1580 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_NONE },
1581 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_NONE },
1582 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE },
1583 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE },
1584 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE },
1585 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE },
1586 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_NONE },
1587 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_NONE },
1588 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE },
1589 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE },
1590 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE },
1591 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE },
1592 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_NONE },
1593 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_NONE },
1594 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE },
1595 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE },
1596 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE },
1597 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE },
1598 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_NONE },
1599 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_NONE },
1600 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE },
1601 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE },
1602 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_NONE },
1603 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_NONE },
1604 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE },
1605 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE },
1606 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_NONE },
1607 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_NONE },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1608
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1609 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1610 { X86::VPCMOVrrr, X86::VPCMOVrmr, 0 },
1611 { X86::VPCMOVrrrY, X86::VPCMOVrmrY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1612 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1613 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1614 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1615 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1616 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1617 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1618 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1619 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1620 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1621 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1622 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1623 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1624 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1625 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1626 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1627 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1628 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1629 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1630 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1631 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1632 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1633 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1634 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1635 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1636 { X86::VPPERMrrr, X86::VPPERMrmr, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1637 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1638 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1639 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1640 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1641 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1642 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1643 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1644 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1645 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1646 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1647 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1648 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1649
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1650 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1651 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1652 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1653 { X86::MULX32rr, X86::MULX32rm, 0 },
1654 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1655 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1656 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1657 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1658 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1659
Simon Pilgrim4ba59692015-12-05 07:27:50 +0000[diff] [blame]1660 // ADX foldable instructions
1661 { X86::ADCX32rr, X86::ADCX32rm, 0 },
1662 { X86::ADCX64rr, X86::ADCX64rm, 0 },
1663 { X86::ADOX32rr, X86::ADOX32rm, 0 },
1664 { X86::ADOX64rr, X86::ADOX64rm, 0 },
1665
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1666 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1667 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1668 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1669 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1670 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1671 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1672 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1673 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1674 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1675 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1676 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1677 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1678 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1679 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1680 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1681 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1682 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1683 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1684 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1685 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1686 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1687 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1688 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1689 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1690 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1691 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1692 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1693 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1694 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1695 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1696 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1697 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1698 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1699 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1700 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
Igor Breger00d9f842015-06-08 14:03:17 +0000[diff] [blame]1701 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1702 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1703 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1704 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1705 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1706
1707 // AVX-512{F,VL} foldable instructions
1708 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1709 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1710 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1711
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1712 // AVX-512{F,VL} foldable instructions
1713 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1714 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1715 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1716 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1717
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1718 // AES foldable instructions
1719 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1720 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1721 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1722 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1723 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1724 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1725 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1726 { X86::VAESENCrr, X86::VAESENCrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1727
1728 // SHA foldable instructions
1729 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1730 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1731 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1732 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1733 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1734 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1735 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1736 };
1737
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1738 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1739 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1740 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1741 // Index 2, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1742 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1743 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1744
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1745 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1746 // FMA foldable instructions
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1747 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1748 { X86::VFMADDSSr231r_Int, X86::VFMADDSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1749 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1750 { X86::VFMADDSDr231r_Int, X86::VFMADDSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1751 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1752 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1753 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1754 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1755 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1756 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1757 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1758 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1759
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1760 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1761 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1762 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1763 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1764 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1765 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1766 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1767 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1768 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1769 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1770 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1771 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1772
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1773 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1774 { X86::VFNMADDSSr231r_Int, X86::VFNMADDSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1775 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1776 { X86::VFNMADDSDr231r_Int, X86::VFNMADDSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1777 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1778 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1779 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1780 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1781 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1782 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1783 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1784 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1785
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1786 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1787 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1788 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1789 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1790 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1791 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1792 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1793 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1794 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1795 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1796 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1797 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1798
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1799 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1800 { X86::VFMSUBSSr231r_Int, X86::VFMSUBSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1801 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1802 { X86::VFMSUBSDr231r_Int, X86::VFMSUBSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1803 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1804 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1805 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1806 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1807 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1808 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1809 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1810 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1811
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1812 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1813 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1814 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1815 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1816 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1817 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1818 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1819 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1820 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1821 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1822 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1823 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1824
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1825 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1826 { X86::VFNMSUBSSr231r_Int, X86::VFNMSUBSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1827 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1828 { X86::VFNMSUBSDr231r_Int, X86::VFNMSUBSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1829 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1830 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1831 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1832 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1833 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1834 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1835 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1836 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, TB_ALIGN_NONE },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1837
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1838 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1839 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1840 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1841 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1842 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1843 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1844 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1845 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1846 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1847 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1848 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1849 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1850
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1851 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1852 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1853 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1854 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1855 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1856 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1857 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1858 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1859 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1860 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1861 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1862 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1863
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1864 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1865 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1866 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1867 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1868 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1869 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1870 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1871 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1872 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1873 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1874 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1875 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1876
1877 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1878 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE },
1879 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE },
1880 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE },
1881 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE },
1882 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_NONE },
1883 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_NONE },
1884 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE },
1885 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE },
1886 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE },
1887 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE },
1888 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_NONE },
1889 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_NONE },
1890 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE },
1891 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE },
1892 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE },
1893 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE },
1894 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_NONE },
1895 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_NONE },
1896 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE },
1897 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE },
1898 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE },
1899 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE },
1900 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_NONE },
1901 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_NONE },
1902 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE },
1903 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE },
1904 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_NONE },
1905 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_NONE },
1906 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE },
1907 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE },
1908 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_NONE },
1909 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_NONE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1910
1911 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1912 { X86::VPCMOVrrr, X86::VPCMOVrrm, 0 },
1913 { X86::VPCMOVrrrY, X86::VPCMOVrrmY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1914 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1915 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1916 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1917 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1918 { X86::VPPERMrrr, X86::VPPERMrrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1919
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]1920 // AVX-512 VPERMI instructions with 3 source operands.
1921 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1922 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1923 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1924 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1925 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1926 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1927 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1928 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1929 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1930 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1931 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1932 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1933 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1934 // AVX-512 arithmetic instructions
1935 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1936 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1937 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1938 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1939 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1940 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1941 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1942 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1943 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1944 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1945 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1946 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1947 // AVX-512{F,VL} arithmetic instructions 256-bit
1948 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1949 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1950 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1951 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1952 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1953 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1954 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1955 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1956 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1957 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1958 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1959 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1960 // AVX-512{F,VL} arithmetic instructions 128-bit
1961 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1962 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1963 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1964 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1965 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1966 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1967 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1968 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1969 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1970 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1971 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1972 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1973 };
1974
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1975 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1976 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1977 Entry.RegOp, Entry.MemOp,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1978 // Index 3, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1979 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1980 }
1981
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1982 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1983 // AVX-512 foldable instructions
1984 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1985 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
1986 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
1987 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
1988 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
1989 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
1990 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
1991 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
1992 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
1993 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
1994 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
1995 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
1996 // AVX-512{F,VL} foldable instructions 256-bit
1997 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
1998 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
1999 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
2000 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
2001 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
2002 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
2003 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
2004 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
2005 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
2006 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
2007 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
2008 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
2009 // AVX-512{F,VL} foldable instructions 128-bit
2010 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
2011 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
2012 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
2013 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
2014 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
2015 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
2016 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
2017 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
2018 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
2019 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
2020 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
2021 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
2022 };
2023
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2024 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2025 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2026 Entry.RegOp, Entry.MemOp,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2027 // Index 4, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2028 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2029 }
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]2030}
2031
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2032void
2033X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2034 MemOp2RegOpTableType &M2RTable,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]2035 uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2036 if ((Flags & TB_NO_FORWARD) == 0) {
2037 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2038 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2039 }
2040 if ((Flags & TB_NO_REVERSE) == 0) {
2041 assert(!M2RTable.count(MemOp) &&
2042 "Duplicated entries in unfolding maps?");
2043 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2044 }
2045}
2046
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2047bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2048X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2049 unsigned &SrcReg, unsigned &DstReg,
2050 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2051 switch (MI.getOpcode()) {
2052 default: break;
2053 case X86::MOVSX16rr8:
2054 case X86::MOVZX16rr8:
2055 case X86::MOVSX32rr8:
2056 case X86::MOVZX32rr8:
2057 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2058 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]2059 // It's not always legal to reference the low 8-bit of the larger
2060 // register in 32-bit mode.
2061 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2062 case X86::MOVSX32rr16:
2063 case X86::MOVZX32rr16:
2064 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]2065 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2066 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2067 // Be conservative.
2068 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2069 SrcReg = MI.getOperand(1).getReg();
2070 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2071 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2072 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2073 case X86::MOVSX16rr8:
2074 case X86::MOVZX16rr8:
2075 case X86::MOVSX32rr8:
2076 case X86::MOVZX32rr8:
2077 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2078 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2079 break;
2080 case X86::MOVSX32rr16:
2081 case X86::MOVZX32rr16:
2082 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2083 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2084 break;
2085 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2086 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2087 break;
2088 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2089 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2090 }
2091 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2092 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2093}
2094
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2095int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
2096 const MachineFunction *MF = MI->getParent()->getParent();
2097 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2098
2099 if (MI->getOpcode() == getCallFrameSetupOpcode() ||
2100 MI->getOpcode() == getCallFrameDestroyOpcode()) {
2101 unsigned StackAlign = TFI->getStackAlignment();
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2102 int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2103 StackAlign;
2104
2105 SPAdj -= MI->getOperand(1).getImm();
2106
2107 if (MI->getOpcode() == getCallFrameSetupOpcode())
2108 return SPAdj;
2109 else
2110 return -SPAdj;
2111 }
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2112
2113 // To know whether a call adjusts the stack, we need information
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2114 // that is bound to the following ADJCALLSTACKUP pseudo.
2115 // Look for the next ADJCALLSTACKUP that follows the call.
2116 if (MI->isCall()) {
2117 const MachineBasicBlock* MBB = MI->getParent();
2118 auto I = ++MachineBasicBlock::const_iterator(MI);
2119 for (auto E = MBB->end(); I != E; ++I) {
2120 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2121 I->isCall())
2122 break;
2123 }
2124
2125 // If we could not find a frame destroy opcode, then it has already
2126 // been simplified, so we don't care.
2127 if (I->getOpcode() != getCallFrameDestroyOpcode())
2128 return 0;
2129
2130 return -(I->getOperand(1).getImm());
2131 }
2132
2133 // Currently handle only PUSHes we can reasonably expect to see
2134 // in call sequences
2135 switch (MI->getOpcode()) {
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2136 default:
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2137 return 0;
2138 case X86::PUSH32i8:
2139 case X86::PUSH32r:
2140 case X86::PUSH32rmm:
2141 case X86::PUSH32rmr:
2142 case X86::PUSHi32:
2143 return 4;
David L Kreitzer0fe46322016-05-02 13:45:25 +0000[diff] [blame^]2144 case X86::PUSH64i8:
2145 case X86::PUSH64r:
2146 case X86::PUSH64rmm:
2147 case X86::PUSH64rmr:
2148 case X86::PUSH64i32:
2149 return 8;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2150 }
2151}
2152
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2153/// Return true and the FrameIndex if the specified
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2154/// operand and follow operands form a reference to the stack frame.
2155bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2156 int &FrameIndex) const {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2157 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2158 MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2159 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2160 MI->getOperand(Op+X86::AddrDisp).isImm() &&
2161 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2162 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2163 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2164 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2165 return true;
2166 }
2167 return false;
2168}
2169
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2170static bool isFrameLoadOpcode(int Opcode) {
2171 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]2172 default:
2173 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2174 case X86::MOV8rm:
2175 case X86::MOV16rm:
2176 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]2177 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]2178 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2179 case X86::MOVSSrm:
2180 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2181 case X86::MOVAPSrm:
2182 case X86::MOVAPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]2183 case X86::MOVDQArm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2184 case X86::VMOVSSrm:
2185 case X86::VMOVSDrm:
2186 case X86::VMOVAPSrm:
2187 case X86::VMOVAPDrm:
2188 case X86::VMOVDQArm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2189 case X86::VMOVUPSYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2190 case X86::VMOVAPSYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2191 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2192 case X86::VMOVAPDYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2193 case X86::VMOVDQUYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2194 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]2195 case X86::MMX_MOVD64rm:
2196 case X86::MMX_MOVQ64rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2197 case X86::VMOVAPSZrm:
2198 case X86::VMOVUPSZrm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2199 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2200 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2201}
2202
2203static bool isFrameStoreOpcode(int Opcode) {
2204 switch (Opcode) {
2205 default: break;
2206 case X86::MOV8mr:
2207 case X86::MOV16mr:
2208 case X86::MOV32mr:
2209 case X86::MOV64mr:
2210 case X86::ST_FpP64m:
2211 case X86::MOVSSmr:
2212 case X86::MOVSDmr:
2213 case X86::MOVAPSmr:
2214 case X86::MOVAPDmr:
2215 case X86::MOVDQAmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2216 case X86::VMOVSSmr:
2217 case X86::VMOVSDmr:
2218 case X86::VMOVAPSmr:
2219 case X86::VMOVAPDmr:
2220 case X86::VMOVDQAmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2221 case X86::VMOVUPSYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2222 case X86::VMOVAPSYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2223 case X86::VMOVUPDYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2224 case X86::VMOVAPDYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2225 case X86::VMOVDQUYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2226 case X86::VMOVDQAYmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2227 case X86::VMOVUPSZmr:
2228 case X86::VMOVAPSZmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2229 case X86::MMX_MOVD64mr:
2230 case X86::MMX_MOVQ64mr:
2231 case X86::MMX_MOVNTQmr:
2232 return true;
2233 }
2234 return false;
2235}
2236
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2237unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2238 int &FrameIndex) const {
2239 if (isFrameLoadOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2240 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2241 return MI->getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2242 return 0;
2243}
2244
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2245unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2246 int &FrameIndex) const {
2247 if (isFrameLoadOpcode(MI->getOpcode())) {
2248 unsigned Reg;
2249 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2250 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2251 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2252 const MachineMemOperand *Dummy;
2253 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2254 }
2255 return 0;
2256}
2257
Dan Gohman0b273252008-11-18 19:49:32 +0000[diff] [blame]2258unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2259 int &FrameIndex) const {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2260 if (isFrameStoreOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2261 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2262 isFrameOperand(MI, 0, FrameIndex))
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]2263 return MI->getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2264 return 0;
2265}
2266
2267unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2268 int &FrameIndex) const {
2269 if (isFrameStoreOpcode(MI->getOpcode())) {
2270 unsigned Reg;
2271 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2272 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2273 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2274 const MachineMemOperand *Dummy;
2275 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2276 }
2277 return 0;
2278}
2279
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2280/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2281static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]2282 // Don't waste compile time scanning use-def chains of physregs.
2283 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2284 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2285 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]2286 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2287 E = MRI.def_instr_end(); I != E; ++I) {
2288 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2289 if (DefMI->getOpcode() != X86::MOVPC32r)
2290 return false;
2291 assert(!isPICBase && "More than one PIC base?");
2292 isPICBase = true;
2293 }
2294 return isPICBase;
2295}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]2296
Bill Wendling1e117682008-05-12 20:54:26 +0000[diff] [blame]2297bool
Dan Gohmane919de52009-10-10 00:34:18 +0000[diff] [blame]2298X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2299 AliasAnalysis *AA) const {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2300 switch (MI->getOpcode()) {
2301 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2302 case X86::MOV8rm:
2303 case X86::MOV16rm:
2304 case X86::MOV32rm:
2305 case X86::MOV64rm:
2306 case X86::LD_Fp64m:
2307 case X86::MOVSSrm:
2308 case X86::MOVSDrm:
2309 case X86::MOVAPSrm:
2310 case X86::MOVUPSrm:
2311 case X86::MOVAPDrm:
2312 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2313 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2314 case X86::VMOVSSrm:
2315 case X86::VMOVSDrm:
2316 case X86::VMOVAPSrm:
2317 case X86::VMOVUPSrm:
2318 case X86::VMOVAPDrm:
2319 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2320 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2321 case X86::VMOVAPSYrm:
2322 case X86::VMOVUPSYrm:
2323 case X86::VMOVAPDYrm:
2324 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2325 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2326 case X86::MMX_MOVD64rm:
2327 case X86::MMX_MOVQ64rm:
2328 case X86::FsVMOVAPSrm:
2329 case X86::FsVMOVAPDrm:
2330 case X86::FsMOVAPSrm:
Igor Bregerf8e461f2015-10-26 08:37:12 +0000[diff] [blame]2331 case X86::FsMOVAPDrm:
2332 // AVX-512
2333 case X86::VMOVAPDZ128rm:
2334 case X86::VMOVAPDZ256rm:
2335 case X86::VMOVAPDZrm:
2336 case X86::VMOVAPSZ128rm:
2337 case X86::VMOVAPSZ256rm:
2338 case X86::VMOVAPSZrm:
2339 case X86::VMOVDQA32Z128rm:
2340 case X86::VMOVDQA32Z256rm:
2341 case X86::VMOVDQA32Zrm:
2342 case X86::VMOVDQA64Z128rm:
2343 case X86::VMOVDQA64Z256rm:
2344 case X86::VMOVDQA64Zrm:
2345 case X86::VMOVDQU16Z128rm:
2346 case X86::VMOVDQU16Z256rm:
2347 case X86::VMOVDQU16Zrm:
2348 case X86::VMOVDQU32Z128rm:
2349 case X86::VMOVDQU32Z256rm:
2350 case X86::VMOVDQU32Zrm:
2351 case X86::VMOVDQU64Z128rm:
2352 case X86::VMOVDQU64Z256rm:
2353 case X86::VMOVDQU64Zrm:
2354 case X86::VMOVDQU8Z128rm:
2355 case X86::VMOVDQU8Z256rm:
2356 case X86::VMOVDQU8Zrm:
2357 case X86::VMOVUPSZ128rm:
2358 case X86::VMOVUPSZ256rm:
2359 case X86::VMOVUPSZrm: {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2360 // Loads from constant pools are trivially rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2361 if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2362 MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2363 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2364 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2365 MI->isInvariantLoad(AA)) {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2366 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2367 if (BaseReg == 0 || BaseReg == X86::RIP)
2368 return true;
2369 // Allow re-materialization of PIC load.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2370 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2371 return false;
2372 const MachineFunction &MF = *MI->getParent()->getParent();
2373 const MachineRegisterInfo &MRI = MF.getRegInfo();
2374 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]2375 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2376 return false;
2377 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2378
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2379 case X86::LEA32r:
2380 case X86::LEA64r: {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2381 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2382 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2383 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2384 !MI->getOperand(1+X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2385 // lea fi#, lea GV, etc. are all rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2386 if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2387 return true;
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2388 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2389 if (BaseReg == 0)
2390 return true;
2391 // Allow re-materialization of lea PICBase + x.
2392 const MachineFunction &MF = *MI->getParent()->getParent();
2393 const MachineRegisterInfo &MRI = MF.getRegInfo();
2394 return regIsPICBase(BaseReg, MRI);
2395 }
2396 return false;
2397 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2398 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]2399
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]2400 // All other instructions marked M_REMATERIALIZABLE are always trivially
2401 // rematerializable.
2402 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2403}
2404
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]2405bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2406 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2407 MachineBasicBlock::iterator E = MBB.end();
2408
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2409 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2410 // safety after visiting 4 instructions in each direction, we will assume
2411 // it's not safe.
2412 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2413 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2414 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2415 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2416 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2417 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2418 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2419 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2420 continue;
2421 if (MO.getReg() == X86::EFLAGS) {
2422 if (MO.isUse())
2423 return false;
2424 SeenDef = true;
2425 }
2426 }
2427
2428 if (SeenDef)
2429 // This instruction defines EFLAGS, no need to look any further.
2430 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2431 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2432 // Skip over DBG_VALUE.
2433 while (Iter != E && Iter->isDebugValue())
2434 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2435 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2436
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2437 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2438 // live in.
2439 if (Iter == E) {
Craig Topperca66fc52015-12-20 18:41:57 +0000[diff] [blame]2440 for (MachineBasicBlock *S : MBB.successors())
2441 if (S->isLiveIn(X86::EFLAGS))
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2442 return false;
2443 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2444 }
2445
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2446 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2447 Iter = I;
2448 for (unsigned i = 0; i < 4; ++i) {
2449 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]2450 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2451 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2452 return !MBB.isLiveIn(X86::EFLAGS);
2453
2454 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2455 // Skip over DBG_VALUE.
2456 while (Iter != B && Iter->isDebugValue())
2457 --Iter;
2458
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2459 bool SawKill = false;
2460 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2461 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2462 // A register mask may clobber EFLAGS, but we should still look for a
2463 // live EFLAGS def.
2464 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2465 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2466 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2467 if (MO.isDef()) return MO.isDead();
2468 if (MO.isKill()) SawKill = true;
2469 }
2470 }
2471
2472 if (SawKill)
2473 // This instruction kills EFLAGS and doesn't redefine it, so
2474 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2475 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2476 }
2477
2478 // Conservative answer.
2479 return false;
2480}
2481
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2482void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2483 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2484 unsigned DestReg, unsigned SubIdx,
Evan Cheng6ad7da92009-11-14 02:55:43 +0000[diff] [blame]2485 const MachineInstr *Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2486 const TargetRegisterInfo &TRI) const {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2487 bool ClobbersEFLAGS = false;
2488 for (const MachineOperand &MO : Orig->operands()) {
2489 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2490 ClobbersEFLAGS = true;
2491 break;
2492 }
2493 }
2494
2495 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2496 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2497 // effects.
2498 int Value;
2499 switch (Orig->getOpcode()) {
2500 case X86::MOV32r0: Value = 0; break;
2501 case X86::MOV32r1: Value = 1; break;
2502 case X86::MOV32r_1: Value = -1; break;
2503 default:
2504 llvm_unreachable("Unexpected instruction!");
2505 }
2506
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2507 DebugLoc DL = Orig->getDebugLoc();
2508 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2509 .addImm(Value);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2510 } else {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2511 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2512 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2513 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]2514
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2515 MachineInstr *NewMI = std::prev(I);
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2516 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2517}
2518
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2519/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
Andrew Kayloraf083d42015-08-26 20:36:52 +0000[diff] [blame]2520bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr *MI) const {
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2521 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2522 MachineOperand &MO = MI->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2523 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2524 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2525 return true;
2526 }
2527 }
2528 return false;
2529}
2530
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2531/// Check whether the shift count for a machine operand is non-zero.
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2532inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2533 unsigned ShiftAmtOperandIdx) {
2534 // The shift count is six bits with the REX.W prefix and five bits without.
2535 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2536 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2537 return Imm & ShiftCountMask;
2538}
2539
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2540/// Check whether the given shift count is appropriate
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2541/// can be represented by a LEA instruction.
2542inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2543 // Left shift instructions can be transformed into load-effective-address
2544 // instructions if we can encode them appropriately.
Sanjay Pateldc87d142015-08-12 15:09:09 +0000[diff] [blame]2545 // A LEA instruction utilizes a SIB byte to encode its scale factor.
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2546 // The SIB.scale field is two bits wide which means that we can encode any
2547 // shift amount less than 4.
2548 return ShAmt < 4 && ShAmt > 0;
2549}
2550
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2551bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2552 unsigned Opc, bool AllowSP,
2553 unsigned &NewSrc, bool &isKill, bool &isUndef,
2554 MachineOperand &ImplicitOp) const {
2555 MachineFunction &MF = *MI->getParent()->getParent();
2556 const TargetRegisterClass *RC;
2557 if (AllowSP) {
2558 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2559 } else {
2560 RC = Opc != X86::LEA32r ?
2561 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2562 }
2563 unsigned SrcReg = Src.getReg();
2564
2565 // For both LEA64 and LEA32 the register already has essentially the right
2566 // type (32-bit or 64-bit) we may just need to forbid SP.
2567 if (Opc != X86::LEA64_32r) {
2568 NewSrc = SrcReg;
2569 isKill = Src.isKill();
2570 isUndef = Src.isUndef();
2571
2572 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2573 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2574 return false;
2575
2576 return true;
2577 }
2578
2579 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2580 // another we need to add 64-bit registers to the final MI.
2581 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2582 ImplicitOp = Src;
2583 ImplicitOp.setImplicit();
2584
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]2585 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2586 MachineBasicBlock::LivenessQueryResult LQR =
2587 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2588
2589 switch (LQR) {
2590 case MachineBasicBlock::LQR_Unknown:
2591 // We can't give sane liveness flags to the instruction, abandon LEA
2592 // formation.
2593 return false;
2594 case MachineBasicBlock::LQR_Live:
2595 isKill = MI->killsRegister(SrcReg);
2596 isUndef = false;
2597 break;
2598 default:
2599 // The physreg itself is dead, so we have to use it as an <undef>.
2600 isKill = false;
2601 isUndef = true;
2602 break;
2603 }
2604 } else {
2605 // Virtual register of the wrong class, we have to create a temporary 64-bit
2606 // vreg to feed into the LEA.
2607 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2608 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2609 get(TargetOpcode::COPY))
2610 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2611 .addOperand(Src);
2612
2613 // Which is obviously going to be dead after we're done with it.
2614 isKill = true;
2615 isUndef = false;
2616 }
2617
2618 // We've set all the parameters without issue.
2619 return true;
2620}
2621
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2622/// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2623/// LEA to form 3-address code by promoting to a 32-bit superregister and then
2624/// truncating back down to a 16-bit subregister.
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2625MachineInstr *
2626X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2627 MachineFunction::iterator &MFI,
2628 MachineBasicBlock::iterator &MBBI,
2629 LiveVariables *LV) const {
2630 MachineInstr *MI = MBBI;
2631 unsigned Dest = MI->getOperand(0).getReg();
2632 unsigned Src = MI->getOperand(1).getReg();
2633 bool isDead = MI->getOperand(0).isDead();
2634 bool isKill = MI->getOperand(1).isKill();
2635
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2636 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2637 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2638 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2639 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2640 Opc = X86::LEA64_32r;
2641 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2642 } else {
2643 Opc = X86::LEA32r;
2644 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2645 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2646
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2647 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2648 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2649 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2650 // movw (%rbp,%rcx,2), %dx
2651 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2652 // But testing has shown this *does* help performance in 64-bit mode (at
2653 // least on modern x86 machines).
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2654 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2655 MachineInstr *InsMI =
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2656 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2657 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2658 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2659
2660 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2661 get(Opc), leaOutReg);
2662 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2663 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2664 case X86::SHL16ri: {
2665 unsigned ShAmt = MI->getOperand(2).getImm();
Aaron Ballmanef0fe1e2016-03-30 21:30:00 +0000[diff] [blame]2666 MIB.addReg(0).addImm(1ULL << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2667 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2668 break;
2669 }
2670 case X86::INC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2671 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2672 break;
2673 case X86::DEC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2674 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2675 break;
2676 case X86::ADD16ri:
2677 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2678 case X86::ADD16ri_DB:
2679 case X86::ADD16ri8_DB:
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2680 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2681 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2682 case X86::ADD16rr:
2683 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2684 unsigned Src2 = MI->getOperand(2).getReg();
2685 bool isKill2 = MI->getOperand(2).isKill();
2686 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2687 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2688 if (Src == Src2) {
2689 // ADD16rr %reg1028<kill>, %reg1028
2690 // just a single insert_subreg.
2691 addRegReg(MIB, leaInReg, true, leaInReg, false);
2692 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2693 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2694 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2695 else
2696 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2697 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2698 // well be shifting and then extracting the lower 16-bits.
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2699 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2700 InsMI2 =
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2701 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2702 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2703 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2704 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2705 }
2706 if (LV && isKill2 && InsMI2)
2707 LV->replaceKillInstruction(Src2, MI, InsMI2);
2708 break;
2709 }
2710 }
2711
2712 MachineInstr *NewMI = MIB;
2713 MachineInstr *ExtMI =
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2714 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2715 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2716 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2717
2718 if (LV) {
2719 // Update live variables
2720 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2721 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2722 if (isKill)
2723 LV->replaceKillInstruction(Src, MI, InsMI);
2724 if (isDead)
2725 LV->replaceKillInstruction(Dest, MI, ExtMI);
2726 }
2727
2728 return ExtMI;
2729}
2730
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2731/// This method must be implemented by targets that
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2732/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2733/// may be able to convert a two-address instruction into a true
2734/// three-address instruction on demand. This allows the X86 target (for
2735/// example) to convert ADD and SHL instructions into LEA instructions if they
2736/// would require register copies due to two-addressness.
2737///
2738/// This method returns a null pointer if the transformation cannot be
2739/// performed, otherwise it returns the new instruction.
2740///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2741MachineInstr *
2742X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2743 MachineBasicBlock::iterator &MBBI,
Owen Anderson30cc0282008-07-02 23:41:07 +0000[diff] [blame]2744 LiveVariables *LV) const {
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2745 MachineInstr *MI = MBBI;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2746
2747 // The following opcodes also sets the condition code register(s). Only
2748 // convert them to equivalent lea if the condition code register def's
2749 // are dead!
2750 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2751 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2752
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2753 MachineFunction &MF = *MI->getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2754 // All instructions input are two-addr instructions. Get the known operands.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2755 const MachineOperand &Dest = MI->getOperand(0);
2756 const MachineOperand &Src = MI->getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2757
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2758 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2759 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2760 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2761 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2762 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2763 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2764
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2765 unsigned MIOpc = MI->getOpcode();
2766 switch (MIOpc) {
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2767 default: return nullptr;
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2768 case X86::SHL64ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2769 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2770 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2771 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2772
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2773 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2774 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2775 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2776 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2777 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2778
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2779 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2780 .addOperand(Dest)
Aaron Ballmanef0fe1e2016-03-30 21:30:00 +0000[diff] [blame]2781 .addReg(0).addImm(1ULL << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2782 break;
2783 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2784 case X86::SHL32ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2785 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2786 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2787 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2788
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2789 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2790
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2791 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2792 bool isKill, isUndef;
2793 unsigned SrcReg;
2794 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2795 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2796 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2797 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2798
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2799 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2800 .addOperand(Dest)
Aaron Ballmanef0fe1e2016-03-30 21:30:00 +0000[diff] [blame]2801 .addReg(0).addImm(1ULL << ShAmt)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2802 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2803 .addImm(0).addReg(0);
2804 if (ImplicitOp.getReg() != 0)
2805 MIB.addOperand(ImplicitOp);
2806 NewMI = MIB;
2807
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2808 break;
2809 }
2810 case X86::SHL16ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2811 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2812 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2813 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2814
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2815 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2816 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2817 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2818 .addOperand(Dest)
Aaron Ballmanef0fe1e2016-03-30 21:30:00 +0000[diff] [blame]2819 .addReg(0).addImm(1ULL << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2820 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2821 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2822 case X86::INC64r:
2823 case X86::INC32r: {
2824 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2825 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2826 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2827 bool isKill, isUndef;
2828 unsigned SrcReg;
2829 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2830 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2831 SrcReg, isKill, isUndef, ImplicitOp))
2832 return nullptr;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2833
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2834 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2835 .addOperand(Dest)
2836 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2837 if (ImplicitOp.getReg() != 0)
2838 MIB.addOperand(ImplicitOp);
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2839
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2840 NewMI = addOffset(MIB, 1);
2841 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2842 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2843 case X86::INC16r:
2844 if (DisableLEA16)
2845 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2846 : nullptr;
2847 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2848 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2849 .addOperand(Dest).addOperand(Src), 1);
2850 break;
2851 case X86::DEC64r:
2852 case X86::DEC32r: {
2853 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2854 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2855 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2856
2857 bool isKill, isUndef;
2858 unsigned SrcReg;
2859 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2860 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2861 SrcReg, isKill, isUndef, ImplicitOp))
2862 return nullptr;
2863
2864 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2865 .addOperand(Dest)
2866 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2867 if (ImplicitOp.getReg() != 0)
2868 MIB.addOperand(ImplicitOp);
2869
2870 NewMI = addOffset(MIB, -1);
2871
2872 break;
2873 }
2874 case X86::DEC16r:
2875 if (DisableLEA16)
2876 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2877 : nullptr;
2878 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2879 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2880 .addOperand(Dest).addOperand(Src), -1);
2881 break;
2882 case X86::ADD64rr:
2883 case X86::ADD64rr_DB:
2884 case X86::ADD32rr:
2885 case X86::ADD32rr_DB: {
2886 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2887 unsigned Opc;
2888 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2889 Opc = X86::LEA64r;
2890 else
2891 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2892
2893 bool isKill, isUndef;
2894 unsigned SrcReg;
2895 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2896 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2897 SrcReg, isKill, isUndef, ImplicitOp))
2898 return nullptr;
2899
2900 const MachineOperand &Src2 = MI->getOperand(2);
2901 bool isKill2, isUndef2;
2902 unsigned SrcReg2;
2903 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2904 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2905 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2906 return nullptr;
2907
2908 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2909 .addOperand(Dest);
2910 if (ImplicitOp.getReg() != 0)
2911 MIB.addOperand(ImplicitOp);
2912 if (ImplicitOp2.getReg() != 0)
2913 MIB.addOperand(ImplicitOp2);
2914
2915 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2916
2917 // Preserve undefness of the operands.
2918 NewMI->getOperand(1).setIsUndef(isUndef);
2919 NewMI->getOperand(3).setIsUndef(isUndef2);
2920
2921 if (LV && Src2.isKill())
2922 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2923 break;
2924 }
2925 case X86::ADD16rr:
2926 case X86::ADD16rr_DB: {
2927 if (DisableLEA16)
2928 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2929 : nullptr;
2930 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2931 unsigned Src2 = MI->getOperand(2).getReg();
2932 bool isKill2 = MI->getOperand(2).isKill();
2933 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2934 .addOperand(Dest),
2935 Src.getReg(), Src.isKill(), Src2, isKill2);
2936
2937 // Preserve undefness of the operands.
2938 bool isUndef = MI->getOperand(1).isUndef();
2939 bool isUndef2 = MI->getOperand(2).isUndef();
2940 NewMI->getOperand(1).setIsUndef(isUndef);
2941 NewMI->getOperand(3).setIsUndef(isUndef2);
2942
2943 if (LV && isKill2)
2944 LV->replaceKillInstruction(Src2, MI, NewMI);
2945 break;
2946 }
2947 case X86::ADD64ri32:
2948 case X86::ADD64ri8:
2949 case X86::ADD64ri32_DB:
2950 case X86::ADD64ri8_DB:
2951 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2952 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2953 .addOperand(Dest).addOperand(Src),
2954 MI->getOperand(2).getImm());
2955 break;
2956 case X86::ADD32ri:
2957 case X86::ADD32ri8:
2958 case X86::ADD32ri_DB:
2959 case X86::ADD32ri8_DB: {
2960 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2961 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2962
2963 bool isKill, isUndef;
2964 unsigned SrcReg;
2965 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2966 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2967 SrcReg, isKill, isUndef, ImplicitOp))
2968 return nullptr;
2969
2970 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2971 .addOperand(Dest)
2972 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2973 if (ImplicitOp.getReg() != 0)
2974 MIB.addOperand(ImplicitOp);
2975
2976 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2977 break;
2978 }
2979 case X86::ADD16ri:
2980 case X86::ADD16ri8:
2981 case X86::ADD16ri_DB:
2982 case X86::ADD16ri8_DB:
2983 if (DisableLEA16)
2984 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2985 : nullptr;
2986 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2987 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2988 .addOperand(Dest).addOperand(Src),
2989 MI->getOperand(2).getImm());
2990 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2991 }
2992
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2993 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]2994
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2995 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2996 if (Src.isKill())
2997 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2998 if (Dest.isDead())
2999 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3000 }
3001
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3002 MFI->insert(MBBI, NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]3003 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3004}
3005
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3006/// Returns true if the given instruction opcode is FMA3.
3007/// Otherwise, returns false.
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3008/// The second parameter is optional and is used as the second return from
3009/// the function. It is set to true if the given instruction has FMA3 opcode
3010/// that is used for lowering of scalar FMA intrinsics, and it is set to false
3011/// otherwise.
3012static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
3013 if (IsIntrinsic)
3014 *IsIntrinsic = false;
3015
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3016 switch (Opcode) {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3017 case X86::VFMADDSDr132r: case X86::VFMADDSDr132m:
3018 case X86::VFMADDSSr132r: case X86::VFMADDSSr132m:
3019 case X86::VFMSUBSDr132r: case X86::VFMSUBSDr132m:
3020 case X86::VFMSUBSSr132r: case X86::VFMSUBSSr132m:
3021 case X86::VFNMADDSDr132r: case X86::VFNMADDSDr132m:
3022 case X86::VFNMADDSSr132r: case X86::VFNMADDSSr132m:
3023 case X86::VFNMSUBSDr132r: case X86::VFNMSUBSDr132m:
3024 case X86::VFNMSUBSSr132r: case X86::VFNMSUBSSr132m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3025
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3026 case X86::VFMADDSDr213r: case X86::VFMADDSDr213m:
3027 case X86::VFMADDSSr213r: case X86::VFMADDSSr213m:
3028 case X86::VFMSUBSDr213r: case X86::VFMSUBSDr213m:
3029 case X86::VFMSUBSSr213r: case X86::VFMSUBSSr213m:
3030 case X86::VFNMADDSDr213r: case X86::VFNMADDSDr213m:
3031 case X86::VFNMADDSSr213r: case X86::VFNMADDSSr213m:
3032 case X86::VFNMSUBSDr213r: case X86::VFNMSUBSDr213m:
3033 case X86::VFNMSUBSSr213r: case X86::VFNMSUBSSr213m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3034
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3035 case X86::VFMADDSDr231r: case X86::VFMADDSDr231m:
3036 case X86::VFMADDSSr231r: case X86::VFMADDSSr231m:
3037 case X86::VFMSUBSDr231r: case X86::VFMSUBSDr231m:
3038 case X86::VFMSUBSSr231r: case X86::VFMSUBSSr231m:
3039 case X86::VFNMADDSDr231r: case X86::VFNMADDSDr231m:
3040 case X86::VFNMADDSSr231r: case X86::VFNMADDSSr231m:
3041 case X86::VFNMSUBSDr231r: case X86::VFNMSUBSDr231m:
3042 case X86::VFNMSUBSSr231r: case X86::VFNMSUBSSr231m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3043
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3044 case X86::VFMADDSUBPDr132r: case X86::VFMADDSUBPDr132m:
3045 case X86::VFMADDSUBPSr132r: case X86::VFMADDSUBPSr132m:
3046 case X86::VFMSUBADDPDr132r: case X86::VFMSUBADDPDr132m:
3047 case X86::VFMSUBADDPSr132r: case X86::VFMSUBADDPSr132m:
3048 case X86::VFMADDSUBPDr132rY: case X86::VFMADDSUBPDr132mY:
3049 case X86::VFMADDSUBPSr132rY: case X86::VFMADDSUBPSr132mY:
3050 case X86::VFMSUBADDPDr132rY: case X86::VFMSUBADDPDr132mY:
3051 case X86::VFMSUBADDPSr132rY: case X86::VFMSUBADDPSr132mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3052
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3053 case X86::VFMADDPDr132r: case X86::VFMADDPDr132m:
3054 case X86::VFMADDPSr132r: case X86::VFMADDPSr132m:
3055 case X86::VFMSUBPDr132r: case X86::VFMSUBPDr132m:
3056 case X86::VFMSUBPSr132r: case X86::VFMSUBPSr132m:
3057 case X86::VFNMADDPDr132r: case X86::VFNMADDPDr132m:
3058 case X86::VFNMADDPSr132r: case X86::VFNMADDPSr132m:
3059 case X86::VFNMSUBPDr132r: case X86::VFNMSUBPDr132m:
3060 case X86::VFNMSUBPSr132r: case X86::VFNMSUBPSr132m:
3061 case X86::VFMADDPDr132rY: case X86::VFMADDPDr132mY:
3062 case X86::VFMADDPSr132rY: case X86::VFMADDPSr132mY:
3063 case X86::VFMSUBPDr132rY: case X86::VFMSUBPDr132mY:
3064 case X86::VFMSUBPSr132rY: case X86::VFMSUBPSr132mY:
3065 case X86::VFNMADDPDr132rY: case X86::VFNMADDPDr132mY:
3066 case X86::VFNMADDPSr132rY: case X86::VFNMADDPSr132mY:
3067 case X86::VFNMSUBPDr132rY: case X86::VFNMSUBPDr132mY:
3068 case X86::VFNMSUBPSr132rY: case X86::VFNMSUBPSr132mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3069
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3070 case X86::VFMADDSUBPDr213r: case X86::VFMADDSUBPDr213m:
3071 case X86::VFMADDSUBPSr213r: case X86::VFMADDSUBPSr213m:
3072 case X86::VFMSUBADDPDr213r: case X86::VFMSUBADDPDr213m:
3073 case X86::VFMSUBADDPSr213r: case X86::VFMSUBADDPSr213m:
3074 case X86::VFMADDSUBPDr213rY: case X86::VFMADDSUBPDr213mY:
3075 case X86::VFMADDSUBPSr213rY: case X86::VFMADDSUBPSr213mY:
3076 case X86::VFMSUBADDPDr213rY: case X86::VFMSUBADDPDr213mY:
3077 case X86::VFMSUBADDPSr213rY: case X86::VFMSUBADDPSr213mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3078
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3079 case X86::VFMADDPDr213r: case X86::VFMADDPDr213m:
3080 case X86::VFMADDPSr213r: case X86::VFMADDPSr213m:
3081 case X86::VFMSUBPDr213r: case X86::VFMSUBPDr213m:
3082 case X86::VFMSUBPSr213r: case X86::VFMSUBPSr213m:
3083 case X86::VFNMADDPDr213r: case X86::VFNMADDPDr213m:
3084 case X86::VFNMADDPSr213r: case X86::VFNMADDPSr213m:
3085 case X86::VFNMSUBPDr213r: case X86::VFNMSUBPDr213m:
3086 case X86::VFNMSUBPSr213r: case X86::VFNMSUBPSr213m:
3087 case X86::VFMADDPDr213rY: case X86::VFMADDPDr213mY:
3088 case X86::VFMADDPSr213rY: case X86::VFMADDPSr213mY:
3089 case X86::VFMSUBPDr213rY: case X86::VFMSUBPDr213mY:
3090 case X86::VFMSUBPSr213rY: case X86::VFMSUBPSr213mY:
3091 case X86::VFNMADDPDr213rY: case X86::VFNMADDPDr213mY:
3092 case X86::VFNMADDPSr213rY: case X86::VFNMADDPSr213mY:
3093 case X86::VFNMSUBPDr213rY: case X86::VFNMSUBPDr213mY:
3094 case X86::VFNMSUBPSr213rY: case X86::VFNMSUBPSr213mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3095
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3096 case X86::VFMADDSUBPDr231r: case X86::VFMADDSUBPDr231m:
3097 case X86::VFMADDSUBPSr231r: case X86::VFMADDSUBPSr231m:
3098 case X86::VFMSUBADDPDr231r: case X86::VFMSUBADDPDr231m:
3099 case X86::VFMSUBADDPSr231r: case X86::VFMSUBADDPSr231m:
3100 case X86::VFMADDSUBPDr231rY: case X86::VFMADDSUBPDr231mY:
3101 case X86::VFMADDSUBPSr231rY: case X86::VFMADDSUBPSr231mY:
3102 case X86::VFMSUBADDPDr231rY: case X86::VFMSUBADDPDr231mY:
3103 case X86::VFMSUBADDPSr231rY: case X86::VFMSUBADDPSr231mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3104
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3105 case X86::VFMADDPDr231r: case X86::VFMADDPDr231m:
3106 case X86::VFMADDPSr231r: case X86::VFMADDPSr231m:
3107 case X86::VFMSUBPDr231r: case X86::VFMSUBPDr231m:
3108 case X86::VFMSUBPSr231r: case X86::VFMSUBPSr231m:
3109 case X86::VFNMADDPDr231r: case X86::VFNMADDPDr231m:
3110 case X86::VFNMADDPSr231r: case X86::VFNMADDPSr231m:
3111 case X86::VFNMSUBPDr231r: case X86::VFNMSUBPDr231m:
3112 case X86::VFNMSUBPSr231r: case X86::VFNMSUBPSr231m:
3113 case X86::VFMADDPDr231rY: case X86::VFMADDPDr231mY:
3114 case X86::VFMADDPSr231rY: case X86::VFMADDPSr231mY:
3115 case X86::VFMSUBPDr231rY: case X86::VFMSUBPDr231mY:
3116 case X86::VFMSUBPSr231rY: case X86::VFMSUBPSr231mY:
3117 case X86::VFNMADDPDr231rY: case X86::VFNMADDPDr231mY:
3118 case X86::VFNMADDPSr231rY: case X86::VFNMADDPSr231mY:
3119 case X86::VFNMSUBPDr231rY: case X86::VFNMSUBPDr231mY:
3120 case X86::VFNMSUBPSr231rY: case X86::VFNMSUBPSr231mY:
3121 return true;
3122
3123 case X86::VFMADDSDr132r_Int: case X86::VFMADDSDr132m_Int:
3124 case X86::VFMADDSSr132r_Int: case X86::VFMADDSSr132m_Int:
3125 case X86::VFMSUBSDr132r_Int: case X86::VFMSUBSDr132m_Int:
3126 case X86::VFMSUBSSr132r_Int: case X86::VFMSUBSSr132m_Int:
3127 case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int:
3128 case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int:
3129 case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int:
3130 case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int:
3131
3132 case X86::VFMADDSDr213r_Int: case X86::VFMADDSDr213m_Int:
3133 case X86::VFMADDSSr213r_Int: case X86::VFMADDSSr213m_Int:
3134 case X86::VFMSUBSDr213r_Int: case X86::VFMSUBSDr213m_Int:
3135 case X86::VFMSUBSSr213r_Int: case X86::VFMSUBSSr213m_Int:
3136 case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int:
3137 case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int:
3138 case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int:
3139 case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int:
3140
3141 case X86::VFMADDSDr231r_Int: case X86::VFMADDSDr231m_Int:
3142 case X86::VFMADDSSr231r_Int: case X86::VFMADDSSr231m_Int:
3143 case X86::VFMSUBSDr231r_Int: case X86::VFMSUBSDr231m_Int:
3144 case X86::VFMSUBSSr231r_Int: case X86::VFMSUBSSr231m_Int:
3145 case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int:
3146 case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
3147 case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
3148 case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
3149 if (IsIntrinsic)
3150 *IsIntrinsic = true;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3151 return true;
3152 default:
3153 return false;
3154 }
3155 llvm_unreachable("Opcode not handled by the switch");
3156}
3157
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3158MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr *MI,
3159 bool NewMI,
3160 unsigned OpIdx1,
3161 unsigned OpIdx2) const {
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3162 switch (MI->getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3163 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3164 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3165 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3166 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3167 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3168 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3169 unsigned Opc;
3170 unsigned Size;
3171 switch (MI->getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3172 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3173 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3174 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3175 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3176 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3177 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3178 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3179 }
Chris Lattner5c463782007-12-30 20:49:49 +0000[diff] [blame]3180 unsigned Amt = MI->getOperand(3).getImm();
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]3181 if (NewMI) {
3182 MachineFunction &MF = *MI->getParent()->getParent();
3183 MI = MF.CloneMachineInstr(MI);
3184 NewMI = false;
Evan Cheng244183e2008-02-13 02:46:49 +0000[diff] [blame]3185 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]3186 MI->setDesc(get(Opc));
3187 MI->getOperand(3).setImm(Size-Amt);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3188 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3189 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3190 case X86::BLENDPDrri:
3191 case X86::BLENDPSrri:
3192 case X86::PBLENDWrri:
3193 case X86::VBLENDPDrri:
3194 case X86::VBLENDPSrri:
3195 case X86::VBLENDPDYrri:
3196 case X86::VBLENDPSYrri:
3197 case X86::VPBLENDDrri:
3198 case X86::VPBLENDWrri:
3199 case X86::VPBLENDDYrri:
3200 case X86::VPBLENDWYrri:{
3201 unsigned Mask;
3202 switch (MI->getOpcode()) {
3203 default: llvm_unreachable("Unreachable!");
3204 case X86::BLENDPDrri: Mask = 0x03; break;
3205 case X86::BLENDPSrri: Mask = 0x0F; break;
3206 case X86::PBLENDWrri: Mask = 0xFF; break;
3207 case X86::VBLENDPDrri: Mask = 0x03; break;
3208 case X86::VBLENDPSrri: Mask = 0x0F; break;
3209 case X86::VBLENDPDYrri: Mask = 0x0F; break;
3210 case X86::VBLENDPSYrri: Mask = 0xFF; break;
3211 case X86::VPBLENDDrri: Mask = 0x0F; break;
3212 case X86::VPBLENDWrri: Mask = 0xFF; break;
3213 case X86::VPBLENDDYrri: Mask = 0xFF; break;
3214 case X86::VPBLENDWYrri: Mask = 0xFF; break;
3215 }
Andrea Di Biagio7ecd22c2014-11-06 14:36:45 +0000[diff] [blame]3216 // Only the least significant bits of Imm are used.
3217 unsigned Imm = MI->getOperand(3).getImm() & Mask;
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3218 if (NewMI) {
3219 MachineFunction &MF = *MI->getParent()->getParent();
3220 MI = MF.CloneMachineInstr(MI);
3221 NewMI = false;
3222 }
3223 MI->getOperand(3).setImm(Mask ^ Imm);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3224 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3225 }
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3226 case X86::PCLMULQDQrr:
3227 case X86::VPCLMULQDQrr:{
3228 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3229 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3230 unsigned Imm = MI->getOperand(3).getImm();
3231 unsigned Src1Hi = Imm & 0x01;
3232 unsigned Src2Hi = Imm & 0x10;
3233 if (NewMI) {
3234 MachineFunction &MF = *MI->getParent()->getParent();
3235 MI = MF.CloneMachineInstr(MI);
3236 NewMI = false;
3237 }
3238 MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3239 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3240 }
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3241 case X86::CMPPDrri:
3242 case X86::CMPPSrri:
3243 case X86::VCMPPDrri:
3244 case X86::VCMPPSrri:
3245 case X86::VCMPPDYrri:
3246 case X86::VCMPPSYrri: {
3247 // Float comparison can be safely commuted for
3248 // Ordered/Unordered/Equal/NotEqual tests
3249 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3250 switch (Imm) {
3251 case 0x00: // EQUAL
3252 case 0x03: // UNORDERED
3253 case 0x04: // NOT EQUAL
3254 case 0x07: // ORDERED
3255 if (NewMI) {
3256 MachineFunction &MF = *MI->getParent()->getParent();
3257 MI = MF.CloneMachineInstr(MI);
3258 NewMI = false;
3259 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3260 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3261 default:
3262 return nullptr;
3263 }
3264 }
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3265 case X86::VPCOMBri: case X86::VPCOMUBri:
3266 case X86::VPCOMDri: case X86::VPCOMUDri:
3267 case X86::VPCOMQri: case X86::VPCOMUQri:
3268 case X86::VPCOMWri: case X86::VPCOMUWri: {
3269 // Flip comparison mode immediate (if necessary).
3270 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3271 switch (Imm) {
3272 case 0x00: Imm = 0x02; break; // LT -> GT
3273 case 0x01: Imm = 0x03; break; // LE -> GE
3274 case 0x02: Imm = 0x00; break; // GT -> LT
3275 case 0x03: Imm = 0x01; break; // GE -> LE
3276 case 0x04: // EQ
3277 case 0x05: // NE
3278 case 0x06: // FALSE
3279 case 0x07: // TRUE
3280 default:
3281 break;
3282 }
3283 if (NewMI) {
3284 MachineFunction &MF = *MI->getParent()->getParent();
3285 MI = MF.CloneMachineInstr(MI);
3286 NewMI = false;
3287 }
3288 MI->getOperand(3).setImm(Imm);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3289 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3290 }
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3291 case X86::VPERM2F128rr:
3292 case X86::VPERM2I128rr: {
3293 // Flip permute source immediate.
3294 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3295 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
3296 unsigned Imm = MI->getOperand(3).getImm() & 0xFF;
3297 if (NewMI) {
3298 MachineFunction &MF = *MI->getParent()->getParent();
3299 MI = MF.CloneMachineInstr(MI);
3300 NewMI = false;
3301 }
3302 MI->getOperand(3).setImm(Imm ^ 0x22);
3303 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
3304 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3305 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
3306 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3307 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
3308 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3309 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3310 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
3311 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
3312 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3313 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3314 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
3315 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
3316 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3317 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
3318 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3319 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
3320 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3321 unsigned Opc;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3322 switch (MI->getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3323 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3324 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
3325 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
3326 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
3327 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3328 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3329 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3330 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
3331 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
3332 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
3333 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3334 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3335 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]3336 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3337 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3338 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3339 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
3340 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
3341 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3342 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
3343 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
3344 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
3345 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3346 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3347 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3348 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3349 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3350 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3351 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
3352 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3353 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3354 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3355 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3356 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3357 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3358 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3359 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3360 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3361 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3362 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3363 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3364 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3365 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3366 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3367 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3368 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3369 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3370 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3371 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3372 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]3373 if (NewMI) {
3374 MachineFunction &MF = *MI->getParent()->getParent();
3375 MI = MF.CloneMachineInstr(MI);
3376 NewMI = false;
3377 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]3378 MI->setDesc(get(Opc));
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3379 // Fallthrough intended.
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3380 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3381 default:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3382 if (isFMA3(MI->getOpcode())) {
3383 unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
3384 if (Opc == 0)
3385 return nullptr;
3386 if (NewMI) {
3387 MachineFunction &MF = *MI->getParent()->getParent();
3388 MI = MF.CloneMachineInstr(MI);
3389 NewMI = false;
3390 }
3391 MI->setDesc(get(Opc));
3392 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3393 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3394 }
3395}
3396
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3397bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr *MI,
3398 unsigned &SrcOpIdx1,
3399 unsigned &SrcOpIdx2) const {
3400
3401 unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3402
3403 // Only the first RegOpsNum operands are commutable.
3404 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3405 // that the operand is not specified/fixed.
3406 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3407 (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3408 return false;
3409 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3410 (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3411 return false;
3412
3413 // Look for two different register operands assumed to be commutable
3414 // regardless of the FMA opcode. The FMA opcode is adjusted later.
3415 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3416 SrcOpIdx2 == CommuteAnyOperandIndex) {
3417 unsigned CommutableOpIdx1 = SrcOpIdx1;
3418 unsigned CommutableOpIdx2 = SrcOpIdx2;
3419
3420 // At least one of operands to be commuted is not specified and
3421 // this method is free to choose appropriate commutable operands.
3422 if (SrcOpIdx1 == SrcOpIdx2)
3423 // Both of operands are not fixed. By default set one of commutable
3424 // operands to the last register operand of the instruction.
3425 CommutableOpIdx2 = RegOpsNum;
3426 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3427 // Only one of operands is not fixed.
3428 CommutableOpIdx2 = SrcOpIdx1;
3429
3430 // CommutableOpIdx2 is well defined now. Let's choose another commutable
3431 // operand and assign its index to CommutableOpIdx1.
3432 unsigned Op2Reg = MI->getOperand(CommutableOpIdx2).getReg();
3433 for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3434 // The commuted operands must have different registers.
3435 // Otherwise, the commute transformation does not change anything and
3436 // is useless then.
3437 if (Op2Reg != MI->getOperand(CommutableOpIdx1).getReg())
3438 break;
3439 }
3440
3441 // No appropriate commutable operands were found.
3442 if (CommutableOpIdx1 == 0)
3443 return false;
3444
3445 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3446 // to return those values.
3447 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3448 CommutableOpIdx1, CommutableOpIdx2))
3449 return false;
3450 }
3451
3452 // Check if we can adjust the opcode to preserve the semantics when
3453 // commute the register operands.
3454 return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
3455}
3456
3457unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(MachineInstr *MI,
3458 unsigned SrcOpIdx1,
3459 unsigned SrcOpIdx2) const {
3460 unsigned Opc = MI->getOpcode();
3461
3462 // Define the array that holds FMA opcodes in groups
3463 // of 3 opcodes(132, 213, 231) in each group.
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3464 static const uint16_t RegularOpcodeGroups[][3] = {
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3465 { X86::VFMADDSSr132r, X86::VFMADDSSr213r, X86::VFMADDSSr231r },
3466 { X86::VFMADDSDr132r, X86::VFMADDSDr213r, X86::VFMADDSDr231r },
3467 { X86::VFMADDPSr132r, X86::VFMADDPSr213r, X86::VFMADDPSr231r },
3468 { X86::VFMADDPDr132r, X86::VFMADDPDr213r, X86::VFMADDPDr231r },
3469 { X86::VFMADDPSr132rY, X86::VFMADDPSr213rY, X86::VFMADDPSr231rY },
3470 { X86::VFMADDPDr132rY, X86::VFMADDPDr213rY, X86::VFMADDPDr231rY },
3471 { X86::VFMADDSSr132m, X86::VFMADDSSr213m, X86::VFMADDSSr231m },
3472 { X86::VFMADDSDr132m, X86::VFMADDSDr213m, X86::VFMADDSDr231m },
3473 { X86::VFMADDPSr132m, X86::VFMADDPSr213m, X86::VFMADDPSr231m },
3474 { X86::VFMADDPDr132m, X86::VFMADDPDr213m, X86::VFMADDPDr231m },
3475 { X86::VFMADDPSr132mY, X86::VFMADDPSr213mY, X86::VFMADDPSr231mY },
3476 { X86::VFMADDPDr132mY, X86::VFMADDPDr213mY, X86::VFMADDPDr231mY },
3477
3478 { X86::VFMSUBSSr132r, X86::VFMSUBSSr213r, X86::VFMSUBSSr231r },
3479 { X86::VFMSUBSDr132r, X86::VFMSUBSDr213r, X86::VFMSUBSDr231r },
3480 { X86::VFMSUBPSr132r, X86::VFMSUBPSr213r, X86::VFMSUBPSr231r },
3481 { X86::VFMSUBPDr132r, X86::VFMSUBPDr213r, X86::VFMSUBPDr231r },
3482 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr213rY, X86::VFMSUBPSr231rY },
3483 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr213rY, X86::VFMSUBPDr231rY },
3484 { X86::VFMSUBSSr132m, X86::VFMSUBSSr213m, X86::VFMSUBSSr231m },
3485 { X86::VFMSUBSDr132m, X86::VFMSUBSDr213m, X86::VFMSUBSDr231m },
3486 { X86::VFMSUBPSr132m, X86::VFMSUBPSr213m, X86::VFMSUBPSr231m },
3487 { X86::VFMSUBPDr132m, X86::VFMSUBPDr213m, X86::VFMSUBPDr231m },
3488 { X86::VFMSUBPSr132mY, X86::VFMSUBPSr213mY, X86::VFMSUBPSr231mY },
3489 { X86::VFMSUBPDr132mY, X86::VFMSUBPDr213mY, X86::VFMSUBPDr231mY },
Vyacheslav Klochkov1ff9cbd2015-11-12 20:11:57 +0000[diff] [blame]3490
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3491 { X86::VFNMADDSSr132r, X86::VFNMADDSSr213r, X86::VFNMADDSSr231r },
3492 { X86::VFNMADDSDr132r, X86::VFNMADDSDr213r, X86::VFNMADDSDr231r },
3493 { X86::VFNMADDPSr132r, X86::VFNMADDPSr213r, X86::VFNMADDPSr231r },
3494 { X86::VFNMADDPDr132r, X86::VFNMADDPDr213r, X86::VFNMADDPDr231r },
3495 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
3496 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
3497 { X86::VFNMADDSSr132m, X86::VFNMADDSSr213m, X86::VFNMADDSSr231m },
3498 { X86::VFNMADDSDr132m, X86::VFNMADDSDr213m, X86::VFNMADDSDr231m },
3499 { X86::VFNMADDPSr132m, X86::VFNMADDPSr213m, X86::VFNMADDPSr231m },
3500 { X86::VFNMADDPDr132m, X86::VFNMADDPDr213m, X86::VFNMADDPDr231m },
3501 { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
3502 { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
3503
3504 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr213r, X86::VFNMSUBSSr231r },
3505 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr213r, X86::VFNMSUBSDr231r },
3506 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr213r, X86::VFNMSUBPSr231r },
3507 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr213r, X86::VFNMSUBPDr231r },
3508 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
3509 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
3510 { X86::VFNMSUBSSr132m, X86::VFNMSUBSSr213m, X86::VFNMSUBSSr231m },
3511 { X86::VFNMSUBSDr132m, X86::VFNMSUBSDr213m, X86::VFNMSUBSDr231m },
3512 { X86::VFNMSUBPSr132m, X86::VFNMSUBPSr213m, X86::VFNMSUBPSr231m },
3513 { X86::VFNMSUBPDr132m, X86::VFNMSUBPDr213m, X86::VFNMSUBPDr231m },
3514 { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
3515 { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
3516
3517 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr231r },
3518 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr231r },
3519 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
3520 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
3521 { X86::VFMADDSUBPSr132m, X86::VFMADDSUBPSr213m, X86::VFMADDSUBPSr231m },
3522 { X86::VFMADDSUBPDr132m, X86::VFMADDSUBPDr213m, X86::VFMADDSUBPDr231m },
3523 { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
3524 { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
3525
3526 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr231r },
3527 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr231r },
3528 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
3529 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
3530 { X86::VFMSUBADDPSr132m, X86::VFMSUBADDPSr213m, X86::VFMSUBADDPSr231m },
3531 { X86::VFMSUBADDPDr132m, X86::VFMSUBADDPDr213m, X86::VFMSUBADDPDr231m },
3532 { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
3533 { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
3534 };
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3535
3536 // Define the array that holds FMA*_Int opcodes in groups
3537 // of 3 opcodes(132, 213, 231) in each group.
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3538 static const uint16_t IntrinOpcodeGroups[][3] = {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3539 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr213r_Int, X86::VFMADDSSr231r_Int },
3540 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr213r_Int, X86::VFMADDSDr231r_Int },
3541 { X86::VFMADDSSr132m_Int, X86::VFMADDSSr213m_Int, X86::VFMADDSSr231m_Int },
3542 { X86::VFMADDSDr132m_Int, X86::VFMADDSDr213m_Int, X86::VFMADDSDr231m_Int },
3543
3544 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr231r_Int },
3545 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr231r_Int },
3546 { X86::VFMSUBSSr132m_Int, X86::VFMSUBSSr213m_Int, X86::VFMSUBSSr231m_Int },
3547 { X86::VFMSUBSDr132m_Int, X86::VFMSUBSDr213m_Int, X86::VFMSUBSDr231m_Int },
3548
3549 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
3550 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
3551 { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
3552 { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
3553
3554 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
3555 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
3556 { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
3557 { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
3558 };
3559
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3560 const unsigned Form132Index = 0;
3561 const unsigned Form213Index = 1;
3562 const unsigned Form231Index = 2;
3563 const unsigned FormsNum = 3;
3564
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3565 bool IsIntrinOpcode;
3566 isFMA3(Opc, &IsIntrinOpcode);
3567
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3568 size_t GroupsNum;
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3569 const uint16_t (*OpcodeGroups)[3];
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3570 if (IsIntrinOpcode) {
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3571 GroupsNum = array_lengthof(IntrinOpcodeGroups);
Craig Topper27e29122015-11-30 02:28:19 +0000[diff] [blame]3572 OpcodeGroups = IntrinOpcodeGroups;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3573 } else {
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3574 GroupsNum = array_lengthof(RegularOpcodeGroups);
Craig Topper27e29122015-11-30 02:28:19 +0000[diff] [blame]3575 OpcodeGroups = RegularOpcodeGroups;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3576 }
3577
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3578 const uint16_t *FoundOpcodesGroup = nullptr;
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3579 size_t FormIndex;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3580
3581 // Look for the input opcode in the corresponding opcodes table.
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3582 for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
3583 ++GroupIndex) {
3584 for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3585 if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
3586 FoundOpcodesGroup = OpcodeGroups[GroupIndex];
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3587 break;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3588 }
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3589 }
3590 }
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3591
3592 // The input opcode does not match with any of the opcodes from the tables.
3593 // The unsupported FMA opcode must be added to one of the two opcode groups
3594 // defined above.
3595 assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3596
3597 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3598 if (SrcOpIdx1 > SrcOpIdx2)
3599 std::swap(SrcOpIdx1, SrcOpIdx2);
3600
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3601 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3602 // analysis. The commute optimization is legal only if all users of FMA*_Int
3603 // use only the lowest element of the FMA*_Int instruction. Such analysis are
3604 // not implemented yet. So, just return 0 in that case.
3605 // When such analysis are available this place will be the right place for
3606 // calling it.
3607 if (IsIntrinOpcode && SrcOpIdx1 == 1)
3608 return 0;
3609
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3610 unsigned Case;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3611 if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3612 Case = 0;
3613 else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3614 Case = 1;
3615 else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3616 Case = 2;
3617 else
3618 return 0;
3619
3620 // Define the FMA forms mapping array that helps to map input FMA form
3621 // to output FMA form to preserve the operation semantics after
3622 // commuting the operands.
3623 static const unsigned FormMapping[][3] = {
3624 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3625 // FMA132 A, C, b; ==> FMA231 C, A, b;
3626 // FMA213 B, A, c; ==> FMA213 A, B, c;
3627 // FMA231 C, A, b; ==> FMA132 A, C, b;
3628 { Form231Index, Form213Index, Form132Index },
3629 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3630 // FMA132 A, c, B; ==> FMA132 B, c, A;
3631 // FMA213 B, a, C; ==> FMA231 C, a, B;
3632 // FMA231 C, a, B; ==> FMA213 B, a, C;
3633 { Form132Index, Form231Index, Form213Index },
3634 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3635 // FMA132 a, C, B; ==> FMA213 a, B, C;
3636 // FMA213 b, A, C; ==> FMA132 b, C, A;
3637 // FMA231 c, A, B; ==> FMA231 c, B, A;
3638 { Form213Index, Form132Index, Form231Index }
3639 };
3640
3641 // Everything is ready, just adjust the FMA opcode and return it.
3642 FormIndex = FormMapping[Case][FormIndex];
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3643 return FoundOpcodesGroup[FormIndex];
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3644}
3645
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3646bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI,
3647 unsigned &SrcOpIdx1,
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3648 unsigned &SrcOpIdx2) const {
3649 switch (MI->getOpcode()) {
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3650 case X86::CMPPDrri:
3651 case X86::CMPPSrri:
3652 case X86::VCMPPDrri:
3653 case X86::VCMPPSrri:
3654 case X86::VCMPPDYrri:
3655 case X86::VCMPPSYrri: {
3656 // Float comparison can be safely commuted for
3657 // Ordered/Unordered/Equal/NotEqual tests
3658 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3659 switch (Imm) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3660 case 0x00: // EQUAL
3661 case 0x03: // UNORDERED
3662 case 0x04: // NOT EQUAL
3663 case 0x07: // ORDERED
3664 // The indices of the commutable operands are 1 and 2.
3665 // Assign them to the returned operand indices here.
3666 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3667 }
3668 return false;
3669 }
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3670 default:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3671 if (isFMA3(MI->getOpcode()))
3672 return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3673 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3674 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3675 return false;
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3676}
3677
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3678static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3679 switch (BrOpc) {
3680 default: return X86::COND_INVALID;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3681 case X86::JE_1: return X86::COND_E;
3682 case X86::JNE_1: return X86::COND_NE;
3683 case X86::JL_1: return X86::COND_L;
3684 case X86::JLE_1: return X86::COND_LE;
3685 case X86::JG_1: return X86::COND_G;
3686 case X86::JGE_1: return X86::COND_GE;
3687 case X86::JB_1: return X86::COND_B;
3688 case X86::JBE_1: return X86::COND_BE;
3689 case X86::JA_1: return X86::COND_A;
3690 case X86::JAE_1: return X86::COND_AE;
3691 case X86::JS_1: return X86::COND_S;
3692 case X86::JNS_1: return X86::COND_NS;
3693 case X86::JP_1: return X86::COND_P;
3694 case X86::JNP_1: return X86::COND_NP;
3695 case X86::JO_1: return X86::COND_O;
3696 case X86::JNO_1: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3697 }
3698}
3699
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3700/// Return condition code of a SET opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3701static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3702 switch (Opc) {
3703 default: return X86::COND_INVALID;
3704 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3705 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3706 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3707 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3708 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3709 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3710 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3711 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3712 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3713 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3714 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3715 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3716 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3717 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3718 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3719 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3720 }
3721}
3722
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3723/// Return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3724X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3725 switch (Opc) {
3726 default: return X86::COND_INVALID;
3727 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3728 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3729 return X86::COND_A;
3730 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3731 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3732 return X86::COND_AE;
3733 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3734 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3735 return X86::COND_B;
3736 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3737 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3738 return X86::COND_BE;
3739 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3740 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3741 return X86::COND_E;
3742 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3743 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3744 return X86::COND_G;
3745 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3746 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3747 return X86::COND_GE;
3748 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3749 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3750 return X86::COND_L;
3751 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3752 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3753 return X86::COND_LE;
3754 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3755 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3756 return X86::COND_NE;
3757 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3758 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3759 return X86::COND_NO;
3760 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3761 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3762 return X86::COND_NP;
3763 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3764 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3765 return X86::COND_NS;
3766 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3767 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3768 return X86::COND_O;
3769 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3770 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3771 return X86::COND_P;
3772 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3773 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3774 return X86::COND_S;
3775 }
3776}
3777
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3778unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3779 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3780 default: llvm_unreachable("Illegal condition code!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3781 case X86::COND_E: return X86::JE_1;
3782 case X86::COND_NE: return X86::JNE_1;
3783 case X86::COND_L: return X86::JL_1;
3784 case X86::COND_LE: return X86::JLE_1;
3785 case X86::COND_G: return X86::JG_1;
3786 case X86::COND_GE: return X86::JGE_1;
3787 case X86::COND_B: return X86::JB_1;
3788 case X86::COND_BE: return X86::JBE_1;
3789 case X86::COND_A: return X86::JA_1;
3790 case X86::COND_AE: return X86::JAE_1;
3791 case X86::COND_S: return X86::JS_1;
3792 case X86::COND_NS: return X86::JNS_1;
3793 case X86::COND_P: return X86::JP_1;
3794 case X86::COND_NP: return X86::JNP_1;
3795 case X86::COND_O: return X86::JO_1;
3796 case X86::COND_NO: return X86::JNO_1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3797 }
3798}
3799
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3800/// Return the inverse of the specified condition,
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3801/// e.g. turning COND_E to COND_NE.
3802X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3803 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3804 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3805 case X86::COND_E: return X86::COND_NE;
3806 case X86::COND_NE: return X86::COND_E;
3807 case X86::COND_L: return X86::COND_GE;
3808 case X86::COND_LE: return X86::COND_G;
3809 case X86::COND_G: return X86::COND_LE;
3810 case X86::COND_GE: return X86::COND_L;
3811 case X86::COND_B: return X86::COND_AE;
3812 case X86::COND_BE: return X86::COND_A;
3813 case X86::COND_A: return X86::COND_BE;
3814 case X86::COND_AE: return X86::COND_B;
3815 case X86::COND_S: return X86::COND_NS;
3816 case X86::COND_NS: return X86::COND_S;
3817 case X86::COND_P: return X86::COND_NP;
3818 case X86::COND_NP: return X86::COND_P;
3819 case X86::COND_O: return X86::COND_NO;
3820 case X86::COND_NO: return X86::COND_O;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3821 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
3822 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3823 }
3824}
3825
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3826/// Assuming the flags are set by MI(a,b), return the condition code if we
3827/// modify the instructions such that flags are set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]3828static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3829 switch (CC) {
3830 default: return X86::COND_INVALID;
3831 case X86::COND_E: return X86::COND_E;
3832 case X86::COND_NE: return X86::COND_NE;
3833 case X86::COND_L: return X86::COND_G;
3834 case X86::COND_LE: return X86::COND_GE;
3835 case X86::COND_G: return X86::COND_L;
3836 case X86::COND_GE: return X86::COND_LE;
3837 case X86::COND_B: return X86::COND_A;
3838 case X86::COND_BE: return X86::COND_AE;
3839 case X86::COND_A: return X86::COND_B;
3840 case X86::COND_AE: return X86::COND_BE;
3841 }
3842}
3843
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3844/// Return a set opcode for the given condition and
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3845/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3846unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3847 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3848 { X86::SETAr, X86::SETAm },
3849 { X86::SETAEr, X86::SETAEm },
3850 { X86::SETBr, X86::SETBm },
3851 { X86::SETBEr, X86::SETBEm },
3852 { X86::SETEr, X86::SETEm },
3853 { X86::SETGr, X86::SETGm },
3854 { X86::SETGEr, X86::SETGEm },
3855 { X86::SETLr, X86::SETLm },
3856 { X86::SETLEr, X86::SETLEm },
3857 { X86::SETNEr, X86::SETNEm },
3858 { X86::SETNOr, X86::SETNOm },
3859 { X86::SETNPr, X86::SETNPm },
3860 { X86::SETNSr, X86::SETNSm },
3861 { X86::SETOr, X86::SETOm },
3862 { X86::SETPr, X86::SETPm },
3863 { X86::SETSr, X86::SETSm }
3864 };
3865
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3866 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3867 return Opc[CC][HasMemoryOperand ? 1 : 0];
3868}
3869
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3870/// Return a cmov opcode for the given condition,
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3871/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]3872unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3873 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3874 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3875 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3876 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3877 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3878 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3879 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3880 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3881 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3882 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3883 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3884 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3885 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3886 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3887 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3888 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3889 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3890 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3891 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3892 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3893 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3894 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3895 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3896 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3897 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3898 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3899 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3900 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3901 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3902 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3903 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3904 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3905 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3906 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3907 };
3908
3909 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3910 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3911 switch(RegBytes) {
3912 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3913 case 2: return Opc[Idx][0];
3914 case 4: return Opc[Idx][1];
3915 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3916 }
3917}
3918
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]3919bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
3920 if (!MI.isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3921
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3922 // Conditional branch is a special case.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]3923 if (MI.isBranch() && !MI.isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3924 return true;
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]3925 if (!MI.isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3926 return true;
3927 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3928}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3929
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3930// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may not
3931// be a fallthorough MBB now due to layout changes). Return nullptr if the
3932// fallthough MBB cannot be identified.
3933static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3934 MachineBasicBlock *TBB) {
3935 MachineBasicBlock *FallthroughBB = nullptr;
3936 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
3937 if ((*SI)->isEHPad() || *SI == TBB)
3938 continue;
3939 // Return a nullptr if we found more than one fallthrough successor.
3940 if (FallthroughBB)
3941 return nullptr;
3942 FallthroughBB = *SI;
3943 }
3944 return FallthroughBB;
3945}
3946
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]3947bool X86InstrInfo::AnalyzeBranchImpl(
3948 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3949 SmallVectorImpl<MachineOperand> &Cond,
3950 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3951
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3952 // Start from the bottom of the block and work up, examining the
3953 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3954 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3955 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3956 while (I != MBB.begin()) {
3957 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]3958 if (I->isDebugValue())
3959 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3960
3961 // Working from the bottom, when we see a non-terminator instruction, we're
3962 // done.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]3963 if (!isUnpredicatedTerminator(*I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3964 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3965
3966 // A terminator that isn't a branch can't easily be handled by this
3967 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3968 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3969 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3970
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3971 // Handle unconditional branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3972 if (I->getOpcode() == X86::JMP_1) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3973 UnCondBrIter = I;
3974
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3975 if (!AllowModify) {
3976 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]3977 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3978 }
3979
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3980 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]3981 while (std::next(I) != MBB.end())
3982 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3983
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3984 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3985 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3986
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3987 // Delete the JMP if it's equivalent to a fall-through.
3988 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3989 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3990 I->eraseFromParent();
3991 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3992 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3993 continue;
3994 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3995
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3996 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3997 TBB = I->getOperand(0).getMBB();
3998 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3999 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4000
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4001 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4002 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4003 if (BranchCode == X86::COND_INVALID)
4004 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4005
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4006 // Working from the bottom, handle the first conditional branch.
4007 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4008 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4009 if (AllowModify && UnCondBrIter != MBB.end() &&
4010 MBB.isLayoutSuccessor(TargetBB)) {
4011 // If we can modify the code and it ends in something like:
4012 //
4013 // jCC L1
4014 // jmp L2
4015 // L1:
4016 // ...
4017 // L2:
4018 //
4019 // Then we can change this to:
4020 //
4021 // jnCC L2
4022 // L1:
4023 // ...
4024 // L2:
4025 //
4026 // Which is a bit more efficient.
4027 // We conditionally jump to the fall-through block.
4028 BranchCode = GetOppositeBranchCondition(BranchCode);
4029 unsigned JNCC = GetCondBranchFromCond(BranchCode);
4030 MachineBasicBlock::iterator OldInst = I;
4031
4032 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4033 .addMBB(UnCondBrIter->getOperand(0).getMBB());
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4034 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4035 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4036
4037 OldInst->eraseFromParent();
4038 UnCondBrIter->eraseFromParent();
4039
4040 // Restart the analysis.
4041 UnCondBrIter = MBB.end();
4042 I = MBB.end();
4043 continue;
4044 }
4045
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4046 FBB = TBB;
4047 TBB = I->getOperand(0).getMBB();
4048 Cond.push_back(MachineOperand::CreateImm(BranchCode));
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4049 CondBranches.push_back(I);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4050 continue;
4051 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4052
4053 // Handle subsequent conditional branches. Only handle the case where all
4054 // conditional branches branch to the same destination and their condition
4055 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4056 assert(Cond.size() == 1);
4057 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4058
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4059 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4060 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4061 auto NewTBB = I->getOperand(0).getMBB();
4062 if (OldBranchCode == BranchCode && TBB == NewTBB)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4063 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4064
4065 // If they differ, see if they fit one of the known patterns. Theoretically,
4066 // we could handle more patterns here, but we shouldn't expect to see them
4067 // if instruction selection has done a reasonable job.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4068 if (TBB == NewTBB &&
4069 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4070 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4071 BranchCode = X86::COND_NE_OR_P;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4072 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4073 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4074 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4075 return true;
4076
4077 // X86::COND_E_AND_NP usually has two different branch destinations.
4078 //
4079 // JP B1
4080 // JE B2
4081 // JMP B1
4082 // B1:
4083 // B2:
4084 //
4085 // Here this condition branches to B2 only if NP && E. It has another
4086 // equivalent form:
4087 //
4088 // JNE B1
4089 // JNP B2
4090 // JMP B1
4091 // B1:
4092 // B2:
4093 //
4094 // Similarly it branches to B2 only if E && NP. That is why this condition
4095 // is named with COND_E_AND_NP.
4096 BranchCode = X86::COND_E_AND_NP;
4097 } else
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4098 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4099
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4100 // Update the MachineOperand.
4101 Cond[0].setImm(BranchCode);
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4102 CondBranches.push_back(I);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]4103 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4104
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4105 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4106}
4107
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4108bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
4109 MachineBasicBlock *&TBB,
4110 MachineBasicBlock *&FBB,
4111 SmallVectorImpl<MachineOperand> &Cond,
4112 bool AllowModify) const {
4113 SmallVector<MachineInstr *, 4> CondBranches;
4114 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4115}
4116
4117bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB,
4118 MachineBranchPredicate &MBP,
4119 bool AllowModify) const {
4120 using namespace std::placeholders;
4121
4122 SmallVector<MachineOperand, 4> Cond;
4123 SmallVector<MachineInstr *, 4> CondBranches;
4124 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4125 AllowModify))
4126 return true;
4127
4128 if (Cond.size() != 1)
4129 return true;
4130
4131 assert(MBP.TrueDest && "expected!");
4132
4133 if (!MBP.FalseDest)
4134 MBP.FalseDest = MBB.getNextNode();
4135
4136 const TargetRegisterInfo *TRI = &getRegisterInfo();
4137
4138 MachineInstr *ConditionDef = nullptr;
4139 bool SingleUseCondition = true;
4140
4141 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4142 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4143 ConditionDef = &*I;
4144 break;
4145 }
4146
4147 if (I->readsRegister(X86::EFLAGS, TRI))
4148 SingleUseCondition = false;
4149 }
4150
4151 if (!ConditionDef)
4152 return true;
4153
4154 if (SingleUseCondition) {
4155 for (auto *Succ : MBB.successors())
4156 if (Succ->isLiveIn(X86::EFLAGS))
4157 SingleUseCondition = false;
4158 }
4159
4160 MBP.ConditionDef = ConditionDef;
4161 MBP.SingleUseCondition = SingleUseCondition;
4162
4163 // Currently we only recognize the simple pattern:
4164 //
4165 // test %reg, %reg
4166 // je %label
4167 //
4168 const unsigned TestOpcode =
4169 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4170
4171 if (ConditionDef->getOpcode() == TestOpcode &&
4172 ConditionDef->getNumOperands() == 3 &&
4173 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4174 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4175 MBP.LHS = ConditionDef->getOperand(0);
4176 MBP.RHS = MachineOperand::CreateImm(0);
4177 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4178 ? MachineBranchPredicate::PRED_NE
4179 : MachineBranchPredicate::PRED_EQ;
4180 return false;
4181 }
4182
4183 return true;
4184}
4185
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4186unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4187 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4188 unsigned Count = 0;
4189
4190 while (I != MBB.begin()) {
4191 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]4192 if (I->isDebugValue())
4193 continue;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4194 if (I->getOpcode() != X86::JMP_1 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4195 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4196 break;
4197 // Remove the branch.
4198 I->eraseFromParent();
4199 I = MBB.end();
4200 ++Count;
4201 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4202
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4203 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4204}
4205
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4206unsigned
4207X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]4208 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]4209 DebugLoc DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4210 // Shouldn't be a fall through.
4211 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]4212 assert((Cond.size() == 1 || Cond.size() == 0) &&
4213 "X86 branch conditions have one component!");
4214
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4215 if (Cond.empty()) {
4216 // Unconditional branch?
4217 assert(!FBB && "Unconditional branch with multiple successors!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4218 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4219 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4220 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4221
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4222 // If FBB is null, it is implied to be a fall-through block.
4223 bool FallThru = FBB == nullptr;
4224
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4225 // Conditional branch.
4226 unsigned Count = 0;
4227 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4228 switch (CC) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4229 case X86::COND_NE_OR_P:
4230 // Synthesize NE_OR_P with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4231 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4232 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4233 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4234 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4235 break;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4236 case X86::COND_E_AND_NP:
4237 // Use the next block of MBB as FBB if it is null.
4238 if (FBB == nullptr) {
4239 FBB = getFallThroughMBB(&MBB, TBB);
4240 assert(FBB && "MBB cannot be the last block in function when the false "
4241 "body is a fall-through.");
4242 }
4243 // Synthesize COND_E_AND_NP with two branches.
4244 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4245 ++Count;
4246 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4247 ++Count;
4248 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4249 default: {
4250 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]4251 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4252 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4253 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4254 }
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4255 if (!FallThru) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4256 // Two-way Conditional branch. Insert the second branch.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4257 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4258 ++Count;
4259 }
4260 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4261}
4262
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4263bool X86InstrInfo::
4264canInsertSelect(const MachineBasicBlock &MBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]4265 ArrayRef<MachineOperand> Cond,
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4266 unsigned TrueReg, unsigned FalseReg,
4267 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4268 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4269 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4270 return false;
4271 if (Cond.size() != 1)
4272 return false;
4273 // We cannot do the composite conditions, at least not in SSA form.
4274 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4275 return false;
4276
4277 // Check register classes.
4278 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4279 const TargetRegisterClass *RC =
4280 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4281 if (!RC)
4282 return false;
4283
4284 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4285 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4286 X86::GR32RegClass.hasSubClassEq(RC) ||
4287 X86::GR64RegClass.hasSubClassEq(RC)) {
4288 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4289 // Bridge. Probably Ivy Bridge as well.
4290 CondCycles = 2;
4291 TrueCycles = 2;
4292 FalseCycles = 2;
4293 return true;
4294 }
4295
4296 // Can't do vectors.
4297 return false;
4298}
4299
4300void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4301 MachineBasicBlock::iterator I, DebugLoc DL,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]4302 unsigned DstReg, ArrayRef<MachineOperand> Cond,
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4303 unsigned TrueReg, unsigned FalseReg) const {
4304 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4305 assert(Cond.size() == 1 && "Invalid Cond array");
4306 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4307 MRI.getRegClass(DstReg)->getSize(),
4308 false/*HasMemoryOperand*/);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4309 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
4310}
4311
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4312/// Test if the given register is a physical h register.
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4313static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4314 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4315}
4316
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4317// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4318static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4319 const X86Subtarget &Subtarget) {
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4320
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4321 // SrcReg(VR128) -> DestReg(GR64)
4322 // SrcReg(VR64) -> DestReg(GR64)
4323 // SrcReg(GR64) -> DestReg(VR128)
4324 // SrcReg(GR64) -> DestReg(VR64)
4325
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4326 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4327 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4328 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4329 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4330 // Copy from a VR128 register to a GR64 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4331 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
4332 X86::MOVPQIto64rr);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4333 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4334 // Copy from a VR64 register to a GR64 register.
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4335 return X86::MMX_MOVD64from64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4336 } else if (X86::GR64RegClass.contains(SrcReg)) {
4337 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4338 if (X86::VR128XRegClass.contains(DestReg))
4339 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
4340 X86::MOV64toPQIrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4341 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4342 if (X86::VR64RegClass.contains(DestReg))
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4343 return X86::MMX_MOVD64to64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4344 }
4345
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4346 // SrcReg(FR32) -> DestReg(GR32)
4347 // SrcReg(GR32) -> DestReg(FR32)
4348
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4349 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4350 // Copy from a FR32 register to a GR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4351 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4352
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4353 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4354 // Copy from a GR32 register to a FR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4355 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4356 return 0;
4357}
4358
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4359static bool isMaskRegClass(const TargetRegisterClass *RC) {
4360 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4361 return X86::VK16RegClass.hasSubClassEq(RC);
4362}
4363
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4364static bool MaskRegClassContains(unsigned Reg) {
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4365 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4366 return X86::VK16RegClass.contains(Reg);
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]4367}
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4368
4369static bool GRRegClassContains(unsigned Reg) {
4370 return X86::GR64RegClass.contains(Reg) ||
4371 X86::GR32RegClass.contains(Reg) ||
4372 X86::GR16RegClass.contains(Reg) ||
4373 X86::GR8RegClass.contains(Reg);
4374}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4375static
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4376unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4377 if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4378 DestReg = getX86SubSuperRegister(DestReg, 32);
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4379 return X86::KMOVBrk;
4380 }
4381 if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4382 SrcReg = getX86SubSuperRegister(SrcReg, 32);
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4383 return X86::KMOVBkr;
4384 }
4385 return 0;
4386}
4387
4388static
4389unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4390 if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4391 return X86::KMOVQkk;
4392 if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4393 return X86::KMOVDrk;
4394 if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4395 return X86::KMOVQrk;
4396 if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4397 return X86::KMOVDkr;
4398 if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4399 return X86::KMOVQkr;
4400 return 0;
4401}
4402
4403static
4404unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4405 const X86Subtarget &Subtarget)
4406{
4407 if (Subtarget.hasDQI())
4408 if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4409 return Opc;
4410 if (Subtarget.hasBWI())
4411 if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4412 return Opc;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4413 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
4414 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
4415 X86::VR512RegClass.contains(DestReg, SrcReg)) {
4416 DestReg = get512BitSuperRegister(DestReg);
4417 SrcReg = get512BitSuperRegister(SrcReg);
4418 return X86::VMOVAPSZrr;
4419 }
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4420 if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4421 return X86::KMOVWkk;
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4422 if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4423 SrcReg = getX86SubSuperRegister(SrcReg, 32);
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4424 return X86::KMOVWkr;
4425 }
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4426 if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4427 DestReg = getX86SubSuperRegister(DestReg, 32);
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4428 return X86::KMOVWrk;
4429 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4430 return 0;
4431}
4432
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4433void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4434 MachineBasicBlock::iterator MI, DebugLoc DL,
4435 unsigned DestReg, unsigned SrcReg,
4436 bool KillSrc) const {
4437 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4438 bool HasAVX = Subtarget.hasAVX();
4439 bool HasAVX512 = Subtarget.hasAVX512();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4440 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4441 if (X86::GR64RegClass.contains(DestReg, SrcReg))
4442 Opc = X86::MOV64rr;
4443 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4444 Opc = X86::MOV32rr;
4445 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4446 Opc = X86::MOV16rr;
4447 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4448 // Copying to or from a physical H register on x86-64 requires a NOREX
4449 // move. Otherwise use a normal move.
4450 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4451 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4452 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]4453 // Both operands must be encodable without an REX prefix.
4454 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4455 "8-bit H register can not be copied outside GR8_NOREX");
4456 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4457 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4458 }
4459 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4460 Opc = X86::MMX_MOVQ64rr;
4461 else if (HasAVX512)
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4462 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4463 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4464 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4465 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4466 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4467 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4468 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4469
4470 if (Opc) {
4471 BuildMI(MBB, MI, DL, get(Opc), DestReg)
4472 .addReg(SrcReg, getKillRegState(KillSrc));
4473 return;
4474 }
4475
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4476 bool FromEFLAGS = SrcReg == X86::EFLAGS;
4477 bool ToEFLAGS = DestReg == X86::EFLAGS;
4478 int Reg = FromEFLAGS ? DestReg : SrcReg;
4479 bool is32 = X86::GR32RegClass.contains(Reg);
4480 bool is64 = X86::GR64RegClass.contains(Reg);
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4481
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4482 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4483 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4484 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4485 int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4486 int Pop = is64 ? X86::POP64r : X86::POP32r;
4487 int PopF = is64 ? X86::POPF64 : X86::POPF32;
4488 int AX = is64 ? X86::RAX : X86::EAX;
4489
4490 if (!Subtarget.hasLAHFSAHF()) {
Hans Wennborg7036e502015-12-15 23:21:46 +0000[diff] [blame]4491 assert(Subtarget.is64Bit() &&
4492 "Not having LAHF/SAHF only happens on 64-bit.");
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4493 // Moving EFLAGS to / from another register requires a push and a pop.
4494 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemer33467632015-12-27 06:07:26 +0000[diff] [blame]4495 // first frame index. See X86FrameLowering.cpp - usesTheStack.
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4496 if (FromEFLAGS) {
4497 BuildMI(MBB, MI, DL, get(PushF));
4498 BuildMI(MBB, MI, DL, get(Pop), DestReg);
4499 }
4500 if (ToEFLAGS) {
4501 BuildMI(MBB, MI, DL, get(Push))
4502 .addReg(SrcReg, getKillRegState(KillSrc));
4503 BuildMI(MBB, MI, DL, get(PopF));
4504 }
4505 return;
4506 }
4507
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4508 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4509 // inefficient. Instead:
4510 // - Save the overflow flag OF into AL using SETO, and restore it using a
4511 // signed 8-bit addition of AL and INT8_MAX.
4512 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4513 // using LAHF/SAHF.
4514 // - When RAX/EAX is live and isn't the destination register, make sure it
4515 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4516 // the flags.
4517 // This approach is ~2.25x faster than using PUSHF/POPF.
4518 //
4519 // This is still somewhat inefficient because we don't know which flags are
4520 // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4521 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4522 //
4523 // PUSHF/POPF is also potentially incorrect because it affects other flags
4524 // such as TF/IF/DF, which LLVM doesn't model.
4525 //
4526 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemerca1c9f02016-01-04 04:49:41 +0000[diff] [blame]4527 // first frame index.
4528 // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4529
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4530 MachineBasicBlock::LivenessQueryResult LQR =
4531 MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI);
4532 // We do not want to save and restore AX if we do not have to.
4533 // Moreover, if we do so whereas AX is dead, we would need to set
4534 // an undef flag on the use of AX, otherwise the verifier will
4535 // complain that we read an undef value.
4536 // We do not want to change the behavior of the machine verifier
4537 // as this is usually wrong to read an undef value.
4538 if (MachineBasicBlock::LQR_Unknown == LQR) {
4539 LivePhysRegs LPR(&getRegisterInfo());
4540 LPR.addLiveOuts(&MBB, /*AddPristinesAndCSRs*/ true);
4541 MachineBasicBlock::iterator I = MBB.end();
4542 while (I != MI) {
4543 --I;
4544 LPR.stepBackward(*I);
4545 }
4546 LQR = LPR.contains(AX) ? MachineBasicBlock::LQR_Live
4547 : MachineBasicBlock::LQR_Dead;
Matthias Braun60d69e22015-12-11 19:42:09 +0000[diff] [blame]4548 }
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4549 bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4550 if (!AXDead)
4551 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4552 if (FromEFLAGS) {
4553 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4554 BuildMI(MBB, MI, DL, get(X86::LAHF));
4555 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4556 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4557 if (ToEFLAGS) {
4558 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4559 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4560 .addReg(X86::AL)
4561 .addImm(INT8_MAX);
4562 BuildMI(MBB, MI, DL, get(X86::SAHF));
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4563 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4564 if (!AXDead)
4565 BuildMI(MBB, MI, DL, get(Pop), AX);
4566 return;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4567 }
4568
4569 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4570 << " to " << RI.getName(DestReg) << '\n');
4571 llvm_unreachable("Cannot emit physreg copy instruction");
4572}
4573
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4574static unsigned getLoadStoreMaskRegOpcode(const TargetRegisterClass *RC,
4575 bool load) {
4576 switch (RC->getSize()) {
4577 default:
4578 llvm_unreachable("Unknown spill size");
4579 case 2:
4580 return load ? X86::KMOVWkm : X86::KMOVWmk;
4581 case 4:
4582 return load ? X86::KMOVDkm : X86::KMOVDmk;
4583 case 8:
4584 return load ? X86::KMOVQkm : X86::KMOVQmk;
4585 }
4586}
4587
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4588static unsigned getLoadStoreRegOpcode(unsigned Reg,
4589 const TargetRegisterClass *RC,
4590 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4591 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4592 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4593 if (STI.hasAVX512()) {
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4594 if (isMaskRegClass(RC))
4595 return getLoadStoreMaskRegOpcode(RC, load);
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4596 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4597 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4598 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4599 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4600 if (X86::VR512RegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4601 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4602 }
4603
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4604 bool HasAVX = STI.hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4605 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]4606 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4607 llvm_unreachable("Unknown spill size");
4608 case 1:
4609 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4610 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4611 // Copying to or from a physical H register on x86-64 requires a NOREX
4612 // move. Otherwise use a normal move.
4613 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4614 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4615 return load ? X86::MOV8rm : X86::MOV8mr;
4616 case 2:
4617 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4618 return load ? X86::MOV16rm : X86::MOV16mr;
4619 case 4:
4620 if (X86::GR32RegClass.hasSubClassEq(RC))
4621 return load ? X86::MOV32rm : X86::MOV32mr;
4622 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4623 return load ?
4624 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4625 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4626 if (X86::RFP32RegClass.hasSubClassEq(RC))
4627 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4628 llvm_unreachable("Unknown 4-byte regclass");
4629 case 8:
4630 if (X86::GR64RegClass.hasSubClassEq(RC))
4631 return load ? X86::MOV64rm : X86::MOV64mr;
4632 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4633 return load ?
4634 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4635 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4636 if (X86::VR64RegClass.hasSubClassEq(RC))
4637 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4638 if (X86::RFP64RegClass.hasSubClassEq(RC))
4639 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4640 llvm_unreachable("Unknown 8-byte regclass");
4641 case 10:
4642 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4643 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4644 case 16: {
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4645 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4646 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4647 // If stack is realigned we can use aligned stores.
4648 if (isStackAligned)
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4649 return load ?
4650 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
4651 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4652 else
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4653 return load ?
4654 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
4655 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4656 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4657 case 32:
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4658 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4659 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4660 // If stack is realigned we can use aligned stores.
4661 if (isStackAligned)
4662 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4663 else
4664 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4665 case 64:
4666 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4667 if (isStackAligned)
4668 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4669 else
4670 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4671 }
4672}
4673
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4674bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
Chad Rosierc27a18f2016-03-09 16:00:35 +0000[diff] [blame]4675 int64_t &Offset,
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4676 const TargetRegisterInfo *TRI) const {
4677 const MCInstrDesc &Desc = MemOp->getDesc();
Craig Topper477649a2016-04-28 05:58:46 +0000[diff] [blame]4678 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4679 if (MemRefBegin < 0)
4680 return false;
4681
4682 MemRefBegin += X86II::getOperandBias(Desc);
4683
Sanjoy Das881de4d2016-02-02 02:32:43 +0000[diff] [blame]4684 MachineOperand &BaseMO = MemOp->getOperand(MemRefBegin + X86::AddrBaseReg);
4685 if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4686 return false;
4687
4688 BaseReg = BaseMO.getReg();
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4689 if (MemOp->getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4690 return false;
4691
4692 if (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
4693 X86::NoRegister)
4694 return false;
4695
4696 const MachineOperand &DispMO = MemOp->getOperand(MemRefBegin + X86::AddrDisp);
4697
4698 // Displacement can be symbolic
4699 if (!DispMO.isImm())
4700 return false;
4701
4702 Offset = DispMO.getImm();
4703
4704 return (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4705 X86::NoRegister);
4706}
4707
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4708static unsigned getStoreRegOpcode(unsigned SrcReg,
4709 const TargetRegisterClass *RC,
4710 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4711 const X86Subtarget &STI) {
4712 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4713}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4714
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4715
4716static unsigned getLoadRegOpcode(unsigned DestReg,
4717 const TargetRegisterClass *RC,
4718 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4719 const X86Subtarget &STI) {
4720 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4721}
4722
4723void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4724 MachineBasicBlock::iterator MI,
4725 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4726 const TargetRegisterClass *RC,
4727 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4728 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]4729 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4730 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4731 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4732 bool isAligned =
4733 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4734 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4735 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4736 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4737 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4738 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4739}
4740
4741void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4742 bool isKill,
4743 SmallVectorImpl<MachineOperand> &Addr,
4744 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4745 MachineInstr::mmo_iterator MMOBegin,
4746 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4747 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4748 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4749 bool isAligned = MMOBegin != MMOEnd &&
4750 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4751 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4752 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4753 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4754 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4755 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4756 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4757 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4758 NewMIs.push_back(MIB);
4759}
4760
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4761
4762void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4763 MachineBasicBlock::iterator MI,
4764 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4765 const TargetRegisterClass *RC,
4766 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4767 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4768 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4769 bool isAligned =
4770 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4771 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4772 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4773 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4774 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4775}
4776
4777void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]4778 SmallVectorImpl<MachineOperand> &Addr,
4779 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4780 MachineInstr::mmo_iterator MMOBegin,
4781 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4782 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4783 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4784 bool isAligned = MMOBegin != MMOEnd &&
4785 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4786 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4787 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4788 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4789 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4790 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4791 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4792 NewMIs.push_back(MIB);
4793}
4794
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4795bool X86InstrInfo::
4796analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
4797 int &CmpMask, int &CmpValue) const {
4798 switch (MI->getOpcode()) {
4799 default: break;
4800 case X86::CMP64ri32:
4801 case X86::CMP64ri8:
4802 case X86::CMP32ri:
4803 case X86::CMP32ri8:
4804 case X86::CMP16ri:
4805 case X86::CMP16ri8:
4806 case X86::CMP8ri:
4807 SrcReg = MI->getOperand(0).getReg();
4808 SrcReg2 = 0;
4809 CmpMask = ~0;
4810 CmpValue = MI->getOperand(1).getImm();
4811 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4812 // A SUB can be used to perform comparison.
4813 case X86::SUB64rm:
4814 case X86::SUB32rm:
4815 case X86::SUB16rm:
4816 case X86::SUB8rm:
4817 SrcReg = MI->getOperand(1).getReg();
4818 SrcReg2 = 0;
4819 CmpMask = ~0;
4820 CmpValue = 0;
4821 return true;
4822 case X86::SUB64rr:
4823 case X86::SUB32rr:
4824 case X86::SUB16rr:
4825 case X86::SUB8rr:
4826 SrcReg = MI->getOperand(1).getReg();
4827 SrcReg2 = MI->getOperand(2).getReg();
4828 CmpMask = ~0;
4829 CmpValue = 0;
4830 return true;
4831 case X86::SUB64ri32:
4832 case X86::SUB64ri8:
4833 case X86::SUB32ri:
4834 case X86::SUB32ri8:
4835 case X86::SUB16ri:
4836 case X86::SUB16ri8:
4837 case X86::SUB8ri:
4838 SrcReg = MI->getOperand(1).getReg();
4839 SrcReg2 = 0;
4840 CmpMask = ~0;
4841 CmpValue = MI->getOperand(2).getImm();
4842 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4843 case X86::CMP64rr:
4844 case X86::CMP32rr:
4845 case X86::CMP16rr:
4846 case X86::CMP8rr:
4847 SrcReg = MI->getOperand(0).getReg();
4848 SrcReg2 = MI->getOperand(1).getReg();
4849 CmpMask = ~0;
4850 CmpValue = 0;
4851 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4852 case X86::TEST8rr:
4853 case X86::TEST16rr:
4854 case X86::TEST32rr:
4855 case X86::TEST64rr:
4856 SrcReg = MI->getOperand(0).getReg();
4857 if (MI->getOperand(1).getReg() != SrcReg) return false;
4858 // Compare against zero.
4859 SrcReg2 = 0;
4860 CmpMask = ~0;
4861 CmpValue = 0;
4862 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4863 }
4864 return false;
4865}
4866
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4867/// Check whether the first instruction, whose only
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4868/// purpose is to update flags, can be made redundant.
4869/// CMPrr can be made redundant by SUBrr if the operands are the same.
4870/// This function can be extended later on.
4871/// SrcReg, SrcRegs: register operands for FlagI.
4872/// ImmValue: immediate for FlagI if it takes an immediate.
4873inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4874 unsigned SrcReg2, int ImmValue,
4875 MachineInstr *OI) {
4876 if (((FlagI->getOpcode() == X86::CMP64rr &&
4877 OI->getOpcode() == X86::SUB64rr) ||
4878 (FlagI->getOpcode() == X86::CMP32rr &&
4879 OI->getOpcode() == X86::SUB32rr)||
4880 (FlagI->getOpcode() == X86::CMP16rr &&
4881 OI->getOpcode() == X86::SUB16rr)||
4882 (FlagI->getOpcode() == X86::CMP8rr &&
4883 OI->getOpcode() == X86::SUB8rr)) &&
4884 ((OI->getOperand(1).getReg() == SrcReg &&
4885 OI->getOperand(2).getReg() == SrcReg2) ||
4886 (OI->getOperand(1).getReg() == SrcReg2 &&
4887 OI->getOperand(2).getReg() == SrcReg)))
4888 return true;
4889
4890 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4891 OI->getOpcode() == X86::SUB64ri32) ||
4892 (FlagI->getOpcode() == X86::CMP64ri8 &&
4893 OI->getOpcode() == X86::SUB64ri8) ||
4894 (FlagI->getOpcode() == X86::CMP32ri &&
4895 OI->getOpcode() == X86::SUB32ri) ||
4896 (FlagI->getOpcode() == X86::CMP32ri8 &&
4897 OI->getOpcode() == X86::SUB32ri8) ||
4898 (FlagI->getOpcode() == X86::CMP16ri &&
4899 OI->getOpcode() == X86::SUB16ri) ||
4900 (FlagI->getOpcode() == X86::CMP16ri8 &&
4901 OI->getOpcode() == X86::SUB16ri8) ||
4902 (FlagI->getOpcode() == X86::CMP8ri &&
4903 OI->getOpcode() == X86::SUB8ri)) &&
4904 OI->getOperand(1).getReg() == SrcReg &&
4905 OI->getOperand(2).getImm() == ImmValue)
4906 return true;
4907 return false;
4908}
4909
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4910/// Check whether the definition can be converted
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4911/// to remove a comparison against zero.
4912inline static bool isDefConvertible(MachineInstr *MI) {
4913 switch (MI->getOpcode()) {
4914 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]4915
4916 // The shift instructions only modify ZF if their shift count is non-zero.
4917 // N.B.: The processor truncates the shift count depending on the encoding.
4918 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
4919 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
4920 return getTruncatedShiftCount(MI, 2) != 0;
4921
4922 // Some left shift instructions can be turned into LEA instructions but only
4923 // if their flags aren't used. Avoid transforming such instructions.
4924 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
4925 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4926 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4927 return ShAmt != 0;
4928 }
4929
4930 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4931 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4932 return getTruncatedShiftCount(MI, 3) != 0;
4933
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4934 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4935 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
4936 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
4937 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
4938 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4939 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4940 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4941 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
4942 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
4943 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
4944 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4945 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4946 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4947 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
4948 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
4949 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
4950 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
4951 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4952 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
4953 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
4954 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
4955 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
4956 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
4957 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
4958 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
4959 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
4960 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4961 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4962 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4963 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4964 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
4965 case X86::ADC32ri: case X86::ADC32ri8:
4966 case X86::ADC32rr: case X86::ADC64ri32:
4967 case X86::ADC64ri8: case X86::ADC64rr:
4968 case X86::SBB32ri: case X86::SBB32ri8:
4969 case X86::SBB32rr: case X86::SBB64ri32:
4970 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]4971 case X86::ANDN32rr: case X86::ANDN32rm:
4972 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4973 case X86::BEXTR32rr: case X86::BEXTR64rr:
4974 case X86::BEXTR32rm: case X86::BEXTR64rm:
4975 case X86::BLSI32rr: case X86::BLSI32rm:
4976 case X86::BLSI64rr: case X86::BLSI64rm:
4977 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4978 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4979 case X86::BLSR32rr: case X86::BLSR32rm:
4980 case X86::BLSR64rr: case X86::BLSR64rm:
4981 case X86::BZHI32rr: case X86::BZHI32rm:
4982 case X86::BZHI64rr: case X86::BZHI64rm:
4983 case X86::LZCNT16rr: case X86::LZCNT16rm:
4984 case X86::LZCNT32rr: case X86::LZCNT32rm:
4985 case X86::LZCNT64rr: case X86::LZCNT64rm:
4986 case X86::POPCNT16rr:case X86::POPCNT16rm:
4987 case X86::POPCNT32rr:case X86::POPCNT32rm:
4988 case X86::POPCNT64rr:case X86::POPCNT64rm:
4989 case X86::TZCNT16rr: case X86::TZCNT16rm:
4990 case X86::TZCNT32rr: case X86::TZCNT32rm:
4991 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4992 return true;
4993 }
4994}
4995
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4996/// Check whether the use can be converted to remove a comparison against zero.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4997static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
4998 switch (MI->getOpcode()) {
4999 default: return X86::COND_INVALID;
5000 case X86::LZCNT16rr: case X86::LZCNT16rm:
5001 case X86::LZCNT32rr: case X86::LZCNT32rm:
5002 case X86::LZCNT64rr: case X86::LZCNT64rm:
5003 return X86::COND_B;
5004 case X86::POPCNT16rr:case X86::POPCNT16rm:
5005 case X86::POPCNT32rr:case X86::POPCNT32rm:
5006 case X86::POPCNT64rr:case X86::POPCNT64rm:
5007 return X86::COND_E;
5008 case X86::TZCNT16rr: case X86::TZCNT16rm:
5009 case X86::TZCNT32rr: case X86::TZCNT32rm:
5010 case X86::TZCNT64rr: case X86::TZCNT64rm:
5011 return X86::COND_B;
5012 }
5013}
5014
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5015/// Check if there exists an earlier instruction that
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5016/// operates on the same source operands and sets flags in the same way as
5017/// Compare; remove Compare if possible.
5018bool X86InstrInfo::
5019optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
5020 int CmpMask, int CmpValue,
5021 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5022 // Check whether we can replace SUB with CMP.
5023 unsigned NewOpcode = 0;
5024 switch (CmpInstr->getOpcode()) {
5025 default: break;
5026 case X86::SUB64ri32:
5027 case X86::SUB64ri8:
5028 case X86::SUB32ri:
5029 case X86::SUB32ri8:
5030 case X86::SUB16ri:
5031 case X86::SUB16ri8:
5032 case X86::SUB8ri:
5033 case X86::SUB64rm:
5034 case X86::SUB32rm:
5035 case X86::SUB16rm:
5036 case X86::SUB8rm:
5037 case X86::SUB64rr:
5038 case X86::SUB32rr:
5039 case X86::SUB16rr:
5040 case X86::SUB8rr: {
5041 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
5042 return false;
5043 // There is no use of the destination register, we can replace SUB with CMP.
5044 switch (CmpInstr->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5045 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5046 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
5047 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
5048 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
5049 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
5050 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
5051 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
5052 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
5053 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
5054 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5055 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
5056 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
5057 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
5058 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
5059 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
5060 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
5061 }
5062 CmpInstr->setDesc(get(NewOpcode));
5063 CmpInstr->RemoveOperand(0);
5064 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5065 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5066 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5067 return false;
5068 }
5069 }
5070
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5071 // Get the unique definition of SrcReg.
5072 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5073 if (!MI) return false;
5074
5075 // CmpInstr is the first instruction of the BB.
5076 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5077
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5078 // If we are comparing against zero, check whether we can use MI to update
5079 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5080 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5081 if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5082 return false;
5083
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5084 // If we have a use of the source register between the def and our compare
5085 // instruction we can eliminate the compare iff the use sets EFLAGS in the
5086 // right way.
5087 bool ShouldUpdateCC = false;
5088 X86::CondCode NewCC = X86::COND_INVALID;
5089 if (IsCmpZero && !isDefConvertible(MI)) {
5090 // Scan forward from the use until we hit the use we're looking for or the
5091 // compare instruction.
5092 for (MachineBasicBlock::iterator J = MI;; ++J) {
5093 // Do we have a convertible instruction?
5094 NewCC = isUseDefConvertible(J);
5095 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5096 J->getOperand(1).getReg() == SrcReg) {
5097 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5098 ShouldUpdateCC = true; // Update CC later on.
5099 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5100 // with the new def.
5101 MI = Def = J;
5102 break;
5103 }
5104
5105 if (J == I)
5106 return false;
5107 }
5108 }
5109
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5110 // We are searching for an earlier instruction that can make CmpInstr
5111 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5112 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5113 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5114
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5115 // We iterate backward, starting from the instruction before CmpInstr and
5116 // stop when reaching the definition of a source register or done with the BB.
5117 // RI points to the instruction before CmpInstr.
5118 // If the definition is in this basic block, RE points to the definition;
5119 // otherwise, RE is the rend of the basic block.
5120 MachineBasicBlock::reverse_iterator
5121 RI = MachineBasicBlock::reverse_iterator(I),
5122 RE = CmpInstr->getParent() == MI->getParent() ?
5123 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
5124 CmpInstr->getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5125 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5126 for (; RI != RE; ++RI) {
5127 MachineInstr *Instr = &*RI;
5128 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5129 if (!IsCmpZero &&
5130 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5131 Sub = Instr;
5132 break;
5133 }
5134
5135 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5136 Instr->readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5137 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5138
5139 // MOV32r0 etc. are implemented with xor which clobbers condition code.
5140 // They are safe to move up, if the definition to EFLAGS is dead and
5141 // earlier instructions do not read or write EFLAGS.
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5142 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5143 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
5144 Movr0Inst = Instr;
5145 continue;
5146 }
5147
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5148 // We can't remove CmpInstr.
5149 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5150 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5151 }
5152
5153 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5154 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5155 return false;
5156
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5157 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5158 Sub->getOperand(2).getReg() == SrcReg);
5159
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5160 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5161 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5162 // If we are done with the basic block, we need to check whether EFLAGS is
5163 // live-out.
5164 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5165 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
5166 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
5167 for (++I; I != E; ++I) {
5168 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5169 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5170 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5171 // We should check the usage if this instruction uses and updates EFLAGS.
5172 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5173 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5174 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5175 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5176 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5177 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5178 continue;
5179
5180 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]5181 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5182 bool OpcIsSET = false;
5183 if (IsCmpZero || IsSwapped) {
5184 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5185 if (Instr.isBranch())
5186 OldCC = getCondFromBranchOpc(Instr.getOpcode());
5187 else {
5188 OldCC = getCondFromSETOpc(Instr.getOpcode());
5189 if (OldCC != X86::COND_INVALID)
5190 OpcIsSET = true;
5191 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]5192 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5193 }
5194 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5195 }
5196 if (IsCmpZero) {
5197 switch (OldCC) {
5198 default: break;
5199 case X86::COND_A: case X86::COND_AE:
5200 case X86::COND_B: case X86::COND_BE:
5201 case X86::COND_G: case X86::COND_GE:
5202 case X86::COND_L: case X86::COND_LE:
5203 case X86::COND_O: case X86::COND_NO:
5204 // CF and OF are used, we can't perform this optimization.
5205 return false;
5206 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5207
5208 // If we're updating the condition code check if we have to reverse the
5209 // condition.
5210 if (ShouldUpdateCC)
5211 switch (OldCC) {
5212 default:
5213 return false;
5214 case X86::COND_E:
5215 break;
5216 case X86::COND_NE:
5217 NewCC = GetOppositeBranchCondition(NewCC);
5218 break;
5219 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5220 } else if (IsSwapped) {
5221 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5222 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5223 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5224 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5225 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5226 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5227
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5228 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5229 // Synthesize the new opcode.
5230 bool HasMemoryOperand = Instr.hasOneMemOperand();
5231 unsigned NewOpc;
5232 if (Instr.isBranch())
5233 NewOpc = GetCondBranchFromCond(NewCC);
5234 else if(OpcIsSET)
5235 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5236 else {
5237 unsigned DstReg = Instr.getOperand(0).getReg();
5238 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5239 HasMemoryOperand);
5240 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5241
5242 // Push the MachineInstr to OpsToUpdate.
5243 // If it is safe to remove CmpInstr, the condition code of these
5244 // instructions will be modified.
5245 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5246 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5247 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5248 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5249 IsSafe = true;
5250 break;
5251 }
5252 }
5253
5254 // If EFLAGS is not killed nor re-defined, we should check whether it is
5255 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5256 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5257 MachineBasicBlock *MBB = CmpInstr->getParent();
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5258 for (MachineBasicBlock *Successor : MBB->successors())
5259 if (Successor->isLiveIn(X86::EFLAGS))
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5260 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5261 }
5262
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5263 // The instruction to be updated is either Sub or MI.
5264 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5265 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5266 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5267 // Look backwards until we find a def that doesn't use the current EFLAGS.
5268 Def = Sub;
5269 MachineBasicBlock::reverse_iterator
5270 InsertI = MachineBasicBlock::reverse_iterator(++Def),
5271 InsertE = Sub->getParent()->rend();
5272 for (; InsertI != InsertE; ++InsertI) {
5273 MachineInstr *Instr = &*InsertI;
5274 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5275 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5276 Sub->getParent()->remove(Movr0Inst);
5277 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5278 Movr0Inst);
5279 break;
5280 }
5281 }
5282 if (InsertI == InsertE)
5283 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5284 }
5285
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]5286 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5287 unsigned i = 0, e = Sub->getNumOperands();
5288 for (; i != e; ++i) {
5289 MachineOperand &MO = Sub->getOperand(i);
5290 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5291 MO.setIsDead(false);
5292 break;
5293 }
5294 }
5295 assert(i != e && "Unable to locate a def EFLAGS operand");
5296
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5297 CmpInstr->eraseFromParent();
5298
5299 // Modify the condition code of instructions in OpsToUpdate.
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5300 for (auto &Op : OpsToUpdate)
5301 Op.first->setDesc(get(Op.second));
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5302 return true;
5303}
5304
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5305/// Try to remove the load by folding it to a register
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5306/// operand at the use. We fold the load instructions if load defines a virtual
5307/// register, the virtual register is used once in the same BB, and the
5308/// instructions in-between do not load or store, and have no side effects.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5309MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
5310 const MachineRegisterInfo *MRI,
5311 unsigned &FoldAsLoadDefReg,
5312 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5313 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5314 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5315 // To be conservative, if there exists another load, clear the load candidate.
5316 if (MI->mayLoad()) {
5317 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5318 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5319 }
5320
5321 // Check whether we can move DefMI here.
5322 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5323 assert(DefMI);
5324 bool SawStore = false;
Matthias Braun07066cc2015-05-19 21:22:20 +0000[diff] [blame]5325 if (!DefMI->isSafeToMove(nullptr, SawStore))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5326 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5327
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5328 // Collect information about virtual register operands of MI.
5329 unsigned SrcOperandId = 0;
5330 bool FoundSrcOperand = false;
5331 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
5332 MachineOperand &MO = MI->getOperand(i);
5333 if (!MO.isReg())
5334 continue;
5335 unsigned Reg = MO.getReg();
5336 if (Reg != FoldAsLoadDefReg)
5337 continue;
5338 // Do not fold if we have a subreg use or a def or multiple uses.
5339 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5340 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5341
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5342 SrcOperandId = i;
5343 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5344 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5345 if (!FoundSrcOperand)
5346 return nullptr;
5347
5348 // Check whether we can fold the def into SrcOperandId.
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5349 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI)) {
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5350 FoldAsLoadDefReg = 0;
5351 return FoldMI;
5352 }
5353
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5354 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5355}
5356
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5357/// Expand a single-def pseudo instruction to a two-addr
5358/// instruction with two undef reads of the register being defined.
5359/// This is used for mapping:
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5360/// %xmm4 = V_SET0
5361/// to:
5362/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5363///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5364static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5365 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5366 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5367 unsigned Reg = MIB->getOperand(0).getReg();
5368 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5369
5370 // MachineInstr::addOperand() will insert explicit operands before any
5371 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5372 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5373 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5374 assert(MIB->getOperand(1).getReg() == Reg &&
5375 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5376 return true;
5377}
5378
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5379/// Expand a single-def pseudo instruction to a two-addr
5380/// instruction with two %k0 reads.
5381/// This is used for mapping:
5382/// %k4 = K_SET1
5383/// to:
5384/// %k4 = KXNORrr %k0, %k0
5385static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5386 const MCInstrDesc &Desc, unsigned Reg) {
5387 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5388 MIB->setDesc(Desc);
5389 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5390 return true;
5391}
5392
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5393static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5394 bool MinusOne) {
5395 MachineBasicBlock &MBB = *MIB->getParent();
5396 DebugLoc DL = MIB->getDebugLoc();
5397 unsigned Reg = MIB->getOperand(0).getReg();
5398
5399 // Insert the XOR.
5400 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5401 .addReg(Reg, RegState::Undef)
5402 .addReg(Reg, RegState::Undef);
5403
5404 // Turn the pseudo into an INC or DEC.
5405 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5406 MIB.addReg(Reg);
5407
5408 return true;
5409}
5410
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5411bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5412 MachineBasicBlock &MBB = *MIB->getParent();
5413 DebugLoc DL = MIB->getDebugLoc();
5414 int64_t Imm = MIB->getOperand(1).getImm();
5415 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5416 MachineBasicBlock::iterator I = MIB.getInstr();
5417
5418 int StackAdjustment;
5419
5420 if (Subtarget.is64Bit()) {
5421 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5422 MIB->getOpcode() == X86::MOV32ImmSExti8);
5423
5424 // Can't use push/pop lowering if the function might write to the red zone.
5425 X86MachineFunctionInfo *X86FI =
5426 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5427 if (X86FI->getUsesRedZone()) {
5428 MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5429 : X86::MOV64ri));
5430 return true;
5431 }
5432
5433 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5434 // widen the register if necessary.
5435 StackAdjustment = 8;
5436 BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5437 MIB->setDesc(get(X86::POP64r));
5438 MIB->getOperand(0)
5439 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5440 } else {
5441 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5442 StackAdjustment = 4;
5443 BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5444 MIB->setDesc(get(X86::POP32r));
5445 }
5446
5447 // Build CFI if necessary.
5448 MachineFunction &MF = *MBB.getParent();
5449 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5450 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5451 bool NeedsDwarfCFI =
5452 !IsWin64Prologue &&
5453 (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5454 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5455 if (EmitCFI) {
5456 TFL->BuildCFI(MBB, I, DL,
5457 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5458 TFL->BuildCFI(MBB, std::next(I), DL,
5459 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5460 }
5461
5462 return true;
5463}
5464
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5465// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5466// code sequence is needed for other targets.
5467static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5468 const TargetInstrInfo &TII) {
5469 MachineBasicBlock &MBB = *MIB->getParent();
5470 DebugLoc DL = MIB->getDebugLoc();
5471 unsigned Reg = MIB->getOperand(0).getReg();
5472 const GlobalValue *GV =
5473 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
5474 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]5475 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
5476 MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]5477 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5478
5479 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5480 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5481 .addMemOperand(MMO);
5482 MIB->setDebugLoc(DL);
5483 MIB->setDesc(TII.get(X86::MOV64rm));
5484 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5485}
5486
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5487bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5488 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5489 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5490 switch (MI->getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]5491 case X86::MOV32r0:
5492 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5493 case X86::MOV32r1:
5494 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5495 case X86::MOV32r_1:
5496 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5497 case X86::MOV32ImmSExti8:
5498 case X86::MOV64ImmSExti8:
5499 return ExpandMOVImmSExti8(MIB);
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5500 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5501 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5502 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5503 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5504 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5505 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5506 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5507 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5508 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5509 case X86::FsFLD0SS:
5510 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5511 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5512 case X86::AVX_SET0:
5513 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5514 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5515 case X86::AVX512_512_SET0:
5516 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5517 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5518 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5519 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5520 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5521 case X86::TEST8ri_NOREX:
5522 MI->setDesc(get(X86::TEST8ri));
5523 return true;
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5524 case X86::MOV32ri64:
5525 MI->setDesc(get(X86::MOV32ri));
5526 return true;
5527
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5528 // KNL does not recognize dependency-breaking idioms for mask registers,
5529 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5530 // Using %k0 as the undef input register is a performance heuristic based
5531 // on the assumption that %k0 is used less frequently than the other mask
5532 // registers, since it is not usable as a write mask.
5533 // FIXME: A more advanced approach would be to choose the best input mask
5534 // register based on context.
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]5535 case X86::KSET0B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5536 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5537 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5538 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5539 case X86::KSET1B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5540 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5541 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5542 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5543 case TargetOpcode::LOAD_STACK_GUARD:
5544 expandLoadStackGuard(MIB, *this);
5545 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5546 }
5547 return false;
5548}
5549
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5550static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5551 int PtrOffset = 0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5552 unsigned NumAddrOps = MOs.size();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5553
5554 if (NumAddrOps < 4) {
5555 // FrameIndex only - add an immediate offset (whether its zero or not).
5556 for (unsigned i = 0; i != NumAddrOps; ++i)
5557 MIB.addOperand(MOs[i]);
5558 addOffset(MIB, PtrOffset);
5559 } else {
5560 // General Memory Addressing - we need to add any offset to an existing
5561 // offset.
5562 assert(MOs.size() == 5 && "Unexpected memory operand list length");
5563 for (unsigned i = 0; i != NumAddrOps; ++i) {
5564 const MachineOperand &MO = MOs[i];
5565 if (i == 3 && PtrOffset != 0) {
Simon Pilgrimae0140d2015-11-19 21:50:57 +0000[diff] [blame]5566 MIB.addDisp(MO, PtrOffset);
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5567 } else {
5568 MIB.addOperand(MO);
5569 }
5570 }
5571 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5572}
5573
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]5574static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5575 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5576 MachineBasicBlock::iterator InsertPt,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]5577 MachineInstr *MI,
5578 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5579 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5580 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]5581 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5582 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5583 MachineInstrBuilder MIB(MF, NewMI);
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5584 addOperands(MIB, MOs);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5585
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5586 // Loop over the rest of the ri operands, converting them over.
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]5587 unsigned NumOps = MI->getDesc().getNumOperands()-2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5588 for (unsigned i = 0; i != NumOps; ++i) {
5589 MachineOperand &MO = MI->getOperand(i+2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5590 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5591 }
5592 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
5593 MachineOperand &MO = MI->getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5594 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5595 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5596
5597 MachineBasicBlock *MBB = InsertPt->getParent();
5598 MBB->insert(InsertPt, NewMI);
5599
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5600 return MIB;
5601}
5602
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5603static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5604 unsigned OpNo, ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5605 MachineBasicBlock::iterator InsertPt,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5606 MachineInstr *MI, const TargetInstrInfo &TII,
5607 int PtrOffset = 0) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5608 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]5609 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5610 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5611 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5612
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5613 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5614 MachineOperand &MO = MI->getOperand(i);
5615 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5616 assert(MO.isReg() && "Expected to fold into reg operand!");
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5617 addOperands(MIB, MOs, PtrOffset);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5618 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5619 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5620 }
5621 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5622
5623 MachineBasicBlock *MBB = InsertPt->getParent();
5624 MBB->insert(InsertPt, NewMI);
5625
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5626 return MIB;
5627}
5628
5629static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5630 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5631 MachineBasicBlock::iterator InsertPt,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5632 MachineInstr *MI) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5633 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5634 MI->getDebugLoc(), TII.get(Opcode));
5635 addOperands(MIB, MOs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5636 return MIB.addImm(0);
5637}
5638
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5639MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5640 MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5641 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5642 unsigned Size, unsigned Align) const {
5643 switch (MI->getOpcode()) {
5644 case X86::INSERTPSrr:
5645 case X86::VINSERTPSrr:
5646 // Attempt to convert the load of inserted vector into a fold load
5647 // of a single float.
5648 if (OpNum == 2) {
5649 unsigned Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
5650 unsigned ZMask = Imm & 15;
5651 unsigned DstIdx = (Imm >> 4) & 3;
5652 unsigned SrcIdx = (Imm >> 6) & 3;
5653
5654 unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5655 if (Size <= RCSize && 4 <= Align) {
5656 int PtrOffset = SrcIdx * 4;
5657 unsigned NewImm = (DstIdx << 4) | ZMask;
5658 unsigned NewOpCode =
5659 (MI->getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
5660 : X86::INSERTPSrm);
5661 MachineInstr *NewMI =
5662 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5663 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5664 return NewMI;
5665 }
5666 }
5667 break;
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5668 case X86::MOVHLPSrr:
5669 case X86::VMOVHLPSrr:
5670 // Move the upper 64-bits of the second operand to the lower 64-bits.
5671 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5672 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5673 if (OpNum == 2) {
5674 unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5675 if (Size <= RCSize && 8 <= Align) {
5676 unsigned NewOpCode =
5677 (MI->getOpcode() == X86::VMOVHLPSrr ? X86::VMOVLPSrm
5678 : X86::MOVLPSrm);
5679 MachineInstr *NewMI =
5680 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5681 return NewMI;
5682 }
5683 }
5684 break;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5685 };
5686
5687 return nullptr;
5688}
5689
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5690MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5691 MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5692 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5693 unsigned Size, unsigned Align, bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5694 const DenseMap<unsigned,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]5695 std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5696 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5697 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5698
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]5699 // For CPUs that favor the register form of a call or push,
5700 // do not fold loads into calls or pushes, unless optimizing for size
5701 // aggressively.
Sanjay Patel924879a2015-08-04 15:49:57 +0000[diff] [blame]5702 if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]5703 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r ||
5704 MI->getOpcode() == X86::PUSH16r || MI->getOpcode() == X86::PUSH32r ||
5705 MI->getOpcode() == X86::PUSH64r))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5706 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5707
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]5708 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5709 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5710 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5711
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5712 // FIXME: AsmPrinter doesn't know how to handle
5713 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5714 if (MI->getOpcode() == X86::ADD32ri &&
5715 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5716 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5717
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5718 MachineInstr *NewMI = nullptr;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5719
5720 // Attempt to fold any custom cases we have.
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5721 if (MachineInstr *CustomMI =
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5722 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5723 return CustomMI;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5724
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5725 // Folding a memory location into the two-address part of a two-address
5726 // instruction is different than folding it other places. It requires
5727 // replacing the *two* registers with the memory location.
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5728 if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5729 MI->getOperand(0).isReg() &&
5730 MI->getOperand(1).isReg() &&
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5731 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5732 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5733 isTwoAddrFold = true;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5734 } else if (OpNum == 0) {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5735 if (MI->getOpcode() == X86::MOV32r0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5736 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5737 if (NewMI)
5738 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]5739 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5740
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5741 OpcodeTablePtr = &RegOp2MemOpTable0;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5742 } else if (OpNum == 1) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5743 OpcodeTablePtr = &RegOp2MemOpTable1;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5744 } else if (OpNum == 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5745 OpcodeTablePtr = &RegOp2MemOpTable2;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5746 } else if (OpNum == 3) {
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]5747 OpcodeTablePtr = &RegOp2MemOpTable3;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5748 } else if (OpNum == 4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]5749 OpcodeTablePtr = &RegOp2MemOpTable4;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5750 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5751
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5752 // If table selected...
5753 if (OpcodeTablePtr) {
5754 // Find the Opcode to fuse
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]5755 auto I = OpcodeTablePtr->find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5756 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5757 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5758 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]5759 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5760 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5761 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5762 if (Size) {
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5763 unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5764 if (Size < RCSize) {
5765 // Check if it's safe to fold the load. If the size of the object is
5766 // narrower than the load width, then it's not.
5767 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5768 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5769 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5770 // a 32-bit load which is implicitly zero-extended. This likely is
5771 // due to live interval analysis remat'ing a load from stack slot.
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5772 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5773 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5774 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5775 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5776 }
5777 }
5778
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5779 if (isTwoAddrFold)
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5780 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5781 else
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5782 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5783
5784 if (NarrowToMOV32rm) {
5785 // If this is the special case where we use a MOV32rm to load a 32-bit
5786 // value and zero-extend the top bits. Change the destination register
5787 // to a 32-bit one.
5788 unsigned DstReg = NewMI->getOperand(0).getReg();
5789 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5790 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5791 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]5792 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5793 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5794 return NewMI;
5795 }
5796 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5797
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5798 // If the instruction and target operand are commutable, commute the
5799 // instruction and try again.
5800 if (AllowCommute) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5801 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5802 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5803 bool HasDef = MI->getDesc().getNumDefs();
5804 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
5805 unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
5806 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5807 bool Tied1 =
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5808 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5809 bool Tied2 =
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5810 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5811
5812 // If either of the commutable operands are tied to the destination
5813 // then we can not commute + fold.
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5814 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5815 (HasDef && Reg0 == Reg2 && Tied2))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5816 return nullptr;
5817
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5818 MachineInstr *CommutedMI =
5819 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5820 if (!CommutedMI) {
5821 // Unable to commute.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5822 return nullptr;
5823 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5824 if (CommutedMI != MI) {
5825 // New instruction. We can't fold from this.
5826 CommutedMI->eraseFromParent();
5827 return nullptr;
5828 }
5829
5830 // Attempt to fold with the commuted version of the instruction.
5831 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5832 Size, Align, /*AllowCommute=*/false);
5833 if (NewMI)
5834 return NewMI;
5835
5836 // Folding failed again - undo the commute before returning.
5837 MachineInstr *UncommutedMI =
5838 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5839 if (!UncommutedMI) {
5840 // Unable to commute.
5841 return nullptr;
5842 }
5843 if (UncommutedMI != MI) {
5844 // New instruction. It doesn't need to be kept.
5845 UncommutedMI->eraseFromParent();
5846 return nullptr;
5847 }
5848
5849 // Return here to prevent duplicate fuse failure report.
5850 return nullptr;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5851 }
5852 }
5853
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5854 // No fusion
Jakob Stoklund Olesen51702ec2010-07-09 20:43:09 +0000[diff] [blame]5855 if (PrintFailedFusing && !MI->isCopy())
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5856 dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5857 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5858}
5859
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5860/// Return true for all instructions that only update
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5861/// the first 32 or 64-bits of the destination register and leave the rest
5862/// unmodified. This can be used to avoid folding loads if the instructions
5863/// only update part of the destination register, and the non-updated part is
5864/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5865/// instructions breaks the partial register dependency and it can improve
5866/// performance. e.g.:
5867///
5868/// movss (%rdi), %xmm0
5869/// cvtss2sd %xmm0, %xmm0
5870///
5871/// Instead of
5872/// cvtss2sd (%rdi), %xmm0
5873///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]5874/// FIXME: This should be turned into a TSFlags.
5875///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5876static bool hasPartialRegUpdate(unsigned Opcode) {
5877 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5878 case X86::CVTSI2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5879 case X86::CVTSI2SSrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5880 case X86::CVTSI2SS64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5881 case X86::CVTSI2SS64rm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5882 case X86::CVTSI2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5883 case X86::CVTSI2SDrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5884 case X86::CVTSI2SD64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5885 case X86::CVTSI2SD64rm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5886 case X86::CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5887 case X86::CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5888 case X86::Int_CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5889 case X86::Int_CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5890 case X86::CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5891 case X86::CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5892 case X86::Int_CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5893 case X86::Int_CVTSS2SDrm:
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5894 case X86::MOVHPDrm:
5895 case X86::MOVHPSrm:
5896 case X86::MOVLPDrm:
5897 case X86::MOVLPSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5898 case X86::RCPSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5899 case X86::RCPSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5900 case X86::RCPSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5901 case X86::RCPSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5902 case X86::ROUNDSDr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5903 case X86::ROUNDSDm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]5904 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5905 case X86::ROUNDSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5906 case X86::ROUNDSSm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]5907 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5908 case X86::RSQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5909 case X86::RSQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5910 case X86::RSQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5911 case X86::RSQRTSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5912 case X86::SQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5913 case X86::SQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5914 case X86::SQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5915 case X86::SQRTSSm_Int:
5916 case X86::SQRTSDr:
5917 case X86::SQRTSDm:
5918 case X86::SQRTSDr_Int:
5919 case X86::SQRTSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5920 return true;
5921 }
5922
5923 return false;
5924}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5925
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5926/// Inform the ExeDepsFix pass how many idle
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5927/// instructions we would like before a partial register update.
5928unsigned X86InstrInfo::
5929getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
5930 const TargetRegisterInfo *TRI) const {
5931 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
5932 return 0;
5933
5934 // If MI is marked as reading Reg, the partial register update is wanted.
5935 const MachineOperand &MO = MI->getOperand(0);
5936 unsigned Reg = MO.getReg();
5937 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
5938 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
5939 return 0;
5940 } else {
5941 if (MI->readsRegister(Reg, TRI))
5942 return 0;
5943 }
5944
5945 // If any of the preceding 16 instructions are reading Reg, insert a
5946 // dependency breaking instruction. The magic number is based on a few
5947 // Nehalem experiments.
5948 return 16;
5949}
5950
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5951// Return true for any instruction the copies the high bits of the first source
5952// operand into the unused high bits of the destination operand.
5953static bool hasUndefRegUpdate(unsigned Opcode) {
5954 switch (Opcode) {
5955 case X86::VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5956 case X86::VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5957 case X86::Int_VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5958 case X86::Int_VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5959 case X86::VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5960 case X86::VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5961 case X86::Int_VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5962 case X86::Int_VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5963 case X86::VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5964 case X86::VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5965 case X86::Int_VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5966 case X86::Int_VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5967 case X86::VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5968 case X86::VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5969 case X86::Int_VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5970 case X86::Int_VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5971 case X86::VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5972 case X86::VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5973 case X86::Int_VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5974 case X86::Int_VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5975 case X86::VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5976 case X86::VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5977 case X86::Int_VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5978 case X86::Int_VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5979 case X86::VRCPSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5980 case X86::VRCPSSm:
5981 case X86::VRCPSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5982 case X86::VROUNDSDr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5983 case X86::VROUNDSDm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5984 case X86::VROUNDSDr_Int:
5985 case X86::VROUNDSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5986 case X86::VROUNDSSm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5987 case X86::VROUNDSSr_Int:
5988 case X86::VRSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5989 case X86::VRSQRTSSm:
5990 case X86::VRSQRTSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5991 case X86::VSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5992 case X86::VSQRTSSm:
5993 case X86::VSQRTSSm_Int:
5994 case X86::VSQRTSDr:
5995 case X86::VSQRTSDm:
5996 case X86::VSQRTSDm_Int:
5997 // AVX-512
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5998 case X86::VCVTSD2SSZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5999 case X86::VCVTSD2SSZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6000 case X86::VCVTSS2SDZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6001 case X86::VCVTSS2SDZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6002 return true;
6003 }
6004
6005 return false;
6006}
6007
6008/// Inform the ExeDepsFix pass how many idle instructions we would like before
6009/// certain undef register reads.
6010///
6011/// This catches the VCVTSI2SD family of instructions:
6012///
6013/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6014///
6015/// We should to be careful *not* to catch VXOR idioms which are presumably
6016/// handled specially in the pipeline:
6017///
6018/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6019///
6020/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6021/// high bits that are passed-through are not live.
6022unsigned X86InstrInfo::
6023getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
6024 const TargetRegisterInfo *TRI) const {
6025 if (!hasUndefRegUpdate(MI->getOpcode()))
6026 return 0;
6027
6028 // Set the OpNum parameter to the first source operand.
6029 OpNum = 1;
6030
6031 const MachineOperand &MO = MI->getOperand(OpNum);
6032 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
6033 // Use the same magic number as getPartialRegUpdateClearance.
6034 return 16;
6035 }
6036 return 0;
6037}
6038
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6039void X86InstrInfo::
6040breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
6041 const TargetRegisterInfo *TRI) const {
6042 unsigned Reg = MI->getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6043 // If MI kills this register, the false dependence is already broken.
6044 if (MI->killsRegister(Reg, TRI))
6045 return;
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6046
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6047 if (X86::VR128RegClass.contains(Reg)) {
6048 // These instructions are all floating point domain, so xorps is the best
6049 // choice.
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6050 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6051 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
6052 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6053 MI->addRegisterKilled(Reg, TRI, true);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6054 } else if (X86::VR256RegClass.contains(Reg)) {
6055 // Use vxorps to clear the full ymm register.
6056 // It wants to read and write the xmm sub-register.
6057 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
6058 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
6059 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
6060 .addReg(Reg, RegState::ImplicitDefine);
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6061 MI->addRegisterKilled(Reg, TRI, true);
6062 }
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6063}
6064
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6065MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6066 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
6067 MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6068 // Check switch flag
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6069 if (NoFusing)
6070 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6071
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6072 // Unless optimizing for size, don't fold to avoid partial
6073 // register update stalls
Sanjay Patel10294b52015-08-10 17:15:17 +0000[diff] [blame]6074 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6075 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6076
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6077 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6078 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6079 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]6080 // If the function stack isn't realigned we don't want to fold instructions
6081 // that need increased alignment.
6082 if (!RI.needsStackRealignment(MF))
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6083 Alignment =
6084 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6085 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6086 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6087 unsigned RCSize = 0;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6088 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6089 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6090 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]6091 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6092 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6093 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6094 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6095 // Check if it's safe to fold the load. If the size of the object is
6096 // narrower than the load width, then it's not.
6097 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6098 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6099 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]6100 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6101 MI->getOperand(1).ChangeToImmediate(0);
6102 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6103 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6104
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]6105 return foldMemoryOperandImpl(MF, MI, Ops[0],
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6106 MachineOperand::CreateFI(FrameIndex), InsertPt,
6107 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6108}
6109
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6110/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6111/// because the latter uses contents that wouldn't be defined in the folded
6112/// version. For instance, this transformation isn't legal:
6113/// movss (%rdi), %xmm0
6114/// addps %xmm0, %xmm0
6115/// ->
6116/// addps (%rdi), %xmm0
6117///
6118/// But this one is:
6119/// movss (%rdi), %xmm0
6120/// addss %xmm0, %xmm0
6121/// ->
6122/// addss (%rdi), %xmm0
6123///
6124static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6125 const MachineInstr &UserMI,
6126 const MachineFunction &MF) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6127 unsigned Opc = LoadMI.getOpcode();
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6128 unsigned UserOpc = UserMI.getOpcode();
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6129 unsigned RegSize =
6130 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6131
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6132 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6133 // These instructions only load 32 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6134 // destination register is wider than 32 bits (4 bytes), and its user
6135 // instruction isn't scalar (SS).
6136 switch (UserOpc) {
6137 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
6138 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
6139 case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
6140 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
Vyacheslav Klochkoved865df2015-11-26 07:45:30 +0000[diff] [blame]6141 case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int:
6142 case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int:
6143 case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int:
6144 case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int:
6145 case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int:
6146 case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6147 return false;
6148 default:
6149 return true;
6150 }
6151 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6152
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6153 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6154 // These instructions only load 64 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6155 // destination register is wider than 64 bits (8 bytes), and its user
6156 // instruction isn't scalar (SD).
6157 switch (UserOpc) {
6158 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
6159 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
6160 case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
6161 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
Vyacheslav Klochkoved865df2015-11-26 07:45:30 +0000[diff] [blame]6162 case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int:
6163 case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int:
6164 case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int:
6165 case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int:
6166 case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int:
6167 case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6168 return false;
6169 default:
6170 return true;
6171 }
6172 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6173
6174 return false;
6175}
6176
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6177MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6178 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
6179 MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6180 // If loading from a FrameIndex, fold directly from the FrameIndex.
6181 unsigned NumOps = LoadMI->getDesc().getNumOperands();
6182 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6183 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6184 if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6185 return nullptr;
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6186 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6187 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6188
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6189 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6190 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6191
Sanjay Pateld09391c2015-08-10 20:45:44 +0000[diff] [blame]6192 // Avoid partial register update stalls unless optimizing for size.
6193 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6194 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6195
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]6196 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6197 unsigned Alignment = 0;
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]6198 if (LoadMI->hasOneMemOperand())
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]6199 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6200 else
6201 switch (LoadMI->getOpcode()) {
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6202 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6203 case X86::AVX_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6204 Alignment = 32;
6205 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6206 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6207 case X86::V_SETALLONES:
6208 Alignment = 16;
6209 break;
6210 case X86::FsFLD0SD:
6211 Alignment = 8;
6212 break;
6213 case X86::FsFLD0SS:
6214 Alignment = 4;
6215 break;
6216 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6217 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6218 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6219 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6220 unsigned NewOpc = 0;
6221 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6222 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6223 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6224 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6225 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6226 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6227 }
6228 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]6229 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6230 MI->getOperand(1).ChangeToImmediate(0);
6231 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6232 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6233
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6234 // Make sure the subregisters match.
6235 // Otherwise we risk changing the size of the load.
6236 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6237 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6238
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6239 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6240 switch (LoadMI->getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6241 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6242 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6243 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6244 case X86::AVX_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6245 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6246 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6247 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6248 // Create a constant-pool entry and operands to load from it.
6249
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6250 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6251 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6252 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6253 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6254
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6255 // x86-32 PIC requires a PIC base register for constant pools.
6256 unsigned PICBase = 0;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6257 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
6258 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6259 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6260 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6261 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6262 // This doesn't work for several reasons.
6263 // 1. GlobalBaseReg may have been spilled.
6264 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6265 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6266 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6267
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6268 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6269 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]6270 Type *Ty;
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6271 unsigned Opc = LoadMI->getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6272 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6273 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6274 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6275 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6276 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]6277 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6278 else
6279 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6280
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]6281 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6282 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6283 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6284 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6285
6286 // Create operands to load from the constant pool entry.
6287 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6288 MOs.push_back(MachineOperand::CreateImm(1));
6289 MOs.push_back(MachineOperand::CreateReg(0, false));
6290 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]6291 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6292 break;
6293 }
6294 default: {
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6295 if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6296 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]6297
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6298 // Folding a normal load. Just copy the load's address operands.
Benjamin Kramer5fbfe2f2015-02-28 13:20:15 +0000[diff] [blame]6299 MOs.append(LoadMI->operands_begin() + NumOps - X86::AddrNumOperands,
6300 LoadMI->operands_begin() + NumOps);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6301 break;
6302 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6303 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6304 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6305 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6306}
6307
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6308bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
6309 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]6310 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6311 auto I = MemOp2RegOpTable.find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6312 if (I == MemOp2RegOpTable.end())
6313 return false;
6314 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6315 unsigned Index = I->second.second & TB_INDEX_MASK;
6316 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6317 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6318 if (UnfoldLoad && !FoldedLoad)
6319 return false;
6320 UnfoldLoad &= FoldedLoad;
6321 if (UnfoldStore && !FoldedStore)
6322 return false;
6323 UnfoldStore &= FoldedStore;
6324
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6325 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6326 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6327 // TODO: Check if 32-byte or greater accesses are slow too?
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6328 if (!MI->hasOneMemOperand() &&
6329 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6330 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6331 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6332 // conservatively assume the address is unaligned. That's bad for
6333 // performance.
6334 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6335 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6336 SmallVector<MachineOperand,2> BeforeOps;
6337 SmallVector<MachineOperand,2> AfterOps;
6338 SmallVector<MachineOperand,4> ImpOps;
6339 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
6340 MachineOperand &Op = MI->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6341 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6342 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6343 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6344 ImpOps.push_back(Op);
6345 else if (i < Index)
6346 BeforeOps.push_back(Op);
6347 else if (i > Index)
6348 AfterOps.push_back(Op);
6349 }
6350
6351 // Emit the load instruction.
6352 if (UnfoldLoad) {
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6353 std::pair<MachineInstr::mmo_iterator,
6354 MachineInstr::mmo_iterator> MMOs =
6355 MF.extractLoadMemRefs(MI->memoperands_begin(),
6356 MI->memoperands_end());
6357 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6358 if (UnfoldStore) {
6359 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6360 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6361 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6362 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6363 MO.setIsKill(false);
6364 }
6365 }
6366 }
6367
6368 // Emit the data processing instruction.
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6369 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]6370 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6371
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6372 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6373 MIB.addReg(Reg, RegState::Define);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6374 for (MachineOperand &BeforeOp : BeforeOps)
6375 MIB.addOperand(BeforeOp);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6376 if (FoldedLoad)
6377 MIB.addReg(Reg);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6378 for (MachineOperand &AfterOp : AfterOps)
6379 MIB.addOperand(AfterOp);
6380 for (MachineOperand &ImpOp : ImpOps) {
6381 MIB.addReg(ImpOp.getReg(),
6382 getDefRegState(ImpOp.isDef()) |
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6383 RegState::Implicit |
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6384 getKillRegState(ImpOp.isKill()) |
6385 getDeadRegState(ImpOp.isDead()) |
6386 getUndefRegState(ImpOp.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6387 }
6388 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6389 switch (DataMI->getOpcode()) {
6390 default: break;
6391 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6392 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6393 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6394 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6395 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6396 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6397 case X86::CMP8ri: {
6398 MachineOperand &MO0 = DataMI->getOperand(0);
6399 MachineOperand &MO1 = DataMI->getOperand(1);
6400 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6401 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6402 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6403 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6404 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6405 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6406 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6407 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6408 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6409 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
6410 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
6411 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]6412 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6413 MO1.ChangeToRegister(MO0.getReg(), false);
6414 }
6415 }
6416 }
6417 NewMIs.push_back(DataMI);
6418
6419 // Emit the store instruction.
6420 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6421 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6422 std::pair<MachineInstr::mmo_iterator,
6423 MachineInstr::mmo_iterator> MMOs =
6424 MF.extractStoreMemRefs(MI->memoperands_begin(),
6425 MI->memoperands_end());
6426 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6427 }
6428
6429 return true;
6430}
6431
6432bool
6433X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]6434 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]6435 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6436 return false;
6437
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6438 auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6439 if (I == MemOp2RegOpTable.end())
6440 return false;
6441 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6442 unsigned Index = I->second.second & TB_INDEX_MASK;
6443 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6444 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6445 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6446 MachineFunction &MF = DAG.getMachineFunction();
6447 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6448 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6449 std::vector<SDValue> AddrOps;
6450 std::vector<SDValue> BeforeOps;
6451 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]6452 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6453 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]6454 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6455 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6456 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6457 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6458 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6459 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6460 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6461 AfterOps.push_back(Op);
6462 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6463 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6464 AddrOps.push_back(Chain);
6465
6466 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6467 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6468 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6469 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6470 std::pair<MachineInstr::mmo_iterator,
6471 MachineInstr::mmo_iterator> MMOs =
6472 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6473 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6474 if (!(*MMOs.first) &&
6475 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6476 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6477 // Do not introduce a slow unaligned load.
6478 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6479 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6480 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6481 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6482 bool isAligned = (*MMOs.first) &&
6483 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6484 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6485 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6486 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6487
6488 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6489 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6490 }
6491
6492 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6493 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6494 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6495 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6496 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6497 VTs.push_back(*DstRC->vt_begin());
6498 }
6499 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6500 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6501 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6502 VTs.push_back(VT);
6503 }
6504 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6505 BeforeOps.push_back(SDValue(Load, 0));
Benjamin Kramer4f6ac162015-02-28 10:11:12 +0000[diff] [blame]6506 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6507 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6508 NewNodes.push_back(NewNode);
6509
6510 // Emit the store instruction.
6511 if (FoldedStore) {
6512 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6513 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6514 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6515 std::pair<MachineInstr::mmo_iterator,
6516 MachineInstr::mmo_iterator> MMOs =
6517 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6518 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6519 if (!(*MMOs.first) &&
6520 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6521 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6522 // Do not introduce a slow unaligned store.
6523 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6524 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6525 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6526 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6527 bool isAligned = (*MMOs.first) &&
6528 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6529 SDNode *Store =
6530 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6531 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6532 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6533
6534 // Preserve memory reference information.
Craig Topper9e71b822015-02-10 06:29:28 +0000[diff] [blame]6535 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6536 }
6537
6538 return true;
6539}
6540
6541unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6542 bool UnfoldLoad, bool UnfoldStore,
6543 unsigned *LoadRegIndex) const {
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6544 auto I = MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6545 if (I == MemOp2RegOpTable.end())
6546 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6547 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6548 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6549 if (UnfoldLoad && !FoldedLoad)
6550 return 0;
6551 if (UnfoldStore && !FoldedStore)
6552 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6553 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6554 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6555 return I->second.first;
6556}
6557
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6558bool
6559X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6560 int64_t &Offset1, int64_t &Offset2) const {
6561 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6562 return false;
6563 unsigned Opc1 = Load1->getMachineOpcode();
6564 unsigned Opc2 = Load2->getMachineOpcode();
6565 switch (Opc1) {
6566 default: return false;
6567 case X86::MOV8rm:
6568 case X86::MOV16rm:
6569 case X86::MOV32rm:
6570 case X86::MOV64rm:
6571 case X86::LD_Fp32m:
6572 case X86::LD_Fp64m:
6573 case X86::LD_Fp80m:
6574 case X86::MOVSSrm:
6575 case X86::MOVSDrm:
6576 case X86::MMX_MOVD64rm:
6577 case X86::MMX_MOVQ64rm:
6578 case X86::FsMOVAPSrm:
6579 case X86::FsMOVAPDrm:
6580 case X86::MOVAPSrm:
6581 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6582 case X86::MOVAPDrm:
6583 case X86::MOVDQArm:
6584 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6585 // AVX load instructions
6586 case X86::VMOVSSrm:
6587 case X86::VMOVSDrm:
6588 case X86::FsVMOVAPSrm:
6589 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6590 case X86::VMOVAPSrm:
6591 case X86::VMOVUPSrm:
6592 case X86::VMOVAPDrm:
6593 case X86::VMOVDQArm:
6594 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6595 case X86::VMOVAPSYrm:
6596 case X86::VMOVUPSYrm:
6597 case X86::VMOVAPDYrm:
6598 case X86::VMOVDQAYrm:
6599 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6600 break;
6601 }
6602 switch (Opc2) {
6603 default: return false;
6604 case X86::MOV8rm:
6605 case X86::MOV16rm:
6606 case X86::MOV32rm:
6607 case X86::MOV64rm:
6608 case X86::LD_Fp32m:
6609 case X86::LD_Fp64m:
6610 case X86::LD_Fp80m:
6611 case X86::MOVSSrm:
6612 case X86::MOVSDrm:
6613 case X86::MMX_MOVD64rm:
6614 case X86::MMX_MOVQ64rm:
6615 case X86::FsMOVAPSrm:
6616 case X86::FsMOVAPDrm:
6617 case X86::MOVAPSrm:
6618 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6619 case X86::MOVAPDrm:
6620 case X86::MOVDQArm:
6621 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6622 // AVX load instructions
6623 case X86::VMOVSSrm:
6624 case X86::VMOVSDrm:
6625 case X86::FsVMOVAPSrm:
6626 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6627 case X86::VMOVAPSrm:
6628 case X86::VMOVUPSrm:
6629 case X86::VMOVAPDrm:
6630 case X86::VMOVDQArm:
6631 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6632 case X86::VMOVAPSYrm:
6633 case X86::VMOVUPSYrm:
6634 case X86::VMOVAPDYrm:
6635 case X86::VMOVDQAYrm:
6636 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6637 break;
6638 }
6639
6640 // Check if chain operands and base addresses match.
6641 if (Load1->getOperand(0) != Load2->getOperand(0) ||
6642 Load1->getOperand(5) != Load2->getOperand(5))
6643 return false;
6644 // Segment operands should match as well.
6645 if (Load1->getOperand(4) != Load2->getOperand(4))
6646 return false;
6647 // Scale should be 1, Index should be Reg0.
6648 if (Load1->getOperand(1) == Load2->getOperand(1) &&
6649 Load1->getOperand(2) == Load2->getOperand(2)) {
6650 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6651 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6652
6653 // Now let's examine the displacements.
6654 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6655 isa<ConstantSDNode>(Load2->getOperand(3))) {
6656 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6657 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6658 return true;
6659 }
6660 }
6661 return false;
6662}
6663
6664bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6665 int64_t Offset1, int64_t Offset2,
6666 unsigned NumLoads) const {
6667 assert(Offset2 > Offset1);
6668 if ((Offset2 - Offset1) / 8 > 64)
6669 return false;
6670
6671 unsigned Opc1 = Load1->getMachineOpcode();
6672 unsigned Opc2 = Load2->getMachineOpcode();
6673 if (Opc1 != Opc2)
6674 return false; // FIXME: overly conservative?
6675
6676 switch (Opc1) {
6677 default: break;
6678 case X86::LD_Fp32m:
6679 case X86::LD_Fp64m:
6680 case X86::LD_Fp80m:
6681 case X86::MMX_MOVD64rm:
6682 case X86::MMX_MOVQ64rm:
6683 return false;
6684 }
6685
6686 EVT VT = Load1->getValueType(0);
6687 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6688 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6689 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6690 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6691 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6692 if (NumLoads >= 3)
6693 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6694 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6695 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6696 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6697 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6698 case MVT::i8:
6699 case MVT::i16:
6700 case MVT::i32:
6701 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]6702 case MVT::f32:
6703 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6704 if (NumLoads)
6705 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6706 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6707 }
6708
6709 return true;
6710}
6711
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6712bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
6713 MachineInstr *Second) const {
6714 // Check if this processor supports macro-fusion. Since this is a minor
6715 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6716 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6717 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6718 return false;
6719
6720 enum {
6721 FuseTest,
6722 FuseCmp,
6723 FuseInc
6724 } FuseKind;
6725
6726 switch(Second->getOpcode()) {
6727 default:
6728 return false;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6729 case X86::JE_1:
6730 case X86::JNE_1:
6731 case X86::JL_1:
6732 case X86::JLE_1:
6733 case X86::JG_1:
6734 case X86::JGE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6735 FuseKind = FuseInc;
6736 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6737 case X86::JB_1:
6738 case X86::JBE_1:
6739 case X86::JA_1:
6740 case X86::JAE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6741 FuseKind = FuseCmp;
6742 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6743 case X86::JS_1:
6744 case X86::JNS_1:
6745 case X86::JP_1:
6746 case X86::JNP_1:
6747 case X86::JO_1:
6748 case X86::JNO_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6749 FuseKind = FuseTest;
6750 break;
6751 }
6752 switch (First->getOpcode()) {
6753 default:
6754 return false;
6755 case X86::TEST8rr:
6756 case X86::TEST16rr:
6757 case X86::TEST32rr:
6758 case X86::TEST64rr:
6759 case X86::TEST8ri:
6760 case X86::TEST16ri:
6761 case X86::TEST32ri:
6762 case X86::TEST32i32:
6763 case X86::TEST64i32:
6764 case X86::TEST64ri32:
6765 case X86::TEST8rm:
6766 case X86::TEST16rm:
6767 case X86::TEST32rm:
6768 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]6769 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6770 case X86::AND16i16:
6771 case X86::AND16ri:
6772 case X86::AND16ri8:
6773 case X86::AND16rm:
6774 case X86::AND16rr:
6775 case X86::AND32i32:
6776 case X86::AND32ri:
6777 case X86::AND32ri8:
6778 case X86::AND32rm:
6779 case X86::AND32rr:
6780 case X86::AND64i32:
6781 case X86::AND64ri32:
6782 case X86::AND64ri8:
6783 case X86::AND64rm:
6784 case X86::AND64rr:
6785 case X86::AND8i8:
6786 case X86::AND8ri:
6787 case X86::AND8rm:
6788 case X86::AND8rr:
6789 return true;
6790 case X86::CMP16i16:
6791 case X86::CMP16ri:
6792 case X86::CMP16ri8:
6793 case X86::CMP16rm:
6794 case X86::CMP16rr:
6795 case X86::CMP32i32:
6796 case X86::CMP32ri:
6797 case X86::CMP32ri8:
6798 case X86::CMP32rm:
6799 case X86::CMP32rr:
6800 case X86::CMP64i32:
6801 case X86::CMP64ri32:
6802 case X86::CMP64ri8:
6803 case X86::CMP64rm:
6804 case X86::CMP64rr:
6805 case X86::CMP8i8:
6806 case X86::CMP8ri:
6807 case X86::CMP8rm:
6808 case X86::CMP8rr:
6809 case X86::ADD16i16:
6810 case X86::ADD16ri:
6811 case X86::ADD16ri8:
6812 case X86::ADD16ri8_DB:
6813 case X86::ADD16ri_DB:
6814 case X86::ADD16rm:
6815 case X86::ADD16rr:
6816 case X86::ADD16rr_DB:
6817 case X86::ADD32i32:
6818 case X86::ADD32ri:
6819 case X86::ADD32ri8:
6820 case X86::ADD32ri8_DB:
6821 case X86::ADD32ri_DB:
6822 case X86::ADD32rm:
6823 case X86::ADD32rr:
6824 case X86::ADD32rr_DB:
6825 case X86::ADD64i32:
6826 case X86::ADD64ri32:
6827 case X86::ADD64ri32_DB:
6828 case X86::ADD64ri8:
6829 case X86::ADD64ri8_DB:
6830 case X86::ADD64rm:
6831 case X86::ADD64rr:
6832 case X86::ADD64rr_DB:
6833 case X86::ADD8i8:
6834 case X86::ADD8mi:
6835 case X86::ADD8mr:
6836 case X86::ADD8ri:
6837 case X86::ADD8rm:
6838 case X86::ADD8rr:
6839 case X86::SUB16i16:
6840 case X86::SUB16ri:
6841 case X86::SUB16ri8:
6842 case X86::SUB16rm:
6843 case X86::SUB16rr:
6844 case X86::SUB32i32:
6845 case X86::SUB32ri:
6846 case X86::SUB32ri8:
6847 case X86::SUB32rm:
6848 case X86::SUB32rr:
6849 case X86::SUB64i32:
6850 case X86::SUB64ri32:
6851 case X86::SUB64ri8:
6852 case X86::SUB64rm:
6853 case X86::SUB64rr:
6854 case X86::SUB8i8:
6855 case X86::SUB8ri:
6856 case X86::SUB8rm:
6857 case X86::SUB8rr:
6858 return FuseKind == FuseCmp || FuseKind == FuseInc;
6859 case X86::INC16r:
6860 case X86::INC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6861 case X86::INC64r:
6862 case X86::INC8r:
6863 case X86::DEC16r:
6864 case X86::DEC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6865 case X86::DEC64r:
6866 case X86::DEC8r:
6867 return FuseKind == FuseInc;
6868 }
6869}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6870
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]6871bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]6872ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]6873 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]6874 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6875 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]6876 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]6877}
6878
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]6879bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]6880isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6881 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]6882 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]6883 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6884 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]6885}
6886
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6887/// Return a virtual register initialized with the
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6888/// the global base register value. Output instructions required to
6889/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]6890///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6891/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6892///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6893unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6894 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6895 "X86-64 PIC uses RIP relative addressing");
6896
6897 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6898 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6899 if (GlobalBaseReg != 0)
6900 return GlobalBaseReg;
6901
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6902 // Create the register. The code to initialize it is inserted
6903 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]6904 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]6905 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6906 X86FI->setGlobalBaseReg(GlobalBaseReg);
6907 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]6908}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6909
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6910// These are the replaceable SSE instructions. Some of these have Int variants
6911// that we don't include here. We don't want to replace instructions selected
6912// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6913static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]6914 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]6915 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
6916 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
6917 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
6918 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
6919 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
Sanjay Patelc03d93b2015-04-15 15:47:51 +0000[diff] [blame]6920 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]6921 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
6922 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
6923 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
6924 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
6925 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
6926 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
6927 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
6928 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
6929 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6930 // AVX 128-bit support
6931 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
6932 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
6933 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
6934 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
6935 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
Sanjay Patel2161c492015-04-17 17:02:37 +0000[diff] [blame]6936 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6937 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6938 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
6939 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
6940 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
6941 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
6942 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
6943 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6944 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
6945 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6946 // AVX 256-bit support
6947 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
6948 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
6949 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
6950 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
6951 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]6952 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
6953};
6954
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6955static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]6956 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]6957 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
6958 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
6959 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
6960 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
6961 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
6962 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
6963 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]6964 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
6965 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6966 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6967 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
6968 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
6969 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]6970 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
6971 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6972 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6973 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6974 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6975 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6976 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6977};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6978
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6979// FIXME: Some shuffle and unpack instructions have equivalents in different
6980// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6981
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6982static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]6983 for (const uint16_t (&Row)[3] : ReplaceableInstrs)
6984 if (Row[domain-1] == opcode)
6985 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6986 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]6987}
6988
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6989static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]6990 for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
6991 if (Row[domain-1] == opcode)
6992 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6993 return nullptr;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6994}
6995
6996std::pair<uint16_t, uint16_t>
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]6997X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6998 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6999 bool hasAVX2 = Subtarget.hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7000 uint16_t validDomains = 0;
7001 if (domain && lookup(MI->getOpcode(), domain))
7002 validDomains = 0xe;
7003 else if (domain && lookupAVX2(MI->getOpcode(), domain))
7004 validDomains = hasAVX2 ? 0xe : 0x6;
7005 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7006}
7007
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]7008void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7009 assert(Domain>0 && Domain<4 && "Invalid execution domain");
7010 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
7011 assert(dom && "Not an SSE instruction");
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7012 const uint16_t *table = lookup(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7013 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7014 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7015 "256-bit vector operations only available in AVX2");
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7016 table = lookupAVX2(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7017 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7018 assert(table && "Cannot change domain");
7019 MI->setDesc(get(table[Domain-1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7020}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7021
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7022/// Return the noop instruction to use for a noop.
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7023void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7024 NopInst.setOpcode(X86::NOOP);
7025}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7026
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7027// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7028// In particular, getJumpInstrTableEntryBound must always return an upper bound
7029// on the encoding lengths of the instructions generated by
7030// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7031void X86InstrInfo::getUnconditionalBranch(
7032 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7033 Branch.setOpcode(X86::JMP_1);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]7034 Branch.addOperand(MCOperand::createExpr(BranchTarget));
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7035}
7036
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7037// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7038// In particular, getJumpInstrTableEntryBound must always return an upper bound
7039// on the encoding lengths of the instructions generated by
7040// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7041void X86InstrInfo::getTrap(MCInst &MI) const {
7042 MI.setOpcode(X86::TRAP);
7043}
7044
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7045// See getTrap and getUnconditionalBranch for conditions on the value returned
7046// by this function.
7047unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7048 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7049 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7050 return 5;
7051}
7052
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7053bool X86InstrInfo::isHighLatencyDef(int opc) const {
7054 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7055 default: return false;
7056 case X86::DIVSDrm:
7057 case X86::DIVSDrm_Int:
7058 case X86::DIVSDrr:
7059 case X86::DIVSDrr_Int:
7060 case X86::DIVSSrm:
7061 case X86::DIVSSrm_Int:
7062 case X86::DIVSSrr:
7063 case X86::DIVSSrr_Int:
7064 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7065 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7066 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7067 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7068 case X86::SQRTSDm:
7069 case X86::SQRTSDm_Int:
7070 case X86::SQRTSDr:
7071 case X86::SQRTSDr_Int:
7072 case X86::SQRTSSm:
7073 case X86::SQRTSSm_Int:
7074 case X86::SQRTSSr:
7075 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7076 // AVX instructions with high latency
7077 case X86::VDIVSDrm:
7078 case X86::VDIVSDrm_Int:
7079 case X86::VDIVSDrr:
7080 case X86::VDIVSDrr_Int:
7081 case X86::VDIVSSrm:
7082 case X86::VDIVSSrm_Int:
7083 case X86::VDIVSSrr:
7084 case X86::VDIVSSrr_Int:
7085 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7086 case X86::VSQRTPDr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7087 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7088 case X86::VSQRTPSr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7089 case X86::VSQRTSDm:
7090 case X86::VSQRTSDm_Int:
7091 case X86::VSQRTSDr:
7092 case X86::VSQRTSSm:
7093 case X86::VSQRTSSm_Int:
7094 case X86::VSQRTSSr:
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]7095 case X86::VSQRTPDZm:
7096 case X86::VSQRTPDZr:
7097 case X86::VSQRTPSZm:
7098 case X86::VSQRTPSZr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7099 case X86::VSQRTSDZm:
7100 case X86::VSQRTSDZm_Int:
7101 case X86::VSQRTSDZr:
7102 case X86::VSQRTSSZm_Int:
7103 case X86::VSQRTSSZr:
7104 case X86::VSQRTSSZm:
7105 case X86::VDIVSDZrm:
7106 case X86::VDIVSDZrr:
7107 case X86::VDIVSSZrm:
7108 case X86::VDIVSSZrr:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7109
7110 case X86::VGATHERQPSZrm:
7111 case X86::VGATHERQPDZrm:
7112 case X86::VGATHERDPDZrm:
7113 case X86::VGATHERDPSZrm:
7114 case X86::VPGATHERQDZrm:
7115 case X86::VPGATHERQQZrm:
7116 case X86::VPGATHERDDZrm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7117 case X86::VPGATHERDQZrm:
7118 case X86::VSCATTERQPDZmr:
7119 case X86::VSCATTERQPSZmr:
7120 case X86::VSCATTERDPDZmr:
7121 case X86::VSCATTERDPSZmr:
7122 case X86::VPSCATTERQDZmr:
7123 case X86::VPSCATTERQQZmr:
7124 case X86::VPSCATTERDDZmr:
7125 case X86::VPSCATTERDQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7126 return true;
7127 }
7128}
7129
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7130bool X86InstrInfo::
Matthias Braun88e21312015-06-13 03:42:11 +0000[diff] [blame]7131hasHighOperandLatency(const TargetSchedModel &SchedModel,
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7132 const MachineRegisterInfo *MRI,
7133 const MachineInstr *DefMI, unsigned DefIdx,
7134 const MachineInstr *UseMI, unsigned UseIdx) const {
7135 return isHighLatencyDef(DefMI->getOpcode());
7136}
7137
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7138bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7139 const MachineBasicBlock *MBB) const {
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7140 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7141 "Reassociation needs binary operators");
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7142
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7143 // Integer binary math/logic instructions have a third source operand:
7144 // the EFLAGS register. That operand must be both defined here and never
7145 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7146 // not change anything because rearranging the operands could affect other
7147 // instructions that depend on the exact status flags (zero, sign, etc.)
7148 // that are set by using these particular operands with this operation.
7149 if (Inst.getNumOperands() == 4) {
7150 assert(Inst.getOperand(3).isReg() &&
7151 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7152 "Unexpected operand in reassociable instruction");
7153 if (!Inst.getOperand(3).isDead())
7154 return false;
7155 }
Sanjay Patele79b43a2015-06-23 00:39:40 +0000[diff] [blame]7156
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7157 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7158}
7159
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7160// TODO: There are many more machine instruction opcodes to match:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7161// 1. Other data types (integer, vectors)
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7162// 2. Other math / logic operations (xor, or)
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7163// 3. Other forms of the same operation (intrinsics and other variants)
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7164bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7165 switch (Inst.getOpcode()) {
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7166 case X86::AND8rr:
7167 case X86::AND16rr:
7168 case X86::AND32rr:
7169 case X86::AND64rr:
Sanjay Pateld9a5c222015-08-31 20:27:03 +0000[diff] [blame]7170 case X86::OR8rr:
7171 case X86::OR16rr:
7172 case X86::OR32rr:
7173 case X86::OR64rr:
Sanjay Patelc9ae9d72015-09-03 16:36:16 +0000[diff] [blame]7174 case X86::XOR8rr:
7175 case X86::XOR16rr:
7176 case X86::XOR32rr:
7177 case X86::XOR64rr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7178 case X86::IMUL16rr:
7179 case X86::IMUL32rr:
7180 case X86::IMUL64rr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7181 case X86::PANDrr:
7182 case X86::PORrr:
7183 case X86::PXORrr:
7184 case X86::VPANDrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7185 case X86::VPANDYrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7186 case X86::VPORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7187 case X86::VPORYrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7188 case X86::VPXORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7189 case X86::VPXORYrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7190 // Normal min/max instructions are not commutative because of NaN and signed
7191 // zero semantics, but these are. Thus, there's no need to check for global
7192 // relaxed math; the instructions themselves have the properties we need.
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7193 case X86::MAXCPDrr:
7194 case X86::MAXCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7195 case X86::MAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7196 case X86::MAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7197 case X86::MINCPDrr:
7198 case X86::MINCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7199 case X86::MINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7200 case X86::MINCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7201 case X86::VMAXCPDrr:
7202 case X86::VMAXCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7203 case X86::VMAXCPDYrr:
7204 case X86::VMAXCPSYrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7205 case X86::VMAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7206 case X86::VMAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7207 case X86::VMINCPDrr:
7208 case X86::VMINCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7209 case X86::VMINCPDYrr:
7210 case X86::VMINCPSYrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7211 case X86::VMINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7212 case X86::VMINCSSrr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7213 return true;
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]7214 case X86::ADDPDrr:
7215 case X86::ADDPSrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]7216 case X86::ADDSDrr:
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7217 case X86::ADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]7218 case X86::MULPDrr:
7219 case X86::MULPSrr:
7220 case X86::MULSDrr:
7221 case X86::MULSSrr:
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]7222 case X86::VADDPDrr:
7223 case X86::VADDPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]7224 case X86::VADDPDYrr:
7225 case X86::VADDPSYrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]7226 case X86::VADDSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]7227 case X86::VADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]7228 case X86::VMULPDrr:
7229 case X86::VMULPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]7230 case X86::VMULPDYrr:
7231 case X86::VMULPSYrr:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7232 case X86::VMULSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]7233 case X86::VMULSSrr:
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7234 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7235 default:
7236 return false;
7237 }
7238}
7239
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7240/// This is an architecture-specific helper function of reassociateOps.
7241/// Set special operand attributes for new instructions after reassociation.
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7242void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7243 MachineInstr &OldMI2,
7244 MachineInstr &NewMI1,
7245 MachineInstr &NewMI2) const {
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7246 // Integer instructions define an implicit EFLAGS source register operand as
7247 // the third source (fourth total) operand.
7248 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7249 return;
7250
7251 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7252 "Unexpected instruction type for reassociation");
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7253
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7254 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7255 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7256 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7257 MachineOperand &NewOp2 = NewMI2.getOperand(3);
7258
7259 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7260 "Must have dead EFLAGS operand in reassociable instruction");
7261 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7262 "Must have dead EFLAGS operand in reassociable instruction");
7263
7264 (void)OldOp1;
7265 (void)OldOp2;
7266
7267 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7268 "Unexpected operand in reassociable instruction");
7269 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7270 "Unexpected operand in reassociable instruction");
7271
7272 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7273 // of this pass or other passes. The EFLAGS operands must be dead in these new
7274 // instructions because the EFLAGS operands in the original instructions must
7275 // be dead in order for reassociation to occur.
7276 NewOp1.setIsDead();
7277 NewOp2.setIsDead();
7278}
7279
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7280std::pair<unsigned, unsigned>
7281X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7282 return std::make_pair(TF, 0u);
7283}
7284
7285ArrayRef<std::pair<unsigned, const char *>>
7286X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7287 using namespace X86II;
Hal Finkel982e8d42015-08-30 08:07:29 +0000[diff] [blame]7288 static const std::pair<unsigned, const char *> TargetFlags[] = {
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7289 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7290 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7291 {MO_GOT, "x86-got"},
7292 {MO_GOTOFF, "x86-gotoff"},
7293 {MO_GOTPCREL, "x86-gotpcrel"},
7294 {MO_PLT, "x86-plt"},
7295 {MO_TLSGD, "x86-tlsgd"},
7296 {MO_TLSLD, "x86-tlsld"},
7297 {MO_TLSLDM, "x86-tlsldm"},
7298 {MO_GOTTPOFF, "x86-gottpoff"},
7299 {MO_INDNTPOFF, "x86-indntpoff"},
7300 {MO_TPOFF, "x86-tpoff"},
7301 {MO_DTPOFF, "x86-dtpoff"},
7302 {MO_NTPOFF, "x86-ntpoff"},
7303 {MO_GOTNTPOFF, "x86-gotntpoff"},
7304 {MO_DLLIMPORT, "x86-dllimport"},
7305 {MO_DARWIN_STUB, "x86-darwin-stub"},
7306 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7307 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7308 {MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, "x86-darwin-hidden-nonlazy-pic-base"},
7309 {MO_TLVP, "x86-tlvp"},
7310 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7311 {MO_SECREL, "x86-secrel"}};
7312 return makeArrayRef(TargetFlags);
7313}
7314
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7315namespace {
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7316 /// Create Global Base Reg pass. This initializes the PIC
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7317 /// global base register for x86-32.
7318 struct CGBR : public MachineFunctionPass {
7319 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]7320 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7321
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7322 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7323 const X86TargetMachine *TM =
7324 static_cast<const X86TargetMachine *>(&MF.getTarget());
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7325 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7326
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]7327 // Don't do anything if this is 64-bit as 64-bit PIC
7328 // uses RIP relative addressing.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7329 if (STI.is64Bit())
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]7330 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7331
7332 // Only emit a global base reg in PIC mode.
7333 if (TM->getRelocationModel() != Reloc::PIC_)
7334 return false;
7335
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]7336 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7337 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7338
7339 // If we didn't need a GlobalBaseReg, don't insert code.
7340 if (GlobalBaseReg == 0)
7341 return false;
7342
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7343 // Insert the set of GlobalBaseReg into the first MBB of the function
7344 MachineBasicBlock &FirstMBB = MF.front();
7345 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7346 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7347 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7348 const X86InstrInfo *TII = STI.getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7349
7350 unsigned PC;
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7351 if (STI.isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]7352 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7353 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]7354 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]7355
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7356 // Operand of MovePCtoStack is completely ignored by asm printer. It's
7357 // only used in JIT code emission as displacement to pc.
7358 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]7359
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7360 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
7361 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7362 if (STI.isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7363 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
7364 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7365 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7366 X86II::MO_GOT_ABSOLUTE_ADDRESS);
7367 }
7368
7369 return true;
7370 }
7371
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7372 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7373 return "X86 PIC Global Base Reg Initialization";
7374 }
7375
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7376 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7377 AU.setPreservesCFG();
7378 MachineFunctionPass::getAnalysisUsage(AU);
7379 }
7380 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]7381}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7382
7383char CGBR::ID = 0;
7384FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]7385llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7386
7387namespace {
7388 struct LDTLSCleanup : public MachineFunctionPass {
7389 static char ID;
7390 LDTLSCleanup() : MachineFunctionPass(ID) {}
7391
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7392 bool runOnMachineFunction(MachineFunction &MF) override {
Andrew Kaylor2bee5ef2016-04-26 21:44:24 +0000[diff] [blame]7393 if (skipFunction(*MF.getFunction()))
7394 return false;
7395
7396 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7397 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7398 // No point folding accesses if there isn't at least two.
7399 return false;
7400 }
7401
7402 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7403 return VisitNode(DT->getRootNode(), 0);
7404 }
7405
7406 // Visit the dominator subtree rooted at Node in pre-order.
7407 // If TLSBaseAddrReg is non-null, then use that to replace any
7408 // TLS_base_addr instructions. Otherwise, create the register
7409 // when the first such instruction is seen, and then use it
7410 // as we encounter more instructions.
7411 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7412 MachineBasicBlock *BB = Node->getBlock();
7413 bool Changed = false;
7414
7415 // Traverse the current block.
7416 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7417 ++I) {
7418 switch (I->getOpcode()) {
7419 case X86::TLS_base_addr32:
7420 case X86::TLS_base_addr64:
7421 if (TLSBaseAddrReg)
7422 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
7423 else
7424 I = SetRegister(I, &TLSBaseAddrReg);
7425 Changed = true;
7426 break;
7427 default:
7428 break;
7429 }
7430 }
7431
7432 // Visit the children of this block in the dominator tree.
7433 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7434 I != E; ++I) {
7435 Changed |= VisitNode(*I, TLSBaseAddrReg);
7436 }
7437
7438 return Changed;
7439 }
7440
7441 // Replace the TLS_base_addr instruction I with a copy from
7442 // TLSBaseAddrReg, returning the new instruction.
7443 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
7444 unsigned TLSBaseAddrReg) {
7445 MachineFunction *MF = I->getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7446 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7447 const bool is64Bit = STI.is64Bit();
7448 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7449
7450 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7451 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
7452 TII->get(TargetOpcode::COPY),
7453 is64Bit ? X86::RAX : X86::EAX)
7454 .addReg(TLSBaseAddrReg);
7455
7456 // Erase the TLS_base_addr instruction.
7457 I->eraseFromParent();
7458
7459 return Copy;
7460 }
7461
7462 // Create a virtal register in *TLSBaseAddrReg, and populate it by
7463 // inserting a copy instruction after I. Returns the new instruction.
7464 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
7465 MachineFunction *MF = I->getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7466 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7467 const bool is64Bit = STI.is64Bit();
7468 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7469
7470 // Create a virtual register for the TLS base address.
7471 MachineRegisterInfo &RegInfo = MF->getRegInfo();
7472 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7473 ? &X86::GR64RegClass
7474 : &X86::GR32RegClass);
7475
7476 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7477 MachineInstr *Next = I->getNextNode();
7478 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
7479 TII->get(TargetOpcode::COPY),
7480 *TLSBaseAddrReg)
7481 .addReg(is64Bit ? X86::RAX : X86::EAX);
7482
7483 return Copy;
7484 }
7485
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7486 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7487 return "Local Dynamic TLS Access Clean-up";
7488 }
7489
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7490 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7491 AU.setPreservesCFG();
7492 AU.addRequired<MachineDominatorTree>();
7493 MachineFunctionPass::getAnalysisUsage(AU);
7494 }
7495 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]7496}
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7497
7498char LDTLSCleanup::ID = 0;
7499FunctionPass*
7500llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }