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Tom Stellard75aadc22012-12-11 21:25:42 +00001//===-- AMDGPUInstructions.td - Common instruction defs ---*- tablegen -*-===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file contains instruction defs that are common to all hw codegen
11// targets.
12//
13//===----------------------------------------------------------------------===//
14
15class AMDGPUInst <dag outs, dag ins, string asm, list<dag> pattern> : Instruction {
Tom Stellardf3b2a1e2013-02-06 17:32:29 +000016 field bit isRegisterLoad = 0;
17 field bit isRegisterStore = 0;
Tom Stellard75aadc22012-12-11 21:25:42 +000018
19 let Namespace = "AMDGPU";
20 let OutOperandList = outs;
21 let InOperandList = ins;
22 let AsmString = asm;
23 let Pattern = pattern;
24 let Itinerary = NullALU;
Tom Stellardf3b2a1e2013-02-06 17:32:29 +000025
26 let TSFlags{63} = isRegisterLoad;
27 let TSFlags{62} = isRegisterStore;
Tom Stellard75aadc22012-12-11 21:25:42 +000028}
29
30class AMDGPUShaderInst <dag outs, dag ins, string asm, list<dag> pattern>
31 : AMDGPUInst<outs, ins, asm, pattern> {
32
33 field bits<32> Inst = 0xffffffff;
34
35}
36
Matt Arsenaultf171cf22014-07-14 23:40:49 +000037def FP32Denormals : Predicate<"Subtarget.hasFP32Denormals()">;
38def FP64Denormals : Predicate<"Subtarget.hasFP64Denormals()">;
Matt Arsenault1d077742014-07-15 20:18:24 +000039def UnsafeFPMath : Predicate<"TM.Options.UnsafeFPMath">;
Matt Arsenaultf171cf22014-07-14 23:40:49 +000040
Tom Stellard75aadc22012-12-11 21:25:42 +000041def InstFlag : OperandWithDefaultOps <i32, (ops (i32 0))>;
Tom Stellard81d871d2013-11-13 23:36:50 +000042def ADDRIndirect : ComplexPattern<iPTR, 2, "SelectADDRIndirect", [], []>;
Tom Stellard75aadc22012-12-11 21:25:42 +000043
Tom Stellardb02094e2014-07-21 15:45:01 +000044let OperandType = "OPERAND_IMMEDIATE" in {
45
Matt Arsenault4d7d3832014-04-15 22:32:49 +000046def u32imm : Operand<i32> {
47 let PrintMethod = "printU32ImmOperand";
48}
49
50def u16imm : Operand<i16> {
51 let PrintMethod = "printU16ImmOperand";
52}
53
54def u8imm : Operand<i8> {
55 let PrintMethod = "printU8ImmOperand";
56}
57
Tom Stellardb02094e2014-07-21 15:45:01 +000058} // End OperandType = "OPERAND_IMMEDIATE"
59
Tom Stellardbc5b5372014-06-13 16:38:59 +000060//===--------------------------------------------------------------------===//
61// Custom Operands
62//===--------------------------------------------------------------------===//
63def brtarget : Operand<OtherVT>;
64
Tom Stellardc0845332013-11-22 23:07:58 +000065//===----------------------------------------------------------------------===//
66// PatLeafs for floating-point comparisons
67//===----------------------------------------------------------------------===//
Tom Stellard75aadc22012-12-11 21:25:42 +000068
Tom Stellard0351ea22013-09-28 02:50:50 +000069def COND_OEQ : PatLeaf <
70 (cond),
71 [{return N->get() == ISD::SETOEQ || N->get() == ISD::SETEQ;}]
72>;
73
Matt Arsenault9cded7a2014-12-11 22:15:35 +000074def COND_ONE : PatLeaf <
75 (cond),
76 [{return N->get() == ISD::SETONE || N->get() == ISD::SETNE;}]
77>;
78
Tom Stellard0351ea22013-09-28 02:50:50 +000079def COND_OGT : PatLeaf <
80 (cond),
81 [{return N->get() == ISD::SETOGT || N->get() == ISD::SETGT;}]
82>;
83
Tom Stellard0351ea22013-09-28 02:50:50 +000084def COND_OGE : PatLeaf <
85 (cond),
86 [{return N->get() == ISD::SETOGE || N->get() == ISD::SETGE;}]
87>;
88
Tom Stellardc0845332013-11-22 23:07:58 +000089def COND_OLT : PatLeaf <
Tom Stellard75aadc22012-12-11 21:25:42 +000090 (cond),
Tom Stellardc0845332013-11-22 23:07:58 +000091 [{return N->get() == ISD::SETOLT || N->get() == ISD::SETLT;}]
Tom Stellard75aadc22012-12-11 21:25:42 +000092>;
93
Tom Stellardc0845332013-11-22 23:07:58 +000094def COND_OLE : PatLeaf <
Tom Stellard75aadc22012-12-11 21:25:42 +000095 (cond),
Tom Stellardc0845332013-11-22 23:07:58 +000096 [{return N->get() == ISD::SETOLE || N->get() == ISD::SETLE;}]
97>;
98
Tom Stellardc0845332013-11-22 23:07:58 +000099
100def COND_O : PatLeaf <(cond), [{return N->get() == ISD::SETO;}]>;
101def COND_UO : PatLeaf <(cond), [{return N->get() == ISD::SETUO;}]>;
102
103//===----------------------------------------------------------------------===//
Matt Arsenault8b989ef2014-12-11 22:15:39 +0000104// PatLeafs for unsigned / unordered comparisons
Tom Stellardc0845332013-11-22 23:07:58 +0000105//===----------------------------------------------------------------------===//
106
Matt Arsenault9cded7a2014-12-11 22:15:35 +0000107def COND_UEQ : PatLeaf <(cond), [{return N->get() == ISD::SETUEQ;}]>;
108def COND_UNE : PatLeaf <(cond), [{return N->get() == ISD::SETUNE;}]>;
Tom Stellardc0845332013-11-22 23:07:58 +0000109def COND_UGT : PatLeaf <(cond), [{return N->get() == ISD::SETUGT;}]>;
110def COND_UGE : PatLeaf <(cond), [{return N->get() == ISD::SETUGE;}]>;
111def COND_ULT : PatLeaf <(cond), [{return N->get() == ISD::SETULT;}]>;
112def COND_ULE : PatLeaf <(cond), [{return N->get() == ISD::SETULE;}]>;
113
Matt Arsenault9cded7a2014-12-11 22:15:35 +0000114// XXX - For some reason R600 version is preferring to use unordered
115// for setne?
116def COND_UNE_NE : PatLeaf <
117 (cond),
118 [{return N->get() == ISD::SETUNE || N->get() == ISD::SETNE;}]
119>;
120
Tom Stellardc0845332013-11-22 23:07:58 +0000121//===----------------------------------------------------------------------===//
122// PatLeafs for signed comparisons
123//===----------------------------------------------------------------------===//
124
125def COND_SGT : PatLeaf <(cond), [{return N->get() == ISD::SETGT;}]>;
126def COND_SGE : PatLeaf <(cond), [{return N->get() == ISD::SETGE;}]>;
127def COND_SLT : PatLeaf <(cond), [{return N->get() == ISD::SETLT;}]>;
128def COND_SLE : PatLeaf <(cond), [{return N->get() == ISD::SETLE;}]>;
129
130//===----------------------------------------------------------------------===//
131// PatLeafs for integer equality
132//===----------------------------------------------------------------------===//
133
134def COND_EQ : PatLeaf <
135 (cond),
136 [{return N->get() == ISD::SETEQ || N->get() == ISD::SETUEQ;}]
137>;
138
139def COND_NE : PatLeaf <
140 (cond),
141 [{return N->get() == ISD::SETNE || N->get() == ISD::SETUNE;}]
Tom Stellard75aadc22012-12-11 21:25:42 +0000142>;
143
Christian Konigb19849a2013-02-21 15:17:04 +0000144def COND_NULL : PatLeaf <
145 (cond),
Tom Stellardaa9a1a82014-08-01 02:05:57 +0000146 [{(void)N; return false;}]
Christian Konigb19849a2013-02-21 15:17:04 +0000147>;
148
Tom Stellard75aadc22012-12-11 21:25:42 +0000149//===----------------------------------------------------------------------===//
150// Load/Store Pattern Fragments
151//===----------------------------------------------------------------------===//
152
Tom Stellardb02094e2014-07-21 15:45:01 +0000153class PrivateMemOp <dag ops, dag frag> : PatFrag <ops, frag, [{
154 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS;
155}]>;
156
157class PrivateLoad <SDPatternOperator op> : PrivateMemOp <
158 (ops node:$ptr), (op node:$ptr)
159>;
160
161class PrivateStore <SDPatternOperator op> : PrivateMemOp <
162 (ops node:$value, node:$ptr), (op node:$value, node:$ptr)
163>;
164
Tom Stellardb02094e2014-07-21 15:45:01 +0000165def load_private : PrivateLoad <load>;
166
167def truncstorei8_private : PrivateStore <truncstorei8>;
168def truncstorei16_private : PrivateStore <truncstorei16>;
169def store_private : PrivateStore <store>;
170
Tom Stellardbc5b5372014-06-13 16:38:59 +0000171def global_store : PatFrag<(ops node:$val, node:$ptr),
172 (store node:$val, node:$ptr), [{
173 return isGlobalStore(dyn_cast<StoreSDNode>(N));
174}]>;
175
176// Global address space loads
177def global_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
178 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
179}]>;
180
181// Constant address space loads
182def constant_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
183 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
184}]>;
185
Tom Stellard31209cc2013-07-15 19:00:09 +0000186def az_extload : PatFrag<(ops node:$ptr), (unindexedload node:$ptr), [{
187 LoadSDNode *L = cast<LoadSDNode>(N);
188 return L->getExtensionType() == ISD::ZEXTLOAD ||
189 L->getExtensionType() == ISD::EXTLOAD;
190}]>;
191
Tom Stellard33dd04b2013-07-23 01:47:52 +0000192def az_extloadi8 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
193 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i8;
194}]>;
195
Tom Stellardc6f4a292013-08-26 15:05:59 +0000196def az_extloadi8_global : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
197 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
198}]>;
199
Tom Stellard9f950332013-07-23 01:48:35 +0000200def sextloadi8_global : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
Tom Stellard75aadc22012-12-11 21:25:42 +0000201 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
202}]>;
203
Matt Arsenault3f981402014-09-15 15:41:53 +0000204def az_extloadi8_flat : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
205 return isFlatLoad(dyn_cast<LoadSDNode>(N));
206}]>;
207
208def sextloadi8_flat : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
209 return isFlatLoad(dyn_cast<LoadSDNode>(N));
210}]>;
211
Tom Stellard33dd04b2013-07-23 01:47:52 +0000212def az_extloadi8_constant : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
Tom Stellard9f950332013-07-23 01:48:35 +0000213 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
214}]>;
215
216def sextloadi8_constant : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
217 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
218}]>;
219
Tom Stellardc6f4a292013-08-26 15:05:59 +0000220def az_extloadi8_local : PatFrag<(ops node:$ptr), (az_extloadi8 node:$ptr), [{
221 return isLocalLoad(dyn_cast<LoadSDNode>(N));
222}]>;
223
224def sextloadi8_local : PatFrag<(ops node:$ptr), (sextloadi8 node:$ptr), [{
225 return isLocalLoad(dyn_cast<LoadSDNode>(N));
Tom Stellard33dd04b2013-07-23 01:47:52 +0000226}]>;
227
Tom Stellardbc377682015-02-17 16:36:00 +0000228def extloadi8_private : PrivateLoad <az_extloadi8>;
229def sextloadi8_private : PrivateLoad <sextloadi8>;
230
Tom Stellard33dd04b2013-07-23 01:47:52 +0000231def az_extloadi16 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
232 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i16;
233}]>;
234
235def az_extloadi16_global : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
236 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
237}]>;
238
Tom Stellard9f950332013-07-23 01:48:35 +0000239def sextloadi16_global : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
Tom Stellard07a10a32013-06-03 17:39:43 +0000240 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
241}]>;
242
Matt Arsenault3f981402014-09-15 15:41:53 +0000243def az_extloadi16_flat : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
244 return isFlatLoad(dyn_cast<LoadSDNode>(N));
245}]>;
246
247def sextloadi16_flat : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
248 return isFlatLoad(dyn_cast<LoadSDNode>(N));
249}]>;
250
Tom Stellard9f950332013-07-23 01:48:35 +0000251def az_extloadi16_constant : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
252 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
253}]>;
254
255def sextloadi16_constant : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
256 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
257}]>;
258
Tom Stellardc6f4a292013-08-26 15:05:59 +0000259def az_extloadi16_local : PatFrag<(ops node:$ptr), (az_extloadi16 node:$ptr), [{
260 return isLocalLoad(dyn_cast<LoadSDNode>(N));
261}]>;
262
263def sextloadi16_local : PatFrag<(ops node:$ptr), (sextloadi16 node:$ptr), [{
264 return isLocalLoad(dyn_cast<LoadSDNode>(N));
265}]>;
266
Tom Stellardbc377682015-02-17 16:36:00 +0000267def extloadi16_private : PrivateLoad <az_extloadi16>;
268def sextloadi16_private : PrivateLoad <sextloadi16>;
269
Tom Stellard31209cc2013-07-15 19:00:09 +0000270def az_extloadi32 : PatFrag<(ops node:$ptr), (az_extload node:$ptr), [{
271 return cast<LoadSDNode>(N)->getMemoryVT() == MVT::i32;
272}]>;
273
274def az_extloadi32_global : PatFrag<(ops node:$ptr),
275 (az_extloadi32 node:$ptr), [{
276 return isGlobalLoad(dyn_cast<LoadSDNode>(N));
277}]>;
278
Matt Arsenault3f981402014-09-15 15:41:53 +0000279def az_extloadi32_flat : PatFrag<(ops node:$ptr),
280 (az_extloadi32 node:$ptr), [{
281 return isFlatLoad(dyn_cast<LoadSDNode>(N));
282}]>;
283
Tom Stellard31209cc2013-07-15 19:00:09 +0000284def az_extloadi32_constant : PatFrag<(ops node:$ptr),
285 (az_extloadi32 node:$ptr), [{
286 return isConstantLoad(dyn_cast<LoadSDNode>(N), -1);
287}]>;
288
Tom Stellardd3ee8c12013-08-16 01:12:06 +0000289def truncstorei8_global : PatFrag<(ops node:$val, node:$ptr),
290 (truncstorei8 node:$val, node:$ptr), [{
291 return isGlobalStore(dyn_cast<StoreSDNode>(N));
292}]>;
293
294def truncstorei16_global : PatFrag<(ops node:$val, node:$ptr),
295 (truncstorei16 node:$val, node:$ptr), [{
296 return isGlobalStore(dyn_cast<StoreSDNode>(N));
297}]>;
298
Matt Arsenault3f981402014-09-15 15:41:53 +0000299def truncstorei8_flat : PatFrag<(ops node:$val, node:$ptr),
300 (truncstorei8 node:$val, node:$ptr), [{
301 return isFlatStore(dyn_cast<StoreSDNode>(N));
302}]>;
303
304def truncstorei16_flat : PatFrag<(ops node:$val, node:$ptr),
305 (truncstorei16 node:$val, node:$ptr), [{
306 return isFlatStore(dyn_cast<StoreSDNode>(N));
307}]>;
308
Tom Stellardc026e8b2013-06-28 15:47:08 +0000309def local_store : PatFrag<(ops node:$val, node:$ptr),
310 (store node:$val, node:$ptr), [{
Tom Stellardf3d166a2013-08-26 15:05:49 +0000311 return isLocalStore(dyn_cast<StoreSDNode>(N));
312}]>;
313
314def truncstorei8_local : PatFrag<(ops node:$val, node:$ptr),
315 (truncstorei8 node:$val, node:$ptr), [{
316 return isLocalStore(dyn_cast<StoreSDNode>(N));
317}]>;
318
319def truncstorei16_local : PatFrag<(ops node:$val, node:$ptr),
320 (truncstorei16 node:$val, node:$ptr), [{
321 return isLocalStore(dyn_cast<StoreSDNode>(N));
322}]>;
323
324def local_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
325 return isLocalLoad(dyn_cast<LoadSDNode>(N));
Tom Stellardc026e8b2013-06-28 15:47:08 +0000326}]>;
327
Tom Stellardf3fc5552014-08-22 18:49:35 +0000328class Aligned8Bytes <dag ops, dag frag> : PatFrag <ops, frag, [{
329 return cast<MemSDNode>(N)->getAlignment() % 8 == 0;
330}]>;
331
332def local_load_aligned8bytes : Aligned8Bytes <
333 (ops node:$ptr), (local_load node:$ptr)
334>;
335
336def local_store_aligned8bytes : Aligned8Bytes <
337 (ops node:$val, node:$ptr), (local_store node:$val, node:$ptr)
338>;
Matt Arsenault72574102014-06-11 18:08:34 +0000339
340class local_binary_atomic_op<SDNode atomic_op> :
341 PatFrag<(ops node:$ptr, node:$value),
342 (atomic_op node:$ptr, node:$value), [{
343 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
Tom Stellard13c68ef2013-09-05 18:38:09 +0000344}]>;
345
Matt Arsenault72574102014-06-11 18:08:34 +0000346
347def atomic_swap_local : local_binary_atomic_op<atomic_swap>;
348def atomic_load_add_local : local_binary_atomic_op<atomic_load_add>;
349def atomic_load_sub_local : local_binary_atomic_op<atomic_load_sub>;
350def atomic_load_and_local : local_binary_atomic_op<atomic_load_and>;
351def atomic_load_or_local : local_binary_atomic_op<atomic_load_or>;
352def atomic_load_xor_local : local_binary_atomic_op<atomic_load_xor>;
353def atomic_load_nand_local : local_binary_atomic_op<atomic_load_nand>;
354def atomic_load_min_local : local_binary_atomic_op<atomic_load_min>;
355def atomic_load_max_local : local_binary_atomic_op<atomic_load_max>;
356def atomic_load_umin_local : local_binary_atomic_op<atomic_load_umin>;
357def atomic_load_umax_local : local_binary_atomic_op<atomic_load_umax>;
Aaron Watry372cecf2013-09-06 20:17:42 +0000358
Tom Stellardd3ee8c12013-08-16 01:12:06 +0000359def mskor_global : PatFrag<(ops node:$val, node:$ptr),
360 (AMDGPUstore_mskor node:$val, node:$ptr), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000361 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;
Tom Stellardd3ee8c12013-08-16 01:12:06 +0000362}]>;
363
Matt Arsenault3f981402014-09-15 15:41:53 +0000364
Matt Arsenaultc793e1d2014-06-11 18:08:48 +0000365def atomic_cmp_swap_32_local :
366 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
367 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
368 AtomicSDNode *AN = cast<AtomicSDNode>(N);
369 return AN->getMemoryVT() == MVT::i32 &&
370 AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
371}]>;
372
Matt Arsenaultcaa0ec22014-06-11 18:08:54 +0000373def atomic_cmp_swap_64_local :
374 PatFrag<(ops node:$ptr, node:$cmp, node:$swap),
375 (atomic_cmp_swap node:$ptr, node:$cmp, node:$swap), [{
376 AtomicSDNode *AN = cast<AtomicSDNode>(N);
377 return AN->getMemoryVT() == MVT::i64 &&
378 AN->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS;
379}]>;
380
Matt Arsenault3f981402014-09-15 15:41:53 +0000381def flat_load : PatFrag<(ops node:$ptr), (load node:$ptr), [{
382 return isFlatLoad(dyn_cast<LoadSDNode>(N));
383}]>;
384
385def flat_store : PatFrag<(ops node:$val, node:$ptr),
386 (store node:$val, node:$ptr), [{
387 return isFlatStore(dyn_cast<StoreSDNode>(N));
388}]>;
389
390def mskor_flat : PatFrag<(ops node:$val, node:$ptr),
391 (AMDGPUstore_mskor node:$val, node:$ptr), [{
Benjamin Kramer619c4e52015-04-10 11:24:51 +0000392 return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::FLAT_ADDRESS;
Matt Arsenault3f981402014-09-15 15:41:53 +0000393}]>;
394
Tom Stellard7980fc82014-09-25 18:30:26 +0000395class global_binary_atomic_op<SDNode atomic_op> : PatFrag<
396 (ops node:$ptr, node:$value),
397 (atomic_op node:$ptr, node:$value),
398 [{return cast<MemSDNode>(N)->getAddressSpace() == AMDGPUAS::GLOBAL_ADDRESS;}]
399>;
400
Aaron Watry81144372014-10-17 23:33:03 +0000401def atomic_swap_global : global_binary_atomic_op<atomic_swap>;
Tom Stellard7980fc82014-09-25 18:30:26 +0000402def atomic_add_global : global_binary_atomic_op<atomic_load_add>;
Aaron Watry62127802014-10-17 23:32:54 +0000403def atomic_and_global : global_binary_atomic_op<atomic_load_and>;
Aaron Watry29f295d2014-10-17 23:32:56 +0000404def atomic_max_global : global_binary_atomic_op<atomic_load_max>;
Aaron Watry58c99922014-10-17 23:32:57 +0000405def atomic_min_global : global_binary_atomic_op<atomic_load_min>;
Aaron Watry8a911e62014-10-17 23:32:59 +0000406def atomic_or_global : global_binary_atomic_op<atomic_load_or>;
Aaron Watry328f1ba2014-10-17 23:32:52 +0000407def atomic_sub_global : global_binary_atomic_op<atomic_load_sub>;
Aaron Watry29f295d2014-10-17 23:32:56 +0000408def atomic_umax_global : global_binary_atomic_op<atomic_load_umax>;
Aaron Watry58c99922014-10-17 23:32:57 +0000409def atomic_umin_global : global_binary_atomic_op<atomic_load_umin>;
Aaron Watryd672ee22014-10-17 23:33:01 +0000410def atomic_xor_global : global_binary_atomic_op<atomic_load_xor>;
Tom Stellard7980fc82014-09-25 18:30:26 +0000411
Tom Stellardb4a313a2014-08-01 00:32:39 +0000412//===----------------------------------------------------------------------===//
413// Misc Pattern Fragments
414//===----------------------------------------------------------------------===//
415
Tom Stellard75aadc22012-12-11 21:25:42 +0000416class Constants {
417int TWO_PI = 0x40c90fdb;
418int PI = 0x40490fdb;
419int TWO_PI_INV = 0x3e22f983;
NAKAMURA Takumi4bb85f92013-10-28 04:07:23 +0000420int FP_UINT_MAX_PLUS_1 = 0x4f800000; // 1 << 32 in floating point encoding
Matt Arsenaultaeca2fa2014-05-31 06:47:42 +0000421int FP32_NEG_ONE = 0xbf800000;
422int FP32_ONE = 0x3f800000;
Tom Stellard75aadc22012-12-11 21:25:42 +0000423}
424def CONST : Constants;
425
426def FP_ZERO : PatLeaf <
427 (fpimm),
428 [{return N->getValueAPF().isZero();}]
429>;
430
431def FP_ONE : PatLeaf <
432 (fpimm),
433 [{return N->isExactlyValue(1.0);}]
434>;
435
Matt Arsenaulteeb2a7e2015-01-15 23:58:35 +0000436def FP_HALF : PatLeaf <
437 (fpimm),
438 [{return N->isExactlyValue(0.5);}]
439>;
440
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000441let isCodeGenOnly = 1, isPseudo = 1 in {
442
443let usesCustomInserter = 1 in {
Tom Stellard75aadc22012-12-11 21:25:42 +0000444
445class CLAMP <RegisterClass rc> : AMDGPUShaderInst <
446 (outs rc:$dst),
447 (ins rc:$src0),
448 "CLAMP $dst, $src0",
Matt Arsenault5d47d4a2014-06-12 21:15:44 +0000449 [(set f32:$dst, (AMDGPUclamp f32:$src0, (f32 FP_ZERO), (f32 FP_ONE)))]
Tom Stellard75aadc22012-12-11 21:25:42 +0000450>;
451
452class FABS <RegisterClass rc> : AMDGPUShaderInst <
453 (outs rc:$dst),
454 (ins rc:$src0),
455 "FABS $dst, $src0",
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000456 [(set f32:$dst, (fabs f32:$src0))]
Tom Stellard75aadc22012-12-11 21:25:42 +0000457>;
458
459class FNEG <RegisterClass rc> : AMDGPUShaderInst <
460 (outs rc:$dst),
461 (ins rc:$src0),
462 "FNEG $dst, $src0",
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000463 [(set f32:$dst, (fneg f32:$src0))]
Tom Stellard75aadc22012-12-11 21:25:42 +0000464>;
465
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000466} // usesCustomInserter = 1
467
468multiclass RegisterLoadStore <RegisterClass dstClass, Operand addrClass,
469 ComplexPattern addrPat> {
Tom Stellard81d871d2013-11-13 23:36:50 +0000470let UseNamedOperandTable = 1 in {
471
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000472 def RegisterLoad : AMDGPUShaderInst <
473 (outs dstClass:$dst),
474 (ins addrClass:$addr, i32imm:$chan),
475 "RegisterLoad $dst, $addr",
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000476 [(set i32:$dst, (AMDGPUregister_load addrPat:$addr, (i32 timm:$chan)))]
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000477 > {
478 let isRegisterLoad = 1;
479 }
480
481 def RegisterStore : AMDGPUShaderInst <
482 (outs),
483 (ins dstClass:$val, addrClass:$addr, i32imm:$chan),
484 "RegisterStore $val, $addr",
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000485 [(AMDGPUregister_store i32:$val, addrPat:$addr, (i32 timm:$chan))]
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000486 > {
487 let isRegisterStore = 1;
488 }
489}
Tom Stellard81d871d2013-11-13 23:36:50 +0000490}
Tom Stellardf3b2a1e2013-02-06 17:32:29 +0000491
492} // End isCodeGenOnly = 1, isPseudo = 1
Tom Stellard75aadc22012-12-11 21:25:42 +0000493
494/* Generic helper patterns for intrinsics */
495/* -------------------------------------- */
496
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000497class POW_Common <AMDGPUInst log_ieee, AMDGPUInst exp_ieee, AMDGPUInst mul>
498 : Pat <
499 (fpow f32:$src0, f32:$src1),
500 (exp_ieee (mul f32:$src1, (log_ieee f32:$src0)))
Tom Stellard75aadc22012-12-11 21:25:42 +0000501>;
502
503/* Other helper patterns */
504/* --------------------- */
505
506/* Extract element pattern */
Matt Arsenault530dde42014-02-26 23:00:58 +0000507class Extract_Element <ValueType sub_type, ValueType vec_type, int sub_idx,
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000508 SubRegIndex sub_reg>
509 : Pat<
510 (sub_type (vector_extract vec_type:$src, sub_idx)),
511 (EXTRACT_SUBREG $src, sub_reg)
Tom Stellard75aadc22012-12-11 21:25:42 +0000512>;
513
514/* Insert element pattern */
515class Insert_Element <ValueType elem_type, ValueType vec_type,
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000516 int sub_idx, SubRegIndex sub_reg>
517 : Pat <
518 (vector_insert vec_type:$vec, elem_type:$elem, sub_idx),
519 (INSERT_SUBREG $vec, $elem, sub_reg)
Tom Stellard75aadc22012-12-11 21:25:42 +0000520>;
521
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000522// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
523// can handle COPY instructions.
Tom Stellard75aadc22012-12-11 21:25:42 +0000524// bitconvert pattern
525class BitConvert <ValueType dt, ValueType st, RegisterClass rc> : Pat <
526 (dt (bitconvert (st rc:$src0))),
527 (dt rc:$src0)
528>;
529
Tom Stellard40b7f1f2013-05-02 15:30:12 +0000530// XXX: Convert to new syntax and use COPY_TO_REG, once the DFAPacketizer
531// can handle COPY instructions.
Tom Stellard75aadc22012-12-11 21:25:42 +0000532class DwordAddrPat<ValueType vt, RegisterClass rc> : Pat <
533 (vt (AMDGPUdwordaddr (vt rc:$addr))),
534 (vt rc:$addr)
535>;
536
Tom Stellard9d10c4c2013-04-19 02:11:06 +0000537// BFI_INT patterns
538
Matt Arsenault7d858d82014-11-02 23:46:54 +0000539multiclass BFIPatterns <Instruction BFI_INT,
540 Instruction LoadImm32,
541 RegisterClass RC64> {
Tom Stellard9d10c4c2013-04-19 02:11:06 +0000542 // Definition from ISA doc:
543 // (y & x) | (z & ~x)
544 def : Pat <
545 (or (and i32:$y, i32:$x), (and i32:$z, (not i32:$x))),
546 (BFI_INT $x, $y, $z)
547 >;
548
549 // SHA-256 Ch function
550 // z ^ (x & (y ^ z))
551 def : Pat <
552 (xor i32:$z, (and i32:$x, (xor i32:$y, i32:$z))),
553 (BFI_INT $x, $y, $z)
554 >;
555
Matt Arsenault6e439652014-06-10 19:00:20 +0000556 def : Pat <
557 (fcopysign f32:$src0, f32:$src1),
558 (BFI_INT (LoadImm32 0x7fffffff), $src0, $src1)
559 >;
560
561 def : Pat <
562 (f64 (fcopysign f64:$src0, f64:$src1)),
Matt Arsenault7d858d82014-11-02 23:46:54 +0000563 (REG_SEQUENCE RC64,
564 (i32 (EXTRACT_SUBREG $src0, sub0)), sub0,
Matt Arsenault6e439652014-06-10 19:00:20 +0000565 (BFI_INT (LoadImm32 0x7fffffff),
566 (i32 (EXTRACT_SUBREG $src0, sub1)),
567 (i32 (EXTRACT_SUBREG $src1, sub1))), sub1)
568 >;
Tom Stellard9d10c4c2013-04-19 02:11:06 +0000569}
570
Tom Stellardeac65dd2013-05-03 17:21:20 +0000571// SHA-256 Ma patterns
572
573// ((x & z) | (y & (x | z))) -> BFI_INT (XOR x, y), z, y
574class SHA256MaPattern <Instruction BFI_INT, Instruction XOR> : Pat <
575 (or (and i32:$x, i32:$z), (and i32:$y, (or i32:$x, i32:$z))),
576 (BFI_INT (XOR i32:$x, i32:$y), i32:$z, i32:$y)
577>;
578
Tom Stellard2b971eb2013-05-10 02:09:45 +0000579// Bitfield extract patterns
580
Marek Olsak949f5da2015-03-24 13:40:34 +0000581def IMMZeroBasedBitfieldMask : PatLeaf <(imm), [{
582 return isMask_32(N->getZExtValue());
583}]>;
Tom Stellarda2a4b8e2014-01-23 18:49:33 +0000584
Marek Olsak949f5da2015-03-24 13:40:34 +0000585def IMMPopCount : SDNodeXForm<imm, [{
Sergey Dmitrouk842a51b2015-04-28 14:05:47 +0000586 return CurDAG->getTargetConstant(countPopulation(N->getZExtValue()), SDLoc(N),
Marek Olsak949f5da2015-03-24 13:40:34 +0000587 MVT::i32);
588}]>;
Tom Stellarda2a4b8e2014-01-23 18:49:33 +0000589
Marek Olsak949f5da2015-03-24 13:40:34 +0000590class BFEPattern <Instruction BFE, Instruction MOV> : Pat <
591 (i32 (and (i32 (srl i32:$src, i32:$rshift)), IMMZeroBasedBitfieldMask:$mask)),
592 (BFE $src, $rshift, (MOV (i32 (IMMPopCount $mask))))
Tom Stellard2b971eb2013-05-10 02:09:45 +0000593>;
594
Tom Stellard5643c4a2013-05-20 15:02:19 +0000595// rotr pattern
596class ROTRPattern <Instruction BIT_ALIGN> : Pat <
597 (rotr i32:$src0, i32:$src1),
598 (BIT_ALIGN $src0, $src0, $src1)
599>;
600
Tom Stellard41fc7852013-07-23 01:48:42 +0000601// 24-bit arithmetic patterns
602def umul24 : PatFrag <(ops node:$x, node:$y), (mul node:$x, node:$y)>;
603
Matt Arsenaulteeb2a7e2015-01-15 23:58:35 +0000604// Special conversion patterns
605
606def cvt_rpi_i32_f32 : PatFrag <
607 (ops node:$src),
Matt Arsenault08ad3282015-01-31 21:28:13 +0000608 (fp_to_sint (ffloor (fadd $src, FP_HALF))),
609 [{ (void) N; return TM.Options.NoNaNsFPMath; }]
Matt Arsenaulteeb2a7e2015-01-15 23:58:35 +0000610>;
611
612def cvt_flr_i32_f32 : PatFrag <
613 (ops node:$src),
Matt Arsenault08ad3282015-01-31 21:28:13 +0000614 (fp_to_sint (ffloor $src)),
615 [{ (void)N; return TM.Options.NoNaNsFPMath; }]
Matt Arsenaulteeb2a7e2015-01-15 23:58:35 +0000616>;
617
Tom Stellard41fc7852013-07-23 01:48:42 +0000618/*
619class UMUL24Pattern <Instruction UMUL24> : Pat <
620 (mul U24:$x, U24:$y),
621 (UMUL24 $x, $y)
622>;
623*/
624
Matt Arsenaulteb260202014-05-22 18:00:15 +0000625class IMad24Pat<Instruction Inst> : Pat <
626 (add (AMDGPUmul_i24 i32:$src0, i32:$src1), i32:$src2),
627 (Inst $src0, $src1, $src2)
628>;
629
630class UMad24Pat<Instruction Inst> : Pat <
631 (add (AMDGPUmul_u24 i32:$src0, i32:$src1), i32:$src2),
632 (Inst $src0, $src1, $src2)
633>;
634
Matt Arsenault493c5f12014-05-22 18:00:24 +0000635multiclass Expand24IBitOps<Instruction MulInst, Instruction AddInst> {
636 def _expand_imad24 : Pat <
637 (AMDGPUmad_i24 i32:$src0, i32:$src1, i32:$src2),
638 (AddInst (MulInst $src0, $src1), $src2)
639 >;
Matt Arsenaultf15a0562014-05-22 18:00:20 +0000640
Matt Arsenault493c5f12014-05-22 18:00:24 +0000641 def _expand_imul24 : Pat <
642 (AMDGPUmul_i24 i32:$src0, i32:$src1),
643 (MulInst $src0, $src1)
644 >;
645}
Matt Arsenaultf15a0562014-05-22 18:00:20 +0000646
Matt Arsenault493c5f12014-05-22 18:00:24 +0000647multiclass Expand24UBitOps<Instruction MulInst, Instruction AddInst> {
648 def _expand_umad24 : Pat <
649 (AMDGPUmad_u24 i32:$src0, i32:$src1, i32:$src2),
650 (AddInst (MulInst $src0, $src1), $src2)
651 >;
652
653 def _expand_umul24 : Pat <
654 (AMDGPUmul_u24 i32:$src0, i32:$src1),
655 (MulInst $src0, $src1)
656 >;
657}
Matt Arsenaulteb260202014-05-22 18:00:15 +0000658
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000659class RcpPat<Instruction RcpInst, ValueType vt> : Pat <
660 (fdiv FP_ONE, vt:$src),
661 (RcpInst $src)
662>;
663
Matt Arsenault0bbcd8b2015-02-14 04:30:08 +0000664class RsqPat<Instruction RsqInst, ValueType vt> : Pat <
665 (AMDGPUrcp (fsqrt vt:$src)),
666 (RsqInst $src)
667>;
Matt Arsenaulta0050b02014-06-19 01:19:19 +0000668
Tom Stellard75aadc22012-12-11 21:25:42 +0000669include "R600Instructions.td"
Tom Stellard2c1c9de2014-03-24 16:07:25 +0000670include "R700Instructions.td"
671include "EvergreenInstructions.td"
672include "CaymanInstructions.td"
Tom Stellard75aadc22012-12-11 21:25:42 +0000673
674include "SIInstrInfo.td"
675