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gerrit-public.fairphone.software / toolchain / llvm-project / 9a17d7ac6e548fbe40778205ed16be50bc4626c5 / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: 79a1ddea786ded24da2d5c1efe414061224540be [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]21#include "llvm/CodeGen/LivePhysRegs.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]22#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]23#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]24#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]25#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]26#include "llvm/CodeGen/MachineInstrBuilder.h"
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]27#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]28#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]29#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]30#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]31#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]32#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]33#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]34#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]35#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]36#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]37#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]38#include "llvm/Support/ErrorHandling.h"
39#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]40#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]41
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]42using namespace llvm;
43
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]44#define DEBUG_TYPE "x86-instr-info"
45
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]46#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]47#include "X86GenInstrInfo.inc"
48
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]49static cl::opt<bool>
50NoFusing("disable-spill-fusing",
51 cl::desc("Disable fusing of spill code into instructions"));
52static cl::opt<bool>
53PrintFailedFusing("print-failed-fuse-candidates",
54 cl::desc("Print instructions that the allocator wants to"
55 " fuse, but the X86 backend currently can't"),
56 cl::Hidden);
57static cl::opt<bool>
58ReMatPICStubLoad("remat-pic-stub-load",
59 cl::desc("Re-materialize load from stub in PIC mode"),
60 cl::init(false), cl::Hidden);
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]61static cl::opt<unsigned>
62PartialRegUpdateClearance("partial-reg-update-clearance",
63 cl::desc("Clearance between two register writes "
64 "for inserting XOR to avoid partial "
65 "register update"),
66 cl::init(64), cl::Hidden);
67static cl::opt<unsigned>
68UndefRegClearance("undef-reg-clearance",
69 cl::desc("How many idle instructions we would like before "
70 "certain undef register reads"),
71 cl::init(64), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]72
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]73enum {
74 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]75 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]76 TB_INDEX_0 = 0,
77 TB_INDEX_1 = 1,
78 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]79 TB_INDEX_3 = 3,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]80 TB_INDEX_4 = 4,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]81 TB_INDEX_MASK = 0xf,
82
83 // Do not insert the reverse map (MemOp -> RegOp) into the table.
84 // This may be needed because there is a many -> one mapping.
85 TB_NO_REVERSE = 1 << 4,
86
87 // Do not insert the forward map (RegOp -> MemOp) into the table.
88 // This is needed for Native Client, which prohibits branch
89 // instructions from using a memory operand.
90 TB_NO_FORWARD = 1 << 5,
91
92 TB_FOLDED_LOAD = 1 << 6,
93 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]94
95 // Minimum alignment required for load/store.
96 // Used for RegOp->MemOp conversion.
97 // (stored in bits 8 - 15)
98 TB_ALIGN_SHIFT = 8,
99 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
100 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
101 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]102 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]103 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]104};
105
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]106struct X86MemoryFoldTableEntry {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]107 uint16_t RegOp;
108 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]109 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]110};
111
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]112// Pin the vtable to this file.
113void X86InstrInfo::anchor() {}
114
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]115X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
David Majnemerf828a0c2015-10-01 18:44:59 +0000[diff] [blame]116 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
117 : X86::ADJCALLSTACKDOWN32),
118 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
119 : X86::ADJCALLSTACKUP32),
120 X86::CATCHRET),
Eric Christophered6a4462015-03-12 17:54:19 +0000[diff] [blame]121 Subtarget(STI), RI(STI.getTargetTriple()) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]122
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]123 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]124 { X86::ADC32ri, X86::ADC32mi, 0 },
125 { X86::ADC32ri8, X86::ADC32mi8, 0 },
126 { X86::ADC32rr, X86::ADC32mr, 0 },
127 { X86::ADC64ri32, X86::ADC64mi32, 0 },
128 { X86::ADC64ri8, X86::ADC64mi8, 0 },
129 { X86::ADC64rr, X86::ADC64mr, 0 },
130 { X86::ADD16ri, X86::ADD16mi, 0 },
131 { X86::ADD16ri8, X86::ADD16mi8, 0 },
132 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
133 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
134 { X86::ADD16rr, X86::ADD16mr, 0 },
135 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
136 { X86::ADD32ri, X86::ADD32mi, 0 },
137 { X86::ADD32ri8, X86::ADD32mi8, 0 },
138 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
139 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
140 { X86::ADD32rr, X86::ADD32mr, 0 },
141 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
142 { X86::ADD64ri32, X86::ADD64mi32, 0 },
143 { X86::ADD64ri8, X86::ADD64mi8, 0 },
144 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
145 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
146 { X86::ADD64rr, X86::ADD64mr, 0 },
147 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
148 { X86::ADD8ri, X86::ADD8mi, 0 },
149 { X86::ADD8rr, X86::ADD8mr, 0 },
150 { X86::AND16ri, X86::AND16mi, 0 },
151 { X86::AND16ri8, X86::AND16mi8, 0 },
152 { X86::AND16rr, X86::AND16mr, 0 },
153 { X86::AND32ri, X86::AND32mi, 0 },
154 { X86::AND32ri8, X86::AND32mi8, 0 },
155 { X86::AND32rr, X86::AND32mr, 0 },
156 { X86::AND64ri32, X86::AND64mi32, 0 },
157 { X86::AND64ri8, X86::AND64mi8, 0 },
158 { X86::AND64rr, X86::AND64mr, 0 },
159 { X86::AND8ri, X86::AND8mi, 0 },
160 { X86::AND8rr, X86::AND8mr, 0 },
161 { X86::DEC16r, X86::DEC16m, 0 },
162 { X86::DEC32r, X86::DEC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]163 { X86::DEC64r, X86::DEC64m, 0 },
164 { X86::DEC8r, X86::DEC8m, 0 },
165 { X86::INC16r, X86::INC16m, 0 },
166 { X86::INC32r, X86::INC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]167 { X86::INC64r, X86::INC64m, 0 },
168 { X86::INC8r, X86::INC8m, 0 },
169 { X86::NEG16r, X86::NEG16m, 0 },
170 { X86::NEG32r, X86::NEG32m, 0 },
171 { X86::NEG64r, X86::NEG64m, 0 },
172 { X86::NEG8r, X86::NEG8m, 0 },
173 { X86::NOT16r, X86::NOT16m, 0 },
174 { X86::NOT32r, X86::NOT32m, 0 },
175 { X86::NOT64r, X86::NOT64m, 0 },
176 { X86::NOT8r, X86::NOT8m, 0 },
177 { X86::OR16ri, X86::OR16mi, 0 },
178 { X86::OR16ri8, X86::OR16mi8, 0 },
179 { X86::OR16rr, X86::OR16mr, 0 },
180 { X86::OR32ri, X86::OR32mi, 0 },
181 { X86::OR32ri8, X86::OR32mi8, 0 },
182 { X86::OR32rr, X86::OR32mr, 0 },
183 { X86::OR64ri32, X86::OR64mi32, 0 },
184 { X86::OR64ri8, X86::OR64mi8, 0 },
185 { X86::OR64rr, X86::OR64mr, 0 },
186 { X86::OR8ri, X86::OR8mi, 0 },
187 { X86::OR8rr, X86::OR8mr, 0 },
188 { X86::ROL16r1, X86::ROL16m1, 0 },
189 { X86::ROL16rCL, X86::ROL16mCL, 0 },
190 { X86::ROL16ri, X86::ROL16mi, 0 },
191 { X86::ROL32r1, X86::ROL32m1, 0 },
192 { X86::ROL32rCL, X86::ROL32mCL, 0 },
193 { X86::ROL32ri, X86::ROL32mi, 0 },
194 { X86::ROL64r1, X86::ROL64m1, 0 },
195 { X86::ROL64rCL, X86::ROL64mCL, 0 },
196 { X86::ROL64ri, X86::ROL64mi, 0 },
197 { X86::ROL8r1, X86::ROL8m1, 0 },
198 { X86::ROL8rCL, X86::ROL8mCL, 0 },
199 { X86::ROL8ri, X86::ROL8mi, 0 },
200 { X86::ROR16r1, X86::ROR16m1, 0 },
201 { X86::ROR16rCL, X86::ROR16mCL, 0 },
202 { X86::ROR16ri, X86::ROR16mi, 0 },
203 { X86::ROR32r1, X86::ROR32m1, 0 },
204 { X86::ROR32rCL, X86::ROR32mCL, 0 },
205 { X86::ROR32ri, X86::ROR32mi, 0 },
206 { X86::ROR64r1, X86::ROR64m1, 0 },
207 { X86::ROR64rCL, X86::ROR64mCL, 0 },
208 { X86::ROR64ri, X86::ROR64mi, 0 },
209 { X86::ROR8r1, X86::ROR8m1, 0 },
210 { X86::ROR8rCL, X86::ROR8mCL, 0 },
211 { X86::ROR8ri, X86::ROR8mi, 0 },
212 { X86::SAR16r1, X86::SAR16m1, 0 },
213 { X86::SAR16rCL, X86::SAR16mCL, 0 },
214 { X86::SAR16ri, X86::SAR16mi, 0 },
215 { X86::SAR32r1, X86::SAR32m1, 0 },
216 { X86::SAR32rCL, X86::SAR32mCL, 0 },
217 { X86::SAR32ri, X86::SAR32mi, 0 },
218 { X86::SAR64r1, X86::SAR64m1, 0 },
219 { X86::SAR64rCL, X86::SAR64mCL, 0 },
220 { X86::SAR64ri, X86::SAR64mi, 0 },
221 { X86::SAR8r1, X86::SAR8m1, 0 },
222 { X86::SAR8rCL, X86::SAR8mCL, 0 },
223 { X86::SAR8ri, X86::SAR8mi, 0 },
224 { X86::SBB32ri, X86::SBB32mi, 0 },
225 { X86::SBB32ri8, X86::SBB32mi8, 0 },
226 { X86::SBB32rr, X86::SBB32mr, 0 },
227 { X86::SBB64ri32, X86::SBB64mi32, 0 },
228 { X86::SBB64ri8, X86::SBB64mi8, 0 },
229 { X86::SBB64rr, X86::SBB64mr, 0 },
230 { X86::SHL16rCL, X86::SHL16mCL, 0 },
231 { X86::SHL16ri, X86::SHL16mi, 0 },
232 { X86::SHL32rCL, X86::SHL32mCL, 0 },
233 { X86::SHL32ri, X86::SHL32mi, 0 },
234 { X86::SHL64rCL, X86::SHL64mCL, 0 },
235 { X86::SHL64ri, X86::SHL64mi, 0 },
236 { X86::SHL8rCL, X86::SHL8mCL, 0 },
237 { X86::SHL8ri, X86::SHL8mi, 0 },
238 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
239 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
240 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
241 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
242 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
243 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
244 { X86::SHR16r1, X86::SHR16m1, 0 },
245 { X86::SHR16rCL, X86::SHR16mCL, 0 },
246 { X86::SHR16ri, X86::SHR16mi, 0 },
247 { X86::SHR32r1, X86::SHR32m1, 0 },
248 { X86::SHR32rCL, X86::SHR32mCL, 0 },
249 { X86::SHR32ri, X86::SHR32mi, 0 },
250 { X86::SHR64r1, X86::SHR64m1, 0 },
251 { X86::SHR64rCL, X86::SHR64mCL, 0 },
252 { X86::SHR64ri, X86::SHR64mi, 0 },
253 { X86::SHR8r1, X86::SHR8m1, 0 },
254 { X86::SHR8rCL, X86::SHR8mCL, 0 },
255 { X86::SHR8ri, X86::SHR8mi, 0 },
256 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
257 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
258 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
259 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
260 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
261 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
262 { X86::SUB16ri, X86::SUB16mi, 0 },
263 { X86::SUB16ri8, X86::SUB16mi8, 0 },
264 { X86::SUB16rr, X86::SUB16mr, 0 },
265 { X86::SUB32ri, X86::SUB32mi, 0 },
266 { X86::SUB32ri8, X86::SUB32mi8, 0 },
267 { X86::SUB32rr, X86::SUB32mr, 0 },
268 { X86::SUB64ri32, X86::SUB64mi32, 0 },
269 { X86::SUB64ri8, X86::SUB64mi8, 0 },
270 { X86::SUB64rr, X86::SUB64mr, 0 },
271 { X86::SUB8ri, X86::SUB8mi, 0 },
272 { X86::SUB8rr, X86::SUB8mr, 0 },
273 { X86::XOR16ri, X86::XOR16mi, 0 },
274 { X86::XOR16ri8, X86::XOR16mi8, 0 },
275 { X86::XOR16rr, X86::XOR16mr, 0 },
276 { X86::XOR32ri, X86::XOR32mi, 0 },
277 { X86::XOR32ri8, X86::XOR32mi8, 0 },
278 { X86::XOR32rr, X86::XOR32mr, 0 },
279 { X86::XOR64ri32, X86::XOR64mi32, 0 },
280 { X86::XOR64ri8, X86::XOR64mi8, 0 },
281 { X86::XOR64rr, X86::XOR64mr, 0 },
282 { X86::XOR8ri, X86::XOR8mi, 0 },
283 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]284 };
285
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]286 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]287 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]288 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]289 // Index 0, folded load and store, no alignment requirement.
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]290 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]291 }
292
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]293 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]294 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
295 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
296 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
297 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
298 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]299 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
300 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
301 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
302 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
303 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
304 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
305 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
306 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
307 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
308 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
309 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
310 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
311 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
312 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
313 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]314 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]315 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
316 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
317 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
318 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
319 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
320 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
321 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
322 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
323 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
324 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
325 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
326 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
327 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
328 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
329 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
330 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
331 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
332 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
333 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
334 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
335 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
336 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]337 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
338 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
339 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
340 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
341 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
342 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]343 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
344 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
345 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
346 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]347 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
348 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]349 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
350 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
351 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]352 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
353 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
354 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
355 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
356 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
357 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
358 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
359 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
360 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
361 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
362 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
363 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
364 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
365 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
366 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
367 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
368 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
369 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
Reid Klecknera580b6e2015-01-30 21:03:31 +0000[diff] [blame]370 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]371 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
372 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
373 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]374 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]375
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]376 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]377 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]378 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]379 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
380 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
381 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
382 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
383 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
384 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
385 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
386 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
387 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]388 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
389 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]390
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]391 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]392 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]393 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
394 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
395 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
396 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]397 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]398
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]399 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]400 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
401 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
402 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
403 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
404 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
405 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
406 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]407 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
408 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]409 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]410 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]411
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]412 // AVX-512 foldable instructions (256-bit versions)
413 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
414 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
415 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
416 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
417 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
418 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
419 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
420 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
421 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
422 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]423
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]424 // AVX-512 foldable instructions (128-bit versions)
425 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
426 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
427 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
428 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
429 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
430 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
431 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
432 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
433 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]434 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]435
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]436 // F16C foldable instructions
437 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
438 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]439 };
440
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]441 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]442 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]443 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]444 }
445
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]446 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
Simon Pilgrim3a771802015-06-07 18:34:25 +0000[diff] [blame]447 { X86::BSF16rr, X86::BSF16rm, 0 },
448 { X86::BSF32rr, X86::BSF32rm, 0 },
449 { X86::BSF64rr, X86::BSF64rm, 0 },
450 { X86::BSR16rr, X86::BSR16rm, 0 },
451 { X86::BSR32rr, X86::BSR32rm, 0 },
452 { X86::BSR64rr, X86::BSR64rm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]453 { X86::CMP16rr, X86::CMP16rm, 0 },
454 { X86::CMP32rr, X86::CMP32rm, 0 },
455 { X86::CMP64rr, X86::CMP64rm, 0 },
456 { X86::CMP8rr, X86::CMP8rm, 0 },
457 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
458 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
459 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
460 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
461 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
462 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
463 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
464 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
465 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
466 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]467 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
468 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
469 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
470 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
471 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
472 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
473 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
474 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]475 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
476 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]477 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
478 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]479 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]480 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]481 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]482 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]483 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]484 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]485 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
486 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
487 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
488 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
489 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
490 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
491 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
492 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]493 { X86::MOV16rr, X86::MOV16rm, 0 },
494 { X86::MOV32rr, X86::MOV32rm, 0 },
495 { X86::MOV64rr, X86::MOV64rm, 0 },
496 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
497 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
498 { X86::MOV8rr, X86::MOV8rm, 0 },
499 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
500 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]501 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
502 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
503 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
504 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]505 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
506 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
507 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
508 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
509 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
510 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
511 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
512 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
513 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
514 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]515 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
516 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
517 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
518 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
519 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]520 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
521 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
522 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]523 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
524 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
525 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
526 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
527 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
528 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
529 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
530 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
531 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
532 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
533 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
534 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
535 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
536 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
537 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
538 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
539 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]540 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
541 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
542 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]543 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]544 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]545 { X86::RCPSSr, X86::RCPSSm, 0 },
546 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]547 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
548 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]549 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]550 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
551 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
552 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]553 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]554 { X86::SQRTSDr, X86::SQRTSDm, 0 },
555 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
556 { X86::SQRTSSr, X86::SQRTSSm, 0 },
557 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
558 { X86::TEST16rr, X86::TEST16rm, 0 },
559 { X86::TEST32rr, X86::TEST32rm, 0 },
560 { X86::TEST64rr, X86::TEST64rm, 0 },
561 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]562 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]563 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
564 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]565
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]566 // MMX version of foldable instructions
567 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
568 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
569 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
570 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
571 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
572 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
573 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
574 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
575 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
576 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
577
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]578 // 3DNow! version of foldable instructions
579 { X86::PF2IDrr, X86::PF2IDrm, 0 },
580 { X86::PF2IWrr, X86::PF2IWrm, 0 },
581 { X86::PFRCPrr, X86::PFRCPrm, 0 },
582 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
583 { X86::PI2FDrr, X86::PI2FDrm, 0 },
584 { X86::PI2FWrr, X86::PI2FWrm, 0 },
585 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
586
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]587 // AVX 128-bit versions of foldable instructions
588 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
589 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]590 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
591 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]592 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
593 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]594 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]595 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
596 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
597 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
598 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
599 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
600 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
601 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
602 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
603 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]604 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]605 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]606 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]607 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]608 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]609 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]610 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
611 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]612 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
613 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
614 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
615 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
616 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
617 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
618 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
619 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]620 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
621 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]622 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]623 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]624 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]625 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
626 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
627 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]628 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
629 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
630 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
631 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
632 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]633 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
634 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]635 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
636 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
637 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
638 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
639 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
640 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
641 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
642 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
643 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
644 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
645 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
646 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]647 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
648 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
649 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]650 { X86::VPTESTrr, X86::VPTESTrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]651 { X86::VRCPPSr, X86::VRCPPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]652 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
653 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]654 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]655 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]656 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]657 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
658 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]659 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]660 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]661
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]662 // AVX 256-bit foldable instructions
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]663 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]664 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]665 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]666 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]667 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]668 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]669 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
670 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]671 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
672 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]673 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]674 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]675 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
676 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]677 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]678 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]679 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
680 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima2618672015-02-07 21:44:06 +0000[diff] [blame]681 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]682 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]683 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
684 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]685 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
686 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
687 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]688 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
689 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]690
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]691 // AVX2 foldable instructions
Sanjay Patel1a20fdf2015-02-17 22:09:54 +0000[diff] [blame]692
693 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
694 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
695 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
696 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
697 // so they don't need an equivalent limitation.
Simon Pilgrimd11b0132015-02-08 17:13:54 +0000[diff] [blame]698 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
699 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
700 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]701 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
702 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
703 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]704 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
705 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
706 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
707 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
708 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
709 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
710 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
711 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
712 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
713 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
714 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
715 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
716 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
717 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
718 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
719 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
720 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
721 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
722 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
723 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
724 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
725 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]726 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
727 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
728 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]729
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]730 // XOP foldable instructions
731 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
732 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
733 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
734 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
735 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
736 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
737 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
738 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
739 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
740 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
741 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
742 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
743 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
744 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
745 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
746 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
747 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
748 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
749 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
750 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
751 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
752 { X86::VPROTBri, X86::VPROTBmi, 0 },
753 { X86::VPROTBrr, X86::VPROTBmr, 0 },
754 { X86::VPROTDri, X86::VPROTDmi, 0 },
755 { X86::VPROTDrr, X86::VPROTDmr, 0 },
756 { X86::VPROTQri, X86::VPROTQmi, 0 },
757 { X86::VPROTQrr, X86::VPROTQmr, 0 },
758 { X86::VPROTWri, X86::VPROTWmi, 0 },
759 { X86::VPROTWrr, X86::VPROTWmr, 0 },
760 { X86::VPSHABrr, X86::VPSHABmr, 0 },
761 { X86::VPSHADrr, X86::VPSHADmr, 0 },
762 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
763 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
764 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
765 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
766 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
767 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
768
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]769 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]770 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
771 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]772 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
773 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
774 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
775 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
776 { X86::BLCI32rr, X86::BLCI32rm, 0 },
777 { X86::BLCI64rr, X86::BLCI64rm, 0 },
778 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
779 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
780 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
781 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
782 { X86::BLCS32rr, X86::BLCS32rm, 0 },
783 { X86::BLCS64rr, X86::BLCS64rm, 0 },
784 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
785 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]786 { X86::BLSI32rr, X86::BLSI32rm, 0 },
787 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]788 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
789 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]790 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
791 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
792 { X86::BLSR32rr, X86::BLSR32rm, 0 },
793 { X86::BLSR64rr, X86::BLSR64rm, 0 },
794 { X86::BZHI32rr, X86::BZHI32rm, 0 },
795 { X86::BZHI64rr, X86::BZHI64rm, 0 },
796 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
797 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
798 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
799 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
800 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
801 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]802 { X86::RORX32ri, X86::RORX32mi, 0 },
803 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]804 { X86::SARX32rr, X86::SARX32rm, 0 },
805 { X86::SARX64rr, X86::SARX64rm, 0 },
806 { X86::SHRX32rr, X86::SHRX32rm, 0 },
807 { X86::SHRX64rr, X86::SHRX64rm, 0 },
808 { X86::SHLX32rr, X86::SHLX32rm, 0 },
809 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]810 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
811 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]812 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
813 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
814 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]815 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
816 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]817
818 // AVX-512 foldable instructions
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]819 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
820 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
821 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
822 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
823 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
824 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
825 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
826 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
827 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
828 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
829 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
830 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
831 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
832 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
833 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
834 { X86::VBROADCASTSSZr_s, X86::VBROADCASTSSZm, TB_NO_REVERSE },
835 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
836 { X86::VBROADCASTSDZr_s, X86::VBROADCASTSDZm, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]837
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]838 // AVX-512 foldable instructions (256-bit versions)
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]839 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
840 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
841 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
842 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
843 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
844 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
845 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
846 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
847 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
848 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
849 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
850 { X86::VBROADCASTSSZ256r_s, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
851 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
852 { X86::VBROADCASTSDZ256r_s, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]853
Igor Breger131008f2016-05-01 08:40:00 +0000[diff] [blame]854 // AVX-512 foldable instructions (128-bit versions)
855 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
856 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
857 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
858 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
859 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
860 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
861 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
862 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
863 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
864 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
865 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
866 { X86::VBROADCASTSSZ128r_s, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]867 // F16C foldable instructions
868 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
869 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]870
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]871 // AES foldable instructions
872 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
873 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
Simon Pilgrim295eaad2015-02-12 20:01:03 +0000[diff] [blame]874 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
875 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]876 };
877
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]878 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]879 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]880 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]881 // Index 1, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]882 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]883 }
884
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]885 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]886 { X86::ADC32rr, X86::ADC32rm, 0 },
887 { X86::ADC64rr, X86::ADC64rm, 0 },
888 { X86::ADD16rr, X86::ADD16rm, 0 },
889 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
890 { X86::ADD32rr, X86::ADD32rm, 0 },
891 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
892 { X86::ADD64rr, X86::ADD64rm, 0 },
893 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
894 { X86::ADD8rr, X86::ADD8rm, 0 },
895 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
896 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
897 { X86::ADDSDrr, X86::ADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]898 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]899 { X86::ADDSSrr, X86::ADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]900 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]901 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
902 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
903 { X86::AND16rr, X86::AND16rm, 0 },
904 { X86::AND32rr, X86::AND32rm, 0 },
905 { X86::AND64rr, X86::AND64rm, 0 },
906 { X86::AND8rr, X86::AND8rm, 0 },
907 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
908 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
909 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
910 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]911 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
912 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
913 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
914 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]915 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
916 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
917 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
918 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
919 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
920 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
921 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
922 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
923 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
924 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
925 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
926 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
927 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
928 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
929 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
930 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
931 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
932 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
933 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
934 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
935 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
936 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
937 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
938 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
939 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
940 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
941 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
942 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
943 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
944 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
945 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
946 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
947 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
948 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
949 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
950 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
951 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
952 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
953 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
954 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
955 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
956 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
957 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
958 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
959 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
960 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
961 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
962 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
963 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
964 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
965 { X86::CMPSDrr, X86::CMPSDrm, 0 },
966 { X86::CMPSSrr, X86::CMPSSrm, 0 },
Simon Pilgrim01846222015-04-03 14:24:40 +0000[diff] [blame]967 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
968 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]969 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
970 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
971 { X86::DIVSDrr, X86::DIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]972 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]973 { X86::DIVSSrr, X86::DIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]974 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
975 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
976 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]977
Sanjay Patel8c13e362015-07-28 00:48:32 +0000[diff] [blame]978 // Do not fold Fs* scalar logical op loads because there are no scalar
979 // load variants for these instructions. When folded, the load is required
980 // to be 128-bits, so the load size would not match.
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]981
982 { X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 },
983 { X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 },
984 { X86::FvANDPDrr, X86::FvANDPDrm, TB_ALIGN_16 },
985 { X86::FvANDPSrr, X86::FvANDPSrm, TB_ALIGN_16 },
986 { X86::FvORPDrr, X86::FvORPDrm, TB_ALIGN_16 },
987 { X86::FvORPSrr, X86::FvORPSrm, TB_ALIGN_16 },
988 { X86::FvXORPDrr, X86::FvXORPDrm, TB_ALIGN_16 },
989 { X86::FvXORPSrr, X86::FvXORPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]990 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
991 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
992 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
993 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
994 { X86::IMUL16rr, X86::IMUL16rm, 0 },
995 { X86::IMUL32rr, X86::IMUL32rm, 0 },
996 { X86::IMUL64rr, X86::IMUL64rm, 0 },
997 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
998 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]999 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
1000 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
1001 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
1002 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
1003 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
1004 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1005 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1006 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1007 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1008 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1009 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1010 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1011 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1012 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1013 { X86::MINSDrr, X86::MINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1014 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1015 { X86::MINSSrr, X86::MINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1016 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1017 { X86::MOVLHPSrr, X86::MOVHPSrm, TB_NO_REVERSE },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1018 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1019 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1020 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1021 { X86::MULSDrr, X86::MULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1022 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1023 { X86::MULSSrr, X86::MULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1024 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1025 { X86::OR16rr, X86::OR16rm, 0 },
1026 { X86::OR32rr, X86::OR32rm, 0 },
1027 { X86::OR64rr, X86::OR64rm, 0 },
1028 { X86::OR8rr, X86::OR8rm, 0 },
1029 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1030 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1031 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1032 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1033 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1034 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1035 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1036 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1037 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1038 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1039 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1040 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1041 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1042 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1043 { X86::PALIGNRrri, X86::PALIGNRrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1044 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1045 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1046 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1047 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1048 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1049 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1050 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1051 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1052 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1053 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1054 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1055 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1056 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1057 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1058 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1059 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1060 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1061 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1062 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1063 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1064 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1065 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1066 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1067 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1068 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1069 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1070 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1071 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1072 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1073 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1074 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]1075 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1076 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1077 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1078 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1079 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1080 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1081 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1082 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1083 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1084 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1085 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1086 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1087 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1088 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1089 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1090 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1091 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1092 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1093 { X86::PSIGNBrr128, X86::PSIGNBrm128, TB_ALIGN_16 },
1094 { X86::PSIGNWrr128, X86::PSIGNWrm128, TB_ALIGN_16 },
1095 { X86::PSIGNDrr128, X86::PSIGNDrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1096 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1097 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1098 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1099 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1100 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1101 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1102 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1103 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1104 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1105 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1106 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1107 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1108 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1109 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1110 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1111 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1112 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1113 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1114 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1115 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1116 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1117 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1118 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1119 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1120 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1121 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
1122 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1123 { X86::SBB32rr, X86::SBB32rm, 0 },
1124 { X86::SBB64rr, X86::SBB64rm, 0 },
1125 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1126 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1127 { X86::SUB16rr, X86::SUB16rm, 0 },
1128 { X86::SUB32rr, X86::SUB32rm, 0 },
1129 { X86::SUB64rr, X86::SUB64rm, 0 },
1130 { X86::SUB8rr, X86::SUB8rm, 0 },
1131 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1132 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1133 { X86::SUBSDrr, X86::SUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1134 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1135 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1136 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1137 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1138 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1139 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1140 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1141 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1142 { X86::XOR16rr, X86::XOR16rm, 0 },
1143 { X86::XOR32rr, X86::XOR32rm, 0 },
1144 { X86::XOR64rr, X86::XOR64rm, 0 },
1145 { X86::XOR8rr, X86::XOR8rm, 0 },
1146 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1147 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1148
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]1149 // MMX version of foldable instructions
1150 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1151 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1152 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1153 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1154 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1155 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1156 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1157 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1158 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1159 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1160 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1161 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1162 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1163 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1164 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1165 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1166 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1167 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1168 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1169 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1170 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1171 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1172 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1173 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1174 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1175 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1176 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1177 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1178 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1179 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1180 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1181 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1182 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1183 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1184 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1185 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1186 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1187 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1188 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1189 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1190 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1191 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1192 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1193 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1194 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1195 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1196 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1197 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1198 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1199 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1200 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1201 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1202 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1203 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1204 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1205 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1206 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1207 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1208 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1209 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1210 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1211 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1212 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1213 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1214 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1215 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1216 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1217 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1218 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1219 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1220
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]1221 // 3DNow! version of foldable instructions
1222 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1223 { X86::PFACCrr, X86::PFACCrm, 0 },
1224 { X86::PFADDrr, X86::PFADDrm, 0 },
1225 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1226 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1227 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1228 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1229 { X86::PFMINrr, X86::PFMINrm, 0 },
1230 { X86::PFMULrr, X86::PFMULrm, 0 },
1231 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1232 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1233 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1234 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1235 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1236 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1237 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1238 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1239
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1240 // AVX 128-bit versions of foldable instructions
1241 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1242 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1243 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1244 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1245 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1246 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1247 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1248 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1249 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1250 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]1251 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1252 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1253 { X86::VRCPSSr, X86::VRCPSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1254 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1255 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1256 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1257 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1258 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1259 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1260 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1261 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1262 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1263 { X86::VADDSDrr, X86::VADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1264 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1265 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1266 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1267 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1268 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1269 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1270 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1271 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1272 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1273 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1274 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1275 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1276 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1277 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1278 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1279 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1280 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1281 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1282 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1283 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1284 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1285 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1286 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1287 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1288 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]1289 // Do not fold VFs* loads because there are no scalar load variants for
1290 // these instructions. When folded, the load is required to be 128-bits, so
1291 // the load size would not match.
1292 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 },
1293 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 },
1294 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 },
1295 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 },
1296 { X86::VFvORPDrr, X86::VFvORPDrm, 0 },
1297 { X86::VFvORPSrr, X86::VFvORPSrm, 0 },
1298 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 },
1299 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1300 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1301 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1302 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1303 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1304 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1305 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1306 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1307 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1308 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1309 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1310 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1311 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1312 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1313 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1314 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1315 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1316 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1317 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]1318 { X86::VMOVLHPSrr, X86::VMOVHPSrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1319 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1320 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1321 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1322 { X86::VMULSDrr, X86::VMULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1323 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1324 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1325 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1326 { X86::VORPDrr, X86::VORPDrm, 0 },
1327 { X86::VORPSrr, X86::VORPSrm, 0 },
1328 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1329 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1330 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1331 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1332 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1333 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1334 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1335 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1336 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1337 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1338 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1339 { X86::VPADDWrr, X86::VPADDWrm, 0 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1340 { X86::VPALIGNRrri, X86::VPALIGNRrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1341 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1342 { X86::VPANDrr, X86::VPANDrm, 0 },
1343 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1344 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1345 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1346 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1347 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1348 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1349 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1350 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1351 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1352 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1353 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1354 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1355 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1356 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1357 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1358 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1359 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1360 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1361 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1362 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1363 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1364 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1365 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1366 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1367 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1368 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1369 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1370 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1371 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1372 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1373 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1374 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1375 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1376 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1377 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1378 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1379 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1380 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1381 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1382 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1383 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1384 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1385 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1386 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1387 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1388 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1389 { X86::VPORrr, X86::VPORrm, 0 },
1390 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1391 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1392 { X86::VPSIGNBrr128, X86::VPSIGNBrm128, 0 },
1393 { X86::VPSIGNWrr128, X86::VPSIGNWrm128, 0 },
1394 { X86::VPSIGNDrr128, X86::VPSIGNDrm128, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1395 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1396 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1397 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1398 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1399 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1400 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1401 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1402 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1403 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1404 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1405 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1406 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1407 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1408 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1409 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1410 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1411 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1412 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1413 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1414 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1415 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1416 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1417 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1418 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1419 { X86::VPXORrr, X86::VPXORrm, 0 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1420 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1421 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1422 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1423 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1424 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1425 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1426 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1427 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1428 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1429 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1430 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1431 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1432 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1433 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1434 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1435 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1436
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1437 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1438 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1439 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1440 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1441 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1442 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1443 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1444 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1445 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1446 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1447 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1448 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1449 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1450 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1451 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1452 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1453 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1454 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1455 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1456 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1457 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1458 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1459 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1460 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1461 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1462 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1463 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1464 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1465 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1466 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1467 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1468 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1469 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1470 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1471 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1472 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1473 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1474 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1475 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1476 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1477 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1478 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1479 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1480 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1481
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1482 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1483 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1484 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1485 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1486 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1487 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1488 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1489 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1490 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1491 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1492 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1493 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1494 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1495 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
Craig Topper7a299302016-06-09 07:06:38 +0000[diff] [blame]1496 { X86::VPALIGNRYrri, X86::VPALIGNRYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1497 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1498 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1499 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1500 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1501 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1502 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1503 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1504 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1505 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1506 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1507 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1508 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1509 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1510 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1511 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1512 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1513 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1514 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1515 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1516 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1517 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1518 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1519 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1520 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1521 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1522 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1523 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1524 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1525 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1526 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1527 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1528 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1529 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1530 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1531 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1532 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1533 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1534 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1535 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1536 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1537 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1538 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1539 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1540 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1541 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1542 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1543 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1544 { X86::VPORYrr, X86::VPORYrm, 0 },
1545 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1546 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
Ahmed Bougachaf3cccab2016-02-16 22:14:12 +0000[diff] [blame]1547 { X86::VPSIGNBYrr256, X86::VPSIGNBYrm256, 0 },
1548 { X86::VPSIGNWYrr256, X86::VPSIGNWYrm256, 0 },
1549 { X86::VPSIGNDYrr256, X86::VPSIGNDYrm256, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1550 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1551 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1552 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1553 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1554 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1555 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1556 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1557 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1558 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1559 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1560 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
Igor Bregere59165c2016-06-20 07:05:43 +0000[diff] [blame]1561 { X86::VPSRAVD_Intrr, X86::VPSRAVD_Intrm, 0 },
1562 { X86::VPSRAVD_IntYrr, X86::VPSRAVD_IntYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1563 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1564 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1565 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1566 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1567 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1568 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1569 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1570 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1571 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1572 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1573 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1574 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1575 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1576 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1577 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1578 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1579 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1580 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1581 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1582 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1583 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1584 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1585 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1586 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1587
1588 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1589 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE },
1590 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE },
1591 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE },
1592 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE },
1593 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_NONE },
1594 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_NONE },
1595 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE },
1596 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE },
1597 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE },
1598 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE },
1599 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_NONE },
1600 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_NONE },
1601 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE },
1602 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE },
1603 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE },
1604 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE },
1605 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_NONE },
1606 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_NONE },
1607 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE },
1608 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE },
1609 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE },
1610 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE },
1611 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_NONE },
1612 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_NONE },
1613 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE },
1614 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE },
1615 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_NONE },
1616 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_NONE },
1617 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE },
1618 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE },
1619 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_NONE },
1620 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_NONE },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1621
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1622 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1623 { X86::VPCMOVrrr, X86::VPCMOVrmr, 0 },
1624 { X86::VPCMOVrrrY, X86::VPCMOVrmrY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1625 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1626 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1627 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1628 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1629 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1630 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1631 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1632 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1633 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1634 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1635 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1636 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1637 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1638 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1639 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1640 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1641 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1642 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1643 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1644 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1645 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1646 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1647 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1648 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1649 { X86::VPPERMrrr, X86::VPPERMrmr, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1650 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1651 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1652 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1653 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1654 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1655 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1656 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1657 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1658 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1659 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1660 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1661 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1662
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1663 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1664 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1665 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1666 { X86::MULX32rr, X86::MULX32rm, 0 },
1667 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1668 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1669 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1670 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1671 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1672
Simon Pilgrim4ba59692015-12-05 07:27:50 +0000[diff] [blame]1673 // ADX foldable instructions
1674 { X86::ADCX32rr, X86::ADCX32rm, 0 },
1675 { X86::ADCX64rr, X86::ADCX64rm, 0 },
1676 { X86::ADOX32rr, X86::ADOX32rm, 0 },
1677 { X86::ADOX64rr, X86::ADOX64rm, 0 },
1678
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1679 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1680 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1681 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1682 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1683 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1684 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1685 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1686 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1687 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1688 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1689 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1690 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1691 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1692 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1693 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1694 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1695 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1696 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1697 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1698 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1699 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1700 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1701 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1702 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1703 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1704 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1705 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1706 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1707 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1708 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1709 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1710 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1711 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1712 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1713 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
Igor Breger00d9f842015-06-08 14:03:17 +0000[diff] [blame]1714 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1715 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1716 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1717 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1718 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1719
1720 // AVX-512{F,VL} foldable instructions
1721 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1722 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1723 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1724
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1725 // AVX-512{F,VL} foldable instructions
1726 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1727 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1728 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1729 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1730
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1731 // AES foldable instructions
1732 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1733 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1734 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1735 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1736 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1737 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1738 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1739 { X86::VAESENCrr, X86::VAESENCrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1740
1741 // SHA foldable instructions
1742 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1743 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1744 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1745 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1746 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1747 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1748 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1749 };
1750
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1751 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1752 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1753 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1754 // Index 2, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1755 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1756 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1757
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1758 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1759 // FMA foldable instructions
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1760 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1761 { X86::VFMADDSSr231r_Int, X86::VFMADDSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1762 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1763 { X86::VFMADDSDr231r_Int, X86::VFMADDSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1764 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1765 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1766 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1767 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1768 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1769 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1770 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1771 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1772
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1773 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1774 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1775 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1776 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1777 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1778 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1779 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1780 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1781 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1782 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1783 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1784 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1785
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1786 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1787 { X86::VFNMADDSSr231r_Int, X86::VFNMADDSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1788 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1789 { X86::VFNMADDSDr231r_Int, X86::VFNMADDSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1790 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1791 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1792 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1793 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1794 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1795 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1796 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1797 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1798
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1799 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1800 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1801 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1802 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1803 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1804 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1805 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1806 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1807 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1808 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1809 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1810 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1811
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1812 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1813 { X86::VFMSUBSSr231r_Int, X86::VFMSUBSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1814 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1815 { X86::VFMSUBSDr231r_Int, X86::VFMSUBSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1816 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1817 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1818 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1819 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1820 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1821 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1822 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1823 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1824
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1825 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1826 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1827 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1828 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1829 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1830 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1831 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1832 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1833 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1834 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1835 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1836 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1837
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1838 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1839 { X86::VFNMSUBSSr231r_Int, X86::VFNMSUBSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1840 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1841 { X86::VFNMSUBSDr231r_Int, X86::VFNMSUBSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1842 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1843 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1844 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1845 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1846 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1847 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1848 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1849 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, TB_ALIGN_NONE },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1850
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1851 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1852 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1853 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1854 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1855 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1856 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1857 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1858 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1859 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1860 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1861 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1862 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1863
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1864 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1865 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1866 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1867 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1868 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1869 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1870 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1871 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1872 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1873 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1874 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1875 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1876
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1877 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1878 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1879 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1880 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1881 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1882 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1883 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1884 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1885 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1886 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1887 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1888 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1889
1890 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1891 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE },
1892 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE },
1893 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE },
1894 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE },
1895 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_NONE },
1896 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_NONE },
1897 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE },
1898 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE },
1899 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE },
1900 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE },
1901 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_NONE },
1902 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_NONE },
1903 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE },
1904 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE },
1905 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE },
1906 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE },
1907 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_NONE },
1908 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_NONE },
1909 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE },
1910 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE },
1911 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE },
1912 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE },
1913 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_NONE },
1914 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_NONE },
1915 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE },
1916 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE },
1917 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_NONE },
1918 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_NONE },
1919 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE },
1920 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE },
1921 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_NONE },
1922 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_NONE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1923
1924 // XOP foldable instructions
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1925 { X86::VPCMOVrrr, X86::VPCMOVrrm, 0 },
1926 { X86::VPCMOVrrrY, X86::VPCMOVrrmY, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1927 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1928 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1929 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1930 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
Simon Pilgrima6ba27f2016-03-24 16:31:30 +0000[diff] [blame]1931 { X86::VPPERMrrr, X86::VPPERMrrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1932
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]1933 // AVX-512 VPERMI instructions with 3 source operands.
1934 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1935 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1936 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1937 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1938 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1939 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1940 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1941 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1942 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1943 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1944 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1945 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1946 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1947 // AVX-512 arithmetic instructions
1948 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1949 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1950 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1951 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1952 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1953 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1954 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1955 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1956 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1957 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1958 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1959 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1960 // AVX-512{F,VL} arithmetic instructions 256-bit
1961 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1962 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1963 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1964 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1965 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1966 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1967 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1968 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1969 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1970 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1971 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1972 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1973 // AVX-512{F,VL} arithmetic instructions 128-bit
1974 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1975 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1976 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1977 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1978 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1979 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1980 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1981 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1982 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1983 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1984 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1985 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1986 };
1987
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1988 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1989 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1990 Entry.RegOp, Entry.MemOp,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1991 // Index 3, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1992 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1993 }
1994
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1995 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1996 // AVX-512 foldable instructions
1997 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1998 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
1999 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
2000 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
2001 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
2002 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
2003 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
2004 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
2005 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
2006 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
2007 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
2008 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
2009 // AVX-512{F,VL} foldable instructions 256-bit
2010 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
2011 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
2012 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
2013 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
2014 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
2015 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
2016 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
2017 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
2018 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
2019 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
2020 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
2021 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
2022 // AVX-512{F,VL} foldable instructions 128-bit
2023 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
2024 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
2025 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
2026 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
2027 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
2028 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
2029 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
2030 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
2031 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
2032 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
2033 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
2034 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
2035 };
2036
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2037 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2038 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2039 Entry.RegOp, Entry.MemOp,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2040 // Index 4, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2041 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2042 }
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]2043}
2044
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2045void
2046X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2047 MemOp2RegOpTableType &M2RTable,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]2048 uint16_t RegOp, uint16_t MemOp, uint16_t Flags) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2049 if ((Flags & TB_NO_FORWARD) == 0) {
2050 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2051 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2052 }
2053 if ((Flags & TB_NO_REVERSE) == 0) {
2054 assert(!M2RTable.count(MemOp) &&
2055 "Duplicated entries in unfolding maps?");
2056 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2057 }
2058}
2059
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2060bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2061X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2062 unsigned &SrcReg, unsigned &DstReg,
2063 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2064 switch (MI.getOpcode()) {
2065 default: break;
2066 case X86::MOVSX16rr8:
2067 case X86::MOVZX16rr8:
2068 case X86::MOVSX32rr8:
2069 case X86::MOVZX32rr8:
2070 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2071 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]2072 // It's not always legal to reference the low 8-bit of the larger
2073 // register in 32-bit mode.
2074 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2075 case X86::MOVSX32rr16:
2076 case X86::MOVZX32rr16:
2077 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]2078 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2079 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2080 // Be conservative.
2081 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2082 SrcReg = MI.getOperand(1).getReg();
2083 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2084 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2085 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2086 case X86::MOVSX16rr8:
2087 case X86::MOVZX16rr8:
2088 case X86::MOVSX32rr8:
2089 case X86::MOVZX32rr8:
2090 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2091 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2092 break;
2093 case X86::MOVSX32rr16:
2094 case X86::MOVZX32rr16:
2095 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2096 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2097 break;
2098 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2099 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2100 break;
2101 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2102 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2103 }
2104 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2105 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2106}
2107
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2108int X86InstrInfo::getSPAdjust(const MachineInstr &MI) const {
2109 const MachineFunction *MF = MI.getParent()->getParent();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2110 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2111
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2112 if (MI.getOpcode() == getCallFrameSetupOpcode() ||
2113 MI.getOpcode() == getCallFrameDestroyOpcode()) {
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2114 unsigned StackAlign = TFI->getStackAlignment();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2115 int SPAdj =
2116 (MI.getOperand(0).getImm() + StackAlign - 1) / StackAlign * StackAlign;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2117
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2118 SPAdj -= MI.getOperand(1).getImm();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2119
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2120 if (MI.getOpcode() == getCallFrameSetupOpcode())
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2121 return SPAdj;
2122 else
2123 return -SPAdj;
2124 }
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2125
2126 // To know whether a call adjusts the stack, we need information
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2127 // that is bound to the following ADJCALLSTACKUP pseudo.
2128 // Look for the next ADJCALLSTACKUP that follows the call.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2129 if (MI.isCall()) {
2130 const MachineBasicBlock *MBB = MI.getParent();
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2131 auto I = ++MachineBasicBlock::const_iterator(MI);
2132 for (auto E = MBB->end(); I != E; ++I) {
2133 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2134 I->isCall())
2135 break;
2136 }
2137
2138 // If we could not find a frame destroy opcode, then it has already
2139 // been simplified, so we don't care.
2140 if (I->getOpcode() != getCallFrameDestroyOpcode())
2141 return 0;
2142
2143 return -(I->getOperand(1).getImm());
2144 }
2145
2146 // Currently handle only PUSHes we can reasonably expect to see
2147 // in call sequences
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2148 switch (MI.getOpcode()) {
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2149 default:
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2150 return 0;
2151 case X86::PUSH32i8:
2152 case X86::PUSH32r:
2153 case X86::PUSH32rmm:
2154 case X86::PUSH32rmr:
2155 case X86::PUSHi32:
2156 return 4;
David L Kreitzer0fe46322016-05-02 13:45:25 +0000[diff] [blame]2157 case X86::PUSH64i8:
2158 case X86::PUSH64r:
2159 case X86::PUSH64rmm:
2160 case X86::PUSH64rmr:
2161 case X86::PUSH64i32:
2162 return 8;
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2163 }
2164}
2165
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2166/// Return true and the FrameIndex if the specified
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2167/// operand and follow operands form a reference to the stack frame.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2168bool X86InstrInfo::isFrameOperand(const MachineInstr &MI, unsigned int Op,
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2169 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2170 if (MI.getOperand(Op + X86::AddrBaseReg).isFI() &&
2171 MI.getOperand(Op + X86::AddrScaleAmt).isImm() &&
2172 MI.getOperand(Op + X86::AddrIndexReg).isReg() &&
2173 MI.getOperand(Op + X86::AddrDisp).isImm() &&
2174 MI.getOperand(Op + X86::AddrScaleAmt).getImm() == 1 &&
2175 MI.getOperand(Op + X86::AddrIndexReg).getReg() == 0 &&
2176 MI.getOperand(Op + X86::AddrDisp).getImm() == 0) {
2177 FrameIndex = MI.getOperand(Op + X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2178 return true;
2179 }
2180 return false;
2181}
2182
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2183static bool isFrameLoadOpcode(int Opcode) {
2184 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]2185 default:
2186 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2187 case X86::MOV8rm:
2188 case X86::MOV16rm:
2189 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]2190 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]2191 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2192 case X86::MOVSSrm:
2193 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2194 case X86::MOVAPSrm:
2195 case X86::MOVAPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]2196 case X86::MOVDQArm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2197 case X86::VMOVSSrm:
2198 case X86::VMOVSDrm:
2199 case X86::VMOVAPSrm:
2200 case X86::VMOVAPDrm:
2201 case X86::VMOVDQArm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2202 case X86::VMOVUPSYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2203 case X86::VMOVAPSYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2204 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2205 case X86::VMOVAPDYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2206 case X86::VMOVDQUYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2207 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]2208 case X86::MMX_MOVD64rm:
2209 case X86::MMX_MOVQ64rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2210 case X86::VMOVAPSZrm:
2211 case X86::VMOVUPSZrm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2212 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2213 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2214}
2215
2216static bool isFrameStoreOpcode(int Opcode) {
2217 switch (Opcode) {
2218 default: break;
2219 case X86::MOV8mr:
2220 case X86::MOV16mr:
2221 case X86::MOV32mr:
2222 case X86::MOV64mr:
2223 case X86::ST_FpP64m:
2224 case X86::MOVSSmr:
2225 case X86::MOVSDmr:
2226 case X86::MOVAPSmr:
2227 case X86::MOVAPDmr:
2228 case X86::MOVDQAmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2229 case X86::VMOVSSmr:
2230 case X86::VMOVSDmr:
2231 case X86::VMOVAPSmr:
2232 case X86::VMOVAPDmr:
2233 case X86::VMOVDQAmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2234 case X86::VMOVUPSYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2235 case X86::VMOVAPSYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2236 case X86::VMOVUPDYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2237 case X86::VMOVAPDYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2238 case X86::VMOVDQUYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2239 case X86::VMOVDQAYmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2240 case X86::VMOVUPSZmr:
2241 case X86::VMOVAPSZmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2242 case X86::MMX_MOVD64mr:
2243 case X86::MMX_MOVQ64mr:
2244 case X86::MMX_MOVNTQmr:
2245 return true;
2246 }
2247 return false;
2248}
2249
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2250unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2251 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2252 if (isFrameLoadOpcode(MI.getOpcode()))
2253 if (MI.getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
2254 return MI.getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2255 return 0;
2256}
2257
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2258unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2259 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2260 if (isFrameLoadOpcode(MI.getOpcode())) {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2261 unsigned Reg;
2262 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2263 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2264 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2265 const MachineMemOperand *Dummy;
2266 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2267 }
2268 return 0;
2269}
2270
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2271unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr &MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2272 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2273 if (isFrameStoreOpcode(MI.getOpcode()))
2274 if (MI.getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2275 isFrameOperand(MI, 0, FrameIndex))
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2276 return MI.getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2277 return 0;
2278}
2279
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2280unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr &MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2281 int &FrameIndex) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2282 if (isFrameStoreOpcode(MI.getOpcode())) {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2283 unsigned Reg;
2284 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2285 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2286 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2287 const MachineMemOperand *Dummy;
2288 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2289 }
2290 return 0;
2291}
2292
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2293/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2294static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]2295 // Don't waste compile time scanning use-def chains of physregs.
2296 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2297 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2298 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]2299 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2300 E = MRI.def_instr_end(); I != E; ++I) {
2301 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2302 if (DefMI->getOpcode() != X86::MOVPC32r)
2303 return false;
2304 assert(!isPICBase && "More than one PIC base?");
2305 isPICBase = true;
2306 }
2307 return isPICBase;
2308}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]2309
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2310bool X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr &MI,
2311 AliasAnalysis *AA) const {
2312 switch (MI.getOpcode()) {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2313 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2314 case X86::MOV8rm:
2315 case X86::MOV16rm:
2316 case X86::MOV32rm:
2317 case X86::MOV64rm:
2318 case X86::LD_Fp64m:
2319 case X86::MOVSSrm:
2320 case X86::MOVSDrm:
2321 case X86::MOVAPSrm:
2322 case X86::MOVUPSrm:
2323 case X86::MOVAPDrm:
2324 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2325 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2326 case X86::VMOVSSrm:
2327 case X86::VMOVSDrm:
2328 case X86::VMOVAPSrm:
2329 case X86::VMOVUPSrm:
2330 case X86::VMOVAPDrm:
2331 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2332 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2333 case X86::VMOVAPSYrm:
2334 case X86::VMOVUPSYrm:
2335 case X86::VMOVAPDYrm:
2336 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2337 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2338 case X86::MMX_MOVD64rm:
2339 case X86::MMX_MOVQ64rm:
2340 case X86::FsVMOVAPSrm:
2341 case X86::FsVMOVAPDrm:
2342 case X86::FsMOVAPSrm:
Igor Bregerf8e461f2015-10-26 08:37:12 +0000[diff] [blame]2343 case X86::FsMOVAPDrm:
2344 // AVX-512
2345 case X86::VMOVAPDZ128rm:
2346 case X86::VMOVAPDZ256rm:
2347 case X86::VMOVAPDZrm:
2348 case X86::VMOVAPSZ128rm:
2349 case X86::VMOVAPSZ256rm:
2350 case X86::VMOVAPSZrm:
2351 case X86::VMOVDQA32Z128rm:
2352 case X86::VMOVDQA32Z256rm:
2353 case X86::VMOVDQA32Zrm:
2354 case X86::VMOVDQA64Z128rm:
2355 case X86::VMOVDQA64Z256rm:
2356 case X86::VMOVDQA64Zrm:
2357 case X86::VMOVDQU16Z128rm:
2358 case X86::VMOVDQU16Z256rm:
2359 case X86::VMOVDQU16Zrm:
2360 case X86::VMOVDQU32Z128rm:
2361 case X86::VMOVDQU32Z256rm:
2362 case X86::VMOVDQU32Zrm:
2363 case X86::VMOVDQU64Z128rm:
2364 case X86::VMOVDQU64Z256rm:
2365 case X86::VMOVDQU64Zrm:
2366 case X86::VMOVDQU8Z128rm:
2367 case X86::VMOVDQU8Z256rm:
2368 case X86::VMOVDQU8Zrm:
2369 case X86::VMOVUPSZ128rm:
2370 case X86::VMOVUPSZ256rm:
2371 case X86::VMOVUPSZrm: {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2372 // Loads from constant pools are trivially rematerializable.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2373 if (MI.getOperand(1 + X86::AddrBaseReg).isReg() &&
2374 MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2375 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2376 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2377 MI.isInvariantLoad(AA)) {
2378 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2379 if (BaseReg == 0 || BaseReg == X86::RIP)
2380 return true;
2381 // Allow re-materialization of PIC load.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2382 if (!ReMatPICStubLoad && MI.getOperand(1 + X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2383 return false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2384 const MachineFunction &MF = *MI.getParent()->getParent();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2385 const MachineRegisterInfo &MRI = MF.getRegInfo();
2386 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]2387 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2388 return false;
2389 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2390
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2391 case X86::LEA32r:
2392 case X86::LEA64r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2393 if (MI.getOperand(1 + X86::AddrScaleAmt).isImm() &&
2394 MI.getOperand(1 + X86::AddrIndexReg).isReg() &&
2395 MI.getOperand(1 + X86::AddrIndexReg).getReg() == 0 &&
2396 !MI.getOperand(1 + X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2397 // lea fi#, lea GV, etc. are all rematerializable.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2398 if (!MI.getOperand(1 + X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2399 return true;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2400 unsigned BaseReg = MI.getOperand(1 + X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2401 if (BaseReg == 0)
2402 return true;
2403 // Allow re-materialization of lea PICBase + x.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2404 const MachineFunction &MF = *MI.getParent()->getParent();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2405 const MachineRegisterInfo &MRI = MF.getRegInfo();
2406 return regIsPICBase(BaseReg, MRI);
2407 }
2408 return false;
2409 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2410 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]2411
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]2412 // All other instructions marked M_REMATERIALIZABLE are always trivially
2413 // rematerializable.
2414 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2415}
2416
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]2417bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2418 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2419 MachineBasicBlock::iterator E = MBB.end();
2420
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2421 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2422 // safety after visiting 4 instructions in each direction, we will assume
2423 // it's not safe.
2424 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2425 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2426 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2427 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2428 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2429 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2430 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2431 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2432 continue;
2433 if (MO.getReg() == X86::EFLAGS) {
2434 if (MO.isUse())
2435 return false;
2436 SeenDef = true;
2437 }
2438 }
2439
2440 if (SeenDef)
2441 // This instruction defines EFLAGS, no need to look any further.
2442 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2443 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2444 // Skip over DBG_VALUE.
2445 while (Iter != E && Iter->isDebugValue())
2446 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2447 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2448
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2449 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2450 // live in.
2451 if (Iter == E) {
Craig Topperca66fc52015-12-20 18:41:57 +0000[diff] [blame]2452 for (MachineBasicBlock *S : MBB.successors())
2453 if (S->isLiveIn(X86::EFLAGS))
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2454 return false;
2455 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2456 }
2457
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2458 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2459 Iter = I;
2460 for (unsigned i = 0; i < 4; ++i) {
2461 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]2462 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2463 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2464 return !MBB.isLiveIn(X86::EFLAGS);
2465
2466 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2467 // Skip over DBG_VALUE.
2468 while (Iter != B && Iter->isDebugValue())
2469 --Iter;
2470
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2471 bool SawKill = false;
2472 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2473 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2474 // A register mask may clobber EFLAGS, but we should still look for a
2475 // live EFLAGS def.
2476 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2477 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2478 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2479 if (MO.isDef()) return MO.isDead();
2480 if (MO.isKill()) SawKill = true;
2481 }
2482 }
2483
2484 if (SawKill)
2485 // This instruction kills EFLAGS and doesn't redefine it, so
2486 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2487 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2488 }
2489
2490 // Conservative answer.
2491 return false;
2492}
2493
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2494void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2495 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2496 unsigned DestReg, unsigned SubIdx,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2497 const MachineInstr &Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2498 const TargetRegisterInfo &TRI) const {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2499 bool ClobbersEFLAGS = false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2500 for (const MachineOperand &MO : Orig.operands()) {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2501 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2502 ClobbersEFLAGS = true;
2503 break;
2504 }
2505 }
2506
2507 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2508 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2509 // effects.
2510 int Value;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2511 switch (Orig.getOpcode()) {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2512 case X86::MOV32r0: Value = 0; break;
2513 case X86::MOV32r1: Value = 1; break;
2514 case X86::MOV32r_1: Value = -1; break;
2515 default:
2516 llvm_unreachable("Unexpected instruction!");
2517 }
2518
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2519 const DebugLoc &DL = Orig.getDebugLoc();
2520 BuildMI(MBB, I, DL, get(X86::MOV32ri))
2521 .addOperand(Orig.getOperand(0))
2522 .addImm(Value);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2523 } else {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2524 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(&Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2525 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2526 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]2527
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2528 MachineInstr *NewMI = std::prev(I);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2529 NewMI->substituteRegister(Orig.getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2530}
2531
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2532/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2533bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr &MI) const {
2534 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
2535 MachineOperand &MO = MI.getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2536 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2537 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2538 return true;
2539 }
2540 }
2541 return false;
2542}
2543
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2544/// Check whether the shift count for a machine operand is non-zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2545inline static unsigned getTruncatedShiftCount(MachineInstr &MI,
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2546 unsigned ShiftAmtOperandIdx) {
2547 // The shift count is six bits with the REX.W prefix and five bits without.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2548 unsigned ShiftCountMask = (MI.getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2549 unsigned Imm = MI.getOperand(ShiftAmtOperandIdx).getImm();
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2550 return Imm & ShiftCountMask;
2551}
2552
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2553/// Check whether the given shift count is appropriate
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2554/// can be represented by a LEA instruction.
2555inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2556 // Left shift instructions can be transformed into load-effective-address
2557 // instructions if we can encode them appropriately.
Sanjay Pateldc87d142015-08-12 15:09:09 +0000[diff] [blame]2558 // A LEA instruction utilizes a SIB byte to encode its scale factor.
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2559 // The SIB.scale field is two bits wide which means that we can encode any
2560 // shift amount less than 4.
2561 return ShAmt < 4 && ShAmt > 0;
2562}
2563
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2564bool X86InstrInfo::classifyLEAReg(MachineInstr &MI, const MachineOperand &Src,
2565 unsigned Opc, bool AllowSP, unsigned &NewSrc,
2566 bool &isKill, bool &isUndef,
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2567 MachineOperand &ImplicitOp) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2568 MachineFunction &MF = *MI.getParent()->getParent();
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2569 const TargetRegisterClass *RC;
2570 if (AllowSP) {
2571 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2572 } else {
2573 RC = Opc != X86::LEA32r ?
2574 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2575 }
2576 unsigned SrcReg = Src.getReg();
2577
2578 // For both LEA64 and LEA32 the register already has essentially the right
2579 // type (32-bit or 64-bit) we may just need to forbid SP.
2580 if (Opc != X86::LEA64_32r) {
2581 NewSrc = SrcReg;
2582 isKill = Src.isKill();
2583 isUndef = Src.isUndef();
2584
2585 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2586 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2587 return false;
2588
2589 return true;
2590 }
2591
2592 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2593 // another we need to add 64-bit registers to the final MI.
2594 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2595 ImplicitOp = Src;
2596 ImplicitOp.setImplicit();
2597
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]2598 NewSrc = getX86SubSuperRegister(Src.getReg(), 64);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2599 MachineBasicBlock::LivenessQueryResult LQR =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2600 MI.getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2601
2602 switch (LQR) {
2603 case MachineBasicBlock::LQR_Unknown:
2604 // We can't give sane liveness flags to the instruction, abandon LEA
2605 // formation.
2606 return false;
2607 case MachineBasicBlock::LQR_Live:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2608 isKill = MI.killsRegister(SrcReg);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2609 isUndef = false;
2610 break;
2611 default:
2612 // The physreg itself is dead, so we have to use it as an <undef>.
2613 isKill = false;
2614 isUndef = true;
2615 break;
2616 }
2617 } else {
2618 // Virtual register of the wrong class, we have to create a temporary 64-bit
2619 // vreg to feed into the LEA.
2620 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2621 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2622 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2623 .addOperand(Src);
2624
2625 // Which is obviously going to be dead after we're done with it.
2626 isKill = true;
2627 isUndef = false;
2628 }
2629
2630 // We've set all the parameters without issue.
2631 return true;
2632}
2633
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2634/// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2635/// LEA to form 3-address code by promoting to a 32-bit superregister and then
2636/// truncating back down to a 16-bit subregister.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2637MachineInstr *X86InstrInfo::convertToThreeAddressWithLEA(
2638 unsigned MIOpc, MachineFunction::iterator &MFI, MachineInstr &MI,
2639 LiveVariables *LV) const {
2640 MachineBasicBlock::iterator MBBI = MI.getIterator();
2641 unsigned Dest = MI.getOperand(0).getReg();
2642 unsigned Src = MI.getOperand(1).getReg();
2643 bool isDead = MI.getOperand(0).isDead();
2644 bool isKill = MI.getOperand(1).isKill();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2645
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2646 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2647 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2648 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2649 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2650 Opc = X86::LEA64_32r;
2651 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2652 } else {
2653 Opc = X86::LEA32r;
2654 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2655 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2656
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2657 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2658 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2659 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2660 // movw (%rbp,%rcx,2), %dx
2661 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2662 // But testing has shown this *does* help performance in 64-bit mode (at
2663 // least on modern x86 machines).
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2664 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2665 MachineInstr *InsMI =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2666 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2667 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2668 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2669
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2670 MachineInstrBuilder MIB =
2671 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(Opc), leaOutReg);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2672 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2673 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2674 case X86::SHL16ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2675 unsigned ShAmt = MI.getOperand(2).getImm();
Aaron Ballmanef0fe1e2016-03-30 21:30:00 +0000[diff] [blame]2676 MIB.addReg(0).addImm(1ULL << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2677 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2678 break;
2679 }
2680 case X86::INC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2681 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2682 break;
2683 case X86::DEC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2684 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2685 break;
2686 case X86::ADD16ri:
2687 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2688 case X86::ADD16ri_DB:
2689 case X86::ADD16ri8_DB:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2690 addRegOffset(MIB, leaInReg, true, MI.getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2691 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2692 case X86::ADD16rr:
2693 case X86::ADD16rr_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2694 unsigned Src2 = MI.getOperand(2).getReg();
2695 bool isKill2 = MI.getOperand(2).isKill();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2696 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2697 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2698 if (Src == Src2) {
2699 // ADD16rr %reg1028<kill>, %reg1028
2700 // just a single insert_subreg.
2701 addRegReg(MIB, leaInReg, true, leaInReg, false);
2702 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2703 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2704 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2705 else
2706 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2707 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2708 // well be shifting and then extracting the lower 16-bits.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2709 BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg2);
2710 InsMI2 = BuildMI(*MFI, &*MIB, MI.getDebugLoc(), get(TargetOpcode::COPY))
2711 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2712 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2713 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2714 }
2715 if (LV && isKill2 && InsMI2)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2716 LV->replaceKillInstruction(Src2, MI, *InsMI2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2717 break;
2718 }
2719 }
2720
2721 MachineInstr *NewMI = MIB;
2722 MachineInstr *ExtMI =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2723 BuildMI(*MFI, MBBI, MI.getDebugLoc(), get(TargetOpcode::COPY))
2724 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
2725 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2726
2727 if (LV) {
2728 // Update live variables
2729 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2730 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2731 if (isKill)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2732 LV->replaceKillInstruction(Src, MI, *InsMI);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2733 if (isDead)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2734 LV->replaceKillInstruction(Dest, MI, *ExtMI);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2735 }
2736
2737 return ExtMI;
2738}
2739
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2740/// This method must be implemented by targets that
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2741/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2742/// may be able to convert a two-address instruction into a true
2743/// three-address instruction on demand. This allows the X86 target (for
2744/// example) to convert ADD and SHL instructions into LEA instructions if they
2745/// would require register copies due to two-addressness.
2746///
2747/// This method returns a null pointer if the transformation cannot be
2748/// performed, otherwise it returns the new instruction.
2749///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2750MachineInstr *
2751X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2752 MachineInstr &MI, LiveVariables *LV) const {
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2753 // The following opcodes also sets the condition code register(s). Only
2754 // convert them to equivalent lea if the condition code register def's
2755 // are dead!
2756 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2757 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2758
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2759 MachineFunction &MF = *MI.getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2760 // All instructions input are two-addr instructions. Get the known operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2761 const MachineOperand &Dest = MI.getOperand(0);
2762 const MachineOperand &Src = MI.getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2763
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2764 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2765 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2766 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2767 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2768 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2769 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2770
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2771 unsigned MIOpc = MI.getOpcode();
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2772 switch (MIOpc) {
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2773 default: return nullptr;
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2774 case X86::SHL64ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2775 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2776 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2777 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2778
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2779 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2780 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2781 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2782 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2783 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2784
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2785 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
2786 .addOperand(Dest)
2787 .addReg(0)
2788 .addImm(1ULL << ShAmt)
2789 .addOperand(Src)
2790 .addImm(0)
2791 .addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2792 break;
2793 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2794 case X86::SHL32ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2795 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2796 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2797 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2798
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2799 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2800
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2801 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2802 bool isKill, isUndef;
2803 unsigned SrcReg;
2804 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2805 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2806 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2807 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2808
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2809 MachineInstrBuilder MIB =
2810 BuildMI(MF, MI.getDebugLoc(), get(Opc))
2811 .addOperand(Dest)
2812 .addReg(0)
2813 .addImm(1ULL << ShAmt)
2814 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2815 .addImm(0)
2816 .addReg(0);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2817 if (ImplicitOp.getReg() != 0)
2818 MIB.addOperand(ImplicitOp);
2819 NewMI = MIB;
2820
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2821 break;
2822 }
2823 case X86::SHL16ri: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2824 assert(MI.getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2825 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2826 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2827
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2828 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2829 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
2830 : nullptr;
2831 NewMI = BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2832 .addOperand(Dest)
2833 .addReg(0)
2834 .addImm(1ULL << ShAmt)
2835 .addOperand(Src)
2836 .addImm(0)
2837 .addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2838 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2839 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2840 case X86::INC64r:
2841 case X86::INC32r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2842 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2843 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2844 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2845 bool isKill, isUndef;
2846 unsigned SrcReg;
2847 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2848 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2849 SrcReg, isKill, isUndef, ImplicitOp))
2850 return nullptr;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2851
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2852 MachineInstrBuilder MIB =
2853 BuildMI(MF, MI.getDebugLoc(), get(Opc))
2854 .addOperand(Dest)
2855 .addReg(SrcReg,
2856 getKillRegState(isKill) | getUndefRegState(isUndef));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2857 if (ImplicitOp.getReg() != 0)
2858 MIB.addOperand(ImplicitOp);
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2859
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2860 NewMI = addOffset(MIB, 1);
2861 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2862 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2863 case X86::INC16r:
2864 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2865 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2866 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2867 assert(MI.getNumOperands() >= 2 && "Unknown inc instruction!");
2868 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2869 .addOperand(Dest)
2870 .addOperand(Src),
2871 1);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2872 break;
2873 case X86::DEC64r:
2874 case X86::DEC32r: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2875 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2876 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2877 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2878
2879 bool isKill, isUndef;
2880 unsigned SrcReg;
2881 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2882 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2883 SrcReg, isKill, isUndef, ImplicitOp))
2884 return nullptr;
2885
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2886 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
2887 .addOperand(Dest)
2888 .addReg(SrcReg, getUndefRegState(isUndef) |
2889 getKillRegState(isKill));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2890 if (ImplicitOp.getReg() != 0)
2891 MIB.addOperand(ImplicitOp);
2892
2893 NewMI = addOffset(MIB, -1);
2894
2895 break;
2896 }
2897 case X86::DEC16r:
2898 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2899 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2900 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2901 assert(MI.getNumOperands() >= 2 && "Unknown dec instruction!");
2902 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
2903 .addOperand(Dest)
2904 .addOperand(Src),
2905 -1);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2906 break;
2907 case X86::ADD64rr:
2908 case X86::ADD64rr_DB:
2909 case X86::ADD32rr:
2910 case X86::ADD32rr_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2911 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2912 unsigned Opc;
2913 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2914 Opc = X86::LEA64r;
2915 else
2916 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2917
2918 bool isKill, isUndef;
2919 unsigned SrcReg;
2920 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2921 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2922 SrcReg, isKill, isUndef, ImplicitOp))
2923 return nullptr;
2924
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2925 const MachineOperand &Src2 = MI.getOperand(2);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2926 bool isKill2, isUndef2;
2927 unsigned SrcReg2;
2928 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2929 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2930 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2931 return nullptr;
2932
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2933 MachineInstrBuilder MIB =
2934 BuildMI(MF, MI.getDebugLoc(), get(Opc)).addOperand(Dest);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2935 if (ImplicitOp.getReg() != 0)
2936 MIB.addOperand(ImplicitOp);
2937 if (ImplicitOp2.getReg() != 0)
2938 MIB.addOperand(ImplicitOp2);
2939
2940 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2941
2942 // Preserve undefness of the operands.
2943 NewMI->getOperand(1).setIsUndef(isUndef);
2944 NewMI->getOperand(3).setIsUndef(isUndef2);
2945
2946 if (LV && Src2.isKill())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2947 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2948 break;
2949 }
2950 case X86::ADD16rr:
2951 case X86::ADD16rr_DB: {
2952 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2953 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2954 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2955 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
2956 unsigned Src2 = MI.getOperand(2).getReg();
2957 bool isKill2 = MI.getOperand(2).isKill();
2958 NewMI = addRegReg(
2959 BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r)).addOperand(Dest),
2960 Src.getReg(), Src.isKill(), Src2, isKill2);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2961
2962 // Preserve undefness of the operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2963 bool isUndef = MI.getOperand(1).isUndef();
2964 bool isUndef2 = MI.getOperand(2).isUndef();
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2965 NewMI->getOperand(1).setIsUndef(isUndef);
2966 NewMI->getOperand(3).setIsUndef(isUndef2);
2967
2968 if (LV && isKill2)
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]2969 LV->replaceKillInstruction(Src2, MI, *NewMI);
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2970 break;
2971 }
2972 case X86::ADD64ri32:
2973 case X86::ADD64ri8:
2974 case X86::ADD64ri32_DB:
2975 case X86::ADD64ri8_DB:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2976 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
2977 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA64r))
2978 .addOperand(Dest)
2979 .addOperand(Src),
2980 MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2981 break;
2982 case X86::ADD32ri:
2983 case X86::ADD32ri8:
2984 case X86::ADD32ri_DB:
2985 case X86::ADD32ri8_DB: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2986 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2987 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2988
2989 bool isKill, isUndef;
2990 unsigned SrcReg;
2991 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2992 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2993 SrcReg, isKill, isUndef, ImplicitOp))
2994 return nullptr;
2995
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]2996 MachineInstrBuilder MIB = BuildMI(MF, MI.getDebugLoc(), get(Opc))
2997 .addOperand(Dest)
2998 .addReg(SrcReg, getUndefRegState(isUndef) |
2999 getKillRegState(isKill));
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3000 if (ImplicitOp.getReg() != 0)
3001 MIB.addOperand(ImplicitOp);
3002
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3003 NewMI = addOffset(MIB, MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3004 break;
3005 }
3006 case X86::ADD16ri:
3007 case X86::ADD16ri8:
3008 case X86::ADD16ri_DB:
3009 case X86::ADD16ri8_DB:
3010 if (DisableLEA16)
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3011 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MI, LV)
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3012 : nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3013 assert(MI.getNumOperands() >= 3 && "Unknown add instruction!");
3014 NewMI = addOffset(BuildMI(MF, MI.getDebugLoc(), get(X86::LEA16r))
3015 .addOperand(Dest)
3016 .addOperand(Src),
3017 MI.getOperand(2).getImm());
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]3018 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3019 }
3020
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3021 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]3022
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3023 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3024 if (Src.isKill())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3025 LV->replaceKillInstruction(Src.getReg(), MI, *NewMI);
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]3026 if (Dest.isDead())
Duncan P. N. Exon Smithd26fdc82016-07-01 01:51:32 +0000[diff] [blame]3027 LV->replaceKillInstruction(Dest.getReg(), MI, *NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]3028 }
3029
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3030 MFI->insert(MI.getIterator(), NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]3031 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]3032}
3033
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3034/// Returns true if the given instruction opcode is FMA3.
3035/// Otherwise, returns false.
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3036/// The second parameter is optional and is used as the second return from
3037/// the function. It is set to true if the given instruction has FMA3 opcode
3038/// that is used for lowering of scalar FMA intrinsics, and it is set to false
3039/// otherwise.
3040static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
3041 if (IsIntrinsic)
3042 *IsIntrinsic = false;
3043
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3044 switch (Opcode) {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3045 case X86::VFMADDSDr132r: case X86::VFMADDSDr132m:
3046 case X86::VFMADDSSr132r: case X86::VFMADDSSr132m:
3047 case X86::VFMSUBSDr132r: case X86::VFMSUBSDr132m:
3048 case X86::VFMSUBSSr132r: case X86::VFMSUBSSr132m:
3049 case X86::VFNMADDSDr132r: case X86::VFNMADDSDr132m:
3050 case X86::VFNMADDSSr132r: case X86::VFNMADDSSr132m:
3051 case X86::VFNMSUBSDr132r: case X86::VFNMSUBSDr132m:
3052 case X86::VFNMSUBSSr132r: case X86::VFNMSUBSSr132m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3053
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3054 case X86::VFMADDSDr213r: case X86::VFMADDSDr213m:
3055 case X86::VFMADDSSr213r: case X86::VFMADDSSr213m:
3056 case X86::VFMSUBSDr213r: case X86::VFMSUBSDr213m:
3057 case X86::VFMSUBSSr213r: case X86::VFMSUBSSr213m:
3058 case X86::VFNMADDSDr213r: case X86::VFNMADDSDr213m:
3059 case X86::VFNMADDSSr213r: case X86::VFNMADDSSr213m:
3060 case X86::VFNMSUBSDr213r: case X86::VFNMSUBSDr213m:
3061 case X86::VFNMSUBSSr213r: case X86::VFNMSUBSSr213m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3062
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3063 case X86::VFMADDSDr231r: case X86::VFMADDSDr231m:
3064 case X86::VFMADDSSr231r: case X86::VFMADDSSr231m:
3065 case X86::VFMSUBSDr231r: case X86::VFMSUBSDr231m:
3066 case X86::VFMSUBSSr231r: case X86::VFMSUBSSr231m:
3067 case X86::VFNMADDSDr231r: case X86::VFNMADDSDr231m:
3068 case X86::VFNMADDSSr231r: case X86::VFNMADDSSr231m:
3069 case X86::VFNMSUBSDr231r: case X86::VFNMSUBSDr231m:
3070 case X86::VFNMSUBSSr231r: case X86::VFNMSUBSSr231m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3071
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3072 case X86::VFMADDSUBPDr132r: case X86::VFMADDSUBPDr132m:
3073 case X86::VFMADDSUBPSr132r: case X86::VFMADDSUBPSr132m:
3074 case X86::VFMSUBADDPDr132r: case X86::VFMSUBADDPDr132m:
3075 case X86::VFMSUBADDPSr132r: case X86::VFMSUBADDPSr132m:
3076 case X86::VFMADDSUBPDr132rY: case X86::VFMADDSUBPDr132mY:
3077 case X86::VFMADDSUBPSr132rY: case X86::VFMADDSUBPSr132mY:
3078 case X86::VFMSUBADDPDr132rY: case X86::VFMSUBADDPDr132mY:
3079 case X86::VFMSUBADDPSr132rY: case X86::VFMSUBADDPSr132mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3080
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3081 case X86::VFMADDPDr132r: case X86::VFMADDPDr132m:
3082 case X86::VFMADDPSr132r: case X86::VFMADDPSr132m:
3083 case X86::VFMSUBPDr132r: case X86::VFMSUBPDr132m:
3084 case X86::VFMSUBPSr132r: case X86::VFMSUBPSr132m:
3085 case X86::VFNMADDPDr132r: case X86::VFNMADDPDr132m:
3086 case X86::VFNMADDPSr132r: case X86::VFNMADDPSr132m:
3087 case X86::VFNMSUBPDr132r: case X86::VFNMSUBPDr132m:
3088 case X86::VFNMSUBPSr132r: case X86::VFNMSUBPSr132m:
3089 case X86::VFMADDPDr132rY: case X86::VFMADDPDr132mY:
3090 case X86::VFMADDPSr132rY: case X86::VFMADDPSr132mY:
3091 case X86::VFMSUBPDr132rY: case X86::VFMSUBPDr132mY:
3092 case X86::VFMSUBPSr132rY: case X86::VFMSUBPSr132mY:
3093 case X86::VFNMADDPDr132rY: case X86::VFNMADDPDr132mY:
3094 case X86::VFNMADDPSr132rY: case X86::VFNMADDPSr132mY:
3095 case X86::VFNMSUBPDr132rY: case X86::VFNMSUBPDr132mY:
3096 case X86::VFNMSUBPSr132rY: case X86::VFNMSUBPSr132mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3097
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3098 case X86::VFMADDSUBPDr213r: case X86::VFMADDSUBPDr213m:
3099 case X86::VFMADDSUBPSr213r: case X86::VFMADDSUBPSr213m:
3100 case X86::VFMSUBADDPDr213r: case X86::VFMSUBADDPDr213m:
3101 case X86::VFMSUBADDPSr213r: case X86::VFMSUBADDPSr213m:
3102 case X86::VFMADDSUBPDr213rY: case X86::VFMADDSUBPDr213mY:
3103 case X86::VFMADDSUBPSr213rY: case X86::VFMADDSUBPSr213mY:
3104 case X86::VFMSUBADDPDr213rY: case X86::VFMSUBADDPDr213mY:
3105 case X86::VFMSUBADDPSr213rY: case X86::VFMSUBADDPSr213mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3106
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3107 case X86::VFMADDPDr213r: case X86::VFMADDPDr213m:
3108 case X86::VFMADDPSr213r: case X86::VFMADDPSr213m:
3109 case X86::VFMSUBPDr213r: case X86::VFMSUBPDr213m:
3110 case X86::VFMSUBPSr213r: case X86::VFMSUBPSr213m:
3111 case X86::VFNMADDPDr213r: case X86::VFNMADDPDr213m:
3112 case X86::VFNMADDPSr213r: case X86::VFNMADDPSr213m:
3113 case X86::VFNMSUBPDr213r: case X86::VFNMSUBPDr213m:
3114 case X86::VFNMSUBPSr213r: case X86::VFNMSUBPSr213m:
3115 case X86::VFMADDPDr213rY: case X86::VFMADDPDr213mY:
3116 case X86::VFMADDPSr213rY: case X86::VFMADDPSr213mY:
3117 case X86::VFMSUBPDr213rY: case X86::VFMSUBPDr213mY:
3118 case X86::VFMSUBPSr213rY: case X86::VFMSUBPSr213mY:
3119 case X86::VFNMADDPDr213rY: case X86::VFNMADDPDr213mY:
3120 case X86::VFNMADDPSr213rY: case X86::VFNMADDPSr213mY:
3121 case X86::VFNMSUBPDr213rY: case X86::VFNMSUBPDr213mY:
3122 case X86::VFNMSUBPSr213rY: case X86::VFNMSUBPSr213mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3123
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3124 case X86::VFMADDSUBPDr231r: case X86::VFMADDSUBPDr231m:
3125 case X86::VFMADDSUBPSr231r: case X86::VFMADDSUBPSr231m:
3126 case X86::VFMSUBADDPDr231r: case X86::VFMSUBADDPDr231m:
3127 case X86::VFMSUBADDPSr231r: case X86::VFMSUBADDPSr231m:
3128 case X86::VFMADDSUBPDr231rY: case X86::VFMADDSUBPDr231mY:
3129 case X86::VFMADDSUBPSr231rY: case X86::VFMADDSUBPSr231mY:
3130 case X86::VFMSUBADDPDr231rY: case X86::VFMSUBADDPDr231mY:
3131 case X86::VFMSUBADDPSr231rY: case X86::VFMSUBADDPSr231mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3132
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3133 case X86::VFMADDPDr231r: case X86::VFMADDPDr231m:
3134 case X86::VFMADDPSr231r: case X86::VFMADDPSr231m:
3135 case X86::VFMSUBPDr231r: case X86::VFMSUBPDr231m:
3136 case X86::VFMSUBPSr231r: case X86::VFMSUBPSr231m:
3137 case X86::VFNMADDPDr231r: case X86::VFNMADDPDr231m:
3138 case X86::VFNMADDPSr231r: case X86::VFNMADDPSr231m:
3139 case X86::VFNMSUBPDr231r: case X86::VFNMSUBPDr231m:
3140 case X86::VFNMSUBPSr231r: case X86::VFNMSUBPSr231m:
3141 case X86::VFMADDPDr231rY: case X86::VFMADDPDr231mY:
3142 case X86::VFMADDPSr231rY: case X86::VFMADDPSr231mY:
3143 case X86::VFMSUBPDr231rY: case X86::VFMSUBPDr231mY:
3144 case X86::VFMSUBPSr231rY: case X86::VFMSUBPSr231mY:
3145 case X86::VFNMADDPDr231rY: case X86::VFNMADDPDr231mY:
3146 case X86::VFNMADDPSr231rY: case X86::VFNMADDPSr231mY:
3147 case X86::VFNMSUBPDr231rY: case X86::VFNMSUBPDr231mY:
3148 case X86::VFNMSUBPSr231rY: case X86::VFNMSUBPSr231mY:
3149 return true;
3150
3151 case X86::VFMADDSDr132r_Int: case X86::VFMADDSDr132m_Int:
3152 case X86::VFMADDSSr132r_Int: case X86::VFMADDSSr132m_Int:
3153 case X86::VFMSUBSDr132r_Int: case X86::VFMSUBSDr132m_Int:
3154 case X86::VFMSUBSSr132r_Int: case X86::VFMSUBSSr132m_Int:
3155 case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int:
3156 case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int:
3157 case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int:
3158 case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int:
3159
3160 case X86::VFMADDSDr213r_Int: case X86::VFMADDSDr213m_Int:
3161 case X86::VFMADDSSr213r_Int: case X86::VFMADDSSr213m_Int:
3162 case X86::VFMSUBSDr213r_Int: case X86::VFMSUBSDr213m_Int:
3163 case X86::VFMSUBSSr213r_Int: case X86::VFMSUBSSr213m_Int:
3164 case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int:
3165 case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int:
3166 case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int:
3167 case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int:
3168
3169 case X86::VFMADDSDr231r_Int: case X86::VFMADDSDr231m_Int:
3170 case X86::VFMADDSSr231r_Int: case X86::VFMADDSSr231m_Int:
3171 case X86::VFMSUBSDr231r_Int: case X86::VFMSUBSDr231m_Int:
3172 case X86::VFMSUBSSr231r_Int: case X86::VFMSUBSSr231m_Int:
3173 case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int:
3174 case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
3175 case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
3176 case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
3177 if (IsIntrinsic)
3178 *IsIntrinsic = true;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3179 return true;
3180 default:
3181 return false;
3182 }
3183 llvm_unreachable("Opcode not handled by the switch");
3184}
3185
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3186MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr &MI, bool NewMI,
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3187 unsigned OpIdx1,
3188 unsigned OpIdx2) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3189 auto cloneIfNew = [NewMI](MachineInstr &MI) -> MachineInstr & {
3190 if (NewMI)
3191 return *MI.getParent()->getParent()->CloneMachineInstr(&MI);
3192 return MI;
3193 };
3194
3195 switch (MI.getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3196 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3197 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3198 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3199 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3200 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3201 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3202 unsigned Opc;
3203 unsigned Size;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3204 switch (MI.getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3205 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3206 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3207 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3208 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3209 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3210 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3211 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3212 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3213 unsigned Amt = MI.getOperand(3).getImm();
3214 auto &WorkingMI = cloneIfNew(MI);
3215 WorkingMI.setDesc(get(Opc));
3216 WorkingMI.getOperand(3).setImm(Size - Amt);
3217 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3218 OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3219 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3220 case X86::BLENDPDrri:
3221 case X86::BLENDPSrri:
3222 case X86::PBLENDWrri:
3223 case X86::VBLENDPDrri:
3224 case X86::VBLENDPSrri:
3225 case X86::VBLENDPDYrri:
3226 case X86::VBLENDPSYrri:
3227 case X86::VPBLENDDrri:
3228 case X86::VPBLENDWrri:
3229 case X86::VPBLENDDYrri:
3230 case X86::VPBLENDWYrri:{
3231 unsigned Mask;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3232 switch (MI.getOpcode()) {
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3233 default: llvm_unreachable("Unreachable!");
3234 case X86::BLENDPDrri: Mask = 0x03; break;
3235 case X86::BLENDPSrri: Mask = 0x0F; break;
3236 case X86::PBLENDWrri: Mask = 0xFF; break;
3237 case X86::VBLENDPDrri: Mask = 0x03; break;
3238 case X86::VBLENDPSrri: Mask = 0x0F; break;
3239 case X86::VBLENDPDYrri: Mask = 0x0F; break;
3240 case X86::VBLENDPSYrri: Mask = 0xFF; break;
3241 case X86::VPBLENDDrri: Mask = 0x0F; break;
3242 case X86::VPBLENDWrri: Mask = 0xFF; break;
3243 case X86::VPBLENDDYrri: Mask = 0xFF; break;
3244 case X86::VPBLENDWYrri: Mask = 0xFF; break;
3245 }
Andrea Di Biagio7ecd22c2014-11-06 14:36:45 +0000[diff] [blame]3246 // Only the least significant bits of Imm are used.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3247 unsigned Imm = MI.getOperand(3).getImm() & Mask;
3248 auto &WorkingMI = cloneIfNew(MI);
3249 WorkingMI.getOperand(3).setImm(Mask ^ Imm);
3250 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3251 OpIdx1, OpIdx2);
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3252 }
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3253 case X86::PCLMULQDQrr:
3254 case X86::VPCLMULQDQrr:{
3255 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3256 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3257 unsigned Imm = MI.getOperand(3).getImm();
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3258 unsigned Src1Hi = Imm & 0x01;
3259 unsigned Src2Hi = Imm & 0x10;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3260 auto &WorkingMI = cloneIfNew(MI);
3261 WorkingMI.getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
3262 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3263 OpIdx1, OpIdx2);
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3264 }
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3265 case X86::CMPPDrri:
3266 case X86::CMPPSrri:
3267 case X86::VCMPPDrri:
3268 case X86::VCMPPSrri:
3269 case X86::VCMPPDYrri:
3270 case X86::VCMPPSYrri: {
3271 // Float comparison can be safely commuted for
3272 // Ordered/Unordered/Equal/NotEqual tests
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3273 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3274 switch (Imm) {
3275 case 0x00: // EQUAL
3276 case 0x03: // UNORDERED
3277 case 0x04: // NOT EQUAL
3278 case 0x07: // ORDERED
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3279 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3280 default:
3281 return nullptr;
3282 }
3283 }
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3284 case X86::VPCOMBri: case X86::VPCOMUBri:
3285 case X86::VPCOMDri: case X86::VPCOMUDri:
3286 case X86::VPCOMQri: case X86::VPCOMUQri:
3287 case X86::VPCOMWri: case X86::VPCOMUWri: {
3288 // Flip comparison mode immediate (if necessary).
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3289 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3290 switch (Imm) {
3291 case 0x00: Imm = 0x02; break; // LT -> GT
3292 case 0x01: Imm = 0x03; break; // LE -> GE
3293 case 0x02: Imm = 0x00; break; // GT -> LT
3294 case 0x03: Imm = 0x01; break; // GE -> LE
3295 case 0x04: // EQ
3296 case 0x05: // NE
3297 case 0x06: // FALSE
3298 case 0x07: // TRUE
3299 default:
3300 break;
3301 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3302 auto &WorkingMI = cloneIfNew(MI);
3303 WorkingMI.getOperand(3).setImm(Imm);
3304 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3305 OpIdx1, OpIdx2);
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3306 }
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3307 case X86::VPERM2F128rr:
3308 case X86::VPERM2I128rr: {
3309 // Flip permute source immediate.
3310 // Imm & 0x02: lo = if set, select Op1.lo/hi else Op0.lo/hi.
3311 // Imm & 0x20: hi = if set, select Op1.lo/hi else Op0.lo/hi.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3312 unsigned Imm = MI.getOperand(3).getImm() & 0xFF;
3313 auto &WorkingMI = cloneIfNew(MI);
3314 WorkingMI.getOperand(3).setImm(Imm ^ 0x22);
3315 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3316 OpIdx1, OpIdx2);
Simon Pilgrimd1d11802016-01-25 21:51:34 +0000[diff] [blame]3317 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3318 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
3319 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3320 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
3321 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3322 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3323 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
3324 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
3325 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3326 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3327 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
3328 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
3329 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3330 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
3331 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3332 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
3333 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3334 unsigned Opc;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3335 switch (MI.getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3336 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3337 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
3338 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
3339 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
3340 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3341 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3342 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3343 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
3344 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
3345 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
3346 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3347 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3348 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]3349 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3350 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3351 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3352 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
3353 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
3354 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3355 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
3356 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
3357 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
3358 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3359 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3360 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3361 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3362 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3363 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3364 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
3365 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3366 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3367 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3368 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3369 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3370 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3371 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3372 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3373 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3374 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3375 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3376 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3377 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3378 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3379 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3380 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3381 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3382 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3383 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3384 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3385 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3386 auto &WorkingMI = cloneIfNew(MI);
3387 WorkingMI.setDesc(get(Opc));
3388 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3389 OpIdx1, OpIdx2);
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3390 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3391 default:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3392 if (isFMA3(MI.getOpcode())) {
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3393 unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
3394 if (Opc == 0)
3395 return nullptr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3396 auto &WorkingMI = cloneIfNew(MI);
3397 WorkingMI.setDesc(get(Opc));
3398 return TargetInstrInfo::commuteInstructionImpl(WorkingMI, /*NewMI=*/false,
3399 OpIdx1, OpIdx2);
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3400 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3401
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3402 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3403 }
3404}
3405
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3406bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr &MI,
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3407 unsigned &SrcOpIdx1,
3408 unsigned &SrcOpIdx2) const {
3409
3410 unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3411
3412 // Only the first RegOpsNum operands are commutable.
3413 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3414 // that the operand is not specified/fixed.
3415 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3416 (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3417 return false;
3418 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3419 (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3420 return false;
3421
3422 // Look for two different register operands assumed to be commutable
3423 // regardless of the FMA opcode. The FMA opcode is adjusted later.
3424 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3425 SrcOpIdx2 == CommuteAnyOperandIndex) {
3426 unsigned CommutableOpIdx1 = SrcOpIdx1;
3427 unsigned CommutableOpIdx2 = SrcOpIdx2;
3428
3429 // At least one of operands to be commuted is not specified and
3430 // this method is free to choose appropriate commutable operands.
3431 if (SrcOpIdx1 == SrcOpIdx2)
3432 // Both of operands are not fixed. By default set one of commutable
3433 // operands to the last register operand of the instruction.
3434 CommutableOpIdx2 = RegOpsNum;
3435 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3436 // Only one of operands is not fixed.
3437 CommutableOpIdx2 = SrcOpIdx1;
3438
3439 // CommutableOpIdx2 is well defined now. Let's choose another commutable
3440 // operand and assign its index to CommutableOpIdx1.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3441 unsigned Op2Reg = MI.getOperand(CommutableOpIdx2).getReg();
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3442 for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3443 // The commuted operands must have different registers.
3444 // Otherwise, the commute transformation does not change anything and
3445 // is useless then.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3446 if (Op2Reg != MI.getOperand(CommutableOpIdx1).getReg())
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3447 break;
3448 }
3449
3450 // No appropriate commutable operands were found.
3451 if (CommutableOpIdx1 == 0)
3452 return false;
3453
3454 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3455 // to return those values.
3456 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3457 CommutableOpIdx1, CommutableOpIdx2))
3458 return false;
3459 }
3460
3461 // Check if we can adjust the opcode to preserve the semantics when
3462 // commute the register operands.
3463 return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
3464}
3465
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3466unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(
3467 MachineInstr &MI, unsigned SrcOpIdx1, unsigned SrcOpIdx2) const {
3468 unsigned Opc = MI.getOpcode();
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3469
3470 // Define the array that holds FMA opcodes in groups
3471 // of 3 opcodes(132, 213, 231) in each group.
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3472 static const uint16_t RegularOpcodeGroups[][3] = {
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3473 { X86::VFMADDSSr132r, X86::VFMADDSSr213r, X86::VFMADDSSr231r },
3474 { X86::VFMADDSDr132r, X86::VFMADDSDr213r, X86::VFMADDSDr231r },
3475 { X86::VFMADDPSr132r, X86::VFMADDPSr213r, X86::VFMADDPSr231r },
3476 { X86::VFMADDPDr132r, X86::VFMADDPDr213r, X86::VFMADDPDr231r },
3477 { X86::VFMADDPSr132rY, X86::VFMADDPSr213rY, X86::VFMADDPSr231rY },
3478 { X86::VFMADDPDr132rY, X86::VFMADDPDr213rY, X86::VFMADDPDr231rY },
3479 { X86::VFMADDSSr132m, X86::VFMADDSSr213m, X86::VFMADDSSr231m },
3480 { X86::VFMADDSDr132m, X86::VFMADDSDr213m, X86::VFMADDSDr231m },
3481 { X86::VFMADDPSr132m, X86::VFMADDPSr213m, X86::VFMADDPSr231m },
3482 { X86::VFMADDPDr132m, X86::VFMADDPDr213m, X86::VFMADDPDr231m },
3483 { X86::VFMADDPSr132mY, X86::VFMADDPSr213mY, X86::VFMADDPSr231mY },
3484 { X86::VFMADDPDr132mY, X86::VFMADDPDr213mY, X86::VFMADDPDr231mY },
3485
3486 { X86::VFMSUBSSr132r, X86::VFMSUBSSr213r, X86::VFMSUBSSr231r },
3487 { X86::VFMSUBSDr132r, X86::VFMSUBSDr213r, X86::VFMSUBSDr231r },
3488 { X86::VFMSUBPSr132r, X86::VFMSUBPSr213r, X86::VFMSUBPSr231r },
3489 { X86::VFMSUBPDr132r, X86::VFMSUBPDr213r, X86::VFMSUBPDr231r },
3490 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr213rY, X86::VFMSUBPSr231rY },
3491 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr213rY, X86::VFMSUBPDr231rY },
3492 { X86::VFMSUBSSr132m, X86::VFMSUBSSr213m, X86::VFMSUBSSr231m },
3493 { X86::VFMSUBSDr132m, X86::VFMSUBSDr213m, X86::VFMSUBSDr231m },
3494 { X86::VFMSUBPSr132m, X86::VFMSUBPSr213m, X86::VFMSUBPSr231m },
3495 { X86::VFMSUBPDr132m, X86::VFMSUBPDr213m, X86::VFMSUBPDr231m },
3496 { X86::VFMSUBPSr132mY, X86::VFMSUBPSr213mY, X86::VFMSUBPSr231mY },
3497 { X86::VFMSUBPDr132mY, X86::VFMSUBPDr213mY, X86::VFMSUBPDr231mY },
Vyacheslav Klochkov1ff9cbd2015-11-12 20:11:57 +0000[diff] [blame]3498
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3499 { X86::VFNMADDSSr132r, X86::VFNMADDSSr213r, X86::VFNMADDSSr231r },
3500 { X86::VFNMADDSDr132r, X86::VFNMADDSDr213r, X86::VFNMADDSDr231r },
3501 { X86::VFNMADDPSr132r, X86::VFNMADDPSr213r, X86::VFNMADDPSr231r },
3502 { X86::VFNMADDPDr132r, X86::VFNMADDPDr213r, X86::VFNMADDPDr231r },
3503 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
3504 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
3505 { X86::VFNMADDSSr132m, X86::VFNMADDSSr213m, X86::VFNMADDSSr231m },
3506 { X86::VFNMADDSDr132m, X86::VFNMADDSDr213m, X86::VFNMADDSDr231m },
3507 { X86::VFNMADDPSr132m, X86::VFNMADDPSr213m, X86::VFNMADDPSr231m },
3508 { X86::VFNMADDPDr132m, X86::VFNMADDPDr213m, X86::VFNMADDPDr231m },
3509 { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
3510 { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
3511
3512 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr213r, X86::VFNMSUBSSr231r },
3513 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr213r, X86::VFNMSUBSDr231r },
3514 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr213r, X86::VFNMSUBPSr231r },
3515 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr213r, X86::VFNMSUBPDr231r },
3516 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
3517 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
3518 { X86::VFNMSUBSSr132m, X86::VFNMSUBSSr213m, X86::VFNMSUBSSr231m },
3519 { X86::VFNMSUBSDr132m, X86::VFNMSUBSDr213m, X86::VFNMSUBSDr231m },
3520 { X86::VFNMSUBPSr132m, X86::VFNMSUBPSr213m, X86::VFNMSUBPSr231m },
3521 { X86::VFNMSUBPDr132m, X86::VFNMSUBPDr213m, X86::VFNMSUBPDr231m },
3522 { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
3523 { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
3524
3525 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr231r },
3526 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr231r },
3527 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
3528 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
3529 { X86::VFMADDSUBPSr132m, X86::VFMADDSUBPSr213m, X86::VFMADDSUBPSr231m },
3530 { X86::VFMADDSUBPDr132m, X86::VFMADDSUBPDr213m, X86::VFMADDSUBPDr231m },
3531 { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
3532 { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
3533
3534 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr231r },
3535 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr231r },
3536 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
3537 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
3538 { X86::VFMSUBADDPSr132m, X86::VFMSUBADDPSr213m, X86::VFMSUBADDPSr231m },
3539 { X86::VFMSUBADDPDr132m, X86::VFMSUBADDPDr213m, X86::VFMSUBADDPDr231m },
3540 { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
3541 { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
3542 };
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3543
3544 // Define the array that holds FMA*_Int opcodes in groups
3545 // of 3 opcodes(132, 213, 231) in each group.
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3546 static const uint16_t IntrinOpcodeGroups[][3] = {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3547 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr213r_Int, X86::VFMADDSSr231r_Int },
3548 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr213r_Int, X86::VFMADDSDr231r_Int },
3549 { X86::VFMADDSSr132m_Int, X86::VFMADDSSr213m_Int, X86::VFMADDSSr231m_Int },
3550 { X86::VFMADDSDr132m_Int, X86::VFMADDSDr213m_Int, X86::VFMADDSDr231m_Int },
3551
3552 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr231r_Int },
3553 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr231r_Int },
3554 { X86::VFMSUBSSr132m_Int, X86::VFMSUBSSr213m_Int, X86::VFMSUBSSr231m_Int },
3555 { X86::VFMSUBSDr132m_Int, X86::VFMSUBSDr213m_Int, X86::VFMSUBSDr231m_Int },
3556
3557 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
3558 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
3559 { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
3560 { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
3561
3562 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
3563 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
3564 { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
3565 { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
3566 };
3567
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3568 const unsigned Form132Index = 0;
3569 const unsigned Form213Index = 1;
3570 const unsigned Form231Index = 2;
3571 const unsigned FormsNum = 3;
3572
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3573 bool IsIntrinOpcode;
3574 isFMA3(Opc, &IsIntrinOpcode);
3575
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3576 size_t GroupsNum;
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3577 const uint16_t (*OpcodeGroups)[3];
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3578 if (IsIntrinOpcode) {
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3579 GroupsNum = array_lengthof(IntrinOpcodeGroups);
Craig Topper27e29122015-11-30 02:28:19 +0000[diff] [blame]3580 OpcodeGroups = IntrinOpcodeGroups;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3581 } else {
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3582 GroupsNum = array_lengthof(RegularOpcodeGroups);
Craig Topper27e29122015-11-30 02:28:19 +0000[diff] [blame]3583 OpcodeGroups = RegularOpcodeGroups;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3584 }
3585
Craig Toppercf65c622016-03-02 04:42:31 +0000[diff] [blame]3586 const uint16_t *FoundOpcodesGroup = nullptr;
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3587 size_t FormIndex;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3588
3589 // Look for the input opcode in the corresponding opcodes table.
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3590 for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
3591 ++GroupIndex) {
3592 for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3593 if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
3594 FoundOpcodesGroup = OpcodeGroups[GroupIndex];
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3595 break;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3596 }
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3597 }
3598 }
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3599
3600 // The input opcode does not match with any of the opcodes from the tables.
3601 // The unsupported FMA opcode must be added to one of the two opcode groups
3602 // defined above.
3603 assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3604
3605 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3606 if (SrcOpIdx1 > SrcOpIdx2)
3607 std::swap(SrcOpIdx1, SrcOpIdx2);
3608
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3609 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3610 // analysis. The commute optimization is legal only if all users of FMA*_Int
3611 // use only the lowest element of the FMA*_Int instruction. Such analysis are
3612 // not implemented yet. So, just return 0 in that case.
3613 // When such analysis are available this place will be the right place for
3614 // calling it.
3615 if (IsIntrinOpcode && SrcOpIdx1 == 1)
3616 return 0;
3617
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3618 unsigned Case;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3619 if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3620 Case = 0;
3621 else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3622 Case = 1;
3623 else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3624 Case = 2;
3625 else
3626 return 0;
3627
3628 // Define the FMA forms mapping array that helps to map input FMA form
3629 // to output FMA form to preserve the operation semantics after
3630 // commuting the operands.
3631 static const unsigned FormMapping[][3] = {
3632 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3633 // FMA132 A, C, b; ==> FMA231 C, A, b;
3634 // FMA213 B, A, c; ==> FMA213 A, B, c;
3635 // FMA231 C, A, b; ==> FMA132 A, C, b;
3636 { Form231Index, Form213Index, Form132Index },
3637 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3638 // FMA132 A, c, B; ==> FMA132 B, c, A;
3639 // FMA213 B, a, C; ==> FMA231 C, a, B;
3640 // FMA231 C, a, B; ==> FMA213 B, a, C;
3641 { Form132Index, Form231Index, Form213Index },
3642 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3643 // FMA132 a, C, B; ==> FMA213 a, B, C;
3644 // FMA213 b, A, C; ==> FMA132 b, C, A;
3645 // FMA231 c, A, B; ==> FMA231 c, B, A;
3646 { Form213Index, Form132Index, Form231Index }
3647 };
3648
3649 // Everything is ready, just adjust the FMA opcode and return it.
3650 FormIndex = FormMapping[Case][FormIndex];
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3651 return FoundOpcodesGroup[FormIndex];
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3652}
3653
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3654bool X86InstrInfo::findCommutedOpIndices(MachineInstr &MI, unsigned &SrcOpIdx1,
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3655 unsigned &SrcOpIdx2) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3656 switch (MI.getOpcode()) {
3657 case X86::CMPPDrri:
3658 case X86::CMPPSrri:
3659 case X86::VCMPPDrri:
3660 case X86::VCMPPSrri:
3661 case X86::VCMPPDYrri:
3662 case X86::VCMPPSYrri: {
3663 // Float comparison can be safely commuted for
3664 // Ordered/Unordered/Equal/NotEqual tests
3665 unsigned Imm = MI.getOperand(3).getImm() & 0x7;
3666 switch (Imm) {
3667 case 0x00: // EQUAL
3668 case 0x03: // UNORDERED
3669 case 0x04: // NOT EQUAL
3670 case 0x07: // ORDERED
3671 // The indices of the commutable operands are 1 and 2.
3672 // Assign them to the returned operand indices here.
3673 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3674 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]3675 return false;
3676 }
3677 default:
3678 if (isFMA3(MI.getOpcode()))
3679 return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3680 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3681 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3682 return false;
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3683}
3684
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3685static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3686 switch (BrOpc) {
3687 default: return X86::COND_INVALID;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3688 case X86::JE_1: return X86::COND_E;
3689 case X86::JNE_1: return X86::COND_NE;
3690 case X86::JL_1: return X86::COND_L;
3691 case X86::JLE_1: return X86::COND_LE;
3692 case X86::JG_1: return X86::COND_G;
3693 case X86::JGE_1: return X86::COND_GE;
3694 case X86::JB_1: return X86::COND_B;
3695 case X86::JBE_1: return X86::COND_BE;
3696 case X86::JA_1: return X86::COND_A;
3697 case X86::JAE_1: return X86::COND_AE;
3698 case X86::JS_1: return X86::COND_S;
3699 case X86::JNS_1: return X86::COND_NS;
3700 case X86::JP_1: return X86::COND_P;
3701 case X86::JNP_1: return X86::COND_NP;
3702 case X86::JO_1: return X86::COND_O;
3703 case X86::JNO_1: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3704 }
3705}
3706
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3707/// Return condition code of a SET opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3708static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3709 switch (Opc) {
3710 default: return X86::COND_INVALID;
3711 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3712 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3713 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3714 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3715 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3716 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3717 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3718 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3719 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3720 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3721 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3722 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3723 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3724 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3725 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3726 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3727 }
3728}
3729
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3730/// Return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3731X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3732 switch (Opc) {
3733 default: return X86::COND_INVALID;
3734 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3735 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3736 return X86::COND_A;
3737 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3738 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3739 return X86::COND_AE;
3740 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3741 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3742 return X86::COND_B;
3743 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3744 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3745 return X86::COND_BE;
3746 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3747 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3748 return X86::COND_E;
3749 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3750 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3751 return X86::COND_G;
3752 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3753 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3754 return X86::COND_GE;
3755 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3756 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3757 return X86::COND_L;
3758 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3759 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3760 return X86::COND_LE;
3761 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3762 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3763 return X86::COND_NE;
3764 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3765 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3766 return X86::COND_NO;
3767 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3768 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3769 return X86::COND_NP;
3770 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3771 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3772 return X86::COND_NS;
3773 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3774 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3775 return X86::COND_O;
3776 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3777 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3778 return X86::COND_P;
3779 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3780 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3781 return X86::COND_S;
3782 }
3783}
3784
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3785unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3786 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3787 default: llvm_unreachable("Illegal condition code!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3788 case X86::COND_E: return X86::JE_1;
3789 case X86::COND_NE: return X86::JNE_1;
3790 case X86::COND_L: return X86::JL_1;
3791 case X86::COND_LE: return X86::JLE_1;
3792 case X86::COND_G: return X86::JG_1;
3793 case X86::COND_GE: return X86::JGE_1;
3794 case X86::COND_B: return X86::JB_1;
3795 case X86::COND_BE: return X86::JBE_1;
3796 case X86::COND_A: return X86::JA_1;
3797 case X86::COND_AE: return X86::JAE_1;
3798 case X86::COND_S: return X86::JS_1;
3799 case X86::COND_NS: return X86::JNS_1;
3800 case X86::COND_P: return X86::JP_1;
3801 case X86::COND_NP: return X86::JNP_1;
3802 case X86::COND_O: return X86::JO_1;
3803 case X86::COND_NO: return X86::JNO_1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3804 }
3805}
3806
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3807/// Return the inverse of the specified condition,
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3808/// e.g. turning COND_E to COND_NE.
3809X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3810 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3811 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3812 case X86::COND_E: return X86::COND_NE;
3813 case X86::COND_NE: return X86::COND_E;
3814 case X86::COND_L: return X86::COND_GE;
3815 case X86::COND_LE: return X86::COND_G;
3816 case X86::COND_G: return X86::COND_LE;
3817 case X86::COND_GE: return X86::COND_L;
3818 case X86::COND_B: return X86::COND_AE;
3819 case X86::COND_BE: return X86::COND_A;
3820 case X86::COND_A: return X86::COND_BE;
3821 case X86::COND_AE: return X86::COND_B;
3822 case X86::COND_S: return X86::COND_NS;
3823 case X86::COND_NS: return X86::COND_S;
3824 case X86::COND_P: return X86::COND_NP;
3825 case X86::COND_NP: return X86::COND_P;
3826 case X86::COND_O: return X86::COND_NO;
3827 case X86::COND_NO: return X86::COND_O;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3828 case X86::COND_NE_OR_P: return X86::COND_E_AND_NP;
3829 case X86::COND_E_AND_NP: return X86::COND_NE_OR_P;
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3830 }
3831}
3832
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3833/// Assuming the flags are set by MI(a,b), return the condition code if we
3834/// modify the instructions such that flags are set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]3835static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3836 switch (CC) {
3837 default: return X86::COND_INVALID;
3838 case X86::COND_E: return X86::COND_E;
3839 case X86::COND_NE: return X86::COND_NE;
3840 case X86::COND_L: return X86::COND_G;
3841 case X86::COND_LE: return X86::COND_GE;
3842 case X86::COND_G: return X86::COND_L;
3843 case X86::COND_GE: return X86::COND_LE;
3844 case X86::COND_B: return X86::COND_A;
3845 case X86::COND_BE: return X86::COND_AE;
3846 case X86::COND_A: return X86::COND_B;
3847 case X86::COND_AE: return X86::COND_BE;
3848 }
3849}
3850
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3851/// Return a set opcode for the given condition and
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3852/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3853unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3854 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3855 { X86::SETAr, X86::SETAm },
3856 { X86::SETAEr, X86::SETAEm },
3857 { X86::SETBr, X86::SETBm },
3858 { X86::SETBEr, X86::SETBEm },
3859 { X86::SETEr, X86::SETEm },
3860 { X86::SETGr, X86::SETGm },
3861 { X86::SETGEr, X86::SETGEm },
3862 { X86::SETLr, X86::SETLm },
3863 { X86::SETLEr, X86::SETLEm },
3864 { X86::SETNEr, X86::SETNEm },
3865 { X86::SETNOr, X86::SETNOm },
3866 { X86::SETNPr, X86::SETNPm },
3867 { X86::SETNSr, X86::SETNSm },
3868 { X86::SETOr, X86::SETOm },
3869 { X86::SETPr, X86::SETPm },
3870 { X86::SETSr, X86::SETSm }
3871 };
3872
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3873 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3874 return Opc[CC][HasMemoryOperand ? 1 : 0];
3875}
3876
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3877/// Return a cmov opcode for the given condition,
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3878/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]3879unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3880 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3881 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3882 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3883 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3884 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3885 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3886 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3887 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3888 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3889 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3890 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3891 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3892 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3893 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3894 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3895 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3896 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3897 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3898 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3899 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3900 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3901 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3902 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3903 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3904 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3905 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3906 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3907 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3908 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3909 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3910 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3911 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3912 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3913 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3914 };
3915
3916 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3917 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3918 switch(RegBytes) {
3919 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3920 case 2: return Opc[Idx][0];
3921 case 4: return Opc[Idx][1];
3922 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3923 }
3924}
3925
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]3926bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr &MI) const {
3927 if (!MI.isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3928
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3929 // Conditional branch is a special case.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]3930 if (MI.isBranch() && !MI.isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3931 return true;
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]3932 if (!MI.isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3933 return true;
3934 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3935}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3936
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]3937// Given a MBB and its TBB, find the FBB which was a fallthrough MBB (it may
3938// not be a fallthrough MBB now due to layout changes). Return nullptr if the
3939// fallthrough MBB cannot be identified.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3940static MachineBasicBlock *getFallThroughMBB(MachineBasicBlock *MBB,
3941 MachineBasicBlock *TBB) {
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]3942 // Look for non-EHPad successors other than TBB. If we find exactly one, it
3943 // is the fallthrough MBB. If we find zero, then TBB is both the target MBB
3944 // and fallthrough MBB. If we find more than one, we cannot identify the
3945 // fallthrough MBB and should return nullptr.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3946 MachineBasicBlock *FallthroughBB = nullptr;
3947 for (auto SI = MBB->succ_begin(), SE = MBB->succ_end(); SI != SE; ++SI) {
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]3948 if ((*SI)->isEHPad() || (*SI == TBB && FallthroughBB))
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3949 continue;
3950 // Return a nullptr if we found more than one fallthrough successor.
David L Kreitzere7c583e2016-05-17 12:47:46 +0000[diff] [blame]3951 if (FallthroughBB && FallthroughBB != TBB)
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]3952 return nullptr;
3953 FallthroughBB = *SI;
3954 }
3955 return FallthroughBB;
3956}
3957
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]3958bool X86InstrInfo::AnalyzeBranchImpl(
3959 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3960 SmallVectorImpl<MachineOperand> &Cond,
3961 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3962
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3963 // Start from the bottom of the block and work up, examining the
3964 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3965 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3966 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3967 while (I != MBB.begin()) {
3968 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]3969 if (I->isDebugValue())
3970 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3971
3972 // Working from the bottom, when we see a non-terminator instruction, we're
3973 // done.
Duncan P. N. Exon Smith6307eb52016-02-23 02:46:52 +0000[diff] [blame]3974 if (!isUnpredicatedTerminator(*I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3975 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3976
3977 // A terminator that isn't a branch can't easily be handled by this
3978 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3979 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3980 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3981
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3982 // Handle unconditional branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3983 if (I->getOpcode() == X86::JMP_1) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3984 UnCondBrIter = I;
3985
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3986 if (!AllowModify) {
3987 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]3988 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3989 }
3990
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3991 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]3992 while (std::next(I) != MBB.end())
3993 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3994
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3995 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3996 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3997
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3998 // Delete the JMP if it's equivalent to a fall-through.
3999 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]4000 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4001 I->eraseFromParent();
4002 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4003 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4004 continue;
4005 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4006
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4007 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4008 TBB = I->getOperand(0).getMBB();
4009 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4010 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4011
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4012 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4013 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4014 if (BranchCode == X86::COND_INVALID)
4015 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4016
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4017 // Working from the bottom, handle the first conditional branch.
4018 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4019 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
4020 if (AllowModify && UnCondBrIter != MBB.end() &&
4021 MBB.isLayoutSuccessor(TargetBB)) {
4022 // If we can modify the code and it ends in something like:
4023 //
4024 // jCC L1
4025 // jmp L2
4026 // L1:
4027 // ...
4028 // L2:
4029 //
4030 // Then we can change this to:
4031 //
4032 // jnCC L2
4033 // L1:
4034 // ...
4035 // L2:
4036 //
4037 // Which is a bit more efficient.
4038 // We conditionally jump to the fall-through block.
4039 BranchCode = GetOppositeBranchCondition(BranchCode);
4040 unsigned JNCC = GetCondBranchFromCond(BranchCode);
4041 MachineBasicBlock::iterator OldInst = I;
4042
4043 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4044 .addMBB(UnCondBrIter->getOperand(0).getMBB());
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4045 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
Benjamin Kramerd477e9e2016-01-27 12:44:12 +0000[diff] [blame]4046 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]4047
4048 OldInst->eraseFromParent();
4049 UnCondBrIter->eraseFromParent();
4050
4051 // Restart the analysis.
4052 UnCondBrIter = MBB.end();
4053 I = MBB.end();
4054 continue;
4055 }
4056
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4057 FBB = TBB;
4058 TBB = I->getOperand(0).getMBB();
4059 Cond.push_back(MachineOperand::CreateImm(BranchCode));
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4060 CondBranches.push_back(I);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4061 continue;
4062 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4063
4064 // Handle subsequent conditional branches. Only handle the case where all
4065 // conditional branches branch to the same destination and their condition
4066 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4067 assert(Cond.size() == 1);
4068 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4069
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4070 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4071 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4072 auto NewTBB = I->getOperand(0).getMBB();
4073 if (OldBranchCode == BranchCode && TBB == NewTBB)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4074 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4075
4076 // If they differ, see if they fit one of the known patterns. Theoretically,
4077 // we could handle more patterns here, but we shouldn't expect to see them
4078 // if instruction selection has done a reasonable job.
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4079 if (TBB == NewTBB &&
4080 ((OldBranchCode == X86::COND_P && BranchCode == X86::COND_NE) ||
4081 (OldBranchCode == X86::COND_NE && BranchCode == X86::COND_P))) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4082 BranchCode = X86::COND_NE_OR_P;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4083 } else if ((OldBranchCode == X86::COND_NP && BranchCode == X86::COND_NE) ||
4084 (OldBranchCode == X86::COND_E && BranchCode == X86::COND_P)) {
4085 if (NewTBB != (FBB ? FBB : getFallThroughMBB(&MBB, TBB)))
4086 return true;
4087
4088 // X86::COND_E_AND_NP usually has two different branch destinations.
4089 //
4090 // JP B1
4091 // JE B2
4092 // JMP B1
4093 // B1:
4094 // B2:
4095 //
4096 // Here this condition branches to B2 only if NP && E. It has another
4097 // equivalent form:
4098 //
4099 // JNE B1
4100 // JNP B2
4101 // JMP B1
4102 // B1:
4103 // B2:
4104 //
4105 // Similarly it branches to B2 only if E && NP. That is why this condition
4106 // is named with COND_E_AND_NP.
4107 BranchCode = X86::COND_E_AND_NP;
4108 } else
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4109 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4110
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4111 // Update the MachineOperand.
4112 Cond[0].setImm(BranchCode);
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4113 CondBranches.push_back(I);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]4114 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4115
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4116 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4117}
4118
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4119bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
4120 MachineBasicBlock *&TBB,
4121 MachineBasicBlock *&FBB,
4122 SmallVectorImpl<MachineOperand> &Cond,
4123 bool AllowModify) const {
4124 SmallVector<MachineInstr *, 4> CondBranches;
4125 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4126}
4127
4128bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB,
4129 MachineBranchPredicate &MBP,
4130 bool AllowModify) const {
4131 using namespace std::placeholders;
4132
4133 SmallVector<MachineOperand, 4> Cond;
4134 SmallVector<MachineInstr *, 4> CondBranches;
4135 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4136 AllowModify))
4137 return true;
4138
4139 if (Cond.size() != 1)
4140 return true;
4141
4142 assert(MBP.TrueDest && "expected!");
4143
4144 if (!MBP.FalseDest)
4145 MBP.FalseDest = MBB.getNextNode();
4146
4147 const TargetRegisterInfo *TRI = &getRegisterInfo();
4148
4149 MachineInstr *ConditionDef = nullptr;
4150 bool SingleUseCondition = true;
4151
4152 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4153 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4154 ConditionDef = &*I;
4155 break;
4156 }
4157
4158 if (I->readsRegister(X86::EFLAGS, TRI))
4159 SingleUseCondition = false;
4160 }
4161
4162 if (!ConditionDef)
4163 return true;
4164
4165 if (SingleUseCondition) {
4166 for (auto *Succ : MBB.successors())
4167 if (Succ->isLiveIn(X86::EFLAGS))
4168 SingleUseCondition = false;
4169 }
4170
4171 MBP.ConditionDef = ConditionDef;
4172 MBP.SingleUseCondition = SingleUseCondition;
4173
4174 // Currently we only recognize the simple pattern:
4175 //
4176 // test %reg, %reg
4177 // je %label
4178 //
4179 const unsigned TestOpcode =
4180 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4181
4182 if (ConditionDef->getOpcode() == TestOpcode &&
4183 ConditionDef->getNumOperands() == 3 &&
4184 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4185 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4186 MBP.LHS = ConditionDef->getOperand(0);
4187 MBP.RHS = MachineOperand::CreateImm(0);
4188 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4189 ? MachineBranchPredicate::PRED_NE
4190 : MachineBranchPredicate::PRED_EQ;
4191 return false;
4192 }
4193
4194 return true;
4195}
4196
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4197unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4198 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4199 unsigned Count = 0;
4200
4201 while (I != MBB.begin()) {
4202 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]4203 if (I->isDebugValue())
4204 continue;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4205 if (I->getOpcode() != X86::JMP_1 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4206 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4207 break;
4208 // Remove the branch.
4209 I->eraseFromParent();
4210 I = MBB.end();
4211 ++Count;
4212 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4213
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4214 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4215}
4216
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4217unsigned X86InstrInfo::InsertBranch(MachineBasicBlock &MBB,
4218 MachineBasicBlock *TBB,
4219 MachineBasicBlock *FBB,
4220 ArrayRef<MachineOperand> Cond,
4221 const DebugLoc &DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4222 // Shouldn't be a fall through.
4223 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]4224 assert((Cond.size() == 1 || Cond.size() == 0) &&
4225 "X86 branch conditions have one component!");
4226
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4227 if (Cond.empty()) {
4228 // Unconditional branch?
4229 assert(!FBB && "Unconditional branch with multiple successors!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4230 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4231 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4232 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4233
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4234 // If FBB is null, it is implied to be a fall-through block.
4235 bool FallThru = FBB == nullptr;
4236
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4237 // Conditional branch.
4238 unsigned Count = 0;
4239 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4240 switch (CC) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4241 case X86::COND_NE_OR_P:
4242 // Synthesize NE_OR_P with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4243 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4244 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4245 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4246 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4247 break;
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4248 case X86::COND_E_AND_NP:
4249 // Use the next block of MBB as FBB if it is null.
4250 if (FBB == nullptr) {
4251 FBB = getFallThroughMBB(&MBB, TBB);
4252 assert(FBB && "MBB cannot be the last block in function when the false "
4253 "body is a fall-through.");
4254 }
4255 // Synthesize COND_E_AND_NP with two branches.
4256 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(FBB);
4257 ++Count;
4258 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
4259 ++Count;
4260 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4261 default: {
4262 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]4263 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4264 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4265 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4266 }
Cong Hou94710842016-03-23 21:45:37 +0000[diff] [blame]4267 if (!FallThru) {
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4268 // Two-way Conditional branch. Insert the second branch.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4269 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4270 ++Count;
4271 }
4272 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4273}
4274
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4275bool X86InstrInfo::
4276canInsertSelect(const MachineBasicBlock &MBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]4277 ArrayRef<MachineOperand> Cond,
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4278 unsigned TrueReg, unsigned FalseReg,
4279 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4280 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4281 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4282 return false;
4283 if (Cond.size() != 1)
4284 return false;
4285 // We cannot do the composite conditions, at least not in SSA form.
4286 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4287 return false;
4288
4289 // Check register classes.
4290 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4291 const TargetRegisterClass *RC =
4292 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4293 if (!RC)
4294 return false;
4295
4296 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4297 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4298 X86::GR32RegClass.hasSubClassEq(RC) ||
4299 X86::GR64RegClass.hasSubClassEq(RC)) {
4300 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4301 // Bridge. Probably Ivy Bridge as well.
4302 CondCycles = 2;
4303 TrueCycles = 2;
4304 FalseCycles = 2;
4305 return true;
4306 }
4307
4308 // Can't do vectors.
4309 return false;
4310}
4311
4312void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4313 MachineBasicBlock::iterator I,
4314 const DebugLoc &DL, unsigned DstReg,
4315 ArrayRef<MachineOperand> Cond, unsigned TrueReg,
4316 unsigned FalseReg) const {
4317 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4318 assert(Cond.size() == 1 && "Invalid Cond array");
4319 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
4320 MRI.getRegClass(DstReg)->getSize(),
4321 false /*HasMemoryOperand*/);
4322 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4323}
4324
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4325/// Test if the given register is a physical h register.
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4326static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4327 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4328}
4329
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4330// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4331static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4332 const X86Subtarget &Subtarget) {
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4333
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4334 // SrcReg(VR128) -> DestReg(GR64)
4335 // SrcReg(VR64) -> DestReg(GR64)
4336 // SrcReg(GR64) -> DestReg(VR128)
4337 // SrcReg(GR64) -> DestReg(VR64)
4338
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4339 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4340 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4341 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4342 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4343 // Copy from a VR128 register to a GR64 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4344 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
4345 X86::MOVPQIto64rr);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4346 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4347 // Copy from a VR64 register to a GR64 register.
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4348 return X86::MMX_MOVD64from64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4349 } else if (X86::GR64RegClass.contains(SrcReg)) {
4350 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4351 if (X86::VR128XRegClass.contains(DestReg))
4352 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
4353 X86::MOV64toPQIrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4354 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4355 if (X86::VR64RegClass.contains(DestReg))
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4356 return X86::MMX_MOVD64to64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4357 }
4358
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4359 // SrcReg(FR32) -> DestReg(GR32)
4360 // SrcReg(GR32) -> DestReg(FR32)
4361
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4362 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4363 // Copy from a FR32 register to a GR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4364 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4365
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4366 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4367 // Copy from a GR32 register to a FR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4368 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4369 return 0;
4370}
4371
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4372static bool isMaskRegClass(const TargetRegisterClass *RC) {
4373 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4374 return X86::VK16RegClass.hasSubClassEq(RC);
4375}
4376
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4377static bool MaskRegClassContains(unsigned Reg) {
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4378 // All KMASK RegClasses hold the same k registers, can be tested against anyone.
4379 return X86::VK16RegClass.contains(Reg);
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]4380}
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4381
4382static bool GRRegClassContains(unsigned Reg) {
4383 return X86::GR64RegClass.contains(Reg) ||
4384 X86::GR32RegClass.contains(Reg) ||
4385 X86::GR16RegClass.contains(Reg) ||
4386 X86::GR8RegClass.contains(Reg);
4387}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4388static
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4389unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4390 if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4391 DestReg = getX86SubSuperRegister(DestReg, 32);
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4392 return X86::KMOVBrk;
4393 }
4394 if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4395 SrcReg = getX86SubSuperRegister(SrcReg, 32);
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4396 return X86::KMOVBkr;
4397 }
4398 return 0;
4399}
4400
4401static
4402unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4403 if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4404 return X86::KMOVQkk;
4405 if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4406 return X86::KMOVDrk;
4407 if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4408 return X86::KMOVQrk;
4409 if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4410 return X86::KMOVDkr;
4411 if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4412 return X86::KMOVQkr;
4413 return 0;
4414}
4415
4416static
4417unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4418 const X86Subtarget &Subtarget)
4419{
4420 if (Subtarget.hasDQI())
4421 if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4422 return Opc;
4423 if (Subtarget.hasBWI())
4424 if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4425 return Opc;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4426 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
4427 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
4428 X86::VR512RegClass.contains(DestReg, SrcReg)) {
4429 DestReg = get512BitSuperRegister(DestReg);
4430 SrcReg = get512BitSuperRegister(SrcReg);
4431 return X86::VMOVAPSZrr;
4432 }
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4433 if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4434 return X86::KMOVWkk;
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4435 if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4436 SrcReg = getX86SubSuperRegister(SrcReg, 32);
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4437 return X86::KMOVWkr;
4438 }
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4439 if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
Craig Topper91dab7b2015-12-25 22:09:45 +0000[diff] [blame]4440 DestReg = getX86SubSuperRegister(DestReg, 32);
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4441 return X86::KMOVWrk;
4442 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4443 return 0;
4444}
4445
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4446void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
Benjamin Kramerbdc49562016-06-12 15:39:02 +0000[diff] [blame]4447 MachineBasicBlock::iterator MI,
4448 const DebugLoc &DL, unsigned DestReg,
4449 unsigned SrcReg, bool KillSrc) const {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4450 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4451 bool HasAVX = Subtarget.hasAVX();
4452 bool HasAVX512 = Subtarget.hasAVX512();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4453 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4454 if (X86::GR64RegClass.contains(DestReg, SrcReg))
4455 Opc = X86::MOV64rr;
4456 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4457 Opc = X86::MOV32rr;
4458 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4459 Opc = X86::MOV16rr;
4460 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4461 // Copying to or from a physical H register on x86-64 requires a NOREX
4462 // move. Otherwise use a normal move.
4463 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4464 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4465 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]4466 // Both operands must be encodable without an REX prefix.
4467 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4468 "8-bit H register can not be copied outside GR8_NOREX");
4469 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4470 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4471 }
4472 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4473 Opc = X86::MMX_MOVQ64rr;
4474 else if (HasAVX512)
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4475 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4476 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4477 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4478 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4479 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4480 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4481 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4482
4483 if (Opc) {
4484 BuildMI(MBB, MI, DL, get(Opc), DestReg)
4485 .addReg(SrcReg, getKillRegState(KillSrc));
4486 return;
4487 }
4488
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4489 bool FromEFLAGS = SrcReg == X86::EFLAGS;
4490 bool ToEFLAGS = DestReg == X86::EFLAGS;
4491 int Reg = FromEFLAGS ? DestReg : SrcReg;
4492 bool is32 = X86::GR32RegClass.contains(Reg);
4493 bool is64 = X86::GR64RegClass.contains(Reg);
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4494
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4495 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4496 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4497 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4498 int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4499 int Pop = is64 ? X86::POP64r : X86::POP32r;
4500 int PopF = is64 ? X86::POPF64 : X86::POPF32;
4501 int AX = is64 ? X86::RAX : X86::EAX;
4502
4503 if (!Subtarget.hasLAHFSAHF()) {
Hans Wennborg7036e502015-12-15 23:21:46 +0000[diff] [blame]4504 assert(Subtarget.is64Bit() &&
4505 "Not having LAHF/SAHF only happens on 64-bit.");
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4506 // Moving EFLAGS to / from another register requires a push and a pop.
4507 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemer33467632015-12-27 06:07:26 +0000[diff] [blame]4508 // first frame index. See X86FrameLowering.cpp - usesTheStack.
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4509 if (FromEFLAGS) {
4510 BuildMI(MBB, MI, DL, get(PushF));
4511 BuildMI(MBB, MI, DL, get(Pop), DestReg);
4512 }
4513 if (ToEFLAGS) {
4514 BuildMI(MBB, MI, DL, get(Push))
4515 .addReg(SrcReg, getKillRegState(KillSrc));
4516 BuildMI(MBB, MI, DL, get(PopF));
4517 }
4518 return;
4519 }
4520
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4521 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4522 // inefficient. Instead:
4523 // - Save the overflow flag OF into AL using SETO, and restore it using a
4524 // signed 8-bit addition of AL and INT8_MAX.
4525 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4526 // using LAHF/SAHF.
4527 // - When RAX/EAX is live and isn't the destination register, make sure it
4528 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4529 // the flags.
4530 // This approach is ~2.25x faster than using PUSHF/POPF.
4531 //
4532 // This is still somewhat inefficient because we don't know which flags are
4533 // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4534 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4535 //
4536 // PUSHF/POPF is also potentially incorrect because it affects other flags
4537 // such as TF/IF/DF, which LLVM doesn't model.
4538 //
4539 // Notice that we have to adjust the stack if we don't want to clobber the
David Majnemerca1c9f02016-01-04 04:49:41 +0000[diff] [blame]4540 // first frame index.
4541 // See X86ISelLowering.cpp - X86::hasCopyImplyingStackAdjustment.
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4542
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4543 const TargetRegisterInfo *TRI = &getRegisterInfo();
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4544 MachineBasicBlock::LivenessQueryResult LQR =
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4545 MBB.computeRegisterLiveness(TRI, AX, MI);
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4546 // We do not want to save and restore AX if we do not have to.
4547 // Moreover, if we do so whereas AX is dead, we would need to set
4548 // an undef flag on the use of AX, otherwise the verifier will
4549 // complain that we read an undef value.
4550 // We do not want to change the behavior of the machine verifier
4551 // as this is usually wrong to read an undef value.
4552 if (MachineBasicBlock::LQR_Unknown == LQR) {
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4553 LivePhysRegs LPR(TRI);
Matthias Braund1aabb22016-05-03 00:24:32 +0000[diff] [blame]4554 LPR.addLiveOuts(MBB);
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4555 MachineBasicBlock::iterator I = MBB.end();
4556 while (I != MI) {
4557 --I;
4558 LPR.stepBackward(*I);
4559 }
Quentin Colombet220f7da2016-05-10 20:49:46 +0000[diff] [blame]4560 // AX contains the top most register in the aliasing hierarchy.
4561 // It may not be live, but one of its aliases may be.
4562 for (MCRegAliasIterator AI(AX, TRI, true);
4563 AI.isValid() && LQR != MachineBasicBlock::LQR_Live; ++AI)
4564 LQR = LPR.contains(*AI) ? MachineBasicBlock::LQR_Live
4565 : MachineBasicBlock::LQR_Dead;
Matthias Braun60d69e22015-12-11 19:42:09 +0000[diff] [blame]4566 }
Quentin Colombet2b3a4e72016-04-26 23:14:32 +0000[diff] [blame]4567 bool AXDead = (Reg == AX) || (MachineBasicBlock::LQR_Dead == LQR);
4568 if (!AXDead)
4569 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4570 if (FromEFLAGS) {
4571 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4572 BuildMI(MBB, MI, DL, get(X86::LAHF));
4573 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4574 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4575 if (ToEFLAGS) {
4576 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4577 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4578 .addReg(X86::AL)
4579 .addImm(INT8_MAX);
4580 BuildMI(MBB, MI, DL, get(X86::SAHF));
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4581 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4582 if (!AXDead)
4583 BuildMI(MBB, MI, DL, get(Pop), AX);
4584 return;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4585 }
4586
4587 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4588 << " to " << RI.getName(DestReg) << '\n');
4589 llvm_unreachable("Cannot emit physreg copy instruction");
4590}
4591
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4592static unsigned getLoadStoreMaskRegOpcode(const TargetRegisterClass *RC,
4593 bool load) {
4594 switch (RC->getSize()) {
4595 default:
4596 llvm_unreachable("Unknown spill size");
4597 case 2:
4598 return load ? X86::KMOVWkm : X86::KMOVWmk;
4599 case 4:
4600 return load ? X86::KMOVDkm : X86::KMOVDmk;
4601 case 8:
4602 return load ? X86::KMOVQkm : X86::KMOVQmk;
4603 }
4604}
4605
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4606static unsigned getLoadStoreRegOpcode(unsigned Reg,
4607 const TargetRegisterClass *RC,
4608 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4609 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4610 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4611 if (STI.hasAVX512()) {
Igor Breger4dc7d392016-02-15 08:25:28 +0000[diff] [blame]4612 if (isMaskRegClass(RC))
4613 return getLoadStoreMaskRegOpcode(RC, load);
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4614 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4615 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4616 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4617 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4618 if (X86::VR512RegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4619 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4620 }
4621
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4622 bool HasAVX = STI.hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4623 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]4624 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4625 llvm_unreachable("Unknown spill size");
4626 case 1:
4627 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4628 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4629 // Copying to or from a physical H register on x86-64 requires a NOREX
4630 // move. Otherwise use a normal move.
4631 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4632 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4633 return load ? X86::MOV8rm : X86::MOV8mr;
4634 case 2:
4635 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4636 return load ? X86::MOV16rm : X86::MOV16mr;
4637 case 4:
4638 if (X86::GR32RegClass.hasSubClassEq(RC))
4639 return load ? X86::MOV32rm : X86::MOV32mr;
4640 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4641 return load ?
4642 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4643 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4644 if (X86::RFP32RegClass.hasSubClassEq(RC))
4645 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4646 llvm_unreachable("Unknown 4-byte regclass");
4647 case 8:
4648 if (X86::GR64RegClass.hasSubClassEq(RC))
4649 return load ? X86::MOV64rm : X86::MOV64mr;
4650 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4651 return load ?
4652 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4653 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4654 if (X86::VR64RegClass.hasSubClassEq(RC))
4655 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4656 if (X86::RFP64RegClass.hasSubClassEq(RC))
4657 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4658 llvm_unreachable("Unknown 8-byte regclass");
4659 case 10:
4660 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4661 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4662 case 16: {
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4663 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4664 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4665 // If stack is realigned we can use aligned stores.
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4666 if (X86::VR128RegClass.hasSubClassEq(RC)) {
4667 if (isStackAligned)
4668 return load ? (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm)
4669 : (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
4670 else
4671 return load ? (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm)
4672 : (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4673 }
Craig Topper3e0c0382016-05-10 05:28:04 +0000[diff] [blame]4674 assert(STI.hasVLX() && "Using extended register requires VLX");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4675 if (isStackAligned)
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4676 return load ? X86::VMOVAPSZ128rm : X86::VMOVAPSZ128mr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4677 else
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4678 return load ? X86::VMOVUPSZ128rm : X86::VMOVUPSZ128mr;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4679 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4680 case 32:
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4681 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4682 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4683 // If stack is realigned we can use aligned stores.
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4684 if (X86::VR256RegClass.hasSubClassEq(RC)) {
4685 if (isStackAligned)
4686 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4687 else
4688 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
4689 }
Craig Topper3e0c0382016-05-10 05:28:04 +0000[diff] [blame]4690 assert(STI.hasVLX() && "Using extended register requires VLX");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4691 if (isStackAligned)
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4692 return load ? X86::VMOVAPSZ256rm : X86::VMOVAPSZ256mr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4693 else
Quentin Colombetee5f36b2016-05-10 01:09:14 +0000[diff] [blame]4694 return load ? X86::VMOVUPSZ256rm : X86::VMOVUPSZ256mr;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4695 case 64:
4696 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
Craig Topper3e0c0382016-05-10 05:28:04 +0000[diff] [blame]4697 assert(STI.hasVLX() && "Using 512-bit register requires AVX512");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4698 if (isStackAligned)
4699 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4700 else
4701 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4702 }
4703}
4704
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4705bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr &MemOp, unsigned &BaseReg,
Chad Rosierc27a18f2016-03-09 16:00:35 +0000[diff] [blame]4706 int64_t &Offset,
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4707 const TargetRegisterInfo *TRI) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4708 const MCInstrDesc &Desc = MemOp.getDesc();
Craig Topper477649a2016-04-28 05:58:46 +0000[diff] [blame]4709 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4710 if (MemRefBegin < 0)
4711 return false;
4712
4713 MemRefBegin += X86II::getOperandBias(Desc);
4714
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4715 MachineOperand &BaseMO = MemOp.getOperand(MemRefBegin + X86::AddrBaseReg);
Sanjoy Das881de4d2016-02-02 02:32:43 +0000[diff] [blame]4716 if (!BaseMO.isReg()) // Can be an MO_FrameIndex
4717 return false;
4718
4719 BaseReg = BaseMO.getReg();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4720 if (MemOp.getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4721 return false;
4722
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4723 if (MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4724 X86::NoRegister)
4725 return false;
4726
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4727 const MachineOperand &DispMO = MemOp.getOperand(MemRefBegin + X86::AddrDisp);
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4728
4729 // Displacement can be symbolic
4730 if (!DispMO.isImm())
4731 return false;
4732
4733 Offset = DispMO.getImm();
4734
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4735 return MemOp.getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4736 X86::NoRegister;
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4737}
4738
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4739static unsigned getStoreRegOpcode(unsigned SrcReg,
4740 const TargetRegisterClass *RC,
4741 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4742 const X86Subtarget &STI) {
4743 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4744}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4745
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4746
4747static unsigned getLoadRegOpcode(unsigned DestReg,
4748 const TargetRegisterClass *RC,
4749 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4750 const X86Subtarget &STI) {
4751 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4752}
4753
4754void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4755 MachineBasicBlock::iterator MI,
4756 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4757 const TargetRegisterClass *RC,
4758 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4759 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]4760 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4761 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4762 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4763 bool isAligned =
4764 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4765 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4766 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4767 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4768 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4769 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4770}
4771
4772void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4773 bool isKill,
4774 SmallVectorImpl<MachineOperand> &Addr,
4775 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4776 MachineInstr::mmo_iterator MMOBegin,
4777 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4778 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4779 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4780 bool isAligned = MMOBegin != MMOEnd &&
4781 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4782 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4783 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4784 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4785 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4786 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4787 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4788 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4789 NewMIs.push_back(MIB);
4790}
4791
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4792
4793void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4794 MachineBasicBlock::iterator MI,
4795 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4796 const TargetRegisterClass *RC,
4797 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4798 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4799 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4800 bool isAligned =
4801 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4802 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4803 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4804 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4805 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4806}
4807
4808void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]4809 SmallVectorImpl<MachineOperand> &Addr,
4810 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4811 MachineInstr::mmo_iterator MMOBegin,
4812 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4813 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4814 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4815 bool isAligned = MMOBegin != MMOEnd &&
4816 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4817 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4818 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4819 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4820 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4821 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4822 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4823 NewMIs.push_back(MIB);
4824}
4825
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4826bool X86InstrInfo::analyzeCompare(const MachineInstr &MI, unsigned &SrcReg,
4827 unsigned &SrcReg2, int &CmpMask,
4828 int &CmpValue) const {
4829 switch (MI.getOpcode()) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4830 default: break;
4831 case X86::CMP64ri32:
4832 case X86::CMP64ri8:
4833 case X86::CMP32ri:
4834 case X86::CMP32ri8:
4835 case X86::CMP16ri:
4836 case X86::CMP16ri8:
4837 case X86::CMP8ri:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4838 SrcReg = MI.getOperand(0).getReg();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4839 SrcReg2 = 0;
4840 CmpMask = ~0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4841 CmpValue = MI.getOperand(1).getImm();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4842 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4843 // A SUB can be used to perform comparison.
4844 case X86::SUB64rm:
4845 case X86::SUB32rm:
4846 case X86::SUB16rm:
4847 case X86::SUB8rm:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4848 SrcReg = MI.getOperand(1).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4849 SrcReg2 = 0;
4850 CmpMask = ~0;
4851 CmpValue = 0;
4852 return true;
4853 case X86::SUB64rr:
4854 case X86::SUB32rr:
4855 case X86::SUB16rr:
4856 case X86::SUB8rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4857 SrcReg = MI.getOperand(1).getReg();
4858 SrcReg2 = MI.getOperand(2).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4859 CmpMask = ~0;
4860 CmpValue = 0;
4861 return true;
4862 case X86::SUB64ri32:
4863 case X86::SUB64ri8:
4864 case X86::SUB32ri:
4865 case X86::SUB32ri8:
4866 case X86::SUB16ri:
4867 case X86::SUB16ri8:
4868 case X86::SUB8ri:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4869 SrcReg = MI.getOperand(1).getReg();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4870 SrcReg2 = 0;
4871 CmpMask = ~0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4872 CmpValue = MI.getOperand(2).getImm();
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4873 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4874 case X86::CMP64rr:
4875 case X86::CMP32rr:
4876 case X86::CMP16rr:
4877 case X86::CMP8rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4878 SrcReg = MI.getOperand(0).getReg();
4879 SrcReg2 = MI.getOperand(1).getReg();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4880 CmpMask = ~0;
4881 CmpValue = 0;
4882 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4883 case X86::TEST8rr:
4884 case X86::TEST16rr:
4885 case X86::TEST32rr:
4886 case X86::TEST64rr:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4887 SrcReg = MI.getOperand(0).getReg();
4888 if (MI.getOperand(1).getReg() != SrcReg)
4889 return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4890 // Compare against zero.
4891 SrcReg2 = 0;
4892 CmpMask = ~0;
4893 CmpValue = 0;
4894 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4895 }
4896 return false;
4897}
4898
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4899/// Check whether the first instruction, whose only
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4900/// purpose is to update flags, can be made redundant.
4901/// CMPrr can be made redundant by SUBrr if the operands are the same.
4902/// This function can be extended later on.
4903/// SrcReg, SrcRegs: register operands for FlagI.
4904/// ImmValue: immediate for FlagI if it takes an immediate.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4905inline static bool isRedundantFlagInstr(MachineInstr &FlagI, unsigned SrcReg,
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4906 unsigned SrcReg2, int ImmValue,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4907 MachineInstr &OI) {
4908 if (((FlagI.getOpcode() == X86::CMP64rr && OI.getOpcode() == X86::SUB64rr) ||
4909 (FlagI.getOpcode() == X86::CMP32rr && OI.getOpcode() == X86::SUB32rr) ||
4910 (FlagI.getOpcode() == X86::CMP16rr && OI.getOpcode() == X86::SUB16rr) ||
4911 (FlagI.getOpcode() == X86::CMP8rr && OI.getOpcode() == X86::SUB8rr)) &&
4912 ((OI.getOperand(1).getReg() == SrcReg &&
4913 OI.getOperand(2).getReg() == SrcReg2) ||
4914 (OI.getOperand(1).getReg() == SrcReg2 &&
4915 OI.getOperand(2).getReg() == SrcReg)))
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4916 return true;
4917
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4918 if (((FlagI.getOpcode() == X86::CMP64ri32 &&
4919 OI.getOpcode() == X86::SUB64ri32) ||
4920 (FlagI.getOpcode() == X86::CMP64ri8 &&
4921 OI.getOpcode() == X86::SUB64ri8) ||
4922 (FlagI.getOpcode() == X86::CMP32ri && OI.getOpcode() == X86::SUB32ri) ||
4923 (FlagI.getOpcode() == X86::CMP32ri8 &&
4924 OI.getOpcode() == X86::SUB32ri8) ||
4925 (FlagI.getOpcode() == X86::CMP16ri && OI.getOpcode() == X86::SUB16ri) ||
4926 (FlagI.getOpcode() == X86::CMP16ri8 &&
4927 OI.getOpcode() == X86::SUB16ri8) ||
4928 (FlagI.getOpcode() == X86::CMP8ri && OI.getOpcode() == X86::SUB8ri)) &&
4929 OI.getOperand(1).getReg() == SrcReg &&
4930 OI.getOperand(2).getImm() == ImmValue)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4931 return true;
4932 return false;
4933}
4934
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4935/// Check whether the definition can be converted
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4936/// to remove a comparison against zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]4937inline static bool isDefConvertible(MachineInstr &MI) {
4938 switch (MI.getOpcode()) {
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4939 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]4940
4941 // The shift instructions only modify ZF if their shift count is non-zero.
4942 // N.B.: The processor truncates the shift count depending on the encoding.
4943 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
4944 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
4945 return getTruncatedShiftCount(MI, 2) != 0;
4946
4947 // Some left shift instructions can be turned into LEA instructions but only
4948 // if their flags aren't used. Avoid transforming such instructions.
4949 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
4950 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4951 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4952 return ShAmt != 0;
4953 }
4954
4955 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4956 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4957 return getTruncatedShiftCount(MI, 3) != 0;
4958
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4959 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4960 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
4961 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
4962 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
4963 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4964 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4965 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4966 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
4967 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
4968 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
4969 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4970 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4971 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4972 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
4973 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
4974 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
4975 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
4976 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4977 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
4978 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
4979 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
4980 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
4981 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
4982 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
4983 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
4984 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
4985 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4986 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4987 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4988 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4989 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
4990 case X86::ADC32ri: case X86::ADC32ri8:
4991 case X86::ADC32rr: case X86::ADC64ri32:
4992 case X86::ADC64ri8: case X86::ADC64rr:
4993 case X86::SBB32ri: case X86::SBB32ri8:
4994 case X86::SBB32rr: case X86::SBB64ri32:
4995 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]4996 case X86::ANDN32rr: case X86::ANDN32rm:
4997 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4998 case X86::BEXTR32rr: case X86::BEXTR64rr:
4999 case X86::BEXTR32rm: case X86::BEXTR64rm:
5000 case X86::BLSI32rr: case X86::BLSI32rm:
5001 case X86::BLSI64rr: case X86::BLSI64rm:
5002 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
5003 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
5004 case X86::BLSR32rr: case X86::BLSR32rm:
5005 case X86::BLSR64rr: case X86::BLSR64rm:
5006 case X86::BZHI32rr: case X86::BZHI32rm:
5007 case X86::BZHI64rr: case X86::BZHI64rm:
5008 case X86::LZCNT16rr: case X86::LZCNT16rm:
5009 case X86::LZCNT32rr: case X86::LZCNT32rm:
5010 case X86::LZCNT64rr: case X86::LZCNT64rm:
5011 case X86::POPCNT16rr:case X86::POPCNT16rm:
5012 case X86::POPCNT32rr:case X86::POPCNT32rm:
5013 case X86::POPCNT64rr:case X86::POPCNT64rm:
5014 case X86::TZCNT16rr: case X86::TZCNT16rm:
5015 case X86::TZCNT32rr: case X86::TZCNT32rm:
5016 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5017 return true;
5018 }
5019}
5020
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5021/// Check whether the use can be converted to remove a comparison against zero.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5022static X86::CondCode isUseDefConvertible(MachineInstr &MI) {
5023 switch (MI.getOpcode()) {
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5024 default: return X86::COND_INVALID;
5025 case X86::LZCNT16rr: case X86::LZCNT16rm:
5026 case X86::LZCNT32rr: case X86::LZCNT32rm:
5027 case X86::LZCNT64rr: case X86::LZCNT64rm:
5028 return X86::COND_B;
5029 case X86::POPCNT16rr:case X86::POPCNT16rm:
5030 case X86::POPCNT32rr:case X86::POPCNT32rm:
5031 case X86::POPCNT64rr:case X86::POPCNT64rm:
5032 return X86::COND_E;
5033 case X86::TZCNT16rr: case X86::TZCNT16rm:
5034 case X86::TZCNT32rr: case X86::TZCNT32rm:
5035 case X86::TZCNT64rr: case X86::TZCNT64rm:
5036 return X86::COND_B;
5037 }
5038}
5039
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5040/// Check if there exists an earlier instruction that
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5041/// operates on the same source operands and sets flags in the same way as
5042/// Compare; remove Compare if possible.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5043bool X86InstrInfo::optimizeCompareInstr(MachineInstr &CmpInstr, unsigned SrcReg,
5044 unsigned SrcReg2, int CmpMask,
5045 int CmpValue,
5046 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5047 // Check whether we can replace SUB with CMP.
5048 unsigned NewOpcode = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5049 switch (CmpInstr.getOpcode()) {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5050 default: break;
5051 case X86::SUB64ri32:
5052 case X86::SUB64ri8:
5053 case X86::SUB32ri:
5054 case X86::SUB32ri8:
5055 case X86::SUB16ri:
5056 case X86::SUB16ri8:
5057 case X86::SUB8ri:
5058 case X86::SUB64rm:
5059 case X86::SUB32rm:
5060 case X86::SUB16rm:
5061 case X86::SUB8rm:
5062 case X86::SUB64rr:
5063 case X86::SUB32rr:
5064 case X86::SUB16rr:
5065 case X86::SUB8rr: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5066 if (!MRI->use_nodbg_empty(CmpInstr.getOperand(0).getReg()))
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5067 return false;
5068 // There is no use of the destination register, we can replace SUB with CMP.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5069 switch (CmpInstr.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]5070 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5071 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
5072 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
5073 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
5074 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
5075 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
5076 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
5077 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
5078 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
5079 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
5080 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
5081 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
5082 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
5083 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
5084 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
5085 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
5086 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5087 CmpInstr.setDesc(get(NewOpcode));
5088 CmpInstr.RemoveOperand(0);
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]5089 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
5090 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
5091 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
5092 return false;
5093 }
5094 }
5095
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5096 // Get the unique definition of SrcReg.
5097 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
5098 if (!MI) return false;
5099
5100 // CmpInstr is the first instruction of the BB.
5101 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
5102
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5103 // If we are comparing against zero, check whether we can use MI to update
5104 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
5105 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5106 if (IsCmpZero && MI->getParent() != CmpInstr.getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5107 return false;
5108
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5109 // If we have a use of the source register between the def and our compare
5110 // instruction we can eliminate the compare iff the use sets EFLAGS in the
5111 // right way.
5112 bool ShouldUpdateCC = false;
5113 X86::CondCode NewCC = X86::COND_INVALID;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5114 if (IsCmpZero && !isDefConvertible(*MI)) {
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5115 // Scan forward from the use until we hit the use we're looking for or the
5116 // compare instruction.
5117 for (MachineBasicBlock::iterator J = MI;; ++J) {
5118 // Do we have a convertible instruction?
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5119 NewCC = isUseDefConvertible(*J);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5120 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
5121 J->getOperand(1).getReg() == SrcReg) {
5122 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5123 ShouldUpdateCC = true; // Update CC later on.
5124 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5125 // with the new def.
5126 MI = Def = J;
5127 break;
5128 }
5129
5130 if (J == I)
5131 return false;
5132 }
5133 }
5134
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5135 // We are searching for an earlier instruction that can make CmpInstr
5136 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5137 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5138 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5139
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5140 // We iterate backward, starting from the instruction before CmpInstr and
5141 // stop when reaching the definition of a source register or done with the BB.
5142 // RI points to the instruction before CmpInstr.
5143 // If the definition is in this basic block, RE points to the definition;
5144 // otherwise, RE is the rend of the basic block.
5145 MachineBasicBlock::reverse_iterator
5146 RI = MachineBasicBlock::reverse_iterator(I),
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5147 RE = CmpInstr.getParent() == MI->getParent()
5148 ? MachineBasicBlock::reverse_iterator(++Def) /* points to MI */
5149 : CmpInstr.getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5150 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5151 for (; RI != RE; ++RI) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5152 MachineInstr &Instr = *RI;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5153 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5154 if (!IsCmpZero &&
5155 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5156 Sub = &Instr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5157 break;
5158 }
5159
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5160 if (Instr.modifiesRegister(X86::EFLAGS, TRI) ||
5161 Instr.readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5162 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5163
5164 // MOV32r0 etc. are implemented with xor which clobbers condition code.
5165 // They are safe to move up, if the definition to EFLAGS is dead and
5166 // earlier instructions do not read or write EFLAGS.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5167 if (!Movr0Inst && Instr.getOpcode() == X86::MOV32r0 &&
5168 Instr.registerDefIsDead(X86::EFLAGS, TRI)) {
5169 Movr0Inst = &Instr;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5170 continue;
5171 }
5172
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5173 // We can't remove CmpInstr.
5174 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5175 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5176 }
5177
5178 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5179 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5180 return false;
5181
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5182 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5183 Sub->getOperand(2).getReg() == SrcReg);
5184
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5185 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5186 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5187 // If we are done with the basic block, we need to check whether EFLAGS is
5188 // live-out.
5189 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5190 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5191 MachineBasicBlock::iterator E = CmpInstr.getParent()->end();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5192 for (++I; I != E; ++I) {
5193 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5194 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5195 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5196 // We should check the usage if this instruction uses and updates EFLAGS.
5197 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5198 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5199 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5200 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5201 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5202 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5203 continue;
5204
5205 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]5206 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5207 bool OpcIsSET = false;
5208 if (IsCmpZero || IsSwapped) {
5209 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5210 if (Instr.isBranch())
5211 OldCC = getCondFromBranchOpc(Instr.getOpcode());
5212 else {
5213 OldCC = getCondFromSETOpc(Instr.getOpcode());
5214 if (OldCC != X86::COND_INVALID)
5215 OpcIsSET = true;
5216 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]5217 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5218 }
5219 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5220 }
5221 if (IsCmpZero) {
5222 switch (OldCC) {
5223 default: break;
5224 case X86::COND_A: case X86::COND_AE:
5225 case X86::COND_B: case X86::COND_BE:
5226 case X86::COND_G: case X86::COND_GE:
5227 case X86::COND_L: case X86::COND_LE:
5228 case X86::COND_O: case X86::COND_NO:
5229 // CF and OF are used, we can't perform this optimization.
5230 return false;
5231 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5232
5233 // If we're updating the condition code check if we have to reverse the
5234 // condition.
5235 if (ShouldUpdateCC)
5236 switch (OldCC) {
5237 default:
5238 return false;
5239 case X86::COND_E:
5240 break;
5241 case X86::COND_NE:
5242 NewCC = GetOppositeBranchCondition(NewCC);
5243 break;
5244 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5245 } else if (IsSwapped) {
5246 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5247 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5248 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5249 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5250 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5251 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5252
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5253 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5254 // Synthesize the new opcode.
5255 bool HasMemoryOperand = Instr.hasOneMemOperand();
5256 unsigned NewOpc;
5257 if (Instr.isBranch())
5258 NewOpc = GetCondBranchFromCond(NewCC);
5259 else if(OpcIsSET)
5260 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5261 else {
5262 unsigned DstReg = Instr.getOperand(0).getReg();
5263 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5264 HasMemoryOperand);
5265 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5266
5267 // Push the MachineInstr to OpsToUpdate.
5268 // If it is safe to remove CmpInstr, the condition code of these
5269 // instructions will be modified.
5270 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5271 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5272 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5273 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5274 IsSafe = true;
5275 break;
5276 }
5277 }
5278
5279 // If EFLAGS is not killed nor re-defined, we should check whether it is
5280 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5281 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5282 MachineBasicBlock *MBB = CmpInstr.getParent();
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5283 for (MachineBasicBlock *Successor : MBB->successors())
5284 if (Successor->isLiveIn(X86::EFLAGS))
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5285 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5286 }
5287
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5288 // The instruction to be updated is either Sub or MI.
5289 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5290 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5291 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5292 // Look backwards until we find a def that doesn't use the current EFLAGS.
5293 Def = Sub;
5294 MachineBasicBlock::reverse_iterator
5295 InsertI = MachineBasicBlock::reverse_iterator(++Def),
5296 InsertE = Sub->getParent()->rend();
5297 for (; InsertI != InsertE; ++InsertI) {
5298 MachineInstr *Instr = &*InsertI;
5299 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5300 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5301 Sub->getParent()->remove(Movr0Inst);
5302 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5303 Movr0Inst);
5304 break;
5305 }
5306 }
5307 if (InsertI == InsertE)
5308 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5309 }
5310
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]5311 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5312 unsigned i = 0, e = Sub->getNumOperands();
5313 for (; i != e; ++i) {
5314 MachineOperand &MO = Sub->getOperand(i);
5315 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5316 MO.setIsDead(false);
5317 break;
5318 }
5319 }
5320 assert(i != e && "Unable to locate a def EFLAGS operand");
5321
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5322 CmpInstr.eraseFromParent();
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5323
5324 // Modify the condition code of instructions in OpsToUpdate.
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]5325 for (auto &Op : OpsToUpdate)
5326 Op.first->setDesc(get(Op.second));
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5327 return true;
5328}
5329
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5330/// Try to remove the load by folding it to a register
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5331/// operand at the use. We fold the load instructions if load defines a virtual
5332/// register, the virtual register is used once in the same BB, and the
5333/// instructions in-between do not load or store, and have no side effects.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5334MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr &MI,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5335 const MachineRegisterInfo *MRI,
5336 unsigned &FoldAsLoadDefReg,
5337 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5338 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5339 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5340 // To be conservative, if there exists another load, clear the load candidate.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5341 if (MI.mayLoad()) {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5342 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5343 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5344 }
5345
5346 // Check whether we can move DefMI here.
5347 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5348 assert(DefMI);
5349 bool SawStore = false;
Matthias Braun07066cc2015-05-19 21:22:20 +0000[diff] [blame]5350 if (!DefMI->isSafeToMove(nullptr, SawStore))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5351 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5352
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5353 // Collect information about virtual register operands of MI.
5354 unsigned SrcOperandId = 0;
5355 bool FoundSrcOperand = false;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5356 for (unsigned i = 0, e = MI.getDesc().getNumOperands(); i != e; ++i) {
5357 MachineOperand &MO = MI.getOperand(i);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5358 if (!MO.isReg())
5359 continue;
5360 unsigned Reg = MO.getReg();
5361 if (Reg != FoldAsLoadDefReg)
5362 continue;
5363 // Do not fold if we have a subreg use or a def or multiple uses.
5364 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5365 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5366
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5367 SrcOperandId = i;
5368 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5369 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5370 if (!FoundSrcOperand)
5371 return nullptr;
5372
5373 // Check whether we can fold the def into SrcOperandId.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5374 if (MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, *DefMI)) {
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5375 FoldAsLoadDefReg = 0;
5376 return FoldMI;
5377 }
5378
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5379 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5380}
5381
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5382/// Expand a single-def pseudo instruction to a two-addr
5383/// instruction with two undef reads of the register being defined.
5384/// This is used for mapping:
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5385/// %xmm4 = V_SET0
5386/// to:
5387/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5388///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5389static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5390 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5391 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5392 unsigned Reg = MIB->getOperand(0).getReg();
5393 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5394
5395 // MachineInstr::addOperand() will insert explicit operands before any
5396 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5397 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5398 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5399 assert(MIB->getOperand(1).getReg() == Reg &&
5400 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5401 return true;
5402}
5403
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5404/// Expand a single-def pseudo instruction to a two-addr
5405/// instruction with two %k0 reads.
5406/// This is used for mapping:
5407/// %k4 = K_SET1
5408/// to:
5409/// %k4 = KXNORrr %k0, %k0
5410static bool Expand2AddrKreg(MachineInstrBuilder &MIB,
5411 const MCInstrDesc &Desc, unsigned Reg) {
5412 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
5413 MIB->setDesc(Desc);
5414 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5415 return true;
5416}
5417
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5418static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5419 bool MinusOne) {
5420 MachineBasicBlock &MBB = *MIB->getParent();
5421 DebugLoc DL = MIB->getDebugLoc();
5422 unsigned Reg = MIB->getOperand(0).getReg();
5423
5424 // Insert the XOR.
5425 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5426 .addReg(Reg, RegState::Undef)
5427 .addReg(Reg, RegState::Undef);
5428
5429 // Turn the pseudo into an INC or DEC.
5430 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5431 MIB.addReg(Reg);
5432
5433 return true;
5434}
5435
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5436bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5437 MachineBasicBlock &MBB = *MIB->getParent();
5438 DebugLoc DL = MIB->getDebugLoc();
5439 int64_t Imm = MIB->getOperand(1).getImm();
5440 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5441 MachineBasicBlock::iterator I = MIB.getInstr();
5442
5443 int StackAdjustment;
5444
5445 if (Subtarget.is64Bit()) {
5446 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5447 MIB->getOpcode() == X86::MOV32ImmSExti8);
5448
5449 // Can't use push/pop lowering if the function might write to the red zone.
5450 X86MachineFunctionInfo *X86FI =
5451 MBB.getParent()->getInfo<X86MachineFunctionInfo>();
5452 if (X86FI->getUsesRedZone()) {
5453 MIB->setDesc(get(MIB->getOpcode() == X86::MOV32ImmSExti8 ? X86::MOV32ri
5454 : X86::MOV64ri));
5455 return true;
5456 }
5457
5458 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5459 // widen the register if necessary.
5460 StackAdjustment = 8;
5461 BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5462 MIB->setDesc(get(X86::POP64r));
5463 MIB->getOperand(0)
5464 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), 64));
5465 } else {
5466 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5467 StackAdjustment = 4;
5468 BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5469 MIB->setDesc(get(X86::POP32r));
5470 }
5471
5472 // Build CFI if necessary.
5473 MachineFunction &MF = *MBB.getParent();
5474 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5475 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5476 bool NeedsDwarfCFI =
5477 !IsWin64Prologue &&
5478 (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5479 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5480 if (EmitCFI) {
5481 TFL->BuildCFI(MBB, I, DL,
5482 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5483 TFL->BuildCFI(MBB, std::next(I), DL,
5484 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5485 }
5486
5487 return true;
5488}
5489
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5490// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5491// code sequence is needed for other targets.
5492static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5493 const TargetInstrInfo &TII) {
5494 MachineBasicBlock &MBB = *MIB->getParent();
5495 DebugLoc DL = MIB->getDebugLoc();
5496 unsigned Reg = MIB->getOperand(0).getReg();
5497 const GlobalValue *GV =
5498 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
5499 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]5500 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
5501 MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]5502 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5503
5504 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5505 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5506 .addMemOperand(MMO);
5507 MIB->setDebugLoc(DL);
5508 MIB->setDesc(TII.get(X86::MOV64rm));
5509 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5510}
5511
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5512bool X86InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5513 bool HasAVX = Subtarget.hasAVX();
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5514 MachineInstrBuilder MIB(*MI.getParent()->getParent(), MI);
5515 switch (MI.getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]5516 case X86::MOV32r0:
5517 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5518 case X86::MOV32r1:
5519 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5520 case X86::MOV32r_1:
5521 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
Hans Wennborg4ae51192016-03-25 01:10:56 +0000[diff] [blame]5522 case X86::MOV32ImmSExti8:
5523 case X86::MOV64ImmSExti8:
5524 return ExpandMOVImmSExti8(MIB);
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5525 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5526 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5527 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5528 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5529 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5530 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5531 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5532 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5533 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5534 case X86::FsFLD0SS:
5535 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5536 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5537 case X86::AVX_SET0:
5538 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5539 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Craig Toppere5ce84a2016-05-08 21:33:53 +0000[diff] [blame]5540 case X86::AVX512_128_SET0:
5541 return Expand2AddrUndef(MIB, get(X86::VPXORDZ128rr));
5542 case X86::AVX512_256_SET0:
5543 return Expand2AddrUndef(MIB, get(X86::VPXORDZ256rr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5544 case X86::AVX512_512_SET0:
5545 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5546 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5547 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5548 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5549 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5550 case X86::TEST8ri_NOREX:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5551 MI.setDesc(get(X86::TEST8ri));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5552 return true;
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5553 case X86::MOV32ri64:
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5554 MI.setDesc(get(X86::MOV32ri));
Craig Toppere00bffb2016-01-05 07:44:14 +0000[diff] [blame]5555 return true;
5556
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5557 // KNL does not recognize dependency-breaking idioms for mask registers,
5558 // so kxnor %k1, %k1, %k2 has a RAW dependence on %k1.
5559 // Using %k0 as the undef input register is a performance heuristic based
5560 // on the assumption that %k0 is used less frequently than the other mask
5561 // registers, since it is not usable as a write mask.
5562 // FIXME: A more advanced approach would be to choose the best input mask
5563 // register based on context.
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]5564 case X86::KSET0B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5565 case X86::KSET0W: return Expand2AddrKreg(MIB, get(X86::KXORWrr), X86::K0);
5566 case X86::KSET0D: return Expand2AddrKreg(MIB, get(X86::KXORDrr), X86::K0);
5567 case X86::KSET0Q: return Expand2AddrKreg(MIB, get(X86::KXORQrr), X86::K0);
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5568 case X86::KSET1B:
Elena Demikhovsky9e225a22015-12-24 08:12:22 +0000[diff] [blame]5569 case X86::KSET1W: return Expand2AddrKreg(MIB, get(X86::KXNORWrr), X86::K0);
5570 case X86::KSET1D: return Expand2AddrKreg(MIB, get(X86::KXNORDrr), X86::K0);
5571 case X86::KSET1Q: return Expand2AddrKreg(MIB, get(X86::KXNORQrr), X86::K0);
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5572 case TargetOpcode::LOAD_STACK_GUARD:
5573 expandLoadStackGuard(MIB, *this);
5574 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5575 }
5576 return false;
5577}
5578
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5579static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5580 int PtrOffset = 0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5581 unsigned NumAddrOps = MOs.size();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5582
5583 if (NumAddrOps < 4) {
5584 // FrameIndex only - add an immediate offset (whether its zero or not).
5585 for (unsigned i = 0; i != NumAddrOps; ++i)
5586 MIB.addOperand(MOs[i]);
5587 addOffset(MIB, PtrOffset);
5588 } else {
5589 // General Memory Addressing - we need to add any offset to an existing
5590 // offset.
5591 assert(MOs.size() == 5 && "Unexpected memory operand list length");
5592 for (unsigned i = 0; i != NumAddrOps; ++i) {
5593 const MachineOperand &MO = MOs[i];
5594 if (i == 3 && PtrOffset != 0) {
Simon Pilgrimae0140d2015-11-19 21:50:57 +0000[diff] [blame]5595 MIB.addDisp(MO, PtrOffset);
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5596 } else {
5597 MIB.addOperand(MO);
5598 }
5599 }
5600 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5601}
5602
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]5603static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5604 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5605 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5606 MachineInstr &MI,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]5607 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5608 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5609 // Omit the implicit operands, something BuildMI can't do.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5610 MachineInstr *NewMI =
5611 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5612 MachineInstrBuilder MIB(MF, NewMI);
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5613 addOperands(MIB, MOs);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5614
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5615 // Loop over the rest of the ri operands, converting them over.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5616 unsigned NumOps = MI.getDesc().getNumOperands() - 2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5617 for (unsigned i = 0; i != NumOps; ++i) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5618 MachineOperand &MO = MI.getOperand(i + 2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5619 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5620 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5621 for (unsigned i = NumOps + 2, e = MI.getNumOperands(); i != e; ++i) {
5622 MachineOperand &MO = MI.getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5623 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5624 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5625
5626 MachineBasicBlock *MBB = InsertPt->getParent();
5627 MBB->insert(InsertPt, NewMI);
5628
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5629 return MIB;
5630}
5631
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5632static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5633 unsigned OpNo, ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5634 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5635 MachineInstr &MI, const TargetInstrInfo &TII,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5636 int PtrOffset = 0) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5637 // Omit the implicit operands, something BuildMI can't do.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5638 MachineInstr *NewMI =
5639 MF.CreateMachineInstr(TII.get(Opcode), MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5640 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5641
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5642 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
5643 MachineOperand &MO = MI.getOperand(i);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5644 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5645 assert(MO.isReg() && "Expected to fold into reg operand!");
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5646 addOperands(MIB, MOs, PtrOffset);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5647 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5648 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5649 }
5650 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5651
5652 MachineBasicBlock *MBB = InsertPt->getParent();
5653 MBB->insert(InsertPt, NewMI);
5654
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5655 return MIB;
5656}
5657
5658static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5659 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5660 MachineBasicBlock::iterator InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5661 MachineInstr &MI) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5662 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5663 MI.getDebugLoc(), TII.get(Opcode));
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5664 addOperands(MIB, MOs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5665 return MIB.addImm(0);
5666}
5667
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5668MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5669 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5670 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5671 unsigned Size, unsigned Align) const {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5672 switch (MI.getOpcode()) {
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5673 case X86::INSERTPSrr:
5674 case X86::VINSERTPSrr:
5675 // Attempt to convert the load of inserted vector into a fold load
5676 // of a single float.
5677 if (OpNum == 2) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5678 unsigned Imm = MI.getOperand(MI.getNumOperands() - 1).getImm();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5679 unsigned ZMask = Imm & 15;
5680 unsigned DstIdx = (Imm >> 4) & 3;
5681 unsigned SrcIdx = (Imm >> 6) & 3;
5682
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5683 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5684 if (Size <= RCSize && 4 <= Align) {
5685 int PtrOffset = SrcIdx * 4;
5686 unsigned NewImm = (DstIdx << 4) | ZMask;
5687 unsigned NewOpCode =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5688 (MI.getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
5689 : X86::INSERTPSrm);
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5690 MachineInstr *NewMI =
5691 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5692 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5693 return NewMI;
5694 }
5695 }
5696 break;
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5697 case X86::MOVHLPSrr:
5698 case X86::VMOVHLPSrr:
5699 // Move the upper 64-bits of the second operand to the lower 64-bits.
5700 // To fold the load, adjust the pointer to the upper and use (V)MOVLPS.
5701 // TODO: In most cases AVX doesn't have a 8-byte alignment requirement.
5702 if (OpNum == 2) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5703 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5704 if (Size <= RCSize && 8 <= Align) {
5705 unsigned NewOpCode =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5706 (MI.getOpcode() == X86::VMOVHLPSrr ? X86::VMOVLPSrm
5707 : X86::MOVLPSrm);
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5708 MachineInstr *NewMI =
5709 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, 8);
5710 return NewMI;
5711 }
5712 }
5713 break;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5714 };
5715
5716 return nullptr;
5717}
5718
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5719MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5720 MachineFunction &MF, MachineInstr &MI, unsigned OpNum,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5721 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5722 unsigned Size, unsigned Align, bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5723 const DenseMap<unsigned,
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]5724 std::pair<uint16_t, uint16_t> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5725 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5726 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5727
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]5728 // For CPUs that favor the register form of a call or push,
5729 // do not fold loads into calls or pushes, unless optimizing for size
5730 // aggressively.
Sanjay Patel924879a2015-08-04 15:49:57 +0000[diff] [blame]5731 if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5732 (MI.getOpcode() == X86::CALL32r || MI.getOpcode() == X86::CALL64r ||
5733 MI.getOpcode() == X86::PUSH16r || MI.getOpcode() == X86::PUSH32r ||
5734 MI.getOpcode() == X86::PUSH64r))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5735 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5736
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5737 unsigned NumOps = MI.getDesc().getNumOperands();
5738 bool isTwoAddr =
5739 NumOps > 1 && MI.getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5740
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5741 // FIXME: AsmPrinter doesn't know how to handle
5742 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5743 if (MI.getOpcode() == X86::ADD32ri &&
5744 MI.getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5745 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5746
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5747 MachineInstr *NewMI = nullptr;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5748
5749 // Attempt to fold any custom cases we have.
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5750 if (MachineInstr *CustomMI =
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5751 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5752 return CustomMI;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5753
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5754 // Folding a memory location into the two-address part of a two-address
5755 // instruction is different than folding it other places. It requires
5756 // replacing the *two* registers with the memory location.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5757 if (isTwoAddr && NumOps >= 2 && OpNum < 2 && MI.getOperand(0).isReg() &&
5758 MI.getOperand(1).isReg() &&
5759 MI.getOperand(0).getReg() == MI.getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5760 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5761 isTwoAddrFold = true;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5762 } else if (OpNum == 0) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5763 if (MI.getOpcode() == X86::MOV32r0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5764 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5765 if (NewMI)
5766 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]5767 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5768
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5769 OpcodeTablePtr = &RegOp2MemOpTable0;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5770 } else if (OpNum == 1) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5771 OpcodeTablePtr = &RegOp2MemOpTable1;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5772 } else if (OpNum == 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5773 OpcodeTablePtr = &RegOp2MemOpTable2;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5774 } else if (OpNum == 3) {
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]5775 OpcodeTablePtr = &RegOp2MemOpTable3;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5776 } else if (OpNum == 4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]5777 OpcodeTablePtr = &RegOp2MemOpTable4;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5778 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5779
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5780 // If table selected...
5781 if (OpcodeTablePtr) {
5782 // Find the Opcode to fuse
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5783 auto I = OpcodeTablePtr->find(MI.getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5784 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5785 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5786 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]5787 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5788 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5789 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5790 if (Size) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5791 unsigned RCSize = getRegClass(MI.getDesc(), OpNum, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5792 if (Size < RCSize) {
5793 // Check if it's safe to fold the load. If the size of the object is
5794 // narrower than the load width, then it's not.
5795 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5796 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5797 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5798 // a 32-bit load which is implicitly zero-extended. This likely is
5799 // due to live interval analysis remat'ing a load from stack slot.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5800 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5801 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5802 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5803 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5804 }
5805 }
5806
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5807 if (isTwoAddrFold)
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5808 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5809 else
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5810 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5811
5812 if (NarrowToMOV32rm) {
5813 // If this is the special case where we use a MOV32rm to load a 32-bit
5814 // value and zero-extend the top bits. Change the destination register
5815 // to a 32-bit one.
5816 unsigned DstReg = NewMI->getOperand(0).getReg();
5817 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5818 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5819 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]5820 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5821 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5822 return NewMI;
5823 }
5824 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5825
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5826 // If the instruction and target operand are commutable, commute the
5827 // instruction and try again.
5828 if (AllowCommute) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5829 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5830 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5831 bool HasDef = MI.getDesc().getNumDefs();
5832 unsigned Reg0 = HasDef ? MI.getOperand(0).getReg() : 0;
5833 unsigned Reg1 = MI.getOperand(CommuteOpIdx1).getReg();
5834 unsigned Reg2 = MI.getOperand(CommuteOpIdx2).getReg();
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5835 bool Tied1 =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5836 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5837 bool Tied2 =
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5838 0 == MI.getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5839
5840 // If either of the commutable operands are tied to the destination
5841 // then we can not commute + fold.
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5842 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5843 (HasDef && Reg0 == Reg2 && Tied2))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5844 return nullptr;
5845
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5846 MachineInstr *CommutedMI =
5847 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5848 if (!CommutedMI) {
5849 // Unable to commute.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5850 return nullptr;
5851 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5852 if (CommutedMI != &MI) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5853 // New instruction. We can't fold from this.
5854 CommutedMI->eraseFromParent();
5855 return nullptr;
5856 }
5857
5858 // Attempt to fold with the commuted version of the instruction.
5859 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5860 Size, Align, /*AllowCommute=*/false);
5861 if (NewMI)
5862 return NewMI;
5863
5864 // Folding failed again - undo the commute before returning.
5865 MachineInstr *UncommutedMI =
5866 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5867 if (!UncommutedMI) {
5868 // Unable to commute.
5869 return nullptr;
5870 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5871 if (UncommutedMI != &MI) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5872 // New instruction. It doesn't need to be kept.
5873 UncommutedMI->eraseFromParent();
5874 return nullptr;
5875 }
5876
5877 // Return here to prevent duplicate fuse failure report.
5878 return nullptr;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5879 }
5880 }
5881
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5882 // No fusion
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5883 if (PrintFailedFusing && !MI.isCopy())
5884 dbgs() << "We failed to fuse operand " << OpNum << " in " << MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5885 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5886}
5887
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5888/// Return true for all instructions that only update
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5889/// the first 32 or 64-bits of the destination register and leave the rest
5890/// unmodified. This can be used to avoid folding loads if the instructions
5891/// only update part of the destination register, and the non-updated part is
5892/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5893/// instructions breaks the partial register dependency and it can improve
5894/// performance. e.g.:
5895///
5896/// movss (%rdi), %xmm0
5897/// cvtss2sd %xmm0, %xmm0
5898///
5899/// Instead of
5900/// cvtss2sd (%rdi), %xmm0
5901///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]5902/// FIXME: This should be turned into a TSFlags.
5903///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5904static bool hasPartialRegUpdate(unsigned Opcode) {
5905 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5906 case X86::CVTSI2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5907 case X86::CVTSI2SSrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5908 case X86::CVTSI2SS64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5909 case X86::CVTSI2SS64rm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5910 case X86::CVTSI2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5911 case X86::CVTSI2SDrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5912 case X86::CVTSI2SD64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5913 case X86::CVTSI2SD64rm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5914 case X86::CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5915 case X86::CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5916 case X86::Int_CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5917 case X86::Int_CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5918 case X86::CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5919 case X86::CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5920 case X86::Int_CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5921 case X86::Int_CVTSS2SDrm:
Simon Pilgrima2074362016-02-08 23:03:46 +0000[diff] [blame]5922 case X86::MOVHPDrm:
5923 case X86::MOVHPSrm:
5924 case X86::MOVLPDrm:
5925 case X86::MOVLPSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5926 case X86::RCPSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5927 case X86::RCPSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5928 case X86::RCPSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5929 case X86::RCPSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5930 case X86::ROUNDSDr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5931 case X86::ROUNDSDm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]5932 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5933 case X86::ROUNDSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5934 case X86::ROUNDSSm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]5935 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5936 case X86::RSQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5937 case X86::RSQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5938 case X86::RSQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5939 case X86::RSQRTSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5940 case X86::SQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5941 case X86::SQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5942 case X86::SQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5943 case X86::SQRTSSm_Int:
5944 case X86::SQRTSDr:
5945 case X86::SQRTSDm:
5946 case X86::SQRTSDr_Int:
5947 case X86::SQRTSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5948 return true;
5949 }
5950
5951 return false;
5952}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5953
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5954/// Inform the ExeDepsFix pass how many idle
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5955/// instructions we would like before a partial register update.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5956unsigned X86InstrInfo::getPartialRegUpdateClearance(
5957 const MachineInstr &MI, unsigned OpNum,
5958 const TargetRegisterInfo *TRI) const {
5959 if (OpNum != 0 || !hasPartialRegUpdate(MI.getOpcode()))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5960 return 0;
5961
5962 // If MI is marked as reading Reg, the partial register update is wanted.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5963 const MachineOperand &MO = MI.getOperand(0);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5964 unsigned Reg = MO.getReg();
5965 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5966 if (MO.readsReg() || MI.readsVirtualRegister(Reg))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5967 return 0;
5968 } else {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]5969 if (MI.readsRegister(Reg, TRI))
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5970 return 0;
5971 }
5972
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]5973 // If any instructions in the clearance range are reading Reg, insert a
5974 // dependency breaking instruction, which is inexpensive and is likely to
5975 // be hidden in other instruction's cycles.
5976 return PartialRegUpdateClearance;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5977}
5978
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5979// Return true for any instruction the copies the high bits of the first source
5980// operand into the unused high bits of the destination operand.
5981static bool hasUndefRegUpdate(unsigned Opcode) {
5982 switch (Opcode) {
5983 case X86::VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5984 case X86::VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5985 case X86::Int_VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5986 case X86::Int_VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5987 case X86::VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5988 case X86::VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5989 case X86::Int_VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5990 case X86::Int_VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5991 case X86::VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5992 case X86::VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5993 case X86::Int_VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5994 case X86::Int_VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5995 case X86::VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5996 case X86::VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5997 case X86::Int_VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5998 case X86::Int_VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5999 case X86::VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6000 case X86::VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6001 case X86::Int_VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6002 case X86::Int_VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6003 case X86::VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6004 case X86::VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6005 case X86::Int_VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6006 case X86::Int_VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6007 case X86::VRCPSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6008 case X86::VRCPSSm:
6009 case X86::VRCPSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6010 case X86::VROUNDSDr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6011 case X86::VROUNDSDm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6012 case X86::VROUNDSDr_Int:
6013 case X86::VROUNDSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6014 case X86::VROUNDSSm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6015 case X86::VROUNDSSr_Int:
6016 case X86::VRSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6017 case X86::VRSQRTSSm:
6018 case X86::VRSQRTSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6019 case X86::VSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6020 case X86::VSQRTSSm:
6021 case X86::VSQRTSSm_Int:
6022 case X86::VSQRTSDr:
6023 case X86::VSQRTSDm:
6024 case X86::VSQRTSDm_Int:
6025 // AVX-512
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6026 case X86::VCVTSD2SSZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6027 case X86::VCVTSD2SSZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6028 case X86::VCVTSS2SDZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]6029 case X86::VCVTSS2SDZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6030 return true;
6031 }
6032
6033 return false;
6034}
6035
6036/// Inform the ExeDepsFix pass how many idle instructions we would like before
6037/// certain undef register reads.
6038///
6039/// This catches the VCVTSI2SD family of instructions:
6040///
6041/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
6042///
6043/// We should to be careful *not* to catch VXOR idioms which are presumably
6044/// handled specially in the pipeline:
6045///
6046/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
6047///
6048/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
6049/// high bits that are passed-through are not live.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6050unsigned
6051X86InstrInfo::getUndefRegClearance(const MachineInstr &MI, unsigned &OpNum,
6052 const TargetRegisterInfo *TRI) const {
6053 if (!hasUndefRegUpdate(MI.getOpcode()))
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6054 return 0;
6055
6056 // Set the OpNum parameter to the first source operand.
6057 OpNum = 1;
6058
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6059 const MachineOperand &MO = MI.getOperand(OpNum);
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6060 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
Dehao Chen8cd84aa2016-06-28 21:19:34 +0000[diff] [blame]6061 return UndefRegClearance;
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6062 }
6063 return 0;
6064}
6065
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6066void X86InstrInfo::breakPartialRegDependency(
6067 MachineInstr &MI, unsigned OpNum, const TargetRegisterInfo *TRI) const {
6068 unsigned Reg = MI.getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6069 // If MI kills this register, the false dependence is already broken.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6070 if (MI.killsRegister(Reg, TRI))
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]6071 return;
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6072
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6073 if (X86::VR128RegClass.contains(Reg)) {
6074 // These instructions are all floating point domain, so xorps is the best
6075 // choice.
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6076 unsigned Opc = Subtarget.hasAVX() ? X86::VXORPSrr : X86::XORPSrr;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6077 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(Opc), Reg)
6078 .addReg(Reg, RegState::Undef)
6079 .addReg(Reg, RegState::Undef);
6080 MI.addRegisterKilled(Reg, TRI, true);
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6081 } else if (X86::VR256RegClass.contains(Reg)) {
6082 // Use vxorps to clear the full ymm register.
6083 // It wants to read and write the xmm sub-register.
6084 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6085 BuildMI(*MI.getParent(), MI, MI.getDebugLoc(), get(X86::VXORPSrr), XReg)
6086 .addReg(XReg, RegState::Undef)
6087 .addReg(XReg, RegState::Undef)
6088 .addReg(Reg, RegState::ImplicitDefine);
6089 MI.addRegisterKilled(Reg, TRI, true);
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6090 }
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]6091}
6092
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6093MachineInstr *
6094X86InstrInfo::foldMemoryOperandImpl(MachineFunction &MF, MachineInstr &MI,
6095 ArrayRef<unsigned> Ops,
6096 MachineBasicBlock::iterator InsertPt,
6097 int FrameIndex, LiveIntervals *LIS) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6098 // Check switch flag
Sanjay Patelcc4c71b2015-12-28 18:18:22 +0000[diff] [blame]6099 if (NoFusing)
6100 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6101
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]6102 // Unless optimizing for size, don't fold to avoid partial
6103 // register update stalls
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6104 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6105 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6106
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6107 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6108 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6109 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]6110 // If the function stack isn't realigned we don't want to fold instructions
6111 // that need increased alignment.
6112 if (!RI.needsStackRealignment(MF))
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]6113 Alignment =
6114 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6115 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6116 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6117 unsigned RCSize = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6118 switch (MI.getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6119 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6120 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]6121 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
6122 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
6123 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6124 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]6125 // Check if it's safe to fold the load. If the size of the object is
6126 // narrower than the load width, then it's not.
6127 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6128 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6129 // Change to CMPXXri r, 0 first.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6130 MI.setDesc(get(NewOpc));
6131 MI.getOperand(1).ChangeToImmediate(0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6132 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6133 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6134
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]6135 return foldMemoryOperandImpl(MF, MI, Ops[0],
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6136 MachineOperand::CreateFI(FrameIndex), InsertPt,
6137 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6138}
6139
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6140/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
6141/// because the latter uses contents that wouldn't be defined in the folded
6142/// version. For instance, this transformation isn't legal:
6143/// movss (%rdi), %xmm0
6144/// addps %xmm0, %xmm0
6145/// ->
6146/// addps (%rdi), %xmm0
6147///
6148/// But this one is:
6149/// movss (%rdi), %xmm0
6150/// addss %xmm0, %xmm0
6151/// ->
6152/// addss (%rdi), %xmm0
6153///
6154static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
6155 const MachineInstr &UserMI,
6156 const MachineFunction &MF) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6157 unsigned Opc = LoadMI.getOpcode();
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6158 unsigned UserOpc = UserMI.getOpcode();
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6159 unsigned RegSize =
6160 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
6161
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6162 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6163 // These instructions only load 32 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6164 // destination register is wider than 32 bits (4 bytes), and its user
6165 // instruction isn't scalar (SS).
6166 switch (UserOpc) {
6167 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
6168 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
6169 case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
6170 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
Vyacheslav Klochkoved865df2015-11-26 07:45:30 +0000[diff] [blame]6171 case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int:
6172 case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int:
6173 case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int:
6174 case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int:
6175 case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int:
6176 case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6177 return false;
6178 default:
6179 return true;
6180 }
6181 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6182
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6183 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6184 // These instructions only load 64 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6185 // destination register is wider than 64 bits (8 bytes), and its user
6186 // instruction isn't scalar (SD).
6187 switch (UserOpc) {
6188 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
6189 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
6190 case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
6191 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
Vyacheslav Klochkoved865df2015-11-26 07:45:30 +0000[diff] [blame]6192 case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int:
6193 case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int:
6194 case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int:
6195 case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int:
6196 case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int:
6197 case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6198 return false;
6199 default:
6200 return true;
6201 }
6202 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6203
6204 return false;
6205}
6206
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6207MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6208 MachineFunction &MF, MachineInstr &MI, ArrayRef<unsigned> Ops,
6209 MachineBasicBlock::iterator InsertPt, MachineInstr &LoadMI,
Jonas Paulsson8e5b0c62016-05-10 08:09:37 +0000[diff] [blame]6210 LiveIntervals *LIS) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6211 // If loading from a FrameIndex, fold directly from the FrameIndex.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6212 unsigned NumOps = LoadMI.getDesc().getNumOperands();
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6213 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6214 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6215 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6216 return nullptr;
Jonas Paulsson8e5b0c62016-05-10 08:09:37 +0000[diff] [blame]6217 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex, LIS);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6218 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6219
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6220 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6221 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6222
Sanjay Pateld09391c2015-08-10 20:45:44 +0000[diff] [blame]6223 // Avoid partial register update stalls unless optimizing for size.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6224 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI.getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6225 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6226
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]6227 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6228 unsigned Alignment = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6229 if (LoadMI.hasOneMemOperand())
6230 Alignment = (*LoadMI.memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6231 else
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6232 switch (LoadMI.getOpcode()) {
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6233 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6234 case X86::AVX_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6235 Alignment = 32;
6236 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6237 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6238 case X86::V_SETALLONES:
6239 Alignment = 16;
6240 break;
6241 case X86::FsFLD0SD:
6242 Alignment = 8;
6243 break;
6244 case X86::FsFLD0SS:
6245 Alignment = 4;
6246 break;
6247 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6248 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6249 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6250 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6251 unsigned NewOpc = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6252 switch (MI.getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6253 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6254 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6255 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6256 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6257 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6258 }
6259 // Change to CMPXXri r, 0 first.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6260 MI.setDesc(get(NewOpc));
6261 MI.getOperand(1).ChangeToImmediate(0);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6262 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6263 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6264
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6265 // Make sure the subregisters match.
6266 // Otherwise we risk changing the size of the load.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6267 if (LoadMI.getOperand(0).getSubReg() != MI.getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6268 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6269
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6270 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6271 switch (LoadMI.getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6272 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6273 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6274 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6275 case X86::AVX_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6276 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6277 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6278 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6279 // Create a constant-pool entry and operands to load from it.
6280
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6281 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6282 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6283 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6284 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6285
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6286 // x86-32 PIC requires a PIC base register for constant pools.
6287 unsigned PICBase = 0;
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000[diff] [blame]6288 if (MF.getTarget().isPositionIndependent()) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6289 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6290 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6291 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6292 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6293 // This doesn't work for several reasons.
6294 // 1. GlobalBaseReg may have been spilled.
6295 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6296 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6297 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6298
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6299 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6300 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]6301 Type *Ty;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6302 unsigned Opc = LoadMI.getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6303 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6304 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6305 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6306 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6307 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]6308 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6309 else
6310 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6311
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]6312 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6313 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6314 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6315 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6316
6317 // Create operands to load from the constant pool entry.
6318 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6319 MOs.push_back(MachineOperand::CreateImm(1));
6320 MOs.push_back(MachineOperand::CreateReg(0, false));
6321 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]6322 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6323 break;
6324 }
6325 default: {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6326 if (isNonFoldablePartialRegisterLoad(LoadMI, MI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6327 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]6328
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6329 // Folding a normal load. Just copy the load's address operands.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6330 MOs.append(LoadMI.operands_begin() + NumOps - X86::AddrNumOperands,
6331 LoadMI.operands_begin() + NumOps);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6332 break;
6333 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6334 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6335 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6336 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6337}
6338
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6339bool X86InstrInfo::unfoldMemoryOperand(
6340 MachineFunction &MF, MachineInstr &MI, unsigned Reg, bool UnfoldLoad,
6341 bool UnfoldStore, SmallVectorImpl<MachineInstr *> &NewMIs) const {
6342 auto I = MemOp2RegOpTable.find(MI.getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6343 if (I == MemOp2RegOpTable.end())
6344 return false;
6345 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6346 unsigned Index = I->second.second & TB_INDEX_MASK;
6347 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6348 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6349 if (UnfoldLoad && !FoldedLoad)
6350 return false;
6351 UnfoldLoad &= FoldedLoad;
6352 if (UnfoldStore && !FoldedStore)
6353 return false;
6354 UnfoldStore &= FoldedStore;
6355
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6356 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6357 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6358 // TODO: Check if 32-byte or greater accesses are slow too?
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6359 if (!MI.hasOneMemOperand() && RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6360 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6361 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6362 // conservatively assume the address is unaligned. That's bad for
6363 // performance.
6364 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6365 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6366 SmallVector<MachineOperand,2> BeforeOps;
6367 SmallVector<MachineOperand,2> AfterOps;
6368 SmallVector<MachineOperand,4> ImpOps;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6369 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
6370 MachineOperand &Op = MI.getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6371 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6372 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6373 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6374 ImpOps.push_back(Op);
6375 else if (i < Index)
6376 BeforeOps.push_back(Op);
6377 else if (i > Index)
6378 AfterOps.push_back(Op);
6379 }
6380
6381 // Emit the load instruction.
6382 if (UnfoldLoad) {
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6383 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6384 MF.extractLoadMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6385 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6386 if (UnfoldStore) {
6387 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6388 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6389 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6390 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6391 MO.setIsKill(false);
6392 }
6393 }
6394 }
6395
6396 // Emit the data processing instruction.
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6397 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI.getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]6398 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6399
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6400 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6401 MIB.addReg(Reg, RegState::Define);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6402 for (MachineOperand &BeforeOp : BeforeOps)
6403 MIB.addOperand(BeforeOp);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6404 if (FoldedLoad)
6405 MIB.addReg(Reg);
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6406 for (MachineOperand &AfterOp : AfterOps)
6407 MIB.addOperand(AfterOp);
6408 for (MachineOperand &ImpOp : ImpOps) {
6409 MIB.addReg(ImpOp.getReg(),
6410 getDefRegState(ImpOp.isDef()) |
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6411 RegState::Implicit |
Sanjay Patel4104f782015-12-29 19:14:23 +0000[diff] [blame]6412 getKillRegState(ImpOp.isKill()) |
6413 getDeadRegState(ImpOp.isDead()) |
6414 getUndefRegState(ImpOp.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6415 }
6416 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6417 switch (DataMI->getOpcode()) {
6418 default: break;
6419 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6420 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6421 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6422 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6423 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6424 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6425 case X86::CMP8ri: {
6426 MachineOperand &MO0 = DataMI->getOperand(0);
6427 MachineOperand &MO1 = DataMI->getOperand(1);
6428 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6429 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6430 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6431 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6432 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6433 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6434 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6435 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6436 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6437 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
6438 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
6439 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]6440 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6441 MO1.ChangeToRegister(MO0.getReg(), false);
6442 }
6443 }
6444 }
6445 NewMIs.push_back(DataMI);
6446
6447 // Emit the store instruction.
6448 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6449 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6450 std::pair<MachineInstr::mmo_iterator, MachineInstr::mmo_iterator> MMOs =
6451 MF.extractStoreMemRefs(MI.memoperands_begin(), MI.memoperands_end());
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6452 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6453 }
6454
6455 return true;
6456}
6457
6458bool
6459X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]6460 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]6461 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6462 return false;
6463
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6464 auto I = MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6465 if (I == MemOp2RegOpTable.end())
6466 return false;
6467 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6468 unsigned Index = I->second.second & TB_INDEX_MASK;
6469 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6470 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6471 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6472 MachineFunction &MF = DAG.getMachineFunction();
6473 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6474 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6475 std::vector<SDValue> AddrOps;
6476 std::vector<SDValue> BeforeOps;
6477 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]6478 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6479 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]6480 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6481 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6482 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6483 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6484 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6485 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6486 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6487 AfterOps.push_back(Op);
6488 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6489 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6490 AddrOps.push_back(Chain);
6491
6492 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6493 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6494 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6495 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6496 std::pair<MachineInstr::mmo_iterator,
6497 MachineInstr::mmo_iterator> MMOs =
6498 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6499 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6500 if (!(*MMOs.first) &&
6501 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6502 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6503 // Do not introduce a slow unaligned load.
6504 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6505 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6506 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6507 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6508 bool isAligned = (*MMOs.first) &&
6509 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6510 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6511 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6512 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6513
6514 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6515 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6516 }
6517
6518 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6519 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6520 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6521 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6522 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6523 VTs.push_back(*DstRC->vt_begin());
6524 }
6525 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6526 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6527 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6528 VTs.push_back(VT);
6529 }
6530 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6531 BeforeOps.push_back(SDValue(Load, 0));
Benjamin Kramer4f6ac162015-02-28 10:11:12 +0000[diff] [blame]6532 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6533 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6534 NewNodes.push_back(NewNode);
6535
6536 // Emit the store instruction.
6537 if (FoldedStore) {
6538 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6539 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6540 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6541 std::pair<MachineInstr::mmo_iterator,
6542 MachineInstr::mmo_iterator> MMOs =
6543 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6544 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6545 if (!(*MMOs.first) &&
6546 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6547 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6548 // Do not introduce a slow unaligned store.
6549 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6550 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6551 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6552 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6553 bool isAligned = (*MMOs.first) &&
6554 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6555 SDNode *Store =
6556 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6557 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6558 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6559
6560 // Preserve memory reference information.
Craig Topper9e71b822015-02-10 06:29:28 +0000[diff] [blame]6561 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6562 }
6563
6564 return true;
6565}
6566
6567unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6568 bool UnfoldLoad, bool UnfoldStore,
6569 unsigned *LoadRegIndex) const {
Craig Toppere012ede2016-04-30 17:59:49 +0000[diff] [blame]6570 auto I = MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6571 if (I == MemOp2RegOpTable.end())
6572 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6573 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6574 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6575 if (UnfoldLoad && !FoldedLoad)
6576 return 0;
6577 if (UnfoldStore && !FoldedStore)
6578 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6579 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6580 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6581 return I->second.first;
6582}
6583
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6584bool
6585X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6586 int64_t &Offset1, int64_t &Offset2) const {
6587 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6588 return false;
6589 unsigned Opc1 = Load1->getMachineOpcode();
6590 unsigned Opc2 = Load2->getMachineOpcode();
6591 switch (Opc1) {
6592 default: return false;
6593 case X86::MOV8rm:
6594 case X86::MOV16rm:
6595 case X86::MOV32rm:
6596 case X86::MOV64rm:
6597 case X86::LD_Fp32m:
6598 case X86::LD_Fp64m:
6599 case X86::LD_Fp80m:
6600 case X86::MOVSSrm:
6601 case X86::MOVSDrm:
6602 case X86::MMX_MOVD64rm:
6603 case X86::MMX_MOVQ64rm:
6604 case X86::FsMOVAPSrm:
6605 case X86::FsMOVAPDrm:
6606 case X86::MOVAPSrm:
6607 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6608 case X86::MOVAPDrm:
6609 case X86::MOVDQArm:
6610 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6611 // AVX load instructions
6612 case X86::VMOVSSrm:
6613 case X86::VMOVSDrm:
6614 case X86::FsVMOVAPSrm:
6615 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6616 case X86::VMOVAPSrm:
6617 case X86::VMOVUPSrm:
6618 case X86::VMOVAPDrm:
6619 case X86::VMOVDQArm:
6620 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6621 case X86::VMOVAPSYrm:
6622 case X86::VMOVUPSYrm:
6623 case X86::VMOVAPDYrm:
6624 case X86::VMOVDQAYrm:
6625 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6626 break;
6627 }
6628 switch (Opc2) {
6629 default: return false;
6630 case X86::MOV8rm:
6631 case X86::MOV16rm:
6632 case X86::MOV32rm:
6633 case X86::MOV64rm:
6634 case X86::LD_Fp32m:
6635 case X86::LD_Fp64m:
6636 case X86::LD_Fp80m:
6637 case X86::MOVSSrm:
6638 case X86::MOVSDrm:
6639 case X86::MMX_MOVD64rm:
6640 case X86::MMX_MOVQ64rm:
6641 case X86::FsMOVAPSrm:
6642 case X86::FsMOVAPDrm:
6643 case X86::MOVAPSrm:
6644 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6645 case X86::MOVAPDrm:
6646 case X86::MOVDQArm:
6647 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6648 // AVX load instructions
6649 case X86::VMOVSSrm:
6650 case X86::VMOVSDrm:
6651 case X86::FsVMOVAPSrm:
6652 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6653 case X86::VMOVAPSrm:
6654 case X86::VMOVUPSrm:
6655 case X86::VMOVAPDrm:
6656 case X86::VMOVDQArm:
6657 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6658 case X86::VMOVAPSYrm:
6659 case X86::VMOVUPSYrm:
6660 case X86::VMOVAPDYrm:
6661 case X86::VMOVDQAYrm:
6662 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6663 break;
6664 }
6665
6666 // Check if chain operands and base addresses match.
6667 if (Load1->getOperand(0) != Load2->getOperand(0) ||
6668 Load1->getOperand(5) != Load2->getOperand(5))
6669 return false;
6670 // Segment operands should match as well.
6671 if (Load1->getOperand(4) != Load2->getOperand(4))
6672 return false;
6673 // Scale should be 1, Index should be Reg0.
6674 if (Load1->getOperand(1) == Load2->getOperand(1) &&
6675 Load1->getOperand(2) == Load2->getOperand(2)) {
6676 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6677 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6678
6679 // Now let's examine the displacements.
6680 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6681 isa<ConstantSDNode>(Load2->getOperand(3))) {
6682 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6683 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6684 return true;
6685 }
6686 }
6687 return false;
6688}
6689
6690bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6691 int64_t Offset1, int64_t Offset2,
6692 unsigned NumLoads) const {
6693 assert(Offset2 > Offset1);
6694 if ((Offset2 - Offset1) / 8 > 64)
6695 return false;
6696
6697 unsigned Opc1 = Load1->getMachineOpcode();
6698 unsigned Opc2 = Load2->getMachineOpcode();
6699 if (Opc1 != Opc2)
6700 return false; // FIXME: overly conservative?
6701
6702 switch (Opc1) {
6703 default: break;
6704 case X86::LD_Fp32m:
6705 case X86::LD_Fp64m:
6706 case X86::LD_Fp80m:
6707 case X86::MMX_MOVD64rm:
6708 case X86::MMX_MOVQ64rm:
6709 return false;
6710 }
6711
6712 EVT VT = Load1->getValueType(0);
6713 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6714 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6715 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6716 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6717 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6718 if (NumLoads >= 3)
6719 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6720 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6721 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6722 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6723 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6724 case MVT::i8:
6725 case MVT::i16:
6726 case MVT::i32:
6727 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]6728 case MVT::f32:
6729 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6730 if (NumLoads)
6731 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6732 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6733 }
6734
6735 return true;
6736}
6737
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6738bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr &First,
6739 MachineInstr &Second) const {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6740 // Check if this processor supports macro-fusion. Since this is a minor
6741 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6742 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6743 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6744 return false;
6745
6746 enum {
6747 FuseTest,
6748 FuseCmp,
6749 FuseInc
6750 } FuseKind;
6751
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6752 switch (Second.getOpcode()) {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6753 default:
6754 return false;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6755 case X86::JE_1:
6756 case X86::JNE_1:
6757 case X86::JL_1:
6758 case X86::JLE_1:
6759 case X86::JG_1:
6760 case X86::JGE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6761 FuseKind = FuseInc;
6762 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6763 case X86::JB_1:
6764 case X86::JBE_1:
6765 case X86::JA_1:
6766 case X86::JAE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6767 FuseKind = FuseCmp;
6768 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6769 case X86::JS_1:
6770 case X86::JNS_1:
6771 case X86::JP_1:
6772 case X86::JNP_1:
6773 case X86::JO_1:
6774 case X86::JNO_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6775 FuseKind = FuseTest;
6776 break;
6777 }
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]6778 switch (First.getOpcode()) {
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6779 default:
6780 return false;
6781 case X86::TEST8rr:
6782 case X86::TEST16rr:
6783 case X86::TEST32rr:
6784 case X86::TEST64rr:
6785 case X86::TEST8ri:
6786 case X86::TEST16ri:
6787 case X86::TEST32ri:
6788 case X86::TEST32i32:
6789 case X86::TEST64i32:
6790 case X86::TEST64ri32:
6791 case X86::TEST8rm:
6792 case X86::TEST16rm:
6793 case X86::TEST32rm:
6794 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]6795 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6796 case X86::AND16i16:
6797 case X86::AND16ri:
6798 case X86::AND16ri8:
6799 case X86::AND16rm:
6800 case X86::AND16rr:
6801 case X86::AND32i32:
6802 case X86::AND32ri:
6803 case X86::AND32ri8:
6804 case X86::AND32rm:
6805 case X86::AND32rr:
6806 case X86::AND64i32:
6807 case X86::AND64ri32:
6808 case X86::AND64ri8:
6809 case X86::AND64rm:
6810 case X86::AND64rr:
6811 case X86::AND8i8:
6812 case X86::AND8ri:
6813 case X86::AND8rm:
6814 case X86::AND8rr:
6815 return true;
6816 case X86::CMP16i16:
6817 case X86::CMP16ri:
6818 case X86::CMP16ri8:
6819 case X86::CMP16rm:
6820 case X86::CMP16rr:
6821 case X86::CMP32i32:
6822 case X86::CMP32ri:
6823 case X86::CMP32ri8:
6824 case X86::CMP32rm:
6825 case X86::CMP32rr:
6826 case X86::CMP64i32:
6827 case X86::CMP64ri32:
6828 case X86::CMP64ri8:
6829 case X86::CMP64rm:
6830 case X86::CMP64rr:
6831 case X86::CMP8i8:
6832 case X86::CMP8ri:
6833 case X86::CMP8rm:
6834 case X86::CMP8rr:
6835 case X86::ADD16i16:
6836 case X86::ADD16ri:
6837 case X86::ADD16ri8:
6838 case X86::ADD16ri8_DB:
6839 case X86::ADD16ri_DB:
6840 case X86::ADD16rm:
6841 case X86::ADD16rr:
6842 case X86::ADD16rr_DB:
6843 case X86::ADD32i32:
6844 case X86::ADD32ri:
6845 case X86::ADD32ri8:
6846 case X86::ADD32ri8_DB:
6847 case X86::ADD32ri_DB:
6848 case X86::ADD32rm:
6849 case X86::ADD32rr:
6850 case X86::ADD32rr_DB:
6851 case X86::ADD64i32:
6852 case X86::ADD64ri32:
6853 case X86::ADD64ri32_DB:
6854 case X86::ADD64ri8:
6855 case X86::ADD64ri8_DB:
6856 case X86::ADD64rm:
6857 case X86::ADD64rr:
6858 case X86::ADD64rr_DB:
6859 case X86::ADD8i8:
6860 case X86::ADD8mi:
6861 case X86::ADD8mr:
6862 case X86::ADD8ri:
6863 case X86::ADD8rm:
6864 case X86::ADD8rr:
6865 case X86::SUB16i16:
6866 case X86::SUB16ri:
6867 case X86::SUB16ri8:
6868 case X86::SUB16rm:
6869 case X86::SUB16rr:
6870 case X86::SUB32i32:
6871 case X86::SUB32ri:
6872 case X86::SUB32ri8:
6873 case X86::SUB32rm:
6874 case X86::SUB32rr:
6875 case X86::SUB64i32:
6876 case X86::SUB64ri32:
6877 case X86::SUB64ri8:
6878 case X86::SUB64rm:
6879 case X86::SUB64rr:
6880 case X86::SUB8i8:
6881 case X86::SUB8ri:
6882 case X86::SUB8rm:
6883 case X86::SUB8rr:
6884 return FuseKind == FuseCmp || FuseKind == FuseInc;
6885 case X86::INC16r:
6886 case X86::INC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6887 case X86::INC64r:
6888 case X86::INC8r:
6889 case X86::DEC16r:
6890 case X86::DEC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6891 case X86::DEC64r:
6892 case X86::DEC8r:
6893 return FuseKind == FuseInc;
6894 }
6895}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6896
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]6897bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]6898ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]6899 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]6900 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
6901 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]6902 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]6903}
6904
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]6905bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]6906isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6907 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]6908 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]6909 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6910 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]6911}
6912
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6913/// Return a virtual register initialized with the
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6914/// the global base register value. Output instructions required to
6915/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]6916///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6917/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6918///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6919unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6920 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6921 "X86-64 PIC uses RIP relative addressing");
6922
6923 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6924 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6925 if (GlobalBaseReg != 0)
6926 return GlobalBaseReg;
6927
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6928 // Create the register. The code to initialize it is inserted
6929 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]6930 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]6931 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6932 X86FI->setGlobalBaseReg(GlobalBaseReg);
6933 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]6934}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6935
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6936// These are the replaceable SSE instructions. Some of these have Int variants
6937// that we don't include here. We don't want to replace instructions selected
6938// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6939static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]6940 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]6941 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
6942 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
6943 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
6944 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
6945 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
Sanjay Patelc03d93b2015-04-15 15:47:51 +0000[diff] [blame]6946 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]6947 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
6948 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
6949 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
6950 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
6951 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
6952 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
6953 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
6954 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
6955 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6956 // AVX 128-bit support
6957 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
6958 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
6959 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
6960 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
6961 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
Sanjay Patel2161c492015-04-17 17:02:37 +0000[diff] [blame]6962 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6963 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6964 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
6965 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
6966 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
6967 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
6968 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
6969 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6970 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
6971 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6972 // AVX 256-bit support
6973 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
6974 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
6975 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
6976 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
6977 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]6978 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
6979};
6980
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6981static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]6982 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]6983 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
6984 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
6985 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
6986 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
6987 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
6988 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
6989 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]6990 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
6991 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6992 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6993 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
6994 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
6995 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]6996 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
6997 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6998 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6999 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
7000 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
7001 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
7002 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7003};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7004
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7005// FIXME: Some shuffle and unpack instructions have equivalents in different
7006// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7007
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7008static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]7009 for (const uint16_t (&Row)[3] : ReplaceableInstrs)
7010 if (Row[domain-1] == opcode)
7011 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]7012 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7013}
7014
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]7015static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]7016 for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
7017 if (Row[domain-1] == opcode)
7018 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]7019 return nullptr;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7020}
7021
7022std::pair<uint16_t, uint16_t>
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7023X86InstrInfo::getExecutionDomain(const MachineInstr &MI) const {
7024 uint16_t domain = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7025 bool hasAVX2 = Subtarget.hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7026 uint16_t validDomains = 0;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7027 if (domain && lookup(MI.getOpcode(), domain))
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7028 validDomains = 0xe;
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7029 else if (domain && lookupAVX2(MI.getOpcode(), domain))
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]7030 validDomains = hasAVX2 ? 0xe : 0x6;
7031 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7032}
7033
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7034void X86InstrInfo::setExecutionDomain(MachineInstr &MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7035 assert(Domain>0 && Domain<4 && "Invalid execution domain");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7036 uint16_t dom = (MI.getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7037 assert(dom && "Not an SSE instruction");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7038 const uint16_t *table = lookup(MI.getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7039 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]7040 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7041 "256-bit vector operations only available in AVX2");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7042 table = lookupAVX2(MI.getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]7043 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]7044 assert(table && "Cannot change domain");
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7045 MI.setDesc(get(table[Domain - 1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]7046}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7047
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7048/// Return the noop instruction to use for a noop.
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]7049void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
7050 NopInst.setOpcode(X86::NOOP);
7051}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7052
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7053// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7054// In particular, getJumpInstrTableEntryBound must always return an upper bound
7055// on the encoding lengths of the instructions generated by
7056// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7057void X86InstrInfo::getUnconditionalBranch(
7058 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]7059 Branch.setOpcode(X86::JMP_1);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]7060 Branch.addOperand(MCOperand::createExpr(BranchTarget));
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7061}
7062
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7063// This code must remain in sync with getJumpInstrTableEntryBound in this class!
7064// In particular, getJumpInstrTableEntryBound must always return an upper bound
7065// on the encoding lengths of the instructions generated by
7066// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]7067void X86InstrInfo::getTrap(MCInst &MI) const {
7068 MI.setOpcode(X86::TRAP);
7069}
7070
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]7071// See getTrap and getUnconditionalBranch for conditions on the value returned
7072// by this function.
7073unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
7074 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
7075 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
7076 return 5;
7077}
7078
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7079bool X86InstrInfo::isHighLatencyDef(int opc) const {
7080 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7081 default: return false;
7082 case X86::DIVSDrm:
7083 case X86::DIVSDrm_Int:
7084 case X86::DIVSDrr:
7085 case X86::DIVSDrr_Int:
7086 case X86::DIVSSrm:
7087 case X86::DIVSSrm_Int:
7088 case X86::DIVSSrr:
7089 case X86::DIVSSrr_Int:
7090 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7091 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7092 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7093 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7094 case X86::SQRTSDm:
7095 case X86::SQRTSDm_Int:
7096 case X86::SQRTSDr:
7097 case X86::SQRTSDr_Int:
7098 case X86::SQRTSSm:
7099 case X86::SQRTSSm_Int:
7100 case X86::SQRTSSr:
7101 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7102 // AVX instructions with high latency
7103 case X86::VDIVSDrm:
7104 case X86::VDIVSDrm_Int:
7105 case X86::VDIVSDrr:
7106 case X86::VDIVSDrr_Int:
7107 case X86::VDIVSSrm:
7108 case X86::VDIVSSrm_Int:
7109 case X86::VDIVSSrr:
7110 case X86::VDIVSSrr_Int:
7111 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7112 case X86::VSQRTPDr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7113 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7114 case X86::VSQRTPSr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]7115 case X86::VSQRTSDm:
7116 case X86::VSQRTSDm_Int:
7117 case X86::VSQRTSDr:
7118 case X86::VSQRTSSm:
7119 case X86::VSQRTSSm_Int:
7120 case X86::VSQRTSSr:
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]7121 case X86::VSQRTPDZm:
7122 case X86::VSQRTPDZr:
7123 case X86::VSQRTPSZm:
7124 case X86::VSQRTPSZr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7125 case X86::VSQRTSDZm:
7126 case X86::VSQRTSDZm_Int:
7127 case X86::VSQRTSDZr:
7128 case X86::VSQRTSSZm_Int:
7129 case X86::VSQRTSSZr:
7130 case X86::VSQRTSSZm:
7131 case X86::VDIVSDZrm:
7132 case X86::VDIVSDZrr:
7133 case X86::VDIVSSZrm:
7134 case X86::VDIVSSZrr:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]7135
7136 case X86::VGATHERQPSZrm:
7137 case X86::VGATHERQPDZrm:
7138 case X86::VGATHERDPDZrm:
7139 case X86::VGATHERDPSZrm:
7140 case X86::VPGATHERQDZrm:
7141 case X86::VPGATHERQQZrm:
7142 case X86::VPGATHERDDZrm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]7143 case X86::VPGATHERDQZrm:
7144 case X86::VSCATTERQPDZmr:
7145 case X86::VSCATTERQPSZmr:
7146 case X86::VSCATTERDPDZmr:
7147 case X86::VSCATTERDPSZmr:
7148 case X86::VPSCATTERQDZmr:
7149 case X86::VPSCATTERQQZmr:
7150 case X86::VPSCATTERDDZmr:
7151 case X86::VPSCATTERDQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]7152 return true;
7153 }
7154}
7155
Duncan P. N. Exon Smith9cfc75c2016-06-30 00:01:54 +0000[diff] [blame]7156bool X86InstrInfo::hasHighOperandLatency(const TargetSchedModel &SchedModel,
7157 const MachineRegisterInfo *MRI,
7158 const MachineInstr &DefMI,
7159 unsigned DefIdx,
7160 const MachineInstr &UseMI,
7161 unsigned UseIdx) const {
7162 return isHighLatencyDef(DefMI.getOpcode());
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]7163}
7164
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7165bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
7166 const MachineBasicBlock *MBB) const {
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7167 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
7168 "Reassociation needs binary operators");
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7169
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7170 // Integer binary math/logic instructions have a third source operand:
7171 // the EFLAGS register. That operand must be both defined here and never
7172 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7173 // not change anything because rearranging the operands could affect other
7174 // instructions that depend on the exact status flags (zero, sign, etc.)
7175 // that are set by using these particular operands with this operation.
7176 if (Inst.getNumOperands() == 4) {
7177 assert(Inst.getOperand(3).isReg() &&
7178 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7179 "Unexpected operand in reassociable instruction");
7180 if (!Inst.getOperand(3).isDead())
7181 return false;
7182 }
Sanjay Patele79b43a2015-06-23 00:39:40 +0000[diff] [blame]7183
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7184 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7185}
7186
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7187// TODO: There are many more machine instruction opcodes to match:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7188// 1. Other data types (integer, vectors)
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7189// 2. Other math / logic operations (xor, or)
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7190// 3. Other forms of the same operation (intrinsics and other variants)
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7191bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7192 switch (Inst.getOpcode()) {
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7193 case X86::AND8rr:
7194 case X86::AND16rr:
7195 case X86::AND32rr:
7196 case X86::AND64rr:
Sanjay Pateld9a5c222015-08-31 20:27:03 +0000[diff] [blame]7197 case X86::OR8rr:
7198 case X86::OR16rr:
7199 case X86::OR32rr:
7200 case X86::OR64rr:
Sanjay Patelc9ae9d72015-09-03 16:36:16 +0000[diff] [blame]7201 case X86::XOR8rr:
7202 case X86::XOR16rr:
7203 case X86::XOR32rr:
7204 case X86::XOR64rr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7205 case X86::IMUL16rr:
7206 case X86::IMUL32rr:
7207 case X86::IMUL64rr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7208 case X86::PANDrr:
7209 case X86::PORrr:
7210 case X86::PXORrr:
7211 case X86::VPANDrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7212 case X86::VPANDYrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7213 case X86::VPORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7214 case X86::VPORYrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7215 case X86::VPXORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7216 case X86::VPXORYrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7217 // Normal min/max instructions are not commutative because of NaN and signed
7218 // zero semantics, but these are. Thus, there's no need to check for global
7219 // relaxed math; the instructions themselves have the properties we need.
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7220 case X86::MAXCPDrr:
7221 case X86::MAXCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7222 case X86::MAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7223 case X86::MAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7224 case X86::MINCPDrr:
7225 case X86::MINCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7226 case X86::MINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7227 case X86::MINCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7228 case X86::VMAXCPDrr:
7229 case X86::VMAXCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7230 case X86::VMAXCPDYrr:
7231 case X86::VMAXCPSYrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7232 case X86::VMAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7233 case X86::VMAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7234 case X86::VMINCPDrr:
7235 case X86::VMINCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7236 case X86::VMINCPDYrr:
7237 case X86::VMINCPSYrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7238 case X86::VMINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7239 case X86::VMINCSSrr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7240 return true;
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]7241 case X86::ADDPDrr:
7242 case X86::ADDPSrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]7243 case X86::ADDSDrr:
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7244 case X86::ADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]7245 case X86::MULPDrr:
7246 case X86::MULPSrr:
7247 case X86::MULSDrr:
7248 case X86::MULSSrr:
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]7249 case X86::VADDPDrr:
7250 case X86::VADDPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]7251 case X86::VADDPDYrr:
7252 case X86::VADDPSYrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]7253 case X86::VADDSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]7254 case X86::VADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]7255 case X86::VMULPDrr:
7256 case X86::VMULPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]7257 case X86::VMULPDYrr:
7258 case X86::VMULPSYrr:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7259 case X86::VMULSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]7260 case X86::VMULSSrr:
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7261 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7262 default:
7263 return false;
7264 }
7265}
7266
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7267/// This is an architecture-specific helper function of reassociateOps.
7268/// Set special operand attributes for new instructions after reassociation.
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7269void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7270 MachineInstr &OldMI2,
7271 MachineInstr &NewMI1,
7272 MachineInstr &NewMI2) const {
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7273 // Integer instructions define an implicit EFLAGS source register operand as
7274 // the third source (fourth total) operand.
7275 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7276 return;
7277
7278 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7279 "Unexpected instruction type for reassociation");
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7280
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7281 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7282 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7283 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7284 MachineOperand &NewOp2 = NewMI2.getOperand(3);
7285
7286 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7287 "Must have dead EFLAGS operand in reassociable instruction");
7288 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7289 "Must have dead EFLAGS operand in reassociable instruction");
7290
7291 (void)OldOp1;
7292 (void)OldOp2;
7293
7294 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7295 "Unexpected operand in reassociable instruction");
7296 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7297 "Unexpected operand in reassociable instruction");
7298
7299 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7300 // of this pass or other passes. The EFLAGS operands must be dead in these new
7301 // instructions because the EFLAGS operands in the original instructions must
7302 // be dead in order for reassociation to occur.
7303 NewOp1.setIsDead();
7304 NewOp2.setIsDead();
7305}
7306
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7307std::pair<unsigned, unsigned>
7308X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7309 return std::make_pair(TF, 0u);
7310}
7311
7312ArrayRef<std::pair<unsigned, const char *>>
7313X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7314 using namespace X86II;
Hal Finkel982e8d42015-08-30 08:07:29 +0000[diff] [blame]7315 static const std::pair<unsigned, const char *> TargetFlags[] = {
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7316 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7317 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7318 {MO_GOT, "x86-got"},
7319 {MO_GOTOFF, "x86-gotoff"},
7320 {MO_GOTPCREL, "x86-gotpcrel"},
7321 {MO_PLT, "x86-plt"},
7322 {MO_TLSGD, "x86-tlsgd"},
7323 {MO_TLSLD, "x86-tlsld"},
7324 {MO_TLSLDM, "x86-tlsldm"},
7325 {MO_GOTTPOFF, "x86-gottpoff"},
7326 {MO_INDNTPOFF, "x86-indntpoff"},
7327 {MO_TPOFF, "x86-tpoff"},
7328 {MO_DTPOFF, "x86-dtpoff"},
7329 {MO_NTPOFF, "x86-ntpoff"},
7330 {MO_GOTNTPOFF, "x86-gotntpoff"},
7331 {MO_DLLIMPORT, "x86-dllimport"},
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7332 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7333 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7334 {MO_TLVP, "x86-tlvp"},
7335 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7336 {MO_SECREL, "x86-secrel"}};
7337 return makeArrayRef(TargetFlags);
7338}
7339
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7340namespace {
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7341 /// Create Global Base Reg pass. This initializes the PIC
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7342 /// global base register for x86-32.
7343 struct CGBR : public MachineFunctionPass {
7344 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]7345 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7346
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7347 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7348 const X86TargetMachine *TM =
7349 static_cast<const X86TargetMachine *>(&MF.getTarget());
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7350 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7351
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]7352 // Don't do anything if this is 64-bit as 64-bit PIC
7353 // uses RIP relative addressing.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7354 if (STI.is64Bit())
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]7355 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7356
7357 // Only emit a global base reg in PIC mode.
Rafael Espindolaf9e348b2016-06-27 21:33:08 +0000[diff] [blame]7358 if (!TM->isPositionIndependent())
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7359 return false;
7360
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]7361 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7362 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7363
7364 // If we didn't need a GlobalBaseReg, don't insert code.
7365 if (GlobalBaseReg == 0)
7366 return false;
7367
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7368 // Insert the set of GlobalBaseReg into the first MBB of the function
7369 MachineBasicBlock &FirstMBB = MF.front();
7370 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7371 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7372 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7373 const X86InstrInfo *TII = STI.getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7374
7375 unsigned PC;
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7376 if (STI.isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]7377 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7378 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]7379 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]7380
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7381 // Operand of MovePCtoStack is completely ignored by asm printer. It's
7382 // only used in JIT code emission as displacement to pc.
7383 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]7384
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7385 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
7386 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7387 if (STI.isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7388 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
7389 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7390 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7391 X86II::MO_GOT_ABSOLUTE_ADDRESS);
7392 }
7393
7394 return true;
7395 }
7396
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7397 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7398 return "X86 PIC Global Base Reg Initialization";
7399 }
7400
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7401 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7402 AU.setPreservesCFG();
7403 MachineFunctionPass::getAnalysisUsage(AU);
7404 }
7405 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]7406}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7407
7408char CGBR::ID = 0;
7409FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]7410llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7411
7412namespace {
7413 struct LDTLSCleanup : public MachineFunctionPass {
7414 static char ID;
7415 LDTLSCleanup() : MachineFunctionPass(ID) {}
7416
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7417 bool runOnMachineFunction(MachineFunction &MF) override {
Andrew Kaylor2bee5ef2016-04-26 21:44:24 +0000[diff] [blame]7418 if (skipFunction(*MF.getFunction()))
7419 return false;
7420
7421 X86MachineFunctionInfo *MFI = MF.getInfo<X86MachineFunctionInfo>();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7422 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7423 // No point folding accesses if there isn't at least two.
7424 return false;
7425 }
7426
7427 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7428 return VisitNode(DT->getRootNode(), 0);
7429 }
7430
7431 // Visit the dominator subtree rooted at Node in pre-order.
7432 // If TLSBaseAddrReg is non-null, then use that to replace any
7433 // TLS_base_addr instructions. Otherwise, create the register
7434 // when the first such instruction is seen, and then use it
7435 // as we encounter more instructions.
7436 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7437 MachineBasicBlock *BB = Node->getBlock();
7438 bool Changed = false;
7439
7440 // Traverse the current block.
7441 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7442 ++I) {
7443 switch (I->getOpcode()) {
7444 case X86::TLS_base_addr32:
7445 case X86::TLS_base_addr64:
7446 if (TLSBaseAddrReg)
7447 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
7448 else
7449 I = SetRegister(I, &TLSBaseAddrReg);
7450 Changed = true;
7451 break;
7452 default:
7453 break;
7454 }
7455 }
7456
7457 // Visit the children of this block in the dominator tree.
7458 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7459 I != E; ++I) {
7460 Changed |= VisitNode(*I, TLSBaseAddrReg);
7461 }
7462
7463 return Changed;
7464 }
7465
7466 // Replace the TLS_base_addr instruction I with a copy from
7467 // TLSBaseAddrReg, returning the new instruction.
7468 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
7469 unsigned TLSBaseAddrReg) {
7470 MachineFunction *MF = I->getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7471 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7472 const bool is64Bit = STI.is64Bit();
7473 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7474
7475 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7476 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
7477 TII->get(TargetOpcode::COPY),
7478 is64Bit ? X86::RAX : X86::EAX)
7479 .addReg(TLSBaseAddrReg);
7480
7481 // Erase the TLS_base_addr instruction.
7482 I->eraseFromParent();
7483
7484 return Copy;
7485 }
7486
7487 // Create a virtal register in *TLSBaseAddrReg, and populate it by
7488 // inserting a copy instruction after I. Returns the new instruction.
7489 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
7490 MachineFunction *MF = I->getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7491 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7492 const bool is64Bit = STI.is64Bit();
7493 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7494
7495 // Create a virtual register for the TLS base address.
7496 MachineRegisterInfo &RegInfo = MF->getRegInfo();
7497 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7498 ? &X86::GR64RegClass
7499 : &X86::GR32RegClass);
7500
7501 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7502 MachineInstr *Next = I->getNextNode();
7503 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
7504 TII->get(TargetOpcode::COPY),
7505 *TLSBaseAddrReg)
7506 .addReg(is64Bit ? X86::RAX : X86::EAX);
7507
7508 return Copy;
7509 }
7510
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7511 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7512 return "Local Dynamic TLS Access Clean-up";
7513 }
7514
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7515 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7516 AU.setPreservesCFG();
7517 AU.addRequired<MachineDominatorTree>();
7518 MachineFunctionPass::getAnalysisUsage(AU);
7519 }
7520 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]7521}
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7522
7523char LDTLSCleanup::ID = 0;
7524FunctionPass*
7525llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }