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gerrit-public.fairphone.software / toolchain / llvm-project / e3547af7bedf5cf01cbfd38f18e7a37dda430e7f / . / llvm / lib / Target / X86 / X86SchedBroadwell.td
blob: 0aa0700975e62cf93eb4df52e10cd12d84e4cbdc [file] [log] [blame]
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1//=- X86SchedBroadwell.td - X86 Broadwell Scheduling ---------*- tablegen -*-=//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
10// This file defines the machine model for Broadwell to support instruction
11// scheduling and other instruction cost heuristics.
12//
13//===----------------------------------------------------------------------===//
14def BroadwellModel : SchedMachineModel {
15 // All x86 instructions are modeled as a single micro-op, and HW can decode 4
16 // instructions per cycle.
17 let IssueWidth = 4;
18 let MicroOpBufferSize = 192; // Based on the reorder buffer.
19 let LoadLatency = 5;
20 let MispredictPenalty = 16;
21
22 // Based on the LSD (loop-stream detector) queue size and benchmarking data.
23 let LoopMicroOpBufferSize = 50;
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]24
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]25 // This flag is set to allow the scheduler to assign a default model to
Simon Pilgrim68f9acc2017-12-12 16:12:53 +0000[diff] [blame]26 // unrecognized opcodes.
27 let CompleteModel = 0;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]28}
29
30let SchedModel = BroadwellModel in {
31
32// Broadwell can issue micro-ops to 8 different ports in one cycle.
33
34// Ports 0, 1, 5, and 6 handle all computation.
35// Port 4 gets the data half of stores. Store data can be available later than
36// the store address, but since we don't model the latency of stores, we can
37// ignore that.
38// Ports 2 and 3 are identical. They handle loads and the address half of
39// stores. Port 7 can handle address calculations.
40def BWPort0 : ProcResource<1>;
41def BWPort1 : ProcResource<1>;
42def BWPort2 : ProcResource<1>;
43def BWPort3 : ProcResource<1>;
44def BWPort4 : ProcResource<1>;
45def BWPort5 : ProcResource<1>;
46def BWPort6 : ProcResource<1>;
47def BWPort7 : ProcResource<1>;
48
49// Many micro-ops are capable of issuing on multiple ports.
50def BWPort01 : ProcResGroup<[BWPort0, BWPort1]>;
51def BWPort23 : ProcResGroup<[BWPort2, BWPort3]>;
52def BWPort237 : ProcResGroup<[BWPort2, BWPort3, BWPort7]>;
53def BWPort04 : ProcResGroup<[BWPort0, BWPort4]>;
54def BWPort05 : ProcResGroup<[BWPort0, BWPort5]>;
55def BWPort06 : ProcResGroup<[BWPort0, BWPort6]>;
56def BWPort15 : ProcResGroup<[BWPort1, BWPort5]>;
57def BWPort16 : ProcResGroup<[BWPort1, BWPort6]>;
58def BWPort56 : ProcResGroup<[BWPort5, BWPort6]>;
59def BWPort015 : ProcResGroup<[BWPort0, BWPort1, BWPort5]>;
60def BWPort056 : ProcResGroup<[BWPort0, BWPort5, BWPort6]>;
61def BWPort0156: ProcResGroup<[BWPort0, BWPort1, BWPort5, BWPort6]>;
62
63// 60 Entry Unified Scheduler
64def BWPortAny : ProcResGroup<[BWPort0, BWPort1, BWPort2, BWPort3, BWPort4,
65 BWPort5, BWPort6, BWPort7]> {
66 let BufferSize=60;
67}
68
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]69// Integer division issued on port 0.
70def BWDivider : ProcResource<1>; // Integer division issued on port 0.
71
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]72// Loads are 5 cycles, so ReadAfterLd registers needn't be available until 5
73// cycles after the memory operand.
74def : ReadAdvance<ReadAfterLd, 5>;
75
76// Many SchedWrites are defined in pairs with and without a folded load.
77// Instructions with folded loads are usually micro-fused, so they only appear
78// as two micro-ops when queued in the reservation station.
79// This multiclass defines the resource usage for variants with and without
80// folded loads.
81multiclass BWWriteResPair<X86FoldableSchedWrite SchedRW,
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]82 list<ProcResourceKind> ExePorts,
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame^]83 int Lat, list<int> Res = [1], int UOps = 1,
84 int LoadLat = 5> {
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]85 // Register variant is using a single cycle on ExePort.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]86 def : WriteRes<SchedRW, ExePorts> {
87 let Latency = Lat;
88 let ResourceCycles = Res;
89 let NumMicroOps = UOps;
90 }
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]91
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame^]92 // Memory variant also uses a cycle on port 2/3 and adds LoadLat cycles to
93 // the latency (default = 5).
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]94 def : WriteRes<SchedRW.Folded, !listconcat([BWPort23], ExePorts)> {
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame^]95 let Latency = !add(Lat, LoadLat);
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]96 let ResourceCycles = !listconcat([1], Res);
Simon Pilgrime3547af2018-03-25 10:21:19 +0000[diff] [blame^]97 let NumMicroOps = !add(UOps, 1);
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]98 }
99}
100
101// A folded store needs a cycle on port 4 for the store data, but it does not
102// need an extra port 2/3 cycle to recompute the address.
103def : WriteRes<WriteRMW, [BWPort4]>;
104
105// Arithmetic.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]106defm : BWWriteResPair<WriteALU, [BWPort0156], 1>; // Simple integer ALU op.
107defm : BWWriteResPair<WriteIMul, [BWPort1], 3>; // Integer multiplication.
108defm : BWWriteResPair<WriteIDiv, [BWPort0, BWDivider], 25, [1, 10]>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]109def : WriteRes<WriteIMulH, []> { let Latency = 3; } // Integer multiplication, high part.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]110
111def : WriteRes<WriteLEA, [BWPort15]>; // LEA instructions can't fold loads.
112
113// Integer shifts and rotates.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]114defm : BWWriteResPair<WriteShift, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]115
116// Loads, stores, and moves, not folded with other operations.
117def : WriteRes<WriteLoad, [BWPort23]> { let Latency = 5; }
118def : WriteRes<WriteStore, [BWPort237, BWPort4]>;
119def : WriteRes<WriteMove, [BWPort0156]>;
120
121// Idioms that clear a register, like xorps %xmm0, %xmm0.
122// These can often bypass execution ports completely.
123def : WriteRes<WriteZero, []>;
124
Sanjoy Das1074eb22017-12-12 19:11:31 +0000[diff] [blame]125// Treat misc copies as a move.
126def : InstRW<[WriteMove], (instrs COPY)>;
127
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]128// Branches don't produce values, so they have no latency, but they still
129// consume resources. Indirect branches can fold loads.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]130defm : BWWriteResPair<WriteJump, [BWPort06], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]131
132// Floating point. This covers both scalar and vector operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]133def : WriteRes<WriteFLoad, [BWPort23]> { let Latency = 5; }
134def : WriteRes<WriteFStore, [BWPort237, BWPort4]>;
135def : WriteRes<WriteFMove, [BWPort5]>;
136
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]137defm : BWWriteResPair<WriteFAdd, [BWPort1], 3>; // Floating point add/sub/compare.
138defm : BWWriteResPair<WriteFMul, [BWPort0], 5>; // Floating point multiplication.
139defm : BWWriteResPair<WriteFDiv, [BWPort0], 12>; // 10-14 cycles. // Floating point division.
140defm : BWWriteResPair<WriteFSqrt, [BWPort0], 15>; // Floating point square root.
141defm : BWWriteResPair<WriteFRcp, [BWPort0], 5>; // Floating point reciprocal estimate.
142defm : BWWriteResPair<WriteFRsqrt, [BWPort0], 5>; // Floating point reciprocal square root estimate.
143defm : BWWriteResPair<WriteFMA, [BWPort01], 5>; // Fused Multiply Add.
144defm : BWWriteResPair<WriteFShuffle, [BWPort5], 1>; // Floating point vector shuffles.
145defm : BWWriteResPair<WriteFBlend, [BWPort015], 1>; // Floating point vector blends.
146defm : BWWriteResPair<WriteFVarBlend, [HWPort5], 2, [2]>; // Fp vector variable blends.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]147
148// FMA Scheduling helper class.
149// class FMASC { X86FoldableSchedWrite Sched = WriteFAdd; }
150
151// Vector integer operations.
Simon Pilgrimfb7aa572018-03-15 14:45:30 +0000[diff] [blame]152def : WriteRes<WriteVecLoad, [BWPort23]> { let Latency = 5; }
153def : WriteRes<WriteVecStore, [BWPort237, BWPort4]>;
154def : WriteRes<WriteVecMove, [BWPort015]>;
155
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]156defm : BWWriteResPair<WriteVecALU, [BWPort15], 1>; // Vector integer ALU op, no logicals.
157defm : BWWriteResPair<WriteVecShift, [BWPort0], 1>; // Vector integer shifts.
158defm : BWWriteResPair<WriteVecIMul, [BWPort0], 5>; // Vector integer multiply.
159defm : BWWriteResPair<WriteShuffle, [BWPort5], 1>; // Vector shuffles.
160defm : BWWriteResPair<WriteBlend, [BWPort15], 1>; // Vector blends.
161defm : BWWriteResPair<WriteVarBlend, [BWPort5], 2, [2]>; // Vector variable blends.
162defm : BWWriteResPair<WriteMPSAD, [BWPort0, BWPort5], 6, [1, 2]>; // Vector MPSAD.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]163
164// Vector bitwise operations.
165// These are often used on both floating point and integer vectors.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]166defm : BWWriteResPair<WriteVecLogic, [BWPort015], 1>; // Vector and/or/xor.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]167
168// Conversion between integer and float.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]169defm : BWWriteResPair<WriteCvtF2I, [BWPort1], 3>; // Float -> Integer.
170defm : BWWriteResPair<WriteCvtI2F, [BWPort1], 4>; // Integer -> Float.
171defm : BWWriteResPair<WriteCvtF2F, [BWPort1], 3>; // Float -> Float size conversion.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]172
173// Strings instructions.
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]174
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]175// Packed Compare Implicit Length Strings, Return Mask
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]176def : WriteRes<WritePCmpIStrM, [BWPort0]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]177 let Latency = 11;
178 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]179 let ResourceCycles = [3];
180}
181def : WriteRes<WritePCmpIStrMLd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]182 let Latency = 16;
183 let NumMicroOps = 4;
184 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]185}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]186
187// Packed Compare Explicit Length Strings, Return Mask
188def : WriteRes<WritePCmpEStrM, [BWPort0, BWPort5, BWPort015, BWPort0156]> {
189 let Latency = 19;
190 let NumMicroOps = 9;
191 let ResourceCycles = [4,3,1,1];
192}
193def : WriteRes<WritePCmpEStrMLd, [BWPort0, BWPort5, BWPort23, BWPort015, BWPort0156]> {
194 let Latency = 24;
195 let NumMicroOps = 10;
196 let ResourceCycles = [4,3,1,1,1];
197}
198
199// Packed Compare Implicit Length Strings, Return Index
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]200def : WriteRes<WritePCmpIStrI, [BWPort0]> {
201 let Latency = 11;
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]202 let NumMicroOps = 3;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]203 let ResourceCycles = [3];
204}
205def : WriteRes<WritePCmpIStrILd, [BWPort0, BWPort23]> {
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]206 let Latency = 16;
207 let NumMicroOps = 4;
208 let ResourceCycles = [3,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]209}
Simon Pilgrim53b2c332018-03-22 14:56:18 +0000[diff] [blame]210
211// Packed Compare Explicit Length Strings, Return Index
212def : WriteRes<WritePCmpEStrI, [BWPort0, BWPort5, BWPort0156]> {
213 let Latency = 18;
214 let NumMicroOps = 8;
215 let ResourceCycles = [4,3,1];
216}
217def : WriteRes<WritePCmpEStrILd, [BWPort0, BWPort5, BWPort23, BWPort0156]> {
218 let Latency = 23;
219 let NumMicroOps = 9;
220 let ResourceCycles = [4,3,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]221}
222
223// AES instructions.
224def : WriteRes<WriteAESDecEnc, [BWPort5]> { // Decryption, encryption.
225 let Latency = 7;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]226 let NumMicroOps = 1;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]227 let ResourceCycles = [1];
228}
229def : WriteRes<WriteAESDecEncLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]230 let Latency = 12;
231 let NumMicroOps = 2;
232 let ResourceCycles = [1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]233}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]234
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]235def : WriteRes<WriteAESIMC, [BWPort5]> { // InvMixColumn.
236 let Latency = 14;
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]237 let NumMicroOps = 2;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]238 let ResourceCycles = [2];
239}
240def : WriteRes<WriteAESIMCLd, [BWPort5, BWPort23]> {
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]241 let Latency = 19;
242 let NumMicroOps = 3;
243 let ResourceCycles = [2,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]244}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]245
246def : WriteRes<WriteAESKeyGen, [BWPort0, BWPort5, BWPort015]> { // Key Generation.
247 let Latency = 29;
248 let NumMicroOps = 11;
249 let ResourceCycles = [2,7,2];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]250}
Simon Pilgrim7684e052018-03-22 13:18:08 +0000[diff] [blame]251def : WriteRes<WriteAESKeyGenLd, [BWPort0, BWPort5, BWPort23, BWPort015]> {
252 let Latency = 33;
253 let NumMicroOps = 11;
254 let ResourceCycles = [2,7,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]255}
256
257// Carry-less multiplication instructions.
Simon Pilgrim3b2ff1f2018-03-22 13:37:30 +0000[diff] [blame]258defm : BWWriteResPair<WriteCLMul, [BWPort0], 5>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]259
260// Catch-all for expensive system instructions.
261def : WriteRes<WriteSystem, [BWPort0156]> { let Latency = 100; } // def WriteSystem : SchedWrite;
262
263// AVX2.
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]264defm : BWWriteResPair<WriteFShuffle256, [BWPort5], 3>; // Fp 256-bit width vector shuffles.
265defm : BWWriteResPair<WriteShuffle256, [BWPort5], 3>; // 256-bit width vector shuffles.
266defm : BWWriteResPair<WriteVarVecShift, [BWPort0, BWPort5], 2, [2, 1]>; // Variable vector shifts.
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]267
268// Old microcoded instructions that nobody use.
269def : WriteRes<WriteMicrocoded, [BWPort0156]> { let Latency = 100; } // def WriteMicrocoded : SchedWrite;
270
271// Fence instructions.
272def : WriteRes<WriteFence, [BWPort23, BWPort4]>;
273
274// Nop, not very useful expect it provides a model for nops!
275def : WriteRes<WriteNop, []>;
276
277////////////////////////////////////////////////////////////////////////////////
278// Horizontal add/sub instructions.
279////////////////////////////////////////////////////////////////////////////////
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]280
Simon Pilgrim30c38c32018-03-19 14:46:07 +0000[diff] [blame]281defm : BWWriteResPair<WriteFHAdd, [BWPort1], 3>;
282defm : BWWriteResPair<WritePHAdd, [BWPort15], 1>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]283
284// Remaining instrs.
285
286def BWWriteResGroup1 : SchedWriteRes<[BWPort0]> {
287 let Latency = 1;
288 let NumMicroOps = 1;
289 let ResourceCycles = [1];
290}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]291def: InstRW<[BWWriteResGroup1], (instregex "MMX_MOVD64from64rr",
292 "MMX_MOVD64grr",
293 "MMX_PMOVMSKBrr",
294 "MMX_PSLLDri",
295 "MMX_PSLLDrr",
296 "MMX_PSLLQri",
297 "MMX_PSLLQrr",
298 "MMX_PSLLWri",
299 "MMX_PSLLWrr",
300 "MMX_PSRADri",
301 "MMX_PSRADrr",
302 "MMX_PSRAWri",
303 "MMX_PSRAWrr",
304 "MMX_PSRLDri",
305 "MMX_PSRLDrr",
306 "MMX_PSRLQri",
307 "MMX_PSRLQrr",
308 "MMX_PSRLWri",
309 "MMX_PSRLWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]310 "(V?)MOVPDI2DIrr",
311 "(V?)MOVPQIto64rr",
312 "(V?)PSLLD(Y?)ri",
313 "(V?)PSLLQ(Y?)ri",
314 "VPSLLVQ(Y?)rr",
315 "(V?)PSLLW(Y?)ri",
316 "(V?)PSRAD(Y?)ri",
317 "(V?)PSRAW(Y?)ri",
318 "(V?)PSRLD(Y?)ri",
319 "(V?)PSRLQ(Y?)ri",
320 "VPSRLVQ(Y?)rr",
321 "(V?)PSRLW(Y?)ri",
322 "VTESTPD(Y?)rr",
323 "VTESTPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]324
325def BWWriteResGroup2 : SchedWriteRes<[BWPort1]> {
326 let Latency = 1;
327 let NumMicroOps = 1;
328 let ResourceCycles = [1];
329}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]330def: InstRW<[BWWriteResGroup2], (instregex "COMP_FST0r",
331 "COM_FST0r",
332 "UCOM_FPr",
333 "UCOM_Fr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]334
335def BWWriteResGroup3 : SchedWriteRes<[BWPort5]> {
336 let Latency = 1;
337 let NumMicroOps = 1;
338 let ResourceCycles = [1];
339}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]340def: InstRW<[BWWriteResGroup3], (instregex "MMX_MOVD64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]341 "MMX_MOVD64to64rr",
342 "MMX_MOVQ2DQrr",
343 "MMX_PALIGNRrri",
344 "MMX_PSHUFBrr",
345 "MMX_PSHUFWri",
346 "MMX_PUNPCKHBWirr",
347 "MMX_PUNPCKHDQirr",
348 "MMX_PUNPCKHWDirr",
349 "MMX_PUNPCKLBWirr",
350 "MMX_PUNPCKLDQirr",
351 "MMX_PUNPCKLWDirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]352 "(V?)ANDNPD(Y?)rr",
353 "(V?)ANDNPS(Y?)rr",
354 "(V?)ANDPD(Y?)rr",
355 "(V?)ANDPS(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]356 "VBROADCASTSSrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]357 "(V?)INSERTPSrr",
358 "(V?)MOV64toPQIrr",
359 "(V?)MOVAPD(Y?)rr",
360 "(V?)MOVAPS(Y?)rr",
361 "(V?)MOVDDUP(Y?)rr",
362 "(V?)MOVDI2PDIrr",
363 "(V?)MOVHLPSrr",
364 "(V?)MOVLHPSrr",
365 "(V?)MOVSDrr",
366 "(V?)MOVSHDUP(Y?)rr",
367 "(V?)MOVSLDUP(Y?)rr",
368 "(V?)MOVSSrr",
369 "(V?)MOVUPD(Y?)rr",
370 "(V?)MOVUPS(Y?)rr",
371 "(V?)ORPD(Y?)rr",
372 "(V?)ORPS(Y?)rr",
373 "(V?)PACKSSDW(Y?)rr",
374 "(V?)PACKSSWB(Y?)rr",
375 "(V?)PACKUSDW(Y?)rr",
376 "(V?)PACKUSWB(Y?)rr",
377 "(V?)PALIGNR(Y?)rri",
378 "(V?)PBLENDW(Y?)rri",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]379 "VPBROADCASTDrr",
380 "VPBROADCASTQrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]381 "VPERMILPD(Y?)ri",
382 "VPERMILPD(Y?)rr",
383 "VPERMILPS(Y?)ri",
384 "VPERMILPS(Y?)rr",
385 "(V?)PMOVSXBDrr",
386 "(V?)PMOVSXBQrr",
387 "(V?)PMOVSXBWrr",
388 "(V?)PMOVSXDQrr",
389 "(V?)PMOVSXWDrr",
390 "(V?)PMOVSXWQrr",
391 "(V?)PMOVZXBDrr",
392 "(V?)PMOVZXBQrr",
393 "(V?)PMOVZXBWrr",
394 "(V?)PMOVZXDQrr",
395 "(V?)PMOVZXWDrr",
396 "(V?)PMOVZXWQrr",
397 "(V?)PSHUFB(Y?)rr",
398 "(V?)PSHUFD(Y?)ri",
399 "(V?)PSHUFHW(Y?)ri",
400 "(V?)PSHUFLW(Y?)ri",
401 "(V?)PSLLDQ(Y?)ri",
402 "(V?)PSRLDQ(Y?)ri",
403 "(V?)PUNPCKHBW(Y?)rr",
404 "(V?)PUNPCKHDQ(Y?)rr",
405 "(V?)PUNPCKHQDQ(Y?)rr",
406 "(V?)PUNPCKHWD(Y?)rr",
407 "(V?)PUNPCKLBW(Y?)rr",
408 "(V?)PUNPCKLDQ(Y?)rr",
409 "(V?)PUNPCKLQDQ(Y?)rr",
410 "(V?)PUNPCKLWD(Y?)rr",
411 "(V?)SHUFPD(Y?)rri",
412 "(V?)SHUFPS(Y?)rri",
413 "(V?)UNPCKHPD(Y?)rr",
414 "(V?)UNPCKHPS(Y?)rr",
415 "(V?)UNPCKLPD(Y?)rr",
416 "(V?)UNPCKLPS(Y?)rr",
417 "(V?)XORPD(Y?)rr",
418 "(V?)XORPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]419
420def BWWriteResGroup4 : SchedWriteRes<[BWPort6]> {
421 let Latency = 1;
422 let NumMicroOps = 1;
423 let ResourceCycles = [1];
424}
425def: InstRW<[BWWriteResGroup4], (instregex "JMP(16|32|64)r")>;
426
427def BWWriteResGroup5 : SchedWriteRes<[BWPort01]> {
428 let Latency = 1;
429 let NumMicroOps = 1;
430 let ResourceCycles = [1];
431}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]432def: InstRW<[BWWriteResGroup5], (instregex "FINCSTP",
433 "FNOP")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]434
435def BWWriteResGroup6 : SchedWriteRes<[BWPort06]> {
436 let Latency = 1;
437 let NumMicroOps = 1;
438 let ResourceCycles = [1];
439}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]440def: InstRW<[BWWriteResGroup6], (instregex "ADC(16|32|64)ri",
441 "ADC(16|32|64)i",
442 "ADC(8|16|32|64)rr",
443 "ADCX(32|64)rr",
444 "ADOX(32|64)rr",
445 "BT(16|32|64)ri8",
446 "BT(16|32|64)rr",
447 "BTC(16|32|64)ri8",
448 "BTC(16|32|64)rr",
449 "BTR(16|32|64)ri8",
450 "BTR(16|32|64)rr",
451 "BTS(16|32|64)ri8",
452 "BTS(16|32|64)rr",
453 "CDQ",
454 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rr",
455 "CQO",
456 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_1",
457 "J(A|AE|B|BE|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)_4",
458 "JMP_1",
459 "JMP_4",
460 "RORX(32|64)ri",
461 "SAR(8|16|32|64)r1",
462 "SAR(8|16|32|64)ri",
463 "SARX(32|64)rr",
464 "SBB(16|32|64)ri",
465 "SBB(16|32|64)i",
466 "SBB(8|16|32|64)rr",
467 "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)r",
468 "SHL(8|16|32|64)r1",
469 "SHL(8|16|32|64)ri",
470 "SHLX(32|64)rr",
471 "SHR(8|16|32|64)r1",
472 "SHR(8|16|32|64)ri",
473 "SHRX(32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]474
475def BWWriteResGroup7 : SchedWriteRes<[BWPort15]> {
476 let Latency = 1;
477 let NumMicroOps = 1;
478 let ResourceCycles = [1];
479}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]480def: InstRW<[BWWriteResGroup7], (instregex "ANDN(32|64)rr",
481 "BLSI(32|64)rr",
482 "BLSMSK(32|64)rr",
483 "BLSR(32|64)rr",
484 "BZHI(32|64)rr",
485 "LEA(16|32|64)(_32)?r",
486 "MMX_PABSBrr",
487 "MMX_PABSDrr",
488 "MMX_PABSWrr",
489 "MMX_PADDBirr",
490 "MMX_PADDDirr",
491 "MMX_PADDQirr",
492 "MMX_PADDSBirr",
493 "MMX_PADDSWirr",
494 "MMX_PADDUSBirr",
495 "MMX_PADDUSWirr",
496 "MMX_PADDWirr",
497 "MMX_PAVGBirr",
498 "MMX_PAVGWirr",
499 "MMX_PCMPEQBirr",
500 "MMX_PCMPEQDirr",
501 "MMX_PCMPEQWirr",
502 "MMX_PCMPGTBirr",
503 "MMX_PCMPGTDirr",
504 "MMX_PCMPGTWirr",
505 "MMX_PMAXSWirr",
506 "MMX_PMAXUBirr",
507 "MMX_PMINSWirr",
508 "MMX_PMINUBirr",
509 "MMX_PSIGNBrr",
510 "MMX_PSIGNDrr",
511 "MMX_PSIGNWrr",
512 "MMX_PSUBBirr",
513 "MMX_PSUBDirr",
514 "MMX_PSUBQirr",
515 "MMX_PSUBSBirr",
516 "MMX_PSUBSWirr",
517 "MMX_PSUBUSBirr",
518 "MMX_PSUBUSWirr",
519 "MMX_PSUBWirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]520 "(V?)PABSB(Y?)rr",
521 "(V?)PABSD(Y?)rr",
522 "(V?)PABSW(Y?)rr",
523 "(V?)PADDB(Y?)rr",
524 "(V?)PADDD(Y?)rr",
525 "(V?)PADDQ(Y?)rr",
526 "(V?)PADDSB(Y?)rr",
527 "(V?)PADDSW(Y?)rr",
528 "(V?)PADDUSB(Y?)rr",
529 "(V?)PADDUSW(Y?)rr",
530 "(V?)PADDW(Y?)rr",
531 "(V?)PAVGB(Y?)rr",
532 "(V?)PAVGW(Y?)rr",
533 "(V?)PCMPEQB(Y?)rr",
534 "(V?)PCMPEQD(Y?)rr",
535 "(V?)PCMPEQQ(Y?)rr",
536 "(V?)PCMPEQW(Y?)rr",
537 "(V?)PCMPGTB(Y?)rr",
538 "(V?)PCMPGTD(Y?)rr",
539 "(V?)PCMPGTW(Y?)rr",
540 "(V?)PMAXSB(Y?)rr",
541 "(V?)PMAXSD(Y?)rr",
542 "(V?)PMAXSW(Y?)rr",
543 "(V?)PMAXUB(Y?)rr",
544 "(V?)PMAXUD(Y?)rr",
545 "(V?)PMAXUW(Y?)rr",
546 "(V?)PMINSB(Y?)rr",
547 "(V?)PMINSD(Y?)rr",
548 "(V?)PMINSW(Y?)rr",
549 "(V?)PMINUB(Y?)rr",
550 "(V?)PMINUD(Y?)rr",
551 "(V?)PMINUW(Y?)rr",
552 "(V?)PSIGNB(Y?)rr",
553 "(V?)PSIGND(Y?)rr",
554 "(V?)PSIGNW(Y?)rr",
555 "(V?)PSUBB(Y?)rr",
556 "(V?)PSUBD(Y?)rr",
557 "(V?)PSUBQ(Y?)rr",
558 "(V?)PSUBSB(Y?)rr",
559 "(V?)PSUBSW(Y?)rr",
560 "(V?)PSUBUSB(Y?)rr",
561 "(V?)PSUBUSW(Y?)rr",
562 "(V?)PSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]563
564def BWWriteResGroup8 : SchedWriteRes<[BWPort015]> {
565 let Latency = 1;
566 let NumMicroOps = 1;
567 let ResourceCycles = [1];
568}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]569def: InstRW<[BWWriteResGroup8], (instregex "MMX_MOVQ64rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]570 "MMX_PANDNirr",
571 "MMX_PANDirr",
572 "MMX_PORirr",
573 "MMX_PXORirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]574 "(V?)BLENDPD(Y?)rri",
575 "(V?)BLENDPS(Y?)rri",
576 "(V?)MOVDQA(Y?)rr",
577 "(V?)MOVDQU(Y?)rr",
578 "(V?)MOVPQI2QIrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]579 "VMOVZPQILo2PQIrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]580 "(V?)PANDN(Y?)rr",
581 "(V?)PAND(Y?)rr",
582 "VPBLENDD(Y?)rri",
583 "(V?)POR(Y?)rr",
584 "(V?)PXOR(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]585
586def BWWriteResGroup9 : SchedWriteRes<[BWPort0156]> {
587 let Latency = 1;
588 let NumMicroOps = 1;
589 let ResourceCycles = [1];
590}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]591def: InstRW<[BWWriteResGroup9], (instrs CWDE)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]592def: InstRW<[BWWriteResGroup9], (instregex "ADD(8|16|32|64)ri",
593 "ADD(8|16|32|64)rr",
594 "ADD(8|16|32|64)i",
595 "AND(8|16|32|64)ri",
596 "AND(8|16|32|64)rr",
597 "AND(8|16|32|64)i",
598 "CBW",
599 "CLC",
600 "CMC",
601 "CMP(8|16|32|64)ri",
602 "CMP(8|16|32|64)rr",
603 "CMP(8|16|32|64)i",
604 "DEC(8|16|32|64)r",
605 "INC(8|16|32|64)r",
606 "LAHF",
607 "MOV(8|16|32|64)rr",
608 "MOV(8|16|32|64)ri",
609 "MOVSX(16|32|64)rr16",
610 "MOVSX(16|32|64)rr32",
611 "MOVSX(16|32|64)rr8",
612 "MOVZX(16|32|64)rr16",
613 "MOVZX(16|32|64)rr8",
614 "NEG(8|16|32|64)r",
615 "NOOP",
616 "NOT(8|16|32|64)r",
617 "OR(8|16|32|64)ri",
618 "OR(8|16|32|64)rr",
619 "OR(8|16|32|64)i",
620 "SAHF",
621 "SGDT64m",
622 "SIDT64m",
623 "SLDT64m",
624 "SMSW16m",
625 "STC",
626 "STRm",
627 "SUB(8|16|32|64)ri",
628 "SUB(8|16|32|64)rr",
629 "SUB(8|16|32|64)i",
630 "SYSCALL",
631 "TEST(8|16|32|64)rr",
632 "TEST(8|16|32|64)i",
633 "TEST(8|16|32|64)ri",
634 "XCHG(16|32|64)rr",
635 "XOR(8|16|32|64)ri",
636 "XOR(8|16|32|64)rr",
637 "XOR(8|16|32|64)i")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]638
639def BWWriteResGroup10 : SchedWriteRes<[BWPort4,BWPort237]> {
640 let Latency = 1;
641 let NumMicroOps = 2;
642 let ResourceCycles = [1,1];
643}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]644def: InstRW<[BWWriteResGroup10], (instregex "FBSTPm",
645 "MMX_MOVD64from64rm",
646 "MMX_MOVD64mr",
647 "MMX_MOVNTQmr",
648 "MMX_MOVQ64mr",
649 "MOV(16|32|64)mr",
650 "MOV8mi",
651 "MOV8mr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]652 "MOVNTI_64mr",
653 "MOVNTImr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]654 "ST_FP32m",
655 "ST_FP64m",
656 "ST_FP80m",
657 "VEXTRACTF128mr",
658 "VEXTRACTI128mr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]659 "(V?)MOVAPD(Y?)mr",
660 "(V?)MOVAPS(Y?)mr",
661 "(V?)MOVDQA(Y?)mr",
662 "(V?)MOVDQU(Y?)mr",
663 "(V?)MOVHPDmr",
664 "(V?)MOVHPSmr",
665 "(V?)MOVLPDmr",
666 "(V?)MOVLPSmr",
667 "(V?)MOVNTDQ(V?)mr",
668 "(V?)MOVNTPD(V?)mr",
669 "(V?)MOVNTPS(V?)mr",
670 "(V?)MOVPDI2DImr",
671 "(V?)MOVPQI2QImr",
672 "(V?)MOVPQIto64mr",
673 "(V?)MOVSDmr",
674 "(V?)MOVSSmr",
675 "(V?)MOVUPD(Y?)mr",
676 "(V?)MOVUPS(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]677
678def BWWriteResGroup11 : SchedWriteRes<[BWPort5]> {
679 let Latency = 2;
680 let NumMicroOps = 2;
681 let ResourceCycles = [2];
682}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]683def: InstRW<[BWWriteResGroup11], (instregex "BLENDVPDrr0",
684 "BLENDVPSrr0",
685 "MMX_PINSRWrr",
686 "PBLENDVBrr0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]687 "VBLENDVPD(Y?)rr",
688 "VBLENDVPS(Y?)rr",
689 "VPBLENDVB(Y?)rr",
690 "(V?)PINSRBrr",
691 "(V?)PINSRDrr",
692 "(V?)PINSRQrr",
693 "(V?)PINSRWrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]694
695def BWWriteResGroup12 : SchedWriteRes<[BWPort01]> {
696 let Latency = 2;
697 let NumMicroOps = 2;
698 let ResourceCycles = [2];
699}
700def: InstRW<[BWWriteResGroup12], (instregex "FDECSTP")>;
701
702def BWWriteResGroup13 : SchedWriteRes<[BWPort06]> {
703 let Latency = 2;
704 let NumMicroOps = 2;
705 let ResourceCycles = [2];
706}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]707def: InstRW<[BWWriteResGroup13], (instregex "ROL(8|16|32|64)r1",
708 "ROL(8|16|32|64)ri",
709 "ROR(8|16|32|64)r1",
710 "ROR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]711
712def BWWriteResGroup14 : SchedWriteRes<[BWPort0156]> {
713 let Latency = 2;
714 let NumMicroOps = 2;
715 let ResourceCycles = [2];
716}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]717def: InstRW<[BWWriteResGroup14], (instregex "LFENCE",
718 "MFENCE",
719 "WAIT",
720 "XGETBV")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]721
722def BWWriteResGroup15 : SchedWriteRes<[BWPort0,BWPort5]> {
723 let Latency = 2;
724 let NumMicroOps = 2;
725 let ResourceCycles = [1,1];
726}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]727def: InstRW<[BWWriteResGroup15], (instregex "MMX_PEXTRWrr",
728 "VCVTPH2PS(Y?)rr",
729 "(V?)CVTPS2PDrr",
730 "(V?)CVTSS2SDrr",
731 "(V?)EXTRACTPSrr",
732 "(V?)PEXTRBrr",
733 "(V?)PEXTRDrr",
734 "(V?)PEXTRQrr",
735 "(V?)PEXTRWrr",
736 "(V?)PSLLDrr",
737 "(V?)PSLLQrr",
738 "(V?)PSLLWrr",
739 "(V?)PSRADrr",
740 "(V?)PSRAWrr",
741 "(V?)PSRLDrr",
742 "(V?)PSRLQrr",
743 "(V?)PSRLWrr",
744 "(V?)PTESTrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]745
746def BWWriteResGroup16 : SchedWriteRes<[BWPort6,BWPort0156]> {
747 let Latency = 2;
748 let NumMicroOps = 2;
749 let ResourceCycles = [1,1];
750}
751def: InstRW<[BWWriteResGroup16], (instregex "CLFLUSH")>;
752
753def BWWriteResGroup17 : SchedWriteRes<[BWPort01,BWPort015]> {
754 let Latency = 2;
755 let NumMicroOps = 2;
756 let ResourceCycles = [1,1];
757}
758def: InstRW<[BWWriteResGroup17], (instregex "MMX_MOVDQ2Qrr")>;
759
760def BWWriteResGroup18 : SchedWriteRes<[BWPort237,BWPort0156]> {
761 let Latency = 2;
762 let NumMicroOps = 2;
763 let ResourceCycles = [1,1];
764}
765def: InstRW<[BWWriteResGroup18], (instregex "SFENCE")>;
766
767def BWWriteResGroup19 : SchedWriteRes<[BWPort06,BWPort15]> {
768 let Latency = 2;
769 let NumMicroOps = 2;
770 let ResourceCycles = [1,1];
771}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]772def: InstRW<[BWWriteResGroup19], (instregex "BEXTR(32|64)rr",
773 "BSWAP(16|32|64)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]774
775def BWWriteResGroup20 : SchedWriteRes<[BWPort06,BWPort0156]> {
776 let Latency = 2;
777 let NumMicroOps = 2;
778 let ResourceCycles = [1,1];
779}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]780def: InstRW<[BWWriteResGroup20], (instrs CWD)>;
Craig Topperb4c78732018-03-19 19:00:32 +0000[diff] [blame]781def: InstRW<[BWWriteResGroup20], (instrs JCXZ, JECXZ, JRCXZ)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]782def: InstRW<[BWWriteResGroup20], (instregex "ADC8i8",
783 "ADC8ri",
784 "CMOV(A|BE)(16|32|64)rr",
785 "SBB8i8",
786 "SBB8ri",
787 "SET(A|BE)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]788
789def BWWriteResGroup21 : SchedWriteRes<[BWPort4,BWPort5,BWPort237]> {
790 let Latency = 2;
791 let NumMicroOps = 3;
792 let ResourceCycles = [1,1,1];
793}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]794def: InstRW<[BWWriteResGroup21], (instregex "(V?)EXTRACTPSmr",
795 "(V?)PEXTRBmr",
796 "(V?)PEXTRDmr",
797 "(V?)PEXTRQmr",
798 "(V?)PEXTRWmr",
799 "(V?)STMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]800
801def BWWriteResGroup22 : SchedWriteRes<[BWPort4,BWPort6,BWPort237]> {
802 let Latency = 2;
803 let NumMicroOps = 3;
804 let ResourceCycles = [1,1,1];
805}
806def: InstRW<[BWWriteResGroup22], (instregex "FNSTCW16m")>;
807
808def BWWriteResGroup23 : SchedWriteRes<[BWPort4,BWPort237,BWPort06]> {
809 let Latency = 2;
810 let NumMicroOps = 3;
811 let ResourceCycles = [1,1,1];
812}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]813def: InstRW<[BWWriteResGroup23], (instregex "SET(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]814
815def BWWriteResGroup24 : SchedWriteRes<[BWPort4,BWPort237,BWPort15]> {
816 let Latency = 2;
817 let NumMicroOps = 3;
818 let ResourceCycles = [1,1,1];
819}
820def: InstRW<[BWWriteResGroup24], (instregex "MOVBE(16|32|64)mr")>;
821
822def BWWriteResGroup25 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
823 let Latency = 2;
824 let NumMicroOps = 3;
825 let ResourceCycles = [1,1,1];
826}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]827def: InstRW<[BWWriteResGroup25], (instrs PUSH16r, PUSH32r, PUSH64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]828def: InstRW<[BWWriteResGroup25], (instregex "PUSH(16|32|64)rmr",
829 "PUSH64i8",
830 "STOSB",
831 "STOSL",
832 "STOSQ",
833 "STOSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]834
835def BWWriteResGroup26 : SchedWriteRes<[BWPort0]> {
836 let Latency = 3;
837 let NumMicroOps = 1;
838 let ResourceCycles = [1];
839}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]840def: InstRW<[BWWriteResGroup26], (instregex "(V?)MOVMSKPD(Y?)rr",
841 "(V?)MOVMSKPS(Y?)rr",
842 "(V?)PMOVMSKB(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]843
844def BWWriteResGroup27 : SchedWriteRes<[BWPort1]> {
845 let Latency = 3;
846 let NumMicroOps = 1;
847 let ResourceCycles = [1];
848}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]849def: InstRW<[BWWriteResGroup27], (instrs IMUL16rr, IMUL32rr, IMUL32rri, IMUL32rri8, IMUL64rr, IMUL64rri32, IMUL64rri8)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]850def: InstRW<[BWWriteResGroup27], (instrs IMUL8r, MUL8r)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]851def: InstRW<[BWWriteResGroup27], (instregex "ADD_FPrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]852 "ADD_FST0r",
853 "ADD_FrST0",
854 "BSF(16|32|64)rr",
855 "BSR(16|32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]856 "LZCNT(16|32|64)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]857 "MMX_CVTPI2PSirr",
858 "PDEP(32|64)rr",
859 "PEXT(32|64)rr",
860 "POPCNT(16|32|64)rr",
861 "SHLD(16|32|64)rri8",
862 "SHRD(16|32|64)rri8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]863 "SUBR_FPrST0",
864 "SUBR_FST0r",
865 "SUBR_FrST0",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]866 "SUB_FPrST0",
867 "SUB_FST0r",
868 "SUB_FrST0",
869 "TZCNT(16|32|64)rr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]870 "(V?)ADDPD(Y?)rr",
871 "(V?)ADDPS(Y?)rr",
872 "(V?)ADDSDrr",
873 "(V?)ADDSSrr",
874 "(V?)ADDSUBPD(Y?)rr",
875 "(V?)ADDSUBPS(Y?)rr",
876 "(V?)CMPPD(Y?)rri",
877 "(V?)CMPPS(Y?)rri",
878 "(V?)CMPSDrr",
879 "(V?)CMPSSrr",
880 "(V?)COMISDrr",
881 "(V?)COMISSrr",
882 "(V?)CVTDQ2PS(Y?)rr",
883 "(V?)CVTPS2DQ(Y?)rr",
884 "(V?)CVTTPS2DQ(Y?)rr",
885 "(V?)MAX(C?)PD(Y?)rr",
886 "(V?)MAX(C?)PS(Y?)rr",
887 "(V?)MAX(C?)SDrr",
888 "(V?)MAX(C?)SSrr",
889 "(V?)MIN(C?)PD(Y?)rr",
890 "(V?)MIN(C?)PS(Y?)rr",
891 "(V?)MIN(C?)SDrr",
892 "(V?)MIN(C?)SSrr",
893 "(V?)SUBPD(Y?)rr",
894 "(V?)SUBPS(Y?)rr",
895 "(V?)SUBSDrr",
896 "(V?)SUBSSrr",
897 "(V?)UCOMISDrr",
898 "(V?)UCOMISSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]899
900def BWWriteResGroup27_16 : SchedWriteRes<[BWPort1, BWPort0156]> {
901 let Latency = 3;
902 let NumMicroOps = 2;
903 let ResourceCycles = [1,1];
904}
Clement Courbet327fac42018-03-07 08:14:02 +0000[diff] [blame]905def: InstRW<[BWWriteResGroup27_16], (instrs IMUL16rri, IMUL16rri8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]906
907def BWWriteResGroup28 : SchedWriteRes<[BWPort5]> {
908 let Latency = 3;
909 let NumMicroOps = 1;
910 let ResourceCycles = [1];
911}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]912def: InstRW<[BWWriteResGroup28], (instregex "VBROADCASTSDYrr",
913 "VBROADCASTSSYrr",
914 "VEXTRACTF128rr",
915 "VEXTRACTI128rr",
916 "VINSERTF128rr",
917 "VINSERTI128rr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]918 "VPBROADCASTB(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]919 "VPBROADCASTDYrr",
920 "VPBROADCASTQYrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]921 "VPBROADCASTW(Y?)rr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]922 "VPERM2F128rr",
923 "VPERM2I128rr",
924 "VPERMDYrr",
925 "VPERMPDYri",
926 "VPERMPSYrr",
927 "VPERMQYri",
928 "VPMOVSXBDYrr",
929 "VPMOVSXBQYrr",
930 "VPMOVSXBWYrr",
931 "VPMOVSXDQYrr",
932 "VPMOVSXWDYrr",
933 "VPMOVSXWQYrr",
934 "VPMOVZXBDYrr",
935 "VPMOVZXBQYrr",
936 "VPMOVZXBWYrr",
937 "VPMOVZXDQYrr",
938 "VPMOVZXWDYrr",
939 "VPMOVZXWQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]940
941def BWWriteResGroup29 : SchedWriteRes<[BWPort01]> {
942 let Latency = 3;
943 let NumMicroOps = 1;
944 let ResourceCycles = [1];
945}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]946def: InstRW<[BWWriteResGroup29], (instregex "(V?)MULPD(Y?)rr",
947 "(V?)MULPS(Y?)rr",
948 "(V?)MULSDrr",
949 "(V?)MULSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]950
951def BWWriteResGroup30 : SchedWriteRes<[BWPort0156]> {
952 let Latency = 3;
953 let NumMicroOps = 3;
954 let ResourceCycles = [3];
955}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]956def: InstRW<[BWWriteResGroup30], (instregex "XADD(8|16|32|64)rr",
957 "XCHG8rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]958
959def BWWriteResGroup31 : SchedWriteRes<[BWPort0,BWPort5]> {
960 let Latency = 3;
961 let NumMicroOps = 3;
962 let ResourceCycles = [2,1];
963}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]964def: InstRW<[BWWriteResGroup31], (instregex "VPSLLVD(Y?)rr",
965 "VPSRAVD(Y?)rr",
966 "VPSRLVD(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]967
968def BWWriteResGroup32 : SchedWriteRes<[BWPort5,BWPort15]> {
969 let Latency = 3;
970 let NumMicroOps = 3;
971 let ResourceCycles = [2,1];
972}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]973def: InstRW<[BWWriteResGroup32], (instregex "MMX_PHADDDrr",
974 "MMX_PHADDSWrr",
975 "MMX_PHADDWrr",
976 "MMX_PHSUBDrr",
977 "MMX_PHSUBSWrr",
978 "MMX_PHSUBWrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]979 "(V?)PHADDD(Y?)rr",
980 "(V?)PHADDSW(Y?)rr",
981 "(V?)PHADDW(Y?)rr",
982 "(V?)PHSUBD(Y?)rr",
983 "(V?)PHSUBSW(Y?)rr",
984 "(V?)PHSUBW(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]985
986def BWWriteResGroup33 : SchedWriteRes<[BWPort5,BWPort0156]> {
987 let Latency = 3;
988 let NumMicroOps = 3;
989 let ResourceCycles = [2,1];
990}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]991def: InstRW<[BWWriteResGroup33], (instregex "MMX_PACKSSDWirr",
992 "MMX_PACKSSWBirr",
993 "MMX_PACKUSWBirr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]994
995def BWWriteResGroup34 : SchedWriteRes<[BWPort6,BWPort0156]> {
996 let Latency = 3;
997 let NumMicroOps = 3;
998 let ResourceCycles = [1,2];
999}
1000def: InstRW<[BWWriteResGroup34], (instregex "CLD")>;
1001
1002def BWWriteResGroup35 : SchedWriteRes<[BWPort06,BWPort0156]> {
1003 let Latency = 3;
1004 let NumMicroOps = 3;
1005 let ResourceCycles = [1,2];
1006}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1007def: InstRW<[BWWriteResGroup35], (instregex "RCL(8|16|32|64)r1",
1008 "RCL(8|16|32|64)ri",
1009 "RCR(8|16|32|64)r1",
1010 "RCR(8|16|32|64)ri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1011
1012def BWWriteResGroup36 : SchedWriteRes<[BWPort06,BWPort0156]> {
1013 let Latency = 3;
1014 let NumMicroOps = 3;
1015 let ResourceCycles = [2,1];
1016}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1017def: InstRW<[BWWriteResGroup36], (instregex "ROL(8|16|32|64)rCL",
1018 "ROR(8|16|32|64)rCL",
1019 "SAR(8|16|32|64)rCL",
1020 "SHL(8|16|32|64)rCL",
1021 "SHR(8|16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1022
1023def BWWriteResGroup37 : SchedWriteRes<[BWPort4,BWPort6,BWPort237,BWPort0156]> {
1024 let Latency = 3;
1025 let NumMicroOps = 4;
1026 let ResourceCycles = [1,1,1,1];
1027}
1028def: InstRW<[BWWriteResGroup37], (instregex "CALL(16|32|64)r")>;
1029
1030def BWWriteResGroup38 : SchedWriteRes<[BWPort4,BWPort237,BWPort06,BWPort0156]> {
1031 let Latency = 3;
1032 let NumMicroOps = 4;
1033 let ResourceCycles = [1,1,1,1];
1034}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1035def: InstRW<[BWWriteResGroup38], (instregex "CALL64pcrel32",
1036 "SET(A|BE)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1037
1038def BWWriteResGroup39 : SchedWriteRes<[BWPort0,BWPort1]> {
1039 let Latency = 4;
1040 let NumMicroOps = 2;
1041 let ResourceCycles = [1,1];
1042}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1043def: InstRW<[BWWriteResGroup39], (instregex "(V?)CVTSD2SI64rr",
1044 "(V?)CVTSD2SIrr",
1045 "(V?)CVTSS2SI64rr",
1046 "(V?)CVTSS2SIrr",
1047 "(V?)CVTTSD2SI64rr",
1048 "(V?)CVTTSD2SIrr",
1049 "(V?)CVTTSS2SI64rr",
1050 "(V?)CVTTSS2SIrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1051
1052def BWWriteResGroup40 : SchedWriteRes<[BWPort0,BWPort5]> {
1053 let Latency = 4;
1054 let NumMicroOps = 2;
1055 let ResourceCycles = [1,1];
1056}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1057def: InstRW<[BWWriteResGroup40], (instregex "VCVTPS2PDYrr",
1058 "VPSLLDYrr",
1059 "VPSLLQYrr",
1060 "VPSLLWYrr",
1061 "VPSRADYrr",
1062 "VPSRAWYrr",
1063 "VPSRLDYrr",
1064 "VPSRLQYrr",
1065 "VPSRLWYrr",
1066 "VPTESTYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1067
1068def BWWriteResGroup41 : SchedWriteRes<[BWPort0,BWPort0156]> {
1069 let Latency = 4;
1070 let NumMicroOps = 2;
1071 let ResourceCycles = [1,1];
1072}
1073def: InstRW<[BWWriteResGroup41], (instregex "FNSTSW16r")>;
1074
1075def BWWriteResGroup42 : SchedWriteRes<[BWPort1,BWPort5]> {
1076 let Latency = 4;
1077 let NumMicroOps = 2;
1078 let ResourceCycles = [1,1];
1079}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1080def: InstRW<[BWWriteResGroup42], (instrs IMUL64r, MUL64r, MULX64rr)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1081def: InstRW<[BWWriteResGroup42], (instregex "MMX_CVTPD2PIirr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1082 "MMX_CVTPI2PDirr",
1083 "MMX_CVTPS2PIirr",
1084 "MMX_CVTTPD2PIirr",
1085 "MMX_CVTTPS2PIirr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1086 "(V?)CVTDQ2PDrr",
1087 "(V?)CVTPD2DQrr",
1088 "(V?)CVTPD2PSrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1089 "VCVTPS2PHrr",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1090 "(V?)CVTSD2SSrr",
1091 "(V?)CVTSI642SDrr",
1092 "(V?)CVTSI2SDrr",
1093 "(V?)CVTSI2SSrr",
1094 "(V?)CVTTPD2DQrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1095
1096def BWWriteResGroup42_16 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1097 let Latency = 4;
1098 let NumMicroOps = 4;
1099}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1100def: InstRW<[BWWriteResGroup42_16], (instrs IMUL16r, MUL16r)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1101
1102def BWWriteResGroup43 : SchedWriteRes<[BWPort0,BWPort4,BWPort237]> {
1103 let Latency = 4;
1104 let NumMicroOps = 3;
1105 let ResourceCycles = [1,1,1];
1106}
1107def: InstRW<[BWWriteResGroup43], (instregex "FNSTSWm")>;
1108
1109def BWWriteResGroup44 : SchedWriteRes<[BWPort1,BWPort4,BWPort237]> {
1110 let Latency = 4;
1111 let NumMicroOps = 3;
1112 let ResourceCycles = [1,1,1];
1113}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1114def: InstRW<[BWWriteResGroup44], (instregex "ISTT_FP16m",
1115 "ISTT_FP32m",
1116 "ISTT_FP64m",
1117 "IST_F16m",
1118 "IST_F32m",
1119 "IST_FP16m",
1120 "IST_FP32m",
1121 "IST_FP64m",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1122 "VCVTPS2PH(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1123
1124def BWWriteResGroup45 : SchedWriteRes<[BWPort0156]> {
1125 let Latency = 4;
1126 let NumMicroOps = 4;
1127 let ResourceCycles = [4];
1128}
1129def: InstRW<[BWWriteResGroup45], (instregex "FNCLEX")>;
1130
1131def BWWriteResGroup46 : SchedWriteRes<[BWPort015,BWPort0156]> {
1132 let Latency = 4;
1133 let NumMicroOps = 4;
1134 let ResourceCycles = [1,3];
1135}
1136def: InstRW<[BWWriteResGroup46], (instregex "VZEROUPPER")>;
1137
1138def BWWriteResGroup47 : SchedWriteRes<[BWPort0]> {
1139 let Latency = 5;
1140 let NumMicroOps = 1;
1141 let ResourceCycles = [1];
1142}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1143def: InstRW<[BWWriteResGroup47], (instregex "MMX_PMADDUBSWrr",
1144 "MMX_PMADDWDirr",
1145 "MMX_PMULHRSWrr",
1146 "MMX_PMULHUWirr",
1147 "MMX_PMULHWirr",
1148 "MMX_PMULLWirr",
1149 "MMX_PMULUDQirr",
1150 "MMX_PSADBWirr",
1151 "MUL_FPrST0",
1152 "MUL_FST0r",
1153 "MUL_FrST0",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1154 "(V?)PCMPGTQ(Y?)rr",
1155 "(V?)PHMINPOSUWrr",
1156 "(V?)PMADDUBSW(Y?)rr",
1157 "(V?)PMADDWD(Y?)rr",
1158 "(V?)PMULDQ(Y?)rr",
1159 "(V?)PMULHRSW(Y?)rr",
1160 "(V?)PMULHUW(Y?)rr",
1161 "(V?)PMULHW(Y?)rr",
1162 "(V?)PMULLW(Y?)rr",
1163 "(V?)PMULUDQ(Y?)rr",
1164 "(V?)PSADBW(Y?)rr",
1165 "(V?)RCPPSr",
1166 "(V?)RCPSSr",
1167 "(V?)RSQRTPSr",
1168 "(V?)RSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1169
1170def BWWriteResGroup48 : SchedWriteRes<[BWPort01]> {
1171 let Latency = 5;
1172 let NumMicroOps = 1;
1173 let ResourceCycles = [1];
1174}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]1175def: InstRW<[BWWriteResGroup48],
1176 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)(Y)?r",
1177 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)r")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1178
1179def BWWriteResGroup49 : SchedWriteRes<[BWPort23]> {
1180 let Latency = 5;
1181 let NumMicroOps = 1;
1182 let ResourceCycles = [1];
1183}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1184def: InstRW<[BWWriteResGroup49], (instregex "MMX_MOVD64rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1185 "MMX_MOVD64to64rm",
1186 "MMX_MOVQ64rm",
1187 "MOV(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1188 "MOVSX(16|32|64)rm16",
1189 "MOVSX(16|32|64)rm32",
1190 "MOVSX(16|32|64)rm8",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1191 "MOVZX(16|32|64)rm16",
1192 "MOVZX(16|32|64)rm8",
1193 "PREFETCHNTA",
1194 "PREFETCHT0",
1195 "PREFETCHT1",
1196 "PREFETCHT2",
1197 "VBROADCASTSSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1198 "(V?)LDDQUrm",
1199 "(V?)MOV64toPQIrm",
1200 "(V?)MOVAPDrm",
1201 "(V?)MOVAPSrm",
1202 "(V?)MOVDDUPrm",
1203 "(V?)MOVDI2PDIrm",
1204 "(V?)MOVDQArm",
1205 "(V?)MOVDQUrm",
1206 "(V?)MOVNTDQArm",
1207 "(V?)MOVQI2PQIrm",
1208 "(V?)MOVSDrm",
1209 "(V?)MOVSHDUPrm",
1210 "(V?)MOVSLDUPrm",
1211 "(V?)MOVSSrm",
1212 "(V?)MOVUPDrm",
1213 "(V?)MOVUPSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1214 "VPBROADCASTDrm",
1215 "VPBROADCASTQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1216
1217def BWWriteResGroup50 : SchedWriteRes<[BWPort1,BWPort5]> {
1218 let Latency = 5;
1219 let NumMicroOps = 3;
1220 let ResourceCycles = [1,2];
1221}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1222def: InstRW<[BWWriteResGroup50], (instregex "(V?)CVTSI642SSrr",
1223 "(V?)HADDPD(Y?)rr",
1224 "(V?)HADDPS(Y?)rr",
1225 "(V?)HSUBPD(Y?)rr",
1226 "(V?)HSUBPS(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1227
1228def BWWriteResGroup51 : SchedWriteRes<[BWPort1,BWPort6,BWPort06]> {
1229 let Latency = 5;
1230 let NumMicroOps = 3;
1231 let ResourceCycles = [1,1,1];
1232}
1233def: InstRW<[BWWriteResGroup51], (instregex "STR(16|32|64)r")>;
1234
1235def BWWriteResGroup52 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1236 let Latency = 4;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1237 let NumMicroOps = 3;
1238 let ResourceCycles = [1,1,1];
1239}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]1240def: InstRW<[BWWriteResGroup52], (instrs IMUL32r, MUL32r, MULX32rr)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1241
1242def BWWriteResGroup53 : SchedWriteRes<[BWPort0,BWPort4,BWPort237,BWPort15]> {
1243 let Latency = 5;
1244 let NumMicroOps = 4;
1245 let ResourceCycles = [1,1,1,1];
1246}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1247def: InstRW<[BWWriteResGroup53], (instregex "VMASKMOVPD(Y?)mr",
1248 "VMASKMOVPS(Y?)mr",
1249 "VPMASKMOVD(Y?)mr",
1250 "VPMASKMOVQ(Y?)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1251
1252def BWWriteResGroup54 : SchedWriteRes<[BWPort6,BWPort0156]> {
1253 let Latency = 5;
1254 let NumMicroOps = 5;
1255 let ResourceCycles = [1,4];
1256}
1257def: InstRW<[BWWriteResGroup54], (instregex "PAUSE")>;
1258
1259def BWWriteResGroup55 : SchedWriteRes<[BWPort06,BWPort0156]> {
1260 let Latency = 5;
1261 let NumMicroOps = 5;
1262 let ResourceCycles = [1,4];
1263}
1264def: InstRW<[BWWriteResGroup55], (instregex "XSETBV")>;
1265
1266def BWWriteResGroup56 : SchedWriteRes<[BWPort06,BWPort0156]> {
1267 let Latency = 5;
1268 let NumMicroOps = 5;
1269 let ResourceCycles = [2,3];
1270}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1271def: InstRW<[BWWriteResGroup56], (instregex "CMPXCHG(8|16|32|64)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1272
1273def BWWriteResGroup57 : SchedWriteRes<[BWPort4,BWPort237,BWPort0156]> {
1274 let Latency = 5;
1275 let NumMicroOps = 6;
1276 let ResourceCycles = [1,1,4];
1277}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1278def: InstRW<[BWWriteResGroup57], (instregex "PUSHF16", "PUSHF64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1279
1280def BWWriteResGroup58 : SchedWriteRes<[BWPort23]> {
1281 let Latency = 6;
1282 let NumMicroOps = 1;
1283 let ResourceCycles = [1];
1284}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1285def: InstRW<[BWWriteResGroup58], (instregex "LD_F32m",
1286 "LD_F64m",
1287 "LD_F80m",
1288 "VBROADCASTF128",
1289 "VBROADCASTI128",
1290 "VBROADCASTSDYrm",
1291 "VBROADCASTSSYrm",
1292 "VLDDQUYrm",
1293 "VMOVAPDYrm",
1294 "VMOVAPSYrm",
1295 "VMOVDDUPYrm",
1296 "VMOVDQAYrm",
1297 "VMOVDQUYrm",
1298 "VMOVNTDQAYrm",
1299 "VMOVSHDUPYrm",
1300 "VMOVSLDUPYrm",
1301 "VMOVUPDYrm",
1302 "VMOVUPSYrm",
1303 "VPBROADCASTDYrm",
1304 "VPBROADCASTQYrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1305 "(V?)ROUNDPD(Y?)r",
1306 "(V?)ROUNDPS(Y?)r",
1307 "(V?)ROUNDSDr",
1308 "(V?)ROUNDSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1309
1310def BWWriteResGroup59 : SchedWriteRes<[BWPort0,BWPort23]> {
1311 let Latency = 6;
1312 let NumMicroOps = 2;
1313 let ResourceCycles = [1,1];
1314}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1315def: InstRW<[BWWriteResGroup59], (instregex "MMX_PSLLDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1316 "MMX_PSLLQrm",
1317 "MMX_PSLLWrm",
1318 "MMX_PSRADrm",
1319 "MMX_PSRAWrm",
1320 "MMX_PSRLDrm",
1321 "MMX_PSRLQrm",
1322 "MMX_PSRLWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1323 "VCVTPH2PS(Y?)rm",
1324 "(V?)CVTPS2PDrm",
1325 "(V?)CVTSS2SDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1326 "VPSLLVQrm",
1327 "VPSRLVQrm",
1328 "VTESTPDrm",
1329 "VTESTPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1330
1331def BWWriteResGroup60 : SchedWriteRes<[BWPort1,BWPort5]> {
1332 let Latency = 6;
1333 let NumMicroOps = 2;
1334 let ResourceCycles = [1,1];
1335}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1336def: InstRW<[BWWriteResGroup60], (instregex "VCVTDQ2PDYrr",
1337 "VCVTPD2DQYrr",
1338 "VCVTPD2PSYrr",
1339 "VCVTPS2PHYrr",
1340 "VCVTTPD2DQYrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1341
1342def BWWriteResGroup61 : SchedWriteRes<[BWPort5,BWPort23]> {
1343 let Latency = 6;
1344 let NumMicroOps = 2;
1345 let ResourceCycles = [1,1];
1346}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1347def: InstRW<[BWWriteResGroup61], (instregex "MMX_PALIGNRrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1348 "MMX_PINSRWrm",
1349 "MMX_PSHUFBrm",
1350 "MMX_PSHUFWmi",
1351 "MMX_PUNPCKHBWirm",
1352 "MMX_PUNPCKHDQirm",
1353 "MMX_PUNPCKHWDirm",
1354 "MMX_PUNPCKLBWirm",
1355 "MMX_PUNPCKLDQirm",
1356 "MMX_PUNPCKLWDirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1357 "(V?)ANDNPDrm",
1358 "(V?)ANDNPSrm",
1359 "(V?)ANDPDrm",
1360 "(V?)ANDPSrm",
1361 "(V?)INSERTPSrm",
1362 "(V?)MOVHPDrm",
1363 "(V?)MOVHPSrm",
1364 "(V?)MOVLPDrm",
1365 "(V?)MOVLPSrm",
1366 "(V?)ORPDrm",
1367 "(V?)ORPSrm",
1368 "(V?)PACKSSDWrm",
1369 "(V?)PACKSSWBrm",
1370 "(V?)PACKUSDWrm",
1371 "(V?)PACKUSWBrm",
1372 "(V?)PALIGNRrmi",
1373 "(V?)PBLENDWrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1374 "VPERMILPDmi",
1375 "VPERMILPDrm",
1376 "VPERMILPSmi",
1377 "VPERMILPSrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1378 "(V?)PINSRBrm",
1379 "(V?)PINSRDrm",
1380 "(V?)PINSRQrm",
1381 "(V?)PINSRWrm",
1382 "(V?)PMOVSXBDrm",
1383 "(V?)PMOVSXBQrm",
1384 "(V?)PMOVSXBWrm",
1385 "(V?)PMOVSXDQrm",
1386 "(V?)PMOVSXWDrm",
1387 "(V?)PMOVSXWQrm",
1388 "(V?)PMOVZXBDrm",
1389 "(V?)PMOVZXBQrm",
1390 "(V?)PMOVZXBWrm",
1391 "(V?)PMOVZXDQrm",
1392 "(V?)PMOVZXWDrm",
1393 "(V?)PMOVZXWQrm",
1394 "(V?)PSHUFBrm",
1395 "(V?)PSHUFDmi",
1396 "(V?)PSHUFHWmi",
1397 "(V?)PSHUFLWmi",
1398 "(V?)PUNPCKHBWrm",
1399 "(V?)PUNPCKHDQrm",
1400 "(V?)PUNPCKHQDQrm",
1401 "(V?)PUNPCKHWDrm",
1402 "(V?)PUNPCKLBWrm",
1403 "(V?)PUNPCKLDQrm",
1404 "(V?)PUNPCKLQDQrm",
1405 "(V?)PUNPCKLWDrm",
1406 "(V?)SHUFPDrmi",
1407 "(V?)SHUFPSrmi",
1408 "(V?)UNPCKHPDrm",
1409 "(V?)UNPCKHPSrm",
1410 "(V?)UNPCKLPDrm",
1411 "(V?)UNPCKLPSrm",
1412 "(V?)XORPDrm",
1413 "(V?)XORPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1414
1415def BWWriteResGroup62 : SchedWriteRes<[BWPort6,BWPort23]> {
1416 let Latency = 6;
1417 let NumMicroOps = 2;
1418 let ResourceCycles = [1,1];
1419}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1420def: InstRW<[BWWriteResGroup62], (instregex "FARJMP64",
1421 "JMP(16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1422
1423def BWWriteResGroup63 : SchedWriteRes<[BWPort23,BWPort06]> {
1424 let Latency = 6;
1425 let NumMicroOps = 2;
1426 let ResourceCycles = [1,1];
1427}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1428def: InstRW<[BWWriteResGroup63], (instregex "ADC(8|16|32|64)rm",
1429 "ADCX(32|64)rm",
1430 "ADOX(32|64)rm",
1431 "BT(16|32|64)mi8",
1432 "CMOV(AE|B|E|G|GE|L|LE|NE|NO|NP|NS|O|P|S)(16|32|64)rm",
1433 "RORX(32|64)mi",
1434 "SARX(32|64)rm",
1435 "SBB(8|16|32|64)rm",
1436 "SHLX(32|64)rm",
1437 "SHRX(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1438
1439def BWWriteResGroup64 : SchedWriteRes<[BWPort23,BWPort15]> {
1440 let Latency = 6;
1441 let NumMicroOps = 2;
1442 let ResourceCycles = [1,1];
1443}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1444def: InstRW<[BWWriteResGroup64], (instregex "ANDN(32|64)rm",
1445 "BLSI(32|64)rm",
1446 "BLSMSK(32|64)rm",
1447 "BLSR(32|64)rm",
1448 "BZHI(32|64)rm",
1449 "MMX_PABSBrm",
1450 "MMX_PABSDrm",
1451 "MMX_PABSWrm",
1452 "MMX_PADDBirm",
1453 "MMX_PADDDirm",
1454 "MMX_PADDQirm",
1455 "MMX_PADDSBirm",
1456 "MMX_PADDSWirm",
1457 "MMX_PADDUSBirm",
1458 "MMX_PADDUSWirm",
1459 "MMX_PADDWirm",
1460 "MMX_PAVGBirm",
1461 "MMX_PAVGWirm",
1462 "MMX_PCMPEQBirm",
1463 "MMX_PCMPEQDirm",
1464 "MMX_PCMPEQWirm",
1465 "MMX_PCMPGTBirm",
1466 "MMX_PCMPGTDirm",
1467 "MMX_PCMPGTWirm",
1468 "MMX_PMAXSWirm",
1469 "MMX_PMAXUBirm",
1470 "MMX_PMINSWirm",
1471 "MMX_PMINUBirm",
1472 "MMX_PSIGNBrm",
1473 "MMX_PSIGNDrm",
1474 "MMX_PSIGNWrm",
1475 "MMX_PSUBBirm",
1476 "MMX_PSUBDirm",
1477 "MMX_PSUBQirm",
1478 "MMX_PSUBSBirm",
1479 "MMX_PSUBSWirm",
1480 "MMX_PSUBUSBirm",
1481 "MMX_PSUBUSWirm",
1482 "MMX_PSUBWirm",
1483 "MOVBE(16|32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1484 "(V?)PABSBrm",
1485 "(V?)PABSDrm",
1486 "(V?)PABSWrm",
1487 "(V?)PADDBrm",
1488 "(V?)PADDDrm",
1489 "(V?)PADDQrm",
1490 "(V?)PADDSBrm",
1491 "(V?)PADDSWrm",
1492 "(V?)PADDUSBrm",
1493 "(V?)PADDUSWrm",
1494 "(V?)PADDWrm",
1495 "(V?)PAVGBrm",
1496 "(V?)PAVGWrm",
1497 "(V?)PCMPEQBrm",
1498 "(V?)PCMPEQDrm",
1499 "(V?)PCMPEQQrm",
1500 "(V?)PCMPEQWrm",
1501 "(V?)PCMPGTBrm",
1502 "(V?)PCMPGTDrm",
1503 "(V?)PCMPGTWrm",
1504 "(V?)PMAXSBrm",
1505 "(V?)PMAXSDrm",
1506 "(V?)PMAXSWrm",
1507 "(V?)PMAXUBrm",
1508 "(V?)PMAXUDrm",
1509 "(V?)PMAXUWrm",
1510 "(V?)PMINSBrm",
1511 "(V?)PMINSDrm",
1512 "(V?)PMINSWrm",
1513 "(V?)PMINUBrm",
1514 "(V?)PMINUDrm",
1515 "(V?)PMINUWrm",
1516 "(V?)PSIGNBrm",
1517 "(V?)PSIGNDrm",
1518 "(V?)PSIGNWrm",
1519 "(V?)PSUBBrm",
1520 "(V?)PSUBDrm",
1521 "(V?)PSUBQrm",
1522 "(V?)PSUBSBrm",
1523 "(V?)PSUBSWrm",
1524 "(V?)PSUBUSBrm",
1525 "(V?)PSUBUSWrm",
1526 "(V?)PSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1527
1528def BWWriteResGroup65 : SchedWriteRes<[BWPort23,BWPort015]> {
1529 let Latency = 6;
1530 let NumMicroOps = 2;
1531 let ResourceCycles = [1,1];
1532}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1533def: InstRW<[BWWriteResGroup65], (instregex "MMX_PANDNirm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1534 "MMX_PANDirm",
1535 "MMX_PORirm",
1536 "MMX_PXORirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1537 "(V?)BLENDPDrmi",
1538 "(V?)BLENDPSrmi",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1539 "VINSERTF128rm",
1540 "VINSERTI128rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1541 "(V?)PANDNrm",
1542 "(V?)PANDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1543 "VPBLENDDrmi",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1544 "(V?)PORrm",
1545 "(V?)PXORrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1546
1547def BWWriteResGroup66 : SchedWriteRes<[BWPort23,BWPort0156]> {
1548 let Latency = 6;
1549 let NumMicroOps = 2;
1550 let ResourceCycles = [1,1];
1551}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1552def: InstRW<[BWWriteResGroup66], (instrs POP16r, POP32r, POP64r)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1553def: InstRW<[BWWriteResGroup66], (instregex "ADD(8|16|32|64)rm",
1554 "AND(8|16|32|64)rm",
1555 "CMP(8|16|32|64)mi",
1556 "CMP(8|16|32|64)mr",
1557 "CMP(8|16|32|64)rm",
1558 "OR(8|16|32|64)rm",
1559 "POP(16|32|64)rmr",
1560 "SUB(8|16|32|64)rm",
1561 "TEST(8|16|32|64)mr",
1562 "TEST(8|16|32|64)mi",
1563 "XOR(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1564
1565def BWWriteResGroup67 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
1566 let Latency = 6;
1567 let NumMicroOps = 4;
1568 let ResourceCycles = [1,1,2];
1569}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1570def: InstRW<[BWWriteResGroup67], (instregex "SHLD(16|32|64)rrCL",
1571 "SHRD(16|32|64)rrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1572
1573def BWWriteResGroup68 : SchedWriteRes<[BWPort1,BWPort6,BWPort06,BWPort0156]> {
1574 let Latency = 6;
1575 let NumMicroOps = 4;
1576 let ResourceCycles = [1,1,1,1];
1577}
1578def: InstRW<[BWWriteResGroup68], (instregex "SLDT(16|32|64)r")>;
1579
1580def BWWriteResGroup69 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1581 let Latency = 6;
1582 let NumMicroOps = 4;
1583 let ResourceCycles = [1,1,1,1];
1584}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1585def: InstRW<[BWWriteResGroup69], (instregex "BTC(16|32|64)mi8",
1586 "BTR(16|32|64)mi8",
1587 "BTS(16|32|64)mi8",
1588 "SAR(8|16|32|64)m1",
1589 "SAR(8|16|32|64)mi",
1590 "SHL(8|16|32|64)m1",
1591 "SHL(8|16|32|64)mi",
1592 "SHR(8|16|32|64)m1",
1593 "SHR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1594
1595def BWWriteResGroup70 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1596 let Latency = 6;
1597 let NumMicroOps = 4;
1598 let ResourceCycles = [1,1,1,1];
1599}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1600def: InstRW<[BWWriteResGroup70], (instregex "ADD(8|16|32|64)mi",
1601 "ADD(8|16|32|64)mr",
1602 "AND(8|16|32|64)mi",
1603 "AND(8|16|32|64)mr",
1604 "DEC(8|16|32|64)m",
1605 "INC(8|16|32|64)m",
1606 "NEG(8|16|32|64)m",
1607 "NOT(8|16|32|64)m",
1608 "OR(8|16|32|64)mi",
1609 "OR(8|16|32|64)mr",
1610 "POP(16|32|64)rmm",
1611 "PUSH(16|32|64)rmm",
1612 "SUB(8|16|32|64)mi",
1613 "SUB(8|16|32|64)mr",
1614 "XOR(8|16|32|64)mi",
1615 "XOR(8|16|32|64)mr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1616
1617def BWWriteResGroup71 : SchedWriteRes<[BWPort6,BWPort0156]> {
1618 let Latency = 6;
1619 let NumMicroOps = 6;
1620 let ResourceCycles = [1,5];
1621}
1622def: InstRW<[BWWriteResGroup71], (instregex "STD")>;
1623
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1624def BWWriteResGroup73 : SchedWriteRes<[BWPort0,BWPort23]> {
1625 let Latency = 7;
1626 let NumMicroOps = 2;
1627 let ResourceCycles = [1,1];
1628}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1629def: InstRW<[BWWriteResGroup73], (instregex "VPSLLDYrm",
1630 "VPSLLQYrm",
1631 "VPSLLVQYrm",
1632 "VPSLLWYrm",
1633 "VPSRADYrm",
1634 "VPSRAWYrm",
1635 "VPSRLDYrm",
1636 "VPSRLQYrm",
1637 "VPSRLVQYrm",
1638 "VPSRLWYrm",
1639 "VTESTPDYrm",
1640 "VTESTPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1641
1642def BWWriteResGroup74 : SchedWriteRes<[BWPort1,BWPort23]> {
1643 let Latency = 7;
1644 let NumMicroOps = 2;
1645 let ResourceCycles = [1,1];
1646}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1647def: InstRW<[BWWriteResGroup74], (instregex "FCOM32m",
1648 "FCOM64m",
1649 "FCOMP32m",
1650 "FCOMP64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1651
1652def BWWriteResGroup75 : SchedWriteRes<[BWPort5,BWPort23]> {
1653 let Latency = 7;
1654 let NumMicroOps = 2;
1655 let ResourceCycles = [1,1];
1656}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1657def: InstRW<[BWWriteResGroup75], (instregex "VANDNPDYrm",
1658 "VANDNPSYrm",
1659 "VANDPDYrm",
1660 "VANDPSYrm",
1661 "VORPDYrm",
1662 "VORPSYrm",
1663 "VPACKSSDWYrm",
1664 "VPACKSSWBYrm",
1665 "VPACKUSDWYrm",
1666 "VPACKUSWBYrm",
1667 "VPALIGNRYrmi",
1668 "VPBLENDWYrmi",
1669 "VPERMILPDYmi",
1670 "VPERMILPDYrm",
1671 "VPERMILPSYmi",
1672 "VPERMILPSYrm",
1673 "VPSHUFBYrm",
1674 "VPSHUFDYmi",
1675 "VPSHUFHWYmi",
1676 "VPSHUFLWYmi",
1677 "VPUNPCKHBWYrm",
1678 "VPUNPCKHDQYrm",
1679 "VPUNPCKHQDQYrm",
1680 "VPUNPCKHWDYrm",
1681 "VPUNPCKLBWYrm",
1682 "VPUNPCKLDQYrm",
1683 "VPUNPCKLQDQYrm",
1684 "VPUNPCKLWDYrm",
1685 "VSHUFPDYrmi",
1686 "VSHUFPSYrmi",
1687 "VUNPCKHPDYrm",
1688 "VUNPCKHPSYrm",
1689 "VUNPCKLPDYrm",
1690 "VUNPCKLPSYrm",
1691 "VXORPDYrm",
1692 "VXORPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1693
1694def BWWriteResGroup76 : SchedWriteRes<[BWPort23,BWPort15]> {
1695 let Latency = 7;
1696 let NumMicroOps = 2;
1697 let ResourceCycles = [1,1];
1698}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1699def: InstRW<[BWWriteResGroup76], (instregex "VPABSBYrm",
1700 "VPABSDYrm",
1701 "VPABSWYrm",
1702 "VPADDBYrm",
1703 "VPADDDYrm",
1704 "VPADDQYrm",
1705 "VPADDSBYrm",
1706 "VPADDSWYrm",
1707 "VPADDUSBYrm",
1708 "VPADDUSWYrm",
1709 "VPADDWYrm",
1710 "VPAVGBYrm",
1711 "VPAVGWYrm",
1712 "VPCMPEQBYrm",
1713 "VPCMPEQDYrm",
1714 "VPCMPEQQYrm",
1715 "VPCMPEQWYrm",
1716 "VPCMPGTBYrm",
1717 "VPCMPGTDYrm",
1718 "VPCMPGTWYrm",
1719 "VPMAXSBYrm",
1720 "VPMAXSDYrm",
1721 "VPMAXSWYrm",
1722 "VPMAXUBYrm",
1723 "VPMAXUDYrm",
1724 "VPMAXUWYrm",
1725 "VPMINSBYrm",
1726 "VPMINSDYrm",
1727 "VPMINSWYrm",
1728 "VPMINUBYrm",
1729 "VPMINUDYrm",
1730 "VPMINUWYrm",
1731 "VPSIGNBYrm",
1732 "VPSIGNDYrm",
1733 "VPSIGNWYrm",
1734 "VPSUBBYrm",
1735 "VPSUBDYrm",
1736 "VPSUBQYrm",
1737 "VPSUBSBYrm",
1738 "VPSUBSWYrm",
1739 "VPSUBUSBYrm",
1740 "VPSUBUSWYrm",
1741 "VPSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1742
1743def BWWriteResGroup77 : SchedWriteRes<[BWPort23,BWPort015]> {
1744 let Latency = 7;
1745 let NumMicroOps = 2;
1746 let ResourceCycles = [1,1];
1747}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1748def: InstRW<[BWWriteResGroup77], (instregex "VBLENDPDYrmi",
1749 "VBLENDPSYrmi",
1750 "VPANDNYrm",
1751 "VPANDYrm",
1752 "VPBLENDDYrmi",
1753 "VPORYrm",
1754 "VPXORYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1755
1756def BWWriteResGroup78 : SchedWriteRes<[BWPort0,BWPort5]> {
1757 let Latency = 7;
1758 let NumMicroOps = 3;
1759 let ResourceCycles = [1,2];
1760}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1761def: InstRW<[BWWriteResGroup78], (instregex "(V?)MPSADBW(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1762
1763def BWWriteResGroup79 : SchedWriteRes<[BWPort5,BWPort23]> {
1764 let Latency = 7;
1765 let NumMicroOps = 3;
1766 let ResourceCycles = [2,1];
1767}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1768def: InstRW<[BWWriteResGroup79], (instregex "BLENDVPDrm0",
1769 "BLENDVPSrm0",
1770 "MMX_PACKSSDWirm",
1771 "MMX_PACKSSWBirm",
1772 "MMX_PACKUSWBirm",
1773 "PBLENDVBrm0",
1774 "VBLENDVPDrm",
1775 "VBLENDVPSrm",
1776 "VMASKMOVPDrm",
1777 "VMASKMOVPSrm",
1778 "VPBLENDVBrm",
1779 "VPMASKMOVDrm",
1780 "VPMASKMOVQrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1781
1782def BWWriteResGroup80 : SchedWriteRes<[BWPort23,BWPort0156]> {
1783 let Latency = 7;
1784 let NumMicroOps = 3;
1785 let ResourceCycles = [1,2];
1786}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1787def: InstRW<[BWWriteResGroup80], (instregex "LEAVE64",
1788 "SCASB",
1789 "SCASL",
1790 "SCASQ",
1791 "SCASW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1792
1793def BWWriteResGroup81 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1794 let Latency = 7;
1795 let NumMicroOps = 3;
1796 let ResourceCycles = [1,1,1];
1797}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1798def: InstRW<[BWWriteResGroup81], (instregex "PSLLDrm",
1799 "PSLLQrm",
1800 "PSLLWrm",
1801 "PSRADrm",
1802 "PSRAWrm",
1803 "PSRLDrm",
1804 "PSRLQrm",
1805 "PSRLWrm",
1806 "PTESTrm",
1807 "VPSLLDrm",
1808 "VPSLLQrm",
1809 "VPSLLWrm",
1810 "VPSRADrm",
1811 "VPSRAWrm",
1812 "VPSRLDrm",
1813 "VPSRLQrm",
1814 "VPSRLWrm",
1815 "VPTESTrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1816
1817def BWWriteResGroup82 : SchedWriteRes<[BWPort0,BWPort01,BWPort23]> {
1818 let Latency = 7;
1819 let NumMicroOps = 3;
1820 let ResourceCycles = [1,1,1];
1821}
1822def: InstRW<[BWWriteResGroup82], (instregex "FLDCW16m")>;
1823
1824def BWWriteResGroup83 : SchedWriteRes<[BWPort0,BWPort23,BWPort0156]> {
1825 let Latency = 7;
1826 let NumMicroOps = 3;
1827 let ResourceCycles = [1,1,1];
1828}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1829def: InstRW<[BWWriteResGroup83], (instregex "(V?)LDMXCSR")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1830
1831def BWWriteResGroup84 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
1832 let Latency = 7;
1833 let NumMicroOps = 3;
1834 let ResourceCycles = [1,1,1];
1835}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1836def: InstRW<[BWWriteResGroup84], (instregex "LRETQ",
1837 "RETQ")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1838
1839def BWWriteResGroup85 : SchedWriteRes<[BWPort23,BWPort06,BWPort15]> {
1840 let Latency = 7;
1841 let NumMicroOps = 3;
1842 let ResourceCycles = [1,1,1];
1843}
Craig Toppera42a2ba2017-12-16 18:35:31 +0000[diff] [blame]1844def: InstRW<[BWWriteResGroup85], (instregex "BEXTR(32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1845
1846def BWWriteResGroup86 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
1847 let Latency = 7;
1848 let NumMicroOps = 3;
1849 let ResourceCycles = [1,1,1];
1850}
Craig Topperf4cd9082018-01-19 05:47:32 +0000[diff] [blame]1851def: InstRW<[BWWriteResGroup86], (instregex "CMOV(A|BE)(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1852
1853def BWWriteResGroup87 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06]> {
1854 let Latency = 7;
1855 let NumMicroOps = 5;
1856 let ResourceCycles = [1,1,1,2];
1857}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1858def: InstRW<[BWWriteResGroup87], (instregex "ROL(8|16|32|64)m1",
1859 "ROL(8|16|32|64)mi",
1860 "ROR(8|16|32|64)m1",
1861 "ROR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1862
1863def BWWriteResGroup88 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
1864 let Latency = 7;
1865 let NumMicroOps = 5;
1866 let ResourceCycles = [1,1,1,2];
1867}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1868def: InstRW<[BWWriteResGroup88], (instregex "XADD(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1869
1870def BWWriteResGroup89 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
1871 let Latency = 7;
1872 let NumMicroOps = 5;
1873 let ResourceCycles = [1,1,1,1,1];
1874}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1875def: InstRW<[BWWriteResGroup89], (instregex "CALL(16|32|64)m",
1876 "FARCALL64")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1877
1878def BWWriteResGroup90 : SchedWriteRes<[BWPort6,BWPort06,BWPort15,BWPort0156]> {
1879 let Latency = 7;
1880 let NumMicroOps = 7;
1881 let ResourceCycles = [2,2,1,2];
1882}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]1883def: InstRW<[BWWriteResGroup90], (instrs LOOP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1884
1885def BWWriteResGroup91 : SchedWriteRes<[BWPort1,BWPort23]> {
1886 let Latency = 8;
1887 let NumMicroOps = 2;
1888 let ResourceCycles = [1,1];
1889}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1890def: InstRW<[BWWriteResGroup91], (instrs IMUL32rm, IMUL32rmi, IMUL32rmi8, IMUL64rm, IMUL64rmi8, IMUL64rmi32)>;
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1891def: InstRW<[BWWriteResGroup91], (instrs IMUL8m, MUL8m)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1892def: InstRW<[BWWriteResGroup91], (instregex "BSF(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1893 "BSR(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1894 "LZCNT(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1895 "MMX_CVTPI2PSirm",
1896 "MMX_CVTPS2PIirm",
1897 "MMX_CVTTPS2PIirm",
1898 "PDEP(32|64)rm",
1899 "PEXT(32|64)rm",
1900 "POPCNT(16|32|64)rm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1901 "TZCNT(16|32|64)rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1902 "(V?)ADDPDrm",
1903 "(V?)ADDPSrm",
1904 "(V?)ADDSDrm",
1905 "(V?)ADDSSrm",
1906 "(V?)ADDSUBPDrm",
1907 "(V?)ADDSUBPSrm",
1908 "(V?)CMPPDrmi",
1909 "(V?)CMPPSrmi",
1910 "(V?)CMPSDrm",
1911 "(V?)CMPSSrm",
1912 "(V?)COMISDrm",
1913 "(V?)COMISSrm",
1914 "(V?)CVTDQ2PSrm",
1915 "(V?)CVTPS2DQrm",
1916 "(V?)CVTTPS2DQrm",
1917 "(V?)MAX(C?)PDrm",
1918 "(V?)MAX(C?)PSrm",
1919 "(V?)MAX(C?)SDrm",
1920 "(V?)MAX(C?)SSrm",
1921 "(V?)MIN(C?)PDrm",
1922 "(V?)MIN(C?)PSrm",
1923 "(V?)MIN(C?)SDrm",
1924 "(V?)MIN(C?)SSrm",
1925 "(V?)SUBPDrm",
1926 "(V?)SUBPSrm",
1927 "(V?)SUBSDrm",
1928 "(V?)SUBSSrm",
1929 "(V?)UCOMISDrm",
1930 "(V?)UCOMISSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1931
1932def BWWriteResGroup91_16 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1933 let Latency = 8;
1934 let NumMicroOps = 3;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1935 let ResourceCycles = [1,1,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1936}
Craig Topperb369cdb2018-01-25 06:57:42 +0000[diff] [blame]1937def: InstRW<[BWWriteResGroup91_16], (instrs IMUL16rm, IMUL16rmi, IMUL16rmi8)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1938
1939def BWWriteResGroup91_16_2 : SchedWriteRes<[BWPort1, BWPort0156, BWPort23]> {
1940 let Latency = 8;
1941 let NumMicroOps = 5;
1942}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1943def: InstRW<[BWWriteResGroup91_16_2], (instrs IMUL16m, MUL16m)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1944
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1945def BWWriteResGroup92 : SchedWriteRes<[BWPort5,BWPort23]> {
1946 let Latency = 8;
1947 let NumMicroOps = 2;
1948 let ResourceCycles = [1,1];
1949}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1950def: InstRW<[BWWriteResGroup92], (instregex "VPMOVSXBDYrm",
1951 "VPMOVSXBQYrm",
1952 "VPMOVSXBWYrm",
1953 "VPMOVSXDQYrm",
1954 "VPMOVSXWDYrm",
1955 "VPMOVSXWQYrm",
1956 "VPMOVZXWDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1957
1958def BWWriteResGroup93 : SchedWriteRes<[BWPort01,BWPort23]> {
1959 let Latency = 8;
1960 let NumMicroOps = 2;
1961 let ResourceCycles = [1,1];
1962}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]1963def: InstRW<[BWWriteResGroup93], (instregex "(V?)MULPDrm",
1964 "(V?)MULPSrm",
1965 "(V?)MULSDrm",
1966 "(V?)MULSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1967
1968def BWWriteResGroup94 : SchedWriteRes<[BWPort5,BWPort23]> {
1969 let Latency = 8;
1970 let NumMicroOps = 3;
1971 let ResourceCycles = [2,1];
1972}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1973def: InstRW<[BWWriteResGroup94], (instregex "VBLENDVPDYrm",
1974 "VBLENDVPSYrm",
1975 "VMASKMOVPDYrm",
1976 "VMASKMOVPSYrm",
1977 "VPBLENDVBYrm",
1978 "VPMASKMOVDYrm",
1979 "VPMASKMOVQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1980
1981def BWWriteResGroup95 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
1982 let Latency = 8;
1983 let NumMicroOps = 4;
1984 let ResourceCycles = [2,1,1];
1985}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1986def: InstRW<[BWWriteResGroup95], (instregex "VPSLLVDrm",
1987 "VPSRAVDrm",
1988 "VPSRLVDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]1989
1990def BWWriteResGroup96 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
1991 let Latency = 8;
1992 let NumMicroOps = 4;
1993 let ResourceCycles = [2,1,1];
1994}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]1995def: InstRW<[BWWriteResGroup96], (instregex "MMX_PHADDDrm",
1996 "MMX_PHADDSWrm",
1997 "MMX_PHADDWrm",
1998 "MMX_PHSUBDrm",
1999 "MMX_PHSUBSWrm",
2000 "MMX_PHSUBWrm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2001 "(V?)PHADDDrm",
2002 "(V?)PHADDSWrm",
2003 "(V?)PHADDWrm",
2004 "(V?)PHSUBDrm",
2005 "(V?)PHSUBSWrm",
2006 "(V?)PHSUBWrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2007
2008def BWWriteResGroup97 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2009 let Latency = 8;
2010 let NumMicroOps = 5;
2011 let ResourceCycles = [1,1,1,2];
2012}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2013def: InstRW<[BWWriteResGroup97], (instregex "RCL(8|16|32|64)m1",
2014 "RCL(8|16|32|64)mi",
2015 "RCR(8|16|32|64)m1",
2016 "RCR(8|16|32|64)mi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2017
2018def BWWriteResGroup98 : SchedWriteRes<[BWPort23,BWPort237,BWPort06,BWPort0156]> {
2019 let Latency = 8;
2020 let NumMicroOps = 5;
2021 let ResourceCycles = [1,1,2,1];
2022}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2023def: InstRW<[BWWriteResGroup98], (instregex "ROR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2024
2025def BWWriteResGroup99 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort0156]> {
2026 let Latency = 8;
2027 let NumMicroOps = 6;
2028 let ResourceCycles = [1,1,1,3];
2029}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2030def: InstRW<[BWWriteResGroup99], (instregex "ADC(8|16|32|64)mi",
2031 "XCHG(8|16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2032
2033def BWWriteResGroup100 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2034 let Latency = 8;
2035 let NumMicroOps = 6;
2036 let ResourceCycles = [1,1,1,2,1];
2037}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2038def: InstRW<[BWWriteResGroup100], (instregex "ADC(8|16|32|64)mr",
2039 "CMPXCHG(8|16|32|64)rm",
2040 "ROL(8|16|32|64)mCL",
2041 "SAR(8|16|32|64)mCL",
2042 "SBB(8|16|32|64)mi",
2043 "SBB(8|16|32|64)mr",
2044 "SHL(8|16|32|64)mCL",
2045 "SHR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2046
2047def BWWriteResGroup101 : SchedWriteRes<[BWPort1,BWPort23]> {
2048 let Latency = 9;
2049 let NumMicroOps = 2;
2050 let ResourceCycles = [1,1];
2051}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2052def: InstRW<[BWWriteResGroup101], (instregex "ADD_F32m",
2053 "ADD_F64m",
2054 "ILD_F16m",
2055 "ILD_F32m",
2056 "ILD_F64m",
2057 "SUBR_F32m",
2058 "SUBR_F64m",
2059 "SUB_F32m",
2060 "SUB_F64m",
2061 "VADDPDYrm",
2062 "VADDPSYrm",
2063 "VADDSUBPDYrm",
2064 "VADDSUBPSYrm",
2065 "VCMPPDYrmi",
2066 "VCMPPSYrmi",
2067 "VCVTDQ2PSYrm",
2068 "VCVTPS2DQYrm",
2069 "VCVTTPS2DQYrm",
2070 "VMAX(C?)PDYrm",
2071 "VMAX(C?)PSYrm",
2072 "VMIN(C?)PDYrm",
2073 "VMIN(C?)PSYrm",
2074 "VSUBPDYrm",
2075 "VSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2076
2077def BWWriteResGroup102 : SchedWriteRes<[BWPort5,BWPort23]> {
2078 let Latency = 9;
2079 let NumMicroOps = 2;
2080 let ResourceCycles = [1,1];
2081}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2082def: InstRW<[BWWriteResGroup102], (instregex "VPERM2F128rm",
2083 "VPERM2I128rm",
2084 "VPERMDYrm",
2085 "VPERMPDYmi",
2086 "VPERMPSYrm",
2087 "VPERMQYmi",
2088 "VPMOVZXBDYrm",
2089 "VPMOVZXBQYrm",
2090 "VPMOVZXBWYrm",
2091 "VPMOVZXDQYrm",
2092 "VPMOVZXWQYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2093
2094def BWWriteResGroup103 : SchedWriteRes<[BWPort01,BWPort23]> {
2095 let Latency = 9;
2096 let NumMicroOps = 2;
2097 let ResourceCycles = [1,1];
2098}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2099def: InstRW<[BWWriteResGroup103], (instregex "VMULPDYrm",
2100 "VMULPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2101
2102def BWWriteResGroup104 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2103 let Latency = 9;
2104 let NumMicroOps = 3;
2105 let ResourceCycles = [1,1,1];
2106}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2107def: InstRW<[BWWriteResGroup104], (instregex "(V?)DPPDrri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2108
2109def BWWriteResGroup105 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2110 let Latency = 9;
2111 let NumMicroOps = 3;
2112 let ResourceCycles = [1,1,1];
2113}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2114def: InstRW<[BWWriteResGroup105], (instregex "(V?)CVTSD2SI64rm",
2115 "(V?)CVTSD2SIrm",
2116 "(V?)CVTSS2SI64rm",
2117 "(V?)CVTSS2SIrm",
2118 "(V?)CVTTSD2SI64rm",
2119 "(V?)CVTTSD2SIrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2120 "VCVTTSS2SI64rm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2121 "(V?)CVTTSS2SIrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2122
2123def BWWriteResGroup106 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2124 let Latency = 9;
2125 let NumMicroOps = 3;
2126 let ResourceCycles = [1,1,1];
2127}
2128def: InstRW<[BWWriteResGroup106], (instregex "VCVTPS2PDYrm")>;
2129
2130def BWWriteResGroup107 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2131 let Latency = 9;
2132 let NumMicroOps = 3;
2133 let ResourceCycles = [1,1,1];
2134}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2135def: InstRW<[BWWriteResGroup107], (instrs IMUL64m, MUL64m, MULX64rm)>;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2136def: InstRW<[BWWriteResGroup107], (instregex "CVTPD2DQrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2137 "CVTPD2PSrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2138 "CVTTPD2DQrm",
2139 "MMX_CVTPD2PIirm",
2140 "MMX_CVTPI2PDirm",
2141 "MMX_CVTTPD2PIirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2142 "(V?)CVTDQ2PDrm",
2143 "(V?)CVTSD2SSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2144
2145def BWWriteResGroup108 : SchedWriteRes<[BWPort5,BWPort23,BWPort015]> {
2146 let Latency = 9;
2147 let NumMicroOps = 3;
2148 let ResourceCycles = [1,1,1];
2149}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2150def: InstRW<[BWWriteResGroup108], (instregex "VPBROADCASTB(Y?)rm",
2151 "VPBROADCASTW(Y?)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2152
2153def BWWriteResGroup109 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2154 let Latency = 9;
2155 let NumMicroOps = 4;
2156 let ResourceCycles = [2,1,1];
2157}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2158def: InstRW<[BWWriteResGroup109], (instregex "VPSLLVDYrm",
2159 "VPSRAVDYrm",
2160 "VPSRLVDYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2161
2162def BWWriteResGroup110 : SchedWriteRes<[BWPort5,BWPort23,BWPort15]> {
2163 let Latency = 9;
2164 let NumMicroOps = 4;
2165 let ResourceCycles = [2,1,1];
2166}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2167def: InstRW<[BWWriteResGroup110], (instregex "VPHADDDYrm",
2168 "VPHADDSWYrm",
2169 "VPHADDWYrm",
2170 "VPHSUBDYrm",
2171 "VPHSUBSWYrm",
2172 "VPHSUBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2173
2174def BWWriteResGroup111 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort0156]> {
2175 let Latency = 9;
2176 let NumMicroOps = 4;
2177 let ResourceCycles = [1,1,1,1];
2178}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2179def: InstRW<[BWWriteResGroup111], (instregex "SHLD(16|32|64)mri8",
2180 "SHRD(16|32|64)mri8")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2181
2182def BWWriteResGroup112 : SchedWriteRes<[BWPort23,BWPort06,BWPort0156]> {
2183 let Latency = 9;
2184 let NumMicroOps = 5;
2185 let ResourceCycles = [1,1,3];
2186}
2187def: InstRW<[BWWriteResGroup112], (instregex "RDRAND(16|32|64)r")>;
2188
2189def BWWriteResGroup113 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2190 let Latency = 9;
2191 let NumMicroOps = 5;
2192 let ResourceCycles = [1,2,1,1];
2193}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2194def: InstRW<[BWWriteResGroup113], (instregex "LAR(16|32|64)rm",
2195 "LSL(16|32|64)rm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2196
2197def BWWriteResGroup114 : SchedWriteRes<[BWPort0]> {
2198 let Latency = 10;
2199 let NumMicroOps = 2;
2200 let ResourceCycles = [2];
2201}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2202def: InstRW<[BWWriteResGroup114], (instregex "(V?)PMULLD(Y?)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2203
2204def BWWriteResGroup115 : SchedWriteRes<[BWPort0,BWPort23]> {
2205 let Latency = 10;
2206 let NumMicroOps = 2;
2207 let ResourceCycles = [1,1];
2208}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2209def: InstRW<[BWWriteResGroup115], (instregex "MMX_PMADDUBSWrm",
2210 "MMX_PMADDWDirm",
2211 "MMX_PMULHRSWrm",
2212 "MMX_PMULHUWirm",
2213 "MMX_PMULHWirm",
2214 "MMX_PMULLWirm",
2215 "MMX_PMULUDQirm",
2216 "MMX_PSADBWirm",
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2217 "(V?)PCMPGTQrm",
2218 "(V?)PHMINPOSUWrm",
2219 "(V?)PMADDUBSWrm",
2220 "(V?)PMADDWDrm",
2221 "(V?)PMULDQrm",
2222 "(V?)PMULHRSWrm",
2223 "(V?)PMULHUWrm",
2224 "(V?)PMULHWrm",
2225 "(V?)PMULLWrm",
2226 "(V?)PMULUDQrm",
2227 "(V?)PSADBWrm",
2228 "(V?)RCPPSm",
2229 "(V?)RCPSSm",
2230 "(V?)RSQRTPSm",
2231 "(V?)RSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2232
2233def BWWriteResGroup116 : SchedWriteRes<[BWPort01,BWPort23]> {
2234 let Latency = 10;
2235 let NumMicroOps = 2;
2236 let ResourceCycles = [1,1];
2237}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2238def: InstRW<[BWWriteResGroup116],
2239 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)m",
2240 "VF(N)?M(ADD|SUB)(132|213|231)S(D|S)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2241
2242def BWWriteResGroup117 : SchedWriteRes<[BWPort1,BWPort23]> {
2243 let Latency = 10;
2244 let NumMicroOps = 3;
2245 let ResourceCycles = [2,1];
2246}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2247def: InstRW<[BWWriteResGroup117], (instregex "FICOM16m",
2248 "FICOM32m",
2249 "FICOMP16m",
2250 "FICOMP32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2251
2252def BWWriteResGroup118 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2253 let Latency = 10;
2254 let NumMicroOps = 3;
2255 let ResourceCycles = [1,1,1];
2256}
2257def: InstRW<[BWWriteResGroup118], (instregex "VPTESTYrm")>;
2258
2259def BWWriteResGroup119 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2260 let Latency = 10;
2261 let NumMicroOps = 4;
2262 let ResourceCycles = [1,2,1];
2263}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2264def: InstRW<[BWWriteResGroup119], (instregex "(V?)HADDPDrm",
2265 "(V?)HADDPSrm",
2266 "(V?)HSUBPDrm",
2267 "(V?)HSUBPSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2268
2269def BWWriteResGroup120 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2270 let Latency = 10;
2271 let NumMicroOps = 4;
2272 let ResourceCycles = [1,1,1,1];
2273}
2274def: InstRW<[BWWriteResGroup120], (instregex "CVTTSS2SI64rm")>;
2275
2276def BWWriteResGroup121 : SchedWriteRes<[BWPort1,BWPort23,BWPort06,BWPort0156]> {
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2277 let Latency = 9;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2278 let NumMicroOps = 4;
2279 let ResourceCycles = [1,1,1,1];
2280}
Craig Topper4a3be6e2018-03-22 19:22:51 +0000[diff] [blame]2281def: InstRW<[BWWriteResGroup121], (instrs IMUL32m, MUL32m, MULX32rm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2282
2283def BWWriteResGroup122 : SchedWriteRes<[BWPort0]> {
2284 let Latency = 11;
2285 let NumMicroOps = 1;
2286 let ResourceCycles = [1];
2287}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2288def: InstRW<[BWWriteResGroup122], (instregex "(V?)DIVPSrr",
2289 "(V?)DIVSSrr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2290
2291def BWWriteResGroup123 : SchedWriteRes<[BWPort0,BWPort23]> {
2292 let Latency = 11;
2293 let NumMicroOps = 2;
2294 let ResourceCycles = [1,1];
2295}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2296def: InstRW<[BWWriteResGroup123], (instregex "MUL_F32m",
2297 "MUL_F64m",
2298 "VPCMPGTQYrm",
2299 "VPMADDUBSWYrm",
2300 "VPMADDWDYrm",
2301 "VPMULDQYrm",
2302 "VPMULHRSWYrm",
2303 "VPMULHUWYrm",
2304 "VPMULHWYrm",
2305 "VPMULLWYrm",
2306 "VPMULUDQYrm",
2307 "VPSADBWYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2308
2309def BWWriteResGroup124 : SchedWriteRes<[BWPort01,BWPort23]> {
2310 let Latency = 11;
2311 let NumMicroOps = 2;
2312 let ResourceCycles = [1,1];
2313}
Craig Topperf82867c2017-12-13 23:11:30 +0000[diff] [blame]2314def: InstRW<[BWWriteResGroup124],
2315 (instregex "VF(N)?M(ADD|SUB|ADDSUB|SUBADD)(132|213|231)P(D|S)Ym")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2316
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2317def BWWriteResGroup126 : SchedWriteRes<[BWPort0,BWPort015]> {
2318 let Latency = 11;
2319 let NumMicroOps = 3;
2320 let ResourceCycles = [2,1];
2321}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2322def: InstRW<[BWWriteResGroup126], (instregex "VRCPPSYr",
2323 "VRSQRTPSYr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2324
2325def BWWriteResGroup127 : SchedWriteRes<[BWPort1,BWPort23]> {
2326 let Latency = 11;
2327 let NumMicroOps = 3;
2328 let ResourceCycles = [2,1];
2329}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2330def: InstRW<[BWWriteResGroup127], (instregex "(V?)ROUNDPDm",
2331 "(V?)ROUNDPSm",
2332 "(V?)ROUNDSDm",
2333 "(V?)ROUNDSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2334
2335def BWWriteResGroup128 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2336 let Latency = 11;
2337 let NumMicroOps = 3;
2338 let ResourceCycles = [1,1,1];
2339}
2340def: InstRW<[BWWriteResGroup128], (instregex "VCVTDQ2PDYrm")>;
2341
2342def BWWriteResGroup129 : SchedWriteRes<[BWPort1,BWPort5,BWPort23]> {
2343 let Latency = 11;
2344 let NumMicroOps = 4;
2345 let ResourceCycles = [1,2,1];
2346}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2347def: InstRW<[BWWriteResGroup129], (instregex "VHADDPDYrm",
2348 "VHADDPSYrm",
2349 "VHSUBPDYrm",
2350 "VHSUBPSYrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2351
2352def BWWriteResGroup130 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2353 let Latency = 11;
2354 let NumMicroOps = 6;
2355 let ResourceCycles = [1,1,1,1,2];
2356}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2357def: InstRW<[BWWriteResGroup130], (instregex "SHLD(16|32|64)mrCL",
2358 "SHRD(16|32|64)mrCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2359
2360def BWWriteResGroup131 : SchedWriteRes<[BWPort1,BWPort06,BWPort0156]> {
2361 let Latency = 11;
2362 let NumMicroOps = 7;
2363 let ResourceCycles = [2,2,3];
2364}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2365def: InstRW<[BWWriteResGroup131], (instregex "RCL(16|32|64)rCL",
2366 "RCR(16|32|64)rCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2367
2368def BWWriteResGroup132 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2369 let Latency = 11;
2370 let NumMicroOps = 9;
2371 let ResourceCycles = [1,4,1,3];
2372}
2373def: InstRW<[BWWriteResGroup132], (instregex "RCL8rCL")>;
2374
2375def BWWriteResGroup133 : SchedWriteRes<[BWPort06,BWPort0156]> {
2376 let Latency = 11;
2377 let NumMicroOps = 11;
2378 let ResourceCycles = [2,9];
2379}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2380def: InstRW<[BWWriteResGroup133], (instrs LOOPE)>;
2381def: InstRW<[BWWriteResGroup133], (instrs LOOPNE)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2382
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2383def BWWriteResGroup135 : SchedWriteRes<[BWPort1,BWPort23]> {
2384 let Latency = 12;
2385 let NumMicroOps = 3;
2386 let ResourceCycles = [2,1];
2387}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2388def: InstRW<[BWWriteResGroup135], (instregex "ADD_FI16m",
2389 "ADD_FI32m",
2390 "SUBR_FI16m",
2391 "SUBR_FI32m",
2392 "SUB_FI16m",
2393 "SUB_FI32m",
Craig Topper40d3b322018-03-22 21:55:20 +0000[diff] [blame]2394 "VROUNDPDYm",
2395 "VROUNDPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2396
2397def BWWriteResGroup136 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2398 let Latency = 12;
2399 let NumMicroOps = 4;
2400 let ResourceCycles = [1,2,1];
2401}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2402def: InstRW<[BWWriteResGroup136], (instregex "(V?)MPSADBWrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2403
2404def BWWriteResGroup137 : SchedWriteRes<[BWPort0]> {
2405 let Latency = 13;
2406 let NumMicroOps = 1;
2407 let ResourceCycles = [1];
2408}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2409def: InstRW<[BWWriteResGroup137], (instregex "SQRTPSr",
2410 "SQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2411
2412def BWWriteResGroup138 : SchedWriteRes<[BWPort0,BWPort5,BWPort23]> {
2413 let Latency = 13;
2414 let NumMicroOps = 4;
2415 let ResourceCycles = [1,2,1];
2416}
2417def: InstRW<[BWWriteResGroup138], (instregex "VMPSADBWYrmi")>;
2418
2419def BWWriteResGroup139 : SchedWriteRes<[BWPort0]> {
2420 let Latency = 14;
2421 let NumMicroOps = 1;
2422 let ResourceCycles = [1];
2423}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2424def: InstRW<[BWWriteResGroup139], (instregex "(V?)DIVPDrr",
2425 "(V?)DIVSDrr",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2426 "VSQRTPSr",
2427 "VSQRTSSr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2428
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2429def BWWriteResGroup141 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2430 let Latency = 14;
2431 let NumMicroOps = 3;
2432 let ResourceCycles = [1,1,1];
2433}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2434def: InstRW<[BWWriteResGroup141], (instregex "MUL_FI16m",
2435 "MUL_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2436
2437def BWWriteResGroup142 : SchedWriteRes<[BWPort0,BWPort1,BWPort5]> {
2438 let Latency = 14;
2439 let NumMicroOps = 4;
2440 let ResourceCycles = [2,1,1];
2441}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2442def: InstRW<[BWWriteResGroup142], (instregex "(V?)DPPS(Y?)rri")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2443
2444def BWWriteResGroup143 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2445 let Latency = 14;
2446 let NumMicroOps = 4;
2447 let ResourceCycles = [1,1,1,1];
2448}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2449def: InstRW<[BWWriteResGroup143], (instregex "(V?)DPPDrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2450
2451def BWWriteResGroup144 : SchedWriteRes<[BWPort1,BWPort6,BWPort23,BWPort0156]> {
2452 let Latency = 14;
2453 let NumMicroOps = 8;
2454 let ResourceCycles = [2,2,1,3];
2455}
2456def: InstRW<[BWWriteResGroup144], (instregex "LAR(16|32|64)rr")>;
2457
2458def BWWriteResGroup145 : SchedWriteRes<[BWPort1,BWPort06,BWPort15,BWPort0156]> {
2459 let Latency = 14;
2460 let NumMicroOps = 10;
2461 let ResourceCycles = [2,3,1,4];
2462}
2463def: InstRW<[BWWriteResGroup145], (instregex "RCR8rCL")>;
2464
2465def BWWriteResGroup146 : SchedWriteRes<[BWPort0,BWPort1,BWPort6,BWPort0156]> {
2466 let Latency = 14;
2467 let NumMicroOps = 12;
2468 let ResourceCycles = [2,1,4,5];
2469}
2470def: InstRW<[BWWriteResGroup146], (instregex "XCH_F")>;
2471
2472def BWWriteResGroup147 : SchedWriteRes<[BWPort0]> {
2473 let Latency = 15;
2474 let NumMicroOps = 1;
2475 let ResourceCycles = [1];
2476}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2477def: InstRW<[BWWriteResGroup147], (instregex "DIVR_FPrST0",
2478 "DIVR_FST0r",
2479 "DIVR_FrST0")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2480
2481def BWWriteResGroup148 : SchedWriteRes<[BWPort0,BWPort23]> {
2482 let Latency = 15;
2483 let NumMicroOps = 3;
2484 let ResourceCycles = [2,1];
2485}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2486def: InstRW<[BWWriteResGroup148], (instregex "(V?)PMULLDrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2487
2488def BWWriteResGroup149 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2489 let Latency = 15;
2490 let NumMicroOps = 10;
2491 let ResourceCycles = [1,1,1,4,1,2];
2492}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2493def: InstRW<[BWWriteResGroup149], (instregex "RCL(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2494
2495def BWWriteResGroup150 : SchedWriteRes<[BWPort0,BWPort23]> {
2496 let Latency = 16;
2497 let NumMicroOps = 2;
2498 let ResourceCycles = [1,1];
2499}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2500def: InstRW<[BWWriteResGroup150], (instregex "(V?)DIVPSrm",
2501 "(V?)DIVSSrm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2502
2503def BWWriteResGroup151 : SchedWriteRes<[BWPort0,BWPort23]> {
2504 let Latency = 16;
2505 let NumMicroOps = 3;
2506 let ResourceCycles = [2,1];
2507}
2508def: InstRW<[BWWriteResGroup151], (instregex "VPMULLDYrm")>;
2509
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2510def BWWriteResGroup153 : SchedWriteRes<[BWPort4,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2511 let Latency = 16;
2512 let NumMicroOps = 14;
2513 let ResourceCycles = [1,1,1,4,2,5];
2514}
2515def: InstRW<[BWWriteResGroup153], (instregex "CMPXCHG8B")>;
2516
2517def BWWriteResGroup154 : SchedWriteRes<[BWPort5]> {
2518 let Latency = 16;
2519 let NumMicroOps = 16;
2520 let ResourceCycles = [16];
2521}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2522def: InstRW<[BWWriteResGroup154], (instrs VZEROALL)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2523
2524def BWWriteResGroup155 : SchedWriteRes<[BWPort0,BWPort015]> {
2525 let Latency = 17;
2526 let NumMicroOps = 3;
2527 let ResourceCycles = [2,1];
2528}
2529def: InstRW<[BWWriteResGroup155], (instregex "VDIVPSYrr")>;
2530
2531def BWWriteResGroup156 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2532 let Latency = 17;
2533 let NumMicroOps = 4;
2534 let ResourceCycles = [2,1,1];
2535}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2536def: InstRW<[BWWriteResGroup156], (instregex "VRCPPSYm",
2537 "VRSQRTPSYm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2538
2539def BWWriteResGroup157 : SchedWriteRes<[BWPort0,BWPort23]> {
2540 let Latency = 18;
2541 let NumMicroOps = 2;
2542 let ResourceCycles = [1,1];
2543}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2544def: InstRW<[BWWriteResGroup157], (instregex "SQRTPSm",
2545 "SQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2546
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2547def BWWriteResGroup159 : SchedWriteRes<[BWPort5,BWPort6,BWPort06,BWPort0156]> {
2548 let Latency = 18;
2549 let NumMicroOps = 8;
2550 let ResourceCycles = [1,1,1,5];
2551}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2552def: InstRW<[BWWriteResGroup159], (instrs CPUID)>;
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2553def: InstRW<[BWWriteResGroup159], (instrs RDTSC)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2554
2555def BWWriteResGroup160 : SchedWriteRes<[BWPort1,BWPort23,BWPort237,BWPort06,BWPort15,BWPort0156]> {
2556 let Latency = 18;
2557 let NumMicroOps = 11;
2558 let ResourceCycles = [2,1,1,3,1,3];
2559}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2560def: InstRW<[BWWriteResGroup160], (instregex "RCR(8|16|32|64)mCL")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2561
2562def BWWriteResGroup161 : SchedWriteRes<[BWPort0,BWPort23]> {
2563 let Latency = 19;
2564 let NumMicroOps = 2;
2565 let ResourceCycles = [1,1];
2566}
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2567def: InstRW<[BWWriteResGroup161], (instregex "(V?)DIVPDrm",
2568 "(V?)DIVSDrm",
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2569 "VSQRTPSm",
2570 "VSQRTSSm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2571
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2572def BWWriteResGroup163 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2573 let Latency = 19;
2574 let NumMicroOps = 5;
2575 let ResourceCycles = [2,1,1,1];
2576}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2577def: InstRW<[BWWriteResGroup163], (instregex "(V?)DPPSrmi")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2578
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2579def BWWriteResGroup165 : SchedWriteRes<[BWPort0]> {
2580 let Latency = 20;
2581 let NumMicroOps = 1;
2582 let ResourceCycles = [1];
2583}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2584def: InstRW<[BWWriteResGroup165], (instregex "DIV_FPrST0",
2585 "DIV_FST0r",
2586 "DIV_FrST0",
2587 "SQRTPDr",
2588 "SQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2589
2590def BWWriteResGroup166 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23]> {
2591 let Latency = 20;
2592 let NumMicroOps = 5;
2593 let ResourceCycles = [2,1,1,1];
2594}
2595def: InstRW<[BWWriteResGroup166], (instregex "VDPPSYrmi")>;
2596
2597def BWWriteResGroup167 : SchedWriteRes<[BWPort4,BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2598 let Latency = 20;
2599 let NumMicroOps = 8;
2600 let ResourceCycles = [1,1,1,1,1,1,2];
2601}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2602def: InstRW<[BWWriteResGroup167], (instregex "INSB",
2603 "INSL",
2604 "INSW")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2605
2606def BWWriteResGroup168 : SchedWriteRes<[BWPort0]> {
2607 let Latency = 21;
2608 let NumMicroOps = 1;
2609 let ResourceCycles = [1];
2610}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2611def: InstRW<[BWWriteResGroup168], (instregex "VSQRTPDr",
2612 "VSQRTSDr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2613
2614def BWWriteResGroup169 : SchedWriteRes<[BWPort0,BWPort23]> {
2615 let Latency = 21;
2616 let NumMicroOps = 2;
2617 let ResourceCycles = [1,1];
2618}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2619def: InstRW<[BWWriteResGroup169], (instregex "DIV_F32m",
2620 "DIV_F64m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2621
2622def BWWriteResGroup170 : SchedWriteRes<[BWPort0,BWPort015]> {
2623 let Latency = 21;
2624 let NumMicroOps = 3;
2625 let ResourceCycles = [2,1];
2626}
2627def: InstRW<[BWWriteResGroup170], (instregex "VSQRTPSYr")>;
2628
2629def BWWriteResGroup171 : SchedWriteRes<[BWPort0,BWPort4,BWPort5,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2630 let Latency = 21;
2631 let NumMicroOps = 19;
2632 let ResourceCycles = [2,1,4,1,1,4,6];
2633}
2634def: InstRW<[BWWriteResGroup171], (instregex "CMPXCHG16B")>;
2635
2636def BWWriteResGroup172 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2637 let Latency = 22;
2638 let NumMicroOps = 18;
2639 let ResourceCycles = [1,1,16];
2640}
2641def: InstRW<[BWWriteResGroup172], (instregex "POPF64")>;
2642
2643def BWWriteResGroup173 : SchedWriteRes<[BWPort0,BWPort015]> {
2644 let Latency = 23;
2645 let NumMicroOps = 3;
2646 let ResourceCycles = [2,1];
2647}
2648def: InstRW<[BWWriteResGroup173], (instregex "VDIVPDYrr")>;
2649
2650def BWWriteResGroup174 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2651 let Latency = 23;
2652 let NumMicroOps = 4;
2653 let ResourceCycles = [2,1,1];
2654}
2655def: InstRW<[BWWriteResGroup174], (instregex "VDIVPSYrm")>;
2656
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2657def BWWriteResGroup176 : SchedWriteRes<[BWPort6,BWPort23,BWPort0156]> {
2658 let Latency = 23;
2659 let NumMicroOps = 19;
2660 let ResourceCycles = [3,1,15];
2661}
Craig Topper391c6f92017-12-10 01:24:08 +0000[diff] [blame]2662def: InstRW<[BWWriteResGroup176], (instregex "XRSTOR(64)?")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2663
2664def BWWriteResGroup177 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2665 let Latency = 24;
2666 let NumMicroOps = 3;
2667 let ResourceCycles = [1,1,1];
2668}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2669def: InstRW<[BWWriteResGroup177], (instregex "DIV_FI16m",
2670 "DIV_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2671
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2672def BWWriteResGroup179 : SchedWriteRes<[BWPort0,BWPort23]> {
2673 let Latency = 25;
2674 let NumMicroOps = 2;
2675 let ResourceCycles = [1,1];
2676}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2677def: InstRW<[BWWriteResGroup179], (instregex "SQRTPDm",
2678 "SQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2679
2680def BWWriteResGroup180 : SchedWriteRes<[BWPort0,BWPort23]> {
2681 let Latency = 26;
2682 let NumMicroOps = 2;
2683 let ResourceCycles = [1,1];
2684}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2685def: InstRW<[BWWriteResGroup180], (instregex "DIVR_F32m",
2686 "DIVR_F64m",
2687 "VSQRTPDm",
2688 "VSQRTSDm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2689
2690def BWWriteResGroup181 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2691 let Latency = 27;
2692 let NumMicroOps = 4;
2693 let ResourceCycles = [2,1,1];
2694}
2695def: InstRW<[BWWriteResGroup181], (instregex "VSQRTPSYm")>;
2696
2697def BWWriteResGroup182 : SchedWriteRes<[BWPort0,BWPort1,BWPort23]> {
2698 let Latency = 29;
2699 let NumMicroOps = 3;
2700 let ResourceCycles = [1,1,1];
2701}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2702def: InstRW<[BWWriteResGroup182], (instregex "DIVR_FI16m",
2703 "DIVR_FI32m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2704
2705def BWWriteResGroup183 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2706 let Latency = 29;
2707 let NumMicroOps = 4;
2708 let ResourceCycles = [2,1,1];
2709}
2710def: InstRW<[BWWriteResGroup183], (instregex "VDIVPDYrm")>;
2711
2712def BWWriteResGroup183_1 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2713 let Latency = 22;
2714 let NumMicroOps = 7;
2715 let ResourceCycles = [1,3,2,1];
2716}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2717def: InstRW<[BWWriteResGroup183_1], (instrs VGATHERQPDrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2718
2719def BWWriteResGroup183_2 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2720 let Latency = 23;
2721 let NumMicroOps = 9;
2722 let ResourceCycles = [1,3,4,1];
2723}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2724def: InstRW<[BWWriteResGroup183_2], (instrs VGATHERQPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2725
2726def BWWriteResGroup183_3 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2727 let Latency = 24;
2728 let NumMicroOps = 9;
2729 let ResourceCycles = [1,5,2,1];
2730}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2731def: InstRW<[BWWriteResGroup183_3], (instrs VGATHERQPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2732
2733def BWWriteResGroup183_4 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2734 let Latency = 25;
2735 let NumMicroOps = 7;
2736 let ResourceCycles = [1,3,2,1];
2737}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2738def: InstRW<[BWWriteResGroup183_4], (instrs VGATHERDPDrm,
2739 VGATHERDPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2740
2741def BWWriteResGroup183_5 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2742 let Latency = 26;
2743 let NumMicroOps = 9;
2744 let ResourceCycles = [1,5,2,1];
2745}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2746def: InstRW<[BWWriteResGroup183_5], (instrs VGATHERDPDYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2747
2748def BWWriteResGroup183_6 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2749 let Latency = 26;
2750 let NumMicroOps = 14;
Simon Pilgrimc21deec2018-03-24 19:37:28 +0000[diff] [blame]2751 let ResourceCycles = [1,4,8,1];
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2752}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2753def: InstRW<[BWWriteResGroup183_6], (instrs VGATHERDPSYrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2754
2755def BWWriteResGroup183_7 : SchedWriteRes<[BWPort4, BWPort5, BWPort23, BWPort0156]> {
2756 let Latency = 27;
2757 let NumMicroOps = 9;
2758 let ResourceCycles = [1,5,2,1];
2759}
Craig Topper17a31182017-12-16 18:35:29 +0000[diff] [blame]2760def: InstRW<[BWWriteResGroup183_7], (instrs VGATHERQPSrm)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2761
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2762def BWWriteResGroup185 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2763 let Latency = 29;
2764 let NumMicroOps = 27;
2765 let ResourceCycles = [1,5,1,1,19];
2766}
2767def: InstRW<[BWWriteResGroup185], (instregex "XSAVE64")>;
2768
2769def BWWriteResGroup186 : SchedWriteRes<[BWPort4,BWPort6,BWPort23,BWPort237,BWPort0156]> {
2770 let Latency = 30;
2771 let NumMicroOps = 28;
2772 let ResourceCycles = [1,6,1,1,19];
2773}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2774def: InstRW<[BWWriteResGroup186], (instregex "^XSAVE$", "XSAVEC", "XSAVES", "XSAVEOPT")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2775
2776def BWWriteResGroup187 : SchedWriteRes<[BWPort01,BWPort15,BWPort015,BWPort0156]> {
2777 let Latency = 31;
2778 let NumMicroOps = 31;
2779 let ResourceCycles = [8,1,21,1];
2780}
2781def: InstRW<[BWWriteResGroup187], (instregex "MMX_EMMS")>;
2782
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2783def BWWriteResGroup189 : SchedWriteRes<[BWPort0,BWPort015]> {
2784 let Latency = 34;
2785 let NumMicroOps = 3;
2786 let ResourceCycles = [2,1];
2787}
2788def: InstRW<[BWWriteResGroup189], (instregex "VSQRTPDYr")>;
2789
2790def BWWriteResGroup190 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2791 let Latency = 34;
2792 let NumMicroOps = 8;
2793 let ResourceCycles = [2,2,2,1,1];
2794}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2795def: InstRW<[BWWriteResGroup190], (instregex "DIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2796
2797def BWWriteResGroup191 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort06,BWPort0156]> {
2798 let Latency = 34;
2799 let NumMicroOps = 23;
2800 let ResourceCycles = [1,5,3,4,10];
2801}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2802def: InstRW<[BWWriteResGroup191], (instregex "IN(8|16|32)ri",
2803 "IN(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2804
2805def BWWriteResGroup193 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort23,BWPort0156]> {
2806 let Latency = 35;
2807 let NumMicroOps = 8;
2808 let ResourceCycles = [2,2,2,1,1];
2809}
Craig Topper13a16502018-03-19 00:56:09 +0000[diff] [blame]2810def: InstRW<[BWWriteResGroup193], (instregex "IDIV(8|16|32|64)m")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2811
2812def BWWriteResGroup194 : SchedWriteRes<[BWPort5,BWPort6,BWPort23,BWPort237,BWPort06,BWPort0156]> {
2813 let Latency = 35;
2814 let NumMicroOps = 23;
2815 let ResourceCycles = [1,5,2,1,4,10];
2816}
Craig Topper5a69a002018-03-21 06:28:42 +0000[diff] [blame]2817def: InstRW<[BWWriteResGroup194], (instregex "OUT(8|16|32)ir",
2818 "OUT(8|16|32)rr")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2819
2820def BWWriteResGroup195 : SchedWriteRes<[BWPort0,BWPort23,BWPort015]> {
2821 let Latency = 40;
2822 let NumMicroOps = 4;
2823 let ResourceCycles = [2,1,1];
2824}
2825def: InstRW<[BWWriteResGroup195], (instregex "VSQRTPDYm")>;
2826
2827def BWWriteResGroup196 : SchedWriteRes<[BWPort5,BWPort0156]> {
2828 let Latency = 42;
2829 let NumMicroOps = 22;
2830 let ResourceCycles = [2,20];
2831}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2832def: InstRW<[BWWriteResGroup196], (instrs RDTSCP)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2833
2834def BWWriteResGroup197 : SchedWriteRes<[BWPort0,BWPort01,BWPort23,BWPort05,BWPort06,BWPort015,BWPort0156]> {
2835 let Latency = 60;
2836 let NumMicroOps = 64;
2837 let ResourceCycles = [2,2,8,1,10,2,39];
2838}
2839def: InstRW<[BWWriteResGroup197], (instregex "FLDENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2840
2841def BWWriteResGroup198 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2842 let Latency = 63;
2843 let NumMicroOps = 88;
2844 let ResourceCycles = [4,4,31,1,2,1,45];
2845}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2846def: InstRW<[BWWriteResGroup198], (instrs FXRSTOR64)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2847
2848def BWWriteResGroup199 : SchedWriteRes<[BWPort0,BWPort6,BWPort23,BWPort05,BWPort06,BWPort15,BWPort0156]> {
2849 let Latency = 63;
2850 let NumMicroOps = 90;
2851 let ResourceCycles = [4,2,33,1,2,1,47];
2852}
Craig Topper2d451e72018-03-18 08:38:06 +0000[diff] [blame]2853def: InstRW<[BWWriteResGroup199], (instrs FXRSTOR)>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2854
2855def BWWriteResGroup200 : SchedWriteRes<[BWPort5,BWPort01,BWPort0156]> {
2856 let Latency = 75;
2857 let NumMicroOps = 15;
2858 let ResourceCycles = [6,3,6];
2859}
2860def: InstRW<[BWWriteResGroup200], (instregex "FNINIT")>;
2861
2862def BWWriteResGroup201 : SchedWriteRes<[BWPort0,BWPort1,BWPort5,BWPort6,BWPort01,BWPort0156]> {
2863 let Latency = 80;
2864 let NumMicroOps = 32;
2865 let ResourceCycles = [7,7,3,3,1,11];
2866}
2867def: InstRW<[BWWriteResGroup201], (instregex "DIV(16|32|64)r")>;
2868
2869def BWWriteResGroup202 : SchedWriteRes<[BWPort0,BWPort1,BWPort4,BWPort5,BWPort6,BWPort237,BWPort06,BWPort0156]> {
2870 let Latency = 115;
2871 let NumMicroOps = 100;
2872 let ResourceCycles = [9,9,11,8,1,11,21,30];
2873}
2874def: InstRW<[BWWriteResGroup202], (instregex "FSTENVm")>;
Gadi Haber323f2e12017-10-24 20:19:47 +0000[diff] [blame]2875
2876} // SchedModel
2877