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gerrit-public.fairphone.software / toolchain / llvm-project / a6a2e512cfba695072a390b0552f984dc98e25af / . / llvm / lib / Target / X86 / X86InstrInfo.cpp
blob: 0a259226167f52b4a69655785a68beb6c259beca [file] [log] [blame]
Jia Liub22310f2012-02-18 12:03:15 +0000[diff] [blame]1//===-- X86InstrInfo.cpp - X86 Instruction Information --------------------===//
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]2//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]3// The LLVM Compiler Infrastructure
4//
Chris Lattnerf3ebc3f2007-12-29 20:36:04 +0000[diff] [blame]5// This file is distributed under the University of Illinois Open Source
6// License. See LICENSE.TXT for details.
Misha Brukmanc88330a2005-04-21 23:38:14 +0000[diff] [blame]7//
John Criswell482202a2003-10-20 19:43:21 +0000[diff] [blame]8//===----------------------------------------------------------------------===//
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]9//
Chris Lattnerb4d58d72003-01-14 22:00:31 +0000[diff] [blame]10// This file contains the X86 implementation of the TargetInstrInfo class.
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]11//
12//===----------------------------------------------------------------------===//
13
Chris Lattner27d24792002-10-29 21:05:24 +0000[diff] [blame]14#include "X86InstrInfo.h"
Chris Lattner0d808742002-12-03 05:42:53 +0000[diff] [blame]15#include "X86.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]16#include "X86InstrBuilder.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]17#include "X86MachineFunctionInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]18#include "X86Subtarget.h"
19#include "X86TargetMachine.h"
Owen Andersone2f23a32007-09-07 04:06:50 +0000[diff] [blame]20#include "llvm/ADT/STLExtras.h"
Chandler Carruthed0881b2012-12-03 16:50:05 +0000[diff] [blame]21#include "llvm/CodeGen/LiveVariables.h"
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]22#include "llvm/CodeGen/MachineConstantPool.h"
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]23#include "llvm/CodeGen/MachineDominators.h"
Owen Anderson6bb0c522008-01-04 23:57:37 +0000[diff] [blame]24#include "llvm/CodeGen/MachineFrameInfo.h"
Evan Chengc8c172e2006-05-30 21:45:53 +0000[diff] [blame]25#include "llvm/CodeGen/MachineInstrBuilder.h"
Hans Wennborga6a2e512015-12-17 23:18:39 +0000[diff] [blame^]26#include "llvm/CodeGen/MachineModuleInfo.h"
Chris Lattnera10fff52007-12-31 04:13:23 +0000[diff] [blame]27#include "llvm/CodeGen/MachineRegisterInfo.h"
Andrew Trick153ebe62013-10-31 22:11:56 +0000[diff] [blame]28#include "llvm/CodeGen/StackMaps.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]29#include "llvm/IR/DerivedTypes.h"
Eric Christopher79cc1e32014-09-02 22:28:02 +0000[diff] [blame]30#include "llvm/IR/Function.h"
Chandler Carruth9fb823b2013-01-02 11:36:10 +0000[diff] [blame]31#include "llvm/IR/LLVMContext.h"
Craig Topperb25fda92012-03-17 18:46:09 +0000[diff] [blame]32#include "llvm/MC/MCAsmInfo.h"
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]33#include "llvm/MC/MCExpr.h"
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]34#include "llvm/MC/MCInst.h"
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]35#include "llvm/Support/CommandLine.h"
David Greened589daf2010-01-05 01:29:29 +0000[diff] [blame]36#include "llvm/Support/Debug.h"
Torok Edwin6dd27302009-07-08 18:01:40 +0000[diff] [blame]37#include "llvm/Support/ErrorHandling.h"
38#include "llvm/Support/raw_ostream.h"
Evan Chenge95f3912007-09-25 01:57:46 +0000[diff] [blame]39#include "llvm/Target/TargetOptions.h"
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]40#include <limits>
41
Chandler Carruthd174b722014-04-22 02:03:14 +0000[diff] [blame]42using namespace llvm;
43
Chandler Carruthe96dd892014-04-21 22:55:11 +0000[diff] [blame]44#define DEBUG_TYPE "x86-instr-info"
45
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]46#define GET_INSTRINFO_CTOR_DTOR
Evan Cheng1e210d02011-06-28 20:07:07 +0000[diff] [blame]47#include "X86GenInstrInfo.inc"
48
Chris Lattnera6f074f2009-08-23 03:41:05 +0000[diff] [blame]49static cl::opt<bool>
50NoFusing("disable-spill-fusing",
51 cl::desc("Disable fusing of spill code into instructions"));
52static cl::opt<bool>
53PrintFailedFusing("print-failed-fuse-candidates",
54 cl::desc("Print instructions that the allocator wants to"
55 " fuse, but the X86 backend currently can't"),
56 cl::Hidden);
57static cl::opt<bool>
58ReMatPICStubLoad("remat-pic-stub-load",
59 cl::desc("Re-materialize load from stub in PIC mode"),
60 cl::init(false), cl::Hidden);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]61
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]62enum {
63 // Select which memory operand is being unfolded.
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]64 // (stored in bits 0 - 3)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]65 TB_INDEX_0 = 0,
66 TB_INDEX_1 = 1,
67 TB_INDEX_2 = 2,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]68 TB_INDEX_3 = 3,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]69 TB_INDEX_4 = 4,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]70 TB_INDEX_MASK = 0xf,
71
72 // Do not insert the reverse map (MemOp -> RegOp) into the table.
73 // This may be needed because there is a many -> one mapping.
74 TB_NO_REVERSE = 1 << 4,
75
76 // Do not insert the forward map (RegOp -> MemOp) into the table.
77 // This is needed for Native Client, which prohibits branch
78 // instructions from using a memory operand.
79 TB_NO_FORWARD = 1 << 5,
80
81 TB_FOLDED_LOAD = 1 << 6,
82 TB_FOLDED_STORE = 1 << 7,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]83
84 // Minimum alignment required for load/store.
85 // Used for RegOp->MemOp conversion.
86 // (stored in bits 8 - 15)
87 TB_ALIGN_SHIFT = 8,
88 TB_ALIGN_NONE = 0 << TB_ALIGN_SHIFT,
89 TB_ALIGN_16 = 16 << TB_ALIGN_SHIFT,
90 TB_ALIGN_32 = 32 << TB_ALIGN_SHIFT,
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]91 TB_ALIGN_64 = 64 << TB_ALIGN_SHIFT,
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]92 TB_ALIGN_MASK = 0xff << TB_ALIGN_SHIFT
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]93};
94
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]95struct X86MemoryFoldTableEntry {
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]96 uint16_t RegOp;
97 uint16_t MemOp;
Craig Topper1cac50b2012-06-23 08:01:18 +0000[diff] [blame]98 uint16_t Flags;
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]99};
100
Juergen Ributzkad12ccbd2013-11-19 00:57:56 +0000[diff] [blame]101// Pin the vtable to this file.
102void X86InstrInfo::anchor() {}
103
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]104X86InstrInfo::X86InstrInfo(X86Subtarget &STI)
David Majnemerf828a0c2015-10-01 18:44:59 +0000[diff] [blame]105 : X86GenInstrInfo((STI.isTarget64BitLP64() ? X86::ADJCALLSTACKDOWN64
106 : X86::ADJCALLSTACKDOWN32),
107 (STI.isTarget64BitLP64() ? X86::ADJCALLSTACKUP64
108 : X86::ADJCALLSTACKUP32),
109 X86::CATCHRET),
Eric Christophered6a4462015-03-12 17:54:19 +0000[diff] [blame]110 Subtarget(STI), RI(STI.getTargetTriple()) {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]111
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]112 static const X86MemoryFoldTableEntry MemoryFoldTable2Addr[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]113 { X86::ADC32ri, X86::ADC32mi, 0 },
114 { X86::ADC32ri8, X86::ADC32mi8, 0 },
115 { X86::ADC32rr, X86::ADC32mr, 0 },
116 { X86::ADC64ri32, X86::ADC64mi32, 0 },
117 { X86::ADC64ri8, X86::ADC64mi8, 0 },
118 { X86::ADC64rr, X86::ADC64mr, 0 },
119 { X86::ADD16ri, X86::ADD16mi, 0 },
120 { X86::ADD16ri8, X86::ADD16mi8, 0 },
121 { X86::ADD16ri_DB, X86::ADD16mi, TB_NO_REVERSE },
122 { X86::ADD16ri8_DB, X86::ADD16mi8, TB_NO_REVERSE },
123 { X86::ADD16rr, X86::ADD16mr, 0 },
124 { X86::ADD16rr_DB, X86::ADD16mr, TB_NO_REVERSE },
125 { X86::ADD32ri, X86::ADD32mi, 0 },
126 { X86::ADD32ri8, X86::ADD32mi8, 0 },
127 { X86::ADD32ri_DB, X86::ADD32mi, TB_NO_REVERSE },
128 { X86::ADD32ri8_DB, X86::ADD32mi8, TB_NO_REVERSE },
129 { X86::ADD32rr, X86::ADD32mr, 0 },
130 { X86::ADD32rr_DB, X86::ADD32mr, TB_NO_REVERSE },
131 { X86::ADD64ri32, X86::ADD64mi32, 0 },
132 { X86::ADD64ri8, X86::ADD64mi8, 0 },
133 { X86::ADD64ri32_DB,X86::ADD64mi32, TB_NO_REVERSE },
134 { X86::ADD64ri8_DB, X86::ADD64mi8, TB_NO_REVERSE },
135 { X86::ADD64rr, X86::ADD64mr, 0 },
136 { X86::ADD64rr_DB, X86::ADD64mr, TB_NO_REVERSE },
137 { X86::ADD8ri, X86::ADD8mi, 0 },
138 { X86::ADD8rr, X86::ADD8mr, 0 },
139 { X86::AND16ri, X86::AND16mi, 0 },
140 { X86::AND16ri8, X86::AND16mi8, 0 },
141 { X86::AND16rr, X86::AND16mr, 0 },
142 { X86::AND32ri, X86::AND32mi, 0 },
143 { X86::AND32ri8, X86::AND32mi8, 0 },
144 { X86::AND32rr, X86::AND32mr, 0 },
145 { X86::AND64ri32, X86::AND64mi32, 0 },
146 { X86::AND64ri8, X86::AND64mi8, 0 },
147 { X86::AND64rr, X86::AND64mr, 0 },
148 { X86::AND8ri, X86::AND8mi, 0 },
149 { X86::AND8rr, X86::AND8mr, 0 },
150 { X86::DEC16r, X86::DEC16m, 0 },
151 { X86::DEC32r, X86::DEC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]152 { X86::DEC64r, X86::DEC64m, 0 },
153 { X86::DEC8r, X86::DEC8m, 0 },
154 { X86::INC16r, X86::INC16m, 0 },
155 { X86::INC32r, X86::INC32m, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]156 { X86::INC64r, X86::INC64m, 0 },
157 { X86::INC8r, X86::INC8m, 0 },
158 { X86::NEG16r, X86::NEG16m, 0 },
159 { X86::NEG32r, X86::NEG32m, 0 },
160 { X86::NEG64r, X86::NEG64m, 0 },
161 { X86::NEG8r, X86::NEG8m, 0 },
162 { X86::NOT16r, X86::NOT16m, 0 },
163 { X86::NOT32r, X86::NOT32m, 0 },
164 { X86::NOT64r, X86::NOT64m, 0 },
165 { X86::NOT8r, X86::NOT8m, 0 },
166 { X86::OR16ri, X86::OR16mi, 0 },
167 { X86::OR16ri8, X86::OR16mi8, 0 },
168 { X86::OR16rr, X86::OR16mr, 0 },
169 { X86::OR32ri, X86::OR32mi, 0 },
170 { X86::OR32ri8, X86::OR32mi8, 0 },
171 { X86::OR32rr, X86::OR32mr, 0 },
172 { X86::OR64ri32, X86::OR64mi32, 0 },
173 { X86::OR64ri8, X86::OR64mi8, 0 },
174 { X86::OR64rr, X86::OR64mr, 0 },
175 { X86::OR8ri, X86::OR8mi, 0 },
176 { X86::OR8rr, X86::OR8mr, 0 },
177 { X86::ROL16r1, X86::ROL16m1, 0 },
178 { X86::ROL16rCL, X86::ROL16mCL, 0 },
179 { X86::ROL16ri, X86::ROL16mi, 0 },
180 { X86::ROL32r1, X86::ROL32m1, 0 },
181 { X86::ROL32rCL, X86::ROL32mCL, 0 },
182 { X86::ROL32ri, X86::ROL32mi, 0 },
183 { X86::ROL64r1, X86::ROL64m1, 0 },
184 { X86::ROL64rCL, X86::ROL64mCL, 0 },
185 { X86::ROL64ri, X86::ROL64mi, 0 },
186 { X86::ROL8r1, X86::ROL8m1, 0 },
187 { X86::ROL8rCL, X86::ROL8mCL, 0 },
188 { X86::ROL8ri, X86::ROL8mi, 0 },
189 { X86::ROR16r1, X86::ROR16m1, 0 },
190 { X86::ROR16rCL, X86::ROR16mCL, 0 },
191 { X86::ROR16ri, X86::ROR16mi, 0 },
192 { X86::ROR32r1, X86::ROR32m1, 0 },
193 { X86::ROR32rCL, X86::ROR32mCL, 0 },
194 { X86::ROR32ri, X86::ROR32mi, 0 },
195 { X86::ROR64r1, X86::ROR64m1, 0 },
196 { X86::ROR64rCL, X86::ROR64mCL, 0 },
197 { X86::ROR64ri, X86::ROR64mi, 0 },
198 { X86::ROR8r1, X86::ROR8m1, 0 },
199 { X86::ROR8rCL, X86::ROR8mCL, 0 },
200 { X86::ROR8ri, X86::ROR8mi, 0 },
201 { X86::SAR16r1, X86::SAR16m1, 0 },
202 { X86::SAR16rCL, X86::SAR16mCL, 0 },
203 { X86::SAR16ri, X86::SAR16mi, 0 },
204 { X86::SAR32r1, X86::SAR32m1, 0 },
205 { X86::SAR32rCL, X86::SAR32mCL, 0 },
206 { X86::SAR32ri, X86::SAR32mi, 0 },
207 { X86::SAR64r1, X86::SAR64m1, 0 },
208 { X86::SAR64rCL, X86::SAR64mCL, 0 },
209 { X86::SAR64ri, X86::SAR64mi, 0 },
210 { X86::SAR8r1, X86::SAR8m1, 0 },
211 { X86::SAR8rCL, X86::SAR8mCL, 0 },
212 { X86::SAR8ri, X86::SAR8mi, 0 },
213 { X86::SBB32ri, X86::SBB32mi, 0 },
214 { X86::SBB32ri8, X86::SBB32mi8, 0 },
215 { X86::SBB32rr, X86::SBB32mr, 0 },
216 { X86::SBB64ri32, X86::SBB64mi32, 0 },
217 { X86::SBB64ri8, X86::SBB64mi8, 0 },
218 { X86::SBB64rr, X86::SBB64mr, 0 },
219 { X86::SHL16rCL, X86::SHL16mCL, 0 },
220 { X86::SHL16ri, X86::SHL16mi, 0 },
221 { X86::SHL32rCL, X86::SHL32mCL, 0 },
222 { X86::SHL32ri, X86::SHL32mi, 0 },
223 { X86::SHL64rCL, X86::SHL64mCL, 0 },
224 { X86::SHL64ri, X86::SHL64mi, 0 },
225 { X86::SHL8rCL, X86::SHL8mCL, 0 },
226 { X86::SHL8ri, X86::SHL8mi, 0 },
227 { X86::SHLD16rrCL, X86::SHLD16mrCL, 0 },
228 { X86::SHLD16rri8, X86::SHLD16mri8, 0 },
229 { X86::SHLD32rrCL, X86::SHLD32mrCL, 0 },
230 { X86::SHLD32rri8, X86::SHLD32mri8, 0 },
231 { X86::SHLD64rrCL, X86::SHLD64mrCL, 0 },
232 { X86::SHLD64rri8, X86::SHLD64mri8, 0 },
233 { X86::SHR16r1, X86::SHR16m1, 0 },
234 { X86::SHR16rCL, X86::SHR16mCL, 0 },
235 { X86::SHR16ri, X86::SHR16mi, 0 },
236 { X86::SHR32r1, X86::SHR32m1, 0 },
237 { X86::SHR32rCL, X86::SHR32mCL, 0 },
238 { X86::SHR32ri, X86::SHR32mi, 0 },
239 { X86::SHR64r1, X86::SHR64m1, 0 },
240 { X86::SHR64rCL, X86::SHR64mCL, 0 },
241 { X86::SHR64ri, X86::SHR64mi, 0 },
242 { X86::SHR8r1, X86::SHR8m1, 0 },
243 { X86::SHR8rCL, X86::SHR8mCL, 0 },
244 { X86::SHR8ri, X86::SHR8mi, 0 },
245 { X86::SHRD16rrCL, X86::SHRD16mrCL, 0 },
246 { X86::SHRD16rri8, X86::SHRD16mri8, 0 },
247 { X86::SHRD32rrCL, X86::SHRD32mrCL, 0 },
248 { X86::SHRD32rri8, X86::SHRD32mri8, 0 },
249 { X86::SHRD64rrCL, X86::SHRD64mrCL, 0 },
250 { X86::SHRD64rri8, X86::SHRD64mri8, 0 },
251 { X86::SUB16ri, X86::SUB16mi, 0 },
252 { X86::SUB16ri8, X86::SUB16mi8, 0 },
253 { X86::SUB16rr, X86::SUB16mr, 0 },
254 { X86::SUB32ri, X86::SUB32mi, 0 },
255 { X86::SUB32ri8, X86::SUB32mi8, 0 },
256 { X86::SUB32rr, X86::SUB32mr, 0 },
257 { X86::SUB64ri32, X86::SUB64mi32, 0 },
258 { X86::SUB64ri8, X86::SUB64mi8, 0 },
259 { X86::SUB64rr, X86::SUB64mr, 0 },
260 { X86::SUB8ri, X86::SUB8mi, 0 },
261 { X86::SUB8rr, X86::SUB8mr, 0 },
262 { X86::XOR16ri, X86::XOR16mi, 0 },
263 { X86::XOR16ri8, X86::XOR16mi8, 0 },
264 { X86::XOR16rr, X86::XOR16mr, 0 },
265 { X86::XOR32ri, X86::XOR32mi, 0 },
266 { X86::XOR32ri8, X86::XOR32mi8, 0 },
267 { X86::XOR32rr, X86::XOR32mr, 0 },
268 { X86::XOR64ri32, X86::XOR64mi32, 0 },
269 { X86::XOR64ri8, X86::XOR64mi8, 0 },
270 { X86::XOR64rr, X86::XOR64mr, 0 },
271 { X86::XOR8ri, X86::XOR8mi, 0 },
272 { X86::XOR8rr, X86::XOR8mr, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]273 };
274
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]275 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2Addr) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]276 AddTableEntry(RegOp2MemOpTable2Addr, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]277 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]278 // Index 0, folded load and store, no alignment requirement.
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]279 Entry.Flags | TB_INDEX_0 | TB_FOLDED_LOAD | TB_FOLDED_STORE);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]280 }
281
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]282 static const X86MemoryFoldTableEntry MemoryFoldTable0[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]283 { X86::BT16ri8, X86::BT16mi8, TB_FOLDED_LOAD },
284 { X86::BT32ri8, X86::BT32mi8, TB_FOLDED_LOAD },
285 { X86::BT64ri8, X86::BT64mi8, TB_FOLDED_LOAD },
286 { X86::CALL32r, X86::CALL32m, TB_FOLDED_LOAD },
287 { X86::CALL64r, X86::CALL64m, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]288 { X86::CMP16ri, X86::CMP16mi, TB_FOLDED_LOAD },
289 { X86::CMP16ri8, X86::CMP16mi8, TB_FOLDED_LOAD },
290 { X86::CMP16rr, X86::CMP16mr, TB_FOLDED_LOAD },
291 { X86::CMP32ri, X86::CMP32mi, TB_FOLDED_LOAD },
292 { X86::CMP32ri8, X86::CMP32mi8, TB_FOLDED_LOAD },
293 { X86::CMP32rr, X86::CMP32mr, TB_FOLDED_LOAD },
294 { X86::CMP64ri32, X86::CMP64mi32, TB_FOLDED_LOAD },
295 { X86::CMP64ri8, X86::CMP64mi8, TB_FOLDED_LOAD },
296 { X86::CMP64rr, X86::CMP64mr, TB_FOLDED_LOAD },
297 { X86::CMP8ri, X86::CMP8mi, TB_FOLDED_LOAD },
298 { X86::CMP8rr, X86::CMP8mr, TB_FOLDED_LOAD },
299 { X86::DIV16r, X86::DIV16m, TB_FOLDED_LOAD },
300 { X86::DIV32r, X86::DIV32m, TB_FOLDED_LOAD },
301 { X86::DIV64r, X86::DIV64m, TB_FOLDED_LOAD },
302 { X86::DIV8r, X86::DIV8m, TB_FOLDED_LOAD },
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]303 { X86::EXTRACTPSrr, X86::EXTRACTPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]304 { X86::IDIV16r, X86::IDIV16m, TB_FOLDED_LOAD },
305 { X86::IDIV32r, X86::IDIV32m, TB_FOLDED_LOAD },
306 { X86::IDIV64r, X86::IDIV64m, TB_FOLDED_LOAD },
307 { X86::IDIV8r, X86::IDIV8m, TB_FOLDED_LOAD },
308 { X86::IMUL16r, X86::IMUL16m, TB_FOLDED_LOAD },
309 { X86::IMUL32r, X86::IMUL32m, TB_FOLDED_LOAD },
310 { X86::IMUL64r, X86::IMUL64m, TB_FOLDED_LOAD },
311 { X86::IMUL8r, X86::IMUL8m, TB_FOLDED_LOAD },
312 { X86::JMP32r, X86::JMP32m, TB_FOLDED_LOAD },
313 { X86::JMP64r, X86::JMP64m, TB_FOLDED_LOAD },
314 { X86::MOV16ri, X86::MOV16mi, TB_FOLDED_STORE },
315 { X86::MOV16rr, X86::MOV16mr, TB_FOLDED_STORE },
316 { X86::MOV32ri, X86::MOV32mi, TB_FOLDED_STORE },
317 { X86::MOV32rr, X86::MOV32mr, TB_FOLDED_STORE },
318 { X86::MOV64ri32, X86::MOV64mi32, TB_FOLDED_STORE },
319 { X86::MOV64rr, X86::MOV64mr, TB_FOLDED_STORE },
320 { X86::MOV8ri, X86::MOV8mi, TB_FOLDED_STORE },
321 { X86::MOV8rr, X86::MOV8mr, TB_FOLDED_STORE },
322 { X86::MOV8rr_NOREX, X86::MOV8mr_NOREX, TB_FOLDED_STORE },
323 { X86::MOVAPDrr, X86::MOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
324 { X86::MOVAPSrr, X86::MOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
325 { X86::MOVDQArr, X86::MOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]326 { X86::MOVPDI2DIrr, X86::MOVPDI2DImr, TB_FOLDED_STORE },
327 { X86::MOVPQIto64rr,X86::MOVPQI2QImr, TB_FOLDED_STORE },
328 { X86::MOVSDto64rr, X86::MOVSDto64mr, TB_FOLDED_STORE },
329 { X86::MOVSS2DIrr, X86::MOVSS2DImr, TB_FOLDED_STORE },
330 { X86::MOVUPDrr, X86::MOVUPDmr, TB_FOLDED_STORE },
331 { X86::MOVUPSrr, X86::MOVUPSmr, TB_FOLDED_STORE },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]332 { X86::MUL16r, X86::MUL16m, TB_FOLDED_LOAD },
333 { X86::MUL32r, X86::MUL32m, TB_FOLDED_LOAD },
334 { X86::MUL64r, X86::MUL64m, TB_FOLDED_LOAD },
335 { X86::MUL8r, X86::MUL8m, TB_FOLDED_LOAD },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]336 { X86::PEXTRDrr, X86::PEXTRDmr, TB_FOLDED_STORE },
337 { X86::PEXTRQrr, X86::PEXTRQmr, TB_FOLDED_STORE },
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]338 { X86::PUSH16r, X86::PUSH16rmm, TB_FOLDED_LOAD },
339 { X86::PUSH32r, X86::PUSH32rmm, TB_FOLDED_LOAD },
340 { X86::PUSH64r, X86::PUSH64rmm, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]341 { X86::SETAEr, X86::SETAEm, TB_FOLDED_STORE },
342 { X86::SETAr, X86::SETAm, TB_FOLDED_STORE },
343 { X86::SETBEr, X86::SETBEm, TB_FOLDED_STORE },
344 { X86::SETBr, X86::SETBm, TB_FOLDED_STORE },
345 { X86::SETEr, X86::SETEm, TB_FOLDED_STORE },
346 { X86::SETGEr, X86::SETGEm, TB_FOLDED_STORE },
347 { X86::SETGr, X86::SETGm, TB_FOLDED_STORE },
348 { X86::SETLEr, X86::SETLEm, TB_FOLDED_STORE },
349 { X86::SETLr, X86::SETLm, TB_FOLDED_STORE },
350 { X86::SETNEr, X86::SETNEm, TB_FOLDED_STORE },
351 { X86::SETNOr, X86::SETNOm, TB_FOLDED_STORE },
352 { X86::SETNPr, X86::SETNPm, TB_FOLDED_STORE },
353 { X86::SETNSr, X86::SETNSm, TB_FOLDED_STORE },
354 { X86::SETOr, X86::SETOm, TB_FOLDED_STORE },
355 { X86::SETPr, X86::SETPm, TB_FOLDED_STORE },
356 { X86::SETSr, X86::SETSm, TB_FOLDED_STORE },
357 { X86::TAILJMPr, X86::TAILJMPm, TB_FOLDED_LOAD },
358 { X86::TAILJMPr64, X86::TAILJMPm64, TB_FOLDED_LOAD },
Reid Klecknera580b6e2015-01-30 21:03:31 +0000[diff] [blame]359 { X86::TAILJMPr64_REX, X86::TAILJMPm64_REX, TB_FOLDED_LOAD },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]360 { X86::TEST16ri, X86::TEST16mi, TB_FOLDED_LOAD },
361 { X86::TEST32ri, X86::TEST32mi, TB_FOLDED_LOAD },
362 { X86::TEST64ri32, X86::TEST64mi32, TB_FOLDED_LOAD },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]363 { X86::TEST8ri, X86::TEST8mi, TB_FOLDED_LOAD },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]364
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]365 // AVX 128-bit versions of foldable instructions
Craig Topperd09a9af2012-12-26 01:47:12 +0000[diff] [blame]366 { X86::VEXTRACTPSrr,X86::VEXTRACTPSmr, TB_FOLDED_STORE },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]367 { X86::VEXTRACTF128rr, X86::VEXTRACTF128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]368 { X86::VMOVAPDrr, X86::VMOVAPDmr, TB_FOLDED_STORE | TB_ALIGN_16 },
369 { X86::VMOVAPSrr, X86::VMOVAPSmr, TB_FOLDED_STORE | TB_ALIGN_16 },
370 { X86::VMOVDQArr, X86::VMOVDQAmr, TB_FOLDED_STORE | TB_ALIGN_16 },
371 { X86::VMOVPDI2DIrr,X86::VMOVPDI2DImr, TB_FOLDED_STORE },
372 { X86::VMOVPQIto64rr, X86::VMOVPQI2QImr,TB_FOLDED_STORE },
373 { X86::VMOVSDto64rr,X86::VMOVSDto64mr, TB_FOLDED_STORE },
374 { X86::VMOVSS2DIrr, X86::VMOVSS2DImr, TB_FOLDED_STORE },
375 { X86::VMOVUPDrr, X86::VMOVUPDmr, TB_FOLDED_STORE },
376 { X86::VMOVUPSrr, X86::VMOVUPSmr, TB_FOLDED_STORE },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]377 { X86::VPEXTRDrr, X86::VPEXTRDmr, TB_FOLDED_STORE },
378 { X86::VPEXTRQrr, X86::VPEXTRQmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]379
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]380 // AVX 256-bit foldable instructions
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]381 { X86::VEXTRACTI128rr, X86::VEXTRACTI128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]382 { X86::VMOVAPDYrr, X86::VMOVAPDYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
383 { X86::VMOVAPSYrr, X86::VMOVAPSYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
384 { X86::VMOVDQAYrr, X86::VMOVDQAYmr, TB_FOLDED_STORE | TB_ALIGN_32 },
385 { X86::VMOVUPDYrr, X86::VMOVUPDYmr, TB_FOLDED_STORE },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]386 { X86::VMOVUPSYrr, X86::VMOVUPSYmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]387
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]388 // AVX-512 foldable instructions
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]389 { X86::VMOVPDI2DIZrr, X86::VMOVPDI2DIZmr, TB_FOLDED_STORE },
390 { X86::VMOVAPDZrr, X86::VMOVAPDZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
391 { X86::VMOVAPSZrr, X86::VMOVAPSZmr, TB_FOLDED_STORE | TB_ALIGN_64 },
392 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
393 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zmr, TB_FOLDED_STORE | TB_ALIGN_64 },
394 { X86::VMOVUPDZrr, X86::VMOVUPDZmr, TB_FOLDED_STORE },
395 { X86::VMOVUPSZrr, X86::VMOVUPSZmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]396 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zmr, TB_FOLDED_STORE },
397 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zmr, TB_FOLDED_STORE },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]398 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zmr, TB_FOLDED_STORE },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]399 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zmr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]400
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]401 // AVX-512 foldable instructions (256-bit versions)
402 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
403 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
404 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
405 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256mr, TB_FOLDED_STORE | TB_ALIGN_32 },
406 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256mr, TB_FOLDED_STORE },
407 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256mr, TB_FOLDED_STORE },
408 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256mr, TB_FOLDED_STORE },
409 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256mr, TB_FOLDED_STORE },
410 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256mr, TB_FOLDED_STORE },
411 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]412
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]413 // AVX-512 foldable instructions (128-bit versions)
414 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
415 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
416 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
417 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128mr, TB_FOLDED_STORE | TB_ALIGN_16 },
418 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128mr, TB_FOLDED_STORE },
419 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128mr, TB_FOLDED_STORE },
420 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128mr, TB_FOLDED_STORE },
421 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128mr, TB_FOLDED_STORE },
422 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128mr, TB_FOLDED_STORE },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]423 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128mr, TB_FOLDED_STORE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]424
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]425 // F16C foldable instructions
426 { X86::VCVTPS2PHrr, X86::VCVTPS2PHmr, TB_FOLDED_STORE },
427 { X86::VCVTPS2PHYrr, X86::VCVTPS2PHYmr, TB_FOLDED_STORE }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]428 };
429
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]430 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable0) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]431 AddTableEntry(RegOp2MemOpTable0, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]432 Entry.RegOp, Entry.MemOp, TB_INDEX_0 | Entry.Flags);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]433 }
434
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]435 static const X86MemoryFoldTableEntry MemoryFoldTable1[] = {
Simon Pilgrim3a771802015-06-07 18:34:25 +0000[diff] [blame]436 { X86::BSF16rr, X86::BSF16rm, 0 },
437 { X86::BSF32rr, X86::BSF32rm, 0 },
438 { X86::BSF64rr, X86::BSF64rm, 0 },
439 { X86::BSR16rr, X86::BSR16rm, 0 },
440 { X86::BSR32rr, X86::BSR32rm, 0 },
441 { X86::BSR64rr, X86::BSR64rm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]442 { X86::CMP16rr, X86::CMP16rm, 0 },
443 { X86::CMP32rr, X86::CMP32rm, 0 },
444 { X86::CMP64rr, X86::CMP64rm, 0 },
445 { X86::CMP8rr, X86::CMP8rm, 0 },
446 { X86::CVTSD2SSrr, X86::CVTSD2SSrm, 0 },
447 { X86::CVTSI2SD64rr, X86::CVTSI2SD64rm, 0 },
448 { X86::CVTSI2SDrr, X86::CVTSI2SDrm, 0 },
449 { X86::CVTSI2SS64rr, X86::CVTSI2SS64rm, 0 },
450 { X86::CVTSI2SSrr, X86::CVTSI2SSrm, 0 },
451 { X86::CVTSS2SDrr, X86::CVTSS2SDrm, 0 },
452 { X86::CVTTSD2SI64rr, X86::CVTTSD2SI64rm, 0 },
453 { X86::CVTTSD2SIrr, X86::CVTTSD2SIrm, 0 },
454 { X86::CVTTSS2SI64rr, X86::CVTTSS2SI64rm, 0 },
455 { X86::CVTTSS2SIrr, X86::CVTTSS2SIrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]456 { X86::IMUL16rri, X86::IMUL16rmi, 0 },
457 { X86::IMUL16rri8, X86::IMUL16rmi8, 0 },
458 { X86::IMUL32rri, X86::IMUL32rmi, 0 },
459 { X86::IMUL32rri8, X86::IMUL32rmi8, 0 },
460 { X86::IMUL64rri32, X86::IMUL64rmi32, 0 },
461 { X86::IMUL64rri8, X86::IMUL64rmi8, 0 },
462 { X86::Int_COMISDrr, X86::Int_COMISDrm, 0 },
463 { X86::Int_COMISSrr, X86::Int_COMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]464 { X86::CVTSD2SI64rr, X86::CVTSD2SI64rm, 0 },
465 { X86::CVTSD2SIrr, X86::CVTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]466 { X86::CVTSS2SI64rr, X86::CVTSS2SI64rm, 0 },
467 { X86::CVTSS2SIrr, X86::CVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]468 { X86::CVTDQ2PDrr, X86::CVTDQ2PDrm, TB_ALIGN_16 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]469 { X86::CVTDQ2PSrr, X86::CVTDQ2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]470 { X86::CVTPD2DQrr, X86::CVTPD2DQrm, TB_ALIGN_16 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]471 { X86::CVTPD2PSrr, X86::CVTPD2PSrm, TB_ALIGN_16 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]472 { X86::CVTPS2DQrr, X86::CVTPS2DQrm, TB_ALIGN_16 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]473 { X86::CVTPS2PDrr, X86::CVTPS2PDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]474 { X86::CVTTPD2DQrr, X86::CVTTPD2DQrm, TB_ALIGN_16 },
475 { X86::CVTTPS2DQrr, X86::CVTTPS2DQrm, TB_ALIGN_16 },
476 { X86::Int_CVTTSD2SI64rr,X86::Int_CVTTSD2SI64rm, 0 },
477 { X86::Int_CVTTSD2SIrr, X86::Int_CVTTSD2SIrm, 0 },
478 { X86::Int_CVTTSS2SI64rr,X86::Int_CVTTSS2SI64rm, 0 },
479 { X86::Int_CVTTSS2SIrr, X86::Int_CVTTSS2SIrm, 0 },
480 { X86::Int_UCOMISDrr, X86::Int_UCOMISDrm, 0 },
481 { X86::Int_UCOMISSrr, X86::Int_UCOMISSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]482 { X86::MOV16rr, X86::MOV16rm, 0 },
483 { X86::MOV32rr, X86::MOV32rm, 0 },
484 { X86::MOV64rr, X86::MOV64rm, 0 },
485 { X86::MOV64toPQIrr, X86::MOVQI2PQIrm, 0 },
486 { X86::MOV64toSDrr, X86::MOV64toSDrm, 0 },
487 { X86::MOV8rr, X86::MOV8rm, 0 },
488 { X86::MOVAPDrr, X86::MOVAPDrm, TB_ALIGN_16 },
489 { X86::MOVAPSrr, X86::MOVAPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]490 { X86::MOVDDUPrr, X86::MOVDDUPrm, 0 },
491 { X86::MOVDI2PDIrr, X86::MOVDI2PDIrm, 0 },
492 { X86::MOVDI2SSrr, X86::MOVDI2SSrm, 0 },
493 { X86::MOVDQArr, X86::MOVDQArm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]494 { X86::MOVSHDUPrr, X86::MOVSHDUPrm, TB_ALIGN_16 },
495 { X86::MOVSLDUPrr, X86::MOVSLDUPrm, TB_ALIGN_16 },
496 { X86::MOVSX16rr8, X86::MOVSX16rm8, 0 },
497 { X86::MOVSX32rr16, X86::MOVSX32rm16, 0 },
498 { X86::MOVSX32rr8, X86::MOVSX32rm8, 0 },
499 { X86::MOVSX64rr16, X86::MOVSX64rm16, 0 },
500 { X86::MOVSX64rr32, X86::MOVSX64rm32, 0 },
501 { X86::MOVSX64rr8, X86::MOVSX64rm8, 0 },
502 { X86::MOVUPDrr, X86::MOVUPDrm, TB_ALIGN_16 },
503 { X86::MOVUPSrr, X86::MOVUPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]504 { X86::MOVZPQILo2PQIrr, X86::MOVZPQILo2PQIrm, TB_ALIGN_16 },
505 { X86::MOVZX16rr8, X86::MOVZX16rm8, 0 },
506 { X86::MOVZX32rr16, X86::MOVZX32rm16, 0 },
507 { X86::MOVZX32_NOREXrr8, X86::MOVZX32_NOREXrm8, 0 },
508 { X86::MOVZX32rr8, X86::MOVZX32rm8, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]509 { X86::PABSBrr128, X86::PABSBrm128, TB_ALIGN_16 },
510 { X86::PABSDrr128, X86::PABSDrm128, TB_ALIGN_16 },
511 { X86::PABSWrr128, X86::PABSWrm128, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]512 { X86::PCMPESTRIrr, X86::PCMPESTRIrm, TB_ALIGN_16 },
513 { X86::PCMPESTRM128rr, X86::PCMPESTRM128rm, TB_ALIGN_16 },
514 { X86::PCMPISTRIrr, X86::PCMPISTRIrm, TB_ALIGN_16 },
515 { X86::PCMPISTRM128rr, X86::PCMPISTRM128rm, TB_ALIGN_16 },
516 { X86::PHMINPOSUWrr128, X86::PHMINPOSUWrm128, TB_ALIGN_16 },
517 { X86::PMOVSXBDrr, X86::PMOVSXBDrm, TB_ALIGN_16 },
518 { X86::PMOVSXBQrr, X86::PMOVSXBQrm, TB_ALIGN_16 },
519 { X86::PMOVSXBWrr, X86::PMOVSXBWrm, TB_ALIGN_16 },
520 { X86::PMOVSXDQrr, X86::PMOVSXDQrm, TB_ALIGN_16 },
521 { X86::PMOVSXWDrr, X86::PMOVSXWDrm, TB_ALIGN_16 },
522 { X86::PMOVSXWQrr, X86::PMOVSXWQrm, TB_ALIGN_16 },
523 { X86::PMOVZXBDrr, X86::PMOVZXBDrm, TB_ALIGN_16 },
524 { X86::PMOVZXBQrr, X86::PMOVZXBQrm, TB_ALIGN_16 },
525 { X86::PMOVZXBWrr, X86::PMOVZXBWrm, TB_ALIGN_16 },
526 { X86::PMOVZXDQrr, X86::PMOVZXDQrm, TB_ALIGN_16 },
527 { X86::PMOVZXWDrr, X86::PMOVZXWDrm, TB_ALIGN_16 },
528 { X86::PMOVZXWQrr, X86::PMOVZXWQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]529 { X86::PSHUFDri, X86::PSHUFDmi, TB_ALIGN_16 },
530 { X86::PSHUFHWri, X86::PSHUFHWmi, TB_ALIGN_16 },
531 { X86::PSHUFLWri, X86::PSHUFLWmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]532 { X86::PTESTrr, X86::PTESTrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]533 { X86::RCPPSr, X86::RCPPSm, TB_ALIGN_16 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]534 { X86::RCPSSr, X86::RCPSSm, 0 },
535 { X86::RCPSSr_Int, X86::RCPSSm_Int, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]536 { X86::ROUNDPDr, X86::ROUNDPDm, TB_ALIGN_16 },
537 { X86::ROUNDPSr, X86::ROUNDPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]538 { X86::RSQRTPSr, X86::RSQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]539 { X86::RSQRTSSr, X86::RSQRTSSm, 0 },
540 { X86::RSQRTSSr_Int, X86::RSQRTSSm_Int, 0 },
541 { X86::SQRTPDr, X86::SQRTPDm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]542 { X86::SQRTPSr, X86::SQRTPSm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]543 { X86::SQRTSDr, X86::SQRTSDm, 0 },
544 { X86::SQRTSDr_Int, X86::SQRTSDm_Int, 0 },
545 { X86::SQRTSSr, X86::SQRTSSm, 0 },
546 { X86::SQRTSSr_Int, X86::SQRTSSm_Int, 0 },
547 { X86::TEST16rr, X86::TEST16rm, 0 },
548 { X86::TEST32rr, X86::TEST32rm, 0 },
549 { X86::TEST64rr, X86::TEST64rm, 0 },
550 { X86::TEST8rr, X86::TEST8rm, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]551 // FIXME: TEST*rr EAX,EAX ---> CMP [mem], 0
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]552 { X86::UCOMISDrr, X86::UCOMISDrm, 0 },
553 { X86::UCOMISSrr, X86::UCOMISSrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]554
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]555 // MMX version of foldable instructions
556 { X86::MMX_CVTPD2PIirr, X86::MMX_CVTPD2PIirm, 0 },
557 { X86::MMX_CVTPI2PDirr, X86::MMX_CVTPI2PDirm, 0 },
558 { X86::MMX_CVTPS2PIirr, X86::MMX_CVTPS2PIirm, 0 },
559 { X86::MMX_CVTTPD2PIirr, X86::MMX_CVTTPD2PIirm, 0 },
560 { X86::MMX_CVTTPS2PIirr, X86::MMX_CVTTPS2PIirm, 0 },
561 { X86::MMX_MOVD64to64rr, X86::MMX_MOVQ64rm, 0 },
562 { X86::MMX_PABSBrr64, X86::MMX_PABSBrm64, 0 },
563 { X86::MMX_PABSDrr64, X86::MMX_PABSDrm64, 0 },
564 { X86::MMX_PABSWrr64, X86::MMX_PABSWrm64, 0 },
565 { X86::MMX_PSHUFWri, X86::MMX_PSHUFWmi, 0 },
566
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]567 // 3DNow! version of foldable instructions
568 { X86::PF2IDrr, X86::PF2IDrm, 0 },
569 { X86::PF2IWrr, X86::PF2IWrm, 0 },
570 { X86::PFRCPrr, X86::PFRCPrm, 0 },
571 { X86::PFRSQRTrr, X86::PFRSQRTrm, 0 },
572 { X86::PI2FDrr, X86::PI2FDrm, 0 },
573 { X86::PI2FWrr, X86::PI2FWrm, 0 },
574 { X86::PSWAPDrr, X86::PSWAPDrm, 0 },
575
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]576 // AVX 128-bit versions of foldable instructions
577 { X86::Int_VCOMISDrr, X86::Int_VCOMISDrm, 0 },
578 { X86::Int_VCOMISSrr, X86::Int_VCOMISSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]579 { X86::Int_VUCOMISDrr, X86::Int_VUCOMISDrm, 0 },
580 { X86::Int_VUCOMISSrr, X86::Int_VUCOMISSrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]581 { X86::VCVTTSD2SI64rr, X86::VCVTTSD2SI64rm, 0 },
582 { X86::Int_VCVTTSD2SI64rr,X86::Int_VCVTTSD2SI64rm,0 },
Pete Cooper8bbce762012-06-14 22:12:58 +0000[diff] [blame]583 { X86::VCVTTSD2SIrr, X86::VCVTTSD2SIrm, 0 },
Craig Topper11913052012-06-15 07:02:58 +0000[diff] [blame]584 { X86::Int_VCVTTSD2SIrr,X86::Int_VCVTTSD2SIrm, 0 },
585 { X86::VCVTTSS2SI64rr, X86::VCVTTSS2SI64rm, 0 },
586 { X86::Int_VCVTTSS2SI64rr,X86::Int_VCVTTSS2SI64rm,0 },
587 { X86::VCVTTSS2SIrr, X86::VCVTTSS2SIrm, 0 },
588 { X86::Int_VCVTTSS2SIrr,X86::Int_VCVTTSS2SIrm, 0 },
589 { X86::VCVTSD2SI64rr, X86::VCVTSD2SI64rm, 0 },
590 { X86::VCVTSD2SIrr, X86::VCVTSD2SIrm, 0 },
591 { X86::VCVTSS2SI64rr, X86::VCVTSS2SI64rm, 0 },
592 { X86::VCVTSS2SIrr, X86::VCVTSS2SIrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]593 { X86::VCVTDQ2PDrr, X86::VCVTDQ2PDrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]594 { X86::VCVTDQ2PSrr, X86::VCVTDQ2PSrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]595 { X86::VCVTPD2DQrr, X86::VCVTPD2DQXrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]596 { X86::VCVTPD2PSrr, X86::VCVTPD2PSXrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]597 { X86::VCVTPS2DQrr, X86::VCVTPS2DQrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]598 { X86::VCVTPS2PDrr, X86::VCVTPS2PDrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]599 { X86::VCVTTPD2DQrr, X86::VCVTTPD2DQXrm, 0 },
600 { X86::VCVTTPS2DQrr, X86::VCVTTPS2DQrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]601 { X86::VMOV64toPQIrr, X86::VMOVQI2PQIrm, 0 },
602 { X86::VMOV64toSDrr, X86::VMOV64toSDrm, 0 },
603 { X86::VMOVAPDrr, X86::VMOVAPDrm, TB_ALIGN_16 },
604 { X86::VMOVAPSrr, X86::VMOVAPSrm, TB_ALIGN_16 },
605 { X86::VMOVDDUPrr, X86::VMOVDDUPrm, 0 },
606 { X86::VMOVDI2PDIrr, X86::VMOVDI2PDIrm, 0 },
607 { X86::VMOVDI2SSrr, X86::VMOVDI2SSrm, 0 },
608 { X86::VMOVDQArr, X86::VMOVDQArm, TB_ALIGN_16 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]609 { X86::VMOVSLDUPrr, X86::VMOVSLDUPrm, 0 },
610 { X86::VMOVSHDUPrr, X86::VMOVSHDUPrm, 0 },
Craig Topperb2922162012-12-26 02:14:19 +0000[diff] [blame]611 { X86::VMOVUPDrr, X86::VMOVUPDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]612 { X86::VMOVUPSrr, X86::VMOVUPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]613 { X86::VMOVZPQILo2PQIrr,X86::VMOVZPQILo2PQIrm, TB_ALIGN_16 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]614 { X86::VPABSBrr128, X86::VPABSBrm128, 0 },
615 { X86::VPABSDrr128, X86::VPABSDrm128, 0 },
616 { X86::VPABSWrr128, X86::VPABSWrm128, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]617 { X86::VPCMPESTRIrr, X86::VPCMPESTRIrm, 0 },
618 { X86::VPCMPESTRM128rr, X86::VPCMPESTRM128rm, 0 },
619 { X86::VPCMPISTRIrr, X86::VPCMPISTRIrm, 0 },
620 { X86::VPCMPISTRM128rr, X86::VPCMPISTRM128rm, 0 },
621 { X86::VPHMINPOSUWrr128, X86::VPHMINPOSUWrm128, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]622 { X86::VPERMILPDri, X86::VPERMILPDmi, 0 },
623 { X86::VPERMILPSri, X86::VPERMILPSmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]624 { X86::VPMOVSXBDrr, X86::VPMOVSXBDrm, 0 },
625 { X86::VPMOVSXBQrr, X86::VPMOVSXBQrm, 0 },
626 { X86::VPMOVSXBWrr, X86::VPMOVSXBWrm, 0 },
627 { X86::VPMOVSXDQrr, X86::VPMOVSXDQrm, 0 },
628 { X86::VPMOVSXWDrr, X86::VPMOVSXWDrm, 0 },
629 { X86::VPMOVSXWQrr, X86::VPMOVSXWQrm, 0 },
630 { X86::VPMOVZXBDrr, X86::VPMOVZXBDrm, 0 },
631 { X86::VPMOVZXBQrr, X86::VPMOVZXBQrm, 0 },
632 { X86::VPMOVZXBWrr, X86::VPMOVZXBWrm, 0 },
633 { X86::VPMOVZXDQrr, X86::VPMOVZXDQrm, 0 },
634 { X86::VPMOVZXWDrr, X86::VPMOVZXWDrm, 0 },
635 { X86::VPMOVZXWQrr, X86::VPMOVZXWQrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]636 { X86::VPSHUFDri, X86::VPSHUFDmi, 0 },
637 { X86::VPSHUFHWri, X86::VPSHUFHWmi, 0 },
638 { X86::VPSHUFLWri, X86::VPSHUFLWmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]639 { X86::VPTESTrr, X86::VPTESTrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]640 { X86::VRCPPSr, X86::VRCPPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]641 { X86::VROUNDPDr, X86::VROUNDPDm, 0 },
642 { X86::VROUNDPSr, X86::VROUNDPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]643 { X86::VRSQRTPSr, X86::VRSQRTPSm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]644 { X86::VSQRTPDr, X86::VSQRTPDm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]645 { X86::VSQRTPSr, X86::VSQRTPSm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]646 { X86::VTESTPDrr, X86::VTESTPDrm, 0 },
647 { X86::VTESTPSrr, X86::VTESTPSrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]648 { X86::VUCOMISDrr, X86::VUCOMISDrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]649 { X86::VUCOMISSrr, X86::VUCOMISSrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]650
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]651 // AVX 256-bit foldable instructions
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]652 { X86::VCVTDQ2PDYrr, X86::VCVTDQ2PDYrm, 0 },
Simon Pilgrim1fc483d2014-11-05 22:28:25 +0000[diff] [blame]653 { X86::VCVTDQ2PSYrr, X86::VCVTDQ2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]654 { X86::VCVTPD2DQYrr, X86::VCVTPD2DQYrm, 0 },
Simon Pilgrimbf1e0792014-12-16 22:30:10 +0000[diff] [blame]655 { X86::VCVTPD2PSYrr, X86::VCVTPD2PSYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]656 { X86::VCVTPS2DQYrr, X86::VCVTPS2DQYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]657 { X86::VCVTPS2PDYrr, X86::VCVTPS2PDYrm, 0 },
Simon Pilgrim615ab8e2014-11-06 22:15:41 +0000[diff] [blame]658 { X86::VCVTTPD2DQYrr, X86::VCVTTPD2DQYrm, 0 },
659 { X86::VCVTTPS2DQYrr, X86::VCVTTPS2DQYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]660 { X86::VMOVAPDYrr, X86::VMOVAPDYrm, TB_ALIGN_32 },
661 { X86::VMOVAPSYrr, X86::VMOVAPSYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]662 { X86::VMOVDDUPYrr, X86::VMOVDDUPYrm, 0 },
Craig Toppera875b7c2012-01-19 08:50:38 +0000[diff] [blame]663 { X86::VMOVDQAYrr, X86::VMOVDQAYrm, TB_ALIGN_32 },
Simon Pilgrim7e6d5732015-01-22 22:39:59 +0000[diff] [blame]664 { X86::VMOVSLDUPYrr, X86::VMOVSLDUPYrm, 0 },
665 { X86::VMOVSHDUPYrr, X86::VMOVSHDUPYrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]666 { X86::VMOVUPDYrr, X86::VMOVUPDYrm, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]667 { X86::VMOVUPSYrr, X86::VMOVUPSYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]668 { X86::VPERMILPDYri, X86::VPERMILPDYmi, 0 },
669 { X86::VPERMILPSYri, X86::VPERMILPSYmi, 0 },
Simon Pilgrima2618672015-02-07 21:44:06 +0000[diff] [blame]670 { X86::VPTESTYrr, X86::VPTESTYrm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]671 { X86::VRCPPSYr, X86::VRCPPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]672 { X86::VROUNDYPDr, X86::VROUNDYPDm, 0 },
673 { X86::VROUNDYPSr, X86::VROUNDYPSm, 0 },
Simon Pilgrima6367262014-10-25 08:11:20 +0000[diff] [blame]674 { X86::VRSQRTPSYr, X86::VRSQRTPSYm, 0 },
675 { X86::VSQRTPDYr, X86::VSQRTPDYm, 0 },
676 { X86::VSQRTPSYr, X86::VSQRTPSYm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]677 { X86::VTESTPDYrr, X86::VTESTPDYrm, 0 },
678 { X86::VTESTPSYrr, X86::VTESTPSYrm, 0 },
Nadav Rotemee3552f2012-07-15 12:26:30 +0000[diff] [blame]679
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]680 // AVX2 foldable instructions
Sanjay Patel1a20fdf2015-02-17 22:09:54 +0000[diff] [blame]681
682 // VBROADCASTS{SD}rr register instructions were an AVX2 addition while the
683 // VBROADCASTS{SD}rm memory instructions were available from AVX1.
684 // TB_NO_REVERSE prevents unfolding from introducing an illegal instruction
685 // on AVX1 targets. The VPBROADCAST instructions are all AVX2 instructions
686 // so they don't need an equivalent limitation.
Simon Pilgrimd11b0132015-02-08 17:13:54 +0000[diff] [blame]687 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrm, TB_NO_REVERSE },
688 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrm, TB_NO_REVERSE },
689 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrm, TB_NO_REVERSE },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]690 { X86::VPABSBrr256, X86::VPABSBrm256, 0 },
691 { X86::VPABSDrr256, X86::VPABSDrm256, 0 },
692 { X86::VPABSWrr256, X86::VPABSWrm256, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]693 { X86::VPBROADCASTBrr, X86::VPBROADCASTBrm, 0 },
694 { X86::VPBROADCASTBYrr, X86::VPBROADCASTBYrm, 0 },
695 { X86::VPBROADCASTDrr, X86::VPBROADCASTDrm, 0 },
696 { X86::VPBROADCASTDYrr, X86::VPBROADCASTDYrm, 0 },
697 { X86::VPBROADCASTQrr, X86::VPBROADCASTQrm, 0 },
698 { X86::VPBROADCASTQYrr, X86::VPBROADCASTQYrm, 0 },
699 { X86::VPBROADCASTWrr, X86::VPBROADCASTWrm, 0 },
700 { X86::VPBROADCASTWYrr, X86::VPBROADCASTWYrm, 0 },
701 { X86::VPERMPDYri, X86::VPERMPDYmi, 0 },
702 { X86::VPERMQYri, X86::VPERMQYmi, 0 },
703 { X86::VPMOVSXBDYrr, X86::VPMOVSXBDYrm, 0 },
704 { X86::VPMOVSXBQYrr, X86::VPMOVSXBQYrm, 0 },
705 { X86::VPMOVSXBWYrr, X86::VPMOVSXBWYrm, 0 },
706 { X86::VPMOVSXDQYrr, X86::VPMOVSXDQYrm, 0 },
707 { X86::VPMOVSXWDYrr, X86::VPMOVSXWDYrm, 0 },
708 { X86::VPMOVSXWQYrr, X86::VPMOVSXWQYrm, 0 },
709 { X86::VPMOVZXBDYrr, X86::VPMOVZXBDYrm, 0 },
710 { X86::VPMOVZXBQYrr, X86::VPMOVZXBQYrm, 0 },
711 { X86::VPMOVZXBWYrr, X86::VPMOVZXBWYrm, 0 },
712 { X86::VPMOVZXDQYrr, X86::VPMOVZXDQYrm, 0 },
713 { X86::VPMOVZXWDYrr, X86::VPMOVZXWDYrm, 0 },
714 { X86::VPMOVZXWQYrr, X86::VPMOVZXWQYrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]715 { X86::VPSHUFDYri, X86::VPSHUFDYmi, 0 },
716 { X86::VPSHUFHWYri, X86::VPSHUFHWYmi, 0 },
717 { X86::VPSHUFLWYri, X86::VPSHUFLWYmi, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]718
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]719 // XOP foldable instructions
720 { X86::VFRCZPDrr, X86::VFRCZPDrm, 0 },
721 { X86::VFRCZPDrrY, X86::VFRCZPDrmY, 0 },
722 { X86::VFRCZPSrr, X86::VFRCZPSrm, 0 },
723 { X86::VFRCZPSrrY, X86::VFRCZPSrmY, 0 },
724 { X86::VFRCZSDrr, X86::VFRCZSDrm, 0 },
725 { X86::VFRCZSSrr, X86::VFRCZSSrm, 0 },
726 { X86::VPHADDBDrr, X86::VPHADDBDrm, 0 },
727 { X86::VPHADDBQrr, X86::VPHADDBQrm, 0 },
728 { X86::VPHADDBWrr, X86::VPHADDBWrm, 0 },
729 { X86::VPHADDDQrr, X86::VPHADDDQrm, 0 },
730 { X86::VPHADDWDrr, X86::VPHADDWDrm, 0 },
731 { X86::VPHADDWQrr, X86::VPHADDWQrm, 0 },
732 { X86::VPHADDUBDrr, X86::VPHADDUBDrm, 0 },
733 { X86::VPHADDUBQrr, X86::VPHADDUBQrm, 0 },
734 { X86::VPHADDUBWrr, X86::VPHADDUBWrm, 0 },
735 { X86::VPHADDUDQrr, X86::VPHADDUDQrm, 0 },
736 { X86::VPHADDUWDrr, X86::VPHADDUWDrm, 0 },
737 { X86::VPHADDUWQrr, X86::VPHADDUWQrm, 0 },
738 { X86::VPHSUBBWrr, X86::VPHSUBBWrm, 0 },
739 { X86::VPHSUBDQrr, X86::VPHSUBDQrm, 0 },
740 { X86::VPHSUBWDrr, X86::VPHSUBWDrm, 0 },
741 { X86::VPROTBri, X86::VPROTBmi, 0 },
742 { X86::VPROTBrr, X86::VPROTBmr, 0 },
743 { X86::VPROTDri, X86::VPROTDmi, 0 },
744 { X86::VPROTDrr, X86::VPROTDmr, 0 },
745 { X86::VPROTQri, X86::VPROTQmi, 0 },
746 { X86::VPROTQrr, X86::VPROTQmr, 0 },
747 { X86::VPROTWri, X86::VPROTWmi, 0 },
748 { X86::VPROTWrr, X86::VPROTWmr, 0 },
749 { X86::VPSHABrr, X86::VPSHABmr, 0 },
750 { X86::VPSHADrr, X86::VPSHADmr, 0 },
751 { X86::VPSHAQrr, X86::VPSHAQmr, 0 },
752 { X86::VPSHAWrr, X86::VPSHAWmr, 0 },
753 { X86::VPSHLBrr, X86::VPSHLBmr, 0 },
754 { X86::VPSHLDrr, X86::VPSHLDmr, 0 },
755 { X86::VPSHLQrr, X86::VPSHLQmr, 0 },
756 { X86::VPSHLWrr, X86::VPSHLWmr, 0 },
757
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]758 // BMI/BMI2/LZCNT/POPCNT/TBM foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]759 { X86::BEXTR32rr, X86::BEXTR32rm, 0 },
760 { X86::BEXTR64rr, X86::BEXTR64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]761 { X86::BEXTRI32ri, X86::BEXTRI32mi, 0 },
762 { X86::BEXTRI64ri, X86::BEXTRI64mi, 0 },
763 { X86::BLCFILL32rr, X86::BLCFILL32rm, 0 },
764 { X86::BLCFILL64rr, X86::BLCFILL64rm, 0 },
765 { X86::BLCI32rr, X86::BLCI32rm, 0 },
766 { X86::BLCI64rr, X86::BLCI64rm, 0 },
767 { X86::BLCIC32rr, X86::BLCIC32rm, 0 },
768 { X86::BLCIC64rr, X86::BLCIC64rm, 0 },
769 { X86::BLCMSK32rr, X86::BLCMSK32rm, 0 },
770 { X86::BLCMSK64rr, X86::BLCMSK64rm, 0 },
771 { X86::BLCS32rr, X86::BLCS32rm, 0 },
772 { X86::BLCS64rr, X86::BLCS64rm, 0 },
773 { X86::BLSFILL32rr, X86::BLSFILL32rm, 0 },
774 { X86::BLSFILL64rr, X86::BLSFILL64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]775 { X86::BLSI32rr, X86::BLSI32rm, 0 },
776 { X86::BLSI64rr, X86::BLSI64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]777 { X86::BLSIC32rr, X86::BLSIC32rm, 0 },
778 { X86::BLSIC64rr, X86::BLSIC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]779 { X86::BLSMSK32rr, X86::BLSMSK32rm, 0 },
780 { X86::BLSMSK64rr, X86::BLSMSK64rm, 0 },
781 { X86::BLSR32rr, X86::BLSR32rm, 0 },
782 { X86::BLSR64rr, X86::BLSR64rm, 0 },
783 { X86::BZHI32rr, X86::BZHI32rm, 0 },
784 { X86::BZHI64rr, X86::BZHI64rm, 0 },
785 { X86::LZCNT16rr, X86::LZCNT16rm, 0 },
786 { X86::LZCNT32rr, X86::LZCNT32rm, 0 },
787 { X86::LZCNT64rr, X86::LZCNT64rm, 0 },
788 { X86::POPCNT16rr, X86::POPCNT16rm, 0 },
789 { X86::POPCNT32rr, X86::POPCNT32rm, 0 },
790 { X86::POPCNT64rr, X86::POPCNT64rm, 0 },
Michael Liao2de86af2012-09-26 08:24:51 +0000[diff] [blame]791 { X86::RORX32ri, X86::RORX32mi, 0 },
792 { X86::RORX64ri, X86::RORX64mi, 0 },
Michael Liao2b425e12012-09-26 08:26:25 +0000[diff] [blame]793 { X86::SARX32rr, X86::SARX32rm, 0 },
794 { X86::SARX64rr, X86::SARX64rm, 0 },
795 { X86::SHRX32rr, X86::SHRX32rm, 0 },
796 { X86::SHRX64rr, X86::SHRX64rm, 0 },
797 { X86::SHLX32rr, X86::SHLX32rm, 0 },
798 { X86::SHLX64rr, X86::SHLX64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]799 { X86::T1MSKC32rr, X86::T1MSKC32rm, 0 },
800 { X86::T1MSKC64rr, X86::T1MSKC64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]801 { X86::TZCNT16rr, X86::TZCNT16rm, 0 },
802 { X86::TZCNT32rr, X86::TZCNT32rm, 0 },
803 { X86::TZCNT64rr, X86::TZCNT64rm, 0 },
Craig Topperc81e2942013-10-05 20:20:51 +0000[diff] [blame]804 { X86::TZMSK32rr, X86::TZMSK32rm, 0 },
805 { X86::TZMSK64rr, X86::TZMSK64rm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]806
807 // AVX-512 foldable instructions
808 { X86::VMOV64toPQIZrr, X86::VMOVQI2PQIZrm, 0 },
809 { X86::VMOVDI2SSZrr, X86::VMOVDI2SSZrm, 0 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]810 { X86::VMOVAPDZrr, X86::VMOVAPDZrm, TB_ALIGN_64 },
811 { X86::VMOVAPSZrr, X86::VMOVAPSZrm, TB_ALIGN_64 },
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]812 { X86::VMOVDQA32Zrr, X86::VMOVDQA32Zrm, TB_ALIGN_64 },
813 { X86::VMOVDQA64Zrr, X86::VMOVDQA64Zrm, TB_ALIGN_64 },
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]814 { X86::VMOVDQU8Zrr, X86::VMOVDQU8Zrm, 0 },
815 { X86::VMOVDQU16Zrr, X86::VMOVDQU16Zrm, 0 },
Robert Khasanov7ca7df02014-08-04 14:35:15 +0000[diff] [blame]816 { X86::VMOVDQU32Zrr, X86::VMOVDQU32Zrm, 0 },
817 { X86::VMOVDQU64Zrr, X86::VMOVDQU64Zrm, 0 },
Robert Khasanov3c30c4b2014-08-06 15:40:34 +0000[diff] [blame]818 { X86::VMOVUPDZrr, X86::VMOVUPDZrm, 0 },
819 { X86::VMOVUPSZrr, X86::VMOVUPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]820 { X86::VPABSDZrr, X86::VPABSDZrm, 0 },
821 { X86::VPABSQZrr, X86::VPABSQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]822 { X86::VBROADCASTSSZr, X86::VBROADCASTSSZm, TB_NO_REVERSE },
823 { X86::VBROADCASTSDZr, X86::VBROADCASTSDZm, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]824
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]825 // AVX-512 foldable instructions (256-bit versions)
826 { X86::VMOVAPDZ256rr, X86::VMOVAPDZ256rm, TB_ALIGN_32 },
827 { X86::VMOVAPSZ256rr, X86::VMOVAPSZ256rm, TB_ALIGN_32 },
828 { X86::VMOVDQA32Z256rr, X86::VMOVDQA32Z256rm, TB_ALIGN_32 },
829 { X86::VMOVDQA64Z256rr, X86::VMOVDQA64Z256rm, TB_ALIGN_32 },
830 { X86::VMOVDQU8Z256rr, X86::VMOVDQU8Z256rm, 0 },
831 { X86::VMOVDQU16Z256rr, X86::VMOVDQU16Z256rm, 0 },
832 { X86::VMOVDQU32Z256rr, X86::VMOVDQU32Z256rm, 0 },
833 { X86::VMOVDQU64Z256rr, X86::VMOVDQU64Z256rm, 0 },
834 { X86::VMOVUPDZ256rr, X86::VMOVUPDZ256rm, 0 },
835 { X86::VMOVUPSZ256rr, X86::VMOVUPSZ256rm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]836 { X86::VBROADCASTSSZ256r, X86::VBROADCASTSSZ256m, TB_NO_REVERSE },
837 { X86::VBROADCASTSDZ256r, X86::VBROADCASTSDZ256m, TB_NO_REVERSE },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]838
Robert Khasanov6d62c022014-09-26 09:48:50 +0000[diff] [blame]839 // AVX-512 foldable instructions (256-bit versions)
840 { X86::VMOVAPDZ128rr, X86::VMOVAPDZ128rm, TB_ALIGN_16 },
841 { X86::VMOVAPSZ128rr, X86::VMOVAPSZ128rm, TB_ALIGN_16 },
842 { X86::VMOVDQA32Z128rr, X86::VMOVDQA32Z128rm, TB_ALIGN_16 },
843 { X86::VMOVDQA64Z128rr, X86::VMOVDQA64Z128rm, TB_ALIGN_16 },
844 { X86::VMOVDQU8Z128rr, X86::VMOVDQU8Z128rm, 0 },
845 { X86::VMOVDQU16Z128rr, X86::VMOVDQU16Z128rm, 0 },
846 { X86::VMOVDQU32Z128rr, X86::VMOVDQU32Z128rm, 0 },
847 { X86::VMOVDQU64Z128rr, X86::VMOVDQU64Z128rm, 0 },
848 { X86::VMOVUPDZ128rr, X86::VMOVUPDZ128rm, 0 },
849 { X86::VMOVUPSZ128rr, X86::VMOVUPSZ128rm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]850 { X86::VBROADCASTSSZ128r, X86::VBROADCASTSSZ128m, TB_NO_REVERSE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]851
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]852 // F16C foldable instructions
853 { X86::VCVTPH2PSrr, X86::VCVTPH2PSrm, 0 },
854 { X86::VCVTPH2PSYrr, X86::VCVTPH2PSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]855
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]856 // AES foldable instructions
857 { X86::AESIMCrr, X86::AESIMCrm, TB_ALIGN_16 },
858 { X86::AESKEYGENASSIST128rr, X86::AESKEYGENASSIST128rm, TB_ALIGN_16 },
Simon Pilgrim295eaad2015-02-12 20:01:03 +0000[diff] [blame]859 { X86::VAESIMCrr, X86::VAESIMCrm, 0 },
860 { X86::VAESKEYGENASSIST128rr, X86::VAESKEYGENASSIST128rm, 0 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]861 };
862
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]863 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable1) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]864 AddTableEntry(RegOp2MemOpTable1, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]865 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]866 // Index 1, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]867 Entry.Flags | TB_INDEX_1 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]868 }
869
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]870 static const X86MemoryFoldTableEntry MemoryFoldTable2[] = {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]871 { X86::ADC32rr, X86::ADC32rm, 0 },
872 { X86::ADC64rr, X86::ADC64rm, 0 },
873 { X86::ADD16rr, X86::ADD16rm, 0 },
874 { X86::ADD16rr_DB, X86::ADD16rm, TB_NO_REVERSE },
875 { X86::ADD32rr, X86::ADD32rm, 0 },
876 { X86::ADD32rr_DB, X86::ADD32rm, TB_NO_REVERSE },
877 { X86::ADD64rr, X86::ADD64rm, 0 },
878 { X86::ADD64rr_DB, X86::ADD64rm, TB_NO_REVERSE },
879 { X86::ADD8rr, X86::ADD8rm, 0 },
880 { X86::ADDPDrr, X86::ADDPDrm, TB_ALIGN_16 },
881 { X86::ADDPSrr, X86::ADDPSrm, TB_ALIGN_16 },
882 { X86::ADDSDrr, X86::ADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]883 { X86::ADDSDrr_Int, X86::ADDSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]884 { X86::ADDSSrr, X86::ADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]885 { X86::ADDSSrr_Int, X86::ADDSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]886 { X86::ADDSUBPDrr, X86::ADDSUBPDrm, TB_ALIGN_16 },
887 { X86::ADDSUBPSrr, X86::ADDSUBPSrm, TB_ALIGN_16 },
888 { X86::AND16rr, X86::AND16rm, 0 },
889 { X86::AND32rr, X86::AND32rm, 0 },
890 { X86::AND64rr, X86::AND64rm, 0 },
891 { X86::AND8rr, X86::AND8rm, 0 },
892 { X86::ANDNPDrr, X86::ANDNPDrm, TB_ALIGN_16 },
893 { X86::ANDNPSrr, X86::ANDNPSrm, TB_ALIGN_16 },
894 { X86::ANDPDrr, X86::ANDPDrm, TB_ALIGN_16 },
895 { X86::ANDPSrr, X86::ANDPSrm, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]896 { X86::BLENDPDrri, X86::BLENDPDrmi, TB_ALIGN_16 },
897 { X86::BLENDPSrri, X86::BLENDPSrmi, TB_ALIGN_16 },
898 { X86::BLENDVPDrr0, X86::BLENDVPDrm0, TB_ALIGN_16 },
899 { X86::BLENDVPSrr0, X86::BLENDVPSrm0, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]900 { X86::CMOVA16rr, X86::CMOVA16rm, 0 },
901 { X86::CMOVA32rr, X86::CMOVA32rm, 0 },
902 { X86::CMOVA64rr, X86::CMOVA64rm, 0 },
903 { X86::CMOVAE16rr, X86::CMOVAE16rm, 0 },
904 { X86::CMOVAE32rr, X86::CMOVAE32rm, 0 },
905 { X86::CMOVAE64rr, X86::CMOVAE64rm, 0 },
906 { X86::CMOVB16rr, X86::CMOVB16rm, 0 },
907 { X86::CMOVB32rr, X86::CMOVB32rm, 0 },
908 { X86::CMOVB64rr, X86::CMOVB64rm, 0 },
909 { X86::CMOVBE16rr, X86::CMOVBE16rm, 0 },
910 { X86::CMOVBE32rr, X86::CMOVBE32rm, 0 },
911 { X86::CMOVBE64rr, X86::CMOVBE64rm, 0 },
912 { X86::CMOVE16rr, X86::CMOVE16rm, 0 },
913 { X86::CMOVE32rr, X86::CMOVE32rm, 0 },
914 { X86::CMOVE64rr, X86::CMOVE64rm, 0 },
915 { X86::CMOVG16rr, X86::CMOVG16rm, 0 },
916 { X86::CMOVG32rr, X86::CMOVG32rm, 0 },
917 { X86::CMOVG64rr, X86::CMOVG64rm, 0 },
918 { X86::CMOVGE16rr, X86::CMOVGE16rm, 0 },
919 { X86::CMOVGE32rr, X86::CMOVGE32rm, 0 },
920 { X86::CMOVGE64rr, X86::CMOVGE64rm, 0 },
921 { X86::CMOVL16rr, X86::CMOVL16rm, 0 },
922 { X86::CMOVL32rr, X86::CMOVL32rm, 0 },
923 { X86::CMOVL64rr, X86::CMOVL64rm, 0 },
924 { X86::CMOVLE16rr, X86::CMOVLE16rm, 0 },
925 { X86::CMOVLE32rr, X86::CMOVLE32rm, 0 },
926 { X86::CMOVLE64rr, X86::CMOVLE64rm, 0 },
927 { X86::CMOVNE16rr, X86::CMOVNE16rm, 0 },
928 { X86::CMOVNE32rr, X86::CMOVNE32rm, 0 },
929 { X86::CMOVNE64rr, X86::CMOVNE64rm, 0 },
930 { X86::CMOVNO16rr, X86::CMOVNO16rm, 0 },
931 { X86::CMOVNO32rr, X86::CMOVNO32rm, 0 },
932 { X86::CMOVNO64rr, X86::CMOVNO64rm, 0 },
933 { X86::CMOVNP16rr, X86::CMOVNP16rm, 0 },
934 { X86::CMOVNP32rr, X86::CMOVNP32rm, 0 },
935 { X86::CMOVNP64rr, X86::CMOVNP64rm, 0 },
936 { X86::CMOVNS16rr, X86::CMOVNS16rm, 0 },
937 { X86::CMOVNS32rr, X86::CMOVNS32rm, 0 },
938 { X86::CMOVNS64rr, X86::CMOVNS64rm, 0 },
939 { X86::CMOVO16rr, X86::CMOVO16rm, 0 },
940 { X86::CMOVO32rr, X86::CMOVO32rm, 0 },
941 { X86::CMOVO64rr, X86::CMOVO64rm, 0 },
942 { X86::CMOVP16rr, X86::CMOVP16rm, 0 },
943 { X86::CMOVP32rr, X86::CMOVP32rm, 0 },
944 { X86::CMOVP64rr, X86::CMOVP64rm, 0 },
945 { X86::CMOVS16rr, X86::CMOVS16rm, 0 },
946 { X86::CMOVS32rr, X86::CMOVS32rm, 0 },
947 { X86::CMOVS64rr, X86::CMOVS64rm, 0 },
948 { X86::CMPPDrri, X86::CMPPDrmi, TB_ALIGN_16 },
949 { X86::CMPPSrri, X86::CMPPSrmi, TB_ALIGN_16 },
950 { X86::CMPSDrr, X86::CMPSDrm, 0 },
951 { X86::CMPSSrr, X86::CMPSSrm, 0 },
Simon Pilgrim01846222015-04-03 14:24:40 +0000[diff] [blame]952 { X86::CRC32r32r32, X86::CRC32r32m32, 0 },
953 { X86::CRC32r64r64, X86::CRC32r64m64, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]954 { X86::DIVPDrr, X86::DIVPDrm, TB_ALIGN_16 },
955 { X86::DIVPSrr, X86::DIVPSrm, TB_ALIGN_16 },
956 { X86::DIVSDrr, X86::DIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]957 { X86::DIVSDrr_Int, X86::DIVSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]958 { X86::DIVSSrr, X86::DIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]959 { X86::DIVSSrr_Int, X86::DIVSSrm_Int, 0 },
960 { X86::DPPDrri, X86::DPPDrmi, TB_ALIGN_16 },
961 { X86::DPPSrri, X86::DPPSrmi, TB_ALIGN_16 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]962
Sanjay Patel8c13e362015-07-28 00:48:32 +0000[diff] [blame]963 // Do not fold Fs* scalar logical op loads because there are no scalar
964 // load variants for these instructions. When folded, the load is required
965 // to be 128-bits, so the load size would not match.
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]966
967 { X86::FvANDNPDrr, X86::FvANDNPDrm, TB_ALIGN_16 },
968 { X86::FvANDNPSrr, X86::FvANDNPSrm, TB_ALIGN_16 },
969 { X86::FvANDPDrr, X86::FvANDPDrm, TB_ALIGN_16 },
970 { X86::FvANDPSrr, X86::FvANDPSrm, TB_ALIGN_16 },
971 { X86::FvORPDrr, X86::FvORPDrm, TB_ALIGN_16 },
972 { X86::FvORPSrr, X86::FvORPSrm, TB_ALIGN_16 },
973 { X86::FvXORPDrr, X86::FvXORPDrm, TB_ALIGN_16 },
974 { X86::FvXORPSrr, X86::FvXORPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]975 { X86::HADDPDrr, X86::HADDPDrm, TB_ALIGN_16 },
976 { X86::HADDPSrr, X86::HADDPSrm, TB_ALIGN_16 },
977 { X86::HSUBPDrr, X86::HSUBPDrm, TB_ALIGN_16 },
978 { X86::HSUBPSrr, X86::HSUBPSrm, TB_ALIGN_16 },
979 { X86::IMUL16rr, X86::IMUL16rm, 0 },
980 { X86::IMUL32rr, X86::IMUL32rm, 0 },
981 { X86::IMUL64rr, X86::IMUL64rm, 0 },
982 { X86::Int_CMPSDrr, X86::Int_CMPSDrm, 0 },
983 { X86::Int_CMPSSrr, X86::Int_CMPSSrm, 0 },
Manman Ren959acb12012-08-13 18:29:41 +0000[diff] [blame]984 { X86::Int_CVTSD2SSrr, X86::Int_CVTSD2SSrm, 0 },
985 { X86::Int_CVTSI2SD64rr,X86::Int_CVTSI2SD64rm, 0 },
986 { X86::Int_CVTSI2SDrr, X86::Int_CVTSI2SDrm, 0 },
987 { X86::Int_CVTSI2SS64rr,X86::Int_CVTSI2SS64rm, 0 },
988 { X86::Int_CVTSI2SSrr, X86::Int_CVTSI2SSrm, 0 },
989 { X86::Int_CVTSS2SDrr, X86::Int_CVTSS2SDrm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]990 { X86::MAXPDrr, X86::MAXPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]991 { X86::MAXPSrr, X86::MAXPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]992 { X86::MAXSDrr, X86::MAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]993 { X86::MAXSDrr_Int, X86::MAXSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]994 { X86::MAXSSrr, X86::MAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]995 { X86::MAXSSrr_Int, X86::MAXSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]996 { X86::MINPDrr, X86::MINPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]997 { X86::MINPSrr, X86::MINPSrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]998 { X86::MINSDrr, X86::MINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]999 { X86::MINSDrr_Int, X86::MINSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1000 { X86::MINSSrr, X86::MINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1001 { X86::MINSSrr_Int, X86::MINSSrm_Int, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1002 { X86::MPSADBWrri, X86::MPSADBWrmi, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1003 { X86::MULPDrr, X86::MULPDrm, TB_ALIGN_16 },
1004 { X86::MULPSrr, X86::MULPSrm, TB_ALIGN_16 },
1005 { X86::MULSDrr, X86::MULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1006 { X86::MULSDrr_Int, X86::MULSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1007 { X86::MULSSrr, X86::MULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1008 { X86::MULSSrr_Int, X86::MULSSrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1009 { X86::OR16rr, X86::OR16rm, 0 },
1010 { X86::OR32rr, X86::OR32rm, 0 },
1011 { X86::OR64rr, X86::OR64rm, 0 },
1012 { X86::OR8rr, X86::OR8rm, 0 },
1013 { X86::ORPDrr, X86::ORPDrm, TB_ALIGN_16 },
1014 { X86::ORPSrr, X86::ORPSrm, TB_ALIGN_16 },
1015 { X86::PACKSSDWrr, X86::PACKSSDWrm, TB_ALIGN_16 },
1016 { X86::PACKSSWBrr, X86::PACKSSWBrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1017 { X86::PACKUSDWrr, X86::PACKUSDWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1018 { X86::PACKUSWBrr, X86::PACKUSWBrm, TB_ALIGN_16 },
1019 { X86::PADDBrr, X86::PADDBrm, TB_ALIGN_16 },
1020 { X86::PADDDrr, X86::PADDDrm, TB_ALIGN_16 },
1021 { X86::PADDQrr, X86::PADDQrm, TB_ALIGN_16 },
1022 { X86::PADDSBrr, X86::PADDSBrm, TB_ALIGN_16 },
1023 { X86::PADDSWrr, X86::PADDSWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1024 { X86::PADDUSBrr, X86::PADDUSBrm, TB_ALIGN_16 },
1025 { X86::PADDUSWrr, X86::PADDUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1026 { X86::PADDWrr, X86::PADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1027 { X86::PALIGNR128rr, X86::PALIGNR128rm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1028 { X86::PANDNrr, X86::PANDNrm, TB_ALIGN_16 },
1029 { X86::PANDrr, X86::PANDrm, TB_ALIGN_16 },
1030 { X86::PAVGBrr, X86::PAVGBrm, TB_ALIGN_16 },
1031 { X86::PAVGWrr, X86::PAVGWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1032 { X86::PBLENDVBrr0, X86::PBLENDVBrm0, TB_ALIGN_16 },
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1033 { X86::PBLENDWrri, X86::PBLENDWrmi, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1034 { X86::PCLMULQDQrr, X86::PCLMULQDQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1035 { X86::PCMPEQBrr, X86::PCMPEQBrm, TB_ALIGN_16 },
1036 { X86::PCMPEQDrr, X86::PCMPEQDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1037 { X86::PCMPEQQrr, X86::PCMPEQQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1038 { X86::PCMPEQWrr, X86::PCMPEQWrm, TB_ALIGN_16 },
1039 { X86::PCMPGTBrr, X86::PCMPGTBrm, TB_ALIGN_16 },
1040 { X86::PCMPGTDrr, X86::PCMPGTDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1041 { X86::PCMPGTQrr, X86::PCMPGTQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1042 { X86::PCMPGTWrr, X86::PCMPGTWrm, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1043 { X86::PHADDDrr, X86::PHADDDrm, TB_ALIGN_16 },
1044 { X86::PHADDWrr, X86::PHADDWrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1045 { X86::PHADDSWrr128, X86::PHADDSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1046 { X86::PHSUBDrr, X86::PHSUBDrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1047 { X86::PHSUBSWrr128, X86::PHSUBSWrm128, TB_ALIGN_16 },
Craig Topperce4f9c52012-01-25 05:37:32 +0000[diff] [blame]1048 { X86::PHSUBWrr, X86::PHSUBWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1049 { X86::PINSRBrr, X86::PINSRBrm, 0 },
1050 { X86::PINSRDrr, X86::PINSRDrm, 0 },
1051 { X86::PINSRQrr, X86::PINSRQrm, 0 },
1052 { X86::PINSRWrri, X86::PINSRWrmi, 0 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1053 { X86::PMADDUBSWrr128, X86::PMADDUBSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1054 { X86::PMADDWDrr, X86::PMADDWDrm, TB_ALIGN_16 },
1055 { X86::PMAXSWrr, X86::PMAXSWrm, TB_ALIGN_16 },
1056 { X86::PMAXUBrr, X86::PMAXUBrm, TB_ALIGN_16 },
1057 { X86::PMINSWrr, X86::PMINSWrm, TB_ALIGN_16 },
1058 { X86::PMINUBrr, X86::PMINUBrm, TB_ALIGN_16 },
Benjamin Kramer4669d182012-12-21 14:04:55 +0000[diff] [blame]1059 { X86::PMINSBrr, X86::PMINSBrm, TB_ALIGN_16 },
1060 { X86::PMINSDrr, X86::PMINSDrm, TB_ALIGN_16 },
1061 { X86::PMINUDrr, X86::PMINUDrm, TB_ALIGN_16 },
1062 { X86::PMINUWrr, X86::PMINUWrm, TB_ALIGN_16 },
1063 { X86::PMAXSBrr, X86::PMAXSBrm, TB_ALIGN_16 },
1064 { X86::PMAXSDrr, X86::PMAXSDrm, TB_ALIGN_16 },
1065 { X86::PMAXUDrr, X86::PMAXUDrm, TB_ALIGN_16 },
1066 { X86::PMAXUWrr, X86::PMAXUWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1067 { X86::PMULDQrr, X86::PMULDQrm, TB_ALIGN_16 },
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1068 { X86::PMULHRSWrr128, X86::PMULHRSWrm128, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1069 { X86::PMULHUWrr, X86::PMULHUWrm, TB_ALIGN_16 },
1070 { X86::PMULHWrr, X86::PMULHWrm, TB_ALIGN_16 },
1071 { X86::PMULLDrr, X86::PMULLDrm, TB_ALIGN_16 },
1072 { X86::PMULLWrr, X86::PMULLWrm, TB_ALIGN_16 },
1073 { X86::PMULUDQrr, X86::PMULUDQrm, TB_ALIGN_16 },
1074 { X86::PORrr, X86::PORrm, TB_ALIGN_16 },
1075 { X86::PSADBWrr, X86::PSADBWrm, TB_ALIGN_16 },
Craig Topper78349002012-01-25 06:43:11 +0000[diff] [blame]1076 { X86::PSHUFBrr, X86::PSHUFBrm, TB_ALIGN_16 },
1077 { X86::PSIGNBrr, X86::PSIGNBrm, TB_ALIGN_16 },
1078 { X86::PSIGNWrr, X86::PSIGNWrm, TB_ALIGN_16 },
1079 { X86::PSIGNDrr, X86::PSIGNDrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1080 { X86::PSLLDrr, X86::PSLLDrm, TB_ALIGN_16 },
1081 { X86::PSLLQrr, X86::PSLLQrm, TB_ALIGN_16 },
1082 { X86::PSLLWrr, X86::PSLLWrm, TB_ALIGN_16 },
1083 { X86::PSRADrr, X86::PSRADrm, TB_ALIGN_16 },
1084 { X86::PSRAWrr, X86::PSRAWrm, TB_ALIGN_16 },
1085 { X86::PSRLDrr, X86::PSRLDrm, TB_ALIGN_16 },
1086 { X86::PSRLQrr, X86::PSRLQrm, TB_ALIGN_16 },
1087 { X86::PSRLWrr, X86::PSRLWrm, TB_ALIGN_16 },
1088 { X86::PSUBBrr, X86::PSUBBrm, TB_ALIGN_16 },
1089 { X86::PSUBDrr, X86::PSUBDrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1090 { X86::PSUBQrr, X86::PSUBQrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1091 { X86::PSUBSBrr, X86::PSUBSBrm, TB_ALIGN_16 },
1092 { X86::PSUBSWrr, X86::PSUBSWrm, TB_ALIGN_16 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1093 { X86::PSUBUSBrr, X86::PSUBUSBrm, TB_ALIGN_16 },
1094 { X86::PSUBUSWrr, X86::PSUBUSWrm, TB_ALIGN_16 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1095 { X86::PSUBWrr, X86::PSUBWrm, TB_ALIGN_16 },
1096 { X86::PUNPCKHBWrr, X86::PUNPCKHBWrm, TB_ALIGN_16 },
1097 { X86::PUNPCKHDQrr, X86::PUNPCKHDQrm, TB_ALIGN_16 },
1098 { X86::PUNPCKHQDQrr, X86::PUNPCKHQDQrm, TB_ALIGN_16 },
1099 { X86::PUNPCKHWDrr, X86::PUNPCKHWDrm, TB_ALIGN_16 },
1100 { X86::PUNPCKLBWrr, X86::PUNPCKLBWrm, TB_ALIGN_16 },
1101 { X86::PUNPCKLDQrr, X86::PUNPCKLDQrm, TB_ALIGN_16 },
1102 { X86::PUNPCKLQDQrr, X86::PUNPCKLQDQrm, TB_ALIGN_16 },
1103 { X86::PUNPCKLWDrr, X86::PUNPCKLWDrm, TB_ALIGN_16 },
1104 { X86::PXORrr, X86::PXORrm, TB_ALIGN_16 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1105 { X86::ROUNDSDr, X86::ROUNDSDm, 0 },
1106 { X86::ROUNDSSr, X86::ROUNDSSm, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1107 { X86::SBB32rr, X86::SBB32rm, 0 },
1108 { X86::SBB64rr, X86::SBB64rm, 0 },
1109 { X86::SHUFPDrri, X86::SHUFPDrmi, TB_ALIGN_16 },
1110 { X86::SHUFPSrri, X86::SHUFPSrmi, TB_ALIGN_16 },
1111 { X86::SUB16rr, X86::SUB16rm, 0 },
1112 { X86::SUB32rr, X86::SUB32rm, 0 },
1113 { X86::SUB64rr, X86::SUB64rm, 0 },
1114 { X86::SUB8rr, X86::SUB8rm, 0 },
1115 { X86::SUBPDrr, X86::SUBPDrm, TB_ALIGN_16 },
1116 { X86::SUBPSrr, X86::SUBPSrm, TB_ALIGN_16 },
1117 { X86::SUBSDrr, X86::SUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1118 { X86::SUBSDrr_Int, X86::SUBSDrm_Int, 0 },
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1119 { X86::SUBSSrr, X86::SUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1120 { X86::SUBSSrr_Int, X86::SUBSSrm_Int, 0 },
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1121 // FIXME: TEST*rr -> swapped operand of TEST*mr.
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1122 { X86::UNPCKHPDrr, X86::UNPCKHPDrm, TB_ALIGN_16 },
1123 { X86::UNPCKHPSrr, X86::UNPCKHPSrm, TB_ALIGN_16 },
1124 { X86::UNPCKLPDrr, X86::UNPCKLPDrm, TB_ALIGN_16 },
1125 { X86::UNPCKLPSrr, X86::UNPCKLPSrm, TB_ALIGN_16 },
1126 { X86::XOR16rr, X86::XOR16rm, 0 },
1127 { X86::XOR32rr, X86::XOR32rm, 0 },
1128 { X86::XOR64rr, X86::XOR64rm, 0 },
1129 { X86::XOR8rr, X86::XOR8rm, 0 },
1130 { X86::XORPDrr, X86::XORPDrm, TB_ALIGN_16 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1131 { X86::XORPSrr, X86::XORPSrm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1132
Bruno Cardoso Lopesab7afa92015-02-25 15:14:02 +0000[diff] [blame]1133 // MMX version of foldable instructions
1134 { X86::MMX_CVTPI2PSirr, X86::MMX_CVTPI2PSirm, 0 },
1135 { X86::MMX_PACKSSDWirr, X86::MMX_PACKSSDWirm, 0 },
1136 { X86::MMX_PACKSSWBirr, X86::MMX_PACKSSWBirm, 0 },
1137 { X86::MMX_PACKUSWBirr, X86::MMX_PACKUSWBirm, 0 },
1138 { X86::MMX_PADDBirr, X86::MMX_PADDBirm, 0 },
1139 { X86::MMX_PADDDirr, X86::MMX_PADDDirm, 0 },
1140 { X86::MMX_PADDQirr, X86::MMX_PADDQirm, 0 },
1141 { X86::MMX_PADDSBirr, X86::MMX_PADDSBirm, 0 },
1142 { X86::MMX_PADDSWirr, X86::MMX_PADDSWirm, 0 },
1143 { X86::MMX_PADDUSBirr, X86::MMX_PADDUSBirm, 0 },
1144 { X86::MMX_PADDUSWirr, X86::MMX_PADDUSWirm, 0 },
1145 { X86::MMX_PADDWirr, X86::MMX_PADDWirm, 0 },
1146 { X86::MMX_PALIGNR64irr, X86::MMX_PALIGNR64irm, 0 },
1147 { X86::MMX_PANDNirr, X86::MMX_PANDNirm, 0 },
1148 { X86::MMX_PANDirr, X86::MMX_PANDirm, 0 },
1149 { X86::MMX_PAVGBirr, X86::MMX_PAVGBirm, 0 },
1150 { X86::MMX_PAVGWirr, X86::MMX_PAVGWirm, 0 },
1151 { X86::MMX_PCMPEQBirr, X86::MMX_PCMPEQBirm, 0 },
1152 { X86::MMX_PCMPEQDirr, X86::MMX_PCMPEQDirm, 0 },
1153 { X86::MMX_PCMPEQWirr, X86::MMX_PCMPEQWirm, 0 },
1154 { X86::MMX_PCMPGTBirr, X86::MMX_PCMPGTBirm, 0 },
1155 { X86::MMX_PCMPGTDirr, X86::MMX_PCMPGTDirm, 0 },
1156 { X86::MMX_PCMPGTWirr, X86::MMX_PCMPGTWirm, 0 },
1157 { X86::MMX_PHADDSWrr64, X86::MMX_PHADDSWrm64, 0 },
1158 { X86::MMX_PHADDWrr64, X86::MMX_PHADDWrm64, 0 },
1159 { X86::MMX_PHADDrr64, X86::MMX_PHADDrm64, 0 },
1160 { X86::MMX_PHSUBDrr64, X86::MMX_PHSUBDrm64, 0 },
1161 { X86::MMX_PHSUBSWrr64, X86::MMX_PHSUBSWrm64, 0 },
1162 { X86::MMX_PHSUBWrr64, X86::MMX_PHSUBWrm64, 0 },
1163 { X86::MMX_PINSRWirri, X86::MMX_PINSRWirmi, 0 },
1164 { X86::MMX_PMADDUBSWrr64, X86::MMX_PMADDUBSWrm64, 0 },
1165 { X86::MMX_PMADDWDirr, X86::MMX_PMADDWDirm, 0 },
1166 { X86::MMX_PMAXSWirr, X86::MMX_PMAXSWirm, 0 },
1167 { X86::MMX_PMAXUBirr, X86::MMX_PMAXUBirm, 0 },
1168 { X86::MMX_PMINSWirr, X86::MMX_PMINSWirm, 0 },
1169 { X86::MMX_PMINUBirr, X86::MMX_PMINUBirm, 0 },
1170 { X86::MMX_PMULHRSWrr64, X86::MMX_PMULHRSWrm64, 0 },
1171 { X86::MMX_PMULHUWirr, X86::MMX_PMULHUWirm, 0 },
1172 { X86::MMX_PMULHWirr, X86::MMX_PMULHWirm, 0 },
1173 { X86::MMX_PMULLWirr, X86::MMX_PMULLWirm, 0 },
1174 { X86::MMX_PMULUDQirr, X86::MMX_PMULUDQirm, 0 },
1175 { X86::MMX_PORirr, X86::MMX_PORirm, 0 },
1176 { X86::MMX_PSADBWirr, X86::MMX_PSADBWirm, 0 },
1177 { X86::MMX_PSHUFBrr64, X86::MMX_PSHUFBrm64, 0 },
1178 { X86::MMX_PSIGNBrr64, X86::MMX_PSIGNBrm64, 0 },
1179 { X86::MMX_PSIGNDrr64, X86::MMX_PSIGNDrm64, 0 },
1180 { X86::MMX_PSIGNWrr64, X86::MMX_PSIGNWrm64, 0 },
1181 { X86::MMX_PSLLDrr, X86::MMX_PSLLDrm, 0 },
1182 { X86::MMX_PSLLQrr, X86::MMX_PSLLQrm, 0 },
1183 { X86::MMX_PSLLWrr, X86::MMX_PSLLWrm, 0 },
1184 { X86::MMX_PSRADrr, X86::MMX_PSRADrm, 0 },
1185 { X86::MMX_PSRAWrr, X86::MMX_PSRAWrm, 0 },
1186 { X86::MMX_PSRLDrr, X86::MMX_PSRLDrm, 0 },
1187 { X86::MMX_PSRLQrr, X86::MMX_PSRLQrm, 0 },
1188 { X86::MMX_PSRLWrr, X86::MMX_PSRLWrm, 0 },
1189 { X86::MMX_PSUBBirr, X86::MMX_PSUBBirm, 0 },
1190 { X86::MMX_PSUBDirr, X86::MMX_PSUBDirm, 0 },
1191 { X86::MMX_PSUBQirr, X86::MMX_PSUBQirm, 0 },
1192 { X86::MMX_PSUBSBirr, X86::MMX_PSUBSBirm, 0 },
1193 { X86::MMX_PSUBSWirr, X86::MMX_PSUBSWirm, 0 },
1194 { X86::MMX_PSUBUSBirr, X86::MMX_PSUBUSBirm, 0 },
1195 { X86::MMX_PSUBUSWirr, X86::MMX_PSUBUSWirm, 0 },
1196 { X86::MMX_PSUBWirr, X86::MMX_PSUBWirm, 0 },
1197 { X86::MMX_PUNPCKHBWirr, X86::MMX_PUNPCKHBWirm, 0 },
1198 { X86::MMX_PUNPCKHDQirr, X86::MMX_PUNPCKHDQirm, 0 },
1199 { X86::MMX_PUNPCKHWDirr, X86::MMX_PUNPCKHWDirm, 0 },
1200 { X86::MMX_PUNPCKLBWirr, X86::MMX_PUNPCKLBWirm, 0 },
1201 { X86::MMX_PUNPCKLDQirr, X86::MMX_PUNPCKLDQirm, 0 },
1202 { X86::MMX_PUNPCKLWDirr, X86::MMX_PUNPCKLWDirm, 0 },
1203 { X86::MMX_PXORirr, X86::MMX_PXORirm, 0 },
1204
Simon Pilgrim8dba5da2015-04-03 11:50:30 +0000[diff] [blame]1205 // 3DNow! version of foldable instructions
1206 { X86::PAVGUSBrr, X86::PAVGUSBrm, 0 },
1207 { X86::PFACCrr, X86::PFACCrm, 0 },
1208 { X86::PFADDrr, X86::PFADDrm, 0 },
1209 { X86::PFCMPEQrr, X86::PFCMPEQrm, 0 },
1210 { X86::PFCMPGErr, X86::PFCMPGErm, 0 },
1211 { X86::PFCMPGTrr, X86::PFCMPGTrm, 0 },
1212 { X86::PFMAXrr, X86::PFMAXrm, 0 },
1213 { X86::PFMINrr, X86::PFMINrm, 0 },
1214 { X86::PFMULrr, X86::PFMULrm, 0 },
1215 { X86::PFNACCrr, X86::PFNACCrm, 0 },
1216 { X86::PFPNACCrr, X86::PFPNACCrm, 0 },
1217 { X86::PFRCPIT1rr, X86::PFRCPIT1rm, 0 },
1218 { X86::PFRCPIT2rr, X86::PFRCPIT2rm, 0 },
1219 { X86::PFRSQIT1rr, X86::PFRSQIT1rm, 0 },
1220 { X86::PFSUBrr, X86::PFSUBrm, 0 },
1221 { X86::PFSUBRrr, X86::PFSUBRrm, 0 },
1222 { X86::PMULHRWrr, X86::PMULHRWrm, 0 },
1223
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1224 // AVX 128-bit versions of foldable instructions
1225 { X86::VCVTSD2SSrr, X86::VCVTSD2SSrm, 0 },
1226 { X86::Int_VCVTSD2SSrr, X86::Int_VCVTSD2SSrm, 0 },
1227 { X86::VCVTSI2SD64rr, X86::VCVTSI2SD64rm, 0 },
1228 { X86::Int_VCVTSI2SD64rr, X86::Int_VCVTSI2SD64rm, 0 },
1229 { X86::VCVTSI2SDrr, X86::VCVTSI2SDrm, 0 },
1230 { X86::Int_VCVTSI2SDrr, X86::Int_VCVTSI2SDrm, 0 },
1231 { X86::VCVTSI2SS64rr, X86::VCVTSI2SS64rm, 0 },
1232 { X86::Int_VCVTSI2SS64rr, X86::Int_VCVTSI2SS64rm, 0 },
1233 { X86::VCVTSI2SSrr, X86::VCVTSI2SSrm, 0 },
1234 { X86::Int_VCVTSI2SSrr, X86::Int_VCVTSI2SSrm, 0 },
Craig Toppercaef1c52012-12-26 00:35:47 +0000[diff] [blame]1235 { X86::VCVTSS2SDrr, X86::VCVTSS2SDrm, 0 },
1236 { X86::Int_VCVTSS2SDrr, X86::Int_VCVTSS2SDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1237 { X86::VRCPSSr, X86::VRCPSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1238 { X86::VRCPSSr_Int, X86::VRCPSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1239 { X86::VRSQRTSSr, X86::VRSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1240 { X86::VRSQRTSSr_Int, X86::VRSQRTSSm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1241 { X86::VSQRTSDr, X86::VSQRTSDm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1242 { X86::VSQRTSDr_Int, X86::VSQRTSDm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1243 { X86::VSQRTSSr, X86::VSQRTSSm, 0 },
Sanjay Patela9f6d352015-05-07 15:48:53 +0000[diff] [blame]1244 { X86::VSQRTSSr_Int, X86::VSQRTSSm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1245 { X86::VADDPDrr, X86::VADDPDrm, 0 },
1246 { X86::VADDPSrr, X86::VADDPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1247 { X86::VADDSDrr, X86::VADDSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1248 { X86::VADDSDrr_Int, X86::VADDSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1249 { X86::VADDSSrr, X86::VADDSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1250 { X86::VADDSSrr_Int, X86::VADDSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1251 { X86::VADDSUBPDrr, X86::VADDSUBPDrm, 0 },
1252 { X86::VADDSUBPSrr, X86::VADDSUBPSrm, 0 },
1253 { X86::VANDNPDrr, X86::VANDNPDrm, 0 },
1254 { X86::VANDNPSrr, X86::VANDNPSrm, 0 },
1255 { X86::VANDPDrr, X86::VANDPDrm, 0 },
1256 { X86::VANDPSrr, X86::VANDPSrm, 0 },
1257 { X86::VBLENDPDrri, X86::VBLENDPDrmi, 0 },
1258 { X86::VBLENDPSrri, X86::VBLENDPSrmi, 0 },
1259 { X86::VBLENDVPDrr, X86::VBLENDVPDrm, 0 },
1260 { X86::VBLENDVPSrr, X86::VBLENDVPSrm, 0 },
1261 { X86::VCMPPDrri, X86::VCMPPDrmi, 0 },
1262 { X86::VCMPPSrri, X86::VCMPPSrmi, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1263 { X86::VCMPSDrr, X86::VCMPSDrm, 0 },
1264 { X86::VCMPSSrr, X86::VCMPSSrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1265 { X86::VDIVPDrr, X86::VDIVPDrm, 0 },
1266 { X86::VDIVPSrr, X86::VDIVPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1267 { X86::VDIVSDrr, X86::VDIVSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1268 { X86::VDIVSDrr_Int, X86::VDIVSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1269 { X86::VDIVSSrr, X86::VDIVSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1270 { X86::VDIVSSrr_Int, X86::VDIVSSrm_Int, 0 },
1271 { X86::VDPPDrri, X86::VDPPDrmi, 0 },
1272 { X86::VDPPSrri, X86::VDPPSrmi, 0 },
Sanjay Patelb811c1d2015-02-17 20:08:21 +0000[diff] [blame]1273 // Do not fold VFs* loads because there are no scalar load variants for
1274 // these instructions. When folded, the load is required to be 128-bits, so
1275 // the load size would not match.
1276 { X86::VFvANDNPDrr, X86::VFvANDNPDrm, 0 },
1277 { X86::VFvANDNPSrr, X86::VFvANDNPSrm, 0 },
1278 { X86::VFvANDPDrr, X86::VFvANDPDrm, 0 },
1279 { X86::VFvANDPSrr, X86::VFvANDPSrm, 0 },
1280 { X86::VFvORPDrr, X86::VFvORPDrm, 0 },
1281 { X86::VFvORPSrr, X86::VFvORPSrm, 0 },
1282 { X86::VFvXORPDrr, X86::VFvXORPDrm, 0 },
1283 { X86::VFvXORPSrr, X86::VFvXORPSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1284 { X86::VHADDPDrr, X86::VHADDPDrm, 0 },
1285 { X86::VHADDPSrr, X86::VHADDPSrm, 0 },
1286 { X86::VHSUBPDrr, X86::VHSUBPDrm, 0 },
1287 { X86::VHSUBPSrr, X86::VHSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1288 { X86::Int_VCMPSDrr, X86::Int_VCMPSDrm, 0 },
1289 { X86::Int_VCMPSSrr, X86::Int_VCMPSSrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1290 { X86::VMAXPDrr, X86::VMAXPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1291 { X86::VMAXPSrr, X86::VMAXPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1292 { X86::VMAXSDrr, X86::VMAXSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1293 { X86::VMAXSDrr_Int, X86::VMAXSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1294 { X86::VMAXSSrr, X86::VMAXSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1295 { X86::VMAXSSrr_Int, X86::VMAXSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1296 { X86::VMINPDrr, X86::VMINPDrm, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1297 { X86::VMINPSrr, X86::VMINPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1298 { X86::VMINSDrr, X86::VMINSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1299 { X86::VMINSDrr_Int, X86::VMINSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1300 { X86::VMINSSrr, X86::VMINSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1301 { X86::VMINSSrr_Int, X86::VMINSSrm_Int, 0 },
Craig Topper81d1e592012-12-26 02:44:47 +0000[diff] [blame]1302 { X86::VMPSADBWrri, X86::VMPSADBWrmi, 0 },
1303 { X86::VMULPDrr, X86::VMULPDrm, 0 },
1304 { X86::VMULPSrr, X86::VMULPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1305 { X86::VMULSDrr, X86::VMULSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1306 { X86::VMULSDrr_Int, X86::VMULSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1307 { X86::VMULSSrr, X86::VMULSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1308 { X86::VMULSSrr_Int, X86::VMULSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1309 { X86::VORPDrr, X86::VORPDrm, 0 },
1310 { X86::VORPSrr, X86::VORPSrm, 0 },
1311 { X86::VPACKSSDWrr, X86::VPACKSSDWrm, 0 },
1312 { X86::VPACKSSWBrr, X86::VPACKSSWBrm, 0 },
1313 { X86::VPACKUSDWrr, X86::VPACKUSDWrm, 0 },
1314 { X86::VPACKUSWBrr, X86::VPACKUSWBrm, 0 },
1315 { X86::VPADDBrr, X86::VPADDBrm, 0 },
1316 { X86::VPADDDrr, X86::VPADDDrm, 0 },
1317 { X86::VPADDQrr, X86::VPADDQrm, 0 },
1318 { X86::VPADDSBrr, X86::VPADDSBrm, 0 },
1319 { X86::VPADDSWrr, X86::VPADDSWrm, 0 },
1320 { X86::VPADDUSBrr, X86::VPADDUSBrm, 0 },
1321 { X86::VPADDUSWrr, X86::VPADDUSWrm, 0 },
1322 { X86::VPADDWrr, X86::VPADDWrm, 0 },
1323 { X86::VPALIGNR128rr, X86::VPALIGNR128rm, 0 },
1324 { X86::VPANDNrr, X86::VPANDNrm, 0 },
1325 { X86::VPANDrr, X86::VPANDrm, 0 },
1326 { X86::VPAVGBrr, X86::VPAVGBrm, 0 },
1327 { X86::VPAVGWrr, X86::VPAVGWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1328 { X86::VPBLENDVBrr, X86::VPBLENDVBrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1329 { X86::VPBLENDWrri, X86::VPBLENDWrmi, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1330 { X86::VPCLMULQDQrr, X86::VPCLMULQDQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1331 { X86::VPCMPEQBrr, X86::VPCMPEQBrm, 0 },
1332 { X86::VPCMPEQDrr, X86::VPCMPEQDrm, 0 },
1333 { X86::VPCMPEQQrr, X86::VPCMPEQQrm, 0 },
1334 { X86::VPCMPEQWrr, X86::VPCMPEQWrm, 0 },
1335 { X86::VPCMPGTBrr, X86::VPCMPGTBrm, 0 },
1336 { X86::VPCMPGTDrr, X86::VPCMPGTDrm, 0 },
1337 { X86::VPCMPGTQrr, X86::VPCMPGTQrm, 0 },
1338 { X86::VPCMPGTWrr, X86::VPCMPGTWrm, 0 },
1339 { X86::VPHADDDrr, X86::VPHADDDrm, 0 },
1340 { X86::VPHADDSWrr128, X86::VPHADDSWrm128, 0 },
1341 { X86::VPHADDWrr, X86::VPHADDWrm, 0 },
1342 { X86::VPHSUBDrr, X86::VPHSUBDrm, 0 },
1343 { X86::VPHSUBSWrr128, X86::VPHSUBSWrm128, 0 },
1344 { X86::VPHSUBWrr, X86::VPHSUBWrm, 0 },
1345 { X86::VPERMILPDrr, X86::VPERMILPDrm, 0 },
1346 { X86::VPERMILPSrr, X86::VPERMILPSrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1347 { X86::VPINSRBrr, X86::VPINSRBrm, 0 },
1348 { X86::VPINSRDrr, X86::VPINSRDrm, 0 },
1349 { X86::VPINSRQrr, X86::VPINSRQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1350 { X86::VPINSRWrri, X86::VPINSRWrmi, 0 },
1351 { X86::VPMADDUBSWrr128, X86::VPMADDUBSWrm128, 0 },
1352 { X86::VPMADDWDrr, X86::VPMADDWDrm, 0 },
1353 { X86::VPMAXSWrr, X86::VPMAXSWrm, 0 },
1354 { X86::VPMAXUBrr, X86::VPMAXUBrm, 0 },
1355 { X86::VPMINSWrr, X86::VPMINSWrm, 0 },
1356 { X86::VPMINUBrr, X86::VPMINUBrm, 0 },
1357 { X86::VPMINSBrr, X86::VPMINSBrm, 0 },
1358 { X86::VPMINSDrr, X86::VPMINSDrm, 0 },
1359 { X86::VPMINUDrr, X86::VPMINUDrm, 0 },
1360 { X86::VPMINUWrr, X86::VPMINUWrm, 0 },
1361 { X86::VPMAXSBrr, X86::VPMAXSBrm, 0 },
1362 { X86::VPMAXSDrr, X86::VPMAXSDrm, 0 },
1363 { X86::VPMAXUDrr, X86::VPMAXUDrm, 0 },
1364 { X86::VPMAXUWrr, X86::VPMAXUWrm, 0 },
1365 { X86::VPMULDQrr, X86::VPMULDQrm, 0 },
1366 { X86::VPMULHRSWrr128, X86::VPMULHRSWrm128, 0 },
1367 { X86::VPMULHUWrr, X86::VPMULHUWrm, 0 },
1368 { X86::VPMULHWrr, X86::VPMULHWrm, 0 },
1369 { X86::VPMULLDrr, X86::VPMULLDrm, 0 },
1370 { X86::VPMULLWrr, X86::VPMULLWrm, 0 },
1371 { X86::VPMULUDQrr, X86::VPMULUDQrm, 0 },
1372 { X86::VPORrr, X86::VPORrm, 0 },
1373 { X86::VPSADBWrr, X86::VPSADBWrm, 0 },
1374 { X86::VPSHUFBrr, X86::VPSHUFBrm, 0 },
1375 { X86::VPSIGNBrr, X86::VPSIGNBrm, 0 },
1376 { X86::VPSIGNWrr, X86::VPSIGNWrm, 0 },
1377 { X86::VPSIGNDrr, X86::VPSIGNDrm, 0 },
1378 { X86::VPSLLDrr, X86::VPSLLDrm, 0 },
1379 { X86::VPSLLQrr, X86::VPSLLQrm, 0 },
1380 { X86::VPSLLWrr, X86::VPSLLWrm, 0 },
1381 { X86::VPSRADrr, X86::VPSRADrm, 0 },
1382 { X86::VPSRAWrr, X86::VPSRAWrm, 0 },
1383 { X86::VPSRLDrr, X86::VPSRLDrm, 0 },
1384 { X86::VPSRLQrr, X86::VPSRLQrm, 0 },
1385 { X86::VPSRLWrr, X86::VPSRLWrm, 0 },
1386 { X86::VPSUBBrr, X86::VPSUBBrm, 0 },
1387 { X86::VPSUBDrr, X86::VPSUBDrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1388 { X86::VPSUBQrr, X86::VPSUBQrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1389 { X86::VPSUBSBrr, X86::VPSUBSBrm, 0 },
1390 { X86::VPSUBSWrr, X86::VPSUBSWrm, 0 },
Simon Pilgrim5fa0fb22015-01-21 23:43:30 +0000[diff] [blame]1391 { X86::VPSUBUSBrr, X86::VPSUBUSBrm, 0 },
1392 { X86::VPSUBUSWrr, X86::VPSUBUSWrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1393 { X86::VPSUBWrr, X86::VPSUBWrm, 0 },
1394 { X86::VPUNPCKHBWrr, X86::VPUNPCKHBWrm, 0 },
1395 { X86::VPUNPCKHDQrr, X86::VPUNPCKHDQrm, 0 },
1396 { X86::VPUNPCKHQDQrr, X86::VPUNPCKHQDQrm, 0 },
1397 { X86::VPUNPCKHWDrr, X86::VPUNPCKHWDrm, 0 },
1398 { X86::VPUNPCKLBWrr, X86::VPUNPCKLBWrm, 0 },
1399 { X86::VPUNPCKLDQrr, X86::VPUNPCKLDQrm, 0 },
1400 { X86::VPUNPCKLQDQrr, X86::VPUNPCKLQDQrm, 0 },
1401 { X86::VPUNPCKLWDrr, X86::VPUNPCKLWDrm, 0 },
1402 { X86::VPXORrr, X86::VPXORrm, 0 },
Simon Pilgrim752de5d2015-07-08 08:07:57 +0000[diff] [blame]1403 { X86::VROUNDSDr, X86::VROUNDSDm, 0 },
1404 { X86::VROUNDSSr, X86::VROUNDSSm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1405 { X86::VSHUFPDrri, X86::VSHUFPDrmi, 0 },
1406 { X86::VSHUFPSrri, X86::VSHUFPSrmi, 0 },
1407 { X86::VSUBPDrr, X86::VSUBPDrm, 0 },
1408 { X86::VSUBPSrr, X86::VSUBPSrm, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1409 { X86::VSUBSDrr, X86::VSUBSDrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1410 { X86::VSUBSDrr_Int, X86::VSUBSDrm_Int, 0 },
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]1411 { X86::VSUBSSrr, X86::VSUBSSrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1412 { X86::VSUBSSrr_Int, X86::VSUBSSrm_Int, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1413 { X86::VUNPCKHPDrr, X86::VUNPCKHPDrm, 0 },
1414 { X86::VUNPCKHPSrr, X86::VUNPCKHPSrm, 0 },
1415 { X86::VUNPCKLPDrr, X86::VUNPCKLPDrm, 0 },
1416 { X86::VUNPCKLPSrr, X86::VUNPCKLPSrm, 0 },
1417 { X86::VXORPDrr, X86::VXORPDrm, 0 },
1418 { X86::VXORPSrr, X86::VXORPSrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1419
Craig Topperd78429f2012-01-14 18:14:53 +0000[diff] [blame]1420 // AVX 256-bit foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1421 { X86::VADDPDYrr, X86::VADDPDYrm, 0 },
1422 { X86::VADDPSYrr, X86::VADDPSYrm, 0 },
1423 { X86::VADDSUBPDYrr, X86::VADDSUBPDYrm, 0 },
1424 { X86::VADDSUBPSYrr, X86::VADDSUBPSYrm, 0 },
1425 { X86::VANDNPDYrr, X86::VANDNPDYrm, 0 },
1426 { X86::VANDNPSYrr, X86::VANDNPSYrm, 0 },
1427 { X86::VANDPDYrr, X86::VANDPDYrm, 0 },
1428 { X86::VANDPSYrr, X86::VANDPSYrm, 0 },
1429 { X86::VBLENDPDYrri, X86::VBLENDPDYrmi, 0 },
1430 { X86::VBLENDPSYrri, X86::VBLENDPSYrmi, 0 },
1431 { X86::VBLENDVPDYrr, X86::VBLENDVPDYrm, 0 },
1432 { X86::VBLENDVPSYrr, X86::VBLENDVPSYrm, 0 },
1433 { X86::VCMPPDYrri, X86::VCMPPDYrmi, 0 },
1434 { X86::VCMPPSYrri, X86::VCMPPSYrmi, 0 },
1435 { X86::VDIVPDYrr, X86::VDIVPDYrm, 0 },
1436 { X86::VDIVPSYrr, X86::VDIVPSYrm, 0 },
Simon Pilgrim20bc37c2015-01-19 22:40:45 +0000[diff] [blame]1437 { X86::VDPPSYrri, X86::VDPPSYrmi, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1438 { X86::VHADDPDYrr, X86::VHADDPDYrm, 0 },
1439 { X86::VHADDPSYrr, X86::VHADDPSYrm, 0 },
1440 { X86::VHSUBPDYrr, X86::VHSUBPDYrm, 0 },
1441 { X86::VHSUBPSYrr, X86::VHSUBPSYrm, 0 },
1442 { X86::VINSERTF128rr, X86::VINSERTF128rm, 0 },
1443 { X86::VMAXPDYrr, X86::VMAXPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1444 { X86::VMAXPSYrr, X86::VMAXPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1445 { X86::VMINPDYrr, X86::VMINPDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1446 { X86::VMINPSYrr, X86::VMINPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1447 { X86::VMULPDYrr, X86::VMULPDYrm, 0 },
1448 { X86::VMULPSYrr, X86::VMULPSYrm, 0 },
1449 { X86::VORPDYrr, X86::VORPDYrm, 0 },
1450 { X86::VORPSYrr, X86::VORPSYrm, 0 },
1451 { X86::VPERM2F128rr, X86::VPERM2F128rm, 0 },
1452 { X86::VPERMILPDYrr, X86::VPERMILPDYrm, 0 },
1453 { X86::VPERMILPSYrr, X86::VPERMILPSYrm, 0 },
1454 { X86::VSHUFPDYrri, X86::VSHUFPDYrmi, 0 },
1455 { X86::VSHUFPSYrri, X86::VSHUFPSYrmi, 0 },
1456 { X86::VSUBPDYrr, X86::VSUBPDYrm, 0 },
1457 { X86::VSUBPSYrr, X86::VSUBPSYrm, 0 },
1458 { X86::VUNPCKHPDYrr, X86::VUNPCKHPDYrm, 0 },
1459 { X86::VUNPCKHPSYrr, X86::VUNPCKHPSYrm, 0 },
1460 { X86::VUNPCKLPDYrr, X86::VUNPCKLPDYrm, 0 },
1461 { X86::VUNPCKLPSYrr, X86::VUNPCKLPSYrm, 0 },
1462 { X86::VXORPDYrr, X86::VXORPDYrm, 0 },
1463 { X86::VXORPSYrr, X86::VXORPSYrm, 0 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1464
Craig Topper182b00a2011-11-14 08:07:55 +0000[diff] [blame]1465 // AVX2 foldable instructions
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1466 { X86::VINSERTI128rr, X86::VINSERTI128rm, 0 },
1467 { X86::VPACKSSDWYrr, X86::VPACKSSDWYrm, 0 },
1468 { X86::VPACKSSWBYrr, X86::VPACKSSWBYrm, 0 },
1469 { X86::VPACKUSDWYrr, X86::VPACKUSDWYrm, 0 },
1470 { X86::VPACKUSWBYrr, X86::VPACKUSWBYrm, 0 },
1471 { X86::VPADDBYrr, X86::VPADDBYrm, 0 },
1472 { X86::VPADDDYrr, X86::VPADDDYrm, 0 },
1473 { X86::VPADDQYrr, X86::VPADDQYrm, 0 },
1474 { X86::VPADDSBYrr, X86::VPADDSBYrm, 0 },
1475 { X86::VPADDSWYrr, X86::VPADDSWYrm, 0 },
1476 { X86::VPADDUSBYrr, X86::VPADDUSBYrm, 0 },
1477 { X86::VPADDUSWYrr, X86::VPADDUSWYrm, 0 },
1478 { X86::VPADDWYrr, X86::VPADDWYrm, 0 },
1479 { X86::VPALIGNR256rr, X86::VPALIGNR256rm, 0 },
1480 { X86::VPANDNYrr, X86::VPANDNYrm, 0 },
1481 { X86::VPANDYrr, X86::VPANDYrm, 0 },
1482 { X86::VPAVGBYrr, X86::VPAVGBYrm, 0 },
1483 { X86::VPAVGWYrr, X86::VPAVGWYrm, 0 },
1484 { X86::VPBLENDDrri, X86::VPBLENDDrmi, 0 },
1485 { X86::VPBLENDDYrri, X86::VPBLENDDYrmi, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1486 { X86::VPBLENDVBYrr, X86::VPBLENDVBYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1487 { X86::VPBLENDWYrri, X86::VPBLENDWYrmi, 0 },
1488 { X86::VPCMPEQBYrr, X86::VPCMPEQBYrm, 0 },
1489 { X86::VPCMPEQDYrr, X86::VPCMPEQDYrm, 0 },
1490 { X86::VPCMPEQQYrr, X86::VPCMPEQQYrm, 0 },
1491 { X86::VPCMPEQWYrr, X86::VPCMPEQWYrm, 0 },
1492 { X86::VPCMPGTBYrr, X86::VPCMPGTBYrm, 0 },
1493 { X86::VPCMPGTDYrr, X86::VPCMPGTDYrm, 0 },
1494 { X86::VPCMPGTQYrr, X86::VPCMPGTQYrm, 0 },
1495 { X86::VPCMPGTWYrr, X86::VPCMPGTWYrm, 0 },
1496 { X86::VPERM2I128rr, X86::VPERM2I128rm, 0 },
1497 { X86::VPERMDYrr, X86::VPERMDYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1498 { X86::VPERMPSYrr, X86::VPERMPSYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1499 { X86::VPHADDDYrr, X86::VPHADDDYrm, 0 },
1500 { X86::VPHADDSWrr256, X86::VPHADDSWrm256, 0 },
1501 { X86::VPHADDWYrr, X86::VPHADDWYrm, 0 },
1502 { X86::VPHSUBDYrr, X86::VPHSUBDYrm, 0 },
1503 { X86::VPHSUBSWrr256, X86::VPHSUBSWrm256, 0 },
1504 { X86::VPHSUBWYrr, X86::VPHSUBWYrm, 0 },
1505 { X86::VPMADDUBSWrr256, X86::VPMADDUBSWrm256, 0 },
1506 { X86::VPMADDWDYrr, X86::VPMADDWDYrm, 0 },
1507 { X86::VPMAXSWYrr, X86::VPMAXSWYrm, 0 },
1508 { X86::VPMAXUBYrr, X86::VPMAXUBYrm, 0 },
1509 { X86::VPMINSWYrr, X86::VPMINSWYrm, 0 },
1510 { X86::VPMINUBYrr, X86::VPMINUBYrm, 0 },
1511 { X86::VPMINSBYrr, X86::VPMINSBYrm, 0 },
1512 { X86::VPMINSDYrr, X86::VPMINSDYrm, 0 },
1513 { X86::VPMINUDYrr, X86::VPMINUDYrm, 0 },
1514 { X86::VPMINUWYrr, X86::VPMINUWYrm, 0 },
1515 { X86::VPMAXSBYrr, X86::VPMAXSBYrm, 0 },
1516 { X86::VPMAXSDYrr, X86::VPMAXSDYrm, 0 },
1517 { X86::VPMAXUDYrr, X86::VPMAXUDYrm, 0 },
1518 { X86::VPMAXUWYrr, X86::VPMAXUWYrm, 0 },
1519 { X86::VMPSADBWYrri, X86::VMPSADBWYrmi, 0 },
1520 { X86::VPMULDQYrr, X86::VPMULDQYrm, 0 },
1521 { X86::VPMULHRSWrr256, X86::VPMULHRSWrm256, 0 },
1522 { X86::VPMULHUWYrr, X86::VPMULHUWYrm, 0 },
1523 { X86::VPMULHWYrr, X86::VPMULHWYrm, 0 },
1524 { X86::VPMULLDYrr, X86::VPMULLDYrm, 0 },
1525 { X86::VPMULLWYrr, X86::VPMULLWYrm, 0 },
1526 { X86::VPMULUDQYrr, X86::VPMULUDQYrm, 0 },
1527 { X86::VPORYrr, X86::VPORYrm, 0 },
1528 { X86::VPSADBWYrr, X86::VPSADBWYrm, 0 },
1529 { X86::VPSHUFBYrr, X86::VPSHUFBYrm, 0 },
1530 { X86::VPSIGNBYrr, X86::VPSIGNBYrm, 0 },
1531 { X86::VPSIGNWYrr, X86::VPSIGNWYrm, 0 },
1532 { X86::VPSIGNDYrr, X86::VPSIGNDYrm, 0 },
1533 { X86::VPSLLDYrr, X86::VPSLLDYrm, 0 },
1534 { X86::VPSLLQYrr, X86::VPSLLQYrm, 0 },
1535 { X86::VPSLLWYrr, X86::VPSLLWYrm, 0 },
1536 { X86::VPSLLVDrr, X86::VPSLLVDrm, 0 },
1537 { X86::VPSLLVDYrr, X86::VPSLLVDYrm, 0 },
1538 { X86::VPSLLVQrr, X86::VPSLLVQrm, 0 },
1539 { X86::VPSLLVQYrr, X86::VPSLLVQYrm, 0 },
1540 { X86::VPSRADYrr, X86::VPSRADYrm, 0 },
1541 { X86::VPSRAWYrr, X86::VPSRAWYrm, 0 },
1542 { X86::VPSRAVDrr, X86::VPSRAVDrm, 0 },
1543 { X86::VPSRAVDYrr, X86::VPSRAVDYrm, 0 },
1544 { X86::VPSRLDYrr, X86::VPSRLDYrm, 0 },
1545 { X86::VPSRLQYrr, X86::VPSRLQYrm, 0 },
1546 { X86::VPSRLWYrr, X86::VPSRLWYrm, 0 },
1547 { X86::VPSRLVDrr, X86::VPSRLVDrm, 0 },
1548 { X86::VPSRLVDYrr, X86::VPSRLVDYrm, 0 },
1549 { X86::VPSRLVQrr, X86::VPSRLVQrm, 0 },
1550 { X86::VPSRLVQYrr, X86::VPSRLVQYrm, 0 },
1551 { X86::VPSUBBYrr, X86::VPSUBBYrm, 0 },
1552 { X86::VPSUBDYrr, X86::VPSUBDYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1553 { X86::VPSUBQYrr, X86::VPSUBQYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1554 { X86::VPSUBSBYrr, X86::VPSUBSBYrm, 0 },
1555 { X86::VPSUBSWYrr, X86::VPSUBSWYrm, 0 },
Simon Pilgrimd142ab72015-02-10 13:22:57 +0000[diff] [blame]1556 { X86::VPSUBUSBYrr, X86::VPSUBUSBYrm, 0 },
1557 { X86::VPSUBUSWYrr, X86::VPSUBUSWYrm, 0 },
Nadav Rotemdc0ad922012-12-24 09:40:33 +0000[diff] [blame]1558 { X86::VPSUBWYrr, X86::VPSUBWYrm, 0 },
1559 { X86::VPUNPCKHBWYrr, X86::VPUNPCKHBWYrm, 0 },
1560 { X86::VPUNPCKHDQYrr, X86::VPUNPCKHDQYrm, 0 },
1561 { X86::VPUNPCKHQDQYrr, X86::VPUNPCKHQDQYrm, 0 },
1562 { X86::VPUNPCKHWDYrr, X86::VPUNPCKHWDYrm, 0 },
1563 { X86::VPUNPCKLBWYrr, X86::VPUNPCKLBWYrm, 0 },
1564 { X86::VPUNPCKLDQYrr, X86::VPUNPCKLDQYrm, 0 },
1565 { X86::VPUNPCKLQDQYrr, X86::VPUNPCKLQDQYrm, 0 },
1566 { X86::VPUNPCKLWDYrr, X86::VPUNPCKLWDYrm, 0 },
1567 { X86::VPXORYrr, X86::VPXORYrm, 0 },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1568
1569 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1570 { X86::VFMADDSS4rr, X86::VFMADDSS4mr, TB_ALIGN_NONE },
1571 { X86::VFMADDSD4rr, X86::VFMADDSD4mr, TB_ALIGN_NONE },
1572 { X86::VFMADDPS4rr, X86::VFMADDPS4mr, TB_ALIGN_NONE },
1573 { X86::VFMADDPD4rr, X86::VFMADDPD4mr, TB_ALIGN_NONE },
1574 { X86::VFMADDPS4rrY, X86::VFMADDPS4mrY, TB_ALIGN_NONE },
1575 { X86::VFMADDPD4rrY, X86::VFMADDPD4mrY, TB_ALIGN_NONE },
1576 { X86::VFNMADDSS4rr, X86::VFNMADDSS4mr, TB_ALIGN_NONE },
1577 { X86::VFNMADDSD4rr, X86::VFNMADDSD4mr, TB_ALIGN_NONE },
1578 { X86::VFNMADDPS4rr, X86::VFNMADDPS4mr, TB_ALIGN_NONE },
1579 { X86::VFNMADDPD4rr, X86::VFNMADDPD4mr, TB_ALIGN_NONE },
1580 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4mrY, TB_ALIGN_NONE },
1581 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4mrY, TB_ALIGN_NONE },
1582 { X86::VFMSUBSS4rr, X86::VFMSUBSS4mr, TB_ALIGN_NONE },
1583 { X86::VFMSUBSD4rr, X86::VFMSUBSD4mr, TB_ALIGN_NONE },
1584 { X86::VFMSUBPS4rr, X86::VFMSUBPS4mr, TB_ALIGN_NONE },
1585 { X86::VFMSUBPD4rr, X86::VFMSUBPD4mr, TB_ALIGN_NONE },
1586 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4mrY, TB_ALIGN_NONE },
1587 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4mrY, TB_ALIGN_NONE },
1588 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4mr, TB_ALIGN_NONE },
1589 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4mr, TB_ALIGN_NONE },
1590 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4mr, TB_ALIGN_NONE },
1591 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4mr, TB_ALIGN_NONE },
1592 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4mrY, TB_ALIGN_NONE },
1593 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4mrY, TB_ALIGN_NONE },
1594 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4mr, TB_ALIGN_NONE },
1595 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4mr, TB_ALIGN_NONE },
1596 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4mrY, TB_ALIGN_NONE },
1597 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4mrY, TB_ALIGN_NONE },
1598 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4mr, TB_ALIGN_NONE },
1599 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4mr, TB_ALIGN_NONE },
1600 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4mrY, TB_ALIGN_NONE },
1601 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4mrY, TB_ALIGN_NONE },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1602
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1603 // XOP foldable instructions
1604 { X86::VPCMOVrr, X86::VPCMOVmr, 0 },
1605 { X86::VPCMOVrrY, X86::VPCMOVmrY, 0 },
1606 { X86::VPCOMBri, X86::VPCOMBmi, 0 },
1607 { X86::VPCOMDri, X86::VPCOMDmi, 0 },
1608 { X86::VPCOMQri, X86::VPCOMQmi, 0 },
1609 { X86::VPCOMWri, X86::VPCOMWmi, 0 },
1610 { X86::VPCOMUBri, X86::VPCOMUBmi, 0 },
1611 { X86::VPCOMUDri, X86::VPCOMUDmi, 0 },
1612 { X86::VPCOMUQri, X86::VPCOMUQmi, 0 },
1613 { X86::VPCOMUWri, X86::VPCOMUWmi, 0 },
1614 { X86::VPERMIL2PDrr, X86::VPERMIL2PDmr, 0 },
1615 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDmrY, 0 },
1616 { X86::VPERMIL2PSrr, X86::VPERMIL2PSmr, 0 },
1617 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSmrY, 0 },
1618 { X86::VPMACSDDrr, X86::VPMACSDDrm, 0 },
1619 { X86::VPMACSDQHrr, X86::VPMACSDQHrm, 0 },
1620 { X86::VPMACSDQLrr, X86::VPMACSDQLrm, 0 },
1621 { X86::VPMACSSDDrr, X86::VPMACSSDDrm, 0 },
1622 { X86::VPMACSSDQHrr, X86::VPMACSSDQHrm, 0 },
1623 { X86::VPMACSSDQLrr, X86::VPMACSSDQLrm, 0 },
1624 { X86::VPMACSSWDrr, X86::VPMACSSWDrm, 0 },
1625 { X86::VPMACSSWWrr, X86::VPMACSSWWrm, 0 },
1626 { X86::VPMACSWDrr, X86::VPMACSWDrm, 0 },
1627 { X86::VPMACSWWrr, X86::VPMACSWWrm, 0 },
1628 { X86::VPMADCSSWDrr, X86::VPMADCSSWDrm, 0 },
1629 { X86::VPMADCSWDrr, X86::VPMADCSWDrm, 0 },
1630 { X86::VPPERMrr, X86::VPPERMmr, 0 },
1631 { X86::VPROTBrr, X86::VPROTBrm, 0 },
1632 { X86::VPROTDrr, X86::VPROTDrm, 0 },
1633 { X86::VPROTQrr, X86::VPROTQrm, 0 },
1634 { X86::VPROTWrr, X86::VPROTWrm, 0 },
1635 { X86::VPSHABrr, X86::VPSHABrm, 0 },
1636 { X86::VPSHADrr, X86::VPSHADrm, 0 },
1637 { X86::VPSHAQrr, X86::VPSHAQrm, 0 },
1638 { X86::VPSHAWrr, X86::VPSHAWrm, 0 },
1639 { X86::VPSHLBrr, X86::VPSHLBrm, 0 },
1640 { X86::VPSHLDrr, X86::VPSHLDrm, 0 },
1641 { X86::VPSHLQrr, X86::VPSHLQrm, 0 },
1642 { X86::VPSHLWrr, X86::VPSHLWrm, 0 },
1643
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1644 // BMI/BMI2 foldable instructions
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1645 { X86::ANDN32rr, X86::ANDN32rm, 0 },
1646 { X86::ANDN64rr, X86::ANDN64rm, 0 },
Michael Liaof9f7b552012-09-26 08:22:37 +0000[diff] [blame]1647 { X86::MULX32rr, X86::MULX32rm, 0 },
1648 { X86::MULX64rr, X86::MULX64rm, 0 },
Craig Topperf924a582012-12-17 05:02:29 +0000[diff] [blame]1649 { X86::PDEP32rr, X86::PDEP32rm, 0 },
1650 { X86::PDEP64rr, X86::PDEP64rm, 0 },
1651 { X86::PEXT32rr, X86::PEXT32rm, 0 },
1652 { X86::PEXT64rr, X86::PEXT64rm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1653
Simon Pilgrim4ba59692015-12-05 07:27:50 +0000[diff] [blame]1654 // ADX foldable instructions
1655 { X86::ADCX32rr, X86::ADCX32rm, 0 },
1656 { X86::ADCX64rr, X86::ADCX64rm, 0 },
1657 { X86::ADOX32rr, X86::ADOX32rm, 0 },
1658 { X86::ADOX64rr, X86::ADOX64rm, 0 },
1659
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1660 // AVX-512 foldable instructions
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1661 { X86::VADDPSZrr, X86::VADDPSZrm, 0 },
1662 { X86::VADDPDZrr, X86::VADDPDZrm, 0 },
1663 { X86::VSUBPSZrr, X86::VSUBPSZrm, 0 },
1664 { X86::VSUBPDZrr, X86::VSUBPDZrm, 0 },
1665 { X86::VMULPSZrr, X86::VMULPSZrm, 0 },
1666 { X86::VMULPDZrr, X86::VMULPDZrm, 0 },
1667 { X86::VDIVPSZrr, X86::VDIVPSZrm, 0 },
1668 { X86::VDIVPDZrr, X86::VDIVPDZrm, 0 },
1669 { X86::VMINPSZrr, X86::VMINPSZrm, 0 },
1670 { X86::VMINPDZrr, X86::VMINPDZrm, 0 },
1671 { X86::VMAXPSZrr, X86::VMAXPSZrm, 0 },
1672 { X86::VMAXPDZrr, X86::VMAXPDZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1673 { X86::VPADDDZrr, X86::VPADDDZrm, 0 },
1674 { X86::VPADDQZrr, X86::VPADDQZrm, 0 },
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]1675 { X86::VPERMPDZri, X86::VPERMPDZmi, 0 },
1676 { X86::VPERMPSZrr, X86::VPERMPSZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1677 { X86::VPMAXSDZrr, X86::VPMAXSDZrm, 0 },
1678 { X86::VPMAXSQZrr, X86::VPMAXSQZrm, 0 },
1679 { X86::VPMAXUDZrr, X86::VPMAXUDZrm, 0 },
1680 { X86::VPMAXUQZrr, X86::VPMAXUQZrm, 0 },
1681 { X86::VPMINSDZrr, X86::VPMINSDZrm, 0 },
1682 { X86::VPMINSQZrr, X86::VPMINSQZrm, 0 },
1683 { X86::VPMINUDZrr, X86::VPMINUDZrm, 0 },
1684 { X86::VPMINUQZrr, X86::VPMINUQZrm, 0 },
1685 { X86::VPMULDQZrr, X86::VPMULDQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1686 { X86::VPSLLVDZrr, X86::VPSLLVDZrm, 0 },
1687 { X86::VPSLLVQZrr, X86::VPSLLVQZrm, 0 },
1688 { X86::VPSRAVDZrr, X86::VPSRAVDZrm, 0 },
1689 { X86::VPSRLVDZrr, X86::VPSRLVDZrm, 0 },
1690 { X86::VPSRLVQZrr, X86::VPSRLVQZrm, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1691 { X86::VPSUBDZrr, X86::VPSUBDZrm, 0 },
1692 { X86::VPSUBQZrr, X86::VPSUBQZrm, 0 },
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]1693 { X86::VSHUFPDZrri, X86::VSHUFPDZrmi, 0 },
1694 { X86::VSHUFPSZrri, X86::VSHUFPSZrmi, 0 },
Igor Breger00d9f842015-06-08 14:03:17 +0000[diff] [blame]1695 { X86::VALIGNQZrri, X86::VALIGNQZrmi, 0 },
1696 { X86::VALIGNDZrri, X86::VALIGNDZrmi, 0 },
Elena Demikhovskybb2f6b72014-03-27 09:45:08 +0000[diff] [blame]1697 { X86::VPMULUDQZrr, X86::VPMULUDQZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1698 { X86::VBROADCASTSSZrkz, X86::VBROADCASTSSZmkz, TB_NO_REVERSE },
1699 { X86::VBROADCASTSDZrkz, X86::VBROADCASTSDZmkz, TB_NO_REVERSE },
1700
1701 // AVX-512{F,VL} foldable instructions
1702 { X86::VBROADCASTSSZ256rkz, X86::VBROADCASTSSZ256mkz, TB_NO_REVERSE },
1703 { X86::VBROADCASTSDZ256rkz, X86::VBROADCASTSDZ256mkz, TB_NO_REVERSE },
1704 { X86::VBROADCASTSSZ128rkz, X86::VBROADCASTSSZ128mkz, TB_NO_REVERSE },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1705
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1706 // AVX-512{F,VL} foldable instructions
1707 { X86::VADDPDZ128rr, X86::VADDPDZ128rm, 0 },
1708 { X86::VADDPDZ256rr, X86::VADDPDZ256rm, 0 },
1709 { X86::VADDPSZ128rr, X86::VADDPSZ128rm, 0 },
1710 { X86::VADDPSZ256rr, X86::VADDPSZ256rm, 0 },
1711
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1712 // AES foldable instructions
1713 { X86::AESDECLASTrr, X86::AESDECLASTrm, TB_ALIGN_16 },
1714 { X86::AESDECrr, X86::AESDECrm, TB_ALIGN_16 },
1715 { X86::AESENCLASTrr, X86::AESENCLASTrm, TB_ALIGN_16 },
1716 { X86::AESENCrr, X86::AESENCrm, TB_ALIGN_16 },
Craig Topperf7e92f12015-02-10 05:10:50 +0000[diff] [blame]1717 { X86::VAESDECLASTrr, X86::VAESDECLASTrm, 0 },
1718 { X86::VAESDECrr, X86::VAESDECrm, 0 },
1719 { X86::VAESENCLASTrr, X86::VAESENCLASTrm, 0 },
1720 { X86::VAESENCrr, X86::VAESENCrm, 0 },
Craig Topper514f02c2013-09-17 06:50:11 +0000[diff] [blame]1721
1722 // SHA foldable instructions
1723 { X86::SHA1MSG1rr, X86::SHA1MSG1rm, TB_ALIGN_16 },
1724 { X86::SHA1MSG2rr, X86::SHA1MSG2rm, TB_ALIGN_16 },
1725 { X86::SHA1NEXTErr, X86::SHA1NEXTErm, TB_ALIGN_16 },
1726 { X86::SHA1RNDS4rri, X86::SHA1RNDS4rmi, TB_ALIGN_16 },
1727 { X86::SHA256MSG1rr, X86::SHA256MSG1rm, TB_ALIGN_16 },
1728 { X86::SHA256MSG2rr, X86::SHA256MSG2rm, TB_ALIGN_16 },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1729 { X86::SHA256RNDS2rr, X86::SHA256RNDS2rm, TB_ALIGN_16 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1730 };
1731
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1732 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable2) {
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1733 AddTableEntry(RegOp2MemOpTable2, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1734 Entry.RegOp, Entry.MemOp,
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]1735 // Index 2, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1736 Entry.Flags | TB_INDEX_2 | TB_FOLDED_LOAD);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]1737 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1738
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1739 static const X86MemoryFoldTableEntry MemoryFoldTable3[] = {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1740 // FMA foldable instructions
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1741 { X86::VFMADDSSr231r, X86::VFMADDSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1742 { X86::VFMADDSSr231r_Int, X86::VFMADDSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1743 { X86::VFMADDSDr231r, X86::VFMADDSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1744 { X86::VFMADDSDr231r_Int, X86::VFMADDSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1745 { X86::VFMADDSSr132r, X86::VFMADDSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1746 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1747 { X86::VFMADDSDr132r, X86::VFMADDSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1748 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1749 { X86::VFMADDSSr213r, X86::VFMADDSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1750 { X86::VFMADDSSr213r_Int, X86::VFMADDSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1751 { X86::VFMADDSDr213r, X86::VFMADDSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1752 { X86::VFMADDSDr213r_Int, X86::VFMADDSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1753
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1754 { X86::VFMADDPSr231r, X86::VFMADDPSr231m, TB_ALIGN_NONE },
1755 { X86::VFMADDPDr231r, X86::VFMADDPDr231m, TB_ALIGN_NONE },
1756 { X86::VFMADDPSr132r, X86::VFMADDPSr132m, TB_ALIGN_NONE },
1757 { X86::VFMADDPDr132r, X86::VFMADDPDr132m, TB_ALIGN_NONE },
1758 { X86::VFMADDPSr213r, X86::VFMADDPSr213m, TB_ALIGN_NONE },
1759 { X86::VFMADDPDr213r, X86::VFMADDPDr213m, TB_ALIGN_NONE },
1760 { X86::VFMADDPSr231rY, X86::VFMADDPSr231mY, TB_ALIGN_NONE },
1761 { X86::VFMADDPDr231rY, X86::VFMADDPDr231mY, TB_ALIGN_NONE },
1762 { X86::VFMADDPSr132rY, X86::VFMADDPSr132mY, TB_ALIGN_NONE },
1763 { X86::VFMADDPDr132rY, X86::VFMADDPDr132mY, TB_ALIGN_NONE },
1764 { X86::VFMADDPSr213rY, X86::VFMADDPSr213mY, TB_ALIGN_NONE },
1765 { X86::VFMADDPDr213rY, X86::VFMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1766
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1767 { X86::VFNMADDSSr231r, X86::VFNMADDSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1768 { X86::VFNMADDSSr231r_Int, X86::VFNMADDSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1769 { X86::VFNMADDSDr231r, X86::VFNMADDSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1770 { X86::VFNMADDSDr231r_Int, X86::VFNMADDSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1771 { X86::VFNMADDSSr132r, X86::VFNMADDSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1772 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1773 { X86::VFNMADDSDr132r, X86::VFNMADDSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1774 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1775 { X86::VFNMADDSSr213r, X86::VFNMADDSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1776 { X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1777 { X86::VFNMADDSDr213r, X86::VFNMADDSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1778 { X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1779
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1780 { X86::VFNMADDPSr231r, X86::VFNMADDPSr231m, TB_ALIGN_NONE },
1781 { X86::VFNMADDPDr231r, X86::VFNMADDPDr231m, TB_ALIGN_NONE },
1782 { X86::VFNMADDPSr132r, X86::VFNMADDPSr132m, TB_ALIGN_NONE },
1783 { X86::VFNMADDPDr132r, X86::VFNMADDPDr132m, TB_ALIGN_NONE },
1784 { X86::VFNMADDPSr213r, X86::VFNMADDPSr213m, TB_ALIGN_NONE },
1785 { X86::VFNMADDPDr213r, X86::VFNMADDPDr213m, TB_ALIGN_NONE },
1786 { X86::VFNMADDPSr231rY, X86::VFNMADDPSr231mY, TB_ALIGN_NONE },
1787 { X86::VFNMADDPDr231rY, X86::VFNMADDPDr231mY, TB_ALIGN_NONE },
1788 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr132mY, TB_ALIGN_NONE },
1789 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr132mY, TB_ALIGN_NONE },
1790 { X86::VFNMADDPSr213rY, X86::VFNMADDPSr213mY, TB_ALIGN_NONE },
1791 { X86::VFNMADDPDr213rY, X86::VFNMADDPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1792
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1793 { X86::VFMSUBSSr231r, X86::VFMSUBSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1794 { X86::VFMSUBSSr231r_Int, X86::VFMSUBSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1795 { X86::VFMSUBSDr231r, X86::VFMSUBSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1796 { X86::VFMSUBSDr231r_Int, X86::VFMSUBSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1797 { X86::VFMSUBSSr132r, X86::VFMSUBSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1798 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1799 { X86::VFMSUBSDr132r, X86::VFMSUBSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1800 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1801 { X86::VFMSUBSSr213r, X86::VFMSUBSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1802 { X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1803 { X86::VFMSUBSDr213r, X86::VFMSUBSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1804 { X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr213m_Int, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1805
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1806 { X86::VFMSUBPSr231r, X86::VFMSUBPSr231m, TB_ALIGN_NONE },
1807 { X86::VFMSUBPDr231r, X86::VFMSUBPDr231m, TB_ALIGN_NONE },
1808 { X86::VFMSUBPSr132r, X86::VFMSUBPSr132m, TB_ALIGN_NONE },
1809 { X86::VFMSUBPDr132r, X86::VFMSUBPDr132m, TB_ALIGN_NONE },
1810 { X86::VFMSUBPSr213r, X86::VFMSUBPSr213m, TB_ALIGN_NONE },
1811 { X86::VFMSUBPDr213r, X86::VFMSUBPDr213m, TB_ALIGN_NONE },
1812 { X86::VFMSUBPSr231rY, X86::VFMSUBPSr231mY, TB_ALIGN_NONE },
1813 { X86::VFMSUBPDr231rY, X86::VFMSUBPDr231mY, TB_ALIGN_NONE },
1814 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr132mY, TB_ALIGN_NONE },
1815 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr132mY, TB_ALIGN_NONE },
1816 { X86::VFMSUBPSr213rY, X86::VFMSUBPSr213mY, TB_ALIGN_NONE },
1817 { X86::VFMSUBPDr213rY, X86::VFMSUBPDr213mY, TB_ALIGN_NONE },
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1818
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1819 { X86::VFNMSUBSSr231r, X86::VFNMSUBSSr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1820 { X86::VFNMSUBSSr231r_Int, X86::VFNMSUBSSr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1821 { X86::VFNMSUBSDr231r, X86::VFNMSUBSDr231m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1822 { X86::VFNMSUBSDr231r_Int, X86::VFNMSUBSDr231m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1823 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1824 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1825 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr132m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1826 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr132m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1827 { X86::VFNMSUBSSr213r, X86::VFNMSUBSSr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1828 { X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr213m_Int, TB_ALIGN_NONE },
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1829 { X86::VFNMSUBSDr213r, X86::VFNMSUBSDr213m, TB_ALIGN_NONE },
Andrew Kaylore41a8c42015-11-04 18:10:41 +0000[diff] [blame]1830 { X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr213m_Int, TB_ALIGN_NONE },
Craig Topper2e127b52012-06-01 05:48:39 +0000[diff] [blame]1831
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1832 { X86::VFNMSUBPSr231r, X86::VFNMSUBPSr231m, TB_ALIGN_NONE },
1833 { X86::VFNMSUBPDr231r, X86::VFNMSUBPDr231m, TB_ALIGN_NONE },
1834 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr132m, TB_ALIGN_NONE },
1835 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr132m, TB_ALIGN_NONE },
1836 { X86::VFNMSUBPSr213r, X86::VFNMSUBPSr213m, TB_ALIGN_NONE },
1837 { X86::VFNMSUBPDr213r, X86::VFNMSUBPDr213m, TB_ALIGN_NONE },
1838 { X86::VFNMSUBPSr231rY, X86::VFNMSUBPSr231mY, TB_ALIGN_NONE },
1839 { X86::VFNMSUBPDr231rY, X86::VFNMSUBPDr231mY, TB_ALIGN_NONE },
1840 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr132mY, TB_ALIGN_NONE },
1841 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr132mY, TB_ALIGN_NONE },
1842 { X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr213mY, TB_ALIGN_NONE },
1843 { X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1844
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1845 { X86::VFMADDSUBPSr231r, X86::VFMADDSUBPSr231m, TB_ALIGN_NONE },
1846 { X86::VFMADDSUBPDr231r, X86::VFMADDSUBPDr231m, TB_ALIGN_NONE },
1847 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr132m, TB_ALIGN_NONE },
1848 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr132m, TB_ALIGN_NONE },
1849 { X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr213m, TB_ALIGN_NONE },
1850 { X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr213m, TB_ALIGN_NONE },
1851 { X86::VFMADDSUBPSr231rY, X86::VFMADDSUBPSr231mY, TB_ALIGN_NONE },
1852 { X86::VFMADDSUBPDr231rY, X86::VFMADDSUBPDr231mY, TB_ALIGN_NONE },
1853 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr132mY, TB_ALIGN_NONE },
1854 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr132mY, TB_ALIGN_NONE },
1855 { X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr213mY, TB_ALIGN_NONE },
1856 { X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr213mY, TB_ALIGN_NONE },
Craig Topper3cb14302012-06-04 07:08:21 +0000[diff] [blame]1857
Lang Hamesc2c75132014-04-02 22:06:16 +0000[diff] [blame]1858 { X86::VFMSUBADDPSr231r, X86::VFMSUBADDPSr231m, TB_ALIGN_NONE },
1859 { X86::VFMSUBADDPDr231r, X86::VFMSUBADDPDr231m, TB_ALIGN_NONE },
1860 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr132m, TB_ALIGN_NONE },
1861 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr132m, TB_ALIGN_NONE },
1862 { X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr213m, TB_ALIGN_NONE },
1863 { X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr213m, TB_ALIGN_NONE },
1864 { X86::VFMSUBADDPSr231rY, X86::VFMSUBADDPSr231mY, TB_ALIGN_NONE },
1865 { X86::VFMSUBADDPDr231rY, X86::VFMSUBADDPDr231mY, TB_ALIGN_NONE },
1866 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr132mY, TB_ALIGN_NONE },
1867 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr132mY, TB_ALIGN_NONE },
1868 { X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr213mY, TB_ALIGN_NONE },
1869 { X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr213mY, TB_ALIGN_NONE },
Craig Topper908e6852012-08-31 23:10:34 +0000[diff] [blame]1870
1871 // FMA4 foldable patterns
Simon Pilgrim616fe502015-06-22 21:49:41 +0000[diff] [blame]1872 { X86::VFMADDSS4rr, X86::VFMADDSS4rm, TB_ALIGN_NONE },
1873 { X86::VFMADDSD4rr, X86::VFMADDSD4rm, TB_ALIGN_NONE },
1874 { X86::VFMADDPS4rr, X86::VFMADDPS4rm, TB_ALIGN_NONE },
1875 { X86::VFMADDPD4rr, X86::VFMADDPD4rm, TB_ALIGN_NONE },
1876 { X86::VFMADDPS4rrY, X86::VFMADDPS4rmY, TB_ALIGN_NONE },
1877 { X86::VFMADDPD4rrY, X86::VFMADDPD4rmY, TB_ALIGN_NONE },
1878 { X86::VFNMADDSS4rr, X86::VFNMADDSS4rm, TB_ALIGN_NONE },
1879 { X86::VFNMADDSD4rr, X86::VFNMADDSD4rm, TB_ALIGN_NONE },
1880 { X86::VFNMADDPS4rr, X86::VFNMADDPS4rm, TB_ALIGN_NONE },
1881 { X86::VFNMADDPD4rr, X86::VFNMADDPD4rm, TB_ALIGN_NONE },
1882 { X86::VFNMADDPS4rrY, X86::VFNMADDPS4rmY, TB_ALIGN_NONE },
1883 { X86::VFNMADDPD4rrY, X86::VFNMADDPD4rmY, TB_ALIGN_NONE },
1884 { X86::VFMSUBSS4rr, X86::VFMSUBSS4rm, TB_ALIGN_NONE },
1885 { X86::VFMSUBSD4rr, X86::VFMSUBSD4rm, TB_ALIGN_NONE },
1886 { X86::VFMSUBPS4rr, X86::VFMSUBPS4rm, TB_ALIGN_NONE },
1887 { X86::VFMSUBPD4rr, X86::VFMSUBPD4rm, TB_ALIGN_NONE },
1888 { X86::VFMSUBPS4rrY, X86::VFMSUBPS4rmY, TB_ALIGN_NONE },
1889 { X86::VFMSUBPD4rrY, X86::VFMSUBPD4rmY, TB_ALIGN_NONE },
1890 { X86::VFNMSUBSS4rr, X86::VFNMSUBSS4rm, TB_ALIGN_NONE },
1891 { X86::VFNMSUBSD4rr, X86::VFNMSUBSD4rm, TB_ALIGN_NONE },
1892 { X86::VFNMSUBPS4rr, X86::VFNMSUBPS4rm, TB_ALIGN_NONE },
1893 { X86::VFNMSUBPD4rr, X86::VFNMSUBPD4rm, TB_ALIGN_NONE },
1894 { X86::VFNMSUBPS4rrY, X86::VFNMSUBPS4rmY, TB_ALIGN_NONE },
1895 { X86::VFNMSUBPD4rrY, X86::VFNMSUBPD4rmY, TB_ALIGN_NONE },
1896 { X86::VFMADDSUBPS4rr, X86::VFMADDSUBPS4rm, TB_ALIGN_NONE },
1897 { X86::VFMADDSUBPD4rr, X86::VFMADDSUBPD4rm, TB_ALIGN_NONE },
1898 { X86::VFMADDSUBPS4rrY, X86::VFMADDSUBPS4rmY, TB_ALIGN_NONE },
1899 { X86::VFMADDSUBPD4rrY, X86::VFMADDSUBPD4rmY, TB_ALIGN_NONE },
1900 { X86::VFMSUBADDPS4rr, X86::VFMSUBADDPS4rm, TB_ALIGN_NONE },
1901 { X86::VFMSUBADDPD4rr, X86::VFMSUBADDPD4rm, TB_ALIGN_NONE },
1902 { X86::VFMSUBADDPS4rrY, X86::VFMSUBADDPS4rmY, TB_ALIGN_NONE },
1903 { X86::VFMSUBADDPD4rrY, X86::VFMSUBADDPD4rmY, TB_ALIGN_NONE },
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]1904
1905 // XOP foldable instructions
1906 { X86::VPCMOVrr, X86::VPCMOVrm, 0 },
1907 { X86::VPCMOVrrY, X86::VPCMOVrmY, 0 },
1908 { X86::VPERMIL2PDrr, X86::VPERMIL2PDrm, 0 },
1909 { X86::VPERMIL2PDrrY, X86::VPERMIL2PDrmY, 0 },
1910 { X86::VPERMIL2PSrr, X86::VPERMIL2PSrm, 0 },
1911 { X86::VPERMIL2PSrrY, X86::VPERMIL2PSrmY, 0 },
1912 { X86::VPPERMrr, X86::VPPERMrm, 0 },
1913
Elena Demikhovsky2e408ae2013-10-06 13:11:09 +0000[diff] [blame]1914 // AVX-512 VPERMI instructions with 3 source operands.
1915 { X86::VPERMI2Drr, X86::VPERMI2Drm, 0 },
1916 { X86::VPERMI2Qrr, X86::VPERMI2Qrm, 0 },
1917 { X86::VPERMI2PSrr, X86::VPERMI2PSrm, 0 },
1918 { X86::VPERMI2PDrr, X86::VPERMI2PDrm, 0 },
Elena Demikhovsky172a27c2014-01-08 10:54:22 +0000[diff] [blame]1919 { X86::VBLENDMPDZrr, X86::VBLENDMPDZrm, 0 },
1920 { X86::VBLENDMPSZrr, X86::VBLENDMPSZrm, 0 },
1921 { X86::VPBLENDMDZrr, X86::VPBLENDMDZrm, 0 },
Robert Khasanov8e8c3992014-12-09 18:45:30 +0000[diff] [blame]1922 { X86::VPBLENDMQZrr, X86::VPBLENDMQZrm, 0 },
1923 { X86::VBROADCASTSSZrk, X86::VBROADCASTSSZmk, TB_NO_REVERSE },
1924 { X86::VBROADCASTSDZrk, X86::VBROADCASTSDZmk, TB_NO_REVERSE },
1925 { X86::VBROADCASTSSZ256rk, X86::VBROADCASTSSZ256mk, TB_NO_REVERSE },
1926 { X86::VBROADCASTSDZ256rk, X86::VBROADCASTSDZ256mk, TB_NO_REVERSE },
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1927 { X86::VBROADCASTSSZ128rk, X86::VBROADCASTSSZ128mk, TB_NO_REVERSE },
1928 // AVX-512 arithmetic instructions
1929 { X86::VADDPSZrrkz, X86::VADDPSZrmkz, 0 },
1930 { X86::VADDPDZrrkz, X86::VADDPDZrmkz, 0 },
1931 { X86::VSUBPSZrrkz, X86::VSUBPSZrmkz, 0 },
1932 { X86::VSUBPDZrrkz, X86::VSUBPDZrmkz, 0 },
1933 { X86::VMULPSZrrkz, X86::VMULPSZrmkz, 0 },
1934 { X86::VMULPDZrrkz, X86::VMULPDZrmkz, 0 },
1935 { X86::VDIVPSZrrkz, X86::VDIVPSZrmkz, 0 },
1936 { X86::VDIVPDZrrkz, X86::VDIVPDZrmkz, 0 },
1937 { X86::VMINPSZrrkz, X86::VMINPSZrmkz, 0 },
1938 { X86::VMINPDZrrkz, X86::VMINPDZrmkz, 0 },
1939 { X86::VMAXPSZrrkz, X86::VMAXPSZrmkz, 0 },
1940 { X86::VMAXPDZrrkz, X86::VMAXPDZrmkz, 0 },
1941 // AVX-512{F,VL} arithmetic instructions 256-bit
1942 { X86::VADDPSZ256rrkz, X86::VADDPSZ256rmkz, 0 },
1943 { X86::VADDPDZ256rrkz, X86::VADDPDZ256rmkz, 0 },
1944 { X86::VSUBPSZ256rrkz, X86::VSUBPSZ256rmkz, 0 },
1945 { X86::VSUBPDZ256rrkz, X86::VSUBPDZ256rmkz, 0 },
1946 { X86::VMULPSZ256rrkz, X86::VMULPSZ256rmkz, 0 },
1947 { X86::VMULPDZ256rrkz, X86::VMULPDZ256rmkz, 0 },
1948 { X86::VDIVPSZ256rrkz, X86::VDIVPSZ256rmkz, 0 },
1949 { X86::VDIVPDZ256rrkz, X86::VDIVPDZ256rmkz, 0 },
1950 { X86::VMINPSZ256rrkz, X86::VMINPSZ256rmkz, 0 },
1951 { X86::VMINPDZ256rrkz, X86::VMINPDZ256rmkz, 0 },
1952 { X86::VMAXPSZ256rrkz, X86::VMAXPSZ256rmkz, 0 },
1953 { X86::VMAXPDZ256rrkz, X86::VMAXPDZ256rmkz, 0 },
1954 // AVX-512{F,VL} arithmetic instructions 128-bit
1955 { X86::VADDPSZ128rrkz, X86::VADDPSZ128rmkz, 0 },
1956 { X86::VADDPDZ128rrkz, X86::VADDPDZ128rmkz, 0 },
1957 { X86::VSUBPSZ128rrkz, X86::VSUBPSZ128rmkz, 0 },
1958 { X86::VSUBPDZ128rrkz, X86::VSUBPDZ128rmkz, 0 },
1959 { X86::VMULPSZ128rrkz, X86::VMULPSZ128rmkz, 0 },
1960 { X86::VMULPDZ128rrkz, X86::VMULPDZ128rmkz, 0 },
1961 { X86::VDIVPSZ128rrkz, X86::VDIVPSZ128rmkz, 0 },
1962 { X86::VDIVPDZ128rrkz, X86::VDIVPDZ128rmkz, 0 },
1963 { X86::VMINPSZ128rrkz, X86::VMINPSZ128rmkz, 0 },
1964 { X86::VMINPDZ128rrkz, X86::VMINPDZ128rmkz, 0 },
1965 { X86::VMAXPSZ128rrkz, X86::VMAXPSZ128rmkz, 0 },
1966 { X86::VMAXPDZ128rrkz, X86::VMAXPDZ128rmkz, 0 }
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1967 };
1968
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1969 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable3) {
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1970 AddTableEntry(RegOp2MemOpTable3, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1971 Entry.RegOp, Entry.MemOp,
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1972 // Index 3, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]1973 Entry.Flags | TB_INDEX_3 | TB_FOLDED_LOAD);
Elena Demikhovsky602f3a22012-05-31 09:20:20 +0000[diff] [blame]1974 }
1975
Sanjay Patele951a382015-02-17 22:38:06 +0000[diff] [blame]1976 static const X86MemoryFoldTableEntry MemoryFoldTable4[] = {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]1977 // AVX-512 foldable instructions
1978 { X86::VADDPSZrrk, X86::VADDPSZrmk, 0 },
1979 { X86::VADDPDZrrk, X86::VADDPDZrmk, 0 },
1980 { X86::VSUBPSZrrk, X86::VSUBPSZrmk, 0 },
1981 { X86::VSUBPDZrrk, X86::VSUBPDZrmk, 0 },
1982 { X86::VMULPSZrrk, X86::VMULPSZrmk, 0 },
1983 { X86::VMULPDZrrk, X86::VMULPDZrmk, 0 },
1984 { X86::VDIVPSZrrk, X86::VDIVPSZrmk, 0 },
1985 { X86::VDIVPDZrrk, X86::VDIVPDZrmk, 0 },
1986 { X86::VMINPSZrrk, X86::VMINPSZrmk, 0 },
1987 { X86::VMINPDZrrk, X86::VMINPDZrmk, 0 },
1988 { X86::VMAXPSZrrk, X86::VMAXPSZrmk, 0 },
1989 { X86::VMAXPDZrrk, X86::VMAXPDZrmk, 0 },
1990 // AVX-512{F,VL} foldable instructions 256-bit
1991 { X86::VADDPSZ256rrk, X86::VADDPSZ256rmk, 0 },
1992 { X86::VADDPDZ256rrk, X86::VADDPDZ256rmk, 0 },
1993 { X86::VSUBPSZ256rrk, X86::VSUBPSZ256rmk, 0 },
1994 { X86::VSUBPDZ256rrk, X86::VSUBPDZ256rmk, 0 },
1995 { X86::VMULPSZ256rrk, X86::VMULPSZ256rmk, 0 },
1996 { X86::VMULPDZ256rrk, X86::VMULPDZ256rmk, 0 },
1997 { X86::VDIVPSZ256rrk, X86::VDIVPSZ256rmk, 0 },
1998 { X86::VDIVPDZ256rrk, X86::VDIVPDZ256rmk, 0 },
1999 { X86::VMINPSZ256rrk, X86::VMINPSZ256rmk, 0 },
2000 { X86::VMINPDZ256rrk, X86::VMINPDZ256rmk, 0 },
2001 { X86::VMAXPSZ256rrk, X86::VMAXPSZ256rmk, 0 },
2002 { X86::VMAXPDZ256rrk, X86::VMAXPDZ256rmk, 0 },
2003 // AVX-512{F,VL} foldable instructions 128-bit
2004 { X86::VADDPSZ128rrk, X86::VADDPSZ128rmk, 0 },
2005 { X86::VADDPDZ128rrk, X86::VADDPDZ128rmk, 0 },
2006 { X86::VSUBPSZ128rrk, X86::VSUBPSZ128rmk, 0 },
2007 { X86::VSUBPDZ128rrk, X86::VSUBPDZ128rmk, 0 },
2008 { X86::VMULPSZ128rrk, X86::VMULPSZ128rmk, 0 },
2009 { X86::VMULPDZ128rrk, X86::VMULPDZ128rmk, 0 },
2010 { X86::VDIVPSZ128rrk, X86::VDIVPSZ128rmk, 0 },
2011 { X86::VDIVPDZ128rrk, X86::VDIVPDZ128rmk, 0 },
2012 { X86::VMINPSZ128rrk, X86::VMINPSZ128rmk, 0 },
2013 { X86::VMINPDZ128rrk, X86::VMINPDZ128rmk, 0 },
2014 { X86::VMAXPSZ128rrk, X86::VMAXPSZ128rmk, 0 },
2015 { X86::VMAXPDZ128rrk, X86::VMAXPDZ128rmk, 0 }
2016 };
2017
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2018 for (X86MemoryFoldTableEntry Entry : MemoryFoldTable4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2019 AddTableEntry(RegOp2MemOpTable4, MemOp2RegOpTable,
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2020 Entry.RegOp, Entry.MemOp,
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2021 // Index 4, folded load
Sanjay Patelcf0a8072015-07-07 15:03:53 +0000[diff] [blame]2022 Entry.Flags | TB_INDEX_4 | TB_FOLDED_LOAD);
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]2023 }
Chris Lattnerd92fb002002-10-25 22:55:53 +0000[diff] [blame]2024}
2025
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]2026void
2027X86InstrInfo::AddTableEntry(RegOp2MemOpTableType &R2MTable,
2028 MemOp2RegOpTableType &M2RTable,
2029 unsigned RegOp, unsigned MemOp, unsigned Flags) {
2030 if ((Flags & TB_NO_FORWARD) == 0) {
2031 assert(!R2MTable.count(RegOp) && "Duplicate entry!");
2032 R2MTable[RegOp] = std::make_pair(MemOp, Flags);
2033 }
2034 if ((Flags & TB_NO_REVERSE) == 0) {
2035 assert(!M2RTable.count(MemOp) &&
2036 "Duplicated entries in unfolding maps?");
2037 M2RTable[MemOp] = std::make_pair(RegOp, Flags);
2038 }
2039}
2040
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2041bool
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2042X86InstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
2043 unsigned &SrcReg, unsigned &DstReg,
2044 unsigned &SubIdx) const {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2045 switch (MI.getOpcode()) {
2046 default: break;
2047 case X86::MOVSX16rr8:
2048 case X86::MOVZX16rr8:
2049 case X86::MOVSX32rr8:
2050 case X86::MOVZX32rr8:
2051 case X86::MOVSX64rr8:
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2052 if (!Subtarget.is64Bit())
Evan Chengceb5a4e2010-01-13 08:01:32 +0000[diff] [blame]2053 // It's not always legal to reference the low 8-bit of the larger
2054 // register in 32-bit mode.
2055 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2056 case X86::MOVSX32rr16:
2057 case X86::MOVZX32rr16:
2058 case X86::MOVSX64rr16:
Tim Northover04eb4232013-05-30 10:43:18 +0000[diff] [blame]2059 case X86::MOVSX64rr32: {
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2060 if (MI.getOperand(0).getSubReg() || MI.getOperand(1).getSubReg())
2061 // Be conservative.
2062 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2063 SrcReg = MI.getOperand(1).getReg();
2064 DstReg = MI.getOperand(0).getReg();
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2065 switch (MI.getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2066 default: llvm_unreachable("Unreachable!");
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2067 case X86::MOVSX16rr8:
2068 case X86::MOVZX16rr8:
2069 case X86::MOVSX32rr8:
2070 case X86::MOVZX32rr8:
2071 case X86::MOVSX64rr8:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2072 SubIdx = X86::sub_8bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2073 break;
2074 case X86::MOVSX32rr16:
2075 case X86::MOVZX32rr16:
2076 case X86::MOVSX64rr16:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2077 SubIdx = X86::sub_16bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2078 break;
2079 case X86::MOVSX64rr32:
Jakob Stoklund Olesen396c8802010-05-25 17:04:16 +0000[diff] [blame]2080 SubIdx = X86::sub_32bit;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2081 break;
2082 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2083 return true;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2084 }
2085 }
Evan Cheng30bebff2010-01-13 00:30:23 +0000[diff] [blame]2086 return false;
Evan Cheng42166152010-01-12 00:09:37 +0000[diff] [blame]2087}
2088
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2089int X86InstrInfo::getSPAdjust(const MachineInstr *MI) const {
2090 const MachineFunction *MF = MI->getParent()->getParent();
2091 const TargetFrameLowering *TFI = MF->getSubtarget().getFrameLowering();
2092
2093 if (MI->getOpcode() == getCallFrameSetupOpcode() ||
2094 MI->getOpcode() == getCallFrameDestroyOpcode()) {
2095 unsigned StackAlign = TFI->getStackAlignment();
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2096 int SPAdj = (MI->getOperand(0).getImm() + StackAlign - 1) / StackAlign *
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2097 StackAlign;
2098
2099 SPAdj -= MI->getOperand(1).getImm();
2100
2101 if (MI->getOpcode() == getCallFrameSetupOpcode())
2102 return SPAdj;
2103 else
2104 return -SPAdj;
2105 }
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2106
2107 // To know whether a call adjusts the stack, we need information
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2108 // that is bound to the following ADJCALLSTACKUP pseudo.
2109 // Look for the next ADJCALLSTACKUP that follows the call.
2110 if (MI->isCall()) {
2111 const MachineBasicBlock* MBB = MI->getParent();
2112 auto I = ++MachineBasicBlock::const_iterator(MI);
2113 for (auto E = MBB->end(); I != E; ++I) {
2114 if (I->getOpcode() == getCallFrameDestroyOpcode() ||
2115 I->isCall())
2116 break;
2117 }
2118
2119 // If we could not find a frame destroy opcode, then it has already
2120 // been simplified, so we don't care.
2121 if (I->getOpcode() != getCallFrameDestroyOpcode())
2122 return 0;
2123
2124 return -(I->getOperand(1).getImm());
2125 }
2126
2127 // Currently handle only PUSHes we can reasonably expect to see
2128 // in call sequences
2129 switch (MI->getOpcode()) {
Simon Pilgrimcd322542015-02-10 12:57:17 +0000[diff] [blame]2130 default:
Michael Kuperstein13fbd452015-02-01 16:56:04 +0000[diff] [blame]2131 return 0;
2132 case X86::PUSH32i8:
2133 case X86::PUSH32r:
2134 case X86::PUSH32rmm:
2135 case X86::PUSH32rmr:
2136 case X86::PUSHi32:
2137 return 4;
2138 }
2139}
2140
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2141/// Return true and the FrameIndex if the specified
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2142/// operand and follow operands form a reference to the stack frame.
2143bool X86InstrInfo::isFrameOperand(const MachineInstr *MI, unsigned int Op,
2144 int &FrameIndex) const {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2145 if (MI->getOperand(Op+X86::AddrBaseReg).isFI() &&
2146 MI->getOperand(Op+X86::AddrScaleAmt).isImm() &&
2147 MI->getOperand(Op+X86::AddrIndexReg).isReg() &&
2148 MI->getOperand(Op+X86::AddrDisp).isImm() &&
2149 MI->getOperand(Op+X86::AddrScaleAmt).getImm() == 1 &&
2150 MI->getOperand(Op+X86::AddrIndexReg).getReg() == 0 &&
2151 MI->getOperand(Op+X86::AddrDisp).getImm() == 0) {
2152 FrameIndex = MI->getOperand(Op+X86::AddrBaseReg).getIndex();
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2153 return true;
2154 }
2155 return false;
2156}
2157
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2158static bool isFrameLoadOpcode(int Opcode) {
2159 switch (Opcode) {
David Blaikie46a9f012012-01-20 21:51:11 +0000[diff] [blame]2160 default:
2161 return false;
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2162 case X86::MOV8rm:
2163 case X86::MOV16rm:
2164 case X86::MOV32rm:
Evan Cheng11b0a5d2006-09-08 06:48:29 +0000[diff] [blame]2165 case X86::MOV64rm:
Dale Johannesen3d7008c2007-07-04 21:07:47 +0000[diff] [blame]2166 case X86::LD_Fp64m:
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2167 case X86::MOVSSrm:
2168 case X86::MOVSDrm:
Chris Lattnerbfc2c682006-04-18 16:44:51 +0000[diff] [blame]2169 case X86::MOVAPSrm:
2170 case X86::MOVAPDrm:
Dan Gohmanbdc0f8b2009-01-09 02:40:34 +0000[diff] [blame]2171 case X86::MOVDQArm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2172 case X86::VMOVSSrm:
2173 case X86::VMOVSDrm:
2174 case X86::VMOVAPSrm:
2175 case X86::VMOVAPDrm:
2176 case X86::VMOVDQArm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2177 case X86::VMOVUPSYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2178 case X86::VMOVAPSYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2179 case X86::VMOVUPDYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2180 case X86::VMOVAPDYrm:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2181 case X86::VMOVDQUYrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2182 case X86::VMOVDQAYrm:
Bill Wendlinge7b2a862007-04-03 06:00:37 +0000[diff] [blame]2183 case X86::MMX_MOVD64rm:
2184 case X86::MMX_MOVQ64rm:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2185 case X86::VMOVAPSZrm:
2186 case X86::VMOVUPSZrm:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2187 return true;
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2188 }
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2189}
2190
2191static bool isFrameStoreOpcode(int Opcode) {
2192 switch (Opcode) {
2193 default: break;
2194 case X86::MOV8mr:
2195 case X86::MOV16mr:
2196 case X86::MOV32mr:
2197 case X86::MOV64mr:
2198 case X86::ST_FpP64m:
2199 case X86::MOVSSmr:
2200 case X86::MOVSDmr:
2201 case X86::MOVAPSmr:
2202 case X86::MOVAPDmr:
2203 case X86::MOVDQAmr:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]2204 case X86::VMOVSSmr:
2205 case X86::VMOVSDmr:
2206 case X86::VMOVAPSmr:
2207 case X86::VMOVAPDmr:
2208 case X86::VMOVDQAmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2209 case X86::VMOVUPSYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2210 case X86::VMOVAPSYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2211 case X86::VMOVUPDYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2212 case X86::VMOVAPDYmr:
Simon Pilgrim9c1e4122014-11-18 23:38:19 +0000[diff] [blame]2213 case X86::VMOVDQUYmr:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]2214 case X86::VMOVDQAYmr:
Elena Demikhovskya5d38a32014-01-23 14:27:26 +0000[diff] [blame]2215 case X86::VMOVUPSZmr:
2216 case X86::VMOVAPSZmr:
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2217 case X86::MMX_MOVD64mr:
2218 case X86::MMX_MOVQ64mr:
2219 case X86::MMX_MOVNTQmr:
2220 return true;
2221 }
2222 return false;
2223}
2224
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2225unsigned X86InstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2226 int &FrameIndex) const {
2227 if (isFrameLoadOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2228 if (MI->getOperand(0).getSubReg() == 0 && isFrameOperand(MI, 1, FrameIndex))
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2229 return MI->getOperand(0).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2230 return 0;
2231}
2232
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2233unsigned X86InstrInfo::isLoadFromStackSlotPostFE(const MachineInstr *MI,
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2234 int &FrameIndex) const {
2235 if (isFrameLoadOpcode(MI->getOpcode())) {
2236 unsigned Reg;
2237 if ((Reg = isLoadFromStackSlot(MI, FrameIndex)))
2238 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2239 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2240 const MachineMemOperand *Dummy;
2241 return hasLoadFromStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2242 }
2243 return 0;
2244}
2245
Dan Gohman0b273252008-11-18 19:49:32 +0000[diff] [blame]2246unsigned X86InstrInfo::isStoreToStackSlot(const MachineInstr *MI,
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2247 int &FrameIndex) const {
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2248 if (isFrameStoreOpcode(MI->getOpcode()))
Jakob Stoklund Olesen96a890a2010-07-27 04:17:01 +0000[diff] [blame]2249 if (MI->getOperand(X86::AddrNumOperands).getSubReg() == 0 &&
2250 isFrameOperand(MI, 0, FrameIndex))
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]2251 return MI->getOperand(X86::AddrNumOperands).getReg();
David Greene2f4c3742009-11-13 00:29:53 +0000[diff] [blame]2252 return 0;
2253}
2254
2255unsigned X86InstrInfo::isStoreToStackSlotPostFE(const MachineInstr *MI,
2256 int &FrameIndex) const {
2257 if (isFrameStoreOpcode(MI->getOpcode())) {
2258 unsigned Reg;
2259 if ((Reg = isStoreToStackSlot(MI, FrameIndex)))
2260 return Reg;
David Greene70fdd572009-11-12 20:55:29 +0000[diff] [blame]2261 // Check for post-frame index elimination operations
David Greene0508e432009-12-04 22:38:46 +0000[diff] [blame]2262 const MachineMemOperand *Dummy;
2263 return hasStoreToStackSlot(MI, Dummy, FrameIndex);
Chris Lattnerbb53acd2006-02-02 20:12:32 +0000[diff] [blame]2264 }
2265 return 0;
2266}
2267
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2268/// Return true if register is PIC base; i.e.g defined by X86::MOVPC32r.
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2269static bool regIsPICBase(unsigned BaseReg, const MachineRegisterInfo &MRI) {
Jakob Stoklund Olesen3b9a4422012-08-08 00:40:47 +0000[diff] [blame]2270 // Don't waste compile time scanning use-def chains of physregs.
2271 if (!TargetRegisterInfo::isVirtualRegister(BaseReg))
2272 return false;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2273 bool isPICBase = false;
Owen Anderson16c6bf42014-03-13 23:12:04 +0000[diff] [blame]2274 for (MachineRegisterInfo::def_instr_iterator I = MRI.def_instr_begin(BaseReg),
2275 E = MRI.def_instr_end(); I != E; ++I) {
2276 MachineInstr *DefMI = &*I;
Evan Cheng308e5642008-03-27 01:45:11 +0000[diff] [blame]2277 if (DefMI->getOpcode() != X86::MOVPC32r)
2278 return false;
2279 assert(!isPICBase && "More than one PIC base?");
2280 isPICBase = true;
2281 }
2282 return isPICBase;
2283}
Evan Cheng1973a462008-03-31 07:54:19 +0000[diff] [blame]2284
Bill Wendling1e117682008-05-12 20:54:26 +0000[diff] [blame]2285bool
Dan Gohmane919de52009-10-10 00:34:18 +0000[diff] [blame]2286X86InstrInfo::isReallyTriviallyReMaterializable(const MachineInstr *MI,
2287 AliasAnalysis *AA) const {
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2288 switch (MI->getOpcode()) {
2289 default: break;
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2290 case X86::MOV8rm:
2291 case X86::MOV16rm:
2292 case X86::MOV32rm:
2293 case X86::MOV64rm:
2294 case X86::LD_Fp64m:
2295 case X86::MOVSSrm:
2296 case X86::MOVSDrm:
2297 case X86::MOVAPSrm:
2298 case X86::MOVUPSrm:
2299 case X86::MOVAPDrm:
2300 case X86::MOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2301 case X86::MOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2302 case X86::VMOVSSrm:
2303 case X86::VMOVSDrm:
2304 case X86::VMOVAPSrm:
2305 case X86::VMOVUPSrm:
2306 case X86::VMOVAPDrm:
2307 case X86::VMOVDQArm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2308 case X86::VMOVDQUrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2309 case X86::VMOVAPSYrm:
2310 case X86::VMOVUPSYrm:
2311 case X86::VMOVAPDYrm:
2312 case X86::VMOVDQAYrm:
Craig Topper922f10a2012-12-06 06:49:16 +0000[diff] [blame]2313 case X86::VMOVDQUYrm:
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2314 case X86::MMX_MOVD64rm:
2315 case X86::MMX_MOVQ64rm:
2316 case X86::FsVMOVAPSrm:
2317 case X86::FsVMOVAPDrm:
2318 case X86::FsMOVAPSrm:
Igor Bregerf8e461f2015-10-26 08:37:12 +0000[diff] [blame]2319 case X86::FsMOVAPDrm:
2320 // AVX-512
2321 case X86::VMOVAPDZ128rm:
2322 case X86::VMOVAPDZ256rm:
2323 case X86::VMOVAPDZrm:
2324 case X86::VMOVAPSZ128rm:
2325 case X86::VMOVAPSZ256rm:
2326 case X86::VMOVAPSZrm:
2327 case X86::VMOVDQA32Z128rm:
2328 case X86::VMOVDQA32Z256rm:
2329 case X86::VMOVDQA32Zrm:
2330 case X86::VMOVDQA64Z128rm:
2331 case X86::VMOVDQA64Z256rm:
2332 case X86::VMOVDQA64Zrm:
2333 case X86::VMOVDQU16Z128rm:
2334 case X86::VMOVDQU16Z256rm:
2335 case X86::VMOVDQU16Zrm:
2336 case X86::VMOVDQU32Z128rm:
2337 case X86::VMOVDQU32Z256rm:
2338 case X86::VMOVDQU32Zrm:
2339 case X86::VMOVDQU64Z128rm:
2340 case X86::VMOVDQU64Z256rm:
2341 case X86::VMOVDQU64Zrm:
2342 case X86::VMOVDQU8Z128rm:
2343 case X86::VMOVDQU8Z256rm:
2344 case X86::VMOVDQU8Zrm:
2345 case X86::VMOVUPSZ128rm:
2346 case X86::VMOVUPSZ256rm:
2347 case X86::VMOVUPSZrm: {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2348 // Loads from constant pools are trivially rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2349 if (MI->getOperand(1+X86::AddrBaseReg).isReg() &&
2350 MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2351 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2352 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2353 MI->isInvariantLoad(AA)) {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2354 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2355 if (BaseReg == 0 || BaseReg == X86::RIP)
2356 return true;
2357 // Allow re-materialization of PIC load.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2358 if (!ReMatPICStubLoad && MI->getOperand(1+X86::AddrDisp).isGlobal())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2359 return false;
2360 const MachineFunction &MF = *MI->getParent()->getParent();
2361 const MachineRegisterInfo &MRI = MF.getRegInfo();
2362 return regIsPICBase(BaseReg, MRI);
Evan Cheng94ba37f2008-02-22 09:25:47 +0000[diff] [blame]2363 }
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2364 return false;
2365 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2366
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2367 case X86::LEA32r:
2368 case X86::LEA64r: {
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2369 if (MI->getOperand(1+X86::AddrScaleAmt).isImm() &&
2370 MI->getOperand(1+X86::AddrIndexReg).isReg() &&
2371 MI->getOperand(1+X86::AddrIndexReg).getReg() == 0 &&
2372 !MI->getOperand(1+X86::AddrDisp).isReg()) {
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2373 // lea fi#, lea GV, etc. are all rematerializable.
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2374 if (!MI->getOperand(1+X86::AddrBaseReg).isReg())
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2375 return true;
Craig Topper646f64f2014-05-06 07:04:32 +0000[diff] [blame]2376 unsigned BaseReg = MI->getOperand(1+X86::AddrBaseReg).getReg();
Craig Toppera0cabf12012-08-21 08:17:07 +0000[diff] [blame]2377 if (BaseReg == 0)
2378 return true;
2379 // Allow re-materialization of lea PICBase + x.
2380 const MachineFunction &MF = *MI->getParent()->getParent();
2381 const MachineRegisterInfo &MRI = MF.getRegInfo();
2382 return regIsPICBase(BaseReg, MRI);
2383 }
2384 return false;
2385 }
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2386 }
Evan Cheng29e62a52008-03-27 01:41:09 +0000[diff] [blame]2387
Dan Gohmane8c1e422007-06-26 00:48:07 +0000[diff] [blame]2388 // All other instructions marked M_REMATERIALIZABLE are always trivially
2389 // rematerializable.
2390 return true;
Dan Gohman4a4a8eb2007-06-14 20:50:44 +0000[diff] [blame]2391}
2392
Alexey Volkov6226de62014-05-20 08:55:50 +0000[diff] [blame]2393bool X86InstrInfo::isSafeToClobberEFLAGS(MachineBasicBlock &MBB,
2394 MachineBasicBlock::iterator I) const {
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2395 MachineBasicBlock::iterator E = MBB.end();
2396
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2397 // For compile time consideration, if we are not able to determine the
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2398 // safety after visiting 4 instructions in each direction, we will assume
2399 // it's not safe.
2400 MachineBasicBlock::iterator Iter = I;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2401 for (unsigned i = 0; Iter != E && i < 4; ++i) {
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2402 bool SeenDef = false;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2403 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2404 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2405 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2406 SeenDef = true;
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2407 if (!MO.isReg())
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2408 continue;
2409 if (MO.getReg() == X86::EFLAGS) {
2410 if (MO.isUse())
2411 return false;
2412 SeenDef = true;
2413 }
2414 }
2415
2416 if (SeenDef)
2417 // This instruction defines EFLAGS, no need to look any further.
2418 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2419 ++Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2420 // Skip over DBG_VALUE.
2421 while (Iter != E && Iter->isDebugValue())
2422 ++Iter;
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2423 }
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2424
Jakob Stoklund Olesenf08354d2011-09-02 23:52:52 +0000[diff] [blame]2425 // It is safe to clobber EFLAGS at the end of a block of no successor has it
2426 // live in.
2427 if (Iter == E) {
2428 for (MachineBasicBlock::succ_iterator SI = MBB.succ_begin(),
2429 SE = MBB.succ_end(); SI != SE; ++SI)
2430 if ((*SI)->isLiveIn(X86::EFLAGS))
2431 return false;
2432 return true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2433 }
2434
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2435 MachineBasicBlock::iterator B = MBB.begin();
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2436 Iter = I;
2437 for (unsigned i = 0; i < 4; ++i) {
2438 // If we make it to the beginning of the block, it's safe to clobber
Sylvestre Ledru91ce36c2012-09-27 10:14:43 +0000[diff] [blame]2439 // EFLAGS iff EFLAGS is not live-in.
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2440 if (Iter == B)
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2441 return !MBB.isLiveIn(X86::EFLAGS);
2442
2443 --Iter;
Evan Chengb6dee6e2010-03-23 20:35:45 +0000[diff] [blame]2444 // Skip over DBG_VALUE.
2445 while (Iter != B && Iter->isDebugValue())
2446 --Iter;
2447
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2448 bool SawKill = false;
2449 for (unsigned j = 0, e = Iter->getNumOperands(); j != e; ++j) {
2450 MachineOperand &MO = Iter->getOperand(j);
Jakob Stoklund Olesen4519fd02012-02-09 00:17:22 +0000[diff] [blame]2451 // A register mask may clobber EFLAGS, but we should still look for a
2452 // live EFLAGS def.
2453 if (MO.isRegMask() && MO.clobbersPhysReg(X86::EFLAGS))
2454 SawKill = true;
Dan Gohman0be8c2b2009-10-14 00:08:59 +0000[diff] [blame]2455 if (MO.isReg() && MO.getReg() == X86::EFLAGS) {
2456 if (MO.isDef()) return MO.isDead();
2457 if (MO.isKill()) SawKill = true;
2458 }
2459 }
2460
2461 if (SawKill)
2462 // This instruction kills EFLAGS and doesn't redefine it, so
2463 // there's no need to look further.
Dan Gohmanc8354582008-10-21 03:24:31 +0000[diff] [blame]2464 return true;
Evan Cheng3f2ceac2008-06-24 07:10:51 +0000[diff] [blame]2465 }
2466
2467 // Conservative answer.
2468 return false;
2469}
2470
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2471void X86InstrInfo::reMaterialize(MachineBasicBlock &MBB,
2472 MachineBasicBlock::iterator I,
Evan Cheng84517442009-07-16 09:20:10 +0000[diff] [blame]2473 unsigned DestReg, unsigned SubIdx,
Evan Cheng6ad7da92009-11-14 02:55:43 +0000[diff] [blame]2474 const MachineInstr *Orig,
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2475 const TargetRegisterInfo &TRI) const {
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2476 bool ClobbersEFLAGS = false;
2477 for (const MachineOperand &MO : Orig->operands()) {
2478 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
2479 ClobbersEFLAGS = true;
2480 break;
2481 }
2482 }
2483
2484 if (ClobbersEFLAGS && !isSafeToClobberEFLAGS(MBB, I)) {
2485 // The instruction clobbers EFLAGS. Re-materialize as MOV32ri to avoid side
2486 // effects.
2487 int Value;
2488 switch (Orig->getOpcode()) {
2489 case X86::MOV32r0: Value = 0; break;
2490 case X86::MOV32r1: Value = 1; break;
2491 case X86::MOV32r_1: Value = -1; break;
2492 default:
2493 llvm_unreachable("Unexpected instruction!");
2494 }
2495
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2496 DebugLoc DL = Orig->getDebugLoc();
2497 BuildMI(MBB, I, DL, get(X86::MOV32ri)).addOperand(Orig->getOperand(0))
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]2498 .addImm(Value);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]2499 } else {
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2500 MachineInstr *MI = MBB.getParent()->CloneMachineInstr(Orig);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2501 MBB.insert(I, MI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2502 }
Evan Cheng147cb762008-04-16 23:44:44 +0000[diff] [blame]2503
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]2504 MachineInstr *NewMI = std::prev(I);
Jakob Stoklund Olesena8ad9772010-06-02 22:47:25 +0000[diff] [blame]2505 NewMI->substituteRegister(Orig->getOperand(0).getReg(), DestReg, SubIdx, TRI);
Evan Chenged6e34f2008-03-31 20:40:39 +0000[diff] [blame]2506}
2507
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2508/// True if MI has a condition code def, e.g. EFLAGS, that is not marked dead.
Andrew Kayloraf083d42015-08-26 20:36:52 +0000[diff] [blame]2509bool X86InstrInfo::hasLiveCondCodeDef(MachineInstr *MI) const {
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2510 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
2511 MachineOperand &MO = MI->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]2512 if (MO.isReg() && MO.isDef() &&
Evan Chenga8a9c152007-10-05 08:04:01 +0000[diff] [blame]2513 MO.getReg() == X86::EFLAGS && !MO.isDead()) {
2514 return true;
2515 }
2516 }
2517 return false;
2518}
2519
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2520/// Check whether the shift count for a machine operand is non-zero.
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2521inline static unsigned getTruncatedShiftCount(MachineInstr *MI,
2522 unsigned ShiftAmtOperandIdx) {
2523 // The shift count is six bits with the REX.W prefix and five bits without.
2524 unsigned ShiftCountMask = (MI->getDesc().TSFlags & X86II::REX_W) ? 63 : 31;
2525 unsigned Imm = MI->getOperand(ShiftAmtOperandIdx).getImm();
2526 return Imm & ShiftCountMask;
2527}
2528
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2529/// Check whether the given shift count is appropriate
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2530/// can be represented by a LEA instruction.
2531inline static bool isTruncatedShiftCountForLEA(unsigned ShAmt) {
2532 // Left shift instructions can be transformed into load-effective-address
2533 // instructions if we can encode them appropriately.
Sanjay Pateldc87d142015-08-12 15:09:09 +0000[diff] [blame]2534 // A LEA instruction utilizes a SIB byte to encode its scale factor.
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2535 // The SIB.scale field is two bits wide which means that we can encode any
2536 // shift amount less than 4.
2537 return ShAmt < 4 && ShAmt > 0;
2538}
2539
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2540bool X86InstrInfo::classifyLEAReg(MachineInstr *MI, const MachineOperand &Src,
2541 unsigned Opc, bool AllowSP,
2542 unsigned &NewSrc, bool &isKill, bool &isUndef,
2543 MachineOperand &ImplicitOp) const {
2544 MachineFunction &MF = *MI->getParent()->getParent();
2545 const TargetRegisterClass *RC;
2546 if (AllowSP) {
2547 RC = Opc != X86::LEA32r ? &X86::GR64RegClass : &X86::GR32RegClass;
2548 } else {
2549 RC = Opc != X86::LEA32r ?
2550 &X86::GR64_NOSPRegClass : &X86::GR32_NOSPRegClass;
2551 }
2552 unsigned SrcReg = Src.getReg();
2553
2554 // For both LEA64 and LEA32 the register already has essentially the right
2555 // type (32-bit or 64-bit) we may just need to forbid SP.
2556 if (Opc != X86::LEA64_32r) {
2557 NewSrc = SrcReg;
2558 isKill = Src.isKill();
2559 isUndef = Src.isUndef();
2560
2561 if (TargetRegisterInfo::isVirtualRegister(NewSrc) &&
2562 !MF.getRegInfo().constrainRegClass(NewSrc, RC))
2563 return false;
2564
2565 return true;
2566 }
2567
2568 // This is for an LEA64_32r and incoming registers are 32-bit. One way or
2569 // another we need to add 64-bit registers to the final MI.
2570 if (TargetRegisterInfo::isPhysicalRegister(SrcReg)) {
2571 ImplicitOp = Src;
2572 ImplicitOp.setImplicit();
2573
2574 NewSrc = getX86SubSuperRegister(Src.getReg(), MVT::i64);
2575 MachineBasicBlock::LivenessQueryResult LQR =
2576 MI->getParent()->computeRegisterLiveness(&getRegisterInfo(), NewSrc, MI);
2577
2578 switch (LQR) {
2579 case MachineBasicBlock::LQR_Unknown:
2580 // We can't give sane liveness flags to the instruction, abandon LEA
2581 // formation.
2582 return false;
2583 case MachineBasicBlock::LQR_Live:
2584 isKill = MI->killsRegister(SrcReg);
2585 isUndef = false;
2586 break;
2587 default:
2588 // The physreg itself is dead, so we have to use it as an <undef>.
2589 isKill = false;
2590 isUndef = true;
2591 break;
2592 }
2593 } else {
2594 // Virtual register of the wrong class, we have to create a temporary 64-bit
2595 // vreg to feed into the LEA.
2596 NewSrc = MF.getRegInfo().createVirtualRegister(RC);
2597 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
2598 get(TargetOpcode::COPY))
2599 .addReg(NewSrc, RegState::Define | RegState::Undef, X86::sub_32bit)
2600 .addOperand(Src);
2601
2602 // Which is obviously going to be dead after we're done with it.
2603 isKill = true;
2604 isUndef = false;
2605 }
2606
2607 // We've set all the parameters without issue.
2608 return true;
2609}
2610
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2611/// Helper for convertToThreeAddress when 16-bit LEA is disabled, use 32-bit
2612/// LEA to form 3-address code by promoting to a 32-bit superregister and then
2613/// truncating back down to a 16-bit subregister.
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2614MachineInstr *
2615X86InstrInfo::convertToThreeAddressWithLEA(unsigned MIOpc,
2616 MachineFunction::iterator &MFI,
2617 MachineBasicBlock::iterator &MBBI,
2618 LiveVariables *LV) const {
2619 MachineInstr *MI = MBBI;
2620 unsigned Dest = MI->getOperand(0).getReg();
2621 unsigned Src = MI->getOperand(1).getReg();
2622 bool isDead = MI->getOperand(0).isDead();
2623 bool isKill = MI->getOperand(1).isKill();
2624
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2625 MachineRegisterInfo &RegInfo = MFI->getParent()->getRegInfo();
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2626 unsigned leaOutReg = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2627 unsigned Opc, leaInReg;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2628 if (Subtarget.is64Bit()) {
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2629 Opc = X86::LEA64_32r;
2630 leaInReg = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2631 } else {
2632 Opc = X86::LEA32r;
2633 leaInReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
2634 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2635
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2636 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2637 // well be shifting and then extracting the lower 16-bits.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2638 // This has the potential to cause partial register stall. e.g.
Evan Cheng3974c8d2009-12-12 18:55:26 +0000[diff] [blame]2639 // movw (%rbp,%rcx,2), %dx
2640 // leal -65(%rdx), %esi
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2641 // But testing has shown this *does* help performance in 64-bit mode (at
2642 // least on modern x86 machines).
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2643 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(X86::IMPLICIT_DEF), leaInReg);
2644 MachineInstr *InsMI =
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2645 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
2646 .addReg(leaInReg, RegState::Define, X86::sub_16bit)
2647 .addReg(Src, getKillRegState(isKill));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2648
2649 MachineInstrBuilder MIB = BuildMI(*MFI, MBBI, MI->getDebugLoc(),
2650 get(Opc), leaOutReg);
2651 switch (MIOpc) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]2652 default: llvm_unreachable("Unreachable!");
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2653 case X86::SHL16ri: {
2654 unsigned ShAmt = MI->getOperand(2).getImm();
2655 MIB.addReg(0).addImm(1 << ShAmt)
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2656 .addReg(leaInReg, RegState::Kill).addImm(0).addReg(0);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2657 break;
2658 }
2659 case X86::INC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2660 addRegOffset(MIB, leaInReg, true, 1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2661 break;
2662 case X86::DEC16r:
Chris Lattnerf4693072010-07-08 23:46:44 +0000[diff] [blame]2663 addRegOffset(MIB, leaInReg, true, -1);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2664 break;
2665 case X86::ADD16ri:
2666 case X86::ADD16ri8:
Chris Lattnerdd774772010-10-08 03:57:25 +0000[diff] [blame]2667 case X86::ADD16ri_DB:
2668 case X86::ADD16ri8_DB:
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2669 addRegOffset(MIB, leaInReg, true, MI->getOperand(2).getImm());
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2670 break;
Chris Lattner626656a2010-10-08 03:54:52 +0000[diff] [blame]2671 case X86::ADD16rr:
2672 case X86::ADD16rr_DB: {
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2673 unsigned Src2 = MI->getOperand(2).getReg();
2674 bool isKill2 = MI->getOperand(2).isKill();
2675 unsigned leaInReg2 = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2676 MachineInstr *InsMI2 = nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2677 if (Src == Src2) {
2678 // ADD16rr %reg1028<kill>, %reg1028
2679 // just a single insert_subreg.
2680 addRegReg(MIB, leaInReg, true, leaInReg, false);
2681 } else {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2682 if (Subtarget.is64Bit())
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2683 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR64_NOSPRegClass);
2684 else
2685 leaInReg2 = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2686 // Build and insert into an implicit UNDEF value. This is OK because
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2687 // well be shifting and then extracting the lower 16-bits.
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2688 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(X86::IMPLICIT_DEF),leaInReg2);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2689 InsMI2 =
Evan Cheng7fae11b2011-12-14 02:11:42 +0000[diff] [blame]2690 BuildMI(*MFI, &*MIB, MI->getDebugLoc(), get(TargetOpcode::COPY))
Jakob Stoklund Olesena1e883d2010-07-08 16:40:15 +0000[diff] [blame]2691 .addReg(leaInReg2, RegState::Define, X86::sub_16bit)
2692 .addReg(Src2, getKillRegState(isKill2));
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2693 addRegReg(MIB, leaInReg, true, leaInReg2, true);
2694 }
2695 if (LV && isKill2 && InsMI2)
2696 LV->replaceKillInstruction(Src2, MI, InsMI2);
2697 break;
2698 }
2699 }
2700
2701 MachineInstr *NewMI = MIB;
2702 MachineInstr *ExtMI =
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2703 BuildMI(*MFI, MBBI, MI->getDebugLoc(), get(TargetOpcode::COPY))
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2704 .addReg(Dest, RegState::Define | getDeadRegState(isDead))
Jakob Stoklund Olesen00264622010-07-08 16:40:22 +0000[diff] [blame]2705 .addReg(leaOutReg, RegState::Kill, X86::sub_16bit);
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2706
2707 if (LV) {
2708 // Update live variables
2709 LV->getVarInfo(leaInReg).Kills.push_back(NewMI);
2710 LV->getVarInfo(leaOutReg).Kills.push_back(ExtMI);
2711 if (isKill)
2712 LV->replaceKillInstruction(Src, MI, InsMI);
2713 if (isDead)
2714 LV->replaceKillInstruction(Dest, MI, ExtMI);
2715 }
2716
2717 return ExtMI;
2718}
2719
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]2720/// This method must be implemented by targets that
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2721/// set the M_CONVERTIBLE_TO_3_ADDR flag. When this flag is set, the target
2722/// may be able to convert a two-address instruction into a true
2723/// three-address instruction on demand. This allows the X86 target (for
2724/// example) to convert ADD and SHL instructions into LEA instructions if they
2725/// would require register copies due to two-addressness.
2726///
2727/// This method returns a null pointer if the transformation cannot be
2728/// performed, otherwise it returns the new instruction.
2729///
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2730MachineInstr *
2731X86InstrInfo::convertToThreeAddress(MachineFunction::iterator &MFI,
2732 MachineBasicBlock::iterator &MBBI,
Owen Anderson30cc0282008-07-02 23:41:07 +0000[diff] [blame]2733 LiveVariables *LV) const {
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2734 MachineInstr *MI = MBBI;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2735
2736 // The following opcodes also sets the condition code register(s). Only
2737 // convert them to equivalent lea if the condition code register def's
2738 // are dead!
2739 if (hasLiveCondCodeDef(MI))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2740 return nullptr;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2741
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]2742 MachineFunction &MF = *MI->getParent()->getParent();
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2743 // All instructions input are two-addr instructions. Get the known operands.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2744 const MachineOperand &Dest = MI->getOperand(0);
2745 const MachineOperand &Src = MI->getOperand(1);
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2746
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2747 MachineInstr *NewMI = nullptr;
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2748 // FIXME: 16-bit LEA's are really slow on Athlons, but not bad on P4's. When
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2749 // we have better subtarget support, enable the 16-bit LEA generation here.
Evan Cheng26fdd722009-12-12 20:03:14 +0000[diff] [blame]2750 // 16-bit LEA is also slow on Core2.
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2751 bool DisableLEA16 = true;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]2752 bool is64Bit = Subtarget.is64Bit();
Evan Cheng07fc1072006-12-01 21:52:41 +0000[diff] [blame]2753
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2754 unsigned MIOpc = MI->getOpcode();
2755 switch (MIOpc) {
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2756 default: return nullptr;
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2757 case X86::SHL64ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2758 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2759 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2760 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2761
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2762 // LEA can't handle RSP.
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2763 if (TargetRegisterInfo::isVirtualRegister(Src.getReg()) &&
2764 !MF.getRegInfo().constrainRegClass(Src.getReg(),
2765 &X86::GR64_NOSPRegClass))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2766 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2767
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]2768 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2769 .addOperand(Dest)
2770 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattnerbcd38852007-03-28 18:12:31 +0000[diff] [blame]2771 break;
2772 }
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2773 case X86::SHL32ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2774 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2775 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2776 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2777
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2778 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2779
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2780 // LEA can't handle ESP.
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2781 bool isKill, isUndef;
2782 unsigned SrcReg;
2783 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2784 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2785 SrcReg, isKill, isUndef, ImplicitOp))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2786 return nullptr;
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2787
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2788 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2789 .addOperand(Dest)
Tim Northover6833e3f2013-06-10 20:43:49 +0000[diff] [blame]2790 .addReg(0).addImm(1 << ShAmt)
2791 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef))
2792 .addImm(0).addReg(0);
2793 if (ImplicitOp.getReg() != 0)
2794 MIB.addOperand(ImplicitOp);
2795 NewMI = MIB;
2796
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2797 break;
2798 }
2799 case X86::SHL16ri: {
Evan Cheng483e1ce2007-09-14 21:48:26 +0000[diff] [blame]2800 assert(MI->getNumOperands() >= 3 && "Unknown shift instruction!");
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]2801 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2802 if (!isTruncatedShiftCountForLEA(ShAmt)) return nullptr;
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2803
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2804 if (DisableLEA16)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2805 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV) : nullptr;
Evan Cheng766a73f2009-12-11 06:01:48 +0000[diff] [blame]2806 NewMI = BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2807 .addOperand(Dest)
2808 .addReg(0).addImm(1 << ShAmt).addOperand(Src).addImm(0).addReg(0);
Chris Lattner3e1d9172007-03-20 06:08:29 +0000[diff] [blame]2809 break;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2810 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2811 case X86::INC64r:
2812 case X86::INC32r: {
2813 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2814 unsigned Opc = MIOpc == X86::INC64r ? X86::LEA64r
2815 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2816 bool isKill, isUndef;
2817 unsigned SrcReg;
2818 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2819 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2820 SrcReg, isKill, isUndef, ImplicitOp))
2821 return nullptr;
Evan Cheng66f849b2006-05-30 20:26:50 +0000[diff] [blame]2822
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2823 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2824 .addOperand(Dest)
2825 .addReg(SrcReg, getKillRegState(isKill) | getUndefRegState(isUndef));
2826 if (ImplicitOp.getReg() != 0)
2827 MIB.addOperand(ImplicitOp);
Jakob Stoklund Olesenb19bae42010-10-07 00:07:26 +0000[diff] [blame]2828
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2829 NewMI = addOffset(MIB, 1);
2830 break;
Evan Chengfa2c8282007-10-05 20:34:26 +0000[diff] [blame]2831 }
Craig Topper39354e12015-01-07 08:10:38 +0000[diff] [blame]2832 case X86::INC16r:
2833 if (DisableLEA16)
2834 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2835 : nullptr;
2836 assert(MI->getNumOperands() >= 2 && "Unknown inc instruction!");
2837 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2838 .addOperand(Dest).addOperand(Src), 1);
2839 break;
2840 case X86::DEC64r:
2841 case X86::DEC32r: {
2842 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2843 unsigned Opc = MIOpc == X86::DEC64r ? X86::LEA64r
2844 : (is64Bit ? X86::LEA64_32r : X86::LEA32r);
2845
2846 bool isKill, isUndef;
2847 unsigned SrcReg;
2848 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2849 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ false,
2850 SrcReg, isKill, isUndef, ImplicitOp))
2851 return nullptr;
2852
2853 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2854 .addOperand(Dest)
2855 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2856 if (ImplicitOp.getReg() != 0)
2857 MIB.addOperand(ImplicitOp);
2858
2859 NewMI = addOffset(MIB, -1);
2860
2861 break;
2862 }
2863 case X86::DEC16r:
2864 if (DisableLEA16)
2865 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2866 : nullptr;
2867 assert(MI->getNumOperands() >= 2 && "Unknown dec instruction!");
2868 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2869 .addOperand(Dest).addOperand(Src), -1);
2870 break;
2871 case X86::ADD64rr:
2872 case X86::ADD64rr_DB:
2873 case X86::ADD32rr:
2874 case X86::ADD32rr_DB: {
2875 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2876 unsigned Opc;
2877 if (MIOpc == X86::ADD64rr || MIOpc == X86::ADD64rr_DB)
2878 Opc = X86::LEA64r;
2879 else
2880 Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2881
2882 bool isKill, isUndef;
2883 unsigned SrcReg;
2884 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2885 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2886 SrcReg, isKill, isUndef, ImplicitOp))
2887 return nullptr;
2888
2889 const MachineOperand &Src2 = MI->getOperand(2);
2890 bool isKill2, isUndef2;
2891 unsigned SrcReg2;
2892 MachineOperand ImplicitOp2 = MachineOperand::CreateReg(0, false);
2893 if (!classifyLEAReg(MI, Src2, Opc, /*AllowSP=*/ false,
2894 SrcReg2, isKill2, isUndef2, ImplicitOp2))
2895 return nullptr;
2896
2897 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2898 .addOperand(Dest);
2899 if (ImplicitOp.getReg() != 0)
2900 MIB.addOperand(ImplicitOp);
2901 if (ImplicitOp2.getReg() != 0)
2902 MIB.addOperand(ImplicitOp2);
2903
2904 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
2905
2906 // Preserve undefness of the operands.
2907 NewMI->getOperand(1).setIsUndef(isUndef);
2908 NewMI->getOperand(3).setIsUndef(isUndef2);
2909
2910 if (LV && Src2.isKill())
2911 LV->replaceKillInstruction(SrcReg2, MI, NewMI);
2912 break;
2913 }
2914 case X86::ADD16rr:
2915 case X86::ADD16rr_DB: {
2916 if (DisableLEA16)
2917 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2918 : nullptr;
2919 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2920 unsigned Src2 = MI->getOperand(2).getReg();
2921 bool isKill2 = MI->getOperand(2).isKill();
2922 NewMI = addRegReg(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2923 .addOperand(Dest),
2924 Src.getReg(), Src.isKill(), Src2, isKill2);
2925
2926 // Preserve undefness of the operands.
2927 bool isUndef = MI->getOperand(1).isUndef();
2928 bool isUndef2 = MI->getOperand(2).isUndef();
2929 NewMI->getOperand(1).setIsUndef(isUndef);
2930 NewMI->getOperand(3).setIsUndef(isUndef2);
2931
2932 if (LV && isKill2)
2933 LV->replaceKillInstruction(Src2, MI, NewMI);
2934 break;
2935 }
2936 case X86::ADD64ri32:
2937 case X86::ADD64ri8:
2938 case X86::ADD64ri32_DB:
2939 case X86::ADD64ri8_DB:
2940 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2941 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA64r))
2942 .addOperand(Dest).addOperand(Src),
2943 MI->getOperand(2).getImm());
2944 break;
2945 case X86::ADD32ri:
2946 case X86::ADD32ri8:
2947 case X86::ADD32ri_DB:
2948 case X86::ADD32ri8_DB: {
2949 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2950 unsigned Opc = is64Bit ? X86::LEA64_32r : X86::LEA32r;
2951
2952 bool isKill, isUndef;
2953 unsigned SrcReg;
2954 MachineOperand ImplicitOp = MachineOperand::CreateReg(0, false);
2955 if (!classifyLEAReg(MI, Src, Opc, /*AllowSP=*/ true,
2956 SrcReg, isKill, isUndef, ImplicitOp))
2957 return nullptr;
2958
2959 MachineInstrBuilder MIB = BuildMI(MF, MI->getDebugLoc(), get(Opc))
2960 .addOperand(Dest)
2961 .addReg(SrcReg, getUndefRegState(isUndef) | getKillRegState(isKill));
2962 if (ImplicitOp.getReg() != 0)
2963 MIB.addOperand(ImplicitOp);
2964
2965 NewMI = addOffset(MIB, MI->getOperand(2).getImm());
2966 break;
2967 }
2968 case X86::ADD16ri:
2969 case X86::ADD16ri8:
2970 case X86::ADD16ri_DB:
2971 case X86::ADD16ri8_DB:
2972 if (DisableLEA16)
2973 return is64Bit ? convertToThreeAddressWithLEA(MIOpc, MFI, MBBI, LV)
2974 : nullptr;
2975 assert(MI->getNumOperands() >= 3 && "Unknown add instruction!");
2976 NewMI = addOffset(BuildMI(MF, MI->getDebugLoc(), get(X86::LEA16r))
2977 .addOperand(Dest).addOperand(Src),
2978 MI->getOperand(2).getImm());
2979 break;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2980 }
2981
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]2982 if (!NewMI) return nullptr;
Evan Cheng1bc1cae2008-02-07 08:29:53 +0000[diff] [blame]2983
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2984 if (LV) { // Update live variables
Jakob Stoklund Olesen70304272012-08-23 22:36:31 +0000[diff] [blame]2985 if (Src.isKill())
2986 LV->replaceKillInstruction(Src.getReg(), MI, NewMI);
2987 if (Dest.isDead())
2988 LV->replaceKillInstruction(Dest.getReg(), MI, NewMI);
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]2989 }
2990
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]2991 MFI->insert(MBBI, NewMI); // Insert the new inst
Evan Chengdc2c8742006-11-15 20:58:11 +0000[diff] [blame]2992 return NewMI;
Chris Lattnerb7782d72005-01-02 02:37:07 +0000[diff] [blame]2993}
2994
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]2995/// Returns true if the given instruction opcode is FMA3.
2996/// Otherwise, returns false.
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]2997/// The second parameter is optional and is used as the second return from
2998/// the function. It is set to true if the given instruction has FMA3 opcode
2999/// that is used for lowering of scalar FMA intrinsics, and it is set to false
3000/// otherwise.
3001static bool isFMA3(unsigned Opcode, bool *IsIntrinsic = nullptr) {
3002 if (IsIntrinsic)
3003 *IsIntrinsic = false;
3004
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3005 switch (Opcode) {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3006 case X86::VFMADDSDr132r: case X86::VFMADDSDr132m:
3007 case X86::VFMADDSSr132r: case X86::VFMADDSSr132m:
3008 case X86::VFMSUBSDr132r: case X86::VFMSUBSDr132m:
3009 case X86::VFMSUBSSr132r: case X86::VFMSUBSSr132m:
3010 case X86::VFNMADDSDr132r: case X86::VFNMADDSDr132m:
3011 case X86::VFNMADDSSr132r: case X86::VFNMADDSSr132m:
3012 case X86::VFNMSUBSDr132r: case X86::VFNMSUBSDr132m:
3013 case X86::VFNMSUBSSr132r: case X86::VFNMSUBSSr132m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3014
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3015 case X86::VFMADDSDr213r: case X86::VFMADDSDr213m:
3016 case X86::VFMADDSSr213r: case X86::VFMADDSSr213m:
3017 case X86::VFMSUBSDr213r: case X86::VFMSUBSDr213m:
3018 case X86::VFMSUBSSr213r: case X86::VFMSUBSSr213m:
3019 case X86::VFNMADDSDr213r: case X86::VFNMADDSDr213m:
3020 case X86::VFNMADDSSr213r: case X86::VFNMADDSSr213m:
3021 case X86::VFNMSUBSDr213r: case X86::VFNMSUBSDr213m:
3022 case X86::VFNMSUBSSr213r: case X86::VFNMSUBSSr213m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3023
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3024 case X86::VFMADDSDr231r: case X86::VFMADDSDr231m:
3025 case X86::VFMADDSSr231r: case X86::VFMADDSSr231m:
3026 case X86::VFMSUBSDr231r: case X86::VFMSUBSDr231m:
3027 case X86::VFMSUBSSr231r: case X86::VFMSUBSSr231m:
3028 case X86::VFNMADDSDr231r: case X86::VFNMADDSDr231m:
3029 case X86::VFNMADDSSr231r: case X86::VFNMADDSSr231m:
3030 case X86::VFNMSUBSDr231r: case X86::VFNMSUBSDr231m:
3031 case X86::VFNMSUBSSr231r: case X86::VFNMSUBSSr231m:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3032
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3033 case X86::VFMADDSUBPDr132r: case X86::VFMADDSUBPDr132m:
3034 case X86::VFMADDSUBPSr132r: case X86::VFMADDSUBPSr132m:
3035 case X86::VFMSUBADDPDr132r: case X86::VFMSUBADDPDr132m:
3036 case X86::VFMSUBADDPSr132r: case X86::VFMSUBADDPSr132m:
3037 case X86::VFMADDSUBPDr132rY: case X86::VFMADDSUBPDr132mY:
3038 case X86::VFMADDSUBPSr132rY: case X86::VFMADDSUBPSr132mY:
3039 case X86::VFMSUBADDPDr132rY: case X86::VFMSUBADDPDr132mY:
3040 case X86::VFMSUBADDPSr132rY: case X86::VFMSUBADDPSr132mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3041
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3042 case X86::VFMADDPDr132r: case X86::VFMADDPDr132m:
3043 case X86::VFMADDPSr132r: case X86::VFMADDPSr132m:
3044 case X86::VFMSUBPDr132r: case X86::VFMSUBPDr132m:
3045 case X86::VFMSUBPSr132r: case X86::VFMSUBPSr132m:
3046 case X86::VFNMADDPDr132r: case X86::VFNMADDPDr132m:
3047 case X86::VFNMADDPSr132r: case X86::VFNMADDPSr132m:
3048 case X86::VFNMSUBPDr132r: case X86::VFNMSUBPDr132m:
3049 case X86::VFNMSUBPSr132r: case X86::VFNMSUBPSr132m:
3050 case X86::VFMADDPDr132rY: case X86::VFMADDPDr132mY:
3051 case X86::VFMADDPSr132rY: case X86::VFMADDPSr132mY:
3052 case X86::VFMSUBPDr132rY: case X86::VFMSUBPDr132mY:
3053 case X86::VFMSUBPSr132rY: case X86::VFMSUBPSr132mY:
3054 case X86::VFNMADDPDr132rY: case X86::VFNMADDPDr132mY:
3055 case X86::VFNMADDPSr132rY: case X86::VFNMADDPSr132mY:
3056 case X86::VFNMSUBPDr132rY: case X86::VFNMSUBPDr132mY:
3057 case X86::VFNMSUBPSr132rY: case X86::VFNMSUBPSr132mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3058
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3059 case X86::VFMADDSUBPDr213r: case X86::VFMADDSUBPDr213m:
3060 case X86::VFMADDSUBPSr213r: case X86::VFMADDSUBPSr213m:
3061 case X86::VFMSUBADDPDr213r: case X86::VFMSUBADDPDr213m:
3062 case X86::VFMSUBADDPSr213r: case X86::VFMSUBADDPSr213m:
3063 case X86::VFMADDSUBPDr213rY: case X86::VFMADDSUBPDr213mY:
3064 case X86::VFMADDSUBPSr213rY: case X86::VFMADDSUBPSr213mY:
3065 case X86::VFMSUBADDPDr213rY: case X86::VFMSUBADDPDr213mY:
3066 case X86::VFMSUBADDPSr213rY: case X86::VFMSUBADDPSr213mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3067
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3068 case X86::VFMADDPDr213r: case X86::VFMADDPDr213m:
3069 case X86::VFMADDPSr213r: case X86::VFMADDPSr213m:
3070 case X86::VFMSUBPDr213r: case X86::VFMSUBPDr213m:
3071 case X86::VFMSUBPSr213r: case X86::VFMSUBPSr213m:
3072 case X86::VFNMADDPDr213r: case X86::VFNMADDPDr213m:
3073 case X86::VFNMADDPSr213r: case X86::VFNMADDPSr213m:
3074 case X86::VFNMSUBPDr213r: case X86::VFNMSUBPDr213m:
3075 case X86::VFNMSUBPSr213r: case X86::VFNMSUBPSr213m:
3076 case X86::VFMADDPDr213rY: case X86::VFMADDPDr213mY:
3077 case X86::VFMADDPSr213rY: case X86::VFMADDPSr213mY:
3078 case X86::VFMSUBPDr213rY: case X86::VFMSUBPDr213mY:
3079 case X86::VFMSUBPSr213rY: case X86::VFMSUBPSr213mY:
3080 case X86::VFNMADDPDr213rY: case X86::VFNMADDPDr213mY:
3081 case X86::VFNMADDPSr213rY: case X86::VFNMADDPSr213mY:
3082 case X86::VFNMSUBPDr213rY: case X86::VFNMSUBPDr213mY:
3083 case X86::VFNMSUBPSr213rY: case X86::VFNMSUBPSr213mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3084
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3085 case X86::VFMADDSUBPDr231r: case X86::VFMADDSUBPDr231m:
3086 case X86::VFMADDSUBPSr231r: case X86::VFMADDSUBPSr231m:
3087 case X86::VFMSUBADDPDr231r: case X86::VFMSUBADDPDr231m:
3088 case X86::VFMSUBADDPSr231r: case X86::VFMSUBADDPSr231m:
3089 case X86::VFMADDSUBPDr231rY: case X86::VFMADDSUBPDr231mY:
3090 case X86::VFMADDSUBPSr231rY: case X86::VFMADDSUBPSr231mY:
3091 case X86::VFMSUBADDPDr231rY: case X86::VFMSUBADDPDr231mY:
3092 case X86::VFMSUBADDPSr231rY: case X86::VFMSUBADDPSr231mY:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3093
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3094 case X86::VFMADDPDr231r: case X86::VFMADDPDr231m:
3095 case X86::VFMADDPSr231r: case X86::VFMADDPSr231m:
3096 case X86::VFMSUBPDr231r: case X86::VFMSUBPDr231m:
3097 case X86::VFMSUBPSr231r: case X86::VFMSUBPSr231m:
3098 case X86::VFNMADDPDr231r: case X86::VFNMADDPDr231m:
3099 case X86::VFNMADDPSr231r: case X86::VFNMADDPSr231m:
3100 case X86::VFNMSUBPDr231r: case X86::VFNMSUBPDr231m:
3101 case X86::VFNMSUBPSr231r: case X86::VFNMSUBPSr231m:
3102 case X86::VFMADDPDr231rY: case X86::VFMADDPDr231mY:
3103 case X86::VFMADDPSr231rY: case X86::VFMADDPSr231mY:
3104 case X86::VFMSUBPDr231rY: case X86::VFMSUBPDr231mY:
3105 case X86::VFMSUBPSr231rY: case X86::VFMSUBPSr231mY:
3106 case X86::VFNMADDPDr231rY: case X86::VFNMADDPDr231mY:
3107 case X86::VFNMADDPSr231rY: case X86::VFNMADDPSr231mY:
3108 case X86::VFNMSUBPDr231rY: case X86::VFNMSUBPDr231mY:
3109 case X86::VFNMSUBPSr231rY: case X86::VFNMSUBPSr231mY:
3110 return true;
3111
3112 case X86::VFMADDSDr132r_Int: case X86::VFMADDSDr132m_Int:
3113 case X86::VFMADDSSr132r_Int: case X86::VFMADDSSr132m_Int:
3114 case X86::VFMSUBSDr132r_Int: case X86::VFMSUBSDr132m_Int:
3115 case X86::VFMSUBSSr132r_Int: case X86::VFMSUBSSr132m_Int:
3116 case X86::VFNMADDSDr132r_Int: case X86::VFNMADDSDr132m_Int:
3117 case X86::VFNMADDSSr132r_Int: case X86::VFNMADDSSr132m_Int:
3118 case X86::VFNMSUBSDr132r_Int: case X86::VFNMSUBSDr132m_Int:
3119 case X86::VFNMSUBSSr132r_Int: case X86::VFNMSUBSSr132m_Int:
3120
3121 case X86::VFMADDSDr213r_Int: case X86::VFMADDSDr213m_Int:
3122 case X86::VFMADDSSr213r_Int: case X86::VFMADDSSr213m_Int:
3123 case X86::VFMSUBSDr213r_Int: case X86::VFMSUBSDr213m_Int:
3124 case X86::VFMSUBSSr213r_Int: case X86::VFMSUBSSr213m_Int:
3125 case X86::VFNMADDSDr213r_Int: case X86::VFNMADDSDr213m_Int:
3126 case X86::VFNMADDSSr213r_Int: case X86::VFNMADDSSr213m_Int:
3127 case X86::VFNMSUBSDr213r_Int: case X86::VFNMSUBSDr213m_Int:
3128 case X86::VFNMSUBSSr213r_Int: case X86::VFNMSUBSSr213m_Int:
3129
3130 case X86::VFMADDSDr231r_Int: case X86::VFMADDSDr231m_Int:
3131 case X86::VFMADDSSr231r_Int: case X86::VFMADDSSr231m_Int:
3132 case X86::VFMSUBSDr231r_Int: case X86::VFMSUBSDr231m_Int:
3133 case X86::VFMSUBSSr231r_Int: case X86::VFMSUBSSr231m_Int:
3134 case X86::VFNMADDSDr231r_Int: case X86::VFNMADDSDr231m_Int:
3135 case X86::VFNMADDSSr231r_Int: case X86::VFNMADDSSr231m_Int:
3136 case X86::VFNMSUBSDr231r_Int: case X86::VFNMSUBSDr231m_Int:
3137 case X86::VFNMSUBSSr231r_Int: case X86::VFNMSUBSSr231m_Int:
3138 if (IsIntrinsic)
3139 *IsIntrinsic = true;
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3140 return true;
3141 default:
3142 return false;
3143 }
3144 llvm_unreachable("Opcode not handled by the switch");
3145}
3146
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3147MachineInstr *X86InstrInfo::commuteInstructionImpl(MachineInstr *MI,
3148 bool NewMI,
3149 unsigned OpIdx1,
3150 unsigned OpIdx2) const {
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3151 switch (MI->getOpcode()) {
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3152 case X86::SHRD16rri8: // A = SHRD16rri8 B, C, I -> A = SHLD16rri8 C, B, (16-I)
3153 case X86::SHLD16rri8: // A = SHLD16rri8 B, C, I -> A = SHRD16rri8 C, B, (16-I)
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3154 case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I)
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3155 case X86::SHLD32rri8: // A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I)
3156 case X86::SHRD64rri8: // A = SHRD64rri8 B, C, I -> A = SHLD64rri8 C, B, (64-I)
3157 case X86::SHLD64rri8:{// A = SHLD64rri8 B, C, I -> A = SHRD64rri8 C, B, (64-I)
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3158 unsigned Opc;
3159 unsigned Size;
3160 switch (MI->getOpcode()) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3161 default: llvm_unreachable("Unreachable!");
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3162 case X86::SHRD16rri8: Size = 16; Opc = X86::SHLD16rri8; break;
3163 case X86::SHLD16rri8: Size = 16; Opc = X86::SHRD16rri8; break;
3164 case X86::SHRD32rri8: Size = 32; Opc = X86::SHLD32rri8; break;
3165 case X86::SHLD32rri8: Size = 32; Opc = X86::SHRD32rri8; break;
Dan Gohman48ea03d2007-09-14 23:17:45 +0000[diff] [blame]3166 case X86::SHRD64rri8: Size = 64; Opc = X86::SHLD64rri8; break;
3167 case X86::SHLD64rri8: Size = 64; Opc = X86::SHRD64rri8; break;
Chris Lattnerd54845f2005-01-19 07:31:24 +0000[diff] [blame]3168 }
Chris Lattner5c463782007-12-30 20:49:49 +0000[diff] [blame]3169 unsigned Amt = MI->getOperand(3).getImm();
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]3170 if (NewMI) {
3171 MachineFunction &MF = *MI->getParent()->getParent();
3172 MI = MF.CloneMachineInstr(MI);
3173 NewMI = false;
Evan Cheng244183e2008-02-13 02:46:49 +0000[diff] [blame]3174 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]3175 MI->setDesc(get(Opc));
3176 MI->getOperand(3).setImm(Size-Amt);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3177 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3178 }
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3179 case X86::BLENDPDrri:
3180 case X86::BLENDPSrri:
3181 case X86::PBLENDWrri:
3182 case X86::VBLENDPDrri:
3183 case X86::VBLENDPSrri:
3184 case X86::VBLENDPDYrri:
3185 case X86::VBLENDPSYrri:
3186 case X86::VPBLENDDrri:
3187 case X86::VPBLENDWrri:
3188 case X86::VPBLENDDYrri:
3189 case X86::VPBLENDWYrri:{
3190 unsigned Mask;
3191 switch (MI->getOpcode()) {
3192 default: llvm_unreachable("Unreachable!");
3193 case X86::BLENDPDrri: Mask = 0x03; break;
3194 case X86::BLENDPSrri: Mask = 0x0F; break;
3195 case X86::PBLENDWrri: Mask = 0xFF; break;
3196 case X86::VBLENDPDrri: Mask = 0x03; break;
3197 case X86::VBLENDPSrri: Mask = 0x0F; break;
3198 case X86::VBLENDPDYrri: Mask = 0x0F; break;
3199 case X86::VBLENDPSYrri: Mask = 0xFF; break;
3200 case X86::VPBLENDDrri: Mask = 0x0F; break;
3201 case X86::VPBLENDWrri: Mask = 0xFF; break;
3202 case X86::VPBLENDDYrri: Mask = 0xFF; break;
3203 case X86::VPBLENDWYrri: Mask = 0xFF; break;
3204 }
Andrea Di Biagio7ecd22c2014-11-06 14:36:45 +0000[diff] [blame]3205 // Only the least significant bits of Imm are used.
3206 unsigned Imm = MI->getOperand(3).getImm() & Mask;
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3207 if (NewMI) {
3208 MachineFunction &MF = *MI->getParent()->getParent();
3209 MI = MF.CloneMachineInstr(MI);
3210 NewMI = false;
3211 }
3212 MI->getOperand(3).setImm(Mask ^ Imm);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3213 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrimc9a07792014-11-04 23:25:08 +0000[diff] [blame]3214 }
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3215 case X86::PCLMULQDQrr:
3216 case X86::VPCLMULQDQrr:{
3217 // SRC1 64bits = Imm[0] ? SRC1[127:64] : SRC1[63:0]
3218 // SRC2 64bits = Imm[4] ? SRC2[127:64] : SRC2[63:0]
3219 unsigned Imm = MI->getOperand(3).getImm();
3220 unsigned Src1Hi = Imm & 0x01;
3221 unsigned Src2Hi = Imm & 0x10;
3222 if (NewMI) {
3223 MachineFunction &MF = *MI->getParent()->getParent();
3224 MI = MF.CloneMachineInstr(MI);
3225 NewMI = false;
3226 }
3227 MI->getOperand(3).setImm((Src1Hi << 4) | (Src2Hi >> 4));
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3228 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim9b7c0032015-01-26 22:00:18 +0000[diff] [blame]3229 }
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3230 case X86::CMPPDrri:
3231 case X86::CMPPSrri:
3232 case X86::VCMPPDrri:
3233 case X86::VCMPPSrri:
3234 case X86::VCMPPDYrri:
3235 case X86::VCMPPSYrri: {
3236 // Float comparison can be safely commuted for
3237 // Ordered/Unordered/Equal/NotEqual tests
3238 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3239 switch (Imm) {
3240 case 0x00: // EQUAL
3241 case 0x03: // UNORDERED
3242 case 0x04: // NOT EQUAL
3243 case 0x07: // ORDERED
3244 if (NewMI) {
3245 MachineFunction &MF = *MI->getParent()->getParent();
3246 MI = MF.CloneMachineInstr(MI);
3247 NewMI = false;
3248 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3249 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3250 default:
3251 return nullptr;
3252 }
3253 }
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3254 case X86::VPCOMBri: case X86::VPCOMUBri:
3255 case X86::VPCOMDri: case X86::VPCOMUDri:
3256 case X86::VPCOMQri: case X86::VPCOMUQri:
3257 case X86::VPCOMWri: case X86::VPCOMUWri: {
3258 // Flip comparison mode immediate (if necessary).
3259 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3260 switch (Imm) {
3261 case 0x00: Imm = 0x02; break; // LT -> GT
3262 case 0x01: Imm = 0x03; break; // LE -> GE
3263 case 0x02: Imm = 0x00; break; // GT -> LT
3264 case 0x03: Imm = 0x01; break; // GE -> LE
3265 case 0x04: // EQ
3266 case 0x05: // NE
3267 case 0x06: // FALSE
3268 case 0x07: // TRUE
3269 default:
3270 break;
3271 }
3272 if (NewMI) {
3273 MachineFunction &MF = *MI->getParent()->getParent();
3274 MI = MF.CloneMachineInstr(MI);
3275 NewMI = false;
3276 }
3277 MI->getOperand(3).setImm(Imm);
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3278 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Simon Pilgrim31457d52015-02-14 22:40:46 +0000[diff] [blame]3279 }
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3280 case X86::CMOVB16rr: case X86::CMOVB32rr: case X86::CMOVB64rr:
3281 case X86::CMOVAE16rr: case X86::CMOVAE32rr: case X86::CMOVAE64rr:
3282 case X86::CMOVE16rr: case X86::CMOVE32rr: case X86::CMOVE64rr:
3283 case X86::CMOVNE16rr: case X86::CMOVNE32rr: case X86::CMOVNE64rr:
3284 case X86::CMOVBE16rr: case X86::CMOVBE32rr: case X86::CMOVBE64rr:
3285 case X86::CMOVA16rr: case X86::CMOVA32rr: case X86::CMOVA64rr:
3286 case X86::CMOVL16rr: case X86::CMOVL32rr: case X86::CMOVL64rr:
3287 case X86::CMOVGE16rr: case X86::CMOVGE32rr: case X86::CMOVGE64rr:
3288 case X86::CMOVLE16rr: case X86::CMOVLE32rr: case X86::CMOVLE64rr:
3289 case X86::CMOVG16rr: case X86::CMOVG32rr: case X86::CMOVG64rr:
3290 case X86::CMOVS16rr: case X86::CMOVS32rr: case X86::CMOVS64rr:
3291 case X86::CMOVNS16rr: case X86::CMOVNS32rr: case X86::CMOVNS64rr:
3292 case X86::CMOVP16rr: case X86::CMOVP32rr: case X86::CMOVP64rr:
3293 case X86::CMOVNP16rr: case X86::CMOVNP32rr: case X86::CMOVNP64rr:
3294 case X86::CMOVO16rr: case X86::CMOVO32rr: case X86::CMOVO64rr:
3295 case X86::CMOVNO16rr: case X86::CMOVNO32rr: case X86::CMOVNO64rr: {
3296 unsigned Opc;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3297 switch (MI->getOpcode()) {
Craig Topper653e7592012-08-21 07:32:16 +0000[diff] [blame]3298 default: llvm_unreachable("Unreachable!");
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3299 case X86::CMOVB16rr: Opc = X86::CMOVAE16rr; break;
3300 case X86::CMOVB32rr: Opc = X86::CMOVAE32rr; break;
3301 case X86::CMOVB64rr: Opc = X86::CMOVAE64rr; break;
3302 case X86::CMOVAE16rr: Opc = X86::CMOVB16rr; break;
3303 case X86::CMOVAE32rr: Opc = X86::CMOVB32rr; break;
3304 case X86::CMOVAE64rr: Opc = X86::CMOVB64rr; break;
3305 case X86::CMOVE16rr: Opc = X86::CMOVNE16rr; break;
3306 case X86::CMOVE32rr: Opc = X86::CMOVNE32rr; break;
3307 case X86::CMOVE64rr: Opc = X86::CMOVNE64rr; break;
3308 case X86::CMOVNE16rr: Opc = X86::CMOVE16rr; break;
3309 case X86::CMOVNE32rr: Opc = X86::CMOVE32rr; break;
3310 case X86::CMOVNE64rr: Opc = X86::CMOVE64rr; break;
Chris Lattner1a1c6002010-10-05 23:00:14 +0000[diff] [blame]3311 case X86::CMOVBE16rr: Opc = X86::CMOVA16rr; break;
3312 case X86::CMOVBE32rr: Opc = X86::CMOVA32rr; break;
3313 case X86::CMOVBE64rr: Opc = X86::CMOVA64rr; break;
3314 case X86::CMOVA16rr: Opc = X86::CMOVBE16rr; break;
3315 case X86::CMOVA32rr: Opc = X86::CMOVBE32rr; break;
3316 case X86::CMOVA64rr: Opc = X86::CMOVBE64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3317 case X86::CMOVL16rr: Opc = X86::CMOVGE16rr; break;
3318 case X86::CMOVL32rr: Opc = X86::CMOVGE32rr; break;
3319 case X86::CMOVL64rr: Opc = X86::CMOVGE64rr; break;
3320 case X86::CMOVGE16rr: Opc = X86::CMOVL16rr; break;
3321 case X86::CMOVGE32rr: Opc = X86::CMOVL32rr; break;
3322 case X86::CMOVGE64rr: Opc = X86::CMOVL64rr; break;
3323 case X86::CMOVLE16rr: Opc = X86::CMOVG16rr; break;
3324 case X86::CMOVLE32rr: Opc = X86::CMOVG32rr; break;
3325 case X86::CMOVLE64rr: Opc = X86::CMOVG64rr; break;
3326 case X86::CMOVG16rr: Opc = X86::CMOVLE16rr; break;
3327 case X86::CMOVG32rr: Opc = X86::CMOVLE32rr; break;
3328 case X86::CMOVG64rr: Opc = X86::CMOVLE64rr; break;
3329 case X86::CMOVS16rr: Opc = X86::CMOVNS16rr; break;
3330 case X86::CMOVS32rr: Opc = X86::CMOVNS32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3331 case X86::CMOVS64rr: Opc = X86::CMOVNS64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3332 case X86::CMOVNS16rr: Opc = X86::CMOVS16rr; break;
3333 case X86::CMOVNS32rr: Opc = X86::CMOVS32rr; break;
3334 case X86::CMOVNS64rr: Opc = X86::CMOVS64rr; break;
3335 case X86::CMOVP16rr: Opc = X86::CMOVNP16rr; break;
3336 case X86::CMOVP32rr: Opc = X86::CMOVNP32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3337 case X86::CMOVP64rr: Opc = X86::CMOVNP64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3338 case X86::CMOVNP16rr: Opc = X86::CMOVP16rr; break;
3339 case X86::CMOVNP32rr: Opc = X86::CMOVP32rr; break;
3340 case X86::CMOVNP64rr: Opc = X86::CMOVP64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3341 case X86::CMOVO16rr: Opc = X86::CMOVNO16rr; break;
3342 case X86::CMOVO32rr: Opc = X86::CMOVNO32rr; break;
Mon P Wang6c8bcf92009-04-18 05:16:01 +0000[diff] [blame]3343 case X86::CMOVO64rr: Opc = X86::CMOVNO64rr; break;
Dan Gohman7e47cc72009-01-07 00:35:10 +0000[diff] [blame]3344 case X86::CMOVNO16rr: Opc = X86::CMOVO16rr; break;
3345 case X86::CMOVNO32rr: Opc = X86::CMOVO32rr; break;
3346 case X86::CMOVNO64rr: Opc = X86::CMOVO64rr; break;
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3347 }
Dan Gohmana39b0a12008-10-17 01:23:35 +0000[diff] [blame]3348 if (NewMI) {
3349 MachineFunction &MF = *MI->getParent()->getParent();
3350 MI = MF.CloneMachineInstr(MI);
3351 NewMI = false;
3352 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]3353 MI->setDesc(get(Opc));
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3354 // Fallthrough intended.
Evan Cheng1151ffd2007-10-05 23:13:21 +0000[diff] [blame]3355 }
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3356 default:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3357 if (isFMA3(MI->getOpcode())) {
3358 unsigned Opc = getFMA3OpcodeToCommuteOperands(MI, OpIdx1, OpIdx2);
3359 if (Opc == 0)
3360 return nullptr;
3361 if (NewMI) {
3362 MachineFunction &MF = *MI->getParent()->getParent();
3363 MI = MF.CloneMachineInstr(MI);
3364 NewMI = false;
3365 }
3366 MI->setDesc(get(Opc));
3367 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3368 return TargetInstrInfo::commuteInstructionImpl(MI, NewMI, OpIdx1, OpIdx2);
Chris Lattner29478012005-01-19 07:11:01 +0000[diff] [blame]3369 }
3370}
3371
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3372bool X86InstrInfo::findFMA3CommutedOpIndices(MachineInstr *MI,
3373 unsigned &SrcOpIdx1,
3374 unsigned &SrcOpIdx2) const {
3375
3376 unsigned RegOpsNum = isMem(MI, 3) ? 2 : 3;
3377
3378 // Only the first RegOpsNum operands are commutable.
3379 // Also, the value 'CommuteAnyOperandIndex' is valid here as it means
3380 // that the operand is not specified/fixed.
3381 if (SrcOpIdx1 != CommuteAnyOperandIndex &&
3382 (SrcOpIdx1 < 1 || SrcOpIdx1 > RegOpsNum))
3383 return false;
3384 if (SrcOpIdx2 != CommuteAnyOperandIndex &&
3385 (SrcOpIdx2 < 1 || SrcOpIdx2 > RegOpsNum))
3386 return false;
3387
3388 // Look for two different register operands assumed to be commutable
3389 // regardless of the FMA opcode. The FMA opcode is adjusted later.
3390 if (SrcOpIdx1 == CommuteAnyOperandIndex ||
3391 SrcOpIdx2 == CommuteAnyOperandIndex) {
3392 unsigned CommutableOpIdx1 = SrcOpIdx1;
3393 unsigned CommutableOpIdx2 = SrcOpIdx2;
3394
3395 // At least one of operands to be commuted is not specified and
3396 // this method is free to choose appropriate commutable operands.
3397 if (SrcOpIdx1 == SrcOpIdx2)
3398 // Both of operands are not fixed. By default set one of commutable
3399 // operands to the last register operand of the instruction.
3400 CommutableOpIdx2 = RegOpsNum;
3401 else if (SrcOpIdx2 == CommuteAnyOperandIndex)
3402 // Only one of operands is not fixed.
3403 CommutableOpIdx2 = SrcOpIdx1;
3404
3405 // CommutableOpIdx2 is well defined now. Let's choose another commutable
3406 // operand and assign its index to CommutableOpIdx1.
3407 unsigned Op2Reg = MI->getOperand(CommutableOpIdx2).getReg();
3408 for (CommutableOpIdx1 = RegOpsNum; CommutableOpIdx1 > 0; CommutableOpIdx1--) {
3409 // The commuted operands must have different registers.
3410 // Otherwise, the commute transformation does not change anything and
3411 // is useless then.
3412 if (Op2Reg != MI->getOperand(CommutableOpIdx1).getReg())
3413 break;
3414 }
3415
3416 // No appropriate commutable operands were found.
3417 if (CommutableOpIdx1 == 0)
3418 return false;
3419
3420 // Assign the found pair of commutable indices to SrcOpIdx1 and SrcOpidx2
3421 // to return those values.
3422 if (!fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2,
3423 CommutableOpIdx1, CommutableOpIdx2))
3424 return false;
3425 }
3426
3427 // Check if we can adjust the opcode to preserve the semantics when
3428 // commute the register operands.
3429 return getFMA3OpcodeToCommuteOperands(MI, SrcOpIdx1, SrcOpIdx2) != 0;
3430}
3431
3432unsigned X86InstrInfo::getFMA3OpcodeToCommuteOperands(MachineInstr *MI,
3433 unsigned SrcOpIdx1,
3434 unsigned SrcOpIdx2) const {
3435 unsigned Opc = MI->getOpcode();
3436
3437 // Define the array that holds FMA opcodes in groups
3438 // of 3 opcodes(132, 213, 231) in each group.
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3439 static const unsigned RegularOpcodeGroups[][3] = {
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3440 { X86::VFMADDSSr132r, X86::VFMADDSSr213r, X86::VFMADDSSr231r },
3441 { X86::VFMADDSDr132r, X86::VFMADDSDr213r, X86::VFMADDSDr231r },
3442 { X86::VFMADDPSr132r, X86::VFMADDPSr213r, X86::VFMADDPSr231r },
3443 { X86::VFMADDPDr132r, X86::VFMADDPDr213r, X86::VFMADDPDr231r },
3444 { X86::VFMADDPSr132rY, X86::VFMADDPSr213rY, X86::VFMADDPSr231rY },
3445 { X86::VFMADDPDr132rY, X86::VFMADDPDr213rY, X86::VFMADDPDr231rY },
3446 { X86::VFMADDSSr132m, X86::VFMADDSSr213m, X86::VFMADDSSr231m },
3447 { X86::VFMADDSDr132m, X86::VFMADDSDr213m, X86::VFMADDSDr231m },
3448 { X86::VFMADDPSr132m, X86::VFMADDPSr213m, X86::VFMADDPSr231m },
3449 { X86::VFMADDPDr132m, X86::VFMADDPDr213m, X86::VFMADDPDr231m },
3450 { X86::VFMADDPSr132mY, X86::VFMADDPSr213mY, X86::VFMADDPSr231mY },
3451 { X86::VFMADDPDr132mY, X86::VFMADDPDr213mY, X86::VFMADDPDr231mY },
3452
3453 { X86::VFMSUBSSr132r, X86::VFMSUBSSr213r, X86::VFMSUBSSr231r },
3454 { X86::VFMSUBSDr132r, X86::VFMSUBSDr213r, X86::VFMSUBSDr231r },
3455 { X86::VFMSUBPSr132r, X86::VFMSUBPSr213r, X86::VFMSUBPSr231r },
3456 { X86::VFMSUBPDr132r, X86::VFMSUBPDr213r, X86::VFMSUBPDr231r },
3457 { X86::VFMSUBPSr132rY, X86::VFMSUBPSr213rY, X86::VFMSUBPSr231rY },
3458 { X86::VFMSUBPDr132rY, X86::VFMSUBPDr213rY, X86::VFMSUBPDr231rY },
3459 { X86::VFMSUBSSr132m, X86::VFMSUBSSr213m, X86::VFMSUBSSr231m },
3460 { X86::VFMSUBSDr132m, X86::VFMSUBSDr213m, X86::VFMSUBSDr231m },
3461 { X86::VFMSUBPSr132m, X86::VFMSUBPSr213m, X86::VFMSUBPSr231m },
3462 { X86::VFMSUBPDr132m, X86::VFMSUBPDr213m, X86::VFMSUBPDr231m },
3463 { X86::VFMSUBPSr132mY, X86::VFMSUBPSr213mY, X86::VFMSUBPSr231mY },
3464 { X86::VFMSUBPDr132mY, X86::VFMSUBPDr213mY, X86::VFMSUBPDr231mY },
Vyacheslav Klochkov1ff9cbd2015-11-12 20:11:57 +0000[diff] [blame]3465
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3466 { X86::VFNMADDSSr132r, X86::VFNMADDSSr213r, X86::VFNMADDSSr231r },
3467 { X86::VFNMADDSDr132r, X86::VFNMADDSDr213r, X86::VFNMADDSDr231r },
3468 { X86::VFNMADDPSr132r, X86::VFNMADDPSr213r, X86::VFNMADDPSr231r },
3469 { X86::VFNMADDPDr132r, X86::VFNMADDPDr213r, X86::VFNMADDPDr231r },
3470 { X86::VFNMADDPSr132rY, X86::VFNMADDPSr213rY, X86::VFNMADDPSr231rY },
3471 { X86::VFNMADDPDr132rY, X86::VFNMADDPDr213rY, X86::VFNMADDPDr231rY },
3472 { X86::VFNMADDSSr132m, X86::VFNMADDSSr213m, X86::VFNMADDSSr231m },
3473 { X86::VFNMADDSDr132m, X86::VFNMADDSDr213m, X86::VFNMADDSDr231m },
3474 { X86::VFNMADDPSr132m, X86::VFNMADDPSr213m, X86::VFNMADDPSr231m },
3475 { X86::VFNMADDPDr132m, X86::VFNMADDPDr213m, X86::VFNMADDPDr231m },
3476 { X86::VFNMADDPSr132mY, X86::VFNMADDPSr213mY, X86::VFNMADDPSr231mY },
3477 { X86::VFNMADDPDr132mY, X86::VFNMADDPDr213mY, X86::VFNMADDPDr231mY },
3478
3479 { X86::VFNMSUBSSr132r, X86::VFNMSUBSSr213r, X86::VFNMSUBSSr231r },
3480 { X86::VFNMSUBSDr132r, X86::VFNMSUBSDr213r, X86::VFNMSUBSDr231r },
3481 { X86::VFNMSUBPSr132r, X86::VFNMSUBPSr213r, X86::VFNMSUBPSr231r },
3482 { X86::VFNMSUBPDr132r, X86::VFNMSUBPDr213r, X86::VFNMSUBPDr231r },
3483 { X86::VFNMSUBPSr132rY, X86::VFNMSUBPSr213rY, X86::VFNMSUBPSr231rY },
3484 { X86::VFNMSUBPDr132rY, X86::VFNMSUBPDr213rY, X86::VFNMSUBPDr231rY },
3485 { X86::VFNMSUBSSr132m, X86::VFNMSUBSSr213m, X86::VFNMSUBSSr231m },
3486 { X86::VFNMSUBSDr132m, X86::VFNMSUBSDr213m, X86::VFNMSUBSDr231m },
3487 { X86::VFNMSUBPSr132m, X86::VFNMSUBPSr213m, X86::VFNMSUBPSr231m },
3488 { X86::VFNMSUBPDr132m, X86::VFNMSUBPDr213m, X86::VFNMSUBPDr231m },
3489 { X86::VFNMSUBPSr132mY, X86::VFNMSUBPSr213mY, X86::VFNMSUBPSr231mY },
3490 { X86::VFNMSUBPDr132mY, X86::VFNMSUBPDr213mY, X86::VFNMSUBPDr231mY },
3491
3492 { X86::VFMADDSUBPSr132r, X86::VFMADDSUBPSr213r, X86::VFMADDSUBPSr231r },
3493 { X86::VFMADDSUBPDr132r, X86::VFMADDSUBPDr213r, X86::VFMADDSUBPDr231r },
3494 { X86::VFMADDSUBPSr132rY, X86::VFMADDSUBPSr213rY, X86::VFMADDSUBPSr231rY },
3495 { X86::VFMADDSUBPDr132rY, X86::VFMADDSUBPDr213rY, X86::VFMADDSUBPDr231rY },
3496 { X86::VFMADDSUBPSr132m, X86::VFMADDSUBPSr213m, X86::VFMADDSUBPSr231m },
3497 { X86::VFMADDSUBPDr132m, X86::VFMADDSUBPDr213m, X86::VFMADDSUBPDr231m },
3498 { X86::VFMADDSUBPSr132mY, X86::VFMADDSUBPSr213mY, X86::VFMADDSUBPSr231mY },
3499 { X86::VFMADDSUBPDr132mY, X86::VFMADDSUBPDr213mY, X86::VFMADDSUBPDr231mY },
3500
3501 { X86::VFMSUBADDPSr132r, X86::VFMSUBADDPSr213r, X86::VFMSUBADDPSr231r },
3502 { X86::VFMSUBADDPDr132r, X86::VFMSUBADDPDr213r, X86::VFMSUBADDPDr231r },
3503 { X86::VFMSUBADDPSr132rY, X86::VFMSUBADDPSr213rY, X86::VFMSUBADDPSr231rY },
3504 { X86::VFMSUBADDPDr132rY, X86::VFMSUBADDPDr213rY, X86::VFMSUBADDPDr231rY },
3505 { X86::VFMSUBADDPSr132m, X86::VFMSUBADDPSr213m, X86::VFMSUBADDPSr231m },
3506 { X86::VFMSUBADDPDr132m, X86::VFMSUBADDPDr213m, X86::VFMSUBADDPDr231m },
3507 { X86::VFMSUBADDPSr132mY, X86::VFMSUBADDPSr213mY, X86::VFMSUBADDPSr231mY },
3508 { X86::VFMSUBADDPDr132mY, X86::VFMSUBADDPDr213mY, X86::VFMSUBADDPDr231mY }
3509 };
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3510
3511 // Define the array that holds FMA*_Int opcodes in groups
3512 // of 3 opcodes(132, 213, 231) in each group.
3513 static const unsigned IntrinOpcodeGroups[][3] = {
3514 { X86::VFMADDSSr132r_Int, X86::VFMADDSSr213r_Int, X86::VFMADDSSr231r_Int },
3515 { X86::VFMADDSDr132r_Int, X86::VFMADDSDr213r_Int, X86::VFMADDSDr231r_Int },
3516 { X86::VFMADDSSr132m_Int, X86::VFMADDSSr213m_Int, X86::VFMADDSSr231m_Int },
3517 { X86::VFMADDSDr132m_Int, X86::VFMADDSDr213m_Int, X86::VFMADDSDr231m_Int },
3518
3519 { X86::VFMSUBSSr132r_Int, X86::VFMSUBSSr213r_Int, X86::VFMSUBSSr231r_Int },
3520 { X86::VFMSUBSDr132r_Int, X86::VFMSUBSDr213r_Int, X86::VFMSUBSDr231r_Int },
3521 { X86::VFMSUBSSr132m_Int, X86::VFMSUBSSr213m_Int, X86::VFMSUBSSr231m_Int },
3522 { X86::VFMSUBSDr132m_Int, X86::VFMSUBSDr213m_Int, X86::VFMSUBSDr231m_Int },
3523
3524 { X86::VFNMADDSSr132r_Int, X86::VFNMADDSSr213r_Int, X86::VFNMADDSSr231r_Int },
3525 { X86::VFNMADDSDr132r_Int, X86::VFNMADDSDr213r_Int, X86::VFNMADDSDr231r_Int },
3526 { X86::VFNMADDSSr132m_Int, X86::VFNMADDSSr213m_Int, X86::VFNMADDSSr231m_Int },
3527 { X86::VFNMADDSDr132m_Int, X86::VFNMADDSDr213m_Int, X86::VFNMADDSDr231m_Int },
3528
3529 { X86::VFNMSUBSSr132r_Int, X86::VFNMSUBSSr213r_Int, X86::VFNMSUBSSr231r_Int },
3530 { X86::VFNMSUBSDr132r_Int, X86::VFNMSUBSDr213r_Int, X86::VFNMSUBSDr231r_Int },
3531 { X86::VFNMSUBSSr132m_Int, X86::VFNMSUBSSr213m_Int, X86::VFNMSUBSSr231m_Int },
3532 { X86::VFNMSUBSDr132m_Int, X86::VFNMSUBSDr213m_Int, X86::VFNMSUBSDr231m_Int },
3533 };
3534
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3535 const unsigned Form132Index = 0;
3536 const unsigned Form213Index = 1;
3537 const unsigned Form231Index = 2;
3538 const unsigned FormsNum = 3;
3539
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3540 bool IsIntrinOpcode;
3541 isFMA3(Opc, &IsIntrinOpcode);
3542
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3543 size_t GroupsNum;
Craig Topper27e29122015-11-30 02:28:19 +0000[diff] [blame]3544 const unsigned (*OpcodeGroups)[3];
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3545 if (IsIntrinOpcode) {
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3546 GroupsNum = array_lengthof(IntrinOpcodeGroups);
Craig Topper27e29122015-11-30 02:28:19 +0000[diff] [blame]3547 OpcodeGroups = IntrinOpcodeGroups;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3548 } else {
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3549 GroupsNum = array_lengthof(RegularOpcodeGroups);
Craig Topper27e29122015-11-30 02:28:19 +0000[diff] [blame]3550 OpcodeGroups = RegularOpcodeGroups;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3551 }
3552
3553 const unsigned *FoundOpcodesGroup = nullptr;
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3554 size_t FormIndex;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3555
3556 // Look for the input opcode in the corresponding opcodes table.
Craig Topperba894c32015-12-01 06:13:13 +0000[diff] [blame]3557 for (size_t GroupIndex = 0; GroupIndex < GroupsNum && !FoundOpcodesGroup;
3558 ++GroupIndex) {
3559 for (FormIndex = 0; FormIndex < FormsNum; ++FormIndex) {
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3560 if (OpcodeGroups[GroupIndex][FormIndex] == Opc) {
3561 FoundOpcodesGroup = OpcodeGroups[GroupIndex];
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3562 break;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3563 }
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3564 }
3565 }
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3566
3567 // The input opcode does not match with any of the opcodes from the tables.
3568 // The unsupported FMA opcode must be added to one of the two opcode groups
3569 // defined above.
3570 assert(FoundOpcodesGroup != nullptr && "Unexpected FMA3 opcode");
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3571
3572 // Put the lowest index to SrcOpIdx1 to simplify the checks below.
3573 if (SrcOpIdx1 > SrcOpIdx2)
3574 std::swap(SrcOpIdx1, SrcOpIdx2);
3575
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3576 // TODO: Commuting the 1st operand of FMA*_Int requires some additional
3577 // analysis. The commute optimization is legal only if all users of FMA*_Int
3578 // use only the lowest element of the FMA*_Int instruction. Such analysis are
3579 // not implemented yet. So, just return 0 in that case.
3580 // When such analysis are available this place will be the right place for
3581 // calling it.
3582 if (IsIntrinOpcode && SrcOpIdx1 == 1)
3583 return 0;
3584
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3585 unsigned Case;
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3586 if (SrcOpIdx1 == 1 && SrcOpIdx2 == 2)
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3587 Case = 0;
3588 else if (SrcOpIdx1 == 1 && SrcOpIdx2 == 3)
3589 Case = 1;
3590 else if (SrcOpIdx1 == 2 && SrcOpIdx2 == 3)
3591 Case = 2;
3592 else
3593 return 0;
3594
3595 // Define the FMA forms mapping array that helps to map input FMA form
3596 // to output FMA form to preserve the operation semantics after
3597 // commuting the operands.
3598 static const unsigned FormMapping[][3] = {
3599 // 0: SrcOpIdx1 == 1 && SrcOpIdx2 == 2;
3600 // FMA132 A, C, b; ==> FMA231 C, A, b;
3601 // FMA213 B, A, c; ==> FMA213 A, B, c;
3602 // FMA231 C, A, b; ==> FMA132 A, C, b;
3603 { Form231Index, Form213Index, Form132Index },
3604 // 1: SrcOpIdx1 == 1 && SrcOpIdx2 == 3;
3605 // FMA132 A, c, B; ==> FMA132 B, c, A;
3606 // FMA213 B, a, C; ==> FMA231 C, a, B;
3607 // FMA231 C, a, B; ==> FMA213 B, a, C;
3608 { Form132Index, Form231Index, Form213Index },
3609 // 2: SrcOpIdx1 == 2 && SrcOpIdx2 == 3;
3610 // FMA132 a, C, B; ==> FMA213 a, B, C;
3611 // FMA213 b, A, C; ==> FMA132 b, C, A;
3612 // FMA231 c, A, B; ==> FMA231 c, B, A;
3613 { Form213Index, Form132Index, Form231Index }
3614 };
3615
3616 // Everything is ready, just adjust the FMA opcode and return it.
3617 FormIndex = FormMapping[Case][FormIndex];
Vyacheslav Klochkovcbc56ba2015-11-13 00:07:35 +0000[diff] [blame]3618 return FoundOpcodesGroup[FormIndex];
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3619}
3620
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3621bool X86InstrInfo::findCommutedOpIndices(MachineInstr *MI,
3622 unsigned &SrcOpIdx1,
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3623 unsigned &SrcOpIdx2) const {
3624 switch (MI->getOpcode()) {
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3625 case X86::CMPPDrri:
3626 case X86::CMPPSrri:
3627 case X86::VCMPPDrri:
3628 case X86::VCMPPSrri:
3629 case X86::VCMPPDYrri:
3630 case X86::VCMPPSYrri: {
3631 // Float comparison can be safely commuted for
3632 // Ordered/Unordered/Equal/NotEqual tests
3633 unsigned Imm = MI->getOperand(3).getImm() & 0x7;
3634 switch (Imm) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3635 case 0x00: // EQUAL
3636 case 0x03: // UNORDERED
3637 case 0x04: // NOT EQUAL
3638 case 0x07: // ORDERED
3639 // The indices of the commutable operands are 1 and 2.
3640 // Assign them to the returned operand indices here.
3641 return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 1, 2);
Simon Pilgrim0629ba12015-01-26 22:29:24 +0000[diff] [blame]3642 }
3643 return false;
3644 }
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3645 default:
Andrew Kaylor4731bea2015-11-06 19:47:25 +0000[diff] [blame]3646 if (isFMA3(MI->getOpcode()))
3647 return findFMA3CommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3648 return TargetInstrInfo::findCommutedOpIndices(MI, SrcOpIdx1, SrcOpIdx2);
3649 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]3650 return false;
Lang Hamesc59a2d02014-04-02 23:57:49 +0000[diff] [blame]3651}
3652
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3653static X86::CondCode getCondFromBranchOpc(unsigned BrOpc) {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3654 switch (BrOpc) {
3655 default: return X86::COND_INVALID;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3656 case X86::JE_1: return X86::COND_E;
3657 case X86::JNE_1: return X86::COND_NE;
3658 case X86::JL_1: return X86::COND_L;
3659 case X86::JLE_1: return X86::COND_LE;
3660 case X86::JG_1: return X86::COND_G;
3661 case X86::JGE_1: return X86::COND_GE;
3662 case X86::JB_1: return X86::COND_B;
3663 case X86::JBE_1: return X86::COND_BE;
3664 case X86::JA_1: return X86::COND_A;
3665 case X86::JAE_1: return X86::COND_AE;
3666 case X86::JS_1: return X86::COND_S;
3667 case X86::JNS_1: return X86::COND_NS;
3668 case X86::JP_1: return X86::COND_P;
3669 case X86::JNP_1: return X86::COND_NP;
3670 case X86::JO_1: return X86::COND_O;
3671 case X86::JNO_1: return X86::COND_NO;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3672 }
3673}
3674
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3675/// Return condition code of a SET opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3676static X86::CondCode getCondFromSETOpc(unsigned Opc) {
3677 switch (Opc) {
3678 default: return X86::COND_INVALID;
3679 case X86::SETAr: case X86::SETAm: return X86::COND_A;
3680 case X86::SETAEr: case X86::SETAEm: return X86::COND_AE;
3681 case X86::SETBr: case X86::SETBm: return X86::COND_B;
3682 case X86::SETBEr: case X86::SETBEm: return X86::COND_BE;
3683 case X86::SETEr: case X86::SETEm: return X86::COND_E;
3684 case X86::SETGr: case X86::SETGm: return X86::COND_G;
3685 case X86::SETGEr: case X86::SETGEm: return X86::COND_GE;
3686 case X86::SETLr: case X86::SETLm: return X86::COND_L;
3687 case X86::SETLEr: case X86::SETLEm: return X86::COND_LE;
3688 case X86::SETNEr: case X86::SETNEm: return X86::COND_NE;
3689 case X86::SETNOr: case X86::SETNOm: return X86::COND_NO;
3690 case X86::SETNPr: case X86::SETNPm: return X86::COND_NP;
3691 case X86::SETNSr: case X86::SETNSm: return X86::COND_NS;
3692 case X86::SETOr: case X86::SETOm: return X86::COND_O;
3693 case X86::SETPr: case X86::SETPm: return X86::COND_P;
3694 case X86::SETSr: case X86::SETSm: return X86::COND_S;
3695 }
3696}
3697
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3698/// Return condition code of a CMov opcode.
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]3699X86::CondCode X86::getCondFromCMovOpc(unsigned Opc) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3700 switch (Opc) {
3701 default: return X86::COND_INVALID;
3702 case X86::CMOVA16rm: case X86::CMOVA16rr: case X86::CMOVA32rm:
3703 case X86::CMOVA32rr: case X86::CMOVA64rm: case X86::CMOVA64rr:
3704 return X86::COND_A;
3705 case X86::CMOVAE16rm: case X86::CMOVAE16rr: case X86::CMOVAE32rm:
3706 case X86::CMOVAE32rr: case X86::CMOVAE64rm: case X86::CMOVAE64rr:
3707 return X86::COND_AE;
3708 case X86::CMOVB16rm: case X86::CMOVB16rr: case X86::CMOVB32rm:
3709 case X86::CMOVB32rr: case X86::CMOVB64rm: case X86::CMOVB64rr:
3710 return X86::COND_B;
3711 case X86::CMOVBE16rm: case X86::CMOVBE16rr: case X86::CMOVBE32rm:
3712 case X86::CMOVBE32rr: case X86::CMOVBE64rm: case X86::CMOVBE64rr:
3713 return X86::COND_BE;
3714 case X86::CMOVE16rm: case X86::CMOVE16rr: case X86::CMOVE32rm:
3715 case X86::CMOVE32rr: case X86::CMOVE64rm: case X86::CMOVE64rr:
3716 return X86::COND_E;
3717 case X86::CMOVG16rm: case X86::CMOVG16rr: case X86::CMOVG32rm:
3718 case X86::CMOVG32rr: case X86::CMOVG64rm: case X86::CMOVG64rr:
3719 return X86::COND_G;
3720 case X86::CMOVGE16rm: case X86::CMOVGE16rr: case X86::CMOVGE32rm:
3721 case X86::CMOVGE32rr: case X86::CMOVGE64rm: case X86::CMOVGE64rr:
3722 return X86::COND_GE;
3723 case X86::CMOVL16rm: case X86::CMOVL16rr: case X86::CMOVL32rm:
3724 case X86::CMOVL32rr: case X86::CMOVL64rm: case X86::CMOVL64rr:
3725 return X86::COND_L;
3726 case X86::CMOVLE16rm: case X86::CMOVLE16rr: case X86::CMOVLE32rm:
3727 case X86::CMOVLE32rr: case X86::CMOVLE64rm: case X86::CMOVLE64rr:
3728 return X86::COND_LE;
3729 case X86::CMOVNE16rm: case X86::CMOVNE16rr: case X86::CMOVNE32rm:
3730 case X86::CMOVNE32rr: case X86::CMOVNE64rm: case X86::CMOVNE64rr:
3731 return X86::COND_NE;
3732 case X86::CMOVNO16rm: case X86::CMOVNO16rr: case X86::CMOVNO32rm:
3733 case X86::CMOVNO32rr: case X86::CMOVNO64rm: case X86::CMOVNO64rr:
3734 return X86::COND_NO;
3735 case X86::CMOVNP16rm: case X86::CMOVNP16rr: case X86::CMOVNP32rm:
3736 case X86::CMOVNP32rr: case X86::CMOVNP64rm: case X86::CMOVNP64rr:
3737 return X86::COND_NP;
3738 case X86::CMOVNS16rm: case X86::CMOVNS16rr: case X86::CMOVNS32rm:
3739 case X86::CMOVNS32rr: case X86::CMOVNS64rm: case X86::CMOVNS64rr:
3740 return X86::COND_NS;
3741 case X86::CMOVO16rm: case X86::CMOVO16rr: case X86::CMOVO32rm:
3742 case X86::CMOVO32rr: case X86::CMOVO64rm: case X86::CMOVO64rr:
3743 return X86::COND_O;
3744 case X86::CMOVP16rm: case X86::CMOVP16rr: case X86::CMOVP32rm:
3745 case X86::CMOVP32rr: case X86::CMOVP64rm: case X86::CMOVP64rr:
3746 return X86::COND_P;
3747 case X86::CMOVS16rm: case X86::CMOVS16rr: case X86::CMOVS32rm:
3748 case X86::CMOVS32rr: case X86::CMOVS64rm: case X86::CMOVS64rr:
3749 return X86::COND_S;
3750 }
3751}
3752
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3753unsigned X86::GetCondBranchFromCond(X86::CondCode CC) {
3754 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3755 default: llvm_unreachable("Illegal condition code!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3756 case X86::COND_E: return X86::JE_1;
3757 case X86::COND_NE: return X86::JNE_1;
3758 case X86::COND_L: return X86::JL_1;
3759 case X86::COND_LE: return X86::JLE_1;
3760 case X86::COND_G: return X86::JG_1;
3761 case X86::COND_GE: return X86::JGE_1;
3762 case X86::COND_B: return X86::JB_1;
3763 case X86::COND_BE: return X86::JBE_1;
3764 case X86::COND_A: return X86::JA_1;
3765 case X86::COND_AE: return X86::JAE_1;
3766 case X86::COND_S: return X86::JS_1;
3767 case X86::COND_NS: return X86::JNS_1;
3768 case X86::COND_P: return X86::JP_1;
3769 case X86::COND_NP: return X86::JNP_1;
3770 case X86::COND_O: return X86::JO_1;
3771 case X86::COND_NO: return X86::JNO_1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3772 }
3773}
3774
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3775/// Return the inverse of the specified condition,
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3776/// e.g. turning COND_E to COND_NE.
3777X86::CondCode X86::GetOppositeBranchCondition(X86::CondCode CC) {
3778 switch (CC) {
Torok Edwinfbcc6632009-07-14 16:55:14 +0000[diff] [blame]3779 default: llvm_unreachable("Illegal condition code!");
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3780 case X86::COND_E: return X86::COND_NE;
3781 case X86::COND_NE: return X86::COND_E;
3782 case X86::COND_L: return X86::COND_GE;
3783 case X86::COND_LE: return X86::COND_G;
3784 case X86::COND_G: return X86::COND_LE;
3785 case X86::COND_GE: return X86::COND_L;
3786 case X86::COND_B: return X86::COND_AE;
3787 case X86::COND_BE: return X86::COND_A;
3788 case X86::COND_A: return X86::COND_BE;
3789 case X86::COND_AE: return X86::COND_B;
3790 case X86::COND_S: return X86::COND_NS;
3791 case X86::COND_NS: return X86::COND_S;
3792 case X86::COND_P: return X86::COND_NP;
3793 case X86::COND_NP: return X86::COND_P;
3794 case X86::COND_O: return X86::COND_NO;
3795 case X86::COND_NO: return X86::COND_O;
3796 }
3797}
3798
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3799/// Assuming the flags are set by MI(a,b), return the condition code if we
3800/// modify the instructions such that flags are set by MI(b,a).
Benjamin Kramerabbfe692012-07-13 13:25:15 +0000[diff] [blame]3801static X86::CondCode getSwappedCondition(X86::CondCode CC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3802 switch (CC) {
3803 default: return X86::COND_INVALID;
3804 case X86::COND_E: return X86::COND_E;
3805 case X86::COND_NE: return X86::COND_NE;
3806 case X86::COND_L: return X86::COND_G;
3807 case X86::COND_LE: return X86::COND_GE;
3808 case X86::COND_G: return X86::COND_L;
3809 case X86::COND_GE: return X86::COND_LE;
3810 case X86::COND_B: return X86::COND_A;
3811 case X86::COND_BE: return X86::COND_AE;
3812 case X86::COND_A: return X86::COND_B;
3813 case X86::COND_AE: return X86::COND_BE;
3814 }
3815}
3816
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3817/// Return a set opcode for the given condition and
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3818/// whether it has memory operand.
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3819unsigned X86::getSETFromCond(CondCode CC, bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3820 static const uint16_t Opc[16][2] = {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3821 { X86::SETAr, X86::SETAm },
3822 { X86::SETAEr, X86::SETAEm },
3823 { X86::SETBr, X86::SETBm },
3824 { X86::SETBEr, X86::SETBEm },
3825 { X86::SETEr, X86::SETEm },
3826 { X86::SETGr, X86::SETGm },
3827 { X86::SETGEr, X86::SETGEm },
3828 { X86::SETLr, X86::SETLm },
3829 { X86::SETLEr, X86::SETLEm },
3830 { X86::SETNEr, X86::SETNEm },
3831 { X86::SETNOr, X86::SETNOm },
3832 { X86::SETNPr, X86::SETNPm },
3833 { X86::SETNSr, X86::SETNSm },
3834 { X86::SETOr, X86::SETOm },
3835 { X86::SETPr, X86::SETPm },
3836 { X86::SETSr, X86::SETSm }
3837 };
3838
Juergen Ributzka2da1bbc2014-06-16 23:58:24 +0000[diff] [blame]3839 assert(CC <= LAST_VALID_COND && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3840 return Opc[CC][HasMemoryOperand ? 1 : 0];
3841}
3842
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]3843/// Return a cmov opcode for the given condition,
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3844/// register size in bytes, and operand type.
Juergen Ributzka6ef06f92014-06-23 21:55:36 +0000[diff] [blame]3845unsigned X86::getCMovFromCond(CondCode CC, unsigned RegBytes,
3846 bool HasMemoryOperand) {
Craig Topperbfcfdeb2012-08-21 08:23:21 +0000[diff] [blame]3847 static const uint16_t Opc[32][3] = {
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3848 { X86::CMOVA16rr, X86::CMOVA32rr, X86::CMOVA64rr },
3849 { X86::CMOVAE16rr, X86::CMOVAE32rr, X86::CMOVAE64rr },
3850 { X86::CMOVB16rr, X86::CMOVB32rr, X86::CMOVB64rr },
3851 { X86::CMOVBE16rr, X86::CMOVBE32rr, X86::CMOVBE64rr },
3852 { X86::CMOVE16rr, X86::CMOVE32rr, X86::CMOVE64rr },
3853 { X86::CMOVG16rr, X86::CMOVG32rr, X86::CMOVG64rr },
3854 { X86::CMOVGE16rr, X86::CMOVGE32rr, X86::CMOVGE64rr },
3855 { X86::CMOVL16rr, X86::CMOVL32rr, X86::CMOVL64rr },
3856 { X86::CMOVLE16rr, X86::CMOVLE32rr, X86::CMOVLE64rr },
3857 { X86::CMOVNE16rr, X86::CMOVNE32rr, X86::CMOVNE64rr },
3858 { X86::CMOVNO16rr, X86::CMOVNO32rr, X86::CMOVNO64rr },
3859 { X86::CMOVNP16rr, X86::CMOVNP32rr, X86::CMOVNP64rr },
3860 { X86::CMOVNS16rr, X86::CMOVNS32rr, X86::CMOVNS64rr },
3861 { X86::CMOVO16rr, X86::CMOVO32rr, X86::CMOVO64rr },
3862 { X86::CMOVP16rr, X86::CMOVP32rr, X86::CMOVP64rr },
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3863 { X86::CMOVS16rr, X86::CMOVS32rr, X86::CMOVS64rr },
3864 { X86::CMOVA16rm, X86::CMOVA32rm, X86::CMOVA64rm },
3865 { X86::CMOVAE16rm, X86::CMOVAE32rm, X86::CMOVAE64rm },
3866 { X86::CMOVB16rm, X86::CMOVB32rm, X86::CMOVB64rm },
3867 { X86::CMOVBE16rm, X86::CMOVBE32rm, X86::CMOVBE64rm },
3868 { X86::CMOVE16rm, X86::CMOVE32rm, X86::CMOVE64rm },
3869 { X86::CMOVG16rm, X86::CMOVG32rm, X86::CMOVG64rm },
3870 { X86::CMOVGE16rm, X86::CMOVGE32rm, X86::CMOVGE64rm },
3871 { X86::CMOVL16rm, X86::CMOVL32rm, X86::CMOVL64rm },
3872 { X86::CMOVLE16rm, X86::CMOVLE32rm, X86::CMOVLE64rm },
3873 { X86::CMOVNE16rm, X86::CMOVNE32rm, X86::CMOVNE64rm },
3874 { X86::CMOVNO16rm, X86::CMOVNO32rm, X86::CMOVNO64rm },
3875 { X86::CMOVNP16rm, X86::CMOVNP32rm, X86::CMOVNP64rm },
3876 { X86::CMOVNS16rm, X86::CMOVNS32rm, X86::CMOVNS64rm },
3877 { X86::CMOVO16rm, X86::CMOVO32rm, X86::CMOVO64rm },
3878 { X86::CMOVP16rm, X86::CMOVP32rm, X86::CMOVP64rm },
3879 { X86::CMOVS16rm, X86::CMOVS32rm, X86::CMOVS64rm }
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3880 };
3881
3882 assert(CC < 16 && "Can only handle standard cond codes");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3883 unsigned Idx = HasMemoryOperand ? 16+CC : CC;
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3884 switch(RegBytes) {
3885 default: llvm_unreachable("Illegal register size!");
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3886 case 2: return Opc[Idx][0];
3887 case 4: return Opc[Idx][1];
3888 case 8: return Opc[Idx][2];
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]3889 }
3890}
3891
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3892bool X86InstrInfo::isUnpredicatedTerminator(const MachineInstr *MI) const {
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3893 if (!MI->isTerminator()) return false;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]3894
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3895 // Conditional branch is a special case.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3896 if (MI->isBranch() && !MI->isBarrier())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3897 return true;
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3898 if (!MI->isPredicable())
Chris Lattnera98c6792008-01-07 01:56:04 +0000[diff] [blame]3899 return true;
3900 return !isPredicated(MI);
Dale Johannesen616627b2007-06-14 22:03:45 +0000[diff] [blame]3901}
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]3902
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]3903bool X86InstrInfo::AnalyzeBranchImpl(
3904 MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
3905 SmallVectorImpl<MachineOperand> &Cond,
3906 SmallVectorImpl<MachineInstr *> &CondBranches, bool AllowModify) const {
3907
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3908 // Start from the bottom of the block and work up, examining the
3909 // terminator instructions.
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3910 MachineBasicBlock::iterator I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3911 MachineBasicBlock::iterator UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3912 while (I != MBB.begin()) {
3913 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]3914 if (I->isDebugValue())
3915 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3916
3917 // Working from the bottom, when we see a non-terminator instruction, we're
3918 // done.
Jakob Stoklund Olesenc30b4dd2010-07-16 17:41:44 +0000[diff] [blame]3919 if (!isUnpredicatedTerminator(I))
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3920 break;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3921
3922 // A terminator that isn't a branch can't easily be handled by this
3923 // analysis.
Evan Cheng7f8e5632011-12-07 07:15:52 +0000[diff] [blame]3924 if (!I->isBranch())
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3925 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3926
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3927 // Handle unconditional branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3928 if (I->getOpcode() == X86::JMP_1) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3929 UnCondBrIter = I;
3930
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3931 if (!AllowModify) {
3932 TBB = I->getOperand(0).getMBB();
Evan Cheng2fa28112009-05-08 06:34:09 +0000[diff] [blame]3933 continue;
Evan Cheng64dfcac2009-02-09 07:14:22 +0000[diff] [blame]3934 }
3935
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3936 // If the block has any instructions after a JMP, delete them.
Benjamin Kramerb6d0bd42014-03-02 12:27:27 +0000[diff] [blame]3937 while (std::next(I) != MBB.end())
3938 std::next(I)->eraseFromParent();
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3939
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3940 Cond.clear();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3941 FBB = nullptr;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3942
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3943 // Delete the JMP if it's equivalent to a fall-through.
3944 if (MBB.isLayoutSuccessor(I->getOperand(0).getMBB())) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]3945 TBB = nullptr;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3946 I->eraseFromParent();
3947 I = MBB.end();
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3948 UnCondBrIter = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3949 continue;
3950 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3951
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3952 // TBB is used to indicate the unconditional destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3953 TBB = I->getOperand(0).getMBB();
3954 continue;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3955 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3956
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3957 // Handle conditional branches.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]3958 X86::CondCode BranchCode = getCondFromBranchOpc(I->getOpcode());
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]3959 if (BranchCode == X86::COND_INVALID)
3960 return true; // Can't handle indirect branch.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]3961
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]3962 // Working from the bottom, handle the first conditional branch.
3963 if (Cond.empty()) {
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3964 MachineBasicBlock *TargetBB = I->getOperand(0).getMBB();
3965 if (AllowModify && UnCondBrIter != MBB.end() &&
3966 MBB.isLayoutSuccessor(TargetBB)) {
3967 // If we can modify the code and it ends in something like:
3968 //
3969 // jCC L1
3970 // jmp L2
3971 // L1:
3972 // ...
3973 // L2:
3974 //
3975 // Then we can change this to:
3976 //
3977 // jnCC L2
3978 // L1:
3979 // ...
3980 // L2:
3981 //
3982 // Which is a bit more efficient.
3983 // We conditionally jump to the fall-through block.
3984 BranchCode = GetOppositeBranchCondition(BranchCode);
3985 unsigned JNCC = GetCondBranchFromCond(BranchCode);
3986 MachineBasicBlock::iterator OldInst = I;
3987
3988 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(JNCC))
3989 .addMBB(UnCondBrIter->getOperand(0).getMBB());
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]3990 BuildMI(MBB, UnCondBrIter, MBB.findDebugLoc(I), get(X86::JMP_1))
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3991 .addMBB(TargetBB);
Evan Cheng4ca4bc62010-04-13 18:50:27 +0000[diff] [blame]3992
3993 OldInst->eraseFromParent();
3994 UnCondBrIter->eraseFromParent();
3995
3996 // Restart the analysis.
3997 UnCondBrIter = MBB.end();
3998 I = MBB.end();
3999 continue;
4000 }
4001
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4002 FBB = TBB;
4003 TBB = I->getOperand(0).getMBB();
4004 Cond.push_back(MachineOperand::CreateImm(BranchCode));
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4005 CondBranches.push_back(I);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4006 continue;
4007 }
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4008
4009 // Handle subsequent conditional branches. Only handle the case where all
4010 // conditional branches branch to the same destination and their condition
4011 // opcodes fit one of the special multi-branch idioms.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4012 assert(Cond.size() == 1);
4013 assert(TBB);
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4014
4015 // Only handle the case where all conditional branches branch to the same
4016 // destination.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4017 if (TBB != I->getOperand(0).getMBB())
4018 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4019
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4020 // If the conditions are the same, we can leave them alone.
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4021 X86::CondCode OldBranchCode = (X86::CondCode)Cond[0].getImm();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4022 if (OldBranchCode == BranchCode)
4023 continue;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4024
4025 // If they differ, see if they fit one of the known patterns. Theoretically,
4026 // we could handle more patterns here, but we shouldn't expect to see them
4027 // if instruction selection has done a reasonable job.
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4028 if ((OldBranchCode == X86::COND_NP &&
4029 BranchCode == X86::COND_E) ||
4030 (OldBranchCode == X86::COND_E &&
4031 BranchCode == X86::COND_NP))
4032 BranchCode = X86::COND_NP_OR_E;
4033 else if ((OldBranchCode == X86::COND_P &&
4034 BranchCode == X86::COND_NE) ||
4035 (OldBranchCode == X86::COND_NE &&
4036 BranchCode == X86::COND_P))
4037 BranchCode = X86::COND_NE_OR_P;
4038 else
4039 return true;
Bill Wendling277381f2009-12-14 06:51:19 +0000[diff] [blame]4040
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4041 // Update the MachineOperand.
4042 Cond[0].setImm(BranchCode);
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4043 CondBranches.push_back(I);
Chris Lattner74436002006-10-30 22:27:23 +0000[diff] [blame]4044 }
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4045
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4046 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4047}
4048
Sanjoy Das6b34a462015-06-15 18:44:21 +0000[diff] [blame]4049bool X86InstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,
4050 MachineBasicBlock *&TBB,
4051 MachineBasicBlock *&FBB,
4052 SmallVectorImpl<MachineOperand> &Cond,
4053 bool AllowModify) const {
4054 SmallVector<MachineInstr *, 4> CondBranches;
4055 return AnalyzeBranchImpl(MBB, TBB, FBB, Cond, CondBranches, AllowModify);
4056}
4057
4058bool X86InstrInfo::AnalyzeBranchPredicate(MachineBasicBlock &MBB,
4059 MachineBranchPredicate &MBP,
4060 bool AllowModify) const {
4061 using namespace std::placeholders;
4062
4063 SmallVector<MachineOperand, 4> Cond;
4064 SmallVector<MachineInstr *, 4> CondBranches;
4065 if (AnalyzeBranchImpl(MBB, MBP.TrueDest, MBP.FalseDest, Cond, CondBranches,
4066 AllowModify))
4067 return true;
4068
4069 if (Cond.size() != 1)
4070 return true;
4071
4072 assert(MBP.TrueDest && "expected!");
4073
4074 if (!MBP.FalseDest)
4075 MBP.FalseDest = MBB.getNextNode();
4076
4077 const TargetRegisterInfo *TRI = &getRegisterInfo();
4078
4079 MachineInstr *ConditionDef = nullptr;
4080 bool SingleUseCondition = true;
4081
4082 for (auto I = std::next(MBB.rbegin()), E = MBB.rend(); I != E; ++I) {
4083 if (I->modifiesRegister(X86::EFLAGS, TRI)) {
4084 ConditionDef = &*I;
4085 break;
4086 }
4087
4088 if (I->readsRegister(X86::EFLAGS, TRI))
4089 SingleUseCondition = false;
4090 }
4091
4092 if (!ConditionDef)
4093 return true;
4094
4095 if (SingleUseCondition) {
4096 for (auto *Succ : MBB.successors())
4097 if (Succ->isLiveIn(X86::EFLAGS))
4098 SingleUseCondition = false;
4099 }
4100
4101 MBP.ConditionDef = ConditionDef;
4102 MBP.SingleUseCondition = SingleUseCondition;
4103
4104 // Currently we only recognize the simple pattern:
4105 //
4106 // test %reg, %reg
4107 // je %label
4108 //
4109 const unsigned TestOpcode =
4110 Subtarget.is64Bit() ? X86::TEST64rr : X86::TEST32rr;
4111
4112 if (ConditionDef->getOpcode() == TestOpcode &&
4113 ConditionDef->getNumOperands() == 3 &&
4114 ConditionDef->getOperand(0).isIdenticalTo(ConditionDef->getOperand(1)) &&
4115 (Cond[0].getImm() == X86::COND_NE || Cond[0].getImm() == X86::COND_E)) {
4116 MBP.LHS = ConditionDef->getOperand(0);
4117 MBP.RHS = MachineOperand::CreateImm(0);
4118 MBP.Predicate = Cond[0].getImm() == X86::COND_NE
4119 ? MachineBranchPredicate::PRED_NE
4120 : MachineBranchPredicate::PRED_EQ;
4121 return false;
4122 }
4123
4124 return true;
4125}
4126
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4127unsigned X86InstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4128 MachineBasicBlock::iterator I = MBB.end();
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4129 unsigned Count = 0;
4130
4131 while (I != MBB.begin()) {
4132 --I;
Dale Johannesen4244d122010-04-02 01:38:09 +0000[diff] [blame]4133 if (I->isDebugValue())
4134 continue;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4135 if (I->getOpcode() != X86::JMP_1 &&
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4136 getCondFromBranchOpc(I->getOpcode()) == X86::COND_INVALID)
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4137 break;
4138 // Remove the branch.
4139 I->eraseFromParent();
4140 I = MBB.end();
4141 ++Count;
4142 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]4143
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4144 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4145}
4146
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4147unsigned
4148X86InstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]4149 MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]4150 DebugLoc DL) const {
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4151 // Shouldn't be a fall through.
4152 assert(TBB && "InsertBranch must not be told to insert a fallthrough");
Chris Lattner6fca75e2006-10-21 05:34:23 +0000[diff] [blame]4153 assert((Cond.size() == 1 || Cond.size() == 0) &&
4154 "X86 branch conditions have one component!");
4155
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4156 if (Cond.empty()) {
4157 // Unconditional branch?
4158 assert(!FBB && "Unconditional branch with multiple successors!");
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4159 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(TBB);
Evan Chenge20dd922007-05-18 00:18:17 +0000[diff] [blame]4160 return 1;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4161 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4162
4163 // Conditional branch.
4164 unsigned Count = 0;
4165 X86::CondCode CC = (X86::CondCode)Cond[0].getImm();
4166 switch (CC) {
4167 case X86::COND_NP_OR_E:
4168 // Synthesize NP_OR_E with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4169 BuildMI(&MBB, DL, get(X86::JNP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4170 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4171 BuildMI(&MBB, DL, get(X86::JE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4172 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4173 break;
4174 case X86::COND_NE_OR_P:
4175 // Synthesize NE_OR_P with two branches.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4176 BuildMI(&MBB, DL, get(X86::JNE_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4177 ++Count;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4178 BuildMI(&MBB, DL, get(X86::JP_1)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4179 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4180 break;
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4181 default: {
4182 unsigned Opc = GetCondBranchFromCond(CC);
Stuart Hastings0125b642010-06-17 22:43:56 +0000[diff] [blame]4183 BuildMI(&MBB, DL, get(Opc)).addMBB(TBB);
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4184 ++Count;
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4185 }
Bill Wendling543ce1f2010-03-05 00:33:59 +0000[diff] [blame]4186 }
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4187 if (FBB) {
4188 // Two-way Conditional branch. Insert the second branch.
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]4189 BuildMI(&MBB, DL, get(X86::JMP_1)).addMBB(FBB);
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]4190 ++Count;
4191 }
4192 return Count;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]4193}
4194
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4195bool X86InstrInfo::
4196canInsertSelect(const MachineBasicBlock &MBB,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]4197 ArrayRef<MachineOperand> Cond,
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4198 unsigned TrueReg, unsigned FalseReg,
4199 int &CondCycles, int &TrueCycles, int &FalseCycles) const {
4200 // Not all subtargets have cmov instructions.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4201 if (!Subtarget.hasCMov())
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4202 return false;
4203 if (Cond.size() != 1)
4204 return false;
4205 // We cannot do the composite conditions, at least not in SSA form.
4206 if ((X86::CondCode)Cond[0].getImm() > X86::COND_S)
4207 return false;
4208
4209 // Check register classes.
4210 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4211 const TargetRegisterClass *RC =
4212 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg));
4213 if (!RC)
4214 return false;
4215
4216 // We have cmov instructions for 16, 32, and 64 bit general purpose registers.
4217 if (X86::GR16RegClass.hasSubClassEq(RC) ||
4218 X86::GR32RegClass.hasSubClassEq(RC) ||
4219 X86::GR64RegClass.hasSubClassEq(RC)) {
4220 // This latency applies to Pentium M, Merom, Wolfdale, Nehalem, and Sandy
4221 // Bridge. Probably Ivy Bridge as well.
4222 CondCycles = 2;
4223 TrueCycles = 2;
4224 FalseCycles = 2;
4225 return true;
4226 }
4227
4228 // Can't do vectors.
4229 return false;
4230}
4231
4232void X86InstrInfo::insertSelect(MachineBasicBlock &MBB,
4233 MachineBasicBlock::iterator I, DebugLoc DL,
Ahmed Bougachac88bf542015-06-11 19:30:37 +0000[diff] [blame]4234 unsigned DstReg, ArrayRef<MachineOperand> Cond,
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4235 unsigned TrueReg, unsigned FalseReg) const {
4236 MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
4237 assert(Cond.size() == 1 && "Invalid Cond array");
4238 unsigned Opc = getCMovFromCond((X86::CondCode)Cond[0].getImm(),
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]4239 MRI.getRegClass(DstReg)->getSize(),
4240 false/*HasMemoryOperand*/);
Jakob Stoklund Olesen49e4d4b2012-07-04 00:09:58 +0000[diff] [blame]4241 BuildMI(MBB, I, DL, get(Opc), DstReg).addReg(FalseReg).addReg(TrueReg);
4242}
4243
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4244/// Test if the given register is a physical h register.
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4245static bool isHReg(unsigned Reg) {
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4246 return X86::GR8_ABCD_HRegClass.contains(Reg);
Dan Gohman7913ea52009-04-15 00:04:23 +0000[diff] [blame]4247}
4248
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4249// Try and copy between VR128/VR64 and GR64 registers.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4250static unsigned CopyToFromAsymmetricReg(unsigned DestReg, unsigned SrcReg,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4251 const X86Subtarget &Subtarget) {
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4252
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4253 // SrcReg(VR128) -> DestReg(GR64)
4254 // SrcReg(VR64) -> DestReg(GR64)
4255 // SrcReg(GR64) -> DestReg(VR128)
4256 // SrcReg(GR64) -> DestReg(VR64)
4257
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4258 bool HasAVX = Subtarget.hasAVX();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4259 bool HasAVX512 = Subtarget.hasAVX512();
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4260 if (X86::GR64RegClass.contains(DestReg)) {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4261 if (X86::VR128XRegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4262 // Copy from a VR128 register to a GR64 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4263 return HasAVX512 ? X86::VMOVPQIto64Zrr: (HasAVX ? X86::VMOVPQIto64rr :
4264 X86::MOVPQIto64rr);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4265 if (X86::VR64RegClass.contains(SrcReg))
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4266 // Copy from a VR64 register to a GR64 register.
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4267 return X86::MMX_MOVD64from64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4268 } else if (X86::GR64RegClass.contains(SrcReg)) {
4269 // Copy from a GR64 register to a VR128 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4270 if (X86::VR128XRegClass.contains(DestReg))
4271 return HasAVX512 ? X86::VMOV64toPQIZrr: (HasAVX ? X86::VMOV64toPQIrr :
4272 X86::MOV64toPQIrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4273 // Copy from a GR64 register to a VR64 register.
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4274 if (X86::VR64RegClass.contains(DestReg))
Bruno Cardoso Lopes9e6dea12015-07-14 20:09:34 +0000[diff] [blame]4275 return X86::MMX_MOVD64to64rr;
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4276 }
4277
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4278 // SrcReg(FR32) -> DestReg(GR32)
4279 // SrcReg(GR32) -> DestReg(FR32)
4280
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4281 if (X86::GR32RegClass.contains(DestReg) && X86::FR32XRegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4282 // Copy from a FR32 register to a GR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4283 return HasAVX512 ? X86::VMOVSS2DIZrr : (HasAVX ? X86::VMOVSS2DIrr : X86::MOVSS2DIrr);
Jakob Stoklund Olesenf05864a2011-09-22 22:45:24 +0000[diff] [blame]4284
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4285 if (X86::FR32XRegClass.contains(DestReg) && X86::GR32RegClass.contains(SrcReg))
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4286 // Copy from a GR32 register to a FR32 register.
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4287 return HasAVX512 ? X86::VMOVDI2SSZrr : (HasAVX ? X86::VMOVDI2SSrr : X86::MOVDI2SSrr);
Anton Korobeynikovc0b36922010-08-27 14:43:06 +0000[diff] [blame]4288 return 0;
4289}
4290
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4291static bool MaskRegClassContains(unsigned Reg) {
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]4292 return X86::VK8RegClass.contains(Reg) ||
4293 X86::VK16RegClass.contains(Reg) ||
Robert Khasanov74acbb72014-07-23 14:49:42 +0000[diff] [blame]4294 X86::VK32RegClass.contains(Reg) ||
4295 X86::VK64RegClass.contains(Reg) ||
Elena Demikhovsky47fc44e2013-12-16 13:52:35 +0000[diff] [blame]4296 X86::VK1RegClass.contains(Reg);
4297}
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4298
4299static bool GRRegClassContains(unsigned Reg) {
4300 return X86::GR64RegClass.contains(Reg) ||
4301 X86::GR32RegClass.contains(Reg) ||
4302 X86::GR16RegClass.contains(Reg) ||
4303 X86::GR8RegClass.contains(Reg);
4304}
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4305static
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4306unsigned copyPhysRegOpcode_AVX512_DQ(unsigned& DestReg, unsigned& SrcReg) {
4307 if (MaskRegClassContains(SrcReg) && X86::GR8RegClass.contains(DestReg)) {
4308 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
4309 return X86::KMOVBrk;
4310 }
4311 if (MaskRegClassContains(DestReg) && X86::GR8RegClass.contains(SrcReg)) {
4312 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
4313 return X86::KMOVBkr;
4314 }
4315 return 0;
4316}
4317
4318static
4319unsigned copyPhysRegOpcode_AVX512_BW(unsigned& DestReg, unsigned& SrcReg) {
4320 if (MaskRegClassContains(SrcReg) && MaskRegClassContains(DestReg))
4321 return X86::KMOVQkk;
4322 if (MaskRegClassContains(SrcReg) && X86::GR32RegClass.contains(DestReg))
4323 return X86::KMOVDrk;
4324 if (MaskRegClassContains(SrcReg) && X86::GR64RegClass.contains(DestReg))
4325 return X86::KMOVQrk;
4326 if (MaskRegClassContains(DestReg) && X86::GR32RegClass.contains(SrcReg))
4327 return X86::KMOVDkr;
4328 if (MaskRegClassContains(DestReg) && X86::GR64RegClass.contains(SrcReg))
4329 return X86::KMOVQkr;
4330 return 0;
4331}
4332
4333static
4334unsigned copyPhysRegOpcode_AVX512(unsigned& DestReg, unsigned& SrcReg,
4335 const X86Subtarget &Subtarget)
4336{
4337 if (Subtarget.hasDQI())
4338 if (auto Opc = copyPhysRegOpcode_AVX512_DQ(DestReg, SrcReg))
4339 return Opc;
4340 if (Subtarget.hasBWI())
4341 if (auto Opc = copyPhysRegOpcode_AVX512_BW(DestReg, SrcReg))
4342 return Opc;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4343 if (X86::VR128XRegClass.contains(DestReg, SrcReg) ||
4344 X86::VR256XRegClass.contains(DestReg, SrcReg) ||
4345 X86::VR512RegClass.contains(DestReg, SrcReg)) {
4346 DestReg = get512BitSuperRegister(DestReg);
4347 SrcReg = get512BitSuperRegister(SrcReg);
4348 return X86::VMOVAPSZrr;
4349 }
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4350 if (MaskRegClassContains(DestReg) && MaskRegClassContains(SrcReg))
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4351 return X86::KMOVWkk;
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4352 if (MaskRegClassContains(DestReg) && GRRegClassContains(SrcReg)) {
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4353 SrcReg = getX86SubSuperRegister(SrcReg, MVT::i32);
4354 return X86::KMOVWkr;
4355 }
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4356 if (GRRegClassContains(DestReg) && MaskRegClassContains(SrcReg)) {
Elena Demikhovsky6270b382013-12-10 11:58:35 +0000[diff] [blame]4357 DestReg = getX86SubSuperRegister(DestReg, MVT::i32);
4358 return X86::KMOVWrk;
4359 }
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4360 return 0;
4361}
4362
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4363void X86InstrInfo::copyPhysReg(MachineBasicBlock &MBB,
4364 MachineBasicBlock::iterator MI, DebugLoc DL,
4365 unsigned DestReg, unsigned SrcReg,
4366 bool KillSrc) const {
4367 // First deal with the normal symmetric copies.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4368 bool HasAVX = Subtarget.hasAVX();
4369 bool HasAVX512 = Subtarget.hasAVX512();
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4370 unsigned Opc = 0;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4371 if (X86::GR64RegClass.contains(DestReg, SrcReg))
4372 Opc = X86::MOV64rr;
4373 else if (X86::GR32RegClass.contains(DestReg, SrcReg))
4374 Opc = X86::MOV32rr;
4375 else if (X86::GR16RegClass.contains(DestReg, SrcReg))
4376 Opc = X86::MOV16rr;
4377 else if (X86::GR8RegClass.contains(DestReg, SrcReg)) {
4378 // Copying to or from a physical H register on x86-64 requires a NOREX
4379 // move. Otherwise use a normal move.
4380 if ((isHReg(DestReg) || isHReg(SrcReg)) &&
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4381 Subtarget.is64Bit()) {
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4382 Opc = X86::MOV8rr_NOREX;
Jakob Stoklund Olesen464fcc02011-10-07 20:15:54 +0000[diff] [blame]4383 // Both operands must be encodable without an REX prefix.
4384 assert(X86::GR8_NOREXRegClass.contains(SrcReg, DestReg) &&
4385 "8-bit H register can not be copied outside GR8_NOREX");
4386 } else
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4387 Opc = X86::MOV8rr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4388 }
4389 else if (X86::VR64RegClass.contains(DestReg, SrcReg))
4390 Opc = X86::MMX_MOVQ64rr;
4391 else if (HasAVX512)
Elena Demikhovsky7c2c9fd2015-11-19 13:13:00 +0000[diff] [blame]4392 Opc = copyPhysRegOpcode_AVX512(DestReg, SrcReg, Subtarget);
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4393 else if (X86::VR128RegClass.contains(DestReg, SrcReg))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4394 Opc = HasAVX ? X86::VMOVAPSrr : X86::MOVAPSrr;
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4395 else if (X86::VR256RegClass.contains(DestReg, SrcReg))
4396 Opc = X86::VMOVAPSYrr;
Elena Demikhovskycf5b1452013-08-11 07:55:09 +0000[diff] [blame]4397 if (!Opc)
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4398 Opc = CopyToFromAsymmetricReg(DestReg, SrcReg, Subtarget);
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4399
4400 if (Opc) {
4401 BuildMI(MBB, MI, DL, get(Opc), DestReg)
4402 .addReg(SrcReg, getKillRegState(KillSrc));
4403 return;
4404 }
4405
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4406 bool FromEFLAGS = SrcReg == X86::EFLAGS;
4407 bool ToEFLAGS = DestReg == X86::EFLAGS;
4408 int Reg = FromEFLAGS ? DestReg : SrcReg;
4409 bool is32 = X86::GR32RegClass.contains(Reg);
4410 bool is64 = X86::GR64RegClass.contains(Reg);
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4411
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4412 if ((FromEFLAGS || ToEFLAGS) && (is32 || is64)) {
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4413 int Mov = is64 ? X86::MOV64rr : X86::MOV32rr;
4414 int Push = is64 ? X86::PUSH64r : X86::PUSH32r;
4415 int PushF = is64 ? X86::PUSHF64 : X86::PUSHF32;
4416 int Pop = is64 ? X86::POP64r : X86::POP32r;
4417 int PopF = is64 ? X86::POPF64 : X86::POPF32;
4418 int AX = is64 ? X86::RAX : X86::EAX;
4419
4420 if (!Subtarget.hasLAHFSAHF()) {
Hans Wennborg7036e502015-12-15 23:21:46 +0000[diff] [blame]4421 assert(Subtarget.is64Bit() &&
4422 "Not having LAHF/SAHF only happens on 64-bit.");
Hans Wennborg5000ce82015-12-04 23:00:33 +0000[diff] [blame]4423 // Moving EFLAGS to / from another register requires a push and a pop.
4424 // Notice that we have to adjust the stack if we don't want to clobber the
4425 // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
4426 if (FromEFLAGS) {
4427 BuildMI(MBB, MI, DL, get(PushF));
4428 BuildMI(MBB, MI, DL, get(Pop), DestReg);
4429 }
4430 if (ToEFLAGS) {
4431 BuildMI(MBB, MI, DL, get(Push))
4432 .addReg(SrcReg, getKillRegState(KillSrc));
4433 BuildMI(MBB, MI, DL, get(PopF));
4434 }
4435 return;
4436 }
4437
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4438 // The flags need to be saved, but saving EFLAGS with PUSHF/POPF is
4439 // inefficient. Instead:
4440 // - Save the overflow flag OF into AL using SETO, and restore it using a
4441 // signed 8-bit addition of AL and INT8_MAX.
4442 // - Save/restore the bottom 8 EFLAGS bits (CF, PF, AF, ZF, SF) to/from AH
4443 // using LAHF/SAHF.
4444 // - When RAX/EAX is live and isn't the destination register, make sure it
4445 // isn't clobbered by PUSH/POP'ing it before and after saving/restoring
4446 // the flags.
4447 // This approach is ~2.25x faster than using PUSHF/POPF.
4448 //
4449 // This is still somewhat inefficient because we don't know which flags are
4450 // actually live inside EFLAGS. Were we able to do a single SETcc instead of
4451 // SETO+LAHF / ADDB+SAHF the code could be 1.02x faster.
4452 //
4453 // PUSHF/POPF is also potentially incorrect because it affects other flags
4454 // such as TF/IF/DF, which LLVM doesn't model.
4455 //
4456 // Notice that we have to adjust the stack if we don't want to clobber the
4457 // first frame index. See X86FrameLowering.cpp - clobbersTheStack.
4458
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4459
Matthias Braun60d69e22015-12-11 19:42:09 +0000[diff] [blame]4460 bool AXDead = (Reg == AX) ||
4461 (MachineBasicBlock::LQR_Dead ==
4462 MBB.computeRegisterLiveness(&getRegisterInfo(), AX, MI));
4463 if (!AXDead) {
4464 // FIXME: If computeRegisterLiveness() reported LQR_Unknown then AX may
4465 // actually be dead. This is not a problem for correctness as we are just
4466 // (unnecessarily) saving+restoring a dead register. However the
4467 // MachineVerifier expects operands that read from dead registers
4468 // to be marked with the "undef" flag.
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4469 BuildMI(MBB, MI, DL, get(Push)).addReg(AX, getKillRegState(true));
Matthias Braun60d69e22015-12-11 19:42:09 +0000[diff] [blame]4470 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4471 if (FromEFLAGS) {
4472 BuildMI(MBB, MI, DL, get(X86::SETOr), X86::AL);
4473 BuildMI(MBB, MI, DL, get(X86::LAHF));
4474 BuildMI(MBB, MI, DL, get(Mov), Reg).addReg(AX);
Craig Topperbab0c762012-08-21 08:29:51 +0000[diff] [blame]4475 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4476 if (ToEFLAGS) {
4477 BuildMI(MBB, MI, DL, get(Mov), AX).addReg(Reg, getKillRegState(KillSrc));
4478 BuildMI(MBB, MI, DL, get(X86::ADD8ri), X86::AL)
4479 .addReg(X86::AL)
4480 .addImm(INT8_MAX);
4481 BuildMI(MBB, MI, DL, get(X86::SAHF));
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4482 }
JF Bastienfa9746d2015-08-10 20:59:36 +0000[diff] [blame]4483 if (!AXDead)
4484 BuildMI(MBB, MI, DL, get(Pop), AX);
4485 return;
Jakob Stoklund Olesen930f8082010-07-08 19:46:25 +0000[diff] [blame]4486 }
4487
4488 DEBUG(dbgs() << "Cannot copy " << RI.getName(SrcReg)
4489 << " to " << RI.getName(DestReg) << '\n');
4490 llvm_unreachable("Cannot emit physreg copy instruction");
4491}
4492
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4493static unsigned getLoadStoreRegOpcode(unsigned Reg,
4494 const TargetRegisterClass *RC,
4495 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4496 const X86Subtarget &STI,
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4497 bool load) {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4498 if (STI.hasAVX512()) {
Andrew Trick8460a3b2013-10-14 22:18:56 +0000[diff] [blame]4499 if (X86::VK8RegClass.hasSubClassEq(RC) ||
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4500 X86::VK16RegClass.hasSubClassEq(RC))
4501 return load ? X86::KMOVWkm : X86::KMOVWmk;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4502 if (RC->getSize() == 4 && X86::FR32XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4503 return load ? X86::VMOVSSZrm : X86::VMOVSSZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4504 if (RC->getSize() == 8 && X86::FR64XRegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4505 return load ? X86::VMOVSDZrm : X86::VMOVSDZmr;
Elena Demikhovsky34586e72013-10-02 12:20:42 +0000[diff] [blame]4506 if (X86::VR512RegClass.hasSubClassEq(RC))
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4507 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
4508 }
4509
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4510 bool HasAVX = STI.hasAVX();
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4511 switch (RC->getSize()) {
Rafael Espindola6635f982010-07-12 03:43:04 +0000[diff] [blame]4512 default:
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4513 llvm_unreachable("Unknown spill size");
4514 case 1:
4515 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass");
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4516 if (STI.is64Bit())
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4517 // Copying to or from a physical H register on x86-64 requires a NOREX
4518 // move. Otherwise use a normal move.
4519 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC))
4520 return load ? X86::MOV8rm_NOREX : X86::MOV8mr_NOREX;
4521 return load ? X86::MOV8rm : X86::MOV8mr;
4522 case 2:
4523 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass");
4524 return load ? X86::MOV16rm : X86::MOV16mr;
4525 case 4:
4526 if (X86::GR32RegClass.hasSubClassEq(RC))
4527 return load ? X86::MOV32rm : X86::MOV32mr;
4528 if (X86::FR32RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4529 return load ?
4530 (HasAVX ? X86::VMOVSSrm : X86::MOVSSrm) :
4531 (HasAVX ? X86::VMOVSSmr : X86::MOVSSmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4532 if (X86::RFP32RegClass.hasSubClassEq(RC))
4533 return load ? X86::LD_Fp32m : X86::ST_Fp32m;
4534 llvm_unreachable("Unknown 4-byte regclass");
4535 case 8:
4536 if (X86::GR64RegClass.hasSubClassEq(RC))
4537 return load ? X86::MOV64rm : X86::MOV64mr;
4538 if (X86::FR64RegClass.hasSubClassEq(RC))
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4539 return load ?
4540 (HasAVX ? X86::VMOVSDrm : X86::MOVSDrm) :
4541 (HasAVX ? X86::VMOVSDmr : X86::MOVSDmr);
Jakob Stoklund Olesen56ce3a02011-06-01 15:32:10 +0000[diff] [blame]4542 if (X86::VR64RegClass.hasSubClassEq(RC))
4543 return load ? X86::MMX_MOVQ64rm : X86::MMX_MOVQ64mr;
4544 if (X86::RFP64RegClass.hasSubClassEq(RC))
4545 return load ? X86::LD_Fp64m : X86::ST_Fp64m;
4546 llvm_unreachable("Unknown 8-byte regclass");
4547 case 10:
4548 assert(X86::RFP80RegClass.hasSubClassEq(RC) && "Unknown 10-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4549 return load ? X86::LD_Fp80m : X86::ST_FpP80m;
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4550 case 16: {
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4551 assert((X86::VR128RegClass.hasSubClassEq(RC) ||
4552 X86::VR128XRegClass.hasSubClassEq(RC))&& "Unknown 16-byte regclass");
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4553 // If stack is realigned we can use aligned stores.
4554 if (isStackAligned)
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4555 return load ?
4556 (HasAVX ? X86::VMOVAPSrm : X86::MOVAPSrm) :
4557 (HasAVX ? X86::VMOVAPSmr : X86::MOVAPSmr);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4558 else
Bruno Cardoso Lopesdb520db2011-08-31 03:04:09 +0000[diff] [blame]4559 return load ?
4560 (HasAVX ? X86::VMOVUPSrm : X86::MOVUPSrm) :
4561 (HasAVX ? X86::VMOVUPSmr : X86::MOVUPSmr);
4562 }
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4563 case 32:
Elena Demikhovsky0a74b7d2013-11-14 11:29:27 +0000[diff] [blame]4564 assert((X86::VR256RegClass.hasSubClassEq(RC) ||
4565 X86::VR256XRegClass.hasSubClassEq(RC)) && "Unknown 32-byte regclass");
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]4566 // If stack is realigned we can use aligned stores.
4567 if (isStackAligned)
4568 return load ? X86::VMOVAPSYrm : X86::VMOVAPSYmr;
4569 else
4570 return load ? X86::VMOVUPSYrm : X86::VMOVUPSYmr;
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4571 case 64:
4572 assert(X86::VR512RegClass.hasSubClassEq(RC) && "Unknown 64-byte regclass");
4573 if (isStackAligned)
4574 return load ? X86::VMOVAPSZrm : X86::VMOVAPSZmr;
4575 else
4576 return load ? X86::VMOVUPSZrm : X86::VMOVUPSZmr;
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4577 }
4578}
4579
Sanjoy Dasb666ea32015-06-15 18:44:14 +0000[diff] [blame]4580bool X86InstrInfo::getMemOpBaseRegImmOfs(MachineInstr *MemOp, unsigned &BaseReg,
4581 unsigned &Offset,
4582 const TargetRegisterInfo *TRI) const {
4583 const MCInstrDesc &Desc = MemOp->getDesc();
4584 int MemRefBegin = X86II::getMemoryOperandNo(Desc.TSFlags, MemOp->getOpcode());
4585 if (MemRefBegin < 0)
4586 return false;
4587
4588 MemRefBegin += X86II::getOperandBias(Desc);
4589
4590 BaseReg = MemOp->getOperand(MemRefBegin + X86::AddrBaseReg).getReg();
4591 if (MemOp->getOperand(MemRefBegin + X86::AddrScaleAmt).getImm() != 1)
4592 return false;
4593
4594 if (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() !=
4595 X86::NoRegister)
4596 return false;
4597
4598 const MachineOperand &DispMO = MemOp->getOperand(MemRefBegin + X86::AddrDisp);
4599
4600 // Displacement can be symbolic
4601 if (!DispMO.isImm())
4602 return false;
4603
4604 Offset = DispMO.getImm();
4605
4606 return (MemOp->getOperand(MemRefBegin + X86::AddrIndexReg).getReg() ==
4607 X86::NoRegister);
4608}
4609
Dan Gohman29869722009-04-27 16:41:36 +0000[diff] [blame]4610static unsigned getStoreRegOpcode(unsigned SrcReg,
4611 const TargetRegisterClass *RC,
4612 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4613 const X86Subtarget &STI) {
4614 return getLoadStoreRegOpcode(SrcReg, RC, isStackAligned, STI, false);
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4615}
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4616
Rafael Espindolae302f832010-06-12 20:13:29 +0000[diff] [blame]4617
4618static unsigned getLoadRegOpcode(unsigned DestReg,
4619 const TargetRegisterClass *RC,
4620 bool isStackAligned,
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4621 const X86Subtarget &STI) {
4622 return getLoadStoreRegOpcode(DestReg, RC, isStackAligned, STI, true);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4623}
4624
4625void X86InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
4626 MachineBasicBlock::iterator MI,
4627 unsigned SrcReg, bool isKill, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4628 const TargetRegisterClass *RC,
4629 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4630 const MachineFunction &MF = *MBB.getParent();
Jakob Stoklund Olesenc3c05ed2010-07-27 04:16:58 +0000[diff] [blame]4631 assert(MF.getFrameInfo()->getObjectSize(FrameIdx) >= RC->getSize() &&
4632 "Stack slot too small for store");
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4633 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4634 bool isAligned =
4635 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4636 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4637 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4638 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4639 addFrameReference(BuildMI(MBB, MI, DL, get(Opc)), FrameIdx)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4640 .addReg(SrcReg, getKillRegState(isKill));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4641}
4642
4643void X86InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
4644 bool isKill,
4645 SmallVectorImpl<MachineOperand> &Addr,
4646 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4647 MachineInstr::mmo_iterator MMOBegin,
4648 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4649 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4650 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4651 bool isAligned = MMOBegin != MMOEnd &&
4652 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4653 unsigned Opc = getStoreRegOpcode(SrcReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4654 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4655 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc));
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4656 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4657 MIB.addOperand(Addr[i]);
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]4658 MIB.addReg(SrcReg, getKillRegState(isKill));
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4659 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4660 NewMIs.push_back(MIB);
4661}
4662
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4663
4664void X86InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4665 MachineBasicBlock::iterator MI,
4666 unsigned DestReg, int FrameIdx,
Evan Chengefb126a2010-05-06 19:06:44 +0000[diff] [blame]4667 const TargetRegisterClass *RC,
4668 const TargetRegisterInfo *TRI) const {
Anton Korobeynikovb7a49922008-07-19 06:30:51 +0000[diff] [blame]4669 const MachineFunction &MF = *MBB.getParent();
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4670 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]4671 bool isAligned =
4672 (Subtarget.getFrameLowering()->getStackAlignment() >= Alignment) ||
4673 RI.canRealignStack(MF);
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4674 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Dale Johannesene5a41342010-01-26 00:03:12 +0000[diff] [blame]4675 DebugLoc DL = MBB.findDebugLoc(MI);
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]4676 addFrameReference(BuildMI(MBB, MI, DL, get(Opc), DestReg), FrameIdx);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4677}
4678
4679void X86InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Evan Cheng7d98a482008-07-03 09:09:37 +0000[diff] [blame]4680 SmallVectorImpl<MachineOperand> &Addr,
4681 const TargetRegisterClass *RC,
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4682 MachineInstr::mmo_iterator MMOBegin,
4683 MachineInstr::mmo_iterator MMOEnd,
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4684 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Elena Demikhovsky3ce8dbb2013-08-18 13:08:57 +0000[diff] [blame]4685 unsigned Alignment = std::max<uint32_t>(RC->getSize(), 16);
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]4686 bool isAligned = MMOBegin != MMOEnd &&
4687 (*MMOBegin)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]4688 unsigned Opc = getLoadRegOpcode(DestReg, RC, isAligned, Subtarget);
Chris Lattner6f306d72010-04-02 20:16:16 +0000[diff] [blame]4689 DebugLoc DL;
Dale Johannesen6b8c76a2009-02-12 23:08:38 +0000[diff] [blame]4690 MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4691 for (unsigned i = 0, e = Addr.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]4692 MIB.addOperand(Addr[i]);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]4693 (*MIB).setMemRefs(MMOBegin, MMOEnd);
Owen Andersoneee14602008-01-01 21:11:32 +0000[diff] [blame]4694 NewMIs.push_back(MIB);
4695}
4696
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4697bool X86InstrInfo::
4698analyzeCompare(const MachineInstr *MI, unsigned &SrcReg, unsigned &SrcReg2,
4699 int &CmpMask, int &CmpValue) const {
4700 switch (MI->getOpcode()) {
4701 default: break;
4702 case X86::CMP64ri32:
4703 case X86::CMP64ri8:
4704 case X86::CMP32ri:
4705 case X86::CMP32ri8:
4706 case X86::CMP16ri:
4707 case X86::CMP16ri8:
4708 case X86::CMP8ri:
4709 SrcReg = MI->getOperand(0).getReg();
4710 SrcReg2 = 0;
4711 CmpMask = ~0;
4712 CmpValue = MI->getOperand(1).getImm();
4713 return true;
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4714 // A SUB can be used to perform comparison.
4715 case X86::SUB64rm:
4716 case X86::SUB32rm:
4717 case X86::SUB16rm:
4718 case X86::SUB8rm:
4719 SrcReg = MI->getOperand(1).getReg();
4720 SrcReg2 = 0;
4721 CmpMask = ~0;
4722 CmpValue = 0;
4723 return true;
4724 case X86::SUB64rr:
4725 case X86::SUB32rr:
4726 case X86::SUB16rr:
4727 case X86::SUB8rr:
4728 SrcReg = MI->getOperand(1).getReg();
4729 SrcReg2 = MI->getOperand(2).getReg();
4730 CmpMask = ~0;
4731 CmpValue = 0;
4732 return true;
4733 case X86::SUB64ri32:
4734 case X86::SUB64ri8:
4735 case X86::SUB32ri:
4736 case X86::SUB32ri8:
4737 case X86::SUB16ri:
4738 case X86::SUB16ri8:
4739 case X86::SUB8ri:
4740 SrcReg = MI->getOperand(1).getReg();
4741 SrcReg2 = 0;
4742 CmpMask = ~0;
4743 CmpValue = MI->getOperand(2).getImm();
4744 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4745 case X86::CMP64rr:
4746 case X86::CMP32rr:
4747 case X86::CMP16rr:
4748 case X86::CMP8rr:
4749 SrcReg = MI->getOperand(0).getReg();
4750 SrcReg2 = MI->getOperand(1).getReg();
4751 CmpMask = ~0;
4752 CmpValue = 0;
4753 return true;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4754 case X86::TEST8rr:
4755 case X86::TEST16rr:
4756 case X86::TEST32rr:
4757 case X86::TEST64rr:
4758 SrcReg = MI->getOperand(0).getReg();
4759 if (MI->getOperand(1).getReg() != SrcReg) return false;
4760 // Compare against zero.
4761 SrcReg2 = 0;
4762 CmpMask = ~0;
4763 CmpValue = 0;
4764 return true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4765 }
4766 return false;
4767}
4768
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4769/// Check whether the first instruction, whose only
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4770/// purpose is to update flags, can be made redundant.
4771/// CMPrr can be made redundant by SUBrr if the operands are the same.
4772/// This function can be extended later on.
4773/// SrcReg, SrcRegs: register operands for FlagI.
4774/// ImmValue: immediate for FlagI if it takes an immediate.
4775inline static bool isRedundantFlagInstr(MachineInstr *FlagI, unsigned SrcReg,
4776 unsigned SrcReg2, int ImmValue,
4777 MachineInstr *OI) {
4778 if (((FlagI->getOpcode() == X86::CMP64rr &&
4779 OI->getOpcode() == X86::SUB64rr) ||
4780 (FlagI->getOpcode() == X86::CMP32rr &&
4781 OI->getOpcode() == X86::SUB32rr)||
4782 (FlagI->getOpcode() == X86::CMP16rr &&
4783 OI->getOpcode() == X86::SUB16rr)||
4784 (FlagI->getOpcode() == X86::CMP8rr &&
4785 OI->getOpcode() == X86::SUB8rr)) &&
4786 ((OI->getOperand(1).getReg() == SrcReg &&
4787 OI->getOperand(2).getReg() == SrcReg2) ||
4788 (OI->getOperand(1).getReg() == SrcReg2 &&
4789 OI->getOperand(2).getReg() == SrcReg)))
4790 return true;
4791
4792 if (((FlagI->getOpcode() == X86::CMP64ri32 &&
4793 OI->getOpcode() == X86::SUB64ri32) ||
4794 (FlagI->getOpcode() == X86::CMP64ri8 &&
4795 OI->getOpcode() == X86::SUB64ri8) ||
4796 (FlagI->getOpcode() == X86::CMP32ri &&
4797 OI->getOpcode() == X86::SUB32ri) ||
4798 (FlagI->getOpcode() == X86::CMP32ri8 &&
4799 OI->getOpcode() == X86::SUB32ri8) ||
4800 (FlagI->getOpcode() == X86::CMP16ri &&
4801 OI->getOpcode() == X86::SUB16ri) ||
4802 (FlagI->getOpcode() == X86::CMP16ri8 &&
4803 OI->getOpcode() == X86::SUB16ri8) ||
4804 (FlagI->getOpcode() == X86::CMP8ri &&
4805 OI->getOpcode() == X86::SUB8ri)) &&
4806 OI->getOperand(1).getReg() == SrcReg &&
4807 OI->getOperand(2).getImm() == ImmValue)
4808 return true;
4809 return false;
4810}
4811
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4812/// Check whether the definition can be converted
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4813/// to remove a comparison against zero.
4814inline static bool isDefConvertible(MachineInstr *MI) {
4815 switch (MI->getOpcode()) {
4816 default: return false;
David Majnemer7ea2a522013-05-22 08:13:02 +0000[diff] [blame]4817
4818 // The shift instructions only modify ZF if their shift count is non-zero.
4819 // N.B.: The processor truncates the shift count depending on the encoding.
4820 case X86::SAR8ri: case X86::SAR16ri: case X86::SAR32ri:case X86::SAR64ri:
4821 case X86::SHR8ri: case X86::SHR16ri: case X86::SHR32ri:case X86::SHR64ri:
4822 return getTruncatedShiftCount(MI, 2) != 0;
4823
4824 // Some left shift instructions can be turned into LEA instructions but only
4825 // if their flags aren't used. Avoid transforming such instructions.
4826 case X86::SHL8ri: case X86::SHL16ri: case X86::SHL32ri:case X86::SHL64ri:{
4827 unsigned ShAmt = getTruncatedShiftCount(MI, 2);
4828 if (isTruncatedShiftCountForLEA(ShAmt)) return false;
4829 return ShAmt != 0;
4830 }
4831
4832 case X86::SHRD16rri8:case X86::SHRD32rri8:case X86::SHRD64rri8:
4833 case X86::SHLD16rri8:case X86::SHLD32rri8:case X86::SHLD64rri8:
4834 return getTruncatedShiftCount(MI, 3) != 0;
4835
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4836 case X86::SUB64ri32: case X86::SUB64ri8: case X86::SUB32ri:
4837 case X86::SUB32ri8: case X86::SUB16ri: case X86::SUB16ri8:
4838 case X86::SUB8ri: case X86::SUB64rr: case X86::SUB32rr:
4839 case X86::SUB16rr: case X86::SUB8rr: case X86::SUB64rm:
4840 case X86::SUB32rm: case X86::SUB16rm: case X86::SUB8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4841 case X86::DEC64r: case X86::DEC32r: case X86::DEC16r: case X86::DEC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4842 case X86::ADD64ri32: case X86::ADD64ri8: case X86::ADD32ri:
4843 case X86::ADD32ri8: case X86::ADD16ri: case X86::ADD16ri8:
4844 case X86::ADD8ri: case X86::ADD64rr: case X86::ADD32rr:
4845 case X86::ADD16rr: case X86::ADD8rr: case X86::ADD64rm:
4846 case X86::ADD32rm: case X86::ADD16rm: case X86::ADD8rm:
Craig Topper5b08cf72012-12-17 04:55:07 +0000[diff] [blame]4847 case X86::INC64r: case X86::INC32r: case X86::INC16r: case X86::INC8r:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4848 case X86::AND64ri32: case X86::AND64ri8: case X86::AND32ri:
4849 case X86::AND32ri8: case X86::AND16ri: case X86::AND16ri8:
4850 case X86::AND8ri: case X86::AND64rr: case X86::AND32rr:
4851 case X86::AND16rr: case X86::AND8rr: case X86::AND64rm:
4852 case X86::AND32rm: case X86::AND16rm: case X86::AND8rm:
4853 case X86::XOR64ri32: case X86::XOR64ri8: case X86::XOR32ri:
4854 case X86::XOR32ri8: case X86::XOR16ri: case X86::XOR16ri8:
4855 case X86::XOR8ri: case X86::XOR64rr: case X86::XOR32rr:
4856 case X86::XOR16rr: case X86::XOR8rr: case X86::XOR64rm:
4857 case X86::XOR32rm: case X86::XOR16rm: case X86::XOR8rm:
4858 case X86::OR64ri32: case X86::OR64ri8: case X86::OR32ri:
4859 case X86::OR32ri8: case X86::OR16ri: case X86::OR16ri8:
4860 case X86::OR8ri: case X86::OR64rr: case X86::OR32rr:
4861 case X86::OR16rr: case X86::OR8rr: case X86::OR64rm:
4862 case X86::OR32rm: case X86::OR16rm: case X86::OR8rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4863 case X86::NEG8r: case X86::NEG16r: case X86::NEG32r: case X86::NEG64r:
4864 case X86::SAR8r1: case X86::SAR16r1: case X86::SAR32r1:case X86::SAR64r1:
4865 case X86::SHR8r1: case X86::SHR16r1: case X86::SHR32r1:case X86::SHR64r1:
4866 case X86::SHL8r1: case X86::SHL16r1: case X86::SHL32r1:case X86::SHL64r1:
4867 case X86::ADC32ri: case X86::ADC32ri8:
4868 case X86::ADC32rr: case X86::ADC64ri32:
4869 case X86::ADC64ri8: case X86::ADC64rr:
4870 case X86::SBB32ri: case X86::SBB32ri8:
4871 case X86::SBB32rr: case X86::SBB64ri32:
4872 case X86::SBB64ri8: case X86::SBB64rr:
Craig Topperf3ff6ae2012-12-17 05:12:30 +0000[diff] [blame]4873 case X86::ANDN32rr: case X86::ANDN32rm:
4874 case X86::ANDN64rr: case X86::ANDN64rm:
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]4875 case X86::BEXTR32rr: case X86::BEXTR64rr:
4876 case X86::BEXTR32rm: case X86::BEXTR64rm:
4877 case X86::BLSI32rr: case X86::BLSI32rm:
4878 case X86::BLSI64rr: case X86::BLSI64rm:
4879 case X86::BLSMSK32rr:case X86::BLSMSK32rm:
4880 case X86::BLSMSK64rr:case X86::BLSMSK64rm:
4881 case X86::BLSR32rr: case X86::BLSR32rm:
4882 case X86::BLSR64rr: case X86::BLSR64rm:
4883 case X86::BZHI32rr: case X86::BZHI32rm:
4884 case X86::BZHI64rr: case X86::BZHI64rm:
4885 case X86::LZCNT16rr: case X86::LZCNT16rm:
4886 case X86::LZCNT32rr: case X86::LZCNT32rm:
4887 case X86::LZCNT64rr: case X86::LZCNT64rm:
4888 case X86::POPCNT16rr:case X86::POPCNT16rm:
4889 case X86::POPCNT32rr:case X86::POPCNT32rm:
4890 case X86::POPCNT64rr:case X86::POPCNT64rm:
4891 case X86::TZCNT16rr: case X86::TZCNT16rm:
4892 case X86::TZCNT32rr: case X86::TZCNT32rm:
4893 case X86::TZCNT64rr: case X86::TZCNT64rm:
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4894 return true;
4895 }
4896}
4897
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4898/// Check whether the use can be converted to remove a comparison against zero.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4899static X86::CondCode isUseDefConvertible(MachineInstr *MI) {
4900 switch (MI->getOpcode()) {
4901 default: return X86::COND_INVALID;
4902 case X86::LZCNT16rr: case X86::LZCNT16rm:
4903 case X86::LZCNT32rr: case X86::LZCNT32rm:
4904 case X86::LZCNT64rr: case X86::LZCNT64rm:
4905 return X86::COND_B;
4906 case X86::POPCNT16rr:case X86::POPCNT16rm:
4907 case X86::POPCNT32rr:case X86::POPCNT32rm:
4908 case X86::POPCNT64rr:case X86::POPCNT64rm:
4909 return X86::COND_E;
4910 case X86::TZCNT16rr: case X86::TZCNT16rm:
4911 case X86::TZCNT32rr: case X86::TZCNT32rm:
4912 case X86::TZCNT64rr: case X86::TZCNT64rm:
4913 return X86::COND_B;
4914 }
4915}
4916
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]4917/// Check if there exists an earlier instruction that
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4918/// operates on the same source operands and sets flags in the same way as
4919/// Compare; remove Compare if possible.
4920bool X86InstrInfo::
4921optimizeCompareInstr(MachineInstr *CmpInstr, unsigned SrcReg, unsigned SrcReg2,
4922 int CmpMask, int CmpValue,
4923 const MachineRegisterInfo *MRI) const {
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4924 // Check whether we can replace SUB with CMP.
4925 unsigned NewOpcode = 0;
4926 switch (CmpInstr->getOpcode()) {
4927 default: break;
4928 case X86::SUB64ri32:
4929 case X86::SUB64ri8:
4930 case X86::SUB32ri:
4931 case X86::SUB32ri8:
4932 case X86::SUB16ri:
4933 case X86::SUB16ri8:
4934 case X86::SUB8ri:
4935 case X86::SUB64rm:
4936 case X86::SUB32rm:
4937 case X86::SUB16rm:
4938 case X86::SUB8rm:
4939 case X86::SUB64rr:
4940 case X86::SUB32rr:
4941 case X86::SUB16rr:
4942 case X86::SUB8rr: {
4943 if (!MRI->use_nodbg_empty(CmpInstr->getOperand(0).getReg()))
4944 return false;
4945 // There is no use of the destination register, we can replace SUB with CMP.
4946 switch (CmpInstr->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]4947 default: llvm_unreachable("Unreachable!");
Manman Ren1be131b2012-08-08 00:51:41 +0000[diff] [blame]4948 case X86::SUB64rm: NewOpcode = X86::CMP64rm; break;
4949 case X86::SUB32rm: NewOpcode = X86::CMP32rm; break;
4950 case X86::SUB16rm: NewOpcode = X86::CMP16rm; break;
4951 case X86::SUB8rm: NewOpcode = X86::CMP8rm; break;
4952 case X86::SUB64rr: NewOpcode = X86::CMP64rr; break;
4953 case X86::SUB32rr: NewOpcode = X86::CMP32rr; break;
4954 case X86::SUB16rr: NewOpcode = X86::CMP16rr; break;
4955 case X86::SUB8rr: NewOpcode = X86::CMP8rr; break;
4956 case X86::SUB64ri32: NewOpcode = X86::CMP64ri32; break;
4957 case X86::SUB64ri8: NewOpcode = X86::CMP64ri8; break;
4958 case X86::SUB32ri: NewOpcode = X86::CMP32ri; break;
4959 case X86::SUB32ri8: NewOpcode = X86::CMP32ri8; break;
4960 case X86::SUB16ri: NewOpcode = X86::CMP16ri; break;
4961 case X86::SUB16ri8: NewOpcode = X86::CMP16ri8; break;
4962 case X86::SUB8ri: NewOpcode = X86::CMP8ri; break;
4963 }
4964 CmpInstr->setDesc(get(NewOpcode));
4965 CmpInstr->RemoveOperand(0);
4966 // Fall through to optimize Cmp if Cmp is CMPrr or CMPri.
4967 if (NewOpcode == X86::CMP64rm || NewOpcode == X86::CMP32rm ||
4968 NewOpcode == X86::CMP16rm || NewOpcode == X86::CMP8rm)
4969 return false;
4970 }
4971 }
4972
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]4973 // Get the unique definition of SrcReg.
4974 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg);
4975 if (!MI) return false;
4976
4977 // CmpInstr is the first instruction of the BB.
4978 MachineBasicBlock::iterator I = CmpInstr, Def = MI;
4979
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4980 // If we are comparing against zero, check whether we can use MI to update
4981 // EFLAGS. If MI is not in the same BB as CmpInstr, do not optimize.
4982 bool IsCmpZero = (SrcReg2 == 0 && CmpValue == 0);
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4983 if (IsCmpZero && MI->getParent() != CmpInstr->getParent())
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]4984 return false;
4985
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]4986 // If we have a use of the source register between the def and our compare
4987 // instruction we can eliminate the compare iff the use sets EFLAGS in the
4988 // right way.
4989 bool ShouldUpdateCC = false;
4990 X86::CondCode NewCC = X86::COND_INVALID;
4991 if (IsCmpZero && !isDefConvertible(MI)) {
4992 // Scan forward from the use until we hit the use we're looking for or the
4993 // compare instruction.
4994 for (MachineBasicBlock::iterator J = MI;; ++J) {
4995 // Do we have a convertible instruction?
4996 NewCC = isUseDefConvertible(J);
4997 if (NewCC != X86::COND_INVALID && J->getOperand(1).isReg() &&
4998 J->getOperand(1).getReg() == SrcReg) {
4999 assert(J->definesRegister(X86::EFLAGS) && "Must be an EFLAGS def!");
5000 ShouldUpdateCC = true; // Update CC later on.
5001 // This is not a def of SrcReg, but still a def of EFLAGS. Keep going
5002 // with the new def.
5003 MI = Def = J;
5004 break;
5005 }
5006
5007 if (J == I)
5008 return false;
5009 }
5010 }
5011
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5012 // We are searching for an earlier instruction that can make CmpInstr
5013 // redundant and that instruction will be saved in Sub.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5014 MachineInstr *Sub = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5015 const TargetRegisterInfo *TRI = &getRegisterInfo();
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5016
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5017 // We iterate backward, starting from the instruction before CmpInstr and
5018 // stop when reaching the definition of a source register or done with the BB.
5019 // RI points to the instruction before CmpInstr.
5020 // If the definition is in this basic block, RE points to the definition;
5021 // otherwise, RE is the rend of the basic block.
5022 MachineBasicBlock::reverse_iterator
5023 RI = MachineBasicBlock::reverse_iterator(I),
5024 RE = CmpInstr->getParent() == MI->getParent() ?
5025 MachineBasicBlock::reverse_iterator(++Def) /* points to MI */ :
5026 CmpInstr->getParent()->rend();
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5027 MachineInstr *Movr0Inst = nullptr;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5028 for (; RI != RE; ++RI) {
5029 MachineInstr *Instr = &*RI;
5030 // Check whether CmpInstr can be made redundant by the current instruction.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5031 if (!IsCmpZero &&
5032 isRedundantFlagInstr(CmpInstr, SrcReg, SrcReg2, CmpValue, Instr)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5033 Sub = Instr;
5034 break;
5035 }
5036
5037 if (Instr->modifiesRegister(X86::EFLAGS, TRI) ||
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5038 Instr->readsRegister(X86::EFLAGS, TRI)) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5039 // This instruction modifies or uses EFLAGS.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5040
5041 // MOV32r0 etc. are implemented with xor which clobbers condition code.
5042 // They are safe to move up, if the definition to EFLAGS is dead and
5043 // earlier instructions do not read or write EFLAGS.
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5044 if (!Movr0Inst && Instr->getOpcode() == X86::MOV32r0 &&
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5045 Instr->registerDefIsDead(X86::EFLAGS, TRI)) {
5046 Movr0Inst = Instr;
5047 continue;
5048 }
5049
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5050 // We can't remove CmpInstr.
5051 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5052 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5053 }
5054
5055 // Return false if no candidates exist.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5056 if (!IsCmpZero && !Sub)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5057 return false;
5058
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5059 bool IsSwapped = (SrcReg2 != 0 && Sub->getOperand(1).getReg() == SrcReg2 &&
5060 Sub->getOperand(2).getReg() == SrcReg);
5061
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5062 // Scan forward from the instruction after CmpInstr for uses of EFLAGS.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5063 // It is safe to remove CmpInstr if EFLAGS is redefined or killed.
5064 // If we are done with the basic block, we need to check whether EFLAGS is
5065 // live-out.
5066 bool IsSafe = false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5067 SmallVector<std::pair<MachineInstr*, unsigned /*NewOpc*/>, 4> OpsToUpdate;
5068 MachineBasicBlock::iterator E = CmpInstr->getParent()->end();
5069 for (++I; I != E; ++I) {
5070 const MachineInstr &Instr = *I;
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5071 bool ModifyEFLAGS = Instr.modifiesRegister(X86::EFLAGS, TRI);
5072 bool UseEFLAGS = Instr.readsRegister(X86::EFLAGS, TRI);
5073 // We should check the usage if this instruction uses and updates EFLAGS.
5074 if (!UseEFLAGS && ModifyEFLAGS) {
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5075 // It is safe to remove CmpInstr if EFLAGS is updated again.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5076 IsSafe = true;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5077 break;
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5078 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5079 if (!UseEFLAGS && !ModifyEFLAGS)
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5080 continue;
5081
5082 // EFLAGS is used by this instruction.
Nick Lewycky0a9a8662014-06-04 07:45:54 +0000[diff] [blame]5083 X86::CondCode OldCC = X86::COND_INVALID;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5084 bool OpcIsSET = false;
5085 if (IsCmpZero || IsSwapped) {
5086 // We decode the condition code from opcode.
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5087 if (Instr.isBranch())
5088 OldCC = getCondFromBranchOpc(Instr.getOpcode());
5089 else {
5090 OldCC = getCondFromSETOpc(Instr.getOpcode());
5091 if (OldCC != X86::COND_INVALID)
5092 OpcIsSET = true;
5093 else
Michael Liao32376622012-09-20 03:06:15 +0000[diff] [blame]5094 OldCC = X86::getCondFromCMovOpc(Instr.getOpcode());
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5095 }
5096 if (OldCC == X86::COND_INVALID) return false;
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5097 }
5098 if (IsCmpZero) {
5099 switch (OldCC) {
5100 default: break;
5101 case X86::COND_A: case X86::COND_AE:
5102 case X86::COND_B: case X86::COND_BE:
5103 case X86::COND_G: case X86::COND_GE:
5104 case X86::COND_L: case X86::COND_LE:
5105 case X86::COND_O: case X86::COND_NO:
5106 // CF and OF are used, we can't perform this optimization.
5107 return false;
5108 }
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5109
5110 // If we're updating the condition code check if we have to reverse the
5111 // condition.
5112 if (ShouldUpdateCC)
5113 switch (OldCC) {
5114 default:
5115 return false;
5116 case X86::COND_E:
5117 break;
5118 case X86::COND_NE:
5119 NewCC = GetOppositeBranchCondition(NewCC);
5120 break;
5121 }
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5122 } else if (IsSwapped) {
5123 // If we have SUB(r1, r2) and CMP(r2, r1), the condition code needs
5124 // to be changed from r2 > r1 to r1 < r2, from r2 < r1 to r1 > r2, etc.
5125 // We swap the condition code and synthesize the new opcode.
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5126 NewCC = getSwappedCondition(OldCC);
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5127 if (NewCC == X86::COND_INVALID) return false;
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5128 }
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5129
Benjamin Kramer594f9632014-05-14 16:14:45 +0000[diff] [blame]5130 if ((ShouldUpdateCC || IsSwapped) && NewCC != OldCC) {
Manman Ren5f6fa422012-07-09 18:57:12 +0000[diff] [blame]5131 // Synthesize the new opcode.
5132 bool HasMemoryOperand = Instr.hasOneMemOperand();
5133 unsigned NewOpc;
5134 if (Instr.isBranch())
5135 NewOpc = GetCondBranchFromCond(NewCC);
5136 else if(OpcIsSET)
5137 NewOpc = getSETFromCond(NewCC, HasMemoryOperand);
5138 else {
5139 unsigned DstReg = Instr.getOperand(0).getReg();
5140 NewOpc = getCMovFromCond(NewCC, MRI->getRegClass(DstReg)->getSize(),
5141 HasMemoryOperand);
5142 }
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5143
5144 // Push the MachineInstr to OpsToUpdate.
5145 // If it is safe to remove CmpInstr, the condition code of these
5146 // instructions will be modified.
5147 OpsToUpdate.push_back(std::make_pair(&*I, NewOpc));
5148 }
Manman Ren32367c02012-07-28 03:15:46 +0000[diff] [blame]5149 if (ModifyEFLAGS || Instr.killsRegister(X86::EFLAGS, TRI)) {
5150 // It is safe to remove CmpInstr if EFLAGS is updated again or killed.
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5151 IsSafe = true;
5152 break;
5153 }
5154 }
5155
5156 // If EFLAGS is not killed nor re-defined, we should check whether it is
5157 // live-out. If it is live-out, do not optimize.
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5158 if ((IsCmpZero || IsSwapped) && !IsSafe) {
Manman Renbb360742012-07-07 03:34:46 +0000[diff] [blame]5159 MachineBasicBlock *MBB = CmpInstr->getParent();
5160 for (MachineBasicBlock::succ_iterator SI = MBB->succ_begin(),
5161 SE = MBB->succ_end(); SI != SE; ++SI)
5162 if ((*SI)->isLiveIn(X86::EFLAGS))
5163 return false;
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5164 }
5165
Manman Rend0a4ee82012-07-18 21:40:01 +0000[diff] [blame]5166 // The instruction to be updated is either Sub or MI.
5167 Sub = IsCmpZero ? MI : Sub;
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5168 // Move Movr0Inst to the appropriate place before Sub.
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5169 if (Movr0Inst) {
David Majnemer5ba473a2013-05-18 01:02:03 +0000[diff] [blame]5170 // Look backwards until we find a def that doesn't use the current EFLAGS.
5171 Def = Sub;
5172 MachineBasicBlock::reverse_iterator
5173 InsertI = MachineBasicBlock::reverse_iterator(++Def),
5174 InsertE = Sub->getParent()->rend();
5175 for (; InsertI != InsertE; ++InsertI) {
5176 MachineInstr *Instr = &*InsertI;
5177 if (!Instr->readsRegister(X86::EFLAGS, TRI) &&
5178 Instr->modifiesRegister(X86::EFLAGS, TRI)) {
5179 Sub->getParent()->remove(Movr0Inst);
5180 Instr->getParent()->insert(MachineBasicBlock::iterator(Instr),
5181 Movr0Inst);
5182 break;
5183 }
5184 }
5185 if (InsertI == InsertE)
5186 return false;
Manman Ren1553ce02012-07-11 19:35:12 +0000[diff] [blame]5187 }
5188
Jan Wen Voung4ce1d7b2012-09-17 22:04:23 +0000[diff] [blame]5189 // Make sure Sub instruction defines EFLAGS and mark the def live.
David Majnemer8f169742013-05-15 22:03:08 +0000[diff] [blame]5190 unsigned i = 0, e = Sub->getNumOperands();
5191 for (; i != e; ++i) {
5192 MachineOperand &MO = Sub->getOperand(i);
5193 if (MO.isReg() && MO.isDef() && MO.getReg() == X86::EFLAGS) {
5194 MO.setIsDead(false);
5195 break;
5196 }
5197 }
5198 assert(i != e && "Unable to locate a def EFLAGS operand");
5199
Manman Renc9656732012-07-06 17:36:20 +0000[diff] [blame]5200 CmpInstr->eraseFromParent();
5201
5202 // Modify the condition code of instructions in OpsToUpdate.
5203 for (unsigned i = 0, e = OpsToUpdate.size(); i < e; i++)
5204 OpsToUpdate[i].first->setDesc(get(OpsToUpdate[i].second));
5205 return true;
5206}
5207
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5208/// Try to remove the load by folding it to a register
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5209/// operand at the use. We fold the load instructions if load defines a virtual
5210/// register, the virtual register is used once in the same BB, and the
5211/// instructions in-between do not load or store, and have no side effects.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5212MachineInstr *X86InstrInfo::optimizeLoadInstr(MachineInstr *MI,
5213 const MachineRegisterInfo *MRI,
5214 unsigned &FoldAsLoadDefReg,
5215 MachineInstr *&DefMI) const {
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5216 if (FoldAsLoadDefReg == 0)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5217 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5218 // To be conservative, if there exists another load, clear the load candidate.
5219 if (MI->mayLoad()) {
5220 FoldAsLoadDefReg = 0;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5221 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5222 }
5223
5224 // Check whether we can move DefMI here.
5225 DefMI = MRI->getVRegDef(FoldAsLoadDefReg);
5226 assert(DefMI);
5227 bool SawStore = false;
Matthias Braun07066cc2015-05-19 21:22:20 +0000[diff] [blame]5228 if (!DefMI->isSafeToMove(nullptr, SawStore))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5229 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5230
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5231 // Collect information about virtual register operands of MI.
5232 unsigned SrcOperandId = 0;
5233 bool FoundSrcOperand = false;
5234 for (unsigned i = 0, e = MI->getDesc().getNumOperands(); i != e; ++i) {
5235 MachineOperand &MO = MI->getOperand(i);
5236 if (!MO.isReg())
5237 continue;
5238 unsigned Reg = MO.getReg();
5239 if (Reg != FoldAsLoadDefReg)
5240 continue;
5241 // Do not fold if we have a subreg use or a def or multiple uses.
5242 if (MO.getSubReg() || MO.isDef() || FoundSrcOperand)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5243 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5244
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5245 SrcOperandId = i;
5246 FoundSrcOperand = true;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5247 }
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5248 if (!FoundSrcOperand)
5249 return nullptr;
5250
5251 // Check whether we can fold the def into SrcOperandId.
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5252 MachineInstr *FoldMI = foldMemoryOperand(MI, SrcOperandId, DefMI);
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5253 if (FoldMI) {
5254 FoldAsLoadDefReg = 0;
5255 return FoldMI;
5256 }
5257
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5258 return nullptr;
Manman Ren5759d012012-08-02 00:56:42 +0000[diff] [blame]5259}
5260
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5261/// Expand a single-def pseudo instruction to a two-addr
5262/// instruction with two undef reads of the register being defined.
5263/// This is used for mapping:
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5264/// %xmm4 = V_SET0
5265/// to:
5266/// %xmm4 = PXORrr %xmm4<undef>, %xmm4<undef>
5267///
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5268static bool Expand2AddrUndef(MachineInstrBuilder &MIB,
5269 const MCInstrDesc &Desc) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5270 assert(Desc.getNumOperands() == 3 && "Expected two-addr instruction.");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5271 unsigned Reg = MIB->getOperand(0).getReg();
5272 MIB->setDesc(Desc);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5273
5274 // MachineInstr::addOperand() will insert explicit operands before any
5275 // implicit operands.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5276 MIB.addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5277 // But we don't trust that.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5278 assert(MIB->getOperand(1).getReg() == Reg &&
5279 MIB->getOperand(2).getReg() == Reg && "Misplaced operand");
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5280 return true;
5281}
5282
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5283static bool expandMOV32r1(MachineInstrBuilder &MIB, const TargetInstrInfo &TII,
5284 bool MinusOne) {
5285 MachineBasicBlock &MBB = *MIB->getParent();
5286 DebugLoc DL = MIB->getDebugLoc();
5287 unsigned Reg = MIB->getOperand(0).getReg();
5288
5289 // Insert the XOR.
5290 BuildMI(MBB, MIB.getInstr(), DL, TII.get(X86::XOR32rr), Reg)
5291 .addReg(Reg, RegState::Undef)
5292 .addReg(Reg, RegState::Undef);
5293
5294 // Turn the pseudo into an INC or DEC.
5295 MIB->setDesc(TII.get(MinusOne ? X86::DEC32r : X86::INC32r));
5296 MIB.addReg(Reg);
5297
5298 return true;
5299}
5300
Hans Wennborga6a2e512015-12-17 23:18:39 +0000[diff] [blame^]5301bool X86InstrInfo::ExpandMOVImmSExti8(MachineInstrBuilder &MIB) const {
5302 MachineBasicBlock &MBB = *MIB->getParent();
5303 DebugLoc DL = MIB->getDebugLoc();
5304 int64_t Imm = MIB->getOperand(1).getImm();
5305 assert(Imm != 0 && "Using push/pop for 0 is not efficient.");
5306 MachineBasicBlock::iterator I = MIB.getInstr();
5307
5308 int StackAdjustment;
5309
5310 if (Subtarget.is64Bit()) {
5311 assert(MIB->getOpcode() == X86::MOV64ImmSExti8 ||
5312 MIB->getOpcode() == X86::MOV32ImmSExti8);
5313 // 64-bit mode doesn't have 32-bit push/pop, so use 64-bit operations and
5314 // widen the register if necessary.
5315 StackAdjustment = 8;
5316 BuildMI(MBB, I, DL, get(X86::PUSH64i8)).addImm(Imm);
5317 MIB->setDesc(get(X86::POP64r));
5318 MIB->getOperand(0)
5319 .setReg(getX86SubSuperRegister(MIB->getOperand(0).getReg(), MVT::i64));
5320 } else {
5321 assert(MIB->getOpcode() == X86::MOV32ImmSExti8);
5322 StackAdjustment = 4;
5323 BuildMI(MBB, I, DL, get(X86::PUSH32i8)).addImm(Imm);
5324 MIB->setDesc(get(X86::POP32r));
5325 }
5326
5327 // Build CFI if necessary.
5328 MachineFunction &MF = *MBB.getParent();
5329 const X86FrameLowering *TFL = Subtarget.getFrameLowering();
5330 bool IsWin64Prologue = MF.getTarget().getMCAsmInfo()->usesWindowsCFI();
5331 bool NeedsDwarfCFI =
5332 !IsWin64Prologue &&
5333 (MF.getMMI().hasDebugInfo() || MF.getFunction()->needsUnwindTableEntry());
5334 bool EmitCFI = !TFL->hasFP(MF) && NeedsDwarfCFI;
5335 if (EmitCFI) {
5336 TFL->BuildCFI(MBB, I, DL,
5337 MCCFIInstruction::createAdjustCfaOffset(nullptr, StackAdjustment));
5338 TFL->BuildCFI(MBB, std::next(I), DL,
5339 MCCFIInstruction::createAdjustCfaOffset(nullptr, -StackAdjustment));
5340 }
5341
5342 return true;
5343}
5344
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5345// LoadStackGuard has so far only been implemented for 64-bit MachO. Different
5346// code sequence is needed for other targets.
5347static void expandLoadStackGuard(MachineInstrBuilder &MIB,
5348 const TargetInstrInfo &TII) {
5349 MachineBasicBlock &MBB = *MIB->getParent();
5350 DebugLoc DL = MIB->getDebugLoc();
5351 unsigned Reg = MIB->getOperand(0).getReg();
5352 const GlobalValue *GV =
5353 cast<GlobalValue>((*MIB->memoperands_begin())->getValue());
5354 unsigned Flag = MachineMemOperand::MOLoad | MachineMemOperand::MOInvariant;
Alex Lorenze40c8a22015-08-11 23:09:45 +0000[diff] [blame]5355 MachineMemOperand *MMO = MBB.getParent()->getMachineMemOperand(
5356 MachinePointerInfo::getGOT(*MBB.getParent()), Flag, 8, 8);
Reid Klecknerda00cf52014-10-31 23:19:46 +0000[diff] [blame]5357 MachineBasicBlock::iterator I = MIB.getInstr();
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5358
5359 BuildMI(MBB, I, DL, TII.get(X86::MOV64rm), Reg).addReg(X86::RIP).addImm(1)
5360 .addReg(0).addGlobalAddress(GV, 0, X86II::MO_GOTPCREL).addReg(0)
5361 .addMemOperand(MMO);
5362 MIB->setDebugLoc(DL);
5363 MIB->setDesc(TII.get(X86::MOV64rm));
5364 MIB.addReg(Reg, RegState::Kill).addImm(1).addReg(0).addImm(0).addReg(0);
5365}
5366
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5367bool X86InstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5368 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5369 MachineInstrBuilder MIB(*MI->getParent()->getParent(), MI);
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5370 switch (MI->getOpcode()) {
Craig Topper854f6442013-12-31 03:05:38 +0000[diff] [blame]5371 case X86::MOV32r0:
5372 return Expand2AddrUndef(MIB, get(X86::XOR32rr));
Hans Wennborg08d59052015-12-15 17:10:28 +0000[diff] [blame]5373 case X86::MOV32r1:
5374 return expandMOV32r1(MIB, *this, /*MinusOne=*/ false);
5375 case X86::MOV32r_1:
5376 return expandMOV32r1(MIB, *this, /*MinusOne=*/ true);
Hans Wennborga6a2e512015-12-17 23:18:39 +0000[diff] [blame^]5377 case X86::MOV32ImmSExti8:
5378 case X86::MOV64ImmSExti8:
5379 return ExpandMOVImmSExti8(MIB);
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5380 case X86::SETB_C8r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5381 return Expand2AddrUndef(MIB, get(X86::SBB8rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5382 case X86::SETB_C16r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5383 return Expand2AddrUndef(MIB, get(X86::SBB16rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5384 case X86::SETB_C32r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5385 return Expand2AddrUndef(MIB, get(X86::SBB32rr));
Craig Topper93849022012-10-05 06:05:15 +0000[diff] [blame]5386 case X86::SETB_C64r:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5387 return Expand2AddrUndef(MIB, get(X86::SBB64rr));
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5388 case X86::V_SET0:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]5389 case X86::FsFLD0SS:
5390 case X86::FsFLD0SD:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5391 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VXORPSrr : X86::XORPSrr));
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]5392 case X86::AVX_SET0:
5393 assert(HasAVX && "AVX not supported");
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5394 return Expand2AddrUndef(MIB, get(X86::VXORPSYrr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5395 case X86::AVX512_512_SET0:
5396 return Expand2AddrUndef(MIB, get(X86::VPXORDZrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5397 case X86::V_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5398 return Expand2AddrUndef(MIB, get(HasAVX ? X86::VPCMPEQDrr : X86::PCMPEQDrr));
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]5399 case X86::AVX2_SETALLONES:
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5400 return Expand2AddrUndef(MIB, get(X86::VPCMPEQDYrr));
Jakob Stoklund Olesen729abd32011-10-08 18:28:28 +0000[diff] [blame]5401 case X86::TEST8ri_NOREX:
5402 MI->setDesc(get(X86::TEST8ri));
5403 return true;
Michael Liao5bf95782014-12-04 05:20:33 +0000[diff] [blame]5404 case X86::KSET0B:
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5405 case X86::KSET0W: return Expand2AddrUndef(MIB, get(X86::KXORWrr));
Elena Demikhovsky702a6ad2015-09-17 06:53:12 +0000[diff] [blame]5406 case X86::KSET0D: return Expand2AddrUndef(MIB, get(X86::KXORDrr));
5407 case X86::KSET0Q: return Expand2AddrUndef(MIB, get(X86::KXORQrr));
Elena Demikhovskyf8f478b2013-08-25 12:54:30 +0000[diff] [blame]5408 case X86::KSET1B:
5409 case X86::KSET1W: return Expand2AddrUndef(MIB, get(X86::KXNORWrr));
Elena Demikhovsky702a6ad2015-09-17 06:53:12 +0000[diff] [blame]5410 case X86::KSET1D: return Expand2AddrUndef(MIB, get(X86::KXNORDrr));
5411 case X86::KSET1Q: return Expand2AddrUndef(MIB, get(X86::KXNORQrr));
Akira Hatanakae5b6e0d2014-07-25 19:31:34 +0000[diff] [blame]5412 case TargetOpcode::LOAD_STACK_GUARD:
5413 expandLoadStackGuard(MIB, *this);
5414 return true;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]5415 }
5416 return false;
5417}
5418
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5419static void addOperands(MachineInstrBuilder &MIB, ArrayRef<MachineOperand> MOs,
5420 int PtrOffset = 0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5421 unsigned NumAddrOps = MOs.size();
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5422
5423 if (NumAddrOps < 4) {
5424 // FrameIndex only - add an immediate offset (whether its zero or not).
5425 for (unsigned i = 0; i != NumAddrOps; ++i)
5426 MIB.addOperand(MOs[i]);
5427 addOffset(MIB, PtrOffset);
5428 } else {
5429 // General Memory Addressing - we need to add any offset to an existing
5430 // offset.
5431 assert(MOs.size() == 5 && "Unexpected memory operand list length");
5432 for (unsigned i = 0; i != NumAddrOps; ++i) {
5433 const MachineOperand &MO = MOs[i];
5434 if (i == 3 && PtrOffset != 0) {
Simon Pilgrimae0140d2015-11-19 21:50:57 +0000[diff] [blame]5435 MIB.addDisp(MO, PtrOffset);
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5436 } else {
5437 MIB.addOperand(MO);
5438 }
5439 }
5440 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5441}
5442
Dan Gohman3b460302008-07-07 23:14:23 +0000[diff] [blame]5443static MachineInstr *FuseTwoAddrInst(MachineFunction &MF, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5444 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5445 MachineBasicBlock::iterator InsertPt,
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]5446 MachineInstr *MI,
5447 const TargetInstrInfo &TII) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5448 // Create the base instruction with the memory operand as the first part.
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5449 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]5450 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5451 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5452 MachineInstrBuilder MIB(MF, NewMI);
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5453 addOperands(MIB, MOs);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5454
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5455 // Loop over the rest of the ri operands, converting them over.
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]5456 unsigned NumOps = MI->getDesc().getNumOperands()-2;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5457 for (unsigned i = 0; i != NumOps; ++i) {
5458 MachineOperand &MO = MI->getOperand(i+2);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5459 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5460 }
5461 for (unsigned i = NumOps+2, e = MI->getNumOperands(); i != e; ++i) {
5462 MachineOperand &MO = MI->getOperand(i);
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5463 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5464 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5465
5466 MachineBasicBlock *MBB = InsertPt->getParent();
5467 MBB->insert(InsertPt, NewMI);
5468
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5469 return MIB;
5470}
5471
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5472static MachineInstr *FuseInst(MachineFunction &MF, unsigned Opcode,
5473 unsigned OpNo, ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5474 MachineBasicBlock::iterator InsertPt,
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5475 MachineInstr *MI, const TargetInstrInfo &TII,
5476 int PtrOffset = 0) {
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5477 // Omit the implicit operands, something BuildMI can't do.
Bill Wendlinge3c78362009-02-03 00:55:04 +0000[diff] [blame]5478 MachineInstr *NewMI = MF.CreateMachineInstr(TII.get(Opcode),
5479 MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]5480 MachineInstrBuilder MIB(MF, NewMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5481
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5482 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
5483 MachineOperand &MO = MI->getOperand(i);
5484 if (i == OpNo) {
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5485 assert(MO.isReg() && "Expected to fold into reg operand!");
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5486 addOperands(MIB, MOs, PtrOffset);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5487 } else {
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]5488 MIB.addOperand(MO);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5489 }
5490 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5491
5492 MachineBasicBlock *MBB = InsertPt->getParent();
5493 MBB->insert(InsertPt, NewMI);
5494
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5495 return MIB;
5496}
5497
5498static MachineInstr *MakeM0Inst(const TargetInstrInfo &TII, unsigned Opcode,
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5499 ArrayRef<MachineOperand> MOs,
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5500 MachineBasicBlock::iterator InsertPt,
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5501 MachineInstr *MI) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5502 MachineInstrBuilder MIB = BuildMI(*InsertPt->getParent(), InsertPt,
5503 MI->getDebugLoc(), TII.get(Opcode));
5504 addOperands(MIB, MOs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5505 return MIB.addImm(0);
5506}
5507
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5508MachineInstr *X86InstrInfo::foldMemoryOperandCustom(
5509 MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5510 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5511 unsigned Size, unsigned Align) const {
5512 switch (MI->getOpcode()) {
5513 case X86::INSERTPSrr:
5514 case X86::VINSERTPSrr:
5515 // Attempt to convert the load of inserted vector into a fold load
5516 // of a single float.
5517 if (OpNum == 2) {
5518 unsigned Imm = MI->getOperand(MI->getNumOperands() - 1).getImm();
5519 unsigned ZMask = Imm & 15;
5520 unsigned DstIdx = (Imm >> 4) & 3;
5521 unsigned SrcIdx = (Imm >> 6) & 3;
5522
5523 unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
5524 if (Size <= RCSize && 4 <= Align) {
5525 int PtrOffset = SrcIdx * 4;
5526 unsigned NewImm = (DstIdx << 4) | ZMask;
5527 unsigned NewOpCode =
5528 (MI->getOpcode() == X86::VINSERTPSrr ? X86::VINSERTPSrm
5529 : X86::INSERTPSrm);
5530 MachineInstr *NewMI =
5531 FuseInst(MF, NewOpCode, OpNum, MOs, InsertPt, MI, *this, PtrOffset);
5532 NewMI->getOperand(NewMI->getNumOperands() - 1).setImm(NewImm);
5533 return NewMI;
5534 }
5535 }
5536 break;
5537 };
5538
5539 return nullptr;
5540}
5541
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5542MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5543 MachineFunction &MF, MachineInstr *MI, unsigned OpNum,
5544 ArrayRef<MachineOperand> MOs, MachineBasicBlock::iterator InsertPt,
5545 unsigned Size, unsigned Align, bool AllowCommute) const {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5546 const DenseMap<unsigned,
5547 std::pair<unsigned,unsigned> > *OpcodeTablePtr = nullptr;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5548 bool isCallRegIndirect = Subtarget.callRegIndirect();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5549 bool isTwoAddrFold = false;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5550
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]5551 // For CPUs that favor the register form of a call or push,
5552 // do not fold loads into calls or pushes, unless optimizing for size
5553 // aggressively.
Sanjay Patel924879a2015-08-04 15:49:57 +0000[diff] [blame]5554 if (isCallRegIndirect && !MF.getFunction()->optForMinSize() &&
Michael Kuperstein454d1452015-07-23 12:23:45 +0000[diff] [blame]5555 (MI->getOpcode() == X86::CALL32r || MI->getOpcode() == X86::CALL64r ||
5556 MI->getOpcode() == X86::PUSH16r || MI->getOpcode() == X86::PUSH32r ||
5557 MI->getOpcode() == X86::PUSH64r))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5558 return nullptr;
Preston Gurdd6be4bf2013-03-27 23:16:18 +0000[diff] [blame]5559
Chris Lattner03ad8852008-01-07 07:27:27 +0000[diff] [blame]5560 unsigned NumOps = MI->getDesc().getNumOperands();
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5561 bool isTwoAddr = NumOps > 1 &&
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]5562 MI->getDesc().getOperandConstraint(1, MCOI::TIED_TO) != -1;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5563
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5564 // FIXME: AsmPrinter doesn't know how to handle
5565 // X86II::MO_GOT_ABSOLUTE_ADDRESS after folding.
5566 if (MI->getOpcode() == X86::ADD32ri &&
5567 MI->getOperand(2).getTargetFlags() == X86II::MO_GOT_ABSOLUTE_ADDRESS)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5568 return nullptr;
Jakob Stoklund Olesen2348cdd2011-04-30 23:00:05 +0000[diff] [blame]5569
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5570 MachineInstr *NewMI = nullptr;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5571
5572 // Attempt to fold any custom cases we have.
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5573 if (MachineInstr *CustomMI =
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5574 foldMemoryOperandCustom(MF, MI, OpNum, MOs, InsertPt, Size, Align))
Simon Pilgrimf669d382015-11-04 21:27:22 +0000[diff] [blame]5575 return CustomMI;
Simon Pilgrim7e6606f2015-11-04 20:48:09 +0000[diff] [blame]5576
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5577 // Folding a memory location into the two-address part of a two-address
5578 // instruction is different than folding it other places. It requires
5579 // replacing the *two* registers with the memory location.
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5580 if (isTwoAddr && NumOps >= 2 && OpNum < 2 &&
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]5581 MI->getOperand(0).isReg() &&
5582 MI->getOperand(1).isReg() &&
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5583 MI->getOperand(0).getReg() == MI->getOperand(1).getReg()) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5584 OpcodeTablePtr = &RegOp2MemOpTable2Addr;
5585 isTwoAddrFold = true;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5586 } else if (OpNum == 0) {
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5587 if (MI->getOpcode() == X86::MOV32r0) {
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5588 NewMI = MakeM0Inst(*this, X86::MOV32mi, MOs, InsertPt, MI);
Tim Northover64ec0ff2013-05-30 13:19:42 +0000[diff] [blame]5589 if (NewMI)
5590 return NewMI;
Craig Topperf9115972012-08-23 04:57:36 +0000[diff] [blame]5591 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5592
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5593 OpcodeTablePtr = &RegOp2MemOpTable0;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5594 } else if (OpNum == 1) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5595 OpcodeTablePtr = &RegOp2MemOpTable1;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5596 } else if (OpNum == 2) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5597 OpcodeTablePtr = &RegOp2MemOpTable2;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5598 } else if (OpNum == 3) {
Elena Demikhovsky3cb3b002012-08-01 12:06:00 +0000[diff] [blame]5599 OpcodeTablePtr = &RegOp2MemOpTable3;
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5600 } else if (OpNum == 4) {
Robert Khasanov79fb7292014-12-18 12:28:22 +0000[diff] [blame]5601 OpcodeTablePtr = &RegOp2MemOpTable4;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5602 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5603
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5604 // If table selected...
5605 if (OpcodeTablePtr) {
5606 // Find the Opcode to fuse
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]5607 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
5608 OpcodeTablePtr->find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5609 if (I != OpcodeTablePtr->end()) {
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5610 unsigned Opcode = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]5611 unsigned MinAlign = (I->second.second & TB_ALIGN_MASK) >> TB_ALIGN_SHIFT;
Evan Cheng9e0c7f22009-07-15 06:10:07 +0000[diff] [blame]5612 if (Align < MinAlign)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5613 return nullptr;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5614 bool NarrowToMOV32rm = false;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5615 if (Size) {
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5616 unsigned RCSize = getRegClass(MI->getDesc(), OpNum, &RI, MF)->getSize();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5617 if (Size < RCSize) {
5618 // Check if it's safe to fold the load. If the size of the object is
5619 // narrower than the load width, then it's not.
5620 if (Opcode != X86::MOV64rm || RCSize != 8 || Size != 4)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5621 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5622 // If this is a 64-bit load, but the spill slot is 32, then we can do
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5623 // a 32-bit load which is implicitly zero-extended. This likely is
5624 // due to live interval analysis remat'ing a load from stack slot.
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5625 if (MI->getOperand(0).getSubReg() || MI->getOperand(1).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5626 return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5627 Opcode = X86::MOV32rm;
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5628 NarrowToMOV32rm = true;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5629 }
5630 }
5631
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5632 if (isTwoAddrFold)
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5633 NewMI = FuseTwoAddrInst(MF, Opcode, MOs, InsertPt, MI, *this);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5634 else
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5635 NewMI = FuseInst(MF, Opcode, OpNum, MOs, InsertPt, MI, *this);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5636
5637 if (NarrowToMOV32rm) {
5638 // If this is the special case where we use a MOV32rm to load a 32-bit
5639 // value and zero-extend the top bits. Change the destination register
5640 // to a 32-bit one.
5641 unsigned DstReg = NewMI->getOperand(0).getReg();
5642 if (TargetRegisterInfo::isPhysicalRegister(DstReg))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5643 NewMI->getOperand(0).setReg(RI.getSubReg(DstReg, X86::sub_32bit));
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5644 else
Jakob Stoklund Olesen9340ea52010-05-24 14:48:17 +0000[diff] [blame]5645 NewMI->getOperand(0).setSubReg(X86::sub_32bit);
Evan Cheng74a32312009-09-11 01:01:31 +0000[diff] [blame]5646 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5647 return NewMI;
5648 }
5649 }
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5650
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5651 // If the instruction and target operand are commutable, commute the
5652 // instruction and try again.
5653 if (AllowCommute) {
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5654 unsigned CommuteOpIdx1 = OpNum, CommuteOpIdx2 = CommuteAnyOperandIndex;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5655 if (findCommutedOpIndices(MI, CommuteOpIdx1, CommuteOpIdx2)) {
5656 bool HasDef = MI->getDesc().getNumDefs();
5657 unsigned Reg0 = HasDef ? MI->getOperand(0).getReg() : 0;
5658 unsigned Reg1 = MI->getOperand(CommuteOpIdx1).getReg();
5659 unsigned Reg2 = MI->getOperand(CommuteOpIdx2).getReg();
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5660 bool Tied1 =
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5661 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx1, MCOI::TIED_TO);
5662 bool Tied2 =
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5663 0 == MI->getDesc().getOperandConstraint(CommuteOpIdx2, MCOI::TIED_TO);
5664
5665 // If either of the commutable operands are tied to the destination
5666 // then we can not commute + fold.
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5667 if ((HasDef && Reg0 == Reg1 && Tied1) ||
5668 (HasDef && Reg0 == Reg2 && Tied2))
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5669 return nullptr;
5670
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5671 MachineInstr *CommutedMI =
5672 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5673 if (!CommutedMI) {
5674 // Unable to commute.
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5675 return nullptr;
5676 }
Andrew Kaylor16c4da02015-09-28 20:33:22 +0000[diff] [blame]5677 if (CommutedMI != MI) {
5678 // New instruction. We can't fold from this.
5679 CommutedMI->eraseFromParent();
5680 return nullptr;
5681 }
5682
5683 // Attempt to fold with the commuted version of the instruction.
5684 NewMI = foldMemoryOperandImpl(MF, MI, CommuteOpIdx2, MOs, InsertPt,
5685 Size, Align, /*AllowCommute=*/false);
5686 if (NewMI)
5687 return NewMI;
5688
5689 // Folding failed again - undo the commute before returning.
5690 MachineInstr *UncommutedMI =
5691 commuteInstruction(MI, false, CommuteOpIdx1, CommuteOpIdx2);
5692 if (!UncommutedMI) {
5693 // Unable to commute.
5694 return nullptr;
5695 }
5696 if (UncommutedMI != MI) {
5697 // New instruction. It doesn't need to be kept.
5698 UncommutedMI->eraseFromParent();
5699 return nullptr;
5700 }
5701
5702 // Return here to prevent duplicate fuse failure report.
5703 return nullptr;
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]5704 }
5705 }
5706
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5707 // No fusion
Jakob Stoklund Olesen51702ec2010-07-09 20:43:09 +0000[diff] [blame]5708 if (PrintFailedFusing && !MI->isCopy())
Sanjay Patela7b893d2015-02-09 16:30:58 +0000[diff] [blame]5709 dbgs() << "We failed to fuse operand " << OpNum << " in " << *MI;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5710 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5711}
5712
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5713/// Return true for all instructions that only update
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5714/// the first 32 or 64-bits of the destination register and leave the rest
5715/// unmodified. This can be used to avoid folding loads if the instructions
5716/// only update part of the destination register, and the non-updated part is
5717/// not needed. e.g. cvtss2sd, sqrtss. Unfolding the load from these
5718/// instructions breaks the partial register dependency and it can improve
5719/// performance. e.g.:
5720///
5721/// movss (%rdi), %xmm0
5722/// cvtss2sd %xmm0, %xmm0
5723///
5724/// Instead of
5725/// cvtss2sd (%rdi), %xmm0
5726///
Bruno Cardoso Lopes7b435682011-09-15 23:04:24 +0000[diff] [blame]5727/// FIXME: This should be turned into a TSFlags.
5728///
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5729static bool hasPartialRegUpdate(unsigned Opcode) {
5730 switch (Opcode) {
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5731 case X86::CVTSI2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5732 case X86::CVTSI2SSrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5733 case X86::CVTSI2SS64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5734 case X86::CVTSI2SS64rm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5735 case X86::CVTSI2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5736 case X86::CVTSI2SDrm:
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5737 case X86::CVTSI2SD64rr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5738 case X86::CVTSI2SD64rm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5739 case X86::CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5740 case X86::CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5741 case X86::Int_CVTSD2SSrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5742 case X86::Int_CVTSD2SSrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5743 case X86::CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5744 case X86::CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5745 case X86::Int_CVTSS2SDrr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5746 case X86::Int_CVTSS2SDrm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5747 case X86::RCPSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5748 case X86::RCPSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5749 case X86::RCPSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5750 case X86::RCPSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5751 case X86::ROUNDSDr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5752 case X86::ROUNDSDm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]5753 case X86::ROUNDSDr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5754 case X86::ROUNDSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5755 case X86::ROUNDSSm:
Benjamin Kramer2dc5dec2011-12-09 15:43:55 +0000[diff] [blame]5756 case X86::ROUNDSSr_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5757 case X86::RSQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5758 case X86::RSQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5759 case X86::RSQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5760 case X86::RSQRTSSm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5761 case X86::SQRTSSr:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5762 case X86::SQRTSSm:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5763 case X86::SQRTSSr_Int:
Michael Kuperstein47c97152014-12-15 13:18:21 +0000[diff] [blame]5764 case X86::SQRTSSm_Int:
5765 case X86::SQRTSDr:
5766 case X86::SQRTSDm:
5767 case X86::SQRTSDr_Int:
5768 case X86::SQRTSDm_Int:
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5769 return true;
5770 }
5771
5772 return false;
5773}
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5774
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]5775/// Inform the ExeDepsFix pass how many idle
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5776/// instructions we would like before a partial register update.
5777unsigned X86InstrInfo::
5778getPartialRegUpdateClearance(const MachineInstr *MI, unsigned OpNum,
5779 const TargetRegisterInfo *TRI) const {
5780 if (OpNum != 0 || !hasPartialRegUpdate(MI->getOpcode()))
5781 return 0;
5782
5783 // If MI is marked as reading Reg, the partial register update is wanted.
5784 const MachineOperand &MO = MI->getOperand(0);
5785 unsigned Reg = MO.getReg();
5786 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
5787 if (MO.readsReg() || MI->readsVirtualRegister(Reg))
5788 return 0;
5789 } else {
5790 if (MI->readsRegister(Reg, TRI))
5791 return 0;
5792 }
5793
5794 // If any of the preceding 16 instructions are reading Reg, insert a
5795 // dependency breaking instruction. The magic number is based on a few
5796 // Nehalem experiments.
5797 return 16;
5798}
5799
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5800// Return true for any instruction the copies the high bits of the first source
5801// operand into the unused high bits of the destination operand.
5802static bool hasUndefRegUpdate(unsigned Opcode) {
5803 switch (Opcode) {
5804 case X86::VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5805 case X86::VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5806 case X86::Int_VCVTSI2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5807 case X86::Int_VCVTSI2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5808 case X86::VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5809 case X86::VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5810 case X86::Int_VCVTSI2SS64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5811 case X86::Int_VCVTSI2SS64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5812 case X86::VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5813 case X86::VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5814 case X86::Int_VCVTSI2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5815 case X86::Int_VCVTSI2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5816 case X86::VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5817 case X86::VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5818 case X86::Int_VCVTSI2SD64rr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5819 case X86::Int_VCVTSI2SD64rm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5820 case X86::VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5821 case X86::VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5822 case X86::Int_VCVTSD2SSrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5823 case X86::Int_VCVTSD2SSrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5824 case X86::VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5825 case X86::VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5826 case X86::Int_VCVTSS2SDrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5827 case X86::Int_VCVTSS2SDrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5828 case X86::VRCPSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5829 case X86::VRCPSSm:
5830 case X86::VRCPSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5831 case X86::VROUNDSDr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5832 case X86::VROUNDSDm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5833 case X86::VROUNDSDr_Int:
5834 case X86::VROUNDSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5835 case X86::VROUNDSSm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5836 case X86::VROUNDSSr_Int:
5837 case X86::VRSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5838 case X86::VRSQRTSSm:
5839 case X86::VRSQRTSSm_Int:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5840 case X86::VSQRTSSr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5841 case X86::VSQRTSSm:
5842 case X86::VSQRTSSm_Int:
5843 case X86::VSQRTSDr:
5844 case X86::VSQRTSDm:
5845 case X86::VSQRTSDm_Int:
5846 // AVX-512
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5847 case X86::VCVTSD2SSZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5848 case X86::VCVTSD2SSZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5849 case X86::VCVTSS2SDZrr:
Michael Kuperstein683c3cd2014-12-28 13:15:05 +0000[diff] [blame]5850 case X86::VCVTSS2SDZrm:
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5851 return true;
5852 }
5853
5854 return false;
5855}
5856
5857/// Inform the ExeDepsFix pass how many idle instructions we would like before
5858/// certain undef register reads.
5859///
5860/// This catches the VCVTSI2SD family of instructions:
5861///
5862/// vcvtsi2sdq %rax, %xmm0<undef>, %xmm14
5863///
5864/// We should to be careful *not* to catch VXOR idioms which are presumably
5865/// handled specially in the pipeline:
5866///
5867/// vxorps %xmm1<undef>, %xmm1<undef>, %xmm1
5868///
5869/// Like getPartialRegUpdateClearance, this makes a strong assumption that the
5870/// high bits that are passed-through are not live.
5871unsigned X86InstrInfo::
5872getUndefRegClearance(const MachineInstr *MI, unsigned &OpNum,
5873 const TargetRegisterInfo *TRI) const {
5874 if (!hasUndefRegUpdate(MI->getOpcode()))
5875 return 0;
5876
5877 // Set the OpNum parameter to the first source operand.
5878 OpNum = 1;
5879
5880 const MachineOperand &MO = MI->getOperand(OpNum);
5881 if (MO.isUndef() && TargetRegisterInfo::isPhysicalRegister(MO.getReg())) {
5882 // Use the same magic number as getPartialRegUpdateClearance.
5883 return 16;
5884 }
5885 return 0;
5886}
5887
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5888void X86InstrInfo::
5889breakPartialRegDependency(MachineBasicBlock::iterator MI, unsigned OpNum,
5890 const TargetRegisterInfo *TRI) const {
5891 unsigned Reg = MI->getOperand(OpNum).getReg();
Andrew Trickb6d56be2013-10-14 22:19:03 +0000[diff] [blame]5892 // If MI kills this register, the false dependence is already broken.
5893 if (MI->killsRegister(Reg, TRI))
5894 return;
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5895 if (X86::VR128RegClass.contains(Reg)) {
5896 // These instructions are all floating point domain, so xorps is the best
5897 // choice.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]5898 bool HasAVX = Subtarget.hasAVX();
Jakob Stoklund Olesenf8ad3362011-11-15 01:15:30 +0000[diff] [blame]5899 unsigned Opc = HasAVX ? X86::VXORPSrr : X86::XORPSrr;
5900 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(Opc), Reg)
5901 .addReg(Reg, RegState::Undef).addReg(Reg, RegState::Undef);
5902 } else if (X86::VR256RegClass.contains(Reg)) {
5903 // Use vxorps to clear the full ymm register.
5904 // It wants to read and write the xmm sub-register.
5905 unsigned XReg = TRI->getSubReg(Reg, X86::sub_xmm);
5906 BuildMI(*MI->getParent(), MI, MI->getDebugLoc(), get(X86::VXORPSrr), XReg)
5907 .addReg(XReg, RegState::Undef).addReg(XReg, RegState::Undef)
5908 .addReg(Reg, RegState::ImplicitDefine);
5909 } else
5910 return;
5911 MI->addRegisterKilled(Reg, TRI, true);
5912}
5913
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5914MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
5915 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
5916 MachineBasicBlock::iterator InsertPt, int FrameIndex) const {
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]5917 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5918 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5919
Bruno Cardoso Lopes6b302952011-09-15 21:42:23 +0000[diff] [blame]5920 // Unless optimizing for size, don't fold to avoid partial
5921 // register update stalls
Sanjay Patel10294b52015-08-10 17:15:17 +0000[diff] [blame]5922 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5923 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]5924
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]5925 const MachineFrameInfo *MFI = MF.getFrameInfo();
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5926 unsigned Size = MFI->getObjectSize(FrameIndex);
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]5927 unsigned Alignment = MFI->getObjectAlignment(FrameIndex);
Benjamin Kramer858a3882013-10-06 13:48:22 +0000[diff] [blame]5928 // If the function stack isn't realigned we don't want to fold instructions
5929 // that need increased alignment.
5930 if (!RI.needsStackRealignment(MF))
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]5931 Alignment =
5932 std::min(Alignment, Subtarget.getFrameLowering()->getStackAlignment());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5933 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
5934 unsigned NewOpc = 0;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5935 unsigned RCSize = 0;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5936 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5937 default: return nullptr;
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5938 case X86::TEST8rr: NewOpc = X86::CMP8ri; RCSize = 1; break;
Dan Gohman887dd1c2010-05-18 21:42:03 +0000[diff] [blame]5939 case X86::TEST16rr: NewOpc = X86::CMP16ri8; RCSize = 2; break;
5940 case X86::TEST32rr: NewOpc = X86::CMP32ri8; RCSize = 4; break;
5941 case X86::TEST64rr: NewOpc = X86::CMP64ri8; RCSize = 8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5942 }
Evan Cheng3cad6282009-09-11 00:39:26 +0000[diff] [blame]5943 // Check if it's safe to fold the load. If the size of the object is
5944 // narrower than the load width, then it's not.
5945 if (Size < RCSize)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5946 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5947 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]5948 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5949 MI->getOperand(1).ChangeToImmediate(0);
5950 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]5951 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5952
Benjamin Kramerf1362f62015-02-28 12:04:00 +0000[diff] [blame]5953 return foldMemoryOperandImpl(MF, MI, Ops[0],
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]5954 MachineOperand::CreateFI(FrameIndex), InsertPt,
5955 Size, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]5956}
5957
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5958/// Check if \p LoadMI is a partial register load that we can't fold into \p MI
5959/// because the latter uses contents that wouldn't be defined in the folded
5960/// version. For instance, this transformation isn't legal:
5961/// movss (%rdi), %xmm0
5962/// addps %xmm0, %xmm0
5963/// ->
5964/// addps (%rdi), %xmm0
5965///
5966/// But this one is:
5967/// movss (%rdi), %xmm0
5968/// addss %xmm0, %xmm0
5969/// ->
5970/// addss (%rdi), %xmm0
5971///
5972static bool isNonFoldablePartialRegisterLoad(const MachineInstr &LoadMI,
5973 const MachineInstr &UserMI,
5974 const MachineFunction &MF) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5975 unsigned Opc = LoadMI.getOpcode();
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5976 unsigned UserOpc = UserMI.getOpcode();
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5977 unsigned RegSize =
5978 MF.getRegInfo().getRegClass(LoadMI.getOperand(0).getReg())->getSize();
5979
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5980 if ((Opc == X86::MOVSSrm || Opc == X86::VMOVSSrm) && RegSize > 4) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]5981 // These instructions only load 32 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5982 // destination register is wider than 32 bits (4 bytes), and its user
5983 // instruction isn't scalar (SS).
5984 switch (UserOpc) {
5985 case X86::ADDSSrr_Int: case X86::VADDSSrr_Int:
5986 case X86::DIVSSrr_Int: case X86::VDIVSSrr_Int:
5987 case X86::MULSSrr_Int: case X86::VMULSSrr_Int:
5988 case X86::SUBSSrr_Int: case X86::VSUBSSrr_Int:
Vyacheslav Klochkoved865df2015-11-26 07:45:30 +0000[diff] [blame]5989 case X86::VFMADDSSr132r_Int: case X86::VFNMADDSSr132r_Int:
5990 case X86::VFMADDSSr213r_Int: case X86::VFNMADDSSr213r_Int:
5991 case X86::VFMADDSSr231r_Int: case X86::VFNMADDSSr231r_Int:
5992 case X86::VFMSUBSSr132r_Int: case X86::VFNMSUBSSr132r_Int:
5993 case X86::VFMSUBSSr213r_Int: case X86::VFNMSUBSSr213r_Int:
5994 case X86::VFMSUBSSr231r_Int: case X86::VFNMSUBSSr231r_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]5995 return false;
5996 default:
5997 return true;
5998 }
5999 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6000
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6001 if ((Opc == X86::MOVSDrm || Opc == X86::VMOVSDrm) && RegSize > 8) {
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6002 // These instructions only load 64 bits, we can't fold them if the
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6003 // destination register is wider than 64 bits (8 bytes), and its user
6004 // instruction isn't scalar (SD).
6005 switch (UserOpc) {
6006 case X86::ADDSDrr_Int: case X86::VADDSDrr_Int:
6007 case X86::DIVSDrr_Int: case X86::VDIVSDrr_Int:
6008 case X86::MULSDrr_Int: case X86::VMULSDrr_Int:
6009 case X86::SUBSDrr_Int: case X86::VSUBSDrr_Int:
Vyacheslav Klochkoved865df2015-11-26 07:45:30 +0000[diff] [blame]6010 case X86::VFMADDSDr132r_Int: case X86::VFNMADDSDr132r_Int:
6011 case X86::VFMADDSDr213r_Int: case X86::VFNMADDSDr213r_Int:
6012 case X86::VFMADDSDr231r_Int: case X86::VFNMADDSDr231r_Int:
6013 case X86::VFMSUBSDr132r_Int: case X86::VFNMSUBSDr132r_Int:
6014 case X86::VFMSUBSDr213r_Int: case X86::VFNMSUBSDr213r_Int:
6015 case X86::VFMSUBSDr231r_Int: case X86::VFNMSUBSDr231r_Int:
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6016 return false;
6017 default:
6018 return true;
6019 }
6020 }
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6021
6022 return false;
6023}
6024
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6025MachineInstr *X86InstrInfo::foldMemoryOperandImpl(
6026 MachineFunction &MF, MachineInstr *MI, ArrayRef<unsigned> Ops,
6027 MachineBasicBlock::iterator InsertPt, MachineInstr *LoadMI) const {
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6028 // If loading from a FrameIndex, fold directly from the FrameIndex.
6029 unsigned NumOps = LoadMI->getDesc().getNumOperands();
6030 int FrameIndex;
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6031 if (isLoadFromStackSlot(LoadMI, FrameIndex)) {
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6032 if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6033 return nullptr;
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6034 return foldMemoryOperandImpl(MF, MI, Ops, InsertPt, FrameIndex);
Akira Hatanaka760814a2014-09-15 18:23:52 +0000[diff] [blame]6035 }
Andrew Trick3112a5e2013-11-12 18:06:12 +0000[diff] [blame]6036
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6037 // Check switch flag
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6038 if (NoFusing) return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6039
Sanjay Pateld09391c2015-08-10 20:45:44 +0000[diff] [blame]6040 // Avoid partial register update stalls unless optimizing for size.
6041 if (!MF.getFunction()->optForSize() && hasPartialRegUpdate(MI->getOpcode()))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6042 return nullptr;
Evan Cheng4cf30b72009-12-18 07:40:29 +0000[diff] [blame]6043
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]6044 // Determine the alignment of the load.
Evan Cheng3b3286d2008-02-08 21:20:40 +0000[diff] [blame]6045 unsigned Alignment = 0;
Dan Gohman9a542a42008-07-12 00:10:52 +0000[diff] [blame]6046 if (LoadMI->hasOneMemOperand())
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]6047 Alignment = (*LoadMI->memoperands_begin())->getAlignment();
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6048 else
6049 switch (LoadMI->getOpcode()) {
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6050 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6051 case X86::AVX_SET0:
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6052 Alignment = 32;
6053 break;
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6054 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6055 case X86::V_SETALLONES:
6056 Alignment = 16;
6057 break;
6058 case X86::FsFLD0SD:
6059 Alignment = 8;
6060 break;
6061 case X86::FsFLD0SS:
6062 Alignment = 4;
6063 break;
6064 default:
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6065 return nullptr;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6066 }
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6067 if (Ops.size() == 2 && Ops[0] == 0 && Ops[1] == 1) {
6068 unsigned NewOpc = 0;
6069 switch (MI->getOpcode()) {
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6070 default: return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6071 case X86::TEST8rr: NewOpc = X86::CMP8ri; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6072 case X86::TEST16rr: NewOpc = X86::CMP16ri8; break;
6073 case X86::TEST32rr: NewOpc = X86::CMP32ri8; break;
6074 case X86::TEST64rr: NewOpc = X86::CMP64ri8; break;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6075 }
6076 // Change to CMPXXri r, 0 first.
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]6077 MI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6078 MI->getOperand(1).ChangeToImmediate(0);
6079 } else if (Ops.size() != 1)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6080 return nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6081
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6082 // Make sure the subregisters match.
6083 // Otherwise we risk changing the size of the load.
6084 if (LoadMI->getOperand(0).getSubReg() != MI->getOperand(Ops[0]).getSubReg())
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6085 return nullptr;
Jakob Stoklund Olesen9c473e42010-08-11 23:08:22 +0000[diff] [blame]6086
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6087 SmallVector<MachineOperand,X86::AddrNumOperands> MOs;
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6088 switch (LoadMI->getOpcode()) {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6089 case X86::V_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6090 case X86::V_SETALLONES:
Craig Toppera3a65832011-11-19 22:34:59 +0000[diff] [blame]6091 case X86::AVX2_SETALLONES:
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6092 case X86::AVX_SET0:
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6093 case X86::FsFLD0SD:
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6094 case X86::FsFLD0SS: {
Jakob Stoklund Olesendd1904e2011-09-29 05:10:54 +0000[diff] [blame]6095 // Folding a V_SET0 or V_SETALLONES as a load, to ease register pressure.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6096 // Create a constant-pool entry and operands to load from it.
6097
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6098 // Medium and large mode can't fold loads this way.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6099 if (MF.getTarget().getCodeModel() != CodeModel::Small &&
6100 MF.getTarget().getCodeModel() != CodeModel::Kernel)
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6101 return nullptr;
Dan Gohman772952f2010-03-09 03:01:40 +0000[diff] [blame]6102
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6103 // x86-32 PIC requires a PIC base register for constant pools.
6104 unsigned PICBase = 0;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6105 if (MF.getTarget().getRelocationModel() == Reloc::PIC_) {
6106 if (Subtarget.is64Bit())
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6107 PICBase = X86::RIP;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6108 else
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6109 // FIXME: PICBase = getGlobalBaseReg(&MF);
Evan Chengfdd0eb42009-07-16 18:44:05 +0000[diff] [blame]6110 // This doesn't work for several reasons.
6111 // 1. GlobalBaseReg may have been spilled.
6112 // 2. It may not be live at MI.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6113 return nullptr;
Jakob Stoklund Olesenc7895d32009-07-16 21:24:13 +0000[diff] [blame]6114 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6115
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6116 // Create a constant-pool entry.
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6117 MachineConstantPool &MCP = *MF.getConstantPool();
Chris Lattner229907c2011-07-18 04:54:35 +0000[diff] [blame]6118 Type *Ty;
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6119 unsigned Opc = LoadMI->getOpcode();
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6120 if (Opc == X86::FsFLD0SS)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6121 Ty = Type::getFloatTy(MF.getFunction()->getContext());
Jakob Stoklund Olesenbde32d32011-11-29 22:27:25 +0000[diff] [blame]6122 else if (Opc == X86::FsFLD0SD)
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6123 Ty = Type::getDoubleTy(MF.getFunction()->getContext());
Craig Topperbd509ee2012-08-28 07:05:28 +0000[diff] [blame]6124 else if (Opc == X86::AVX2_SETALLONES || Opc == X86::AVX_SET0)
Craig Toppera4c5a472012-01-13 06:12:41 +0000[diff] [blame]6125 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 8);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6126 else
6127 Ty = VectorType::get(Type::getInt32Ty(MF.getFunction()->getContext()), 4);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6128
Craig Topper72f51c32012-08-28 07:30:47 +0000[diff] [blame]6129 bool IsAllOnes = (Opc == X86::V_SETALLONES || Opc == X86::AVX2_SETALLONES);
Bruno Cardoso Lopes9212bf22011-07-25 23:05:32 +0000[diff] [blame]6130 const Constant *C = IsAllOnes ? Constant::getAllOnesValue(Ty) :
6131 Constant::getNullValue(Ty);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6132 unsigned CPI = MCP.getConstantPoolIndex(C, Alignment);
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6133
6134 // Create operands to load from the constant pool entry.
6135 MOs.push_back(MachineOperand::CreateReg(PICBase, false));
6136 MOs.push_back(MachineOperand::CreateImm(1));
6137 MOs.push_back(MachineOperand::CreateReg(0, false));
6138 MOs.push_back(MachineOperand::CreateCPI(CPI, 0));
Rafael Espindola3b2df102009-04-08 21:14:34 +0000[diff] [blame]6139 MOs.push_back(MachineOperand::CreateReg(0, false));
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6140 break;
6141 }
6142 default: {
Ahmed Bougachaed3c4d12015-06-22 20:51:51 +0000[diff] [blame]6143 if (isNonFoldablePartialRegisterLoad(*LoadMI, *MI, MF))
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6144 return nullptr;
Manman Ren5b462822012-11-27 18:09:26 +0000[diff] [blame]6145
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6146 // Folding a normal load. Just copy the load's address operands.
Benjamin Kramer5fbfe2f2015-02-28 13:20:15 +0000[diff] [blame]6147 MOs.append(LoadMI->operands_begin() + NumOps - X86::AddrNumOperands,
6148 LoadMI->operands_begin() + NumOps);
Dan Gohman69499b132009-09-21 18:30:38 +0000[diff] [blame]6149 break;
6150 }
Dan Gohmancc78cdf2008-12-03 05:21:24 +0000[diff] [blame]6151 }
Keno Fischere70b31f2015-06-08 20:09:58 +0000[diff] [blame]6152 return foldMemoryOperandImpl(MF, MI, Ops[0], MOs, InsertPt,
Simon Pilgrim2f9548a2014-10-20 22:14:22 +0000[diff] [blame]6153 /*Size=*/0, Alignment, /*AllowCommute=*/true);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6154}
6155
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6156bool X86InstrInfo::unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI,
6157 unsigned Reg, bool UnfoldLoad, bool UnfoldStore,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]6158 SmallVectorImpl<MachineInstr*> &NewMIs) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]6159 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
6160 MemOp2RegOpTable.find(MI->getOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6161 if (I == MemOp2RegOpTable.end())
6162 return false;
6163 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6164 unsigned Index = I->second.second & TB_INDEX_MASK;
6165 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6166 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6167 if (UnfoldLoad && !FoldedLoad)
6168 return false;
6169 UnfoldLoad &= FoldedLoad;
6170 if (UnfoldStore && !FoldedStore)
6171 return false;
6172 UnfoldStore &= FoldedStore;
6173
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6174 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6175 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6176 // TODO: Check if 32-byte or greater accesses are slow too?
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6177 if (!MI->hasOneMemOperand() &&
6178 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6179 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6180 // Without memoperands, loadRegFromAddr and storeRegToStackSlot will
6181 // conservatively assume the address is unaligned. That's bad for
6182 // performance.
6183 return false;
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6184 SmallVector<MachineOperand, X86::AddrNumOperands> AddrOps;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6185 SmallVector<MachineOperand,2> BeforeOps;
6186 SmallVector<MachineOperand,2> AfterOps;
6187 SmallVector<MachineOperand,4> ImpOps;
6188 for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
6189 MachineOperand &Op = MI->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6190 if (i >= Index && i < Index + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6191 AddrOps.push_back(Op);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6192 else if (Op.isReg() && Op.isImplicit())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6193 ImpOps.push_back(Op);
6194 else if (i < Index)
6195 BeforeOps.push_back(Op);
6196 else if (i > Index)
6197 AfterOps.push_back(Op);
6198 }
6199
6200 // Emit the load instruction.
6201 if (UnfoldLoad) {
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6202 std::pair<MachineInstr::mmo_iterator,
6203 MachineInstr::mmo_iterator> MMOs =
6204 MF.extractLoadMemRefs(MI->memoperands_begin(),
6205 MI->memoperands_end());
6206 loadRegFromAddr(MF, Reg, AddrOps, RC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6207 if (UnfoldStore) {
6208 // Address operands cannot be marked isKill.
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6209 for (unsigned i = 1; i != 1 + X86::AddrNumOperands; ++i) {
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6210 MachineOperand &MO = NewMIs[0]->getOperand(i);
Dan Gohman0d1e9a82008-10-03 15:45:36 +0000[diff] [blame]6211 if (MO.isReg())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6212 MO.setIsKill(false);
6213 }
6214 }
6215 }
6216
6217 // Emit the data processing instruction.
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6218 MachineInstr *DataMI = MF.CreateMachineInstr(MCID, MI->getDebugLoc(), true);
Jakob Stoklund Olesenb159b5f2012-12-19 21:31:56 +0000[diff] [blame]6219 MachineInstrBuilder MIB(MF, DataMI);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]6220
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6221 if (FoldedStore)
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6222 MIB.addReg(Reg, RegState::Define);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6223 for (unsigned i = 0, e = BeforeOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]6224 MIB.addOperand(BeforeOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6225 if (FoldedLoad)
6226 MIB.addReg(Reg);
6227 for (unsigned i = 0, e = AfterOps.size(); i != e; ++i)
Dan Gohman2af1f852009-02-18 05:45:50 +0000[diff] [blame]6228 MIB.addOperand(AfterOps[i]);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6229 for (unsigned i = 0, e = ImpOps.size(); i != e; ++i) {
6230 MachineOperand &MO = ImpOps[i];
Bill Wendlingf7b83c72009-05-13 21:33:08 +0000[diff] [blame]6231 MIB.addReg(MO.getReg(),
6232 getDefRegState(MO.isDef()) |
6233 RegState::Implicit |
6234 getKillRegState(MO.isKill()) |
Evan Cheng0dc101b2009-06-30 08:49:04 +0000[diff] [blame]6235 getDeadRegState(MO.isDead()) |
6236 getUndefRegState(MO.isUndef()));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6237 }
6238 // Change CMP32ri r, 0 back to TEST32rr r, r, etc.
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6239 switch (DataMI->getOpcode()) {
6240 default: break;
6241 case X86::CMP64ri32:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6242 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6243 case X86::CMP32ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6244 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6245 case X86::CMP16ri:
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6246 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6247 case X86::CMP8ri: {
6248 MachineOperand &MO0 = DataMI->getOperand(0);
6249 MachineOperand &MO1 = DataMI->getOperand(1);
6250 if (MO1.getImm() == 0) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6251 unsigned NewOpc;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6252 switch (DataMI->getOpcode()) {
Craig Topper4bc3e5a2012-08-21 08:16:16 +0000[diff] [blame]6253 default: llvm_unreachable("Unreachable!");
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6254 case X86::CMP64ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6255 case X86::CMP64ri32: NewOpc = X86::TEST64rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6256 case X86::CMP32ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6257 case X86::CMP32ri: NewOpc = X86::TEST32rr; break;
Dan Gohmanf8bf6632010-05-18 21:54:15 +0000[diff] [blame]6258 case X86::CMP16ri8:
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6259 case X86::CMP16ri: NewOpc = X86::TEST16rr; break;
6260 case X86::CMP8ri: NewOpc = X86::TEST8rr; break;
6261 }
Chris Lattner59687512008-01-11 18:10:50 +0000[diff] [blame]6262 DataMI->setDesc(get(NewOpc));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6263 MO1.ChangeToRegister(MO0.getReg(), false);
6264 }
6265 }
6266 }
6267 NewMIs.push_back(DataMI);
6268
6269 // Emit the store instruction.
6270 if (UnfoldStore) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6271 const TargetRegisterClass *DstRC = getRegClass(MCID, 0, &RI, MF);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6272 std::pair<MachineInstr::mmo_iterator,
6273 MachineInstr::mmo_iterator> MMOs =
6274 MF.extractStoreMemRefs(MI->memoperands_begin(),
6275 MI->memoperands_end());
6276 storeRegToAddr(MF, Reg, true, AddrOps, DstRC, MMOs.first, MMOs.second, NewMIs);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6277 }
6278
6279 return true;
6280}
6281
6282bool
6283X86InstrInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
Bill Wendling27b508d2009-02-11 21:51:19 +0000[diff] [blame]6284 SmallVectorImpl<SDNode*> &NewNodes) const {
Dan Gohman17059682008-07-17 19:10:17 +0000[diff] [blame]6285 if (!N->isMachineOpcode())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6286 return false;
6287
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]6288 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
6289 MemOp2RegOpTable.find(N->getMachineOpcode());
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6290 if (I == MemOp2RegOpTable.end())
6291 return false;
6292 unsigned Opc = I->second.first;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6293 unsigned Index = I->second.second & TB_INDEX_MASK;
6294 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6295 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6296 const MCInstrDesc &MCID = get(Opc);
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6297 MachineFunction &MF = DAG.getMachineFunction();
6298 const TargetRegisterClass *RC = getRegClass(MCID, Index, &RI, MF);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6299 unsigned NumDefs = MCID.NumDefs;
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6300 std::vector<SDValue> AddrOps;
6301 std::vector<SDValue> BeforeOps;
6302 std::vector<SDValue> AfterOps;
Andrew Trickef9de2a2013-05-25 02:42:55 +0000[diff] [blame]6303 SDLoc dl(N);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6304 unsigned NumOps = N->getNumOperands();
Dan Gohman48b185d2009-09-25 20:36:54 +0000[diff] [blame]6305 for (unsigned i = 0; i != NumOps-1; ++i) {
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6306 SDValue Op = N->getOperand(i);
Chris Lattnerec536272010-07-08 22:41:28 +0000[diff] [blame]6307 if (i >= Index-NumDefs && i < Index-NumDefs + X86::AddrNumOperands)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6308 AddrOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6309 else if (i < Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6310 BeforeOps.push_back(Op);
Dan Gohmancc329b52009-03-04 19:23:38 +0000[diff] [blame]6311 else if (i > Index-NumDefs)
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6312 AfterOps.push_back(Op);
6313 }
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6314 SDValue Chain = N->getOperand(NumOps-1);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6315 AddrOps.push_back(Chain);
6316
6317 // Emit the load instruction.
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6318 SDNode *Load = nullptr;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6319 if (FoldedLoad) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6320 EVT VT = *RC->vt_begin();
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6321 std::pair<MachineInstr::mmo_iterator,
6322 MachineInstr::mmo_iterator> MMOs =
6323 MF.extractLoadMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6324 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6325 if (!(*MMOs.first) &&
6326 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6327 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6328 // Do not introduce a slow unaligned load.
6329 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6330 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6331 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6332 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6333 bool isAligned = (*MMOs.first) &&
6334 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6335 Load = DAG.getMachineNode(getLoadRegOpcode(0, RC, isAligned, Subtarget), dl,
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6336 VT, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6337 NewNodes.push_back(Load);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6338
6339 // Preserve memory reference information.
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6340 cast<MachineSDNode>(Load)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6341 }
6342
6343 // Emit the data processing instruction.
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6344 std::vector<EVT> VTs;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6345 const TargetRegisterClass *DstRC = nullptr;
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6346 if (MCID.getNumDefs() > 0) {
Jakob Stoklund Olesen3c52f022012-05-07 22:10:26 +0000[diff] [blame]6347 DstRC = getRegClass(MCID, 0, &RI, MF);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6348 VTs.push_back(*DstRC->vt_begin());
6349 }
6350 for (unsigned i = 0, e = N->getNumValues(); i != e; ++i) {
Owen Anderson53aa7a92009-08-10 22:56:29 +0000[diff] [blame]6351 EVT VT = N->getValueType(i);
Evan Cheng6cc775f2011-06-28 19:10:37 +0000[diff] [blame]6352 if (VT != MVT::Other && i >= (unsigned)MCID.getNumDefs())
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6353 VTs.push_back(VT);
6354 }
6355 if (Load)
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6356 BeforeOps.push_back(SDValue(Load, 0));
Benjamin Kramer4f6ac162015-02-28 10:11:12 +0000[diff] [blame]6357 BeforeOps.insert(BeforeOps.end(), AfterOps.begin(), AfterOps.end());
Michael Liaob53d8962013-04-19 22:22:57 +0000[diff] [blame]6358 SDNode *NewNode= DAG.getMachineNode(Opc, dl, VTs, BeforeOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6359 NewNodes.push_back(NewNode);
6360
6361 // Emit the store instruction.
6362 if (FoldedStore) {
6363 AddrOps.pop_back();
Dan Gohman2ce6f2a2008-07-27 21:46:04 +0000[diff] [blame]6364 AddrOps.push_back(SDValue(NewNode, 0));
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6365 AddrOps.push_back(Chain);
Evan Chengf25ef4f2009-11-16 21:56:03 +0000[diff] [blame]6366 std::pair<MachineInstr::mmo_iterator,
6367 MachineInstr::mmo_iterator> MMOs =
6368 MF.extractStoreMemRefs(cast<MachineSDNode>(N)->memoperands_begin(),
6369 cast<MachineSDNode>(N)->memoperands_end());
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6370 if (!(*MMOs.first) &&
6371 RC == &X86::VR128RegClass &&
Sanjay Patel30145672015-09-01 20:51:51 +0000[diff] [blame]6372 Subtarget.isUnalignedMem16Slow())
Evan Cheng0ce84482010-07-02 20:36:18 +0000[diff] [blame]6373 // Do not introduce a slow unaligned store.
6374 return false;
Sanjay Patel9e916dc2015-08-21 20:17:26 +0000[diff] [blame]6375 // FIXME: If a VR128 can have size 32, we should be checking if a 32-byte
6376 // memory access is slow above.
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6377 unsigned Alignment = RC->getSize() == 32 ? 32 : 16;
6378 bool isAligned = (*MMOs.first) &&
6379 (*MMOs.first)->getAlignment() >= Alignment;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6380 SDNode *Store =
6381 DAG.getMachineNode(getStoreRegOpcode(0, DstRC, isAligned, Subtarget),
6382 dl, MVT::Other, AddrOps);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6383 NewNodes.push_back(Store);
Dan Gohmandd76bb22009-10-09 18:10:05 +0000[diff] [blame]6384
6385 // Preserve memory reference information.
Craig Topper9e71b822015-02-10 06:29:28 +0000[diff] [blame]6386 cast<MachineSDNode>(Store)->setMemRefs(MMOs.first, MMOs.second);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6387 }
6388
6389 return true;
6390}
6391
6392unsigned X86InstrInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6393 bool UnfoldLoad, bool UnfoldStore,
6394 unsigned *LoadRegIndex) const {
Chris Lattner1c090c02010-10-07 23:08:41 +0000[diff] [blame]6395 DenseMap<unsigned, std::pair<unsigned,unsigned> >::const_iterator I =
6396 MemOp2RegOpTable.find(Opc);
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6397 if (I == MemOp2RegOpTable.end())
6398 return 0;
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6399 bool FoldedLoad = I->second.second & TB_FOLDED_LOAD;
6400 bool FoldedStore = I->second.second & TB_FOLDED_STORE;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6401 if (UnfoldLoad && !FoldedLoad)
6402 return 0;
6403 if (UnfoldStore && !FoldedStore)
6404 return 0;
Dan Gohman49fa51d2009-10-30 22:18:41 +0000[diff] [blame]6405 if (LoadRegIndex)
Bruno Cardoso Lopes23eb5262011-09-08 18:35:57 +0000[diff] [blame]6406 *LoadRegIndex = I->second.second & TB_INDEX_MASK;
Owen Anderson2a3be7b2008-01-07 01:35:02 +0000[diff] [blame]6407 return I->second.first;
6408}
6409
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6410bool
6411X86InstrInfo::areLoadsFromSameBasePtr(SDNode *Load1, SDNode *Load2,
6412 int64_t &Offset1, int64_t &Offset2) const {
6413 if (!Load1->isMachineOpcode() || !Load2->isMachineOpcode())
6414 return false;
6415 unsigned Opc1 = Load1->getMachineOpcode();
6416 unsigned Opc2 = Load2->getMachineOpcode();
6417 switch (Opc1) {
6418 default: return false;
6419 case X86::MOV8rm:
6420 case X86::MOV16rm:
6421 case X86::MOV32rm:
6422 case X86::MOV64rm:
6423 case X86::LD_Fp32m:
6424 case X86::LD_Fp64m:
6425 case X86::LD_Fp80m:
6426 case X86::MOVSSrm:
6427 case X86::MOVSDrm:
6428 case X86::MMX_MOVD64rm:
6429 case X86::MMX_MOVQ64rm:
6430 case X86::FsMOVAPSrm:
6431 case X86::FsMOVAPDrm:
6432 case X86::MOVAPSrm:
6433 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6434 case X86::MOVAPDrm:
6435 case X86::MOVDQArm:
6436 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6437 // AVX load instructions
6438 case X86::VMOVSSrm:
6439 case X86::VMOVSDrm:
6440 case X86::FsVMOVAPSrm:
6441 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6442 case X86::VMOVAPSrm:
6443 case X86::VMOVUPSrm:
6444 case X86::VMOVAPDrm:
6445 case X86::VMOVDQArm:
6446 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6447 case X86::VMOVAPSYrm:
6448 case X86::VMOVUPSYrm:
6449 case X86::VMOVAPDYrm:
6450 case X86::VMOVDQAYrm:
6451 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6452 break;
6453 }
6454 switch (Opc2) {
6455 default: return false;
6456 case X86::MOV8rm:
6457 case X86::MOV16rm:
6458 case X86::MOV32rm:
6459 case X86::MOV64rm:
6460 case X86::LD_Fp32m:
6461 case X86::LD_Fp64m:
6462 case X86::LD_Fp80m:
6463 case X86::MOVSSrm:
6464 case X86::MOVSDrm:
6465 case X86::MMX_MOVD64rm:
6466 case X86::MMX_MOVQ64rm:
6467 case X86::FsMOVAPSrm:
6468 case X86::FsMOVAPDrm:
6469 case X86::MOVAPSrm:
6470 case X86::MOVUPSrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6471 case X86::MOVAPDrm:
6472 case X86::MOVDQArm:
6473 case X86::MOVDQUrm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6474 // AVX load instructions
6475 case X86::VMOVSSrm:
6476 case X86::VMOVSDrm:
6477 case X86::FsVMOVAPSrm:
6478 case X86::FsVMOVAPDrm:
Bruno Cardoso Lopesd560b8c2011-09-14 02:36:58 +0000[diff] [blame]6479 case X86::VMOVAPSrm:
6480 case X86::VMOVUPSrm:
6481 case X86::VMOVAPDrm:
6482 case X86::VMOVDQArm:
6483 case X86::VMOVDQUrm:
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6484 case X86::VMOVAPSYrm:
6485 case X86::VMOVUPSYrm:
6486 case X86::VMOVAPDYrm:
6487 case X86::VMOVDQAYrm:
6488 case X86::VMOVDQUYrm:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6489 break;
6490 }
6491
6492 // Check if chain operands and base addresses match.
6493 if (Load1->getOperand(0) != Load2->getOperand(0) ||
6494 Load1->getOperand(5) != Load2->getOperand(5))
6495 return false;
6496 // Segment operands should match as well.
6497 if (Load1->getOperand(4) != Load2->getOperand(4))
6498 return false;
6499 // Scale should be 1, Index should be Reg0.
6500 if (Load1->getOperand(1) == Load2->getOperand(1) &&
6501 Load1->getOperand(2) == Load2->getOperand(2)) {
6502 if (cast<ConstantSDNode>(Load1->getOperand(1))->getZExtValue() != 1)
6503 return false;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6504
6505 // Now let's examine the displacements.
6506 if (isa<ConstantSDNode>(Load1->getOperand(3)) &&
6507 isa<ConstantSDNode>(Load2->getOperand(3))) {
6508 Offset1 = cast<ConstantSDNode>(Load1->getOperand(3))->getSExtValue();
6509 Offset2 = cast<ConstantSDNode>(Load2->getOperand(3))->getSExtValue();
6510 return true;
6511 }
6512 }
6513 return false;
6514}
6515
6516bool X86InstrInfo::shouldScheduleLoadsNear(SDNode *Load1, SDNode *Load2,
6517 int64_t Offset1, int64_t Offset2,
6518 unsigned NumLoads) const {
6519 assert(Offset2 > Offset1);
6520 if ((Offset2 - Offset1) / 8 > 64)
6521 return false;
6522
6523 unsigned Opc1 = Load1->getMachineOpcode();
6524 unsigned Opc2 = Load2->getMachineOpcode();
6525 if (Opc1 != Opc2)
6526 return false; // FIXME: overly conservative?
6527
6528 switch (Opc1) {
6529 default: break;
6530 case X86::LD_Fp32m:
6531 case X86::LD_Fp64m:
6532 case X86::LD_Fp80m:
6533 case X86::MMX_MOVD64rm:
6534 case X86::MMX_MOVQ64rm:
6535 return false;
6536 }
6537
6538 EVT VT = Load1->getValueType(0);
6539 switch (VT.getSimpleVT().SimpleTy) {
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6540 default:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6541 // XMM registers. In 64-bit mode we can be a bit more aggressive since we
6542 // have 16 of them to play with.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6543 if (Subtarget.is64Bit()) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6544 if (NumLoads >= 3)
6545 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6546 } else if (NumLoads) {
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6547 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6548 }
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6549 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6550 case MVT::i8:
6551 case MVT::i16:
6552 case MVT::i32:
6553 case MVT::i64:
Evan Cheng16cf9342010-01-22 23:49:11 +0000[diff] [blame]6554 case MVT::f32:
6555 case MVT::f64:
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6556 if (NumLoads)
6557 return false;
Bill Wendling8ce69cd2010-06-22 22:16:17 +0000[diff] [blame]6558 break;
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6559 }
6560
6561 return true;
6562}
6563
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6564bool X86InstrInfo::shouldScheduleAdjacent(MachineInstr* First,
6565 MachineInstr *Second) const {
6566 // Check if this processor supports macro-fusion. Since this is a minor
6567 // heuristic, we haven't specifically reserved a feature. hasAVX is a decent
6568 // proxy for SandyBridge+.
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6569 if (!Subtarget.hasAVX())
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6570 return false;
6571
6572 enum {
6573 FuseTest,
6574 FuseCmp,
6575 FuseInc
6576 } FuseKind;
6577
6578 switch(Second->getOpcode()) {
6579 default:
6580 return false;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6581 case X86::JE_1:
6582 case X86::JNE_1:
6583 case X86::JL_1:
6584 case X86::JLE_1:
6585 case X86::JG_1:
6586 case X86::JGE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6587 FuseKind = FuseInc;
6588 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6589 case X86::JB_1:
6590 case X86::JBE_1:
6591 case X86::JA_1:
6592 case X86::JAE_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6593 FuseKind = FuseCmp;
6594 break;
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6595 case X86::JS_1:
6596 case X86::JNS_1:
6597 case X86::JP_1:
6598 case X86::JNP_1:
6599 case X86::JO_1:
6600 case X86::JNO_1:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6601 FuseKind = FuseTest;
6602 break;
6603 }
6604 switch (First->getOpcode()) {
6605 default:
6606 return false;
6607 case X86::TEST8rr:
6608 case X86::TEST16rr:
6609 case X86::TEST32rr:
6610 case X86::TEST64rr:
6611 case X86::TEST8ri:
6612 case X86::TEST16ri:
6613 case X86::TEST32ri:
6614 case X86::TEST32i32:
6615 case X86::TEST64i32:
6616 case X86::TEST64ri32:
6617 case X86::TEST8rm:
6618 case X86::TEST16rm:
6619 case X86::TEST32rm:
6620 case X86::TEST64rm:
Akira Hatanaka7cc27642014-07-10 18:00:53 +0000[diff] [blame]6621 case X86::TEST8ri_NOREX:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6622 case X86::AND16i16:
6623 case X86::AND16ri:
6624 case X86::AND16ri8:
6625 case X86::AND16rm:
6626 case X86::AND16rr:
6627 case X86::AND32i32:
6628 case X86::AND32ri:
6629 case X86::AND32ri8:
6630 case X86::AND32rm:
6631 case X86::AND32rr:
6632 case X86::AND64i32:
6633 case X86::AND64ri32:
6634 case X86::AND64ri8:
6635 case X86::AND64rm:
6636 case X86::AND64rr:
6637 case X86::AND8i8:
6638 case X86::AND8ri:
6639 case X86::AND8rm:
6640 case X86::AND8rr:
6641 return true;
6642 case X86::CMP16i16:
6643 case X86::CMP16ri:
6644 case X86::CMP16ri8:
6645 case X86::CMP16rm:
6646 case X86::CMP16rr:
6647 case X86::CMP32i32:
6648 case X86::CMP32ri:
6649 case X86::CMP32ri8:
6650 case X86::CMP32rm:
6651 case X86::CMP32rr:
6652 case X86::CMP64i32:
6653 case X86::CMP64ri32:
6654 case X86::CMP64ri8:
6655 case X86::CMP64rm:
6656 case X86::CMP64rr:
6657 case X86::CMP8i8:
6658 case X86::CMP8ri:
6659 case X86::CMP8rm:
6660 case X86::CMP8rr:
6661 case X86::ADD16i16:
6662 case X86::ADD16ri:
6663 case X86::ADD16ri8:
6664 case X86::ADD16ri8_DB:
6665 case X86::ADD16ri_DB:
6666 case X86::ADD16rm:
6667 case X86::ADD16rr:
6668 case X86::ADD16rr_DB:
6669 case X86::ADD32i32:
6670 case X86::ADD32ri:
6671 case X86::ADD32ri8:
6672 case X86::ADD32ri8_DB:
6673 case X86::ADD32ri_DB:
6674 case X86::ADD32rm:
6675 case X86::ADD32rr:
6676 case X86::ADD32rr_DB:
6677 case X86::ADD64i32:
6678 case X86::ADD64ri32:
6679 case X86::ADD64ri32_DB:
6680 case X86::ADD64ri8:
6681 case X86::ADD64ri8_DB:
6682 case X86::ADD64rm:
6683 case X86::ADD64rr:
6684 case X86::ADD64rr_DB:
6685 case X86::ADD8i8:
6686 case X86::ADD8mi:
6687 case X86::ADD8mr:
6688 case X86::ADD8ri:
6689 case X86::ADD8rm:
6690 case X86::ADD8rr:
6691 case X86::SUB16i16:
6692 case X86::SUB16ri:
6693 case X86::SUB16ri8:
6694 case X86::SUB16rm:
6695 case X86::SUB16rr:
6696 case X86::SUB32i32:
6697 case X86::SUB32ri:
6698 case X86::SUB32ri8:
6699 case X86::SUB32rm:
6700 case X86::SUB32rr:
6701 case X86::SUB64i32:
6702 case X86::SUB64ri32:
6703 case X86::SUB64ri8:
6704 case X86::SUB64rm:
6705 case X86::SUB64rr:
6706 case X86::SUB8i8:
6707 case X86::SUB8ri:
6708 case X86::SUB8rm:
6709 case X86::SUB8rr:
6710 return FuseKind == FuseCmp || FuseKind == FuseInc;
6711 case X86::INC16r:
6712 case X86::INC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6713 case X86::INC64r:
6714 case X86::INC8r:
6715 case X86::DEC16r:
6716 case X86::DEC32r:
Andrew Trick47740de2013-06-23 09:00:28 +0000[diff] [blame]6717 case X86::DEC64r:
6718 case X86::DEC8r:
6719 return FuseKind == FuseInc;
6720 }
6721}
Evan Cheng4f026f32010-01-22 03:34:51 +0000[diff] [blame]6722
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]6723bool X86InstrInfo::
Owen Anderson4f6bf042008-08-14 22:49:33 +0000[diff] [blame]6724ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]6725 assert(Cond.size() == 1 && "Invalid X86 branch condition!");
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]6726 X86::CondCode CC = static_cast<X86::CondCode>(Cond[0].getImm());
Dan Gohman97d95d62008-10-21 03:29:32 +0000[diff] [blame]6727 if (CC == X86::COND_NE_OR_P || CC == X86::COND_NP_OR_E)
6728 return true;
Evan Chengf93bc7f2008-08-29 23:21:31 +0000[diff] [blame]6729 Cond[0].setImm(GetOppositeBranchCondition(CC));
Chris Lattner3a897f32006-10-21 05:52:40 +0000[diff] [blame]6730 return false;
Chris Lattnerc0fb5672006-10-20 17:42:20 +0000[diff] [blame]6731}
6732
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]6733bool X86InstrInfo::
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]6734isSafeToMoveRegClassDefs(const TargetRegisterClass *RC) const {
6735 // FIXME: Return false for x87 stack register classes for now. We can't
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]6736 // allow any loads of these registers before FpGet_ST0_80.
Evan Chengb5f0ec32009-02-06 17:17:30 +0000[diff] [blame]6737 return !(RC == &X86::CCRRegClass || RC == &X86::RFP32RegClass ||
6738 RC == &X86::RFP64RegClass || RC == &X86::RFP80RegClass);
Evan Chengf7137222008-10-27 07:14:50 +0000[diff] [blame]6739}
6740
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6741/// Return a virtual register initialized with the
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6742/// the global base register value. Output instructions required to
6743/// initialize the register in the function entry block, if necessary.
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]6744///
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6745/// TODO: Eliminate this and move the code to X86MachineFunctionInfo.
6746///
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6747unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6748 assert(!Subtarget.is64Bit() &&
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6749 "X86-64 PIC uses RIP relative addressing");
6750
6751 X86MachineFunctionInfo *X86FI = MF->getInfo<X86MachineFunctionInfo>();
6752 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
6753 if (GlobalBaseReg != 0)
6754 return GlobalBaseReg;
6755
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6756 // Create the register. The code to initialize it is inserted
6757 // later, by the CGBR pass (below).
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]6758 MachineRegisterInfo &RegInfo = MF->getRegInfo();
Jakob Stoklund Olesen38dcd592012-05-20 18:43:00 +0000[diff] [blame]6759 GlobalBaseReg = RegInfo.createVirtualRegister(&X86::GR32_NOSPRegClass);
Dan Gohman6ebe7342008-09-30 00:58:23 +0000[diff] [blame]6760 X86FI->setGlobalBaseReg(GlobalBaseReg);
6761 return GlobalBaseReg;
Dan Gohman24300732008-09-23 18:22:58 +0000[diff] [blame]6762}
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6763
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6764// These are the replaceable SSE instructions. Some of these have Int variants
6765// that we don't include here. We don't want to replace instructions selected
6766// by intrinsics.
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6767static const uint16_t ReplaceableInstrs[][3] = {
Bruno Cardoso Lopes1401e042010-08-12 02:08:52 +0000[diff] [blame]6768 //PackedSingle PackedDouble PackedInt
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]6769 { X86::MOVAPSmr, X86::MOVAPDmr, X86::MOVDQAmr },
6770 { X86::MOVAPSrm, X86::MOVAPDrm, X86::MOVDQArm },
6771 { X86::MOVAPSrr, X86::MOVAPDrr, X86::MOVDQArr },
6772 { X86::MOVUPSmr, X86::MOVUPDmr, X86::MOVDQUmr },
6773 { X86::MOVUPSrm, X86::MOVUPDrm, X86::MOVDQUrm },
Sanjay Patelc03d93b2015-04-15 15:47:51 +0000[diff] [blame]6774 { X86::MOVLPSmr, X86::MOVLPDmr, X86::MOVPQI2QImr },
Jakob Stoklund Olesendbff4e82010-03-30 22:46:53 +0000[diff] [blame]6775 { X86::MOVNTPSmr, X86::MOVNTPDmr, X86::MOVNTDQmr },
6776 { X86::ANDNPSrm, X86::ANDNPDrm, X86::PANDNrm },
6777 { X86::ANDNPSrr, X86::ANDNPDrr, X86::PANDNrr },
6778 { X86::ANDPSrm, X86::ANDPDrm, X86::PANDrm },
6779 { X86::ANDPSrr, X86::ANDPDrr, X86::PANDrr },
6780 { X86::ORPSrm, X86::ORPDrm, X86::PORrm },
6781 { X86::ORPSrr, X86::ORPDrr, X86::PORrr },
6782 { X86::XORPSrm, X86::XORPDrm, X86::PXORrm },
6783 { X86::XORPSrr, X86::XORPDrr, X86::PXORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6784 // AVX 128-bit support
6785 { X86::VMOVAPSmr, X86::VMOVAPDmr, X86::VMOVDQAmr },
6786 { X86::VMOVAPSrm, X86::VMOVAPDrm, X86::VMOVDQArm },
6787 { X86::VMOVAPSrr, X86::VMOVAPDrr, X86::VMOVDQArr },
6788 { X86::VMOVUPSmr, X86::VMOVUPDmr, X86::VMOVDQUmr },
6789 { X86::VMOVUPSrm, X86::VMOVUPDrm, X86::VMOVDQUrm },
Sanjay Patel2161c492015-04-17 17:02:37 +0000[diff] [blame]6790 { X86::VMOVLPSmr, X86::VMOVLPDmr, X86::VMOVPQI2QImr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6791 { X86::VMOVNTPSmr, X86::VMOVNTPDmr, X86::VMOVNTDQmr },
6792 { X86::VANDNPSrm, X86::VANDNPDrm, X86::VPANDNrm },
6793 { X86::VANDNPSrr, X86::VANDNPDrr, X86::VPANDNrr },
6794 { X86::VANDPSrm, X86::VANDPDrm, X86::VPANDrm },
6795 { X86::VANDPSrr, X86::VANDPDrr, X86::VPANDrr },
6796 { X86::VORPSrm, X86::VORPDrm, X86::VPORrm },
6797 { X86::VORPSrr, X86::VORPDrr, X86::VPORrr },
Bruno Cardoso Lopes7f704b32010-08-12 20:20:53 +0000[diff] [blame]6798 { X86::VXORPSrm, X86::VXORPDrm, X86::VPXORrm },
6799 { X86::VXORPSrr, X86::VXORPDrr, X86::VPXORrr },
Bruno Cardoso Lopes67785972011-07-14 18:50:58 +0000[diff] [blame]6800 // AVX 256-bit support
6801 { X86::VMOVAPSYmr, X86::VMOVAPDYmr, X86::VMOVDQAYmr },
6802 { X86::VMOVAPSYrm, X86::VMOVAPDYrm, X86::VMOVDQAYrm },
6803 { X86::VMOVAPSYrr, X86::VMOVAPDYrr, X86::VMOVDQAYrr },
6804 { X86::VMOVUPSYmr, X86::VMOVUPDYmr, X86::VMOVDQUYmr },
6805 { X86::VMOVUPSYrm, X86::VMOVUPDYrm, X86::VMOVDQUYrm },
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]6806 { X86::VMOVNTPSYmr, X86::VMOVNTPDYmr, X86::VMOVNTDQYmr }
6807};
6808
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6809static const uint16_t ReplaceableInstrsAVX2[][3] = {
Craig Topper05baa852011-11-15 05:55:35 +0000[diff] [blame]6810 //PackedSingle PackedDouble PackedInt
Craig Topperf87a2be2011-11-09 09:37:21 +0000[diff] [blame]6811 { X86::VANDNPSYrm, X86::VANDNPDYrm, X86::VPANDNYrm },
6812 { X86::VANDNPSYrr, X86::VANDNPDYrr, X86::VPANDNYrr },
6813 { X86::VANDPSYrm, X86::VANDPDYrm, X86::VPANDYrm },
6814 { X86::VANDPSYrr, X86::VANDPDYrr, X86::VPANDYrr },
6815 { X86::VORPSYrm, X86::VORPDYrm, X86::VPORYrm },
6816 { X86::VORPSYrr, X86::VORPDYrr, X86::VPORYrr },
6817 { X86::VXORPSYrm, X86::VXORPDYrm, X86::VPXORYrm },
Craig Topper12b72de2011-11-29 05:37:58 +0000[diff] [blame]6818 { X86::VXORPSYrr, X86::VXORPDYrr, X86::VPXORYrr },
6819 { X86::VEXTRACTF128mr, X86::VEXTRACTF128mr, X86::VEXTRACTI128mr },
6820 { X86::VEXTRACTF128rr, X86::VEXTRACTF128rr, X86::VEXTRACTI128rr },
6821 { X86::VINSERTF128rm, X86::VINSERTF128rm, X86::VINSERTI128rm },
6822 { X86::VINSERTF128rr, X86::VINSERTF128rr, X86::VINSERTI128rr },
6823 { X86::VPERM2F128rm, X86::VPERM2F128rm, X86::VPERM2I128rm },
Quentin Colombet6f12ae02014-03-26 00:10:22 +0000[diff] [blame]6824 { X86::VPERM2F128rr, X86::VPERM2F128rr, X86::VPERM2I128rr },
6825 { X86::VBROADCASTSSrm, X86::VBROADCASTSSrm, X86::VPBROADCASTDrm},
6826 { X86::VBROADCASTSSrr, X86::VBROADCASTSSrr, X86::VPBROADCASTDrr},
6827 { X86::VBROADCASTSSYrr, X86::VBROADCASTSSYrr, X86::VPBROADCASTDYrr},
6828 { X86::VBROADCASTSSYrm, X86::VBROADCASTSSYrm, X86::VPBROADCASTDYrm},
6829 { X86::VBROADCASTSDYrr, X86::VBROADCASTSDYrr, X86::VPBROADCASTQYrr},
6830 { X86::VBROADCASTSDYrm, X86::VBROADCASTSDYrm, X86::VPBROADCASTQYrm}
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6831};
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6832
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6833// FIXME: Some shuffle and unpack instructions have equivalents in different
6834// domains, but they require a bit more work than just switching opcodes.
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6835
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6836static const uint16_t *lookup(unsigned opcode, unsigned domain) {
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]6837 for (const uint16_t (&Row)[3] : ReplaceableInstrs)
6838 if (Row[domain-1] == opcode)
6839 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6840 return nullptr;
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]6841}
6842
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6843static const uint16_t *lookupAVX2(unsigned opcode, unsigned domain) {
Craig Topper271f9de2015-12-01 06:13:15 +0000[diff] [blame]6844 for (const uint16_t (&Row)[3] : ReplaceableInstrsAVX2)
6845 if (Row[domain-1] == opcode)
6846 return Row;
Craig Topper062a2ba2014-04-25 05:30:21 +0000[diff] [blame]6847 return nullptr;
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6848}
6849
6850std::pair<uint16_t, uint16_t>
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]6851X86InstrInfo::getExecutionDomain(const MachineInstr *MI) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6852 uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6853 bool hasAVX2 = Subtarget.hasAVX2();
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]6854 uint16_t validDomains = 0;
6855 if (domain && lookup(MI->getOpcode(), domain))
6856 validDomains = 0xe;
6857 else if (domain && lookupAVX2(MI->getOpcode(), domain))
6858 validDomains = hasAVX2 ? 0xe : 0x6;
6859 return std::make_pair(domain, validDomains);
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6860}
6861
Jakob Stoklund Olesenb48c9942011-09-27 22:57:18 +0000[diff] [blame]6862void X86InstrInfo::setExecutionDomain(MachineInstr *MI, unsigned Domain) const {
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6863 assert(Domain>0 && Domain<4 && "Invalid execution domain");
6864 uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
6865 assert(dom && "Not an SSE instruction");
Craig Topper2dac9622012-03-09 07:45:21 +0000[diff] [blame]6866 const uint16_t *table = lookup(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]6867 if (!table) { // try the other table
Eric Christopher6c786a12014-06-10 22:34:31 +0000[diff] [blame]6868 assert((Subtarget.hasAVX2() || Domain < 3) &&
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]6869 "256-bit vector operations only available in AVX2");
Craig Topper649d1c52011-11-15 06:39:01 +0000[diff] [blame]6870 table = lookupAVX2(MI->getOpcode(), dom);
Jakob Stoklund Olesen02845412011-11-23 04:03:08 +0000[diff] [blame]6871 }
Jakob Stoklund Olesenb551aa42010-03-29 23:24:21 +0000[diff] [blame]6872 assert(table && "Cannot change domain");
6873 MI->setDesc(get(table[Domain-1]));
Jakob Stoklund Olesen49e121d2010-03-25 17:25:00 +0000[diff] [blame]6874}
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]6875
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]6876/// Return the noop instruction to use for a noop.
Chris Lattner6a5e7062010-04-26 23:37:21 +0000[diff] [blame]6877void X86InstrInfo::getNoopForMachoTarget(MCInst &NopInst) const {
6878 NopInst.setOpcode(X86::NOOP);
6879}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]6880
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]6881// This code must remain in sync with getJumpInstrTableEntryBound in this class!
6882// In particular, getJumpInstrTableEntryBound must always return an upper bound
6883// on the encoding lengths of the instructions generated by
6884// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]6885void X86InstrInfo::getUnconditionalBranch(
6886 MCInst &Branch, const MCSymbolRefExpr *BranchTarget) const {
Craig Topper49758aa2015-01-06 04:23:53 +0000[diff] [blame]6887 Branch.setOpcode(X86::JMP_1);
Jim Grosbache9119e42015-05-13 18:37:00 +0000[diff] [blame]6888 Branch.addOperand(MCOperand::createExpr(BranchTarget));
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]6889}
6890
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]6891// This code must remain in sync with getJumpInstrTableEntryBound in this class!
6892// In particular, getJumpInstrTableEntryBound must always return an upper bound
6893// on the encoding lengths of the instructions generated by
6894// getUnconditionalBranch and getTrap.
Tom Roeder44cb65f2014-06-05 19:29:43 +0000[diff] [blame]6895void X86InstrInfo::getTrap(MCInst &MI) const {
6896 MI.setOpcode(X86::TRAP);
6897}
6898
Tom Roedereb7a3032014-11-11 21:08:02 +0000[diff] [blame]6899// See getTrap and getUnconditionalBranch for conditions on the value returned
6900// by this function.
6901unsigned X86InstrInfo::getJumpInstrTableEntryBound() const {
6902 // 5 bytes suffice: JMP_4 Symbol@PLT is uses 1 byte (E9) for the JMP_4 and 4
6903 // bytes for the symbol offset. And TRAP is ud2, which is two bytes (0F 0B).
6904 return 5;
6905}
6906
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]6907bool X86InstrInfo::isHighLatencyDef(int opc) const {
6908 switch (opc) {
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6909 default: return false;
6910 case X86::DIVSDrm:
6911 case X86::DIVSDrm_Int:
6912 case X86::DIVSDrr:
6913 case X86::DIVSDrr_Int:
6914 case X86::DIVSSrm:
6915 case X86::DIVSSrm_Int:
6916 case X86::DIVSSrr:
6917 case X86::DIVSSrr_Int:
6918 case X86::SQRTPDm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6919 case X86::SQRTPDr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6920 case X86::SQRTPSm:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6921 case X86::SQRTPSr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6922 case X86::SQRTSDm:
6923 case X86::SQRTSDm_Int:
6924 case X86::SQRTSDr:
6925 case X86::SQRTSDr_Int:
6926 case X86::SQRTSSm:
6927 case X86::SQRTSSm_Int:
6928 case X86::SQRTSSr:
6929 case X86::SQRTSSr_Int:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6930 // AVX instructions with high latency
6931 case X86::VDIVSDrm:
6932 case X86::VDIVSDrm_Int:
6933 case X86::VDIVSDrr:
6934 case X86::VDIVSDrr_Int:
6935 case X86::VDIVSSrm:
6936 case X86::VDIVSSrm_Int:
6937 case X86::VDIVSSrr:
6938 case X86::VDIVSSrr_Int:
6939 case X86::VSQRTPDm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6940 case X86::VSQRTPDr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6941 case X86::VSQRTPSm:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6942 case X86::VSQRTPSr:
Bruno Cardoso Lopesc69d68a2011-09-15 22:15:52 +0000[diff] [blame]6943 case X86::VSQRTSDm:
6944 case X86::VSQRTSDm_Int:
6945 case X86::VSQRTSDr:
6946 case X86::VSQRTSSm:
6947 case X86::VSQRTSSm_Int:
6948 case X86::VSQRTSSr:
Robert Khasanov1cf354c2014-10-28 18:22:41 +0000[diff] [blame]6949 case X86::VSQRTPDZm:
6950 case X86::VSQRTPDZr:
6951 case X86::VSQRTPSZm:
6952 case X86::VSQRTPSZr:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]6953 case X86::VSQRTSDZm:
6954 case X86::VSQRTSDZm_Int:
6955 case X86::VSQRTSDZr:
6956 case X86::VSQRTSSZm_Int:
6957 case X86::VSQRTSSZr:
6958 case X86::VSQRTSSZm:
6959 case X86::VDIVSDZrm:
6960 case X86::VDIVSDZrr:
6961 case X86::VDIVSSZrm:
6962 case X86::VDIVSSZrr:
Elena Demikhovsky534015e2013-09-02 07:12:29 +0000[diff] [blame]6963
6964 case X86::VGATHERQPSZrm:
6965 case X86::VGATHERQPDZrm:
6966 case X86::VGATHERDPDZrm:
6967 case X86::VGATHERDPSZrm:
6968 case X86::VPGATHERQDZrm:
6969 case X86::VPGATHERQQZrm:
6970 case X86::VPGATHERDDZrm:
Elena Demikhovsky402ee642013-09-02 07:41:01 +0000[diff] [blame]6971 case X86::VPGATHERDQZrm:
6972 case X86::VSCATTERQPDZmr:
6973 case X86::VSCATTERQPSZmr:
6974 case X86::VSCATTERDPDZmr:
6975 case X86::VSCATTERDPSZmr:
6976 case X86::VPSCATTERQDZmr:
6977 case X86::VPSCATTERQQZmr:
6978 case X86::VPSCATTERDDZmr:
6979 case X86::VPSCATTERDQZmr:
Evan Cheng63c76082010-10-19 18:58:51 +0000[diff] [blame]6980 return true;
6981 }
6982}
6983
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]6984bool X86InstrInfo::
Matthias Braun88e21312015-06-13 03:42:11 +0000[diff] [blame]6985hasHighOperandLatency(const TargetSchedModel &SchedModel,
Andrew Trick641e2d42011-03-05 08:00:22 +0000[diff] [blame]6986 const MachineRegisterInfo *MRI,
6987 const MachineInstr *DefMI, unsigned DefIdx,
6988 const MachineInstr *UseMI, unsigned UseIdx) const {
6989 return isHighLatencyDef(DefMI->getOpcode());
6990}
6991
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]6992bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
6993 const MachineBasicBlock *MBB) const {
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]6994 assert((Inst.getNumOperands() == 3 || Inst.getNumOperands() == 4) &&
6995 "Reassociation needs binary operators");
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]6996
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]6997 // Integer binary math/logic instructions have a third source operand:
6998 // the EFLAGS register. That operand must be both defined here and never
6999 // used; ie, it must be dead. If the EFLAGS operand is live, then we can
7000 // not change anything because rearranging the operands could affect other
7001 // instructions that depend on the exact status flags (zero, sign, etc.)
7002 // that are set by using these particular operands with this operation.
7003 if (Inst.getNumOperands() == 4) {
7004 assert(Inst.getOperand(3).isReg() &&
7005 Inst.getOperand(3).getReg() == X86::EFLAGS &&
7006 "Unexpected operand in reassociable instruction");
7007 if (!Inst.getOperand(3).isDead())
7008 return false;
7009 }
Sanjay Patele79b43a2015-06-23 00:39:40 +0000[diff] [blame]7010
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7011 return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
Sanjay Patel08829ba2015-06-10 20:32:21 +0000[diff] [blame]7012}
7013
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7014// TODO: There are many more machine instruction opcodes to match:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7015// 1. Other data types (integer, vectors)
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7016// 2. Other math / logic operations (xor, or)
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7017// 3. Other forms of the same operation (intrinsics and other variants)
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7018bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7019 switch (Inst.getOpcode()) {
Sanjay Patel7c912892015-08-28 14:09:48 +0000[diff] [blame]7020 case X86::AND8rr:
7021 case X86::AND16rr:
7022 case X86::AND32rr:
7023 case X86::AND64rr:
Sanjay Pateld9a5c222015-08-31 20:27:03 +0000[diff] [blame]7024 case X86::OR8rr:
7025 case X86::OR16rr:
7026 case X86::OR32rr:
7027 case X86::OR64rr:
Sanjay Patelc9ae9d72015-09-03 16:36:16 +0000[diff] [blame]7028 case X86::XOR8rr:
7029 case X86::XOR16rr:
7030 case X86::XOR32rr:
7031 case X86::XOR64rr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7032 case X86::IMUL16rr:
7033 case X86::IMUL32rr:
7034 case X86::IMUL64rr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7035 case X86::PANDrr:
7036 case X86::PORrr:
7037 case X86::PXORrr:
7038 case X86::VPANDrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7039 case X86::VPANDYrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7040 case X86::VPORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7041 case X86::VPORYrr:
Sanjay Patel8b960d22015-09-12 19:47:50 +0000[diff] [blame]7042 case X86::VPXORrr:
Sanjay Patela114a102015-09-30 22:25:55 +0000[diff] [blame]7043 case X86::VPXORYrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7044 // Normal min/max instructions are not commutative because of NaN and signed
7045 // zero semantics, but these are. Thus, there's no need to check for global
7046 // relaxed math; the instructions themselves have the properties we need.
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7047 case X86::MAXCPDrr:
7048 case X86::MAXCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7049 case X86::MAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7050 case X86::MAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7051 case X86::MINCPDrr:
7052 case X86::MINCPSrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7053 case X86::MINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7054 case X86::MINCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7055 case X86::VMAXCPDrr:
7056 case X86::VMAXCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7057 case X86::VMAXCPDYrr:
7058 case X86::VMAXCPSYrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7059 case X86::VMAXCSDrr:
Sanjay Patel4e3ee1e2015-08-19 21:18:46 +0000[diff] [blame]7060 case X86::VMAXCSSrr:
Sanjay Patelcf942fa2015-08-21 18:06:49 +0000[diff] [blame]7061 case X86::VMINCPDrr:
7062 case X86::VMINCPSrr:
Sanjay Patelf0bc07f2015-08-21 21:04:21 +0000[diff] [blame]7063 case X86::VMINCPDYrr:
7064 case X86::VMINCPSYrr:
Sanjay Patel9e5927f2015-08-19 21:27:27 +0000[diff] [blame]7065 case X86::VMINCSDrr:
Sanjay Patel40d4eb42015-08-15 17:01:54 +0000[diff] [blame]7066 case X86::VMINCSSrr:
Sanjay Patel9ff46262015-07-31 16:21:55 +0000[diff] [blame]7067 return true;
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]7068 case X86::ADDPDrr:
7069 case X86::ADDPSrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]7070 case X86::ADDSDrr:
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7071 case X86::ADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]7072 case X86::MULPDrr:
7073 case X86::MULPSrr:
7074 case X86::MULSDrr:
7075 case X86::MULSSrr:
Sanjay Patele0178262015-08-08 19:08:20 +0000[diff] [blame]7076 case X86::VADDPDrr:
7077 case X86::VADDPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]7078 case X86::VADDPDYrr:
7079 case X86::VADDPSYrr:
Sanjay Patelea81edf2015-07-09 22:48:54 +0000[diff] [blame]7080 case X86::VADDSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]7081 case X86::VADDSSrr:
Sanjay Patel2c6a0152015-08-11 20:19:23 +0000[diff] [blame]7082 case X86::VMULPDrr:
7083 case X86::VMULPSrr:
Sanjay Patel260b6d32015-08-12 00:29:10 +0000[diff] [blame]7084 case X86::VMULPDYrr:
7085 case X86::VMULPSYrr:
Sanjay Patel81beefc2015-07-09 22:58:39 +0000[diff] [blame]7086 case X86::VMULSDrr:
Sanjay Patel093fb172015-07-08 22:35:20 +0000[diff] [blame]7087 case X86::VMULSSrr:
Sanjay Patel5bfbb362015-07-30 00:04:21 +0000[diff] [blame]7088 return Inst.getParent()->getParent()->getTarget().Options.UnsafeFPMath;
Sanjay Patel681a56a2015-07-06 22:35:29 +0000[diff] [blame]7089 default:
7090 return false;
7091 }
7092}
7093
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7094/// This is an architecture-specific helper function of reassociateOps.
7095/// Set special operand attributes for new instructions after reassociation.
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7096void X86InstrInfo::setSpecialOperandAttr(MachineInstr &OldMI1,
7097 MachineInstr &OldMI2,
7098 MachineInstr &NewMI1,
7099 MachineInstr &NewMI2) const {
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7100 // Integer instructions define an implicit EFLAGS source register operand as
7101 // the third source (fourth total) operand.
7102 if (OldMI1.getNumOperands() != 4 || OldMI2.getNumOperands() != 4)
7103 return;
7104
7105 assert(NewMI1.getNumOperands() == 4 && NewMI2.getNumOperands() == 4 &&
7106 "Unexpected instruction type for reassociation");
Chad Rosier03a47302015-09-21 15:09:11 +0000[diff] [blame]7107
Sanjay Patel75ced272015-08-04 15:21:56 +0000[diff] [blame]7108 MachineOperand &OldOp1 = OldMI1.getOperand(3);
7109 MachineOperand &OldOp2 = OldMI2.getOperand(3);
7110 MachineOperand &NewOp1 = NewMI1.getOperand(3);
7111 MachineOperand &NewOp2 = NewMI2.getOperand(3);
7112
7113 assert(OldOp1.isReg() && OldOp1.getReg() == X86::EFLAGS && OldOp1.isDead() &&
7114 "Must have dead EFLAGS operand in reassociable instruction");
7115 assert(OldOp2.isReg() && OldOp2.getReg() == X86::EFLAGS && OldOp2.isDead() &&
7116 "Must have dead EFLAGS operand in reassociable instruction");
7117
7118 (void)OldOp1;
7119 (void)OldOp2;
7120
7121 assert(NewOp1.isReg() && NewOp1.getReg() == X86::EFLAGS &&
7122 "Unexpected operand in reassociable instruction");
7123 assert(NewOp2.isReg() && NewOp2.getReg() == X86::EFLAGS &&
7124 "Unexpected operand in reassociable instruction");
7125
7126 // Mark the new EFLAGS operands as dead to be helpful to subsequent iterations
7127 // of this pass or other passes. The EFLAGS operands must be dead in these new
7128 // instructions because the EFLAGS operands in the original instructions must
7129 // be dead in order for reassociation to occur.
7130 NewOp1.setIsDead();
7131 NewOp2.setIsDead();
7132}
7133
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7134std::pair<unsigned, unsigned>
7135X86InstrInfo::decomposeMachineOperandsTargetFlags(unsigned TF) const {
7136 return std::make_pair(TF, 0u);
7137}
7138
7139ArrayRef<std::pair<unsigned, const char *>>
7140X86InstrInfo::getSerializableDirectMachineOperandTargetFlags() const {
7141 using namespace X86II;
Hal Finkel982e8d42015-08-30 08:07:29 +0000[diff] [blame]7142 static const std::pair<unsigned, const char *> TargetFlags[] = {
Alex Lorenz49873a82015-08-06 00:44:07 +0000[diff] [blame]7143 {MO_GOT_ABSOLUTE_ADDRESS, "x86-got-absolute-address"},
7144 {MO_PIC_BASE_OFFSET, "x86-pic-base-offset"},
7145 {MO_GOT, "x86-got"},
7146 {MO_GOTOFF, "x86-gotoff"},
7147 {MO_GOTPCREL, "x86-gotpcrel"},
7148 {MO_PLT, "x86-plt"},
7149 {MO_TLSGD, "x86-tlsgd"},
7150 {MO_TLSLD, "x86-tlsld"},
7151 {MO_TLSLDM, "x86-tlsldm"},
7152 {MO_GOTTPOFF, "x86-gottpoff"},
7153 {MO_INDNTPOFF, "x86-indntpoff"},
7154 {MO_TPOFF, "x86-tpoff"},
7155 {MO_DTPOFF, "x86-dtpoff"},
7156 {MO_NTPOFF, "x86-ntpoff"},
7157 {MO_GOTNTPOFF, "x86-gotntpoff"},
7158 {MO_DLLIMPORT, "x86-dllimport"},
7159 {MO_DARWIN_STUB, "x86-darwin-stub"},
7160 {MO_DARWIN_NONLAZY, "x86-darwin-nonlazy"},
7161 {MO_DARWIN_NONLAZY_PIC_BASE, "x86-darwin-nonlazy-pic-base"},
7162 {MO_DARWIN_HIDDEN_NONLAZY_PIC_BASE, "x86-darwin-hidden-nonlazy-pic-base"},
7163 {MO_TLVP, "x86-tlvp"},
7164 {MO_TLVP_PIC_BASE, "x86-tlvp-pic-base"},
7165 {MO_SECREL, "x86-secrel"}};
7166 return makeArrayRef(TargetFlags);
7167}
7168
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7169namespace {
Sanjay Patel203ee502015-02-17 21:55:20 +0000[diff] [blame]7170 /// Create Global Base Reg pass. This initializes the PIC
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7171 /// global base register for x86-32.
7172 struct CGBR : public MachineFunctionPass {
7173 static char ID;
Owen Andersona7aed182010-08-06 18:33:48 +0000[diff] [blame]7174 CGBR() : MachineFunctionPass(ID) {}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7175
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7176 bool runOnMachineFunction(MachineFunction &MF) override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7177 const X86TargetMachine *TM =
7178 static_cast<const X86TargetMachine *>(&MF.getTarget());
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7179 const X86Subtarget &STI = MF.getSubtarget<X86Subtarget>();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7180
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]7181 // Don't do anything if this is 64-bit as 64-bit PIC
7182 // uses RIP relative addressing.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7183 if (STI.is64Bit())
Eric Christopher0d5c99e2014-05-22 01:46:02 +0000[diff] [blame]7184 return false;
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7185
7186 // Only emit a global base reg in PIC mode.
7187 if (TM->getRelocationModel() != Reloc::PIC_)
7188 return false;
7189
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]7190 X86MachineFunctionInfo *X86FI = MF.getInfo<X86MachineFunctionInfo>();
7191 unsigned GlobalBaseReg = X86FI->getGlobalBaseReg();
7192
7193 // If we didn't need a GlobalBaseReg, don't insert code.
7194 if (GlobalBaseReg == 0)
7195 return false;
7196
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7197 // Insert the set of GlobalBaseReg into the first MBB of the function
7198 MachineBasicBlock &FirstMBB = MF.front();
7199 MachineBasicBlock::iterator MBBI = FirstMBB.begin();
7200 DebugLoc DL = FirstMBB.findDebugLoc(MBBI);
7201 MachineRegisterInfo &RegInfo = MF.getRegInfo();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7202 const X86InstrInfo *TII = STI.getInstrInfo();
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7203
7204 unsigned PC;
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7205 if (STI.isPICStyleGOT())
Craig Topperabadc662012-04-20 06:31:50 +0000[diff] [blame]7206 PC = RegInfo.createVirtualRegister(&X86::GR32RegClass);
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7207 else
Dan Gohman534db8a2010-09-17 20:24:24 +0000[diff] [blame]7208 PC = GlobalBaseReg;
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]7209
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7210 // Operand of MovePCtoStack is completely ignored by asm printer. It's
7211 // only used in JIT code emission as displacement to pc.
7212 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::MOVPC32r), PC).addImm(0);
NAKAMURA Takumi9d29eff2011-01-26 02:03:37 +0000[diff] [blame]7213
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7214 // If we're using vanilla 'GOT' PIC style, we should use relative addressing
7215 // not to pc, but to _GLOBAL_OFFSET_TABLE_ external.
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7216 if (STI.isPICStyleGOT()) {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7217 // Generate addl $__GLOBAL_OFFSET_TABLE_ + [.-piclabel], %some_register
7218 BuildMI(FirstMBB, MBBI, DL, TII->get(X86::ADD32ri), GlobalBaseReg)
7219 .addReg(PC).addExternalSymbol("_GLOBAL_OFFSET_TABLE_",
7220 X86II::MO_GOT_ABSOLUTE_ADDRESS);
7221 }
7222
7223 return true;
7224 }
7225
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7226 const char *getPassName() const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7227 return "X86 PIC Global Base Reg Initialization";
7228 }
7229
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7230 void getAnalysisUsage(AnalysisUsage &AU) const override {
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7231 AU.setPreservesCFG();
7232 MachineFunctionPass::getAnalysisUsage(AU);
7233 }
7234 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]7235}
Dan Gohmand7b5ce32010-07-10 09:00:22 +0000[diff] [blame]7236
7237char CGBR::ID = 0;
7238FunctionPass*
Eric Christopher463b84b2014-05-22 01:45:57 +0000[diff] [blame]7239llvm::createX86GlobalBaseRegPass() { return new CGBR(); }
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7240
7241namespace {
7242 struct LDTLSCleanup : public MachineFunctionPass {
7243 static char ID;
7244 LDTLSCleanup() : MachineFunctionPass(ID) {}
7245
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7246 bool runOnMachineFunction(MachineFunction &MF) override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7247 X86MachineFunctionInfo* MFI = MF.getInfo<X86MachineFunctionInfo>();
7248 if (MFI->getNumLocalDynamicTLSAccesses() < 2) {
7249 // No point folding accesses if there isn't at least two.
7250 return false;
7251 }
7252
7253 MachineDominatorTree *DT = &getAnalysis<MachineDominatorTree>();
7254 return VisitNode(DT->getRootNode(), 0);
7255 }
7256
7257 // Visit the dominator subtree rooted at Node in pre-order.
7258 // If TLSBaseAddrReg is non-null, then use that to replace any
7259 // TLS_base_addr instructions. Otherwise, create the register
7260 // when the first such instruction is seen, and then use it
7261 // as we encounter more instructions.
7262 bool VisitNode(MachineDomTreeNode *Node, unsigned TLSBaseAddrReg) {
7263 MachineBasicBlock *BB = Node->getBlock();
7264 bool Changed = false;
7265
7266 // Traverse the current block.
7267 for (MachineBasicBlock::iterator I = BB->begin(), E = BB->end(); I != E;
7268 ++I) {
7269 switch (I->getOpcode()) {
7270 case X86::TLS_base_addr32:
7271 case X86::TLS_base_addr64:
7272 if (TLSBaseAddrReg)
7273 I = ReplaceTLSBaseAddrCall(I, TLSBaseAddrReg);
7274 else
7275 I = SetRegister(I, &TLSBaseAddrReg);
7276 Changed = true;
7277 break;
7278 default:
7279 break;
7280 }
7281 }
7282
7283 // Visit the children of this block in the dominator tree.
7284 for (MachineDomTreeNode::iterator I = Node->begin(), E = Node->end();
7285 I != E; ++I) {
7286 Changed |= VisitNode(*I, TLSBaseAddrReg);
7287 }
7288
7289 return Changed;
7290 }
7291
7292 // Replace the TLS_base_addr instruction I with a copy from
7293 // TLSBaseAddrReg, returning the new instruction.
7294 MachineInstr *ReplaceTLSBaseAddrCall(MachineInstr *I,
7295 unsigned TLSBaseAddrReg) {
7296 MachineFunction *MF = I->getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7297 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7298 const bool is64Bit = STI.is64Bit();
7299 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7300
7301 // Insert a Copy from TLSBaseAddrReg to RAX/EAX.
7302 MachineInstr *Copy = BuildMI(*I->getParent(), I, I->getDebugLoc(),
7303 TII->get(TargetOpcode::COPY),
7304 is64Bit ? X86::RAX : X86::EAX)
7305 .addReg(TLSBaseAddrReg);
7306
7307 // Erase the TLS_base_addr instruction.
7308 I->eraseFromParent();
7309
7310 return Copy;
7311 }
7312
7313 // Create a virtal register in *TLSBaseAddrReg, and populate it by
7314 // inserting a copy instruction after I. Returns the new instruction.
7315 MachineInstr *SetRegister(MachineInstr *I, unsigned *TLSBaseAddrReg) {
7316 MachineFunction *MF = I->getParent()->getParent();
Eric Christopher05b81972015-02-02 17:38:43 +0000[diff] [blame]7317 const X86Subtarget &STI = MF->getSubtarget<X86Subtarget>();
7318 const bool is64Bit = STI.is64Bit();
7319 const X86InstrInfo *TII = STI.getInstrInfo();
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7320
7321 // Create a virtual register for the TLS base address.
7322 MachineRegisterInfo &RegInfo = MF->getRegInfo();
7323 *TLSBaseAddrReg = RegInfo.createVirtualRegister(is64Bit
7324 ? &X86::GR64RegClass
7325 : &X86::GR32RegClass);
7326
7327 // Insert a copy from RAX/EAX to TLSBaseAddrReg.
7328 MachineInstr *Next = I->getNextNode();
7329 MachineInstr *Copy = BuildMI(*I->getParent(), Next, I->getDebugLoc(),
7330 TII->get(TargetOpcode::COPY),
7331 *TLSBaseAddrReg)
7332 .addReg(is64Bit ? X86::RAX : X86::EAX);
7333
7334 return Copy;
7335 }
7336
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7337 const char *getPassName() const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7338 return "Local Dynamic TLS Access Clean-up";
7339 }
7340
Craig Topper2d9361e2014-03-09 07:44:38 +0000[diff] [blame]7341 void getAnalysisUsage(AnalysisUsage &AU) const override {
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7342 AU.setPreservesCFG();
7343 AU.addRequired<MachineDominatorTree>();
7344 MachineFunctionPass::getAnalysisUsage(AU);
7345 }
7346 };
Alexander Kornienkof00654e2015-06-23 09:49:53 +0000[diff] [blame]7347}
Hans Wennborg789acfb2012-06-01 16:27:21 +0000[diff] [blame]7348
7349char LDTLSCleanup::ID = 0;
7350FunctionPass*
7351llvm::createCleanupLocalDynamicTLSPass() { return new LDTLSCleanup(); }