Jack Carter | 9770097 | 2013-08-13 20:19:16 +0000 | [diff] [blame] | 1 | def addrimm12 : ComplexPattern<iPTR, 2, "selectIntAddrMM", [frameindex]>; |
| 2 | |
Jozef Kolek | aa2b927 | 2014-11-27 14:41:44 +0000 | [diff] [blame^] | 3 | def simm4 : Operand<i32> { |
| 4 | let DecoderMethod = "DecodeSimm4"; |
| 5 | } |
| 6 | def li_simm7 : Operand<i32> { |
| 7 | let DecoderMethod = "DecodeLiSimm7"; |
| 8 | } |
Zoran Jovanovic | b26f889 | 2014-10-10 13:45:34 +0000 | [diff] [blame] | 9 | |
Jack Carter | 9770097 | 2013-08-13 20:19:16 +0000 | [diff] [blame] | 10 | def simm12 : Operand<i32> { |
| 11 | let DecoderMethod = "DecodeSimm12"; |
| 12 | } |
| 13 | |
Zoran Jovanovic | c74e3eb9 | 2014-09-12 14:29:54 +0000 | [diff] [blame] | 14 | def uimm5_lsl2 : Operand<OtherVT> { |
| 15 | let EncoderMethod = "getUImm5Lsl2Encoding"; |
| 16 | } |
| 17 | |
Zoran Jovanovic | 42b8444 | 2014-10-23 11:13:59 +0000 | [diff] [blame] | 18 | def uimm6_lsl2 : Operand<i32> { |
| 19 | let EncoderMethod = "getUImm6Lsl2Encoding"; |
Jozef Kolek | aa2b927 | 2014-11-27 14:41:44 +0000 | [diff] [blame^] | 20 | let DecoderMethod = "DecodeUImm6Lsl2"; |
Zoran Jovanovic | 42b8444 | 2014-10-23 11:13:59 +0000 | [diff] [blame] | 21 | } |
| 22 | |
Zoran Jovanovic | 98bd58c | 2014-10-10 14:37:30 +0000 | [diff] [blame] | 23 | def simm9_addiusp : Operand<i32> { |
| 24 | let EncoderMethod = "getSImm9AddiuspValue"; |
| 25 | } |
| 26 | |
Zoran Jovanovic | 4a00fdc | 2014-10-23 10:42:01 +0000 | [diff] [blame] | 27 | def uimm3_shift : Operand<i32> { |
| 28 | let EncoderMethod = "getUImm3Mod8Encoding"; |
| 29 | } |
| 30 | |
Zoran Jovanovic | bac3619 | 2014-10-23 11:06:34 +0000 | [diff] [blame] | 31 | def simm3_lsa2 : Operand<i32> { |
| 32 | let EncoderMethod = "getSImm3Lsa2Value"; |
Jozef Kolek | aa2b927 | 2014-11-27 14:41:44 +0000 | [diff] [blame^] | 33 | let DecoderMethod = "DecodeAddiur2Simm7"; |
Zoran Jovanovic | bac3619 | 2014-10-23 11:06:34 +0000 | [diff] [blame] | 34 | } |
| 35 | |
Zoran Jovanovic | 8853171 | 2014-11-05 17:31:00 +0000 | [diff] [blame] | 36 | def uimm4_andi : Operand<i32> { |
| 37 | let EncoderMethod = "getUImm4AndValue"; |
| 38 | } |
| 39 | |
Jozef Kolek | 4d55b4d | 2014-11-19 13:23:58 +0000 | [diff] [blame] | 40 | def immSExtAddiur2 : ImmLeaf<i32, [{return Imm == 1 || Imm == -1 || |
| 41 | ((Imm % 4 == 0) && |
| 42 | Imm < 28 && Imm > 0);}]>; |
| 43 | |
Jozef Kolek | 73f64ea | 2014-11-19 13:11:09 +0000 | [diff] [blame] | 44 | def immSExtAddius5 : ImmLeaf<i32, [{return Imm >= -8 && Imm <= 7;}]>; |
| 45 | |
Zoran Jovanovic | 06c9d55 | 2014-11-05 17:43:00 +0000 | [diff] [blame] | 46 | def immZExtAndi16 : ImmLeaf<i32, |
| 47 | [{return (Imm == 128 || (Imm >= 1 && Imm <= 4) || Imm == 7 || Imm == 8 || |
| 48 | Imm == 15 || Imm == 16 || Imm == 31 || Imm == 32 || Imm == 63 || |
| 49 | Imm == 64 || Imm == 255 || Imm == 32768 || Imm == 65535 );}]>; |
| 50 | |
Zoran Jovanovic | 4a00fdc | 2014-10-23 10:42:01 +0000 | [diff] [blame] | 51 | def immZExt2Shift : ImmLeaf<i32, [{return Imm >= 1 && Imm <= 8;}]>; |
| 52 | |
Zoran Jovanovic | 9bda2f1 | 2014-10-23 10:59:24 +0000 | [diff] [blame] | 53 | def immLi16 : ImmLeaf<i32, [{return Imm >= -1 && Imm <= 126;}]>; |
| 54 | |
Jozef Kolek | e8c9d1e | 2014-11-24 14:39:13 +0000 | [diff] [blame] | 55 | def MicroMipsMemGPRMM16AsmOperand : AsmOperandClass { |
| 56 | let Name = "MicroMipsMem"; |
| 57 | let RenderMethod = "addMicroMipsMemOperands"; |
| 58 | let ParserMethod = "parseMemOperand"; |
| 59 | let PredicateMethod = "isMemWithGRPMM16Base"; |
| 60 | } |
| 61 | |
| 62 | class mem_mm_4_generic : Operand<i32> { |
| 63 | let PrintMethod = "printMemOperand"; |
| 64 | let MIOperandInfo = (ops ptr_rc, simm4); |
| 65 | let OperandType = "OPERAND_MEMORY"; |
| 66 | let ParserMatchClass = MicroMipsMemGPRMM16AsmOperand; |
| 67 | } |
| 68 | |
| 69 | def mem_mm_4 : mem_mm_4_generic { |
| 70 | let EncoderMethod = "getMemEncodingMMImm4"; |
| 71 | } |
| 72 | |
| 73 | def mem_mm_4_lsl1 : mem_mm_4_generic { |
| 74 | let EncoderMethod = "getMemEncodingMMImm4Lsl1"; |
| 75 | } |
| 76 | |
| 77 | def mem_mm_4_lsl2 : mem_mm_4_generic { |
| 78 | let EncoderMethod = "getMemEncodingMMImm4Lsl2"; |
| 79 | } |
| 80 | |
Jack Carter | 9770097 | 2013-08-13 20:19:16 +0000 | [diff] [blame] | 81 | def mem_mm_12 : Operand<i32> { |
| 82 | let PrintMethod = "printMemOperand"; |
| 83 | let MIOperandInfo = (ops GPR32, simm12); |
| 84 | let EncoderMethod = "getMemEncodingMMImm12"; |
| 85 | let ParserMatchClass = MipsMemAsmOperand; |
| 86 | let OperandType = "OPERAND_MEMORY"; |
| 87 | } |
| 88 | |
Zoran Jovanovic | 507e084 | 2013-10-29 16:38:59 +0000 | [diff] [blame] | 89 | def jmptarget_mm : Operand<OtherVT> { |
| 90 | let EncoderMethod = "getJumpTargetOpValueMM"; |
| 91 | } |
| 92 | |
| 93 | def calltarget_mm : Operand<iPTR> { |
| 94 | let EncoderMethod = "getJumpTargetOpValueMM"; |
| 95 | } |
| 96 | |
Zoran Jovanovic | 8a80aa7 | 2013-11-04 14:53:22 +0000 | [diff] [blame] | 97 | def brtarget_mm : Operand<OtherVT> { |
| 98 | let EncoderMethod = "getBranchTargetOpValueMM"; |
| 99 | let OperandType = "OPERAND_PCREL"; |
| 100 | let DecoderMethod = "DecodeBranchTargetMM"; |
| 101 | } |
| 102 | |
Zoran Jovanovic | 73ff948 | 2014-08-14 12:09:10 +0000 | [diff] [blame] | 103 | class CompactBranchMM<string opstr, DAGOperand opnd, PatFrag cond_op, |
| 104 | RegisterOperand RO> : |
| 105 | InstSE<(outs), (ins RO:$rs, opnd:$offset), |
| 106 | !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI> { |
| 107 | let isBranch = 1; |
| 108 | let isTerminator = 1; |
| 109 | let hasDelaySlot = 0; |
| 110 | let Defs = [AT]; |
| 111 | } |
| 112 | |
Jack Carter | 9770097 | 2013-08-13 20:19:16 +0000 | [diff] [blame] | 113 | let canFoldAsLoad = 1 in |
| 114 | class LoadLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO, |
| 115 | Operand MemOpnd> : |
| 116 | InstSE<(outs RO:$rt), (ins MemOpnd:$addr, RO:$src), |
| 117 | !strconcat(opstr, "\t$rt, $addr"), |
| 118 | [(set RO:$rt, (OpNode addrimm12:$addr, RO:$src))], |
| 119 | NoItinerary, FrmI> { |
Vladimir Medic | dde3d58 | 2013-09-06 12:30:36 +0000 | [diff] [blame] | 120 | let DecoderMethod = "DecodeMemMMImm12"; |
Jack Carter | 9770097 | 2013-08-13 20:19:16 +0000 | [diff] [blame] | 121 | string Constraints = "$src = $rt"; |
| 122 | } |
| 123 | |
| 124 | class StoreLeftRightMM<string opstr, SDNode OpNode, RegisterOperand RO, |
| 125 | Operand MemOpnd>: |
| 126 | InstSE<(outs), (ins RO:$rt, MemOpnd:$addr), |
| 127 | !strconcat(opstr, "\t$rt, $addr"), |
Vladimir Medic | dde3d58 | 2013-09-06 12:30:36 +0000 | [diff] [blame] | 128 | [(OpNode RO:$rt, addrimm12:$addr)], NoItinerary, FrmI> { |
| 129 | let DecoderMethod = "DecodeMemMMImm12"; |
| 130 | } |
Jack Carter | 9770097 | 2013-08-13 20:19:16 +0000 | [diff] [blame] | 131 | |
Zoran Jovanovic | ff9d5f3 | 2013-12-19 16:12:56 +0000 | [diff] [blame] | 132 | class LLBaseMM<string opstr, RegisterOperand RO> : |
| 133 | InstSE<(outs RO:$rt), (ins mem_mm_12:$addr), |
| 134 | !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { |
Zoran Jovanovic | 7d63392 | 2014-01-15 13:17:33 +0000 | [diff] [blame] | 135 | let DecoderMethod = "DecodeMemMMImm12"; |
Zoran Jovanovic | ff9d5f3 | 2013-12-19 16:12:56 +0000 | [diff] [blame] | 136 | let mayLoad = 1; |
| 137 | } |
| 138 | |
| 139 | class SCBaseMM<string opstr, RegisterOperand RO> : |
Zoran Jovanovic | 285cc28 | 2014-02-28 18:22:56 +0000 | [diff] [blame] | 140 | InstSE<(outs RO:$dst), (ins RO:$rt, mem_mm_12:$addr), |
Zoran Jovanovic | ff9d5f3 | 2013-12-19 16:12:56 +0000 | [diff] [blame] | 141 | !strconcat(opstr, "\t$rt, $addr"), [], NoItinerary, FrmI> { |
Zoran Jovanovic | 7d63392 | 2014-01-15 13:17:33 +0000 | [diff] [blame] | 142 | let DecoderMethod = "DecodeMemMMImm12"; |
Zoran Jovanovic | ff9d5f3 | 2013-12-19 16:12:56 +0000 | [diff] [blame] | 143 | let mayStore = 1; |
Zoran Jovanovic | 285cc28 | 2014-02-28 18:22:56 +0000 | [diff] [blame] | 144 | let Constraints = "$rt = $dst"; |
Zoran Jovanovic | ff9d5f3 | 2013-12-19 16:12:56 +0000 | [diff] [blame] | 145 | } |
| 146 | |
Zoran Jovanovic | d4cb61c | 2014-01-15 13:01:18 +0000 | [diff] [blame] | 147 | class LoadMM<string opstr, DAGOperand RO, SDPatternOperator OpNode = null_frag, |
| 148 | InstrItinClass Itin = NoItinerary> : |
| 149 | InstSE<(outs RO:$rt), (ins mem_mm_12:$addr), |
| 150 | !strconcat(opstr, "\t$rt, $addr"), |
| 151 | [(set RO:$rt, (OpNode addrimm12:$addr))], Itin, FrmI> { |
| 152 | let DecoderMethod = "DecodeMemMMImm12"; |
| 153 | let canFoldAsLoad = 1; |
| 154 | let mayLoad = 1; |
| 155 | } |
| 156 | |
Zoran Jovanovic | 592239d | 2014-10-21 08:44:58 +0000 | [diff] [blame] | 157 | class ArithRMM16<string opstr, RegisterOperand RO, bit isComm = 0, |
| 158 | InstrItinClass Itin = NoItinerary, |
| 159 | SDPatternOperator OpNode = null_frag> : |
| 160 | MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, RO:$rt), |
| 161 | !strconcat(opstr, "\t$rd, $rs, $rt"), |
| 162 | [(set RO:$rd, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { |
| 163 | let isCommutable = isComm; |
| 164 | } |
| 165 | |
Zoran Jovanovic | 8853171 | 2014-11-05 17:31:00 +0000 | [diff] [blame] | 166 | class AndImmMM16<string opstr, RegisterOperand RO, |
| 167 | InstrItinClass Itin = NoItinerary> : |
| 168 | MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, uimm4_andi:$imm), |
| 169 | !strconcat(opstr, "\t$rd, $rs, $imm"), [], Itin, FrmI>; |
| 170 | |
Zoran Jovanovic | 81ceebc | 2014-10-21 08:32:40 +0000 | [diff] [blame] | 171 | class LogicRMM16<string opstr, RegisterOperand RO, |
| 172 | InstrItinClass Itin = NoItinerary, |
| 173 | SDPatternOperator OpNode = null_frag> : |
| 174 | MicroMipsInst16<(outs RO:$dst), (ins RO:$rs, RO:$rt), |
| 175 | !strconcat(opstr, "\t$rt, $rs"), |
| 176 | [(set RO:$dst, (OpNode RO:$rs, RO:$rt))], Itin, FrmR> { |
| 177 | let isCommutable = 1; |
| 178 | let Constraints = "$rt = $dst"; |
| 179 | } |
| 180 | |
| 181 | class NotMM16<string opstr, RegisterOperand RO> : |
| 182 | MicroMipsInst16<(outs RO:$rt), (ins RO:$rs), |
| 183 | !strconcat(opstr, "\t$rt, $rs"), |
| 184 | [(set RO:$rt, (not RO:$rs))], NoItinerary, FrmR>; |
| 185 | |
Zoran Jovanovic | 9f99723 | 2014-11-05 17:38:31 +0000 | [diff] [blame] | 186 | class ShiftIMM16<string opstr, Operand ImmOpnd, RegisterOperand RO, |
Zoran Jovanovic | 4a00fdc | 2014-10-23 10:42:01 +0000 | [diff] [blame] | 187 | InstrItinClass Itin = NoItinerary> : |
| 188 | MicroMipsInst16<(outs RO:$rd), (ins RO:$rt, ImmOpnd:$shamt), |
Zoran Jovanovic | 9f99723 | 2014-11-05 17:38:31 +0000 | [diff] [blame] | 189 | !strconcat(opstr, "\t$rd, $rt, $shamt"), [], Itin, FrmR>; |
Zoran Jovanovic | 4a00fdc | 2014-10-23 10:42:01 +0000 | [diff] [blame] | 190 | |
Jozef Kolek | e8c9d1e | 2014-11-24 14:39:13 +0000 | [diff] [blame] | 191 | class LoadMM16<string opstr, DAGOperand RO, SDPatternOperator OpNode, |
| 192 | InstrItinClass Itin, Operand MemOpnd> : |
| 193 | MicroMipsInst16<(outs RO:$rt), (ins MemOpnd:$addr), |
| 194 | !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> { |
Jozef Kolek | 315e7ec | 2014-11-26 18:56:38 +0000 | [diff] [blame] | 195 | let DecoderMethod = "DecodeMemMMImm4"; |
Jozef Kolek | e8c9d1e | 2014-11-24 14:39:13 +0000 | [diff] [blame] | 196 | let canFoldAsLoad = 1; |
| 197 | let mayLoad = 1; |
| 198 | } |
| 199 | |
| 200 | class StoreMM16<string opstr, DAGOperand RTOpnd, DAGOperand RO, |
| 201 | SDPatternOperator OpNode, InstrItinClass Itin, |
| 202 | Operand MemOpnd> : |
| 203 | MicroMipsInst16<(outs), (ins RTOpnd:$rt, MemOpnd:$addr), |
| 204 | !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI> { |
Jozef Kolek | 315e7ec | 2014-11-26 18:56:38 +0000 | [diff] [blame] | 205 | let DecoderMethod = "DecodeMemMMImm4"; |
Jozef Kolek | e8c9d1e | 2014-11-24 14:39:13 +0000 | [diff] [blame] | 206 | let mayStore = 1; |
| 207 | } |
| 208 | |
Zoran Jovanovic | bac3619 | 2014-10-23 11:06:34 +0000 | [diff] [blame] | 209 | class AddImmUR2<string opstr, RegisterOperand RO> : |
| 210 | MicroMipsInst16<(outs RO:$rd), (ins RO:$rs, simm3_lsa2:$imm), |
| 211 | !strconcat(opstr, "\t$rd, $rs, $imm"), |
| 212 | [], NoItinerary, FrmR> { |
| 213 | let isCommutable = 1; |
| 214 | } |
| 215 | |
Zoran Jovanovic | b26f889 | 2014-10-10 13:45:34 +0000 | [diff] [blame] | 216 | class AddImmUS5<string opstr, RegisterOperand RO> : |
| 217 | MicroMipsInst16<(outs RO:$dst), (ins RO:$rd, simm4:$imm), |
| 218 | !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR> { |
| 219 | let Constraints = "$rd = $dst"; |
Zoran Jovanovic | b26f889 | 2014-10-10 13:45:34 +0000 | [diff] [blame] | 220 | } |
| 221 | |
Zoran Jovanovic | 42b8444 | 2014-10-23 11:13:59 +0000 | [diff] [blame] | 222 | class AddImmUR1SP<string opstr, RegisterOperand RO> : |
| 223 | MicroMipsInst16<(outs RO:$rd), (ins uimm6_lsl2:$imm), |
| 224 | !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmR>; |
| 225 | |
Zoran Jovanovic | 98bd58c | 2014-10-10 14:37:30 +0000 | [diff] [blame] | 226 | class AddImmUSP<string opstr> : |
| 227 | MicroMipsInst16<(outs), (ins simm9_addiusp:$imm), |
| 228 | !strconcat(opstr, "\t$imm"), [], NoItinerary, FrmI>; |
| 229 | |
Zoran Jovanovic | cabf0f4 | 2014-04-03 12:47:34 +0000 | [diff] [blame] | 230 | class MoveFromHILOMM<string opstr, RegisterOperand RO, Register UseReg> : |
| 231 | MicroMipsInst16<(outs RO:$rd), (ins), !strconcat(opstr, "\t$rd"), |
| 232 | [], II_MFHI_MFLO, FrmR> { |
| 233 | let Uses = [UseReg]; |
| 234 | let hasSideEffects = 0; |
| 235 | } |
| 236 | |
Zoran Jovanovic | 87d13e5 | 2014-03-20 10:18:24 +0000 | [diff] [blame] | 237 | class MoveMM16<string opstr, RegisterOperand RO, bit isComm = 0, |
| 238 | InstrItinClass Itin = NoItinerary> : |
| 239 | MicroMipsInst16<(outs RO:$rd), (ins RO:$rs), |
| 240 | !strconcat(opstr, "\t$rd, $rs"), [], Itin, FrmR> { |
| 241 | let isCommutable = isComm; |
| 242 | let isReMaterializable = 1; |
| 243 | } |
| 244 | |
Zoran Jovanovic | 9bda2f1 | 2014-10-23 10:59:24 +0000 | [diff] [blame] | 245 | class LoadImmMM16<string opstr, Operand Od, RegisterOperand RO, |
| 246 | SDPatternOperator imm_type = null_frag> : |
| 247 | MicroMipsInst16<(outs RO:$rd), (ins Od:$imm), |
| 248 | !strconcat(opstr, "\t$rd, $imm"), [], NoItinerary, FrmI> { |
| 249 | let isReMaterializable = 1; |
| 250 | } |
| 251 | |
Zoran Jovanovic | 87d13e5 | 2014-03-20 10:18:24 +0000 | [diff] [blame] | 252 | // 16-bit Jump and Link (Call) |
| 253 | class JumpLinkRegMM16<string opstr, RegisterOperand RO> : |
| 254 | MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), |
Zoran Jovanovic | 9b05a31 | 2014-03-31 14:00:10 +0000 | [diff] [blame] | 255 | [(MipsJmpLink RO:$rs)], IIBranch, FrmR> { |
Zoran Jovanovic | 87d13e5 | 2014-03-20 10:18:24 +0000 | [diff] [blame] | 256 | let isCall = 1; |
| 257 | let hasDelaySlot = 1; |
| 258 | let Defs = [RA]; |
| 259 | } |
| 260 | |
Zoran Jovanovic | 95e14e7 | 2014-10-10 14:02:44 +0000 | [diff] [blame] | 261 | // 16-bit Jump Reg |
| 262 | class JumpRegMM16<string opstr, RegisterOperand RO> : |
| 263 | MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), |
| 264 | [], IIBranch, FrmR> { |
| 265 | let hasDelaySlot = 1; |
| 266 | let isBranch = 1; |
| 267 | let isIndirectBranch = 1; |
| 268 | } |
| 269 | |
Zoran Jovanovic | c74e3eb9 | 2014-09-12 14:29:54 +0000 | [diff] [blame] | 270 | // Base class for JRADDIUSP instruction. |
| 271 | class JumpRAddiuStackMM16 : |
| 272 | MicroMipsInst16<(outs), (ins uimm5_lsl2:$imm), "jraddiusp\t$imm", |
| 273 | [], IIBranch, FrmR> { |
| 274 | let isTerminator = 1; |
| 275 | let isBarrier = 1; |
Zoran Jovanovic | c74e3eb9 | 2014-09-12 14:29:54 +0000 | [diff] [blame] | 276 | let isBranch = 1; |
| 277 | let isIndirectBranch = 1; |
| 278 | } |
| 279 | |
Zoran Jovanovic | 6097bad | 2014-10-10 13:22:28 +0000 | [diff] [blame] | 280 | // 16-bit Jump and Link (Call) - Short Delay Slot |
| 281 | class JumpLinkRegSMM16<string opstr, RegisterOperand RO> : |
| 282 | MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), |
| 283 | [], IIBranch, FrmR> { |
| 284 | let isCall = 1; |
| 285 | let hasDelaySlot = 1; |
| 286 | let Defs = [RA]; |
| 287 | } |
| 288 | |
Zoran Jovanovic | b39a174f | 2014-10-10 13:31:18 +0000 | [diff] [blame] | 289 | // 16-bit Jump Register Compact - No delay slot |
| 290 | class JumpRegCMM16<string opstr, RegisterOperand RO> : |
| 291 | MicroMipsInst16<(outs), (ins RO:$rs), !strconcat(opstr, "\t$rs"), |
| 292 | [], IIBranch, FrmR> { |
| 293 | let isTerminator = 1; |
| 294 | let isBarrier = 1; |
| 295 | let isBranch = 1; |
| 296 | let isIndirectBranch = 1; |
| 297 | } |
| 298 | |
Zoran Jovanovic | ac9ef12 | 2014-09-12 13:43:41 +0000 | [diff] [blame] | 299 | // MicroMIPS Jump and Link (Call) - Short Delay Slot |
| 300 | let isCall = 1, hasDelaySlot = 1, Defs = [RA] in { |
| 301 | class JumpLinkMM<string opstr, DAGOperand opnd> : |
| 302 | InstSE<(outs), (ins opnd:$target), !strconcat(opstr, "\t$target"), |
| 303 | [], IIBranch, FrmJ, opstr> { |
| 304 | let DecoderMethod = "DecodeJumpTargetMM"; |
| 305 | } |
| 306 | |
| 307 | class JumpLinkRegMM<string opstr, RegisterOperand RO>: |
| 308 | InstSE<(outs RO:$rd), (ins RO:$rs), !strconcat(opstr, "\t$rd, $rs"), |
| 309 | [], IIBranch, FrmR>; |
Zoran Jovanovic | ed6dd6b | 2014-09-12 13:51:58 +0000 | [diff] [blame] | 310 | |
| 311 | class BranchCompareToZeroLinkMM<string opstr, DAGOperand opnd, |
| 312 | RegisterOperand RO> : |
| 313 | InstSE<(outs), (ins RO:$rs, opnd:$offset), |
| 314 | !strconcat(opstr, "\t$rs, $offset"), [], IIBranch, FrmI, opstr>; |
Zoran Jovanovic | ac9ef12 | 2014-09-12 13:43:41 +0000 | [diff] [blame] | 315 | } |
| 316 | |
Jozef Kolek | 5f95dd2 | 2014-11-19 11:39:12 +0000 | [diff] [blame] | 317 | class LoadWordIndexedScaledMM<string opstr, RegisterOperand RO, |
| 318 | InstrItinClass Itin = NoItinerary, |
| 319 | SDPatternOperator OpNode = null_frag> : |
| 320 | InstSE<(outs RO:$rd), (ins PtrRC:$base, PtrRC:$index), |
| 321 | !strconcat(opstr, "\t$rd, ${index}(${base})"), [], Itin, FrmFI>; |
| 322 | |
Zoran Jovanovic | a4c4b5f | 2014-11-19 16:44:02 +0000 | [diff] [blame] | 323 | /// A list of registers used by load/store multiple instructions. |
| 324 | def RegListAsmOperand : AsmOperandClass { |
| 325 | let Name = "RegList"; |
| 326 | let ParserMethod = "parseRegisterList"; |
| 327 | } |
| 328 | |
| 329 | def reglist : Operand<i32> { |
| 330 | let EncoderMethod = "getRegisterListOpValue"; |
| 331 | let ParserMatchClass = RegListAsmOperand; |
| 332 | let PrintMethod = "printRegisterList"; |
| 333 | let DecoderMethod = "DecodeRegListOperand"; |
| 334 | } |
| 335 | |
| 336 | class StoreMultMM<string opstr, |
| 337 | InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : |
| 338 | InstSE<(outs), (ins reglist:$rt, mem_mm_12:$addr), |
| 339 | !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> { |
| 340 | let DecoderMethod = "DecodeMemMMImm12"; |
| 341 | let mayStore = 1; |
| 342 | } |
| 343 | |
| 344 | class LoadMultMM<string opstr, |
| 345 | InstrItinClass Itin = NoItinerary, ComplexPattern Addr = addr> : |
| 346 | InstSE<(outs reglist:$rt), (ins mem_mm_12:$addr), |
| 347 | !strconcat(opstr, "\t$rt, $addr"), [], Itin, FrmI, opstr> { |
| 348 | let DecoderMethod = "DecodeMemMMImm12"; |
| 349 | let mayLoad = 1; |
| 350 | } |
| 351 | |
Zoran Jovanovic | 592239d | 2014-10-21 08:44:58 +0000 | [diff] [blame] | 352 | def ADDU16_MM : ArithRMM16<"addu16", GPRMM16Opnd, 1, II_ADDU, add>, |
| 353 | ARITH_FM_MM16<0>; |
| 354 | def SUBU16_MM : ArithRMM16<"subu16", GPRMM16Opnd, 0, II_SUBU, sub>, |
| 355 | ARITH_FM_MM16<1>; |
Zoran Jovanovic | 8853171 | 2014-11-05 17:31:00 +0000 | [diff] [blame] | 356 | def ANDI16_MM : AndImmMM16<"andi16", GPRMM16Opnd, II_AND>, ANDI_FM_MM16<0x0b>; |
Zoran Jovanovic | 81ceebc | 2014-10-21 08:32:40 +0000 | [diff] [blame] | 357 | def AND16_MM : LogicRMM16<"and16", GPRMM16Opnd, II_AND, and>, |
| 358 | LOGIC_FM_MM16<0x2>; |
| 359 | def OR16_MM : LogicRMM16<"or16", GPRMM16Opnd, II_OR, or>, |
| 360 | LOGIC_FM_MM16<0x3>; |
| 361 | def XOR16_MM : LogicRMM16<"xor16", GPRMM16Opnd, II_XOR, xor>, |
| 362 | LOGIC_FM_MM16<0x1>; |
| 363 | def NOT16_MM : NotMM16<"not16", GPRMM16Opnd>, LOGIC_FM_MM16<0x0>; |
Zoran Jovanovic | 9f99723 | 2014-11-05 17:38:31 +0000 | [diff] [blame] | 364 | def SLL16_MM : ShiftIMM16<"sll16", uimm3_shift, GPRMM16Opnd, II_SLL>, |
| 365 | SHIFT_FM_MM16<0>; |
| 366 | def SRL16_MM : ShiftIMM16<"srl16", uimm3_shift, GPRMM16Opnd, II_SRL>, |
| 367 | SHIFT_FM_MM16<1>; |
Jozef Kolek | e8c9d1e | 2014-11-24 14:39:13 +0000 | [diff] [blame] | 368 | def LBU16_MM : LoadMM16<"lbu16", GPRMM16Opnd, zextloadi8, II_LBU, |
| 369 | mem_mm_4>, LOAD_STORE_FM_MM16<0x02>; |
| 370 | def LHU16_MM : LoadMM16<"lhu16", GPRMM16Opnd, zextloadi16, II_LHU, |
| 371 | mem_mm_4_lsl1>, LOAD_STORE_FM_MM16<0x0a>; |
| 372 | def LW16_MM : LoadMM16<"lw16", GPRMM16Opnd, load, II_LW, mem_mm_4_lsl2>, |
| 373 | LOAD_STORE_FM_MM16<0x1a>; |
| 374 | def SB16_MM : StoreMM16<"sb16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei8, |
| 375 | II_SB, mem_mm_4>, LOAD_STORE_FM_MM16<0x22>; |
| 376 | def SH16_MM : StoreMM16<"sh16", GPRMM16OpndZero, GPRMM16Opnd, truncstorei16, |
| 377 | II_SH, mem_mm_4_lsl1>, |
| 378 | LOAD_STORE_FM_MM16<0x2a>; |
| 379 | def SW16_MM : StoreMM16<"sw16", GPRMM16OpndZero, GPRMM16Opnd, store, II_SW, |
| 380 | mem_mm_4_lsl2>, LOAD_STORE_FM_MM16<0x3a>; |
Zoran Jovanovic | 42b8444 | 2014-10-23 11:13:59 +0000 | [diff] [blame] | 381 | def ADDIUR1SP_MM : AddImmUR1SP<"addiur1sp", GPRMM16Opnd>, ADDIUR1SP_FM_MM16; |
Zoran Jovanovic | bac3619 | 2014-10-23 11:06:34 +0000 | [diff] [blame] | 382 | def ADDIUR2_MM : AddImmUR2<"addiur2", GPRMM16Opnd>, ADDIUR2_FM_MM16; |
Zoran Jovanovic | b26f889 | 2014-10-10 13:45:34 +0000 | [diff] [blame] | 383 | def ADDIUS5_MM : AddImmUS5<"addius5", GPR32Opnd>, ADDIUS5_FM_MM16; |
Zoran Jovanovic | 98bd58c | 2014-10-10 14:37:30 +0000 | [diff] [blame] | 384 | def ADDIUSP_MM : AddImmUSP<"addiusp">, ADDIUSP_FM_MM16; |
Zoran Jovanovic | cabf0f4 | 2014-04-03 12:47:34 +0000 | [diff] [blame] | 385 | def MFHI16_MM : MoveFromHILOMM<"mfhi", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x10>; |
| 386 | def MFLO16_MM : MoveFromHILOMM<"mflo", GPR32Opnd, AC0>, MFHILO_FM_MM16<0x12>; |
Zoran Jovanovic | 87d13e5 | 2014-03-20 10:18:24 +0000 | [diff] [blame] | 387 | def MOVE16_MM : MoveMM16<"move", GPR32Opnd>, MOVE_FM_MM16<0x03>; |
Jozef Kolek | aa2b927 | 2014-11-27 14:41:44 +0000 | [diff] [blame^] | 388 | def LI16_MM : LoadImmMM16<"li16", li_simm7, GPRMM16Opnd, immLi16>, |
Zoran Jovanovic | 9bda2f1 | 2014-10-23 10:59:24 +0000 | [diff] [blame] | 389 | LI_FM_MM16, IsAsCheapAsAMove; |
Zoran Jovanovic | 87d13e5 | 2014-03-20 10:18:24 +0000 | [diff] [blame] | 390 | def JALR16_MM : JumpLinkRegMM16<"jalr", GPR32Opnd>, JALR_FM_MM16<0x0e>; |
Zoran Jovanovic | 6097bad | 2014-10-10 13:22:28 +0000 | [diff] [blame] | 391 | def JALRS16_MM : JumpLinkRegSMM16<"jalrs16", GPR32Opnd>, JALR_FM_MM16<0x0f>; |
Zoran Jovanovic | b39a174f | 2014-10-10 13:31:18 +0000 | [diff] [blame] | 392 | def JRC16_MM : JumpRegCMM16<"jrc", GPR32Opnd>, JALR_FM_MM16<0x0d>; |
Zoran Jovanovic | c74e3eb9 | 2014-09-12 14:29:54 +0000 | [diff] [blame] | 393 | def JRADDIUSP : JumpRAddiuStackMM16, JRADDIUSP_FM_MM16<0x18>; |
Zoran Jovanovic | 95e14e7 | 2014-10-10 14:02:44 +0000 | [diff] [blame] | 394 | def JR16_MM : JumpRegMM16<"jr16", GPR32Opnd>, JALR_FM_MM16<0x0c>; |
Zoran Jovanovic | 87d13e5 | 2014-03-20 10:18:24 +0000 | [diff] [blame] | 395 | |
Zoran Jovanovic | a0f5328 | 2014-03-20 10:41:37 +0000 | [diff] [blame] | 396 | class WaitMM<string opstr> : |
| 397 | InstSE<(outs), (ins uimm10:$code_), !strconcat(opstr, "\t$code_"), [], |
| 398 | NoItinerary, FrmOther, opstr>; |
| 399 | |
Akira Hatanaka | a43b56d | 2013-08-20 20:46:51 +0000 | [diff] [blame] | 400 | let DecoderNamespace = "MicroMips", Predicates = [InMicroMips] in { |
Zoran Jovanovic | 73ff948 | 2014-08-14 12:09:10 +0000 | [diff] [blame] | 401 | /// Compact Branch Instructions |
| 402 | def BEQZC_MM : CompactBranchMM<"beqzc", brtarget_mm, seteq, GPR32Opnd>, |
| 403 | COMPACT_BRANCH_FM_MM<0x7>; |
| 404 | def BNEZC_MM : CompactBranchMM<"bnezc", brtarget_mm, setne, GPR32Opnd>, |
| 405 | COMPACT_BRANCH_FM_MM<0x5>; |
| 406 | |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 407 | /// Arithmetic Instructions (ALU Immediate) |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 408 | def ADDiu_MM : MMRel, ArithLogicI<"addiu", simm16, GPR32Opnd>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 409 | ADDI_FM_MM<0xc>; |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 410 | def ADDi_MM : MMRel, ArithLogicI<"addi", simm16, GPR32Opnd>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 411 | ADDI_FM_MM<0x4>; |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 412 | def SLTi_MM : MMRel, SetCC_I<"slti", setlt, simm16, immSExt16, GPR32Opnd>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 413 | SLTI_FM_MM<0x24>; |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 414 | def SLTiu_MM : MMRel, SetCC_I<"sltiu", setult, simm16, immSExt16, GPR32Opnd>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 415 | SLTI_FM_MM<0x2c>; |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 416 | def ANDi_MM : MMRel, ArithLogicI<"andi", uimm16, GPR32Opnd>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 417 | ADDI_FM_MM<0x34>; |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 418 | def ORi_MM : MMRel, ArithLogicI<"ori", uimm16, GPR32Opnd>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 419 | ADDI_FM_MM<0x14>; |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 420 | def XORi_MM : MMRel, ArithLogicI<"xori", uimm16, GPR32Opnd>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 421 | ADDI_FM_MM<0x1c>; |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 422 | def LUi_MM : MMRel, LoadUpper<"lui", GPR32Opnd, uimm16>, LUI_FM_MM; |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 423 | |
Zoran Jovanovic | bd28c37 | 2013-12-25 10:14:07 +0000 | [diff] [blame] | 424 | def LEA_ADDiu_MM : MMRel, EffectiveAddress<"addiu", GPR32Opnd>, |
| 425 | LW_FM_MM<0xc>; |
| 426 | |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 427 | /// Arithmetic Instructions (3-Operand, R-Type) |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 428 | def ADDu_MM : MMRel, ArithLogicR<"addu", GPR32Opnd>, ADD_FM_MM<0, 0x150>; |
| 429 | def SUBu_MM : MMRel, ArithLogicR<"subu", GPR32Opnd>, ADD_FM_MM<0, 0x1d0>; |
| 430 | def MUL_MM : MMRel, ArithLogicR<"mul", GPR32Opnd>, ADD_FM_MM<0, 0x210>; |
| 431 | def ADD_MM : MMRel, ArithLogicR<"add", GPR32Opnd>, ADD_FM_MM<0, 0x110>; |
| 432 | def SUB_MM : MMRel, ArithLogicR<"sub", GPR32Opnd>, ADD_FM_MM<0, 0x190>; |
| 433 | def SLT_MM : MMRel, SetCC_R<"slt", setlt, GPR32Opnd>, ADD_FM_MM<0, 0x350>; |
| 434 | def SLTu_MM : MMRel, SetCC_R<"sltu", setult, GPR32Opnd>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 435 | ADD_FM_MM<0, 0x390>; |
Daniel Sanders | 4aefdc7 | 2014-01-16 17:13:57 +0000 | [diff] [blame] | 436 | def AND_MM : MMRel, ArithLogicR<"and", GPR32Opnd, 1, II_AND, and>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 437 | ADD_FM_MM<0, 0x250>; |
Daniel Sanders | 4aefdc7 | 2014-01-16 17:13:57 +0000 | [diff] [blame] | 438 | def OR_MM : MMRel, ArithLogicR<"or", GPR32Opnd, 1, II_OR, or>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 439 | ADD_FM_MM<0, 0x290>; |
Daniel Sanders | 4aefdc7 | 2014-01-16 17:13:57 +0000 | [diff] [blame] | 440 | def XOR_MM : MMRel, ArithLogicR<"xor", GPR32Opnd, 1, II_XOR, xor>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 441 | ADD_FM_MM<0, 0x310>; |
Akira Hatanaka | 13e6ccf | 2013-08-06 23:08:38 +0000 | [diff] [blame] | 442 | def NOR_MM : MMRel, LogicNOR<"nor", GPR32Opnd>, ADD_FM_MM<0, 0x2d0>; |
Daniel Sanders | e95a137 | 2014-01-17 14:32:41 +0000 | [diff] [blame] | 443 | def MULT_MM : MMRel, Mult<"mult", II_MULT, GPR32Opnd, [HI0, LO0]>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 444 | MULT_FM_MM<0x22c>; |
Daniel Sanders | e95a137 | 2014-01-17 14:32:41 +0000 | [diff] [blame] | 445 | def MULTu_MM : MMRel, Mult<"multu", II_MULTU, GPR32Opnd, [HI0, LO0]>, |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 446 | MULT_FM_MM<0x26c>; |
Daniel Sanders | c7a9f8d | 2014-01-17 14:48:06 +0000 | [diff] [blame] | 447 | def SDIV_MM : MMRel, Div<"div", II_DIV, GPR32Opnd, [HI0, LO0]>, |
Zoran Jovanovic | 3671a54 | 2013-09-14 07:15:21 +0000 | [diff] [blame] | 448 | MULT_FM_MM<0x2ac>; |
Daniel Sanders | c7a9f8d | 2014-01-17 14:48:06 +0000 | [diff] [blame] | 449 | def UDIV_MM : MMRel, Div<"divu", II_DIVU, GPR32Opnd, [HI0, LO0]>, |
Zoran Jovanovic | 3671a54 | 2013-09-14 07:15:21 +0000 | [diff] [blame] | 450 | MULT_FM_MM<0x2ec>; |
Akira Hatanaka | cd9b74a | 2013-04-25 01:11:15 +0000 | [diff] [blame] | 451 | |
| 452 | /// Shift Instructions |
Daniel Sanders | 980589a | 2014-01-16 14:27:20 +0000 | [diff] [blame] | 453 | def SLL_MM : MMRel, shift_rotate_imm<"sll", uimm5, GPR32Opnd, II_SLL>, |
Akira Hatanaka | cd9b74a | 2013-04-25 01:11:15 +0000 | [diff] [blame] | 454 | SRA_FM_MM<0, 0>; |
Daniel Sanders | 980589a | 2014-01-16 14:27:20 +0000 | [diff] [blame] | 455 | def SRL_MM : MMRel, shift_rotate_imm<"srl", uimm5, GPR32Opnd, II_SRL>, |
Akira Hatanaka | cd9b74a | 2013-04-25 01:11:15 +0000 | [diff] [blame] | 456 | SRA_FM_MM<0x40, 0>; |
Daniel Sanders | 980589a | 2014-01-16 14:27:20 +0000 | [diff] [blame] | 457 | def SRA_MM : MMRel, shift_rotate_imm<"sra", uimm5, GPR32Opnd, II_SRA>, |
Akira Hatanaka | cd9b74a | 2013-04-25 01:11:15 +0000 | [diff] [blame] | 458 | SRA_FM_MM<0x80, 0>; |
Daniel Sanders | 980589a | 2014-01-16 14:27:20 +0000 | [diff] [blame] | 459 | def SLLV_MM : MMRel, shift_rotate_reg<"sllv", GPR32Opnd, II_SLLV>, |
Akira Hatanaka | cd9b74a | 2013-04-25 01:11:15 +0000 | [diff] [blame] | 460 | SRLV_FM_MM<0x10, 0>; |
Daniel Sanders | 980589a | 2014-01-16 14:27:20 +0000 | [diff] [blame] | 461 | def SRLV_MM : MMRel, shift_rotate_reg<"srlv", GPR32Opnd, II_SRLV>, |
Akira Hatanaka | cd9b74a | 2013-04-25 01:11:15 +0000 | [diff] [blame] | 462 | SRLV_FM_MM<0x50, 0>; |
Daniel Sanders | 980589a | 2014-01-16 14:27:20 +0000 | [diff] [blame] | 463 | def SRAV_MM : MMRel, shift_rotate_reg<"srav", GPR32Opnd, II_SRAV>, |
Akira Hatanaka | cd9b74a | 2013-04-25 01:11:15 +0000 | [diff] [blame] | 464 | SRLV_FM_MM<0x90, 0>; |
Daniel Sanders | 980589a | 2014-01-16 14:27:20 +0000 | [diff] [blame] | 465 | def ROTR_MM : MMRel, shift_rotate_imm<"rotr", uimm5, GPR32Opnd, II_ROTR>, |
Akira Hatanaka | cd9b74a | 2013-04-25 01:11:15 +0000 | [diff] [blame] | 466 | SRA_FM_MM<0xc0, 0>; |
Daniel Sanders | 980589a | 2014-01-16 14:27:20 +0000 | [diff] [blame] | 467 | def ROTRV_MM : MMRel, shift_rotate_reg<"rotrv", GPR32Opnd, II_ROTRV>, |
Akira Hatanaka | cd9b74a | 2013-04-25 01:11:15 +0000 | [diff] [blame] | 468 | SRLV_FM_MM<0xd0, 0>; |
Akira Hatanaka | f0aa6c9 | 2013-04-25 01:21:25 +0000 | [diff] [blame] | 469 | |
| 470 | /// Load and Store Instructions - aligned |
Vladimir Medic | dde3d58 | 2013-09-06 12:30:36 +0000 | [diff] [blame] | 471 | let DecoderMethod = "DecodeMemMMImm16" in { |
| 472 | def LB_MM : Load<"lb", GPR32Opnd>, MMRel, LW_FM_MM<0x7>; |
| 473 | def LBu_MM : Load<"lbu", GPR32Opnd>, MMRel, LW_FM_MM<0x5>; |
| 474 | def LH_MM : Load<"lh", GPR32Opnd>, MMRel, LW_FM_MM<0xf>; |
| 475 | def LHu_MM : Load<"lhu", GPR32Opnd>, MMRel, LW_FM_MM<0xd>; |
| 476 | def LW_MM : Load<"lw", GPR32Opnd>, MMRel, LW_FM_MM<0x3f>; |
| 477 | def SB_MM : Store<"sb", GPR32Opnd>, MMRel, LW_FM_MM<0x6>; |
| 478 | def SH_MM : Store<"sh", GPR32Opnd>, MMRel, LW_FM_MM<0xe>; |
| 479 | def SW_MM : Store<"sw", GPR32Opnd>, MMRel, LW_FM_MM<0x3e>; |
| 480 | } |
Jack Carter | 9770097 | 2013-08-13 20:19:16 +0000 | [diff] [blame] | 481 | |
Jozef Kolek | 5f95dd2 | 2014-11-19 11:39:12 +0000 | [diff] [blame] | 482 | def LWXS_MM : LoadWordIndexedScaledMM<"lwxs", GPR32Opnd>, LWXS_FM_MM<0x118>; |
| 483 | |
Daniel Sanders | 0b385ac | 2014-01-21 15:21:14 +0000 | [diff] [blame] | 484 | def LWU_MM : LoadMM<"lwu", GPR32Opnd, zextloadi32, II_LWU>, LL_FM_MM<0xe>; |
Zoran Jovanovic | d4cb61c | 2014-01-15 13:01:18 +0000 | [diff] [blame] | 485 | |
Jack Carter | 9770097 | 2013-08-13 20:19:16 +0000 | [diff] [blame] | 486 | /// Load and Store Instructions - unaligned |
Akira Hatanaka | a43b56d | 2013-08-20 20:46:51 +0000 | [diff] [blame] | 487 | def LWL_MM : LoadLeftRightMM<"lwl", MipsLWL, GPR32Opnd, mem_mm_12>, |
| 488 | LWL_FM_MM<0x0>; |
| 489 | def LWR_MM : LoadLeftRightMM<"lwr", MipsLWR, GPR32Opnd, mem_mm_12>, |
| 490 | LWL_FM_MM<0x1>; |
| 491 | def SWL_MM : StoreLeftRightMM<"swl", MipsSWL, GPR32Opnd, mem_mm_12>, |
| 492 | LWL_FM_MM<0x8>; |
| 493 | def SWR_MM : StoreLeftRightMM<"swr", MipsSWR, GPR32Opnd, mem_mm_12>, |
| 494 | LWL_FM_MM<0x9>; |
Vladimir Medic | e0fbb44 | 2013-09-06 12:41:17 +0000 | [diff] [blame] | 495 | |
Zoran Jovanovic | a4c4b5f | 2014-11-19 16:44:02 +0000 | [diff] [blame] | 496 | /// Load and Store Instructions - multiple |
| 497 | def SWM32_MM : StoreMultMM<"swm32">, LWM_FM_MM<0xd>; |
| 498 | def LWM32_MM : LoadMultMM<"lwm32">, LWM_FM_MM<0x5>; |
| 499 | |
Vladimir Medic | e0fbb44 | 2013-09-06 12:41:17 +0000 | [diff] [blame] | 500 | /// Move Conditional |
| 501 | def MOVZ_I_MM : MMRel, CMov_I_I_FT<"movz", GPR32Opnd, GPR32Opnd, |
| 502 | NoItinerary>, ADD_FM_MM<0, 0x58>; |
| 503 | def MOVN_I_MM : MMRel, CMov_I_I_FT<"movn", GPR32Opnd, GPR32Opnd, |
| 504 | NoItinerary>, ADD_FM_MM<0, 0x18>; |
Daniel Sanders | 4aefdc7 | 2014-01-16 17:13:57 +0000 | [diff] [blame] | 505 | def MOVT_I_MM : MMRel, CMov_F_I_FT<"movt", GPR32Opnd, II_MOVT>, |
Vladimir Medic | e0fbb44 | 2013-09-06 12:41:17 +0000 | [diff] [blame] | 506 | CMov_F_I_FM_MM<0x25>; |
Daniel Sanders | 4aefdc7 | 2014-01-16 17:13:57 +0000 | [diff] [blame] | 507 | def MOVF_I_MM : MMRel, CMov_F_I_FT<"movf", GPR32Opnd, II_MOVF>, |
Vladimir Medic | e0fbb44 | 2013-09-06 12:41:17 +0000 | [diff] [blame] | 508 | CMov_F_I_FM_MM<0x5>; |
Vladimir Medic | 457ba56 | 2013-09-06 12:53:21 +0000 | [diff] [blame] | 509 | |
| 510 | /// Move to/from HI/LO |
| 511 | def MTHI_MM : MMRel, MoveToLOHI<"mthi", GPR32Opnd, [HI0]>, |
| 512 | MTLO_FM_MM<0x0b5>; |
| 513 | def MTLO_MM : MMRel, MoveToLOHI<"mtlo", GPR32Opnd, [LO0]>, |
| 514 | MTLO_FM_MM<0x0f5>; |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 515 | def MFHI_MM : MMRel, MoveFromLOHI<"mfhi", GPR32Opnd, AC0>, |
Vladimir Medic | 457ba56 | 2013-09-06 12:53:21 +0000 | [diff] [blame] | 516 | MFLO_FM_MM<0x035>; |
Akira Hatanaka | 1604833 | 2013-10-07 18:49:46 +0000 | [diff] [blame] | 517 | def MFLO_MM : MMRel, MoveFromLOHI<"mflo", GPR32Opnd, AC0>, |
Vladimir Medic | 457ba56 | 2013-09-06 12:53:21 +0000 | [diff] [blame] | 518 | MFLO_FM_MM<0x075>; |
Vladimir Medic | b936da1 | 2013-09-06 13:08:00 +0000 | [diff] [blame] | 519 | |
| 520 | /// Multiply Add/Sub Instructions |
Daniel Sanders | e95a137 | 2014-01-17 14:32:41 +0000 | [diff] [blame] | 521 | def MADD_MM : MMRel, MArithR<"madd", II_MADD, 1>, MULT_FM_MM<0x32c>; |
| 522 | def MADDU_MM : MMRel, MArithR<"maddu", II_MADDU, 1>, MULT_FM_MM<0x36c>; |
| 523 | def MSUB_MM : MMRel, MArithR<"msub", II_MSUB>, MULT_FM_MM<0x3ac>; |
| 524 | def MSUBU_MM : MMRel, MArithR<"msubu", II_MSUBU>, MULT_FM_MM<0x3ec>; |
Zoran Jovanovic | ab85278 | 2013-09-14 06:49:25 +0000 | [diff] [blame] | 525 | |
| 526 | /// Count Leading |
Daniel Sanders | 070fd1c | 2014-05-12 12:41:59 +0000 | [diff] [blame] | 527 | def CLZ_MM : MMRel, CountLeading0<"clz", GPR32Opnd>, CLO_FM_MM<0x16c>, |
| 528 | ISA_MIPS32; |
| 529 | def CLO_MM : MMRel, CountLeading1<"clo", GPR32Opnd>, CLO_FM_MM<0x12c>, |
| 530 | ISA_MIPS32; |
Zoran Jovanovic | ab85278 | 2013-09-14 06:49:25 +0000 | [diff] [blame] | 531 | |
| 532 | /// Sign Ext In Register Instructions. |
Daniel Sanders | fcea810 | 2014-05-12 12:28:15 +0000 | [diff] [blame] | 533 | def SEB_MM : MMRel, SignExtInReg<"seb", i8, GPR32Opnd, II_SEB>, |
| 534 | SEB_FM_MM<0x0ac>, ISA_MIPS32R2; |
| 535 | def SEH_MM : MMRel, SignExtInReg<"seh", i16, GPR32Opnd, II_SEH>, |
| 536 | SEB_FM_MM<0x0ec>, ISA_MIPS32R2; |
Zoran Jovanovic | ab85278 | 2013-09-14 06:49:25 +0000 | [diff] [blame] | 537 | |
| 538 | /// Word Swap Bytes Within Halfwords |
Daniel Sanders | 39d0051 | 2014-05-12 12:15:41 +0000 | [diff] [blame] | 539 | def WSBH_MM : MMRel, SubwordSwap<"wsbh", GPR32Opnd>, SEB_FM_MM<0x1ec>, |
| 540 | ISA_MIPS32R2; |
Zoran Jovanovic | ab85278 | 2013-09-14 06:49:25 +0000 | [diff] [blame] | 541 | |
| 542 | def EXT_MM : MMRel, ExtBase<"ext", GPR32Opnd, uimm5, MipsExt>, |
| 543 | EXT_FM_MM<0x2c>; |
| 544 | def INS_MM : MMRel, InsBase<"ins", GPR32Opnd, uimm5, MipsIns>, |
| 545 | EXT_FM_MM<0x0c>; |
Zoran Jovanovic | 507e084 | 2013-10-29 16:38:59 +0000 | [diff] [blame] | 546 | |
| 547 | /// Jump Instructions |
| 548 | let DecoderMethod = "DecodeJumpTargetMM" in { |
| 549 | def J_MM : MMRel, JumpFJ<jmptarget_mm, "j", br, bb, "j">, |
| 550 | J_FM_MM<0x35>; |
| 551 | def JAL_MM : MMRel, JumpLink<"jal", calltarget_mm>, J_FM_MM<0x3d>; |
Zoran Jovanovic | 507e084 | 2013-10-29 16:38:59 +0000 | [diff] [blame] | 552 | } |
| 553 | def JR_MM : MMRel, IndirectBranch<"jr", GPR32Opnd>, JR_FM_MM<0x3c>; |
Zoran Jovanovic | 87d13e5 | 2014-03-20 10:18:24 +0000 | [diff] [blame] | 554 | def JALR_MM : JumpLinkReg<"jalr", GPR32Opnd>, JALR_FM_MM<0x03c>; |
Zoran Jovanovic | 8a80aa7 | 2013-11-04 14:53:22 +0000 | [diff] [blame] | 555 | |
Zoran Jovanovic | ac9ef12 | 2014-09-12 13:43:41 +0000 | [diff] [blame] | 556 | /// Jump Instructions - Short Delay Slot |
| 557 | def JALS_MM : JumpLinkMM<"jals", calltarget_mm>, J_FM_MM<0x1d>; |
| 558 | def JALRS_MM : JumpLinkRegMM<"jalrs", GPR32Opnd>, JALR_FM_MM<0x13c>; |
| 559 | |
Zoran Jovanovic | 8a80aa7 | 2013-11-04 14:53:22 +0000 | [diff] [blame] | 560 | /// Branch Instructions |
| 561 | def BEQ_MM : MMRel, CBranch<"beq", brtarget_mm, seteq, GPR32Opnd>, |
| 562 | BEQ_FM_MM<0x25>; |
| 563 | def BNE_MM : MMRel, CBranch<"bne", brtarget_mm, setne, GPR32Opnd>, |
| 564 | BEQ_FM_MM<0x2d>; |
| 565 | def BGEZ_MM : MMRel, CBranchZero<"bgez", brtarget_mm, setge, GPR32Opnd>, |
| 566 | BGEZ_FM_MM<0x2>; |
| 567 | def BGTZ_MM : MMRel, CBranchZero<"bgtz", brtarget_mm, setgt, GPR32Opnd>, |
| 568 | BGEZ_FM_MM<0x6>; |
| 569 | def BLEZ_MM : MMRel, CBranchZero<"blez", brtarget_mm, setle, GPR32Opnd>, |
| 570 | BGEZ_FM_MM<0x4>; |
| 571 | def BLTZ_MM : MMRel, CBranchZero<"bltz", brtarget_mm, setlt, GPR32Opnd>, |
| 572 | BGEZ_FM_MM<0x0>; |
| 573 | def BGEZAL_MM : MMRel, BGEZAL_FT<"bgezal", brtarget_mm, GPR32Opnd>, |
| 574 | BGEZAL_FM_MM<0x03>; |
| 575 | def BLTZAL_MM : MMRel, BGEZAL_FT<"bltzal", brtarget_mm, GPR32Opnd>, |
| 576 | BGEZAL_FM_MM<0x01>; |
Zoran Jovanovic | c18b6d1 | 2013-11-07 14:35:24 +0000 | [diff] [blame] | 577 | |
Zoran Jovanovic | ed6dd6b | 2014-09-12 13:51:58 +0000 | [diff] [blame] | 578 | /// Branch Instructions - Short Delay Slot |
| 579 | def BGEZALS_MM : BranchCompareToZeroLinkMM<"bgezals", brtarget_mm, |
| 580 | GPR32Opnd>, BGEZAL_FM_MM<0x13>; |
| 581 | def BLTZALS_MM : BranchCompareToZeroLinkMM<"bltzals", brtarget_mm, |
| 582 | GPR32Opnd>, BGEZAL_FM_MM<0x11>; |
| 583 | |
Zoran Jovanovic | 8e918c3 | 2013-12-19 16:25:00 +0000 | [diff] [blame] | 584 | /// Control Instructions |
| 585 | def SYNC_MM : MMRel, SYNC_FT<"sync">, SYNC_FM_MM; |
| 586 | def BREAK_MM : MMRel, BRK_FT<"break">, BRK_FM_MM; |
| 587 | def SYSCALL_MM : MMRel, SYS_FT<"syscall">, SYS_FM_MM; |
Zoran Jovanovic | a0f5328 | 2014-03-20 10:41:37 +0000 | [diff] [blame] | 588 | def WAIT_MM : WaitMM<"wait">, WAIT_FM_MM; |
Zoran Jovanovic | 8e918c3 | 2013-12-19 16:25:00 +0000 | [diff] [blame] | 589 | def ERET_MM : MMRel, ER_FT<"eret">, ER_FM_MM<0x3cd>; |
| 590 | def DERET_MM : MMRel, ER_FT<"deret">, ER_FM_MM<0x38d>; |
Daniel Sanders | 387fc15 | 2014-05-13 11:45:36 +0000 | [diff] [blame] | 591 | def EI_MM : MMRel, DEI_FT<"ei", GPR32Opnd>, EI_FM_MM<0x15d>, |
| 592 | ISA_MIPS32R2; |
| 593 | def DI_MM : MMRel, DEI_FT<"di", GPR32Opnd>, EI_FM_MM<0x11d>, |
| 594 | ISA_MIPS32R2; |
Zoran Jovanovic | 8e918c3 | 2013-12-19 16:25:00 +0000 | [diff] [blame] | 595 | |
Zoran Jovanovic | c18b6d1 | 2013-11-07 14:35:24 +0000 | [diff] [blame] | 596 | /// Trap Instructions |
| 597 | def TEQ_MM : MMRel, TEQ_FT<"teq", GPR32Opnd>, TEQ_FM_MM<0x0>; |
| 598 | def TGE_MM : MMRel, TEQ_FT<"tge", GPR32Opnd>, TEQ_FM_MM<0x08>; |
| 599 | def TGEU_MM : MMRel, TEQ_FT<"tgeu", GPR32Opnd>, TEQ_FM_MM<0x10>; |
| 600 | def TLT_MM : MMRel, TEQ_FT<"tlt", GPR32Opnd>, TEQ_FM_MM<0x20>; |
| 601 | def TLTU_MM : MMRel, TEQ_FT<"tltu", GPR32Opnd>, TEQ_FM_MM<0x28>; |
| 602 | def TNE_MM : MMRel, TEQ_FT<"tne", GPR32Opnd>, TEQ_FM_MM<0x30>; |
Zoran Jovanovic | ccb70ca | 2013-11-13 13:15:03 +0000 | [diff] [blame] | 603 | |
| 604 | def TEQI_MM : MMRel, TEQI_FT<"teqi", GPR32Opnd>, TEQI_FM_MM<0x0e>; |
| 605 | def TGEI_MM : MMRel, TEQI_FT<"tgei", GPR32Opnd>, TEQI_FM_MM<0x09>; |
| 606 | def TGEIU_MM : MMRel, TEQI_FT<"tgeiu", GPR32Opnd>, TEQI_FM_MM<0x0b>; |
| 607 | def TLTI_MM : MMRel, TEQI_FT<"tlti", GPR32Opnd>, TEQI_FM_MM<0x08>; |
| 608 | def TLTIU_MM : MMRel, TEQI_FT<"tltiu", GPR32Opnd>, TEQI_FM_MM<0x0a>; |
| 609 | def TNEI_MM : MMRel, TEQI_FT<"tnei", GPR32Opnd>, TEQI_FM_MM<0x0c>; |
Zoran Jovanovic | ff9d5f3 | 2013-12-19 16:12:56 +0000 | [diff] [blame] | 610 | |
| 611 | /// Load-linked, Store-conditional |
| 612 | def LL_MM : LLBaseMM<"ll", GPR32Opnd>, LL_FM_MM<0x3>; |
| 613 | def SC_MM : SCBaseMM<"sc", GPR32Opnd>, LL_FM_MM<0xb>; |
Zoran Jovanovic | 4e7ac4a | 2014-09-12 13:33:33 +0000 | [diff] [blame] | 614 | |
| 615 | def TLBP_MM : MMRel, TLB<"tlbp">, COP0_TLB_FM_MM<0x0d>; |
| 616 | def TLBR_MM : MMRel, TLB<"tlbr">, COP0_TLB_FM_MM<0x4d>; |
| 617 | def TLBWI_MM : MMRel, TLB<"tlbwi">, COP0_TLB_FM_MM<0x8d>; |
| 618 | def TLBWR_MM : MMRel, TLB<"tlbwr">, COP0_TLB_FM_MM<0xcd>; |
Jozef Kolek | dc62fc4 | 2014-11-19 11:25:50 +0000 | [diff] [blame] | 619 | |
| 620 | def SDBBP_MM : MMRel, SYS_FT<"sdbbp">, SDBBP_FM_MM; |
| 621 | def RDHWR_MM : MMRel, ReadHardware<GPR32Opnd, HWRegsOpnd>, RDHWR_FM_MM; |
Akira Hatanaka | be6a818 | 2013-04-19 19:03:11 +0000 | [diff] [blame] | 622 | } |
Zoran Jovanovic | a0f5328 | 2014-03-20 10:41:37 +0000 | [diff] [blame] | 623 | |
Zoran Jovanovic | fd88863 | 2014-11-12 13:30:10 +0000 | [diff] [blame] | 624 | let Predicates = [InMicroMips] in { |
| 625 | |
Zoran Jovanovic | a0f5328 | 2014-03-20 10:41:37 +0000 | [diff] [blame] | 626 | //===----------------------------------------------------------------------===// |
Zoran Jovanovic | 9f99723 | 2014-11-05 17:38:31 +0000 | [diff] [blame] | 627 | // MicroMips arbitrary patterns that map to one or more instructions |
| 628 | //===----------------------------------------------------------------------===// |
| 629 | |
Jozef Kolek | 4d55b4d | 2014-11-19 13:23:58 +0000 | [diff] [blame] | 630 | def : MipsPat<(add GPRMM16:$src, immSExtAddiur2:$imm), |
| 631 | (ADDIUR2_MM GPRMM16:$src, immSExtAddiur2:$imm)>; |
Jozef Kolek | 73f64ea | 2014-11-19 13:11:09 +0000 | [diff] [blame] | 632 | def : MipsPat<(add GPR32:$src, immSExtAddius5:$imm), |
| 633 | (ADDIUS5_MM GPR32:$src, immSExtAddius5:$imm)>; |
| 634 | def : MipsPat<(add GPR32:$src, immSExt16:$imm), |
| 635 | (ADDiu_MM GPR32:$src, immSExt16:$imm)>; |
| 636 | |
Zoran Jovanovic | 06c9d55 | 2014-11-05 17:43:00 +0000 | [diff] [blame] | 637 | def : MipsPat<(and GPRMM16:$src, immZExtAndi16:$imm), |
| 638 | (ANDI16_MM GPRMM16:$src, immZExtAndi16:$imm)>; |
| 639 | def : MipsPat<(and GPR32:$src, immZExt16:$imm), |
| 640 | (ANDi_MM GPR32:$src, immZExt16:$imm)>; |
| 641 | |
Zoran Jovanovic | 9f99723 | 2014-11-05 17:38:31 +0000 | [diff] [blame] | 642 | def : MipsPat<(shl GPRMM16:$src, immZExt2Shift:$imm), |
| 643 | (SLL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; |
| 644 | def : MipsPat<(shl GPR32:$src, immZExt5:$imm), |
| 645 | (SLL_MM GPR32:$src, immZExt5:$imm)>; |
| 646 | |
| 647 | def : MipsPat<(srl GPRMM16:$src, immZExt2Shift:$imm), |
| 648 | (SRL16_MM GPRMM16:$src, immZExt2Shift:$imm)>; |
| 649 | def : MipsPat<(srl GPR32:$src, immZExt5:$imm), |
| 650 | (SRL_MM GPR32:$src, immZExt5:$imm)>; |
| 651 | |
| 652 | //===----------------------------------------------------------------------===// |
Zoran Jovanovic | a0f5328 | 2014-03-20 10:41:37 +0000 | [diff] [blame] | 653 | // MicroMips instruction aliases |
| 654 | //===----------------------------------------------------------------------===// |
| 655 | |
Daniel Sanders | 7d290b0 | 2014-05-08 16:12:31 +0000 | [diff] [blame] | 656 | def : MipsInstAlias<"wait", (WAIT_MM 0x0), 1>; |
Zoran Jovanovic | a0f5328 | 2014-03-20 10:41:37 +0000 | [diff] [blame] | 657 | } |