blob: 26b6eebf42952fe006cf587475d2f115bb922ce7 [file] [log] [blame]
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +00001//===-- llvm/CodeGen/VirtRegMap.cpp - Virtual Register Map ----------------===//
2//
3// The LLVM Compiler Infrastructure
4//
5// This file was developed by the LLVM research group and is distributed under
6// the University of Illinois Open Source License. See LICENSE.TXT for details.
7//
8//===----------------------------------------------------------------------===//
9//
Chris Lattner8c4d88d2004-09-30 01:54:45 +000010// This file implements the VirtRegMap class.
11//
12// It also contains implementations of the the Spiller interface, which, given a
13// virtual register map and a machine function, eliminates all virtual
14// references by replacing them with physical register references - adding spill
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000015// code as necessary.
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000016//
17//===----------------------------------------------------------------------===//
18
Chris Lattner8c4d88d2004-09-30 01:54:45 +000019#define DEBUG_TYPE "spiller"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000020#include "VirtRegMap.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000021#include "llvm/Function.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000022#include "llvm/CodeGen/MachineFrameInfo.h"
Chris Lattner8c4d88d2004-09-30 01:54:45 +000023#include "llvm/CodeGen/MachineFunction.h"
24#include "llvm/CodeGen/SSARegMap.h"
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000025#include "llvm/Target/TargetMachine.h"
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000026#include "llvm/Target/TargetInstrInfo.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000027#include "llvm/Support/CommandLine.h"
28#include "llvm/Support/Debug.h"
Chris Lattnera4f0b3a2006-08-27 12:54:02 +000029#include "llvm/Support/Compiler.h"
Reid Spencer551ccae2004-09-01 22:55:40 +000030#include "llvm/ADT/Statistic.h"
31#include "llvm/ADT/STLExtras.h"
Chris Lattner27f29162004-10-26 15:35:58 +000032#include <algorithm>
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000033using namespace llvm;
34
35namespace {
Chris Lattnerac0b6ae2006-12-06 17:46:33 +000036 static Statistic NumSpills("spiller", "Number of register spills");
37 static Statistic NumStores("spiller", "Number of stores added");
38 static Statistic NumLoads ("spiller", "Number of loads added");
39 static Statistic NumReused("spiller", "Number of values reused");
40 static Statistic NumDSE ("spiller", "Number of dead stores elided");
41 static Statistic NumDCE ("spiller", "Number of copies elided");
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +000042
Chris Lattner8c4d88d2004-09-30 01:54:45 +000043 enum SpillerName { simple, local };
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +000044
Andrew Lenharthed41f1b2006-07-20 17:28:38 +000045 static cl::opt<SpillerName>
Chris Lattner8c4d88d2004-09-30 01:54:45 +000046 SpillerOpt("spiller",
Chris Lattner7fb64342004-10-01 19:04:51 +000047 cl::desc("Spiller to use: (default: local)"),
Chris Lattner8c4d88d2004-09-30 01:54:45 +000048 cl::Prefix,
49 cl::values(clEnumVal(simple, " simple spiller"),
50 clEnumVal(local, " local spiller"),
51 clEnumValEnd),
Chris Lattner7fb64342004-10-01 19:04:51 +000052 cl::init(local));
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000053}
54
Chris Lattner8c4d88d2004-09-30 01:54:45 +000055//===----------------------------------------------------------------------===//
56// VirtRegMap implementation
57//===----------------------------------------------------------------------===//
58
Chris Lattner29268692006-09-05 02:12:02 +000059VirtRegMap::VirtRegMap(MachineFunction &mf)
60 : TII(*mf.getTarget().getInstrInfo()), MF(mf),
61 Virt2PhysMap(NO_PHYS_REG), Virt2StackSlotMap(NO_STACK_SLOT) {
62 grow();
63}
64
Chris Lattner8c4d88d2004-09-30 01:54:45 +000065void VirtRegMap::grow() {
Chris Lattner7f690e62004-09-30 02:15:18 +000066 Virt2PhysMap.grow(MF.getSSARegMap()->getLastVirtReg());
67 Virt2StackSlotMap.grow(MF.getSSARegMap()->getLastVirtReg());
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +000068}
69
Chris Lattner8c4d88d2004-09-30 01:54:45 +000070int VirtRegMap::assignVirt2StackSlot(unsigned virtReg) {
71 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000072 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000073 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000074 const TargetRegisterClass* RC = MF.getSSARegMap()->getRegClass(virtReg);
75 int frameIndex = MF.getFrameInfo()->CreateStackObject(RC->getSize(),
76 RC->getAlignment());
77 Virt2StackSlotMap[virtReg] = frameIndex;
Chris Lattner8c4d88d2004-09-30 01:54:45 +000078 ++NumSpills;
79 return frameIndex;
80}
81
82void VirtRegMap::assignVirt2StackSlot(unsigned virtReg, int frameIndex) {
83 assert(MRegisterInfo::isVirtualRegister(virtReg));
Chris Lattner7f690e62004-09-30 02:15:18 +000084 assert(Virt2StackSlotMap[virtReg] == NO_STACK_SLOT &&
Chris Lattner8c4d88d2004-09-30 01:54:45 +000085 "attempt to assign stack slot to already spilled register");
Chris Lattner7f690e62004-09-30 02:15:18 +000086 Virt2StackSlotMap[virtReg] = frameIndex;
Alkis Evlogimenos38af59a2004-05-29 20:38:05 +000087}
88
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000089void VirtRegMap::virtFolded(unsigned VirtReg, MachineInstr *OldMI,
Chris Lattner35f27052006-05-01 21:16:03 +000090 unsigned OpNo, MachineInstr *NewMI) {
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000091 // Move previous memory references folded to new instruction.
92 MI2VirtMapTy::iterator IP = MI2VirtMap.lower_bound(NewMI);
Misha Brukmanedf128a2005-04-21 22:36:52 +000093 for (MI2VirtMapTy::iterator I = MI2VirtMap.lower_bound(OldMI),
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000094 E = MI2VirtMap.end(); I != E && I->first == OldMI; ) {
95 MI2VirtMap.insert(IP, std::make_pair(NewMI, I->second));
Chris Lattnerdbea9732004-09-30 16:35:08 +000096 MI2VirtMap.erase(I++);
Chris Lattner8c4d88d2004-09-30 01:54:45 +000097 }
Chris Lattnerdbea9732004-09-30 16:35:08 +000098
Chris Lattnerbec6a9e2004-10-01 23:15:36 +000099 ModRef MRInfo;
Evan Cheng5c2a4602006-12-08 08:02:34 +0000100 const TargetInstrDescriptor *TID = OldMI->getInstrDescriptor();
101 if (TID->getOperandConstraint(OpNo, TOI::TIED_TO) != -1 ||
Evan Chengcc22a7a2006-12-08 18:45:48 +0000102 TID->findTiedToSrcOperand(OpNo) != -1) {
Chris Lattner29268692006-09-05 02:12:02 +0000103 // Folded a two-address operand.
104 MRInfo = isModRef;
105 } else if (OldMI->getOperand(OpNo).isDef()) {
106 MRInfo = isMod;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000107 } else {
Chris Lattner29268692006-09-05 02:12:02 +0000108 MRInfo = isRef;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000109 }
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000110
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000111 // add new memory reference
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000112 MI2VirtMap.insert(IP, std::make_pair(NewMI, std::make_pair(VirtReg, MRInfo)));
Alkis Evlogimenos5f375022004-03-01 20:05:10 +0000113}
114
Chris Lattner7f690e62004-09-30 02:15:18 +0000115void VirtRegMap::print(std::ostream &OS) const {
116 const MRegisterInfo* MRI = MF.getTarget().getRegisterInfo();
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000117
Chris Lattner7f690e62004-09-30 02:15:18 +0000118 OS << "********** REGISTER MAP **********\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000119 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000120 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i) {
121 if (Virt2PhysMap[i] != (unsigned)VirtRegMap::NO_PHYS_REG)
122 OS << "[reg" << i << " -> " << MRI->getName(Virt2PhysMap[i]) << "]\n";
Misha Brukmanedf128a2005-04-21 22:36:52 +0000123
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000124 }
125
126 for (unsigned i = MRegisterInfo::FirstVirtualRegister,
Chris Lattner7f690e62004-09-30 02:15:18 +0000127 e = MF.getSSARegMap()->getLastVirtReg(); i <= e; ++i)
128 if (Virt2StackSlotMap[i] != VirtRegMap::NO_STACK_SLOT)
129 OS << "[reg" << i << " -> fi#" << Virt2StackSlotMap[i] << "]\n";
130 OS << '\n';
Alkis Evlogimenos34d9bc92004-02-23 23:08:11 +0000131}
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000132
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000133void VirtRegMap::dump() const {
Bill Wendling5c7e3262006-12-17 05:15:13 +0000134 print(DOUT);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000135}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000136
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000137
138//===----------------------------------------------------------------------===//
139// Simple Spiller Implementation
140//===----------------------------------------------------------------------===//
141
142Spiller::~Spiller() {}
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000143
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000144namespace {
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000145 struct VISIBILITY_HIDDEN SimpleSpiller : public Spiller {
Chris Lattner35f27052006-05-01 21:16:03 +0000146 bool runOnMachineFunction(MachineFunction& mf, VirtRegMap &VRM);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000147 };
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000148}
149
Chris Lattner35f27052006-05-01 21:16:03 +0000150bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000151 DOUT << "********** REWRITE MACHINE CODE **********\n";
152 DOUT << "********** Function: " << MF.getFunction()->getName() << '\n';
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000153 const TargetMachine &TM = MF.getTarget();
154 const MRegisterInfo &MRI = *TM.getRegisterInfo();
155 bool *PhysRegsUsed = MF.getUsedPhysregs();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000156
Chris Lattner4ea1b822004-09-30 02:33:48 +0000157 // LoadedRegs - Keep track of which vregs are loaded, so that we only load
158 // each vreg once (in the case where a spilled vreg is used by multiple
159 // operands). This is always smaller than the number of operands to the
160 // current machine instr, so it should be small.
161 std::vector<unsigned> LoadedRegs;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000162
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000163 for (MachineFunction::iterator MBBI = MF.begin(), E = MF.end();
164 MBBI != E; ++MBBI) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000165 DOUT << MBBI->getBasicBlock()->getName() << ":\n";
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000166 MachineBasicBlock &MBB = *MBBI;
167 for (MachineBasicBlock::iterator MII = MBB.begin(),
168 E = MBB.end(); MII != E; ++MII) {
169 MachineInstr &MI = *MII;
170 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000171 MachineOperand &MO = MI.getOperand(i);
Chris Lattner886dd912005-04-04 21:35:34 +0000172 if (MO.isRegister() && MO.getReg())
173 if (MRegisterInfo::isVirtualRegister(MO.getReg())) {
174 unsigned VirtReg = MO.getReg();
175 unsigned PhysReg = VRM.getPhys(VirtReg);
176 if (VRM.hasStackSlot(VirtReg)) {
177 int StackSlot = VRM.getStackSlot(VirtReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000178 const TargetRegisterClass* RC =
179 MF.getSSARegMap()->getRegClass(VirtReg);
Misha Brukmanedf128a2005-04-21 22:36:52 +0000180
Chris Lattner886dd912005-04-04 21:35:34 +0000181 if (MO.isUse() &&
182 std::find(LoadedRegs.begin(), LoadedRegs.end(), VirtReg)
183 == LoadedRegs.end()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000184 MRI.loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000185 LoadedRegs.push_back(VirtReg);
186 ++NumLoads;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000187 DOUT << '\t' << *prior(MII);
Chris Lattner886dd912005-04-04 21:35:34 +0000188 }
Misha Brukmanedf128a2005-04-21 22:36:52 +0000189
Chris Lattner886dd912005-04-04 21:35:34 +0000190 if (MO.isDef()) {
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000191 MRI.storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Chris Lattner886dd912005-04-04 21:35:34 +0000192 ++NumStores;
193 }
Chris Lattner0fc27cc2004-09-30 02:59:33 +0000194 }
Chris Lattner886dd912005-04-04 21:35:34 +0000195 PhysRegsUsed[PhysReg] = true;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000196 MI.getOperand(i).setReg(PhysReg);
Chris Lattner886dd912005-04-04 21:35:34 +0000197 } else {
198 PhysRegsUsed[MO.getReg()] = true;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000199 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000200 }
Chris Lattner886dd912005-04-04 21:35:34 +0000201
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000202 DOUT << '\t' << MI;
Chris Lattner4ea1b822004-09-30 02:33:48 +0000203 LoadedRegs.clear();
Alkis Evlogimenosdd420e02004-03-01 23:18:15 +0000204 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000205 }
206 return true;
207}
208
209//===----------------------------------------------------------------------===//
210// Local Spiller Implementation
211//===----------------------------------------------------------------------===//
212
213namespace {
Chris Lattner7fb64342004-10-01 19:04:51 +0000214 /// LocalSpiller - This spiller does a simple pass over the machine basic
215 /// block to attempt to keep spills in registers as much as possible for
216 /// blocks that have low register pressure (the vreg may be spilled due to
217 /// register pressure in other blocks).
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000218 class VISIBILITY_HIDDEN LocalSpiller : public Spiller {
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000219 const MRegisterInfo *MRI;
Chris Lattner7fb64342004-10-01 19:04:51 +0000220 const TargetInstrInfo *TII;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000221 public:
Chris Lattner35f27052006-05-01 21:16:03 +0000222 bool runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000223 MRI = MF.getTarget().getRegisterInfo();
224 TII = MF.getTarget().getInstrInfo();
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000225 DOUT << "\n**** Local spiller rewriting function '"
226 << MF.getFunction()->getName() << "':\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000227
Chris Lattner7fb64342004-10-01 19:04:51 +0000228 for (MachineFunction::iterator MBB = MF.begin(), E = MF.end();
229 MBB != E; ++MBB)
230 RewriteMBB(*MBB, VRM);
231 return true;
232 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000233 private:
Chris Lattner35f27052006-05-01 21:16:03 +0000234 void RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM);
Chris Lattner7fb64342004-10-01 19:04:51 +0000235 void ClobberPhysReg(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000236 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner7fb64342004-10-01 19:04:51 +0000237 void ClobberPhysRegOnly(unsigned PR, std::map<int, unsigned> &SpillSlots,
Chris Lattner07cf1412006-02-03 00:36:31 +0000238 std::multimap<unsigned, int> &PhysRegs);
239 void ModifyStackSlot(int Slot, std::map<int, unsigned> &SpillSlots,
240 std::multimap<unsigned, int> &PhysRegs);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000241 };
242}
243
Chris Lattner66cf80f2006-02-03 23:13:58 +0000244/// AvailableSpills - As the local spiller is scanning and rewriting an MBB from
245/// top down, keep track of which spills slots are available in each register.
Chris Lattner593c9582006-02-03 23:28:46 +0000246///
247/// Note that not all physregs are created equal here. In particular, some
248/// physregs are reloads that we are allowed to clobber or ignore at any time.
249/// Other physregs are values that the register allocated program is using that
250/// we cannot CHANGE, but we can read if we like. We keep track of this on a
251/// per-stack-slot basis as the low bit in the value of the SpillSlotsAvailable
252/// entries. The predicate 'canClobberPhysReg()' checks this bit and
253/// addAvailable sets it if.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000254namespace {
255class VISIBILITY_HIDDEN AvailableSpills {
Chris Lattner66cf80f2006-02-03 23:13:58 +0000256 const MRegisterInfo *MRI;
257 const TargetInstrInfo *TII;
258
259 // SpillSlotsAvailable - This map keeps track of all of the spilled virtual
260 // register values that are still available, due to being loaded or stored to,
261 // but not invalidated yet.
262 std::map<int, unsigned> SpillSlotsAvailable;
263
264 // PhysRegsAvailable - This is the inverse of SpillSlotsAvailable, indicating
265 // which stack slot values are currently held by a physreg. This is used to
266 // invalidate entries in SpillSlotsAvailable when a physreg is modified.
267 std::multimap<unsigned, int> PhysRegsAvailable;
268
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000269 void disallowClobberPhysRegOnly(unsigned PhysReg);
270
Chris Lattner66cf80f2006-02-03 23:13:58 +0000271 void ClobberPhysRegOnly(unsigned PhysReg);
272public:
273 AvailableSpills(const MRegisterInfo *mri, const TargetInstrInfo *tii)
274 : MRI(mri), TII(tii) {
275 }
276
277 /// getSpillSlotPhysReg - If the specified stack slot is available in a
278 /// physical register, return that PhysReg, otherwise return 0.
279 unsigned getSpillSlotPhysReg(int Slot) const {
280 std::map<int, unsigned>::const_iterator I = SpillSlotsAvailable.find(Slot);
281 if (I != SpillSlotsAvailable.end())
Chris Lattner593c9582006-02-03 23:28:46 +0000282 return I->second >> 1; // Remove the CanClobber bit.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000283 return 0;
284 }
Chris Lattner540fec62006-02-25 01:51:33 +0000285
286 const MRegisterInfo *getRegInfo() const { return MRI; }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000287
288 /// addAvailable - Mark that the specified stack slot is available in the
Chris Lattner593c9582006-02-03 23:28:46 +0000289 /// specified physreg. If CanClobber is true, the physreg can be modified at
290 /// any time without changing the semantics of the program.
291 void addAvailable(int Slot, unsigned Reg, bool CanClobber = true) {
Chris Lattner86662492006-02-03 23:50:46 +0000292 // If this stack slot is thought to be available in some other physreg,
293 // remove its record.
294 ModifyStackSlot(Slot);
295
Chris Lattner66cf80f2006-02-03 23:13:58 +0000296 PhysRegsAvailable.insert(std::make_pair(Reg, Slot));
Jeff Cohen003cecb2006-02-04 03:27:39 +0000297 SpillSlotsAvailable[Slot] = (Reg << 1) | (unsigned)CanClobber;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000298
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000299 DOUT << "Remembering SS#" << Slot << " in physreg "
300 << MRI->getName(Reg) << "\n";
Chris Lattner66cf80f2006-02-03 23:13:58 +0000301 }
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000302
Chris Lattner593c9582006-02-03 23:28:46 +0000303 /// canClobberPhysReg - Return true if the spiller is allowed to change the
304 /// value of the specified stackslot register if it desires. The specified
305 /// stack slot must be available in a physreg for this query to make sense.
306 bool canClobberPhysReg(int Slot) const {
307 assert(SpillSlotsAvailable.count(Slot) && "Slot not available!");
308 return SpillSlotsAvailable.find(Slot)->second & 1;
309 }
Chris Lattner66cf80f2006-02-03 23:13:58 +0000310
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000311 /// disallowClobberPhysReg - Unset the CanClobber bit of the specified
312 /// stackslot register. The register is still available but is no longer
313 /// allowed to be modifed.
314 void disallowClobberPhysReg(unsigned PhysReg);
315
Chris Lattner66cf80f2006-02-03 23:13:58 +0000316 /// ClobberPhysReg - This is called when the specified physreg changes
317 /// value. We use this to invalidate any info about stuff we thing lives in
318 /// it and any of its aliases.
319 void ClobberPhysReg(unsigned PhysReg);
320
321 /// ModifyStackSlot - This method is called when the value in a stack slot
322 /// changes. This removes information about which register the previous value
323 /// for this slot lives in (as the previous value is dead now).
324 void ModifyStackSlot(int Slot);
325};
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000326}
Chris Lattner66cf80f2006-02-03 23:13:58 +0000327
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000328/// disallowClobberPhysRegOnly - Unset the CanClobber bit of the specified
329/// stackslot register. The register is still available but is no longer
330/// allowed to be modifed.
331void AvailableSpills::disallowClobberPhysRegOnly(unsigned PhysReg) {
332 std::multimap<unsigned, int>::iterator I =
333 PhysRegsAvailable.lower_bound(PhysReg);
334 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
335 int Slot = I->second;
336 I++;
337 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
338 "Bidirectional map mismatch!");
339 SpillSlotsAvailable[Slot] &= ~1;
340 DOUT << "PhysReg " << MRI->getName(PhysReg)
341 << " copied, it is available for use but can no longer be modified\n";
342 }
343}
344
345/// disallowClobberPhysReg - Unset the CanClobber bit of the specified
346/// stackslot register and its aliases. The register and its aliases may
347/// still available but is no longer allowed to be modifed.
348void AvailableSpills::disallowClobberPhysReg(unsigned PhysReg) {
349 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
350 disallowClobberPhysRegOnly(*AS);
351 disallowClobberPhysRegOnly(PhysReg);
352}
353
Chris Lattner66cf80f2006-02-03 23:13:58 +0000354/// ClobberPhysRegOnly - This is called when the specified physreg changes
355/// value. We use this to invalidate any info about stuff we thing lives in it.
356void AvailableSpills::ClobberPhysRegOnly(unsigned PhysReg) {
357 std::multimap<unsigned, int>::iterator I =
358 PhysRegsAvailable.lower_bound(PhysReg);
Chris Lattner07cf1412006-02-03 00:36:31 +0000359 while (I != PhysRegsAvailable.end() && I->first == PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000360 int Slot = I->second;
Chris Lattner07cf1412006-02-03 00:36:31 +0000361 PhysRegsAvailable.erase(I++);
Chris Lattner593c9582006-02-03 23:28:46 +0000362 assert((SpillSlotsAvailable[Slot] >> 1) == PhysReg &&
Chris Lattner66cf80f2006-02-03 23:13:58 +0000363 "Bidirectional map mismatch!");
364 SpillSlotsAvailable.erase(Slot);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000365 DOUT << "PhysReg " << MRI->getName(PhysReg)
366 << " clobbered, invalidating SS#" << Slot << "\n";
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000367 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000368}
369
Chris Lattner66cf80f2006-02-03 23:13:58 +0000370/// ClobberPhysReg - This is called when the specified physreg changes
371/// value. We use this to invalidate any info about stuff we thing lives in
372/// it and any of its aliases.
373void AvailableSpills::ClobberPhysReg(unsigned PhysReg) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000374 for (const unsigned *AS = MRI->getAliasSet(PhysReg); *AS; ++AS)
Chris Lattner66cf80f2006-02-03 23:13:58 +0000375 ClobberPhysRegOnly(*AS);
376 ClobberPhysRegOnly(PhysReg);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000377}
378
Chris Lattner07cf1412006-02-03 00:36:31 +0000379/// ModifyStackSlot - This method is called when the value in a stack slot
380/// changes. This removes information about which register the previous value
381/// for this slot lives in (as the previous value is dead now).
Chris Lattner66cf80f2006-02-03 23:13:58 +0000382void AvailableSpills::ModifyStackSlot(int Slot) {
383 std::map<int, unsigned>::iterator It = SpillSlotsAvailable.find(Slot);
384 if (It == SpillSlotsAvailable.end()) return;
Chris Lattner593c9582006-02-03 23:28:46 +0000385 unsigned Reg = It->second >> 1;
Chris Lattner66cf80f2006-02-03 23:13:58 +0000386 SpillSlotsAvailable.erase(It);
Chris Lattner07cf1412006-02-03 00:36:31 +0000387
388 // This register may hold the value of multiple stack slots, only remove this
389 // stack slot from the set of values the register contains.
390 std::multimap<unsigned, int>::iterator I = PhysRegsAvailable.lower_bound(Reg);
391 for (; ; ++I) {
392 assert(I != PhysRegsAvailable.end() && I->first == Reg &&
393 "Map inverse broken!");
394 if (I->second == Slot) break;
395 }
396 PhysRegsAvailable.erase(I);
397}
398
399
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000400
Chris Lattner7fb64342004-10-01 19:04:51 +0000401// ReusedOp - For each reused operand, we keep track of a bit of information, in
402// case we need to rollback upon processing a new operand. See comments below.
403namespace {
404 struct ReusedOp {
405 // The MachineInstr operand that reused an available value.
406 unsigned Operand;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000407
Chris Lattner7fb64342004-10-01 19:04:51 +0000408 // StackSlot - The spill slot of the value being reused.
409 unsigned StackSlot;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000410
Chris Lattner7fb64342004-10-01 19:04:51 +0000411 // PhysRegReused - The physical register the value was available in.
412 unsigned PhysRegReused;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000413
Chris Lattner7fb64342004-10-01 19:04:51 +0000414 // AssignedPhysReg - The physreg that was assigned for use by the reload.
415 unsigned AssignedPhysReg;
Chris Lattner8a61a752005-10-06 17:19:06 +0000416
417 // VirtReg - The virtual register itself.
418 unsigned VirtReg;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000419
Chris Lattner8a61a752005-10-06 17:19:06 +0000420 ReusedOp(unsigned o, unsigned ss, unsigned prr, unsigned apr,
421 unsigned vreg)
422 : Operand(o), StackSlot(ss), PhysRegReused(prr), AssignedPhysReg(apr),
423 VirtReg(vreg) {}
Chris Lattner7fb64342004-10-01 19:04:51 +0000424 };
Chris Lattner540fec62006-02-25 01:51:33 +0000425
426 /// ReuseInfo - This maintains a collection of ReuseOp's for each operand that
427 /// is reused instead of reloaded.
Chris Lattnerf8c68f62006-06-28 22:17:39 +0000428 class VISIBILITY_HIDDEN ReuseInfo {
Chris Lattner540fec62006-02-25 01:51:33 +0000429 MachineInstr &MI;
430 std::vector<ReusedOp> Reuses;
Evan Chenge077ef62006-11-04 00:21:55 +0000431 bool *PhysRegsClobbered;
Chris Lattner540fec62006-02-25 01:51:33 +0000432 public:
Evan Chenge077ef62006-11-04 00:21:55 +0000433 ReuseInfo(MachineInstr &mi, const MRegisterInfo *mri) : MI(mi) {
434 PhysRegsClobbered = new bool[mri->getNumRegs()];
435 std::fill(PhysRegsClobbered, PhysRegsClobbered+mri->getNumRegs(), false);
436 }
437 ~ReuseInfo() {
438 delete[] PhysRegsClobbered;
439 }
Chris Lattner540fec62006-02-25 01:51:33 +0000440
441 bool hasReuses() const {
442 return !Reuses.empty();
443 }
444
445 /// addReuse - If we choose to reuse a virtual register that is already
446 /// available instead of reloading it, remember that we did so.
447 void addReuse(unsigned OpNo, unsigned StackSlot,
448 unsigned PhysRegReused, unsigned AssignedPhysReg,
449 unsigned VirtReg) {
450 // If the reload is to the assigned register anyway, no undo will be
451 // required.
452 if (PhysRegReused == AssignedPhysReg) return;
453
454 // Otherwise, remember this.
455 Reuses.push_back(ReusedOp(OpNo, StackSlot, PhysRegReused,
456 AssignedPhysReg, VirtReg));
457 }
Evan Chenge077ef62006-11-04 00:21:55 +0000458
459 void markClobbered(unsigned PhysReg) {
460 PhysRegsClobbered[PhysReg] = true;
461 }
462
463 bool isClobbered(unsigned PhysReg) const {
464 return PhysRegsClobbered[PhysReg];
465 }
Chris Lattner540fec62006-02-25 01:51:33 +0000466
467 /// GetRegForReload - We are about to emit a reload into PhysReg. If there
468 /// is some other operand that is using the specified register, either pick
469 /// a new register to use, or evict the previous reload and use this reg.
470 unsigned GetRegForReload(unsigned PhysReg, MachineInstr *MI,
471 AvailableSpills &Spills,
472 std::map<int, MachineInstr*> &MaybeDeadStores) {
473 if (Reuses.empty()) return PhysReg; // This is most often empty.
474
475 for (unsigned ro = 0, e = Reuses.size(); ro != e; ++ro) {
476 ReusedOp &Op = Reuses[ro];
477 // If we find some other reuse that was supposed to use this register
478 // exactly for its reload, we can change this reload to use ITS reload
479 // register.
480 if (Op.PhysRegReused == PhysReg) {
481 // Yup, use the reload register that we didn't use before.
Evan Chenge077ef62006-11-04 00:21:55 +0000482 unsigned NewReg = Op.AssignedPhysReg;
Chris Lattner47cb7172006-02-25 02:03:40 +0000483 return GetRegForReload(NewReg, MI, Spills, MaybeDeadStores);
Chris Lattner540fec62006-02-25 01:51:33 +0000484 } else {
485 // Otherwise, we might also have a problem if a previously reused
486 // value aliases the new register. If so, codegen the previous reload
487 // and use this one.
488 unsigned PRRU = Op.PhysRegReused;
489 const MRegisterInfo *MRI = Spills.getRegInfo();
490 if (MRI->areAliases(PRRU, PhysReg)) {
491 // Okay, we found out that an alias of a reused register
492 // was used. This isn't good because it means we have
493 // to undo a previous reuse.
494 MachineBasicBlock *MBB = MI->getParent();
495 const TargetRegisterClass *AliasRC =
Chris Lattner28bad082006-02-25 02:17:31 +0000496 MBB->getParent()->getSSARegMap()->getRegClass(Op.VirtReg);
497
498 // Copy Op out of the vector and remove it, we're going to insert an
499 // explicit load for it.
500 ReusedOp NewOp = Op;
501 Reuses.erase(Reuses.begin()+ro);
502
503 // Ok, we're going to try to reload the assigned physreg into the
504 // slot that we were supposed to in the first place. However, that
505 // register could hold a reuse. Check to see if it conflicts or
506 // would prefer us to use a different register.
507 unsigned NewPhysReg = GetRegForReload(NewOp.AssignedPhysReg,
508 MI, Spills, MaybeDeadStores);
509
510 MRI->loadRegFromStackSlot(*MBB, MI, NewPhysReg,
511 NewOp.StackSlot, AliasRC);
512 Spills.ClobberPhysReg(NewPhysReg);
513 Spills.ClobberPhysReg(NewOp.PhysRegReused);
Chris Lattner540fec62006-02-25 01:51:33 +0000514
515 // Any stores to this stack slot are not dead anymore.
Chris Lattner28bad082006-02-25 02:17:31 +0000516 MaybeDeadStores.erase(NewOp.StackSlot);
Chris Lattner540fec62006-02-25 01:51:33 +0000517
Chris Lattnere53f4a02006-05-04 17:52:23 +0000518 MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000519
Chris Lattner28bad082006-02-25 02:17:31 +0000520 Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
Chris Lattner540fec62006-02-25 01:51:33 +0000521 ++NumLoads;
522 DEBUG(MachineBasicBlock::iterator MII = MI;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000523 DOUT << '\t' << *prior(MII));
Chris Lattner540fec62006-02-25 01:51:33 +0000524
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000525 DOUT << "Reuse undone!\n";
Chris Lattner540fec62006-02-25 01:51:33 +0000526 --NumReused;
Chris Lattner28bad082006-02-25 02:17:31 +0000527
528 // Finally, PhysReg is now available, go ahead and use it.
Chris Lattner540fec62006-02-25 01:51:33 +0000529 return PhysReg;
530 }
531 }
532 }
533 return PhysReg;
534 }
535 };
Chris Lattner7fb64342004-10-01 19:04:51 +0000536}
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000537
Chris Lattner7fb64342004-10-01 19:04:51 +0000538
539/// rewriteMBB - Keep track of which spills are available even after the
540/// register allocator is done with them. If possible, avoid reloading vregs.
Chris Lattner35f27052006-05-01 21:16:03 +0000541void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000542
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000543 DOUT << MBB.getBasicBlock()->getName() << ":\n";
Chris Lattner7fb64342004-10-01 19:04:51 +0000544
Chris Lattner66cf80f2006-02-03 23:13:58 +0000545 // Spills - Keep track of which spilled values are available in physregs so
546 // that we can choose to reuse the physregs instead of emitting reloads.
547 AvailableSpills Spills(MRI, TII);
548
Chris Lattner52b25db2004-10-01 19:47:12 +0000549 // MaybeDeadStores - When we need to write a value back into a stack slot,
550 // keep track of the inserted store. If the stack slot value is never read
551 // (because the value was used from some available register, for example), and
552 // subsequently stored to, the original store is dead. This map keeps track
553 // of inserted stores that are not used. If we see a subsequent store to the
554 // same stack slot, the original store is deleted.
555 std::map<int, MachineInstr*> MaybeDeadStores;
556
Chris Lattnerb0f31bf2005-01-23 22:45:13 +0000557 bool *PhysRegsUsed = MBB.getParent()->getUsedPhysregs();
558
Chris Lattner7fb64342004-10-01 19:04:51 +0000559 for (MachineBasicBlock::iterator MII = MBB.begin(), E = MBB.end();
560 MII != E; ) {
561 MachineInstr &MI = *MII;
562 MachineBasicBlock::iterator NextMII = MII; ++NextMII;
563
Chris Lattner540fec62006-02-25 01:51:33 +0000564 /// ReusedOperands - Keep track of operand reuse in case we need to undo
565 /// reuse.
Evan Chenge077ef62006-11-04 00:21:55 +0000566 ReuseInfo ReusedOperands(MI, MRI);
567
568 // Loop over all of the implicit defs, clearing them from our available
569 // sets.
Evan Cheng86facc22006-12-15 06:41:01 +0000570 const TargetInstrDescriptor *TID = MI.getInstrDescriptor();
571 const unsigned *ImpDef = TID->ImplicitDefs;
Evan Chenge077ef62006-11-04 00:21:55 +0000572 if (ImpDef) {
573 for ( ; *ImpDef; ++ImpDef) {
574 PhysRegsUsed[*ImpDef] = true;
575 ReusedOperands.markClobbered(*ImpDef);
576 Spills.ClobberPhysReg(*ImpDef);
577 }
578 }
579
Chris Lattner7fb64342004-10-01 19:04:51 +0000580 // Process all of the spilled uses and all non spilled reg references.
581 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
582 MachineOperand &MO = MI.getOperand(i);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000583 if (!MO.isRegister() || MO.getReg() == 0)
584 continue; // Ignore non-register operands.
585
586 if (MRegisterInfo::isPhysicalRegister(MO.getReg())) {
587 // Ignore physregs for spilling, but remember that it is used by this
588 // function.
Chris Lattner886dd912005-04-04 21:35:34 +0000589 PhysRegsUsed[MO.getReg()] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000590 ReusedOperands.markClobbered(MO.getReg());
Chris Lattner50ea01e2005-09-09 20:29:51 +0000591 continue;
592 }
593
594 assert(MRegisterInfo::isVirtualRegister(MO.getReg()) &&
595 "Not a virtual or a physical register?");
596
597 unsigned VirtReg = MO.getReg();
598 if (!VRM.hasStackSlot(VirtReg)) {
599 // This virtual register was assigned a physreg!
600 unsigned Phys = VRM.getPhys(VirtReg);
601 PhysRegsUsed[Phys] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000602 if (MO.isDef())
603 ReusedOperands.markClobbered(Phys);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000604 MI.getOperand(i).setReg(Phys);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000605 continue;
606 }
607
608 // This virtual register is now known to be a spilled value.
609 if (!MO.isUse())
610 continue; // Handle defs in the loop below (handle use&def here though)
Chris Lattner7fb64342004-10-01 19:04:51 +0000611
Chris Lattner50ea01e2005-09-09 20:29:51 +0000612 int StackSlot = VRM.getStackSlot(VirtReg);
613 unsigned PhysReg;
Chris Lattner7fb64342004-10-01 19:04:51 +0000614
Chris Lattner50ea01e2005-09-09 20:29:51 +0000615 // Check to see if this stack slot is available.
Chris Lattneraddc55a2006-04-28 01:46:50 +0000616 if ((PhysReg = Spills.getSpillSlotPhysReg(StackSlot))) {
Chris Lattner7fb64342004-10-01 19:04:51 +0000617
Chris Lattner29268692006-09-05 02:12:02 +0000618 // This spilled operand might be part of a two-address operand. If this
619 // is the case, then changing it will necessarily require changing the
620 // def part of the instruction as well. However, in some cases, we
621 // aren't allowed to modify the reused register. If none of these cases
622 // apply, reuse it.
623 bool CanReuse = true;
Evan Cheng86facc22006-12-15 06:41:01 +0000624 int ti = TID->getOperandConstraint(i, TOI::TIED_TO);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000625 if (ti != -1 &&
626 MI.getOperand(ti).isReg() &&
627 MI.getOperand(ti).getReg() == VirtReg) {
Chris Lattner29268692006-09-05 02:12:02 +0000628 // Okay, we have a two address operand. We can reuse this physreg as
Evan Chenge077ef62006-11-04 00:21:55 +0000629 // long as we are allowed to clobber the value and there is an earlier
630 // def that has already clobbered the physreg.
631 CanReuse = Spills.canClobberPhysReg(StackSlot) &&
632 !ReusedOperands.isClobbered(PhysReg);
Chris Lattner29268692006-09-05 02:12:02 +0000633 }
634
635 if (CanReuse) {
Chris Lattneraddc55a2006-04-28 01:46:50 +0000636 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000637 DOUT << "Reusing SS#" << StackSlot << " from physreg "
638 << MRI->getName(PhysReg) << " for vreg"
639 << VirtReg <<" instead of reloading into physreg "
640 << MRI->getName(VRM.getPhys(VirtReg)) << "\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000641 MI.getOperand(i).setReg(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000642
643 // The only technical detail we have is that we don't know that
644 // PhysReg won't be clobbered by a reloaded stack slot that occurs
645 // later in the instruction. In particular, consider 'op V1, V2'.
646 // If V1 is available in physreg R0, we would choose to reuse it
647 // here, instead of reloading it into the register the allocator
648 // indicated (say R1). However, V2 might have to be reloaded
649 // later, and it might indicate that it needs to live in R0. When
650 // this occurs, we need to have information available that
651 // indicates it is safe to use R1 for the reload instead of R0.
652 //
653 // To further complicate matters, we might conflict with an alias,
654 // or R0 and R1 might not be compatible with each other. In this
655 // case, we actually insert a reload for V1 in R1, ensuring that
656 // we can get at R0 or its alias.
657 ReusedOperands.addReuse(i, StackSlot, PhysReg,
658 VRM.getPhys(VirtReg), VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000659 if (ti != -1)
660 // Only mark it clobbered if this is a use&def operand.
661 ReusedOperands.markClobbered(PhysReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000662 ++NumReused;
663 continue;
664 }
665
666 // Otherwise we have a situation where we have a two-address instruction
667 // whose mod/ref operand needs to be reloaded. This reload is already
668 // available in some register "PhysReg", but if we used PhysReg as the
669 // operand to our 2-addr instruction, the instruction would modify
670 // PhysReg. This isn't cool if something later uses PhysReg and expects
671 // to get its initial value.
Chris Lattner50ea01e2005-09-09 20:29:51 +0000672 //
Chris Lattneraddc55a2006-04-28 01:46:50 +0000673 // To avoid this problem, and to avoid doing a load right after a store,
674 // we emit a copy from PhysReg into the designated register for this
675 // operand.
676 unsigned DesignatedReg = VRM.getPhys(VirtReg);
677 assert(DesignatedReg && "Must map virtreg to physreg!");
678
679 // Note that, if we reused a register for a previous operand, the
680 // register we want to reload into might not actually be
681 // available. If this occurs, use the register indicated by the
682 // reuser.
683 if (ReusedOperands.hasReuses())
684 DesignatedReg = ReusedOperands.GetRegForReload(DesignatedReg, &MI,
685 Spills, MaybeDeadStores);
686
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000687 // If the mapped designated register is actually the physreg we have
688 // incoming, we don't need to inserted a dead copy.
689 if (DesignatedReg == PhysReg) {
690 // If this stack slot value is already available, reuse it!
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000691 DOUT << "Reusing SS#" << StackSlot << " from physreg "
692 << MRI->getName(PhysReg) << " for vreg"
693 << VirtReg
694 << " instead of reloading into same physreg.\n";
Chris Lattnere53f4a02006-05-04 17:52:23 +0000695 MI.getOperand(i).setReg(PhysReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000696 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerba1fc3d2006-04-28 04:43:18 +0000697 ++NumReused;
698 continue;
699 }
700
Chris Lattneraddc55a2006-04-28 01:46:50 +0000701 const TargetRegisterClass* RC =
702 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
703
704 PhysRegsUsed[DesignatedReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000705 ReusedOperands.markClobbered(DesignatedReg);
Chris Lattneraddc55a2006-04-28 01:46:50 +0000706 MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC);
707
708 // This invalidates DesignatedReg.
709 Spills.ClobberPhysReg(DesignatedReg);
710
711 Spills.addAvailable(StackSlot, DesignatedReg);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000712 MI.getOperand(i).setReg(DesignatedReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000713 DOUT << '\t' << *prior(MII);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000714 ++NumReused;
715 continue;
716 }
717
718 // Otherwise, reload it and remember that we have it.
719 PhysReg = VRM.getPhys(VirtReg);
Chris Lattner172c3622006-01-04 06:47:48 +0000720 assert(PhysReg && "Must map virtreg to physreg!");
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000721 const TargetRegisterClass* RC =
722 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000723
Chris Lattner50ea01e2005-09-09 20:29:51 +0000724 // Note that, if we reused a register for a previous operand, the
725 // register we want to reload into might not actually be
726 // available. If this occurs, use the register indicated by the
727 // reuser.
Chris Lattner540fec62006-02-25 01:51:33 +0000728 if (ReusedOperands.hasReuses())
729 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
730 Spills, MaybeDeadStores);
731
Chris Lattner50ea01e2005-09-09 20:29:51 +0000732 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000733 ReusedOperands.markClobbered(PhysReg);
Chris Lattnerbf9716b2005-09-30 01:29:00 +0000734 MRI->loadRegFromStackSlot(MBB, &MI, PhysReg, StackSlot, RC);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000735 // This invalidates PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000736 Spills.ClobberPhysReg(PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000737
738 // Any stores to this stack slot are not dead anymore.
739 MaybeDeadStores.erase(StackSlot);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000740 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner50ea01e2005-09-09 20:29:51 +0000741 ++NumLoads;
Chris Lattnere53f4a02006-05-04 17:52:23 +0000742 MI.getOperand(i).setReg(PhysReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000743 DOUT << '\t' << *prior(MII);
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000744 }
745
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000746 DOUT << '\t' << MI;
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000747
Chris Lattner7fb64342004-10-01 19:04:51 +0000748 // If we have folded references to memory operands, make sure we clear all
749 // physical registers that may contain the value of the spilled virtual
750 // register
Chris Lattner8f1d6402005-01-14 15:54:24 +0000751 VirtRegMap::MI2VirtMapTy::const_iterator I, End;
752 for (tie(I, End) = VRM.getFoldedVirts(&MI); I != End; ++I) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000753 DOUT << "Folded vreg: " << I->second.first << " MR: "
754 << I->second.second;
Chris Lattnerbec6a9e2004-10-01 23:15:36 +0000755 unsigned VirtReg = I->second.first;
756 VirtRegMap::ModRef MR = I->second.second;
Chris Lattnercea86882005-09-19 06:56:21 +0000757 if (!VRM.hasStackSlot(VirtReg)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000758 DOUT << ": No stack slot!\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000759 continue;
760 }
761 int SS = VRM.getStackSlot(VirtReg);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000762 DOUT << " - StackSlot: " << SS << "\n";
Chris Lattnercea86882005-09-19 06:56:21 +0000763
764 // If this folded instruction is just a use, check to see if it's a
765 // straight load from the virt reg slot.
766 if ((MR & VirtRegMap::isRef) && !(MR & VirtRegMap::isMod)) {
767 int FrameIdx;
Chris Lattner40839602006-02-02 20:12:32 +0000768 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
Chris Lattner6ec36262006-10-12 17:45:38 +0000769 if (FrameIdx == SS) {
770 // If this spill slot is available, turn it into a copy (or nothing)
771 // instead of leaving it as a load!
772 if (unsigned InReg = Spills.getSpillSlotPhysReg(SS)) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000773 DOUT << "Promoted Load To Copy: " << MI;
Chris Lattner6ec36262006-10-12 17:45:38 +0000774 MachineFunction &MF = *MBB.getParent();
775 if (DestReg != InReg) {
776 MRI->copyRegToReg(MBB, &MI, DestReg, InReg,
777 MF.getSSARegMap()->getRegClass(VirtReg));
778 // Revisit the copy so we make sure to notice the effects of the
779 // operation on the destreg (either needing to RA it if it's
780 // virtual or needing to clobber any values if it's physical).
781 NextMII = &MI;
782 --NextMII; // backtrack to the copy.
783 }
784 VRM.RemoveFromFoldedVirtMap(&MI);
785 MBB.erase(&MI);
786 goto ProcessNextInst;
Chris Lattnercea86882005-09-19 06:56:21 +0000787 }
Chris Lattnercea86882005-09-19 06:56:21 +0000788 }
789 }
790 }
791
792 // If this reference is not a use, any previous store is now dead.
793 // Otherwise, the store to this stack slot is not dead anymore.
794 std::map<int, MachineInstr*>::iterator MDSI = MaybeDeadStores.find(SS);
795 if (MDSI != MaybeDeadStores.end()) {
796 if (MR & VirtRegMap::isRef) // Previous store is not dead.
797 MaybeDeadStores.erase(MDSI);
798 else {
799 // If we get here, the store is dead, nuke it now.
Chris Lattner35f27052006-05-01 21:16:03 +0000800 assert(VirtRegMap::isMod && "Can't be modref!");
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000801 DOUT << "Removed dead store:\t" << *MDSI->second;
Chris Lattner35f27052006-05-01 21:16:03 +0000802 MBB.erase(MDSI->second);
Chris Lattner229924a2006-05-01 22:03:24 +0000803 VRM.RemoveFromFoldedVirtMap(MDSI->second);
Chris Lattner35f27052006-05-01 21:16:03 +0000804 MaybeDeadStores.erase(MDSI);
805 ++NumDSE;
Chris Lattnercea86882005-09-19 06:56:21 +0000806 }
807 }
808
809 // If the spill slot value is available, and this is a new definition of
810 // the value, the value is not available anymore.
811 if (MR & VirtRegMap::isMod) {
Chris Lattner07cf1412006-02-03 00:36:31 +0000812 // Notice that the value in this stack slot has been modified.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000813 Spills.ModifyStackSlot(SS);
Chris Lattnercd816392006-02-02 23:29:36 +0000814
815 // If this is *just* a mod of the value, check to see if this is just a
816 // store to the spill slot (i.e. the spill got merged into the copy). If
817 // so, realize that the vreg is available now, and add the store to the
818 // MaybeDeadStore info.
819 int StackSlot;
820 if (!(MR & VirtRegMap::isRef)) {
821 if (unsigned SrcReg = TII->isStoreToStackSlot(&MI, StackSlot)) {
822 assert(MRegisterInfo::isPhysicalRegister(SrcReg) &&
823 "Src hasn't been allocated yet?");
Chris Lattner07cf1412006-02-03 00:36:31 +0000824 // Okay, this is certainly a store of SrcReg to [StackSlot]. Mark
Chris Lattnercd816392006-02-02 23:29:36 +0000825 // this as a potentially dead store in case there is a subsequent
826 // store into the stack slot without a read from it.
827 MaybeDeadStores[StackSlot] = &MI;
828
Chris Lattnercd816392006-02-02 23:29:36 +0000829 // If the stack slot value was previously available in some other
830 // register, change it now. Otherwise, make the register available,
831 // in PhysReg.
Chris Lattner593c9582006-02-03 23:28:46 +0000832 Spills.addAvailable(StackSlot, SrcReg, false /*don't clobber*/);
Chris Lattnercd816392006-02-02 23:29:36 +0000833 }
834 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000835 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000836 }
837
Chris Lattner7fb64342004-10-01 19:04:51 +0000838 // Process all of the spilled defs.
839 for (unsigned i = 0, e = MI.getNumOperands(); i != e; ++i) {
840 MachineOperand &MO = MI.getOperand(i);
841 if (MO.isRegister() && MO.getReg() && MO.isDef()) {
842 unsigned VirtReg = MO.getReg();
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000843
Chris Lattner7fb64342004-10-01 19:04:51 +0000844 if (!MRegisterInfo::isVirtualRegister(VirtReg)) {
Chris Lattner29268692006-09-05 02:12:02 +0000845 // Check to see if this is a noop copy. If so, eliminate the
846 // instruction before considering the dest reg to be changed.
847 unsigned Src, Dst;
848 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
849 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000850 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner29268692006-09-05 02:12:02 +0000851 MBB.erase(&MI);
852 VRM.RemoveFromFoldedVirtMap(&MI);
Evan Cheng7a0d51c2006-12-14 07:54:05 +0000853 Spills.disallowClobberPhysReg(VirtReg);
Chris Lattner29268692006-09-05 02:12:02 +0000854 goto ProcessNextInst;
Chris Lattner7fb64342004-10-01 19:04:51 +0000855 }
Chris Lattner6ec36262006-10-12 17:45:38 +0000856
857 // If it's not a no-op copy, it clobbers the value in the destreg.
Chris Lattner29268692006-09-05 02:12:02 +0000858 Spills.ClobberPhysReg(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000859 ReusedOperands.markClobbered(VirtReg);
Chris Lattner6ec36262006-10-12 17:45:38 +0000860
861 // Check to see if this instruction is a load from a stack slot into
862 // a register. If so, this provides the stack slot value in the reg.
863 int FrameIdx;
864 if (unsigned DestReg = TII->isLoadFromStackSlot(&MI, FrameIdx)) {
865 assert(DestReg == VirtReg && "Unknown load situation!");
866
867 // Otherwise, if it wasn't available, remember that it is now!
868 Spills.addAvailable(FrameIdx, DestReg);
869 goto ProcessNextInst;
870 }
871
Chris Lattner29268692006-09-05 02:12:02 +0000872 continue;
Misha Brukmanedf128a2005-04-21 22:36:52 +0000873 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000874
Chris Lattner84e752a2006-02-03 03:06:49 +0000875 // The only vregs left are stack slot definitions.
876 int StackSlot = VRM.getStackSlot(VirtReg);
877 const TargetRegisterClass *RC =
878 MBB.getParent()->getSSARegMap()->getRegClass(VirtReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000879
Chris Lattner29268692006-09-05 02:12:02 +0000880 // If this def is part of a two-address operand, make sure to execute
881 // the store from the correct physical register.
882 unsigned PhysReg;
Evan Chengcc22a7a2006-12-08 18:45:48 +0000883 int TiedOp = MI.getInstrDescriptor()->findTiedToSrcOperand(i);
Evan Cheng360c2dd2006-11-01 23:06:55 +0000884 if (TiedOp != -1)
885 PhysReg = MI.getOperand(TiedOp).getReg();
Evan Chenge077ef62006-11-04 00:21:55 +0000886 else {
Chris Lattner29268692006-09-05 02:12:02 +0000887 PhysReg = VRM.getPhys(VirtReg);
Evan Chenge077ef62006-11-04 00:21:55 +0000888 if (ReusedOperands.isClobbered(PhysReg)) {
889 // Another def has taken the assigned physreg. It must have been a
890 // use&def which got it due to reuse. Undo the reuse!
891 PhysReg = ReusedOperands.GetRegForReload(PhysReg, &MI,
892 Spills, MaybeDeadStores);
893 }
894 }
Chris Lattner7fb64342004-10-01 19:04:51 +0000895
Chris Lattner84e752a2006-02-03 03:06:49 +0000896 PhysRegsUsed[PhysReg] = true;
Evan Chenge077ef62006-11-04 00:21:55 +0000897 ReusedOperands.markClobbered(PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000898 MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000899 DOUT << "Store:\t" << *next(MII);
Chris Lattnere53f4a02006-05-04 17:52:23 +0000900 MI.getOperand(i).setReg(PhysReg);
Chris Lattner7fb64342004-10-01 19:04:51 +0000901
Chris Lattner109afed2006-02-03 03:16:14 +0000902 // Check to see if this is a noop copy. If so, eliminate the
903 // instruction before considering the dest reg to be changed.
904 {
905 unsigned Src, Dst;
906 if (TII->isMoveInstr(MI, Src, Dst) && Src == Dst) {
907 ++NumDCE;
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000908 DOUT << "Removing now-noop copy: " << MI;
Chris Lattner109afed2006-02-03 03:16:14 +0000909 MBB.erase(&MI);
Chris Lattner229924a2006-05-01 22:03:24 +0000910 VRM.RemoveFromFoldedVirtMap(&MI);
Chris Lattner109afed2006-02-03 03:16:14 +0000911 goto ProcessNextInst;
912 }
913 }
914
Chris Lattner84e752a2006-02-03 03:06:49 +0000915 // If there is a dead store to this stack slot, nuke it now.
916 MachineInstr *&LastStore = MaybeDeadStores[StackSlot];
917 if (LastStore) {
Bill Wendlingb2b9c202006-11-17 02:09:07 +0000918 DOUT << "Removed dead store:\t" << *LastStore;
Chris Lattner84e752a2006-02-03 03:06:49 +0000919 ++NumDSE;
920 MBB.erase(LastStore);
Chris Lattner229924a2006-05-01 22:03:24 +0000921 VRM.RemoveFromFoldedVirtMap(LastStore);
Chris Lattner7fb64342004-10-01 19:04:51 +0000922 }
Chris Lattner84e752a2006-02-03 03:06:49 +0000923 LastStore = next(MII);
924
925 // If the stack slot value was previously available in some other
926 // register, change it now. Otherwise, make the register available,
927 // in PhysReg.
Chris Lattner66cf80f2006-02-03 23:13:58 +0000928 Spills.ModifyStackSlot(StackSlot);
929 Spills.ClobberPhysReg(PhysReg);
Chris Lattner66cf80f2006-02-03 23:13:58 +0000930 Spills.addAvailable(StackSlot, PhysReg);
Chris Lattner84e752a2006-02-03 03:06:49 +0000931 ++NumStores;
Chris Lattner7fb64342004-10-01 19:04:51 +0000932 }
933 }
Chris Lattnercea86882005-09-19 06:56:21 +0000934 ProcessNextInst:
Chris Lattner7fb64342004-10-01 19:04:51 +0000935 MII = NextMII;
936 }
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000937}
938
Chris Lattnerf7da2c72006-08-24 22:43:55 +0000939
940
Chris Lattner8c4d88d2004-09-30 01:54:45 +0000941llvm::Spiller* llvm::createSpiller() {
942 switch (SpillerOpt) {
943 default: assert(0 && "Unreachable!");
944 case local:
945 return new LocalSpiller();
946 case simple:
947 return new SimpleSpiller();
948 }
Alkis Evlogimenos0d6c5b62004-02-24 08:58:30 +0000949}