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gerrit-public.fairphone.software / kernel / msm-4.19 / 0987a6ef94238097a380aa5e8a69a74393baa5be / . / arch / arm / boot / dts / am33xx.dtsi
blob: d1e2b363f9272f931321a75694235873e85aaf7f [file] [log] [blame]
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]1/*
2 * Device Tree Source for AM33XX SoC
3 *
4 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/
5 *
6 * This file is licensed under the terms of the GNU General Public License
7 * version 2. This program is licensed "as is" without any warranty of any
8 * kind, whether express or implied.
9 */
10
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]11#include <dt-bindings/gpio/gpio.h>
Florian Vaussard6a8a6b62013-06-03 16:12:25 +0200[diff] [blame]12#include <dt-bindings/pinctrl/am33xx.h>
Florian Vaussarde94233c2013-06-03 16:12:23 +0200[diff] [blame]13
Florian Vaussardeb33ef662013-06-03 16:12:22 +0200[diff] [blame]14#include "skeleton.dtsi"
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]15
16/ {
17 compatible = "ti,am33xx";
Benoit Cousson4c94ac22012-10-24 10:47:52 +0200[diff] [blame]18 interrupt-parent = <&intc>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]19
20 aliases {
Nishanth Menon6a968672013-10-16 15:21:04 -0500[diff] [blame]21 i2c0 = &i2c0;
22 i2c1 = &i2c1;
23 i2c2 = &i2c2;
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]24 serial0 = &uart0;
25 serial1 = &uart1;
26 serial2 = &uart2;
27 serial3 = &uart3;
28 serial4 = &uart4;
29 serial5 = &uart5;
AnilKumar Ch7a57ee82012-11-14 23:38:24 +0530[diff] [blame]30 d_can0 = &dcan0;
31 d_can1 = &dcan1;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]32 usb0 = &usb0;
33 usb1 = &usb1;
34 phy0 = &usb0_phy;
35 phy1 = &usb1_phy;
Dan Murphy81700562013-10-02 12:58:33 -0500[diff] [blame]36 ethernet0 = &cpsw_emac0;
37 ethernet1 = &cpsw_emac1;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]38 };
39
40 cpus {
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]41 #address-cells = <1>;
42 #size-cells = <0>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]43 cpu@0 {
44 compatible = "arm,cortex-a8";
Lorenzo Pieralisi2e0d5132013-04-18 18:35:59 +0100[diff] [blame]45 device_type = "cpu";
46 reg = <0>;
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]47
48 /*
49 * To consider voltage drop between PMIC and SoC,
50 * tolerance value is reduced to 2% from 4% and
51 * voltage value is increased as a precaution.
52 */
53 operating-points = <
54 /* kHz uV */
55 720000 1285000
56 600000 1225000
57 500000 1125000
58 275000 1125000
59 >;
60 voltage-tolerance = <2>; /* 2 percentage */
Nishanth Menon8d766fa2014-01-29 12:19:17 -0600[diff] [blame]61
62 clocks = <&dpll_mpu_ck>;
63 clock-names = "cpu";
64
AnilKumar Chefeedcf22012-08-31 15:07:20 +0530[diff] [blame]65 clock-latency = <300000>; /* From omap-cpufreq driver */
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]66 };
67 };
68
Alexandre Belloni6797cdb2013-08-03 20:00:54 +0200[diff] [blame]69 pmu {
70 compatible = "arm,cortex-a8-pmu";
71 interrupts = <3>;
72 };
73
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]74 /*
75 * The soc node represents the soc top level view. It is uses for IPs
76 * that are not memory mapped in the MPU view or for the MPU itself.
77 */
78 soc {
79 compatible = "ti,omap-infra";
80 mpu {
81 compatible = "ti,omap3-mpu";
82 ti,hwmods = "mpu";
83 };
84 };
85
AnilKumar Chb552dfc2012-09-20 02:49:26 +0530[diff] [blame]86 am33xx_pinmux: pinmux@44e10800 {
87 compatible = "pinctrl-single";
88 reg = <0x44e10800 0x0238>;
89 #address-cells = <1>;
90 #size-cells = <0>;
91 pinctrl-single,register-width = <32>;
92 pinctrl-single,function-mask = <0x7f>;
93 };
94
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]95 /*
96 * XXX: Use a flat representation of the AM33XX interconnect.
97 * The real AM33XX interconnect network is quite complex.Since
98 * that will not bring real advantage to represent that in DT
99 * for the moment, just use a fake OCP bus entry to represent
100 * the whole bus hierarchy.
101 */
102 ocp {
103 compatible = "simple-bus";
104 #address-cells = <1>;
105 #size-cells = <1>;
106 ranges;
107 ti,hwmods = "l3_main";
108
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]109 prcm: prcm@44e00000 {
110 compatible = "ti,am3-prcm";
111 reg = <0x44e00000 0x4000>;
112
113 prcm_clocks: clocks {
114 #address-cells = <1>;
115 #size-cells = <0>;
116 };
117
118 prcm_clockdomains: clockdomains {
119 };
120 };
121
122 scrm: scrm@44e10000 {
123 compatible = "ti,am3-scrm";
124 reg = <0x44e10000 0x2000>;
125
126 scrm_clocks: clocks {
127 #address-cells = <1>;
128 #size-cells = <0>;
129 };
130
131 scrm_clockdomains: clockdomains {
132 };
133 };
134
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]135 intc: interrupt-controller@48200000 {
136 compatible = "ti,omap2-intc";
137 interrupt-controller;
138 #interrupt-cells = <1>;
139 ti,intc-size = <128>;
140 reg = <0x48200000 0x1000>;
141 };
142
Matt Porter505975d2013-09-10 14:24:37 -0500[diff] [blame]143 edma: edma@49000000 {
144 compatible = "ti,edma3";
145 ti,hwmods = "tpcc", "tptc0", "tptc1", "tptc2";
146 reg = <0x49000000 0x10000>,
147 <0x44e10f90 0x10>;
148 interrupts = <12 13 14>;
149 #dma-cells = <1>;
150 dma-channels = <64>;
151 ti,edma-regions = <4>;
152 ti,edma-slots = <256>;
153 };
154
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]155 gpio0: gpio@44e07000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]156 compatible = "ti,omap4-gpio";
157 ti,hwmods = "gpio1";
158 gpio-controller;
159 #gpio-cells = <2>;
160 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]161 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]162 reg = <0x44e07000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]163 interrupts = <96>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]164 };
165
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]166 gpio1: gpio@4804c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]167 compatible = "ti,omap4-gpio";
168 ti,hwmods = "gpio2";
169 gpio-controller;
170 #gpio-cells = <2>;
171 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]172 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]173 reg = <0x4804c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]174 interrupts = <98>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]175 };
176
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]177 gpio2: gpio@481ac000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]178 compatible = "ti,omap4-gpio";
179 ti,hwmods = "gpio3";
180 gpio-controller;
181 #gpio-cells = <2>;
182 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]183 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]184 reg = <0x481ac000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]185 interrupts = <32>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]186 };
187
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]188 gpio3: gpio@481ae000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]189 compatible = "ti,omap4-gpio";
190 ti,hwmods = "gpio4";
191 gpio-controller;
192 #gpio-cells = <2>;
193 interrupt-controller;
Lars Poeschel5eac0eb2013-08-07 13:06:32 +0200[diff] [blame]194 #interrupt-cells = <2>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]195 reg = <0x481ae000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]196 interrupts = <62>;
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]197 };
198
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]199 uart0: serial@44e09000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]200 compatible = "ti,omap3-uart";
201 ti,hwmods = "uart1";
202 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]203 reg = <0x44e09000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]204 interrupts = <72>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]205 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]206 };
207
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]208 uart1: serial@48022000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]209 compatible = "ti,omap3-uart";
210 ti,hwmods = "uart2";
211 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]212 reg = <0x48022000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]213 interrupts = <73>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]214 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]215 };
216
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]217 uart2: serial@48024000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]218 compatible = "ti,omap3-uart";
219 ti,hwmods = "uart3";
220 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]221 reg = <0x48024000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]222 interrupts = <74>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]223 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]224 };
225
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]226 uart3: serial@481a6000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]227 compatible = "ti,omap3-uart";
228 ti,hwmods = "uart4";
229 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]230 reg = <0x481a6000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]231 interrupts = <44>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]232 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]233 };
234
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]235 uart4: serial@481a8000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]236 compatible = "ti,omap3-uart";
237 ti,hwmods = "uart5";
238 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]239 reg = <0x481a8000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]240 interrupts = <45>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]241 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]242 };
243
Vaibhav Hiremathdde3b0d2013-03-28 11:36:05 +0530[diff] [blame]244 uart5: serial@481aa000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]245 compatible = "ti,omap3-uart";
246 ti,hwmods = "uart6";
247 clock-frequency = <48000000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]248 reg = <0x481aa000 0x2000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]249 interrupts = <46>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]250 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]251 };
252
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]253 i2c0: i2c@44e0b000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]254 compatible = "ti,omap4-i2c";
255 #address-cells = <1>;
256 #size-cells = <0>;
257 ti,hwmods = "i2c1";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]258 reg = <0x44e0b000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]259 interrupts = <70>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]260 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]261 };
262
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]263 i2c1: i2c@4802a000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]264 compatible = "ti,omap4-i2c";
265 #address-cells = <1>;
266 #size-cells = <0>;
267 ti,hwmods = "i2c2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]268 reg = <0x4802a000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]269 interrupts = <71>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]270 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]271 };
272
AnilKumar Chb918e2c2012-11-21 17:22:17 +0530[diff] [blame]273 i2c2: i2c@4819c000 {
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]274 compatible = "ti,omap4-i2c";
275 #address-cells = <1>;
276 #size-cells = <0>;
277 ti,hwmods = "i2c3";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]278 reg = <0x4819c000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]279 interrupts = <30>;
Vaibhav Hiremath53d91032012-08-15 16:53:25 +0530[diff] [blame]280 status = "disabled";
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]281 };
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]282
Matt Porter55b44522013-09-10 14:24:39 -0500[diff] [blame]283 mmc1: mmc@48060000 {
284 compatible = "ti,omap4-hsmmc";
285 ti,hwmods = "mmc1";
286 ti,dual-volt;
287 ti,needs-special-reset;
288 ti,needs-special-hs-handling;
289 dmas = <&edma 24
290 &edma 25>;
291 dma-names = "tx", "rx";
292 interrupts = <64>;
293 interrupt-parent = <&intc>;
294 reg = <0x48060000 0x1000>;
295 status = "disabled";
296 };
297
298 mmc2: mmc@481d8000 {
299 compatible = "ti,omap4-hsmmc";
300 ti,hwmods = "mmc2";
301 ti,needs-special-reset;
302 dmas = <&edma 2
303 &edma 3>;
304 dma-names = "tx", "rx";
305 interrupts = <28>;
306 interrupt-parent = <&intc>;
307 reg = <0x481d8000 0x1000>;
308 status = "disabled";
309 };
310
311 mmc3: mmc@47810000 {
312 compatible = "ti,omap4-hsmmc";
313 ti,hwmods = "mmc3";
314 ti,needs-special-reset;
315 interrupts = <29>;
316 interrupt-parent = <&intc>;
317 reg = <0x47810000 0x1000>;
318 status = "disabled";
319 };
320
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]321 hwspinlock: spinlock@480ca000 {
322 compatible = "ti,omap4-hwspinlock";
323 reg = <0x480ca000 0x1000>;
324 ti,hwmods = "spinlock";
Suman Anna34054212014-01-13 18:26:45 -0600[diff] [blame]325 #hwlock-cells = <1>;
Suman Annad4cbe802013-10-10 16:15:35 -0500[diff] [blame]326 };
327
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]328 wdt2: wdt@44e35000 {
329 compatible = "ti,omap3-wdt";
330 ti,hwmods = "wd_timer2";
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]331 reg = <0x44e35000 0x1000>;
Vaibhav Hiremath4462b312012-08-27 17:21:01 +0530[diff] [blame]332 interrupts = <91>;
Afzal Mohammed5f789eb2012-07-04 18:00:37 +0530[diff] [blame]333 };
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]334
335 dcan0: d_can@481cc000 {
336 compatible = "bosch,d_can";
337 ti,hwmods = "d_can0";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]338 reg = <0x481cc000 0x2000
339 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]340 interrupts = <52>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]341 status = "disabled";
342 };
343
344 dcan1: d_can@481d0000 {
345 compatible = "bosch,d_can";
346 ti,hwmods = "d_can1";
AnilKumar Chf178c012012-11-14 23:38:25 +0530[diff] [blame]347 reg = <0x481d0000 0x2000
348 0x44e10644 0x4>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]349 interrupts = <55>;
AnilKumar Ch059b1852012-09-20 02:49:27 +0530[diff] [blame]350 status = "disabled";
351 };
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]352
353 timer1: timer@44e31000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]354 compatible = "ti,am335x-timer-1ms";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]355 reg = <0x44e31000 0x400>;
356 interrupts = <67>;
357 ti,hwmods = "timer1";
358 ti,timer-alwon;
359 };
360
361 timer2: timer@48040000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]362 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]363 reg = <0x48040000 0x400>;
364 interrupts = <68>;
365 ti,hwmods = "timer2";
366 };
367
368 timer3: timer@48042000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]369 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]370 reg = <0x48042000 0x400>;
371 interrupts = <69>;
372 ti,hwmods = "timer3";
373 };
374
375 timer4: timer@48044000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]376 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]377 reg = <0x48044000 0x400>;
378 interrupts = <92>;
379 ti,hwmods = "timer4";
380 ti,timer-pwm;
381 };
382
383 timer5: timer@48046000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]384 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]385 reg = <0x48046000 0x400>;
386 interrupts = <93>;
387 ti,hwmods = "timer5";
388 ti,timer-pwm;
389 };
390
391 timer6: timer@48048000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]392 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]393 reg = <0x48048000 0x400>;
394 interrupts = <94>;
395 ti,hwmods = "timer6";
396 ti,timer-pwm;
397 };
398
399 timer7: timer@4804a000 {
Jon Hunter002e1ec2013-03-19 12:38:18 -0500[diff] [blame]400 compatible = "ti,am335x-timer";
Jon Hunterfab8ad02012-10-19 09:59:00 -0500[diff] [blame]401 reg = <0x4804a000 0x400>;
402 interrupts = <95>;
403 ti,hwmods = "timer7";
404 ti,timer-pwm;
405 };
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]406
Stefan Roeseccd8b9e2014-02-05 13:12:39 +0100[diff] [blame]407 rtc: rtc@44e3e000 {
Afzal Mohammed0d935c12012-10-30 15:04:01 +0530[diff] [blame]408 compatible = "ti,da830-rtc";
409 reg = <0x44e3e000 0x1000>;
410 interrupts = <75
411 76>;
412 ti,hwmods = "rtc";
413 };
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]414
415 spi0: spi@48030000 {
416 compatible = "ti,omap4-mcspi";
417 #address-cells = <1>;
418 #size-cells = <0>;
419 reg = <0x48030000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]420 interrupts = <65>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]421 ti,spi-num-cs = <2>;
422 ti,hwmods = "spi0";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]423 dmas = <&edma 16
424 &edma 17
425 &edma 18
426 &edma 19>;
427 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]428 status = "disabled";
429 };
430
431 spi1: spi@481a0000 {
432 compatible = "ti,omap4-mcspi";
433 #address-cells = <1>;
434 #size-cells = <0>;
435 reg = <0x481a0000 0x400>;
Philip Avinash7b3754c2013-02-01 11:07:27 +0530[diff] [blame]436 interrupts = <125>;
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]437 ti,spi-num-cs = <2>;
438 ti,hwmods = "spi1";
Matt Porterf5e2f802013-09-10 14:24:38 -0500[diff] [blame]439 dmas = <&edma 42
440 &edma 43
441 &edma 44
442 &edma 45>;
443 dma-names = "tx0", "rx0", "tx1", "rx1";
Philip, Avinash9fd3c742012-10-31 16:21:09 +0530[diff] [blame]444 status = "disabled";
445 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]446
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]447 usb: usb@47400000 {
448 compatible = "ti,am33xx-usb";
449 reg = <0x47400000 0x1000>;
450 ranges;
451 #address-cells = <1>;
452 #size-cells = <1>;
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]453 ti,hwmods = "usb_otg_hs";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]454 status = "disabled";
455
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]456 usb_ctrl_mod: control@44e10620 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]457 compatible = "ti,am335x-usb-ctrl-module";
458 reg = <0x44e10620 0x10
459 0x44e10648 0x4>;
460 reg-names = "phy_ctrl", "wakeup";
461 status = "disabled";
462 };
463
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]464 usb0_phy: usb-phy@47401300 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]465 compatible = "ti,am335x-usb-phy";
466 reg = <0x47401300 0x100>;
467 reg-names = "phy";
468 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]469 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]470 };
471
472 usb0: usb@47401000 {
473 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]474 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]475 reg = <0x47401400 0x400
476 0x47401000 0x200>;
477 reg-names = "mc", "control";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]478
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]479 interrupts = <18>;
480 interrupt-names = "mc";
481 dr_mode = "otg";
482 mentor,multipoint = <1>;
483 mentor,num-eps = <16>;
484 mentor,ram-bits = <12>;
485 mentor,power = <500>;
486 phys = <&usb0_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]487
488 dmas = <&cppi41dma 0 0 &cppi41dma 1 0
489 &cppi41dma 2 0 &cppi41dma 3 0
490 &cppi41dma 4 0 &cppi41dma 5 0
491 &cppi41dma 6 0 &cppi41dma 7 0
492 &cppi41dma 8 0 &cppi41dma 9 0
493 &cppi41dma 10 0 &cppi41dma 11 0
494 &cppi41dma 12 0 &cppi41dma 13 0
495 &cppi41dma 14 0 &cppi41dma 0 1
496 &cppi41dma 1 1 &cppi41dma 2 1
497 &cppi41dma 3 1 &cppi41dma 4 1
498 &cppi41dma 5 1 &cppi41dma 6 1
499 &cppi41dma 7 1 &cppi41dma 8 1
500 &cppi41dma 9 1 &cppi41dma 10 1
501 &cppi41dma 11 1 &cppi41dma 12 1
502 &cppi41dma 13 1 &cppi41dma 14 1>;
503 dma-names =
504 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
505 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
506 "rx14", "rx15",
507 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
508 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
509 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]510 };
511
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]512 usb1_phy: usb-phy@47401b00 {
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]513 compatible = "ti,am335x-usb-phy";
514 reg = <0x47401b00 0x100>;
515 reg-names = "phy";
516 status = "disabled";
Markus Pargmanne7243b72013-10-14 14:49:21 +0200[diff] [blame]517 ti,ctrl_mod = <&usb_ctrl_mod>;
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]518 };
519
520 usb1: usb@47401800 {
521 compatible = "ti,musb-am33xx";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]522 status = "disabled";
Sebastian Andrzej Siewiorc031a7d2013-08-20 18:35:47 +0200[diff] [blame]523 reg = <0x47401c00 0x400
524 0x47401800 0x200>;
525 reg-names = "mc", "control";
526 interrupts = <19>;
527 interrupt-names = "mc";
528 dr_mode = "otg";
529 mentor,multipoint = <1>;
530 mentor,num-eps = <16>;
531 mentor,ram-bits = <12>;
532 mentor,power = <500>;
533 phys = <&usb1_phy>;
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]534
535 dmas = <&cppi41dma 15 0 &cppi41dma 16 0
536 &cppi41dma 17 0 &cppi41dma 18 0
537 &cppi41dma 19 0 &cppi41dma 20 0
538 &cppi41dma 21 0 &cppi41dma 22 0
539 &cppi41dma 23 0 &cppi41dma 24 0
540 &cppi41dma 25 0 &cppi41dma 26 0
541 &cppi41dma 27 0 &cppi41dma 28 0
542 &cppi41dma 29 0 &cppi41dma 15 1
543 &cppi41dma 16 1 &cppi41dma 17 1
544 &cppi41dma 18 1 &cppi41dma 19 1
545 &cppi41dma 20 1 &cppi41dma 21 1
546 &cppi41dma 22 1 &cppi41dma 23 1
547 &cppi41dma 24 1 &cppi41dma 25 1
548 &cppi41dma 26 1 &cppi41dma 27 1
549 &cppi41dma 28 1 &cppi41dma 29 1>;
550 dma-names =
551 "rx1", "rx2", "rx3", "rx4", "rx5", "rx6", "rx7",
552 "rx8", "rx9", "rx10", "rx11", "rx12", "rx13",
553 "rx14", "rx15",
554 "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7",
555 "tx8", "tx9", "tx10", "tx11", "tx12", "tx13",
556 "tx14", "tx15";
Sebastian Andrzej Siewior97238b32013-07-05 14:51:33 +0200[diff] [blame]557 };
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]558
Mugunthan V N8abcdd62014-03-06 18:01:34 +0530[diff] [blame]559 cppi41dma: dma-controller@47402000 {
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]560 compatible = "ti,am3359-cppi41";
561 reg = <0x47400000 0x1000
562 0x47402000 0x1000
563 0x47403000 0x1000
564 0x47404000 0x4000>;
Sebastian Andrzej Siewior3b6394b2013-08-20 18:35:45 +0200[diff] [blame]565 reg-names = "glue", "controller", "scheduler", "queuemgr";
Sebastian Andrzej Siewior9b3452d2013-06-20 12:13:04 +0200[diff] [blame]566 interrupts = <17>;
567 interrupt-names = "glue";
568 #dma-cells = <2>;
569 #dma-channels = <30>;
570 #dma-requests = <256>;
571 status = "disabled";
572 };
Ajay Kumar Gupta35b47fb2012-11-06 19:59:38 +0530[diff] [blame]573 };
Linus Torvalds6be35c72012-12-12 18:07:07 -0800[diff] [blame]574
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]575 epwmss0: epwmss@48300000 {
576 compatible = "ti,am33xx-pwmss";
577 reg = <0x48300000 0x10>;
578 ti,hwmods = "epwmss0";
579 #address-cells = <1>;
580 #size-cells = <1>;
581 status = "disabled";
582 ranges = <0x48300100 0x48300100 0x80 /* ECAP */
583 0x48300180 0x48300180 0x80 /* EQEP */
584 0x48300200 0x48300200 0x80>; /* EHRPWM */
585
586 ecap0: ecap@48300100 {
587 compatible = "ti,am33xx-ecap";
588 #pwm-cells = <3>;
589 reg = <0x48300100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]590 interrupts = <31>;
591 interrupt-names = "ecap0";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]592 ti,hwmods = "ecap0";
593 status = "disabled";
594 };
595
596 ehrpwm0: ehrpwm@48300200 {
597 compatible = "ti,am33xx-ehrpwm";
598 #pwm-cells = <3>;
599 reg = <0x48300200 0x80>;
600 ti,hwmods = "ehrpwm0";
601 status = "disabled";
602 };
603 };
604
605 epwmss1: epwmss@48302000 {
606 compatible = "ti,am33xx-pwmss";
607 reg = <0x48302000 0x10>;
608 ti,hwmods = "epwmss1";
609 #address-cells = <1>;
610 #size-cells = <1>;
611 status = "disabled";
612 ranges = <0x48302100 0x48302100 0x80 /* ECAP */
613 0x48302180 0x48302180 0x80 /* EQEP */
614 0x48302200 0x48302200 0x80>; /* EHRPWM */
615
616 ecap1: ecap@48302100 {
617 compatible = "ti,am33xx-ecap";
618 #pwm-cells = <3>;
619 reg = <0x48302100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]620 interrupts = <47>;
621 interrupt-names = "ecap1";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]622 ti,hwmods = "ecap1";
623 status = "disabled";
624 };
625
626 ehrpwm1: ehrpwm@48302200 {
627 compatible = "ti,am33xx-ehrpwm";
628 #pwm-cells = <3>;
629 reg = <0x48302200 0x80>;
630 ti,hwmods = "ehrpwm1";
631 status = "disabled";
632 };
633 };
634
635 epwmss2: epwmss@48304000 {
636 compatible = "ti,am33xx-pwmss";
637 reg = <0x48304000 0x10>;
638 ti,hwmods = "epwmss2";
639 #address-cells = <1>;
640 #size-cells = <1>;
641 status = "disabled";
642 ranges = <0x48304100 0x48304100 0x80 /* ECAP */
643 0x48304180 0x48304180 0x80 /* EQEP */
644 0x48304200 0x48304200 0x80>; /* EHRPWM */
645
646 ecap2: ecap@48304100 {
647 compatible = "ti,am33xx-ecap";
648 #pwm-cells = <3>;
649 reg = <0x48304100 0x80>;
Matt Portere8c85a32014-01-29 15:59:59 -0500[diff] [blame]650 interrupts = <61>;
651 interrupt-names = "ecap2";
Philip Avinash0a7486c2013-06-06 15:52:37 +0200[diff] [blame]652 ti,hwmods = "ecap2";
653 status = "disabled";
654 };
655
656 ehrpwm2: ehrpwm@48304200 {
657 compatible = "ti,am33xx-ehrpwm";
658 #pwm-cells = <3>;
659 reg = <0x48304200 0x80>;
660 ti,hwmods = "ehrpwm2";
661 status = "disabled";
662 };
663 };
664
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]665 mac: ethernet@4a100000 {
666 compatible = "ti,cpsw";
667 ti,hwmods = "cpgmac0";
George Cherian0987a6e2014-05-02 12:01:59 +0530[diff] [blame^]668 clocks = <&cpsw_125mhz_gclk>, <&cpsw_cpts_rft_clk>;
669 clock-names = "fck", "cpts";
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]670 cpdma_channels = <8>;
671 ale_entries = <1024>;
672 bd_ram_size = <0x2000>;
673 no_bd_ram = <0>;
674 rx_descs = <64>;
675 mac_control = <0x20>;
676 slaves = <2>;
Mugunthan V Ne86ac132013-03-11 23:16:35 +0000[diff] [blame]677 active_slave = <0>;
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]678 cpts_clock_mult = <0x80000000>;
679 cpts_clock_shift = <29>;
680 reg = <0x4a100000 0x800
681 0x4a101200 0x100>;
682 #address-cells = <1>;
683 #size-cells = <1>;
684 interrupt-parent = <&intc>;
685 /*
686 * c0_rx_thresh_pend
687 * c0_rx_pend
688 * c0_tx_pend
689 * c0_misc_pend
690 */
691 interrupts = <40 41 42 43>;
692 ranges;
693
694 davinci_mdio: mdio@4a101000 {
695 compatible = "ti,davinci_mdio";
696 #address-cells = <1>;
697 #size-cells = <0>;
698 ti,hwmods = "davinci_mdio";
699 bus_freq = <1000000>;
700 reg = <0x4a101000 0x100>;
701 };
702
703 cpsw_emac0: slave@4a100200 {
704 /* Filled in by U-Boot */
705 mac-address = [ 00 00 00 00 00 00 ];
706 };
707
708 cpsw_emac1: slave@4a100300 {
709 /* Filled in by U-Boot */
710 mac-address = [ 00 00 00 00 00 00 ];
711 };
Mugunthan V N39ffbd92013-09-21 00:50:41 +0530[diff] [blame]712
713 phy_sel: cpsw-phy-sel@44e10650 {
714 compatible = "ti,am3352-cpsw-phy-sel";
715 reg= <0x44e10650 0x4>;
716 reg-names = "gmii-sel";
717 };
Mugunthan V N1a39a652012-11-14 09:08:00 +0000[diff] [blame]718 };
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]719
720 ocmcram: ocmcram@40300000 {
721 compatible = "ti,am3352-ocmcram";
722 reg = <0x40300000 0x10000>;
723 ti,hwmods = "ocmcram";
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]724 };
725
726 wkup_m3: wkup_m3@44d00000 {
727 compatible = "ti,am3353-wkup-m3";
728 reg = <0x44d00000 0x4000 /* M3 UMEM */
729 0x44d80000 0x2000>; /* M3 DMEM */
730 ti,hwmods = "wkup_m3";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]731 ti,no-reset-on-init;
Vaibhav Bediaf6575c92013-01-29 16:45:07 +0530[diff] [blame]732 };
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]733
Philip, Avinash15e82462013-05-31 13:19:03 +0530[diff] [blame]734 elm: elm@48080000 {
735 compatible = "ti,am3352-elm";
736 reg = <0x48080000 0x2000>;
737 interrupts = <4>;
738 ti,hwmods = "elm";
739 status = "disabled";
740 };
741
Benoit Parrotd6cfc1e2013-08-08 18:28:14 -0500[diff] [blame]742 lcdc: lcdc@4830e000 {
743 compatible = "ti,am33xx-tilcdc";
744 reg = <0x4830e000 0x1000>;
745 interrupt-parent = <&intc>;
746 interrupts = <36>;
747 ti,hwmods = "lcdc";
748 status = "disabled";
749 };
750
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]751 tscadc: tscadc@44e0d000 {
752 compatible = "ti,am3359-tscadc";
753 reg = <0x44e0d000 0x1000>;
754 interrupt-parent = <&intc>;
755 interrupts = <16>;
756 ti,hwmods = "adc_tsc";
757 status = "disabled";
758
759 tsc {
760 compatible = "ti,am3359-tsc";
761 };
762 am335x_adc: adc {
763 #io-channel-cells = <1>;
764 compatible = "ti,am3359-adc";
765 };
Patil, Rachnaa82279d2013-01-24 03:45:12 +0000[diff] [blame]766 };
767
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]768 gpmc: gpmc@50000000 {
769 compatible = "ti,am3352-gpmc";
770 ti,hwmods = "gpmc";
Rajendra Nayakf12ecbe2013-10-15 12:37:50 +0530[diff] [blame]771 ti,no-idle-on-init;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]772 reg = <0x50000000 0x2000>;
773 interrupts = <100>;
Lars Poeschel00dddca2013-05-28 10:24:57 +0200[diff] [blame]774 gpmc,num-cs = <7>;
775 gpmc,num-waitpins = <2>;
Philip Avinashe45879e2013-05-02 15:14:03 +0530[diff] [blame]776 #address-cells = <2>;
777 #size-cells = <1>;
778 status = "disabled";
779 };
Mark A. Greerf8302e12013-08-23 14:12:35 -0700[diff] [blame]780
781 sham: sham@53100000 {
782 compatible = "ti,omap4-sham";
783 ti,hwmods = "sham";
784 reg = <0x53100000 0x200>;
785 interrupts = <109>;
786 dmas = <&edma 36>;
787 dma-names = "rx";
788 };
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]789
790 aes: aes@53500000 {
791 compatible = "ti,omap4-aes";
792 ti,hwmods = "aes";
793 reg = <0x53500000 0xa0>;
Joel Fernandes7af88842013-07-17 19:07:52 -0500[diff] [blame]794 interrupts = <103>;
Mark A. Greer99919e5e2013-08-23 14:12:36 -0700[diff] [blame]795 dmas = <&edma 6>,
796 <&edma 5>;
797 dma-names = "tx", "rx";
798 };
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]799
800 mcasp0: mcasp@48038000 {
801 compatible = "ti,am33xx-mcasp-audio";
802 ti,hwmods = "mcasp0";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]803 reg = <0x48038000 0x2000>,
804 <0x46000000 0x400000>;
805 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]806 interrupts = <80>, <81>;
807 interrupts-names = "tx", "rx";
808 status = "disabled";
809 dmas = <&edma 8>,
810 <&edma 9>;
811 dma-names = "tx", "rx";
812 };
813
814 mcasp1: mcasp@4803C000 {
815 compatible = "ti,am33xx-mcasp-audio";
816 ti,hwmods = "mcasp1";
Jyri Sarha0bee55a2013-10-20 20:04:09 +0300[diff] [blame]817 reg = <0x4803C000 0x2000>,
818 <0x46400000 0x400000>;
819 reg-names = "mpu", "dat";
Pantelis Antoniou3f72f872013-10-20 20:04:08 +0300[diff] [blame]820 interrupts = <82>, <83>;
821 interrupts-names = "tx", "rx";
822 status = "disabled";
823 dmas = <&edma 10>,
824 <&edma 11>;
825 dma-names = "tx", "rx";
826 };
Lokesh Vutlaed845d62013-08-29 18:22:09 +0530[diff] [blame]827
828 rng: rng@48310000 {
829 compatible = "ti,omap4-rng";
830 ti,hwmods = "rng";
831 reg = <0x48310000 0x2000>;
832 interrupts = <111>;
833 };
AnilKumar Ch5fc0b422012-06-22 15:10:48 +0530[diff] [blame]834 };
835};
Tero Kristoea291c92013-07-18 18:15:35 +0300[diff] [blame]836
837/include/ "am33xx-clocks.dtsi"