Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008-2010 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * Zou Nan hai <nanhai.zou@intel.com> |
| 26 | * Xiang Hai hao<haihao.xiang@intel.com> |
| 27 | * |
| 28 | */ |
| 29 | |
| 30 | #include "drmP.h" |
| 31 | #include "drm.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 32 | #include "i915_drv.h" |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 33 | #include "i915_drm.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 34 | #include "i915_trace.h" |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 35 | #include "intel_drv.h" |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 36 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 37 | /* |
| 38 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 39 | * over cache flushing. |
| 40 | */ |
| 41 | struct pipe_control { |
| 42 | struct drm_i915_gem_object *obj; |
| 43 | volatile u32 *cpu_page; |
| 44 | u32 gtt_offset; |
| 45 | }; |
| 46 | |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 47 | static inline int ring_space(struct intel_ring_buffer *ring) |
| 48 | { |
| 49 | int space = (ring->head & HEAD_ADDR) - (ring->tail + 8); |
| 50 | if (space < 0) |
| 51 | space += ring->size; |
| 52 | return space; |
| 53 | } |
| 54 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 55 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 56 | render_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 57 | u32 invalidate_domains, |
| 58 | u32 flush_domains) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 59 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 60 | struct drm_device *dev = ring->dev; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 61 | u32 cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 62 | int ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 63 | |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 64 | /* |
| 65 | * read/write caches: |
| 66 | * |
| 67 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 68 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 69 | * also flushed at 2d versus 3d pipeline switches. |
| 70 | * |
| 71 | * read-only caches: |
| 72 | * |
| 73 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 74 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 75 | * |
| 76 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 77 | * |
| 78 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 79 | * invalidated when MI_EXE_FLUSH is set. |
| 80 | * |
| 81 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 82 | * invalidated with every MI_FLUSH. |
| 83 | * |
| 84 | * TLBs: |
| 85 | * |
| 86 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 87 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 88 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 89 | * are flushed at any MI_FLUSH. |
| 90 | */ |
| 91 | |
| 92 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 93 | if ((invalidate_domains|flush_domains) & |
| 94 | I915_GEM_DOMAIN_RENDER) |
| 95 | cmd &= ~MI_NO_WRITE_FLUSH; |
| 96 | if (INTEL_INFO(dev)->gen < 4) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 97 | /* |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 98 | * On the 965, the sampler cache always gets flushed |
| 99 | * and this bit is reserved. |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 100 | */ |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 101 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 102 | cmd |= MI_READ_FLUSH; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 103 | } |
Chris Wilson | 36d527d | 2011-03-19 22:26:49 +0000 | [diff] [blame] | 104 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 105 | cmd |= MI_EXE_FLUSH; |
| 106 | |
| 107 | if (invalidate_domains & I915_GEM_DOMAIN_COMMAND && |
| 108 | (IS_G4X(dev) || IS_GEN5(dev))) |
| 109 | cmd |= MI_INVALIDATE_ISP; |
| 110 | |
| 111 | ret = intel_ring_begin(ring, 2); |
| 112 | if (ret) |
| 113 | return ret; |
| 114 | |
| 115 | intel_ring_emit(ring, cmd); |
| 116 | intel_ring_emit(ring, MI_NOOP); |
| 117 | intel_ring_advance(ring); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 118 | |
| 119 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 120 | } |
| 121 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 122 | /** |
| 123 | * Emits a PIPE_CONTROL with a non-zero post-sync operation, for |
| 124 | * implementing two workarounds on gen6. From section 1.4.7.1 |
| 125 | * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1: |
| 126 | * |
| 127 | * [DevSNB-C+{W/A}] Before any depth stall flush (including those |
| 128 | * produced by non-pipelined state commands), software needs to first |
| 129 | * send a PIPE_CONTROL with no bits set except Post-Sync Operation != |
| 130 | * 0. |
| 131 | * |
| 132 | * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable |
| 133 | * =1, a PIPE_CONTROL with any non-zero post-sync-op is required. |
| 134 | * |
| 135 | * And the workaround for these two requires this workaround first: |
| 136 | * |
| 137 | * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent |
| 138 | * BEFORE the pipe-control with a post-sync op and no write-cache |
| 139 | * flushes. |
| 140 | * |
| 141 | * And this last workaround is tricky because of the requirements on |
| 142 | * that bit. From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM |
| 143 | * volume 2 part 1: |
| 144 | * |
| 145 | * "1 of the following must also be set: |
| 146 | * - Render Target Cache Flush Enable ([12] of DW1) |
| 147 | * - Depth Cache Flush Enable ([0] of DW1) |
| 148 | * - Stall at Pixel Scoreboard ([1] of DW1) |
| 149 | * - Depth Stall ([13] of DW1) |
| 150 | * - Post-Sync Operation ([13] of DW1) |
| 151 | * - Notify Enable ([8] of DW1)" |
| 152 | * |
| 153 | * The cache flushes require the workaround flush that triggered this |
| 154 | * one, so we can't use it. Depth stall would trigger the same. |
| 155 | * Post-sync nonzero is what triggered this second workaround, so we |
| 156 | * can't use that one either. Notify enable is IRQs, which aren't |
| 157 | * really our business. That leaves only stall at scoreboard. |
| 158 | */ |
| 159 | static int |
| 160 | intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring) |
| 161 | { |
| 162 | struct pipe_control *pc = ring->private; |
| 163 | u32 scratch_addr = pc->gtt_offset + 128; |
| 164 | int ret; |
| 165 | |
| 166 | |
| 167 | ret = intel_ring_begin(ring, 6); |
| 168 | if (ret) |
| 169 | return ret; |
| 170 | |
| 171 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 172 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL | |
| 173 | PIPE_CONTROL_STALL_AT_SCOREBOARD); |
| 174 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 175 | intel_ring_emit(ring, 0); /* low dword */ |
| 176 | intel_ring_emit(ring, 0); /* high dword */ |
| 177 | intel_ring_emit(ring, MI_NOOP); |
| 178 | intel_ring_advance(ring); |
| 179 | |
| 180 | ret = intel_ring_begin(ring, 6); |
| 181 | if (ret) |
| 182 | return ret; |
| 183 | |
| 184 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 185 | intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE); |
| 186 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */ |
| 187 | intel_ring_emit(ring, 0); |
| 188 | intel_ring_emit(ring, 0); |
| 189 | intel_ring_emit(ring, MI_NOOP); |
| 190 | intel_ring_advance(ring); |
| 191 | |
| 192 | return 0; |
| 193 | } |
| 194 | |
| 195 | static int |
| 196 | gen6_render_ring_flush(struct intel_ring_buffer *ring, |
| 197 | u32 invalidate_domains, u32 flush_domains) |
| 198 | { |
| 199 | u32 flags = 0; |
| 200 | struct pipe_control *pc = ring->private; |
| 201 | u32 scratch_addr = pc->gtt_offset + 128; |
| 202 | int ret; |
| 203 | |
| 204 | /* Force SNB workarounds for PIPE_CONTROL flushes */ |
| 205 | intel_emit_post_sync_nonzero_flush(ring); |
| 206 | |
| 207 | /* Just flush everything. Experiments have shown that reducing the |
| 208 | * number of bits based on the write domains has little performance |
| 209 | * impact. |
| 210 | */ |
| 211 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
| 212 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; |
| 213 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; |
| 214 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; |
| 215 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; |
| 216 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; |
| 217 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; |
| 218 | |
| 219 | ret = intel_ring_begin(ring, 6); |
| 220 | if (ret) |
| 221 | return ret; |
| 222 | |
| 223 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5)); |
| 224 | intel_ring_emit(ring, flags); |
| 225 | intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); |
| 226 | intel_ring_emit(ring, 0); /* lower dword */ |
| 227 | intel_ring_emit(ring, 0); /* uppwer dword */ |
| 228 | intel_ring_emit(ring, MI_NOOP); |
| 229 | intel_ring_advance(ring); |
| 230 | |
| 231 | return 0; |
| 232 | } |
| 233 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 234 | static void ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 235 | u32 value) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 236 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 237 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 238 | I915_WRITE_TAIL(ring, value); |
Xiang, Haihao | d46eefa | 2010-09-16 10:43:12 +0800 | [diff] [blame] | 239 | } |
| 240 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 241 | u32 intel_ring_get_active_head(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 242 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 243 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
| 244 | u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ? |
Daniel Vetter | 3d281d8 | 2010-09-24 21:14:22 +0200 | [diff] [blame] | 245 | RING_ACTHD(ring->mmio_base) : ACTHD; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 246 | |
| 247 | return I915_READ(acthd_reg); |
| 248 | } |
| 249 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 250 | static int init_ring_common(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 251 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 252 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 253 | struct drm_i915_gem_object *obj = ring->obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 254 | u32 head; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 255 | |
| 256 | /* Stop the ring if it's running. */ |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 257 | I915_WRITE_CTL(ring, 0); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 258 | I915_WRITE_HEAD(ring, 0); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 259 | ring->write_tail(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 260 | |
| 261 | /* Initialize the ring. */ |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 262 | I915_WRITE_START(ring, obj->gtt_offset); |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 263 | head = I915_READ_HEAD(ring) & HEAD_ADDR; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 264 | |
| 265 | /* G45 ring initialization fails to reset head to zero */ |
| 266 | if (head != 0) { |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 267 | DRM_DEBUG_KMS("%s head not reset to zero " |
| 268 | "ctl %08x head %08x tail %08x start %08x\n", |
| 269 | ring->name, |
| 270 | I915_READ_CTL(ring), |
| 271 | I915_READ_HEAD(ring), |
| 272 | I915_READ_TAIL(ring), |
| 273 | I915_READ_START(ring)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 274 | |
Daniel Vetter | 570ef60 | 2010-08-02 17:06:23 +0200 | [diff] [blame] | 275 | I915_WRITE_HEAD(ring, 0); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 276 | |
Chris Wilson | 6fd0d56 | 2010-12-05 20:42:33 +0000 | [diff] [blame] | 277 | if (I915_READ_HEAD(ring) & HEAD_ADDR) { |
| 278 | DRM_ERROR("failed to set %s head to zero " |
| 279 | "ctl %08x head %08x tail %08x start %08x\n", |
| 280 | ring->name, |
| 281 | I915_READ_CTL(ring), |
| 282 | I915_READ_HEAD(ring), |
| 283 | I915_READ_TAIL(ring), |
| 284 | I915_READ_START(ring)); |
| 285 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 286 | } |
| 287 | |
Daniel Vetter | 7f2ab69 | 2010-08-02 17:06:59 +0200 | [diff] [blame] | 288 | I915_WRITE_CTL(ring, |
Chris Wilson | ae69b42 | 2010-11-07 11:45:52 +0000 | [diff] [blame] | 289 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) |
Chris Wilson | 5d031e5 | 2012-02-08 13:34:13 +0000 | [diff] [blame] | 290 | | RING_VALID); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 291 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 292 | /* If the head is still not zero, the ring is dead */ |
Sean Paul | f01db98 | 2012-03-16 12:43:22 -0400 | [diff] [blame] | 293 | if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 && |
| 294 | I915_READ_START(ring) == obj->gtt_offset && |
| 295 | (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) { |
Chris Wilson | e74cfed | 2010-11-09 10:16:56 +0000 | [diff] [blame] | 296 | DRM_ERROR("%s initialization failed " |
| 297 | "ctl %08x head %08x tail %08x start %08x\n", |
| 298 | ring->name, |
| 299 | I915_READ_CTL(ring), |
| 300 | I915_READ_HEAD(ring), |
| 301 | I915_READ_TAIL(ring), |
| 302 | I915_READ_START(ring)); |
| 303 | return -EIO; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 304 | } |
| 305 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 306 | if (!drm_core_check_feature(ring->dev, DRIVER_MODESET)) |
| 307 | i915_kernel_lost_context(ring->dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 308 | else { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 309 | ring->head = I915_READ_HEAD(ring); |
Daniel Vetter | 870e86d | 2010-08-02 16:29:44 +0200 | [diff] [blame] | 310 | ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 311 | ring->space = ring_space(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 312 | } |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 313 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 314 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 315 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 316 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 317 | static int |
| 318 | init_pipe_control(struct intel_ring_buffer *ring) |
| 319 | { |
| 320 | struct pipe_control *pc; |
| 321 | struct drm_i915_gem_object *obj; |
| 322 | int ret; |
| 323 | |
| 324 | if (ring->private) |
| 325 | return 0; |
| 326 | |
| 327 | pc = kmalloc(sizeof(*pc), GFP_KERNEL); |
| 328 | if (!pc) |
| 329 | return -ENOMEM; |
| 330 | |
| 331 | obj = i915_gem_alloc_object(ring->dev, 4096); |
| 332 | if (obj == NULL) { |
| 333 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 334 | ret = -ENOMEM; |
| 335 | goto err; |
| 336 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 337 | |
| 338 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 339 | |
| 340 | ret = i915_gem_object_pin(obj, 4096, true); |
| 341 | if (ret) |
| 342 | goto err_unref; |
| 343 | |
| 344 | pc->gtt_offset = obj->gtt_offset; |
| 345 | pc->cpu_page = kmap(obj->pages[0]); |
| 346 | if (pc->cpu_page == NULL) |
| 347 | goto err_unpin; |
| 348 | |
| 349 | pc->obj = obj; |
| 350 | ring->private = pc; |
| 351 | return 0; |
| 352 | |
| 353 | err_unpin: |
| 354 | i915_gem_object_unpin(obj); |
| 355 | err_unref: |
| 356 | drm_gem_object_unreference(&obj->base); |
| 357 | err: |
| 358 | kfree(pc); |
| 359 | return ret; |
| 360 | } |
| 361 | |
| 362 | static void |
| 363 | cleanup_pipe_control(struct intel_ring_buffer *ring) |
| 364 | { |
| 365 | struct pipe_control *pc = ring->private; |
| 366 | struct drm_i915_gem_object *obj; |
| 367 | |
| 368 | if (!ring->private) |
| 369 | return; |
| 370 | |
| 371 | obj = pc->obj; |
| 372 | kunmap(obj->pages[0]); |
| 373 | i915_gem_object_unpin(obj); |
| 374 | drm_gem_object_unreference(&obj->base); |
| 375 | |
| 376 | kfree(pc); |
| 377 | ring->private = NULL; |
| 378 | } |
| 379 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 380 | static int init_render_ring(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 381 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 382 | struct drm_device *dev = ring->dev; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 383 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 384 | int ret = init_ring_common(ring); |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 385 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 386 | if (INTEL_INFO(dev)->gen > 3) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 387 | int mode = VS_TIMER_DISPATCH << 16 | VS_TIMER_DISPATCH; |
Zhenyu Wang | a69ffdb | 2010-08-30 16:12:42 +0800 | [diff] [blame] | 388 | I915_WRITE(MI_MODE, mode); |
Jesse Barnes | b095cd0 | 2011-08-12 15:28:32 -0700 | [diff] [blame] | 389 | if (IS_GEN7(dev)) |
| 390 | I915_WRITE(GFX_MODE_GEN7, |
| 391 | GFX_MODE_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) | |
| 392 | GFX_MODE_ENABLE(GFX_REPLAY_MODE)); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 393 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 394 | |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 395 | if (INTEL_INFO(dev)->gen >= 5) { |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 396 | ret = init_pipe_control(ring); |
| 397 | if (ret) |
| 398 | return ret; |
| 399 | } |
| 400 | |
Ben Widawsky | 84f9f93 | 2011-12-12 19:21:58 -0800 | [diff] [blame] | 401 | if (INTEL_INFO(dev)->gen >= 6) { |
| 402 | I915_WRITE(INSTPM, |
| 403 | INSTPM_FORCE_ORDERING << 16 | INSTPM_FORCE_ORDERING); |
| 404 | } |
| 405 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 406 | return ret; |
| 407 | } |
| 408 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 409 | static void render_ring_cleanup(struct intel_ring_buffer *ring) |
| 410 | { |
| 411 | if (!ring->private) |
| 412 | return; |
| 413 | |
| 414 | cleanup_pipe_control(ring); |
| 415 | } |
| 416 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 417 | static void |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 418 | update_mboxes(struct intel_ring_buffer *ring, |
| 419 | u32 seqno, |
| 420 | u32 mmio_offset) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 421 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 422 | intel_ring_emit(ring, MI_SEMAPHORE_MBOX | |
| 423 | MI_SEMAPHORE_GLOBAL_GTT | |
| 424 | MI_SEMAPHORE_REGISTER | |
| 425 | MI_SEMAPHORE_UPDATE); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 426 | intel_ring_emit(ring, seqno); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 427 | intel_ring_emit(ring, mmio_offset); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 428 | } |
| 429 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 430 | /** |
| 431 | * gen6_add_request - Update the semaphore mailbox registers |
| 432 | * |
| 433 | * @ring - ring that is adding a request |
| 434 | * @seqno - return seqno stuck into the ring |
| 435 | * |
| 436 | * Update the mailbox registers in the *other* rings with the current seqno. |
| 437 | * This acts like a signal in the canonical semaphore. |
| 438 | */ |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 439 | static int |
| 440 | gen6_add_request(struct intel_ring_buffer *ring, |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 441 | u32 *seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 442 | { |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 443 | u32 mbox1_reg; |
| 444 | u32 mbox2_reg; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 445 | int ret; |
| 446 | |
| 447 | ret = intel_ring_begin(ring, 10); |
| 448 | if (ret) |
| 449 | return ret; |
| 450 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 451 | mbox1_reg = ring->signal_mbox[0]; |
| 452 | mbox2_reg = ring->signal_mbox[1]; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 453 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 454 | *seqno = i915_gem_next_request_seqno(ring); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 455 | |
| 456 | update_mboxes(ring, *seqno, mbox1_reg); |
| 457 | update_mboxes(ring, *seqno, mbox2_reg); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 458 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 459 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 460 | intel_ring_emit(ring, *seqno); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 461 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 462 | intel_ring_advance(ring); |
| 463 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 464 | return 0; |
| 465 | } |
| 466 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 467 | /** |
| 468 | * intel_ring_sync - sync the waiter to the signaller on seqno |
| 469 | * |
| 470 | * @waiter - ring that is waiting |
| 471 | * @signaller - ring which has, or will signal |
| 472 | * @seqno - seqno which the waiter will block on |
| 473 | */ |
| 474 | static int |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 475 | gen6_ring_sync(struct intel_ring_buffer *waiter, |
| 476 | struct intel_ring_buffer *signaller, |
| 477 | u32 seqno) |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 478 | { |
| 479 | int ret; |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 480 | u32 dw1 = MI_SEMAPHORE_MBOX | |
| 481 | MI_SEMAPHORE_COMPARE | |
| 482 | MI_SEMAPHORE_REGISTER; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 483 | |
Ben Widawsky | 1500f7e | 2012-04-11 11:18:21 -0700 | [diff] [blame] | 484 | /* Throughout all of the GEM code, seqno passed implies our current |
| 485 | * seqno is >= the last seqno executed. However for hardware the |
| 486 | * comparison is strictly greater than. |
| 487 | */ |
| 488 | seqno -= 1; |
| 489 | |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 490 | WARN_ON(signaller->semaphore_register[waiter->id] == |
| 491 | MI_SEMAPHORE_SYNC_INVALID); |
| 492 | |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 493 | ret = intel_ring_begin(waiter, 4); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 494 | if (ret) |
| 495 | return ret; |
| 496 | |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 497 | intel_ring_emit(waiter, |
| 498 | dw1 | signaller->semaphore_register[waiter->id]); |
Ben Widawsky | c8c99b0 | 2011-09-14 20:32:47 -0700 | [diff] [blame] | 499 | intel_ring_emit(waiter, seqno); |
| 500 | intel_ring_emit(waiter, 0); |
| 501 | intel_ring_emit(waiter, MI_NOOP); |
| 502 | intel_ring_advance(waiter); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 503 | |
| 504 | return 0; |
| 505 | } |
| 506 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 507 | #define PIPE_CONTROL_FLUSH(ring__, addr__) \ |
| 508 | do { \ |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 509 | intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | \ |
| 510 | PIPE_CONTROL_DEPTH_STALL); \ |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 511 | intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT); \ |
| 512 | intel_ring_emit(ring__, 0); \ |
| 513 | intel_ring_emit(ring__, 0); \ |
| 514 | } while (0) |
| 515 | |
| 516 | static int |
| 517 | pc_render_add_request(struct intel_ring_buffer *ring, |
| 518 | u32 *result) |
| 519 | { |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 520 | u32 seqno = i915_gem_next_request_seqno(ring); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 521 | struct pipe_control *pc = ring->private; |
| 522 | u32 scratch_addr = pc->gtt_offset + 128; |
| 523 | int ret; |
| 524 | |
| 525 | /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently |
| 526 | * incoherent with writes to memory, i.e. completely fubar, |
| 527 | * so we need to use PIPE_NOTIFY instead. |
| 528 | * |
| 529 | * However, we also need to workaround the qword write |
| 530 | * incoherence by flushing the 6 PIPE_NOTIFY buffers out to |
| 531 | * memory before requesting an interrupt. |
| 532 | */ |
| 533 | ret = intel_ring_begin(ring, 32); |
| 534 | if (ret) |
| 535 | return ret; |
| 536 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 537 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 538 | PIPE_CONTROL_WRITE_FLUSH | |
| 539 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE); |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 540 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 541 | intel_ring_emit(ring, seqno); |
| 542 | intel_ring_emit(ring, 0); |
| 543 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 544 | scratch_addr += 128; /* write to separate cachelines */ |
| 545 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 546 | scratch_addr += 128; |
| 547 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 548 | scratch_addr += 128; |
| 549 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 550 | scratch_addr += 128; |
| 551 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
| 552 | scratch_addr += 128; |
| 553 | PIPE_CONTROL_FLUSH(ring, scratch_addr); |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 554 | |
Kenneth Graunke | fcbc34e | 2011-10-11 23:41:08 +0200 | [diff] [blame] | 555 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE | |
Kenneth Graunke | 9d971b3 | 2011-10-11 23:41:09 +0200 | [diff] [blame] | 556 | PIPE_CONTROL_WRITE_FLUSH | |
| 557 | PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 558 | PIPE_CONTROL_NOTIFY); |
| 559 | intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT); |
| 560 | intel_ring_emit(ring, seqno); |
| 561 | intel_ring_emit(ring, 0); |
| 562 | intel_ring_advance(ring); |
| 563 | |
| 564 | *result = seqno; |
| 565 | return 0; |
| 566 | } |
| 567 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 568 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 569 | render_ring_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 570 | u32 *result) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 571 | { |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 572 | u32 seqno = i915_gem_next_request_seqno(ring); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 573 | int ret; |
Zhenyu Wang | ca76482 | 2010-05-27 10:26:42 +0800 | [diff] [blame] | 574 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 575 | ret = intel_ring_begin(ring, 4); |
| 576 | if (ret) |
| 577 | return ret; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 578 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 579 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 580 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 581 | intel_ring_emit(ring, seqno); |
| 582 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 583 | intel_ring_advance(ring); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 584 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 585 | *result = seqno; |
| 586 | return 0; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 587 | } |
| 588 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 589 | static u32 |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 590 | gen6_ring_get_seqno(struct intel_ring_buffer *ring) |
| 591 | { |
| 592 | struct drm_device *dev = ring->dev; |
| 593 | |
| 594 | /* Workaround to force correct ordering between irq and seqno writes on |
| 595 | * ivb (and maybe also on snb) by reading from a CS register (like |
| 596 | * ACTHD) before reading the status page. */ |
Daniel Vetter | 1c7eaac | 2012-03-27 09:31:24 +0200 | [diff] [blame] | 597 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 598 | intel_ring_get_active_head(ring); |
| 599 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 600 | } |
| 601 | |
| 602 | static u32 |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 603 | ring_get_seqno(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 604 | { |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 605 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); |
| 606 | } |
| 607 | |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 608 | static u32 |
| 609 | pc_render_get_seqno(struct intel_ring_buffer *ring) |
| 610 | { |
| 611 | struct pipe_control *pc = ring->private; |
| 612 | return pc->cpu_page[0]; |
| 613 | } |
| 614 | |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 615 | static void |
| 616 | ironlake_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 617 | { |
| 618 | dev_priv->gt_irq_mask &= ~mask; |
| 619 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 620 | POSTING_READ(GTIMR); |
| 621 | } |
| 622 | |
| 623 | static void |
| 624 | ironlake_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 625 | { |
| 626 | dev_priv->gt_irq_mask |= mask; |
| 627 | I915_WRITE(GTIMR, dev_priv->gt_irq_mask); |
| 628 | POSTING_READ(GTIMR); |
| 629 | } |
| 630 | |
| 631 | static void |
| 632 | i915_enable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 633 | { |
| 634 | dev_priv->irq_mask &= ~mask; |
| 635 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 636 | POSTING_READ(IMR); |
| 637 | } |
| 638 | |
| 639 | static void |
| 640 | i915_disable_irq(drm_i915_private_t *dev_priv, u32 mask) |
| 641 | { |
| 642 | dev_priv->irq_mask |= mask; |
| 643 | I915_WRITE(IMR, dev_priv->irq_mask); |
| 644 | POSTING_READ(IMR); |
| 645 | } |
| 646 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 647 | static bool |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 648 | gen5_ring_get_irq(struct intel_ring_buffer *ring) |
| 649 | { |
| 650 | struct drm_device *dev = ring->dev; |
| 651 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 652 | |
| 653 | if (!dev->irq_enabled) |
| 654 | return false; |
| 655 | |
| 656 | spin_lock(&ring->irq_lock); |
| 657 | if (ring->irq_refcount++ == 0) |
| 658 | ironlake_enable_irq(dev_priv, ring->irq_enable_mask); |
| 659 | spin_unlock(&ring->irq_lock); |
| 660 | |
| 661 | return true; |
| 662 | } |
| 663 | |
| 664 | static void |
| 665 | gen5_ring_put_irq(struct intel_ring_buffer *ring) |
| 666 | { |
| 667 | struct drm_device *dev = ring->dev; |
| 668 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 669 | |
| 670 | spin_lock(&ring->irq_lock); |
| 671 | if (--ring->irq_refcount == 0) |
| 672 | ironlake_disable_irq(dev_priv, ring->irq_enable_mask); |
| 673 | spin_unlock(&ring->irq_lock); |
| 674 | } |
| 675 | |
| 676 | static bool |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 677 | i9xx_ring_get_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 678 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 679 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 680 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 681 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 682 | if (!dev->irq_enabled) |
| 683 | return false; |
| 684 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 685 | spin_lock(&ring->irq_lock); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 686 | if (ring->irq_refcount++ == 0) |
| 687 | i915_enable_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 688 | spin_unlock(&ring->irq_lock); |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 689 | |
| 690 | return true; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 691 | } |
| 692 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 693 | static void |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 694 | i9xx_ring_put_irq(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 695 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 696 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 697 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 698 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 699 | spin_lock(&ring->irq_lock); |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 700 | if (--ring->irq_refcount == 0) |
| 701 | i915_disable_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 702 | spin_unlock(&ring->irq_lock); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 703 | } |
| 704 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 705 | void intel_ring_setup_status_page(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 706 | { |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 707 | struct drm_device *dev = ring->dev; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 708 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 709 | u32 mmio = 0; |
| 710 | |
| 711 | /* The ring status page addresses are no longer next to the rest of |
| 712 | * the ring registers as of gen7. |
| 713 | */ |
| 714 | if (IS_GEN7(dev)) { |
| 715 | switch (ring->id) { |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 716 | case RCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 717 | mmio = RENDER_HWS_PGA_GEN7; |
| 718 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 719 | case BCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 720 | mmio = BLT_HWS_PGA_GEN7; |
| 721 | break; |
Daniel Vetter | 96154f2 | 2011-12-14 13:57:00 +0100 | [diff] [blame] | 722 | case VCS: |
Eric Anholt | 4593010 | 2011-05-06 17:12:35 -0700 | [diff] [blame] | 723 | mmio = BSD_HWS_PGA_GEN7; |
| 724 | break; |
| 725 | } |
| 726 | } else if (IS_GEN6(ring->dev)) { |
| 727 | mmio = RING_HWS_PGA_GEN6(ring->mmio_base); |
| 728 | } else { |
| 729 | mmio = RING_HWS_PGA(ring->mmio_base); |
| 730 | } |
| 731 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 732 | I915_WRITE(mmio, (u32)ring->status_page.gfx_addr); |
| 733 | POSTING_READ(mmio); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 734 | } |
| 735 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 736 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 737 | bsd_ring_flush(struct intel_ring_buffer *ring, |
| 738 | u32 invalidate_domains, |
| 739 | u32 flush_domains) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 740 | { |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 741 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 742 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 743 | ret = intel_ring_begin(ring, 2); |
| 744 | if (ret) |
| 745 | return ret; |
| 746 | |
| 747 | intel_ring_emit(ring, MI_FLUSH); |
| 748 | intel_ring_emit(ring, MI_NOOP); |
| 749 | intel_ring_advance(ring); |
| 750 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 751 | } |
| 752 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 753 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 754 | ring_add_request(struct intel_ring_buffer *ring, |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 755 | u32 *result) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 756 | { |
| 757 | u32 seqno; |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 758 | int ret; |
| 759 | |
| 760 | ret = intel_ring_begin(ring, 4); |
| 761 | if (ret) |
| 762 | return ret; |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 763 | |
Daniel Vetter | 53d227f | 2012-01-25 16:32:49 +0100 | [diff] [blame] | 764 | seqno = i915_gem_next_request_seqno(ring); |
Chris Wilson | 6f392d548 | 2010-08-07 11:01:22 +0100 | [diff] [blame] | 765 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 766 | intel_ring_emit(ring, MI_STORE_DWORD_INDEX); |
| 767 | intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 768 | intel_ring_emit(ring, seqno); |
| 769 | intel_ring_emit(ring, MI_USER_INTERRUPT); |
| 770 | intel_ring_advance(ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 771 | |
Chris Wilson | 3cce469 | 2010-10-27 16:11:02 +0100 | [diff] [blame] | 772 | *result = seqno; |
| 773 | return 0; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 774 | } |
| 775 | |
Chris Wilson | b13c2b9 | 2010-12-13 16:54:50 +0000 | [diff] [blame] | 776 | static bool |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 777 | gen6_ring_get_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 778 | { |
| 779 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 780 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 781 | |
| 782 | if (!dev->irq_enabled) |
| 783 | return false; |
| 784 | |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 785 | /* It looks like we need to prevent the gt from suspending while waiting |
| 786 | * for an notifiy irq, otherwise irqs seem to get lost on at least the |
| 787 | * blt/bsd rings on ivb. */ |
Daniel Vetter | 99ffa16 | 2012-01-25 14:04:00 +0100 | [diff] [blame] | 788 | gen6_gt_force_wake_get(dev_priv); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 789 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 790 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 791 | if (ring->irq_refcount++ == 0) { |
Daniel Vetter | 6a848cc | 2012-04-11 22:12:46 +0200 | [diff] [blame] | 792 | I915_WRITE_IMR(ring, ~ring->irq_enable_mask); |
| 793 | ironlake_enable_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 794 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 795 | spin_unlock(&ring->irq_lock); |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 796 | |
| 797 | return true; |
| 798 | } |
| 799 | |
| 800 | static void |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 801 | gen6_ring_put_irq(struct intel_ring_buffer *ring) |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 802 | { |
| 803 | struct drm_device *dev = ring->dev; |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 804 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 0f46832 | 2011-01-04 17:35:21 +0000 | [diff] [blame] | 805 | |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 806 | spin_lock(&ring->irq_lock); |
Chris Wilson | 01a0333 | 2011-01-04 22:22:56 +0000 | [diff] [blame] | 807 | if (--ring->irq_refcount == 0) { |
Daniel Vetter | 6a848cc | 2012-04-11 22:12:46 +0200 | [diff] [blame] | 808 | I915_WRITE_IMR(ring, ~0); |
| 809 | ironlake_disable_irq(dev_priv, ring->irq_enable_mask); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 810 | } |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 811 | spin_unlock(&ring->irq_lock); |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 812 | |
Daniel Vetter | 99ffa16 | 2012-01-25 14:04:00 +0100 | [diff] [blame] | 813 | gen6_gt_force_wake_put(dev_priv); |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 814 | } |
| 815 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 816 | static int |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 817 | ring_dispatch_execbuffer(struct intel_ring_buffer *ring, u32 offset, u32 length) |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 818 | { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 819 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 820 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 821 | ret = intel_ring_begin(ring, 2); |
| 822 | if (ret) |
| 823 | return ret; |
| 824 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 825 | intel_ring_emit(ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 826 | MI_BATCH_BUFFER_START | (2 << 6) | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 827 | MI_BATCH_NON_SECURE_I965); |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 828 | intel_ring_emit(ring, offset); |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 829 | intel_ring_advance(ring); |
| 830 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 831 | return 0; |
| 832 | } |
| 833 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 834 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 835 | render_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 836 | u32 offset, u32 len) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 837 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 838 | struct drm_device *dev = ring->dev; |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 839 | int ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 840 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 841 | if (IS_I830(dev) || IS_845G(dev)) { |
| 842 | ret = intel_ring_begin(ring, 4); |
| 843 | if (ret) |
| 844 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 845 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 846 | intel_ring_emit(ring, MI_BATCH_BUFFER); |
| 847 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
| 848 | intel_ring_emit(ring, offset + len - 8); |
| 849 | intel_ring_emit(ring, 0); |
| 850 | } else { |
| 851 | ret = intel_ring_begin(ring, 2); |
| 852 | if (ret) |
| 853 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 854 | |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 855 | if (INTEL_INFO(dev)->gen >= 4) { |
| 856 | intel_ring_emit(ring, |
| 857 | MI_BATCH_BUFFER_START | (2 << 6) | |
| 858 | MI_BATCH_NON_SECURE_I965); |
| 859 | intel_ring_emit(ring, offset); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 860 | } else { |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 861 | intel_ring_emit(ring, |
| 862 | MI_BATCH_BUFFER_START | (2 << 6)); |
| 863 | intel_ring_emit(ring, offset | MI_BATCH_NON_SECURE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 864 | } |
| 865 | } |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 866 | intel_ring_advance(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 867 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 868 | return 0; |
| 869 | } |
| 870 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 871 | static void cleanup_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 872 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 873 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 874 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 875 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 876 | obj = ring->status_page.obj; |
| 877 | if (obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 878 | return; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 879 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 880 | kunmap(obj->pages[0]); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 881 | i915_gem_object_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 882 | drm_gem_object_unreference(&obj->base); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 883 | ring->status_page.obj = NULL; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 884 | |
| 885 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 886 | } |
| 887 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 888 | static int init_status_page(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 889 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 890 | struct drm_device *dev = ring->dev; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 891 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 892 | struct drm_i915_gem_object *obj; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 893 | int ret; |
| 894 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 895 | obj = i915_gem_alloc_object(dev, 4096); |
| 896 | if (obj == NULL) { |
| 897 | DRM_ERROR("Failed to allocate status page\n"); |
| 898 | ret = -ENOMEM; |
| 899 | goto err; |
| 900 | } |
Chris Wilson | e4ffd17 | 2011-04-04 09:44:39 +0100 | [diff] [blame] | 901 | |
| 902 | i915_gem_object_set_cache_level(obj, I915_CACHE_LLC); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 903 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 904 | ret = i915_gem_object_pin(obj, 4096, true); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 905 | if (ret != 0) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 906 | goto err_unref; |
| 907 | } |
| 908 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 909 | ring->status_page.gfx_addr = obj->gtt_offset; |
| 910 | ring->status_page.page_addr = kmap(obj->pages[0]); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 911 | if (ring->status_page.page_addr == NULL) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 912 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 913 | goto err_unpin; |
| 914 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 915 | ring->status_page.obj = obj; |
| 916 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 917 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 918 | intel_ring_setup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 919 | DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n", |
| 920 | ring->name, ring->status_page.gfx_addr); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 921 | |
| 922 | return 0; |
| 923 | |
| 924 | err_unpin: |
| 925 | i915_gem_object_unpin(obj); |
| 926 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 927 | drm_gem_object_unreference(&obj->base); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 928 | err: |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 929 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 930 | } |
| 931 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 932 | int intel_init_ring_buffer(struct drm_device *dev, |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 933 | struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 934 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 935 | struct drm_i915_gem_object *obj; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 936 | int ret; |
| 937 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 938 | ring->dev = dev; |
Chris Wilson | 23bc598 | 2010-09-29 16:10:57 +0100 | [diff] [blame] | 939 | INIT_LIST_HEAD(&ring->active_list); |
| 940 | INIT_LIST_HEAD(&ring->request_list); |
Chris Wilson | 6419340 | 2010-10-24 12:38:05 +0100 | [diff] [blame] | 941 | INIT_LIST_HEAD(&ring->gpu_write_list); |
Daniel Vetter | dfc9ef2 | 2012-04-11 22:12:47 +0200 | [diff] [blame] | 942 | ring->size = 32 * PAGE_SIZE; |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 943 | |
Chris Wilson | b259f67 | 2011-03-29 13:19:09 +0100 | [diff] [blame] | 944 | init_waitqueue_head(&ring->irq_queue); |
Chris Wilson | 0dc79fb | 2011-01-05 10:32:24 +0000 | [diff] [blame] | 945 | spin_lock_init(&ring->irq_lock); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 946 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 947 | if (I915_NEED_GFX_HWS(dev)) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 948 | ret = init_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 949 | if (ret) |
| 950 | return ret; |
| 951 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 952 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 953 | obj = i915_gem_alloc_object(dev, ring->size); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 954 | if (obj == NULL) { |
| 955 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 956 | ret = -ENOMEM; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 957 | goto err_hws; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 958 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 959 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 960 | ring->obj = obj; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 961 | |
Daniel Vetter | 75e9e91 | 2010-11-04 17:11:09 +0100 | [diff] [blame] | 962 | ret = i915_gem_object_pin(obj, PAGE_SIZE, true); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 963 | if (ret) |
| 964 | goto err_unref; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 965 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 966 | ring->map.size = ring->size; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 967 | ring->map.offset = dev->agp->base + obj->gtt_offset; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 968 | ring->map.type = 0; |
| 969 | ring->map.flags = 0; |
| 970 | ring->map.mtrr = 0; |
| 971 | |
| 972 | drm_core_ioremap_wc(&ring->map, dev); |
| 973 | if (ring->map.handle == NULL) { |
| 974 | DRM_ERROR("Failed to map ringbuffer.\n"); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 975 | ret = -EINVAL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 976 | goto err_unpin; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 977 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 978 | |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 979 | ring->virtual_start = ring->map.handle; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 980 | ret = ring->init(ring); |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 981 | if (ret) |
| 982 | goto err_unmap; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 983 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 984 | /* Workaround an erratum on the i830 which causes a hang if |
| 985 | * the TAIL pointer points to within the last 2 cachelines |
| 986 | * of the buffer. |
| 987 | */ |
| 988 | ring->effective_size = ring->size; |
| 989 | if (IS_I830(ring->dev)) |
| 990 | ring->effective_size -= 128; |
| 991 | |
Chris Wilson | c584fe4 | 2010-10-29 18:15:52 +0100 | [diff] [blame] | 992 | return 0; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 993 | |
| 994 | err_unmap: |
| 995 | drm_core_ioremapfree(&ring->map, dev); |
| 996 | err_unpin: |
| 997 | i915_gem_object_unpin(obj); |
| 998 | err_unref: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 999 | drm_gem_object_unreference(&obj->base); |
| 1000 | ring->obj = NULL; |
Chris Wilson | dd785e3 | 2010-08-07 11:01:34 +0100 | [diff] [blame] | 1001 | err_hws: |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1002 | cleanup_status_page(ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1003 | return ret; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1004 | } |
| 1005 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1006 | void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1007 | { |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1008 | struct drm_i915_private *dev_priv; |
| 1009 | int ret; |
| 1010 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1011 | if (ring->obj == NULL) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1012 | return; |
| 1013 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1014 | /* Disable the ring buffer. The ring must be idle at this point */ |
| 1015 | dev_priv = ring->dev->dev_private; |
Ben Widawsky | 96f298a | 2011-03-19 18:14:27 -0700 | [diff] [blame] | 1016 | ret = intel_wait_ring_idle(ring); |
Chris Wilson | 29ee399 | 2011-01-24 16:35:42 +0000 | [diff] [blame] | 1017 | if (ret) |
| 1018 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", |
| 1019 | ring->name, ret); |
| 1020 | |
Chris Wilson | 33626e6 | 2010-10-29 16:18:36 +0100 | [diff] [blame] | 1021 | I915_WRITE_CTL(ring, 0); |
| 1022 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1023 | drm_core_ioremapfree(&ring->map, ring->dev); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1024 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1025 | i915_gem_object_unpin(ring->obj); |
| 1026 | drm_gem_object_unreference(&ring->obj->base); |
| 1027 | ring->obj = NULL; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1028 | |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1029 | if (ring->cleanup) |
| 1030 | ring->cleanup(ring); |
| 1031 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1032 | cleanup_status_page(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1033 | } |
| 1034 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1035 | static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1036 | { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1037 | unsigned int *virt; |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1038 | int rem = ring->size - ring->tail; |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1039 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1040 | if (ring->space < rem) { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1041 | int ret = intel_wait_ring_buffer(ring, rem); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1042 | if (ret) |
| 1043 | return ret; |
| 1044 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1045 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1046 | virt = (unsigned int *)(ring->virtual_start + ring->tail); |
Chris Wilson | 1741dd4 | 2010-08-04 15:18:12 +0100 | [diff] [blame] | 1047 | rem /= 8; |
| 1048 | while (rem--) { |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1049 | *virt++ = MI_NOOP; |
Chris Wilson | 1741dd4 | 2010-08-04 15:18:12 +0100 | [diff] [blame] | 1050 | *virt++ = MI_NOOP; |
| 1051 | } |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1052 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1053 | ring->tail = 0; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1054 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1055 | |
| 1056 | return 0; |
| 1057 | } |
| 1058 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1059 | static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno) |
| 1060 | { |
| 1061 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
| 1062 | bool was_interruptible; |
| 1063 | int ret; |
| 1064 | |
| 1065 | /* XXX As we have not yet audited all the paths to check that |
| 1066 | * they are ready for ERESTARTSYS from intel_ring_begin, do not |
| 1067 | * allow us to be interruptible by a signal. |
| 1068 | */ |
| 1069 | was_interruptible = dev_priv->mm.interruptible; |
| 1070 | dev_priv->mm.interruptible = false; |
| 1071 | |
| 1072 | ret = i915_wait_request(ring, seqno, true); |
| 1073 | |
| 1074 | dev_priv->mm.interruptible = was_interruptible; |
| 1075 | |
| 1076 | return ret; |
| 1077 | } |
| 1078 | |
| 1079 | static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n) |
| 1080 | { |
| 1081 | struct drm_i915_gem_request *request; |
| 1082 | u32 seqno = 0; |
| 1083 | int ret; |
| 1084 | |
| 1085 | i915_gem_retire_requests_ring(ring); |
| 1086 | |
| 1087 | if (ring->last_retired_head != -1) { |
| 1088 | ring->head = ring->last_retired_head; |
| 1089 | ring->last_retired_head = -1; |
| 1090 | ring->space = ring_space(ring); |
| 1091 | if (ring->space >= n) |
| 1092 | return 0; |
| 1093 | } |
| 1094 | |
| 1095 | list_for_each_entry(request, &ring->request_list, list) { |
| 1096 | int space; |
| 1097 | |
| 1098 | if (request->tail == -1) |
| 1099 | continue; |
| 1100 | |
| 1101 | space = request->tail - (ring->tail + 8); |
| 1102 | if (space < 0) |
| 1103 | space += ring->size; |
| 1104 | if (space >= n) { |
| 1105 | seqno = request->seqno; |
| 1106 | break; |
| 1107 | } |
| 1108 | |
| 1109 | /* Consume this request in case we need more space than |
| 1110 | * is available and so need to prevent a race between |
| 1111 | * updating last_retired_head and direct reads of |
| 1112 | * I915_RING_HEAD. It also provides a nice sanity check. |
| 1113 | */ |
| 1114 | request->tail = -1; |
| 1115 | } |
| 1116 | |
| 1117 | if (seqno == 0) |
| 1118 | return -ENOSPC; |
| 1119 | |
| 1120 | ret = intel_ring_wait_seqno(ring, seqno); |
| 1121 | if (ret) |
| 1122 | return ret; |
| 1123 | |
| 1124 | if (WARN_ON(ring->last_retired_head == -1)) |
| 1125 | return -ENOSPC; |
| 1126 | |
| 1127 | ring->head = ring->last_retired_head; |
| 1128 | ring->last_retired_head = -1; |
| 1129 | ring->space = ring_space(ring); |
| 1130 | if (WARN_ON(ring->space < n)) |
| 1131 | return -ENOSPC; |
| 1132 | |
| 1133 | return 0; |
| 1134 | } |
| 1135 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1136 | int intel_wait_ring_buffer(struct intel_ring_buffer *ring, int n) |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1137 | { |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1138 | struct drm_device *dev = ring->dev; |
Zou Nan hai | cae5852 | 2010-11-09 17:17:32 +0800 | [diff] [blame] | 1139 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1140 | unsigned long end; |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1141 | int ret; |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1142 | |
Chris Wilson | a71d8d9 | 2012-02-15 11:25:36 +0000 | [diff] [blame] | 1143 | ret = intel_ring_wait_request(ring, n); |
| 1144 | if (ret != -ENOSPC) |
| 1145 | return ret; |
| 1146 | |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1147 | trace_i915_ring_wait_begin(ring); |
Daniel Vetter | e6bfaf8 | 2011-12-14 13:56:59 +0100 | [diff] [blame] | 1148 | if (drm_core_check_feature(dev, DRIVER_GEM)) |
| 1149 | /* With GEM the hangcheck timer should kick us out of the loop, |
| 1150 | * leaving it early runs the risk of corrupting GEM state (due |
| 1151 | * to running on almost untested codepaths). But on resume |
| 1152 | * timers don't work yet, so prevent a complete hang in that |
| 1153 | * case by choosing an insanely large timeout. */ |
| 1154 | end = jiffies + 60 * HZ; |
| 1155 | else |
| 1156 | end = jiffies + 3 * HZ; |
| 1157 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1158 | do { |
Chris Wilson | c7dca47 | 2011-01-20 17:00:10 +0000 | [diff] [blame] | 1159 | ring->head = I915_READ_HEAD(ring); |
| 1160 | ring->space = ring_space(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1161 | if (ring->space >= n) { |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1162 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1163 | return 0; |
| 1164 | } |
| 1165 | |
| 1166 | if (dev->primary->master) { |
| 1167 | struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv; |
| 1168 | if (master_priv->sarea_priv) |
| 1169 | master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT; |
| 1170 | } |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1171 | |
Chris Wilson | e60a0b1 | 2010-10-13 10:09:14 +0100 | [diff] [blame] | 1172 | msleep(1); |
Chris Wilson | f4e0b29 | 2010-10-29 21:06:16 +0100 | [diff] [blame] | 1173 | if (atomic_read(&dev_priv->mm.wedged)) |
| 1174 | return -EAGAIN; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1175 | } while (!time_after(jiffies, end)); |
Chris Wilson | db53a30 | 2011-02-03 11:57:46 +0000 | [diff] [blame] | 1176 | trace_i915_ring_wait_end(ring); |
Eric Anholt | 62fdfea | 2010-05-21 13:26:39 -0700 | [diff] [blame] | 1177 | return -EBUSY; |
| 1178 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1179 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1180 | int intel_ring_begin(struct intel_ring_buffer *ring, |
| 1181 | int num_dwords) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1182 | { |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 1183 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
Zou Nan hai | be26a10 | 2010-06-12 17:40:24 +0800 | [diff] [blame] | 1184 | int n = 4*num_dwords; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1185 | int ret; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1186 | |
Chris Wilson | 21dd373 | 2011-01-26 15:55:56 +0000 | [diff] [blame] | 1187 | if (unlikely(atomic_read(&dev_priv->mm.wedged))) |
| 1188 | return -EIO; |
| 1189 | |
Chris Wilson | 55249ba | 2010-12-22 14:04:47 +0000 | [diff] [blame] | 1190 | if (unlikely(ring->tail + n > ring->effective_size)) { |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1191 | ret = intel_wrap_ring_buffer(ring); |
| 1192 | if (unlikely(ret)) |
| 1193 | return ret; |
| 1194 | } |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1195 | |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1196 | if (unlikely(ring->space < n)) { |
| 1197 | ret = intel_wait_ring_buffer(ring, n); |
| 1198 | if (unlikely(ret)) |
| 1199 | return ret; |
| 1200 | } |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 1201 | |
| 1202 | ring->space -= n; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1203 | return 0; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1204 | } |
| 1205 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1206 | void intel_ring_advance(struct intel_ring_buffer *ring) |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1207 | { |
Chris Wilson | d97ed33 | 2010-08-04 15:18:13 +0100 | [diff] [blame] | 1208 | ring->tail &= ring->size - 1; |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1209 | ring->write_tail(ring, ring->tail); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1210 | } |
| 1211 | |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1212 | |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1213 | static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring, |
Chris Wilson | 297b0c5 | 2010-10-22 17:02:41 +0100 | [diff] [blame] | 1214 | u32 value) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1215 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1216 | drm_i915_private_t *dev_priv = ring->dev->dev_private; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1217 | |
| 1218 | /* Every tail move must follow the sequence below */ |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1219 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1220 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
| 1221 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_DISABLE); |
| 1222 | I915_WRITE(GEN6_BSD_RNCID, 0x0); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1223 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1224 | if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) & |
| 1225 | GEN6_BSD_SLEEP_PSMI_CONTROL_IDLE_INDICATOR) == 0, |
| 1226 | 50)) |
| 1227 | DRM_ERROR("timed out waiting for IDLE Indicator\n"); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1228 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1229 | I915_WRITE_TAIL(ring, value); |
| 1230 | I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL, |
| 1231 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_MODIFY_MASK | |
| 1232 | GEN6_BSD_SLEEP_PSMI_CONTROL_RC_ILDL_MESSAGE_ENABLE); |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1233 | } |
| 1234 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1235 | static int gen6_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1236 | u32 invalidate, u32 flush) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1237 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1238 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1239 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1240 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1241 | ret = intel_ring_begin(ring, 4); |
| 1242 | if (ret) |
| 1243 | return ret; |
| 1244 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1245 | cmd = MI_FLUSH_DW; |
| 1246 | if (invalidate & I915_GEM_GPU_DOMAINS) |
| 1247 | cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD; |
| 1248 | intel_ring_emit(ring, cmd); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1249 | intel_ring_emit(ring, 0); |
| 1250 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1251 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1252 | intel_ring_advance(ring); |
| 1253 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1254 | } |
| 1255 | |
| 1256 | static int |
Chris Wilson | 78501ea | 2010-10-27 12:18:21 +0100 | [diff] [blame] | 1257 | gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring, |
Chris Wilson | c4e7a41 | 2010-11-30 14:10:25 +0000 | [diff] [blame] | 1258 | u32 offset, u32 len) |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1259 | { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1260 | int ret; |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1261 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1262 | ret = intel_ring_begin(ring, 2); |
| 1263 | if (ret) |
| 1264 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 1265 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1266 | intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_NON_SECURE_I965); |
| 1267 | /* bit0-7 is the length on GEN6+ */ |
| 1268 | intel_ring_emit(ring, offset); |
| 1269 | intel_ring_advance(ring); |
Chris Wilson | ab6f8e3 | 2010-09-19 17:53:44 +0100 | [diff] [blame] | 1270 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1271 | return 0; |
Xiang, Haihao | 881f47b | 2010-09-19 14:40:43 +0100 | [diff] [blame] | 1272 | } |
| 1273 | |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1274 | /* Blitter support (SandyBridge+) */ |
| 1275 | |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1276 | static int blt_ring_flush(struct intel_ring_buffer *ring, |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1277 | u32 invalidate, u32 flush) |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1278 | { |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1279 | uint32_t cmd; |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1280 | int ret; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1281 | |
Daniel Vetter | 6a233c7 | 2011-12-14 13:57:07 +0100 | [diff] [blame] | 1282 | ret = intel_ring_begin(ring, 4); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1283 | if (ret) |
| 1284 | return ret; |
| 1285 | |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1286 | cmd = MI_FLUSH_DW; |
| 1287 | if (invalidate & I915_GEM_DOMAIN_RENDER) |
| 1288 | cmd |= MI_INVALIDATE_TLB; |
| 1289 | intel_ring_emit(ring, cmd); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1290 | intel_ring_emit(ring, 0); |
| 1291 | intel_ring_emit(ring, 0); |
Chris Wilson | 71a77e0 | 2011-02-02 12:13:49 +0000 | [diff] [blame] | 1292 | intel_ring_emit(ring, MI_NOOP); |
Chris Wilson | b72f3ac | 2011-01-04 17:34:02 +0000 | [diff] [blame] | 1293 | intel_ring_advance(ring); |
| 1294 | return 0; |
Zou Nan hai | 8d19215 | 2010-11-02 16:31:01 +0800 | [diff] [blame] | 1295 | } |
| 1296 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1297 | int intel_init_render_ring_buffer(struct drm_device *dev) |
| 1298 | { |
| 1299 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1300 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1301 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1302 | ring->name = "render ring"; |
| 1303 | ring->id = RCS; |
| 1304 | ring->mmio_base = RENDER_RING_BASE; |
| 1305 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1306 | if (INTEL_INFO(dev)->gen >= 6) { |
| 1307 | ring->add_request = gen6_add_request; |
Jesse Barnes | 8d31528 | 2011-10-16 10:23:31 +0200 | [diff] [blame] | 1308 | ring->flush = gen6_render_ring_flush; |
Ben Widawsky | 25c0630 | 2012-03-29 19:11:27 -0700 | [diff] [blame] | 1309 | ring->irq_get = gen6_ring_get_irq; |
| 1310 | ring->irq_put = gen6_ring_put_irq; |
Daniel Vetter | 6a848cc | 2012-04-11 22:12:46 +0200 | [diff] [blame] | 1311 | ring->irq_enable_mask = GT_USER_INTERRUPT; |
Daniel Vetter | 4cd53c0 | 2012-12-14 16:01:25 +0100 | [diff] [blame] | 1312 | ring->get_seqno = gen6_ring_get_seqno; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1313 | ring->sync_to = gen6_ring_sync; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1314 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_INVALID; |
| 1315 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_RV; |
| 1316 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_RB; |
| 1317 | ring->signal_mbox[0] = GEN6_VRSYNC; |
| 1318 | ring->signal_mbox[1] = GEN6_BRSYNC; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1319 | } else if (IS_GEN5(dev)) { |
| 1320 | ring->add_request = pc_render_add_request; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1321 | ring->flush = render_ring_flush; |
Chris Wilson | c6df541 | 2010-12-15 09:56:50 +0000 | [diff] [blame] | 1322 | ring->get_seqno = pc_render_get_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1323 | ring->irq_get = gen5_ring_get_irq; |
| 1324 | ring->irq_put = gen5_ring_put_irq; |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1325 | ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1326 | } else { |
| 1327 | ring->add_request = render_ring_add_request; |
| 1328 | ring->flush = render_ring_flush; |
| 1329 | ring->get_seqno = ring_get_seqno; |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1330 | ring->irq_get = i9xx_ring_get_irq; |
| 1331 | ring->irq_put = i9xx_ring_put_irq; |
| 1332 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1333 | } |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1334 | ring->write_tail = ring_write_tail; |
| 1335 | ring->dispatch_execbuffer = render_ring_dispatch_execbuffer; |
| 1336 | ring->init = init_render_ring; |
| 1337 | ring->cleanup = render_ring_cleanup; |
| 1338 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1339 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1340 | if (!I915_NEED_GFX_HWS(dev)) { |
| 1341 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1342 | memset(ring->status_page.page_addr, 0, PAGE_SIZE); |
| 1343 | } |
| 1344 | |
| 1345 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1346 | } |
| 1347 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1348 | int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size) |
| 1349 | { |
| 1350 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1351 | struct intel_ring_buffer *ring = &dev_priv->ring[RCS]; |
| 1352 | |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1353 | ring->name = "render ring"; |
| 1354 | ring->id = RCS; |
| 1355 | ring->mmio_base = RENDER_RING_BASE; |
| 1356 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1357 | if (INTEL_INFO(dev)->gen >= 6) { |
Daniel Vetter | b4178f8 | 2012-04-11 22:12:51 +0200 | [diff] [blame] | 1358 | /* non-kms not supported on gen6+ */ |
| 1359 | return -ENODEV; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1360 | } else if (IS_GEN5(dev)) { |
| 1361 | ring->add_request = pc_render_add_request; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1362 | ring->flush = render_ring_flush; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1363 | ring->get_seqno = pc_render_get_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1364 | ring->irq_get = gen5_ring_get_irq; |
| 1365 | ring->irq_put = gen5_ring_put_irq; |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1366 | ring->irq_enable_mask = GT_USER_INTERRUPT | GT_PIPE_NOTIFY; |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1367 | } else { |
| 1368 | ring->add_request = render_ring_add_request; |
| 1369 | ring->flush = render_ring_flush; |
| 1370 | ring->get_seqno = ring_get_seqno; |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1371 | ring->irq_get = i9xx_ring_get_irq; |
| 1372 | ring->irq_put = i9xx_ring_put_irq; |
| 1373 | ring->irq_enable_mask = I915_USER_INTERRUPT; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1374 | } |
Daniel Vetter | 59465b5 | 2012-04-11 22:12:48 +0200 | [diff] [blame] | 1375 | ring->write_tail = ring_write_tail; |
| 1376 | ring->dispatch_execbuffer = render_ring_dispatch_execbuffer; |
| 1377 | ring->init = init_render_ring; |
| 1378 | ring->cleanup = render_ring_cleanup; |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1379 | |
Keith Packard | f323470 | 2011-07-22 10:44:39 -0700 | [diff] [blame] | 1380 | if (!I915_NEED_GFX_HWS(dev)) |
| 1381 | ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr; |
| 1382 | |
Chris Wilson | e8616b6 | 2011-01-20 09:57:11 +0000 | [diff] [blame] | 1383 | ring->dev = dev; |
| 1384 | INIT_LIST_HEAD(&ring->active_list); |
| 1385 | INIT_LIST_HEAD(&ring->request_list); |
| 1386 | INIT_LIST_HEAD(&ring->gpu_write_list); |
| 1387 | |
| 1388 | ring->size = size; |
| 1389 | ring->effective_size = ring->size; |
| 1390 | if (IS_I830(ring->dev)) |
| 1391 | ring->effective_size -= 128; |
| 1392 | |
| 1393 | ring->map.offset = start; |
| 1394 | ring->map.size = size; |
| 1395 | ring->map.type = 0; |
| 1396 | ring->map.flags = 0; |
| 1397 | ring->map.mtrr = 0; |
| 1398 | |
| 1399 | drm_core_ioremap_wc(&ring->map, dev); |
| 1400 | if (ring->map.handle == NULL) { |
| 1401 | DRM_ERROR("can not ioremap virtual address for" |
| 1402 | " ring buffer\n"); |
| 1403 | return -ENOMEM; |
| 1404 | } |
| 1405 | |
| 1406 | ring->virtual_start = (void __force __iomem *)ring->map.handle; |
| 1407 | return 0; |
| 1408 | } |
| 1409 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1410 | int intel_init_bsd_ring_buffer(struct drm_device *dev) |
| 1411 | { |
| 1412 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1413 | struct intel_ring_buffer *ring = &dev_priv->ring[VCS]; |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1414 | |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1415 | ring->name = "bsd ring"; |
| 1416 | ring->id = VCS; |
| 1417 | |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame^] | 1418 | ring->write_tail = ring_write_tail; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1419 | if (IS_GEN6(dev) || IS_GEN7(dev)) { |
| 1420 | ring->mmio_base = GEN6_BSD_RING_BASE; |
Daniel Vetter | 0fd2c20 | 2012-04-11 22:12:55 +0200 | [diff] [blame^] | 1421 | /* gen6 bsd needs a special wa for tail updates */ |
| 1422 | if (IS_GEN6(dev)) |
| 1423 | ring->write_tail = gen6_bsd_ring_write_tail; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1424 | ring->flush = gen6_ring_flush; |
| 1425 | ring->add_request = gen6_add_request; |
| 1426 | ring->get_seqno = gen6_ring_get_seqno; |
| 1427 | ring->irq_enable_mask = GEN6_BSD_USER_INTERRUPT; |
| 1428 | ring->irq_get = gen6_ring_get_irq; |
| 1429 | ring->irq_put = gen6_ring_put_irq; |
| 1430 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1431 | ring->sync_to = gen6_ring_sync; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1432 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_VR; |
| 1433 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_INVALID; |
| 1434 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_VB; |
| 1435 | ring->signal_mbox[0] = GEN6_RVSYNC; |
| 1436 | ring->signal_mbox[1] = GEN6_BVSYNC; |
| 1437 | } else { |
| 1438 | ring->mmio_base = BSD_RING_BASE; |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1439 | ring->flush = bsd_ring_flush; |
| 1440 | ring->add_request = ring_add_request; |
| 1441 | ring->get_seqno = ring_get_seqno; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1442 | if (IS_GEN5(dev)) { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1443 | ring->irq_enable_mask = GT_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1444 | ring->irq_get = gen5_ring_get_irq; |
| 1445 | ring->irq_put = gen5_ring_put_irq; |
| 1446 | } else { |
Daniel Vetter | e367031 | 2012-04-11 22:12:53 +0200 | [diff] [blame] | 1447 | ring->irq_enable_mask = I915_BSD_USER_INTERRUPT; |
Daniel Vetter | e48d863 | 2012-04-11 22:12:54 +0200 | [diff] [blame] | 1448 | ring->irq_get = i9xx_ring_get_irq; |
| 1449 | ring->irq_put = i9xx_ring_put_irq; |
| 1450 | } |
Daniel Vetter | 58fa383 | 2012-04-11 22:12:49 +0200 | [diff] [blame] | 1451 | ring->dispatch_execbuffer = ring_dispatch_execbuffer; |
| 1452 | } |
| 1453 | ring->init = init_ring_common; |
| 1454 | |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1455 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1456 | return intel_init_ring_buffer(dev, ring); |
Xiang, Haihao | 5c1143b | 2010-09-16 10:43:11 +0800 | [diff] [blame] | 1457 | } |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1458 | |
| 1459 | int intel_init_blt_ring_buffer(struct drm_device *dev) |
| 1460 | { |
| 1461 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1462 | struct intel_ring_buffer *ring = &dev_priv->ring[BCS]; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1463 | |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1464 | ring->name = "blitter ring"; |
| 1465 | ring->id = BCS; |
| 1466 | |
| 1467 | ring->mmio_base = BLT_RING_BASE; |
| 1468 | ring->write_tail = ring_write_tail; |
| 1469 | ring->flush = blt_ring_flush; |
| 1470 | ring->add_request = gen6_add_request; |
| 1471 | ring->get_seqno = gen6_ring_get_seqno; |
| 1472 | ring->irq_enable_mask = GEN6_BLITTER_USER_INTERRUPT; |
| 1473 | ring->irq_get = gen6_ring_get_irq; |
| 1474 | ring->irq_put = gen6_ring_put_irq; |
| 1475 | ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer; |
Daniel Vetter | 686cb5f | 2012-04-11 22:12:52 +0200 | [diff] [blame] | 1476 | ring->sync_to = gen6_ring_sync; |
Daniel Vetter | 3535d9d | 2012-04-11 22:12:50 +0200 | [diff] [blame] | 1477 | ring->semaphore_register[0] = MI_SEMAPHORE_SYNC_BR; |
| 1478 | ring->semaphore_register[1] = MI_SEMAPHORE_SYNC_BV; |
| 1479 | ring->semaphore_register[2] = MI_SEMAPHORE_SYNC_INVALID; |
| 1480 | ring->signal_mbox[0] = GEN6_RBSYNC; |
| 1481 | ring->signal_mbox[1] = GEN6_VBSYNC; |
| 1482 | ring->init = init_ring_common; |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1483 | |
Chris Wilson | 1ec14ad | 2010-12-04 11:30:53 +0000 | [diff] [blame] | 1484 | return intel_init_ring_buffer(dev, ring); |
Chris Wilson | 549f736 | 2010-10-19 11:19:32 +0100 | [diff] [blame] | 1485 | } |