Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1 | /* |
| 2 | * RTL8XXXU mac80211 USB driver |
| 3 | * |
| 4 | * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com> |
| 5 | * |
| 6 | * Portions, notably calibration code: |
| 7 | * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved. |
| 8 | * |
| 9 | * This driver was written as a replacement for the vendor provided |
| 10 | * rtl8723au driver. As the Realtek 8xxx chips are very similar in |
| 11 | * their programming interface, I have started adding support for |
| 12 | * additional 8xxx chips like the 8192cu, 8188cus, etc. |
| 13 | * |
| 14 | * This program is free software; you can redistribute it and/or modify it |
| 15 | * under the terms of version 2 of the GNU General Public License as |
| 16 | * published by the Free Software Foundation. |
| 17 | * |
| 18 | * This program is distributed in the hope that it will be useful, but WITHOUT |
| 19 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
| 20 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
| 21 | * more details. |
| 22 | */ |
| 23 | |
| 24 | #include <linux/init.h> |
| 25 | #include <linux/kernel.h> |
| 26 | #include <linux/sched.h> |
| 27 | #include <linux/errno.h> |
| 28 | #include <linux/slab.h> |
| 29 | #include <linux/module.h> |
| 30 | #include <linux/spinlock.h> |
| 31 | #include <linux/list.h> |
| 32 | #include <linux/usb.h> |
| 33 | #include <linux/netdevice.h> |
| 34 | #include <linux/etherdevice.h> |
| 35 | #include <linux/ethtool.h> |
| 36 | #include <linux/wireless.h> |
| 37 | #include <linux/firmware.h> |
| 38 | #include <linux/moduleparam.h> |
| 39 | #include <net/mac80211.h> |
| 40 | #include "rtl8xxxu.h" |
| 41 | #include "rtl8xxxu_regs.h" |
| 42 | |
| 43 | #define DRIVER_NAME "rtl8xxxu" |
| 44 | |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 45 | static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 46 | static bool rtl8xxxu_ht40_2g; |
| 47 | |
| 48 | MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>"); |
| 49 | MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver"); |
| 50 | MODULE_LICENSE("GPL"); |
| 51 | MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin"); |
| 52 | MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin"); |
| 53 | MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin"); |
| 54 | MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin"); |
| 55 | MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin"); |
| 56 | MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin"); |
Jes Sorensen | b001e08 | 2016-02-29 17:04:02 -0500 | [diff] [blame] | 57 | MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin"); |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 58 | MODULE_FIRMWARE("rtlwifi/rtl8723bu_nic.bin"); |
| 59 | MODULE_FIRMWARE("rtlwifi/rtl8723bu_bt.bin"); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 60 | |
| 61 | module_param_named(debug, rtl8xxxu_debug, int, 0600); |
| 62 | MODULE_PARM_DESC(debug, "Set debug mask"); |
| 63 | module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600); |
| 64 | MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band"); |
| 65 | |
| 66 | #define USB_VENDOR_ID_REALTEK 0x0bda |
| 67 | /* Minimum IEEE80211_MAX_FRAME_LEN */ |
| 68 | #define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN |
| 69 | #define RTL8XXXU_RX_URBS 32 |
| 70 | #define RTL8XXXU_RX_URB_PENDING_WATER 8 |
| 71 | #define RTL8XXXU_TX_URBS 64 |
| 72 | #define RTL8XXXU_TX_URB_LOW_WATER 25 |
| 73 | #define RTL8XXXU_TX_URB_HIGH_WATER 32 |
| 74 | |
| 75 | static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, |
| 76 | struct rtl8xxxu_rx_urb *rx_urb); |
| 77 | |
| 78 | static struct ieee80211_rate rtl8xxxu_rates[] = { |
| 79 | { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 }, |
| 80 | { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 }, |
| 81 | { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 }, |
| 82 | { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 }, |
| 83 | { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 }, |
| 84 | { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 }, |
| 85 | { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 }, |
| 86 | { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 }, |
| 87 | { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 }, |
| 88 | { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 }, |
| 89 | { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 }, |
| 90 | { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 }, |
| 91 | }; |
| 92 | |
| 93 | static struct ieee80211_channel rtl8xxxu_channels_2g[] = { |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 94 | { .band = NL80211_BAND_2GHZ, .center_freq = 2412, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 95 | .hw_value = 1, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 96 | { .band = NL80211_BAND_2GHZ, .center_freq = 2417, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 97 | .hw_value = 2, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 98 | { .band = NL80211_BAND_2GHZ, .center_freq = 2422, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 99 | .hw_value = 3, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 100 | { .band = NL80211_BAND_2GHZ, .center_freq = 2427, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 101 | .hw_value = 4, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 102 | { .band = NL80211_BAND_2GHZ, .center_freq = 2432, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 103 | .hw_value = 5, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 104 | { .band = NL80211_BAND_2GHZ, .center_freq = 2437, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 105 | .hw_value = 6, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 106 | { .band = NL80211_BAND_2GHZ, .center_freq = 2442, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 107 | .hw_value = 7, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 108 | { .band = NL80211_BAND_2GHZ, .center_freq = 2447, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 109 | .hw_value = 8, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 110 | { .band = NL80211_BAND_2GHZ, .center_freq = 2452, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 111 | .hw_value = 9, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 112 | { .band = NL80211_BAND_2GHZ, .center_freq = 2457, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 113 | .hw_value = 10, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 114 | { .band = NL80211_BAND_2GHZ, .center_freq = 2462, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 115 | .hw_value = 11, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 116 | { .band = NL80211_BAND_2GHZ, .center_freq = 2467, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 117 | .hw_value = 12, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 118 | { .band = NL80211_BAND_2GHZ, .center_freq = 2472, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 119 | .hw_value = 13, .max_power = 30 }, |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 120 | { .band = NL80211_BAND_2GHZ, .center_freq = 2484, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 121 | .hw_value = 14, .max_power = 30 } |
| 122 | }; |
| 123 | |
| 124 | static struct ieee80211_supported_band rtl8xxxu_supported_band = { |
| 125 | .channels = rtl8xxxu_channels_2g, |
| 126 | .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g), |
| 127 | .bitrates = rtl8xxxu_rates, |
| 128 | .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates), |
| 129 | }; |
| 130 | |
| 131 | static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = { |
| 132 | {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00}, |
| 133 | {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, |
| 134 | {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00}, |
| 135 | {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05}, |
| 136 | {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01}, |
| 137 | {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f}, |
| 138 | {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72}, |
| 139 | {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08}, |
| 140 | {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, |
| 141 | {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, |
| 142 | {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, |
| 143 | {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, |
| 144 | {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, |
| 145 | {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, |
| 146 | {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16}, |
| 147 | {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00}, |
| 148 | {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02}, |
| 149 | {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, |
| 150 | {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, |
| 151 | {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, |
| 152 | {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, |
| 153 | {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff}, |
| 154 | }; |
| 155 | |
Jes Sorensen | b7dd8ff | 2016-02-29 17:04:17 -0500 | [diff] [blame] | 156 | static struct rtl8xxxu_reg8val rtl8723b_mac_init_table[] = { |
| 157 | {0x02f, 0x30}, {0x035, 0x00}, {0x039, 0x08}, {0x04e, 0xe0}, |
| 158 | {0x064, 0x00}, {0x067, 0x20}, {0x428, 0x0a}, {0x429, 0x10}, |
| 159 | {0x430, 0x00}, {0x431, 0x00}, |
| 160 | {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, |
| 161 | {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05}, |
| 162 | {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01}, |
| 163 | {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00}, |
| 164 | {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f}, |
| 165 | {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00}, |
| 166 | {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f}, |
| 167 | {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66}, |
| 168 | {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, |
| 169 | {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, |
| 170 | {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, |
| 171 | {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, |
| 172 | {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, |
| 173 | {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, |
| 174 | {0x516, 0x0a}, {0x525, 0x4f}, |
| 175 | {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, |
| 176 | {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, |
| 177 | {0x620, 0xff}, {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, |
| 178 | {0x624, 0xff}, {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, |
| 179 | {0x638, 0x50}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, |
| 180 | {0x63f, 0x0e}, {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, |
| 181 | {0x652, 0xc8}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, |
| 182 | {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, |
| 183 | {0x70a, 0x65}, {0x70b, 0x87}, {0x765, 0x18}, {0x76e, 0x04}, |
| 184 | {0xffff, 0xff}, |
| 185 | }; |
| 186 | |
Jes Sorensen | c606e66 | 2016-04-07 14:19:16 -0400 | [diff] [blame] | 187 | static struct rtl8xxxu_reg8val rtl8192e_mac_init_table[] = { |
| 188 | {0x011, 0xeb}, {0x012, 0x07}, {0x014, 0x75}, {0x303, 0xa7}, |
| 189 | {0x428, 0x0a}, {0x429, 0x10}, {0x430, 0x00}, {0x431, 0x00}, |
| 190 | {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05}, |
| 191 | {0x436, 0x07}, {0x437, 0x08}, {0x43c, 0x04}, {0x43d, 0x05}, |
| 192 | {0x43e, 0x07}, {0x43f, 0x08}, {0x440, 0x5d}, {0x441, 0x01}, |
| 193 | {0x442, 0x00}, {0x444, 0x10}, {0x445, 0x00}, {0x446, 0x00}, |
| 194 | {0x447, 0x00}, {0x448, 0x00}, {0x449, 0xf0}, {0x44a, 0x0f}, |
| 195 | {0x44b, 0x3e}, {0x44c, 0x10}, {0x44d, 0x00}, {0x44e, 0x00}, |
| 196 | {0x44f, 0x00}, {0x450, 0x00}, {0x451, 0xf0}, {0x452, 0x0f}, |
| 197 | {0x453, 0x00}, {0x456, 0x5e}, {0x460, 0x66}, {0x461, 0x66}, |
| 198 | {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff}, {0x4cd, 0xff}, |
| 199 | {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2}, {0x502, 0x2f}, |
| 200 | {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3}, {0x506, 0x5e}, |
| 201 | {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4}, {0x50a, 0x5e}, |
| 202 | {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4}, {0x50e, 0x00}, |
| 203 | {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a}, {0x516, 0x0a}, |
| 204 | {0x525, 0x4f}, {0x540, 0x12}, {0x541, 0x64}, {0x550, 0x10}, |
| 205 | {0x551, 0x10}, {0x559, 0x02}, {0x55c, 0x50}, {0x55d, 0xff}, |
| 206 | {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a}, {0x620, 0xff}, |
| 207 | {0x621, 0xff}, {0x622, 0xff}, {0x623, 0xff}, {0x624, 0xff}, |
| 208 | {0x625, 0xff}, {0x626, 0xff}, {0x627, 0xff}, {0x638, 0x50}, |
| 209 | {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e}, {0x63f, 0x0e}, |
| 210 | {0x640, 0x40}, {0x642, 0x40}, {0x643, 0x00}, {0x652, 0xc8}, |
| 211 | {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43}, {0x702, 0x65}, |
| 212 | {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43}, {0x70a, 0x65}, |
| 213 | {0x70b, 0x87}, |
| 214 | {0xffff, 0xff}, |
| 215 | }; |
| 216 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 217 | static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = { |
| 218 | {0x800, 0x80040000}, {0x804, 0x00000003}, |
| 219 | {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, |
| 220 | {0x810, 0x10001331}, {0x814, 0x020c3d10}, |
| 221 | {0x818, 0x02200385}, {0x81c, 0x00000000}, |
| 222 | {0x820, 0x01000100}, {0x824, 0x00390004}, |
| 223 | {0x828, 0x00000000}, {0x82c, 0x00000000}, |
| 224 | {0x830, 0x00000000}, {0x834, 0x00000000}, |
| 225 | {0x838, 0x00000000}, {0x83c, 0x00000000}, |
| 226 | {0x840, 0x00010000}, {0x844, 0x00000000}, |
| 227 | {0x848, 0x00000000}, {0x84c, 0x00000000}, |
| 228 | {0x850, 0x00000000}, {0x854, 0x00000000}, |
| 229 | {0x858, 0x569a569a}, {0x85c, 0x001b25a4}, |
| 230 | {0x860, 0x66f60110}, {0x864, 0x061f0130}, |
| 231 | {0x868, 0x00000000}, {0x86c, 0x32323200}, |
| 232 | {0x870, 0x07000760}, {0x874, 0x22004000}, |
| 233 | {0x878, 0x00000808}, {0x87c, 0x00000000}, |
| 234 | {0x880, 0xc0083070}, {0x884, 0x000004d5}, |
| 235 | {0x888, 0x00000000}, {0x88c, 0xccc000c0}, |
| 236 | {0x890, 0x00000800}, {0x894, 0xfffffffe}, |
| 237 | {0x898, 0x40302010}, {0x89c, 0x00706050}, |
| 238 | {0x900, 0x00000000}, {0x904, 0x00000023}, |
| 239 | {0x908, 0x00000000}, {0x90c, 0x81121111}, |
| 240 | {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, |
| 241 | {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, |
| 242 | {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, |
| 243 | {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, |
| 244 | {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, |
| 245 | {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, |
| 246 | {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, |
| 247 | {0xa78, 0x00000900}, |
| 248 | {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, |
| 249 | {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, |
| 250 | {0xc10, 0x08800000}, {0xc14, 0x40000100}, |
| 251 | {0xc18, 0x08800000}, {0xc1c, 0x40000100}, |
| 252 | {0xc20, 0x00000000}, {0xc24, 0x00000000}, |
| 253 | {0xc28, 0x00000000}, {0xc2c, 0x00000000}, |
| 254 | {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, |
| 255 | {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, |
| 256 | {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, |
| 257 | {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, |
| 258 | {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, |
| 259 | {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, |
| 260 | {0xc60, 0x00000000}, {0xc64, 0x7112848b}, |
| 261 | {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, |
| 262 | {0xc70, 0x2c7f000d}, {0xc74, 0x018610db}, |
| 263 | {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, |
| 264 | {0xc80, 0x40000100}, {0xc84, 0x20f60000}, |
| 265 | {0xc88, 0x40000100}, {0xc8c, 0x20200000}, |
| 266 | {0xc90, 0x00121820}, {0xc94, 0x00000000}, |
| 267 | {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, |
| 268 | {0xca0, 0x00000000}, {0xca4, 0x00000080}, |
| 269 | {0xca8, 0x00000000}, {0xcac, 0x00000000}, |
| 270 | {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, |
| 271 | {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, |
| 272 | {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, |
| 273 | {0xcc8, 0x00000000}, {0xccc, 0x00000000}, |
| 274 | {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, |
| 275 | {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, |
| 276 | {0xce0, 0x00222222}, {0xce4, 0x00000000}, |
| 277 | {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, |
| 278 | {0xd00, 0x00080740}, {0xd04, 0x00020401}, |
| 279 | {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, |
| 280 | {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, |
| 281 | {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, |
| 282 | {0xd30, 0x00000000}, {0xd34, 0x80608000}, |
| 283 | {0xd38, 0x00000000}, {0xd3c, 0x00027293}, |
| 284 | {0xd40, 0x00000000}, {0xd44, 0x00000000}, |
| 285 | {0xd48, 0x00000000}, {0xd4c, 0x00000000}, |
| 286 | {0xd50, 0x6437140a}, {0xd54, 0x00000000}, |
| 287 | {0xd58, 0x00000000}, {0xd5c, 0x30032064}, |
| 288 | {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, |
| 289 | {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, |
| 290 | {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, |
| 291 | {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, |
| 292 | {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, |
| 293 | {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, |
| 294 | {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, |
| 295 | {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, |
| 296 | {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, |
| 297 | {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, |
| 298 | {0xe44, 0x01004800}, {0xe48, 0xfb000000}, |
| 299 | {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, |
| 300 | {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, |
| 301 | {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, |
| 302 | {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0}, |
| 303 | {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0}, |
| 304 | {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0}, |
| 305 | {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0}, |
| 306 | {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0}, |
| 307 | {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0}, |
| 308 | {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0}, |
| 309 | {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0}, |
| 310 | {0xf14, 0x00000003}, {0xf4c, 0x00000000}, |
| 311 | {0xf00, 0x00000300}, |
| 312 | {0xffff, 0xffffffff}, |
| 313 | }; |
| 314 | |
Jes Sorensen | 36c3258 | 2016-02-29 17:04:14 -0500 | [diff] [blame] | 315 | static struct rtl8xxxu_reg32val rtl8723b_phy_1t_init_table[] = { |
| 316 | {0x800, 0x80040000}, {0x804, 0x00000003}, |
| 317 | {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, |
| 318 | {0x810, 0x10001331}, {0x814, 0x020c3d10}, |
| 319 | {0x818, 0x02200385}, {0x81c, 0x00000000}, |
| 320 | {0x820, 0x01000100}, {0x824, 0x00190204}, |
| 321 | {0x828, 0x00000000}, {0x82c, 0x00000000}, |
| 322 | {0x830, 0x00000000}, {0x834, 0x00000000}, |
| 323 | {0x838, 0x00000000}, {0x83c, 0x00000000}, |
| 324 | {0x840, 0x00010000}, {0x844, 0x00000000}, |
| 325 | {0x848, 0x00000000}, {0x84c, 0x00000000}, |
| 326 | {0x850, 0x00000000}, {0x854, 0x00000000}, |
| 327 | {0x858, 0x569a11a9}, {0x85c, 0x01000014}, |
| 328 | {0x860, 0x66f60110}, {0x864, 0x061f0649}, |
| 329 | {0x868, 0x00000000}, {0x86c, 0x27272700}, |
| 330 | {0x870, 0x07000760}, {0x874, 0x25004000}, |
| 331 | {0x878, 0x00000808}, {0x87c, 0x00000000}, |
| 332 | {0x880, 0xb0000c1c}, {0x884, 0x00000001}, |
| 333 | {0x888, 0x00000000}, {0x88c, 0xccc000c0}, |
| 334 | {0x890, 0x00000800}, {0x894, 0xfffffffe}, |
| 335 | {0x898, 0x40302010}, {0x89c, 0x00706050}, |
| 336 | {0x900, 0x00000000}, {0x904, 0x00000023}, |
| 337 | {0x908, 0x00000000}, {0x90c, 0x81121111}, |
| 338 | {0x910, 0x00000002}, {0x914, 0x00000201}, |
| 339 | {0xa00, 0x00d047c8}, {0xa04, 0x80ff800c}, |
| 340 | {0xa08, 0x8c838300}, {0xa0c, 0x2e7f120f}, |
| 341 | {0xa10, 0x9500bb78}, {0xa14, 0x1114d028}, |
| 342 | {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, |
| 343 | {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, |
| 344 | {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, |
| 345 | {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, |
| 346 | {0xa78, 0x00000900}, {0xa7c, 0x225b0606}, |
| 347 | {0xa80, 0x21806490}, {0xb2c, 0x00000000}, |
| 348 | {0xc00, 0x48071d40}, {0xc04, 0x03a05611}, |
| 349 | {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, |
| 350 | {0xc10, 0x08800000}, {0xc14, 0x40000100}, |
| 351 | {0xc18, 0x08800000}, {0xc1c, 0x40000100}, |
| 352 | {0xc20, 0x00000000}, {0xc24, 0x00000000}, |
| 353 | {0xc28, 0x00000000}, {0xc2c, 0x00000000}, |
| 354 | {0xc30, 0x69e9ac44}, {0xc34, 0x469652af}, |
| 355 | {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, |
| 356 | {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, |
| 357 | {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, |
| 358 | {0xc50, 0x69553420}, {0xc54, 0x43bc0094}, |
| 359 | {0xc58, 0x00013149}, {0xc5c, 0x00250492}, |
| 360 | {0xc60, 0x00000000}, {0xc64, 0x7112848b}, |
| 361 | {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, |
| 362 | {0xc70, 0x2c7f000d}, {0xc74, 0x020610db}, |
| 363 | {0xc78, 0x0000001f}, {0xc7c, 0x00b91612}, |
| 364 | {0xc80, 0x390000e4}, {0xc84, 0x20f60000}, |
| 365 | {0xc88, 0x40000100}, {0xc8c, 0x20200000}, |
| 366 | {0xc90, 0x00020e1a}, {0xc94, 0x00000000}, |
| 367 | {0xc98, 0x00020e1a}, {0xc9c, 0x00007f7f}, |
| 368 | {0xca0, 0x00000000}, {0xca4, 0x000300a0}, |
| 369 | {0xca8, 0x00000000}, {0xcac, 0x00000000}, |
| 370 | {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, |
| 371 | {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, |
| 372 | {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, |
| 373 | {0xcc8, 0x00000000}, {0xccc, 0x00000000}, |
| 374 | {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, |
| 375 | {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, |
| 376 | {0xce0, 0x00222222}, {0xce4, 0x00000000}, |
| 377 | {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, |
| 378 | {0xd00, 0x00000740}, {0xd04, 0x40020401}, |
| 379 | {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, |
| 380 | {0xd10, 0xa0633333}, {0xd14, 0x3333bc53}, |
| 381 | {0xd18, 0x7a8f5b6f}, {0xd2c, 0xcc979975}, |
| 382 | {0xd30, 0x00000000}, {0xd34, 0x80608000}, |
| 383 | {0xd38, 0x00000000}, {0xd3c, 0x00127353}, |
| 384 | {0xd40, 0x00000000}, {0xd44, 0x00000000}, |
| 385 | {0xd48, 0x00000000}, {0xd4c, 0x00000000}, |
| 386 | {0xd50, 0x6437140a}, {0xd54, 0x00000000}, |
| 387 | {0xd58, 0x00000282}, {0xd5c, 0x30032064}, |
| 388 | {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, |
| 389 | {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, |
| 390 | {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, |
| 391 | {0xd78, 0x000e3c24}, {0xe00, 0x2d2d2d2d}, |
| 392 | {0xe04, 0x2d2d2d2d}, {0xe08, 0x0390272d}, |
| 393 | {0xe10, 0x2d2d2d2d}, {0xe14, 0x2d2d2d2d}, |
| 394 | {0xe18, 0x2d2d2d2d}, {0xe1c, 0x2d2d2d2d}, |
| 395 | {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, |
| 396 | {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, |
| 397 | {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, |
| 398 | {0xe44, 0x01004800}, {0xe48, 0xfb000000}, |
| 399 | {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, |
| 400 | {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, |
| 401 | {0xe5c, 0x28160d05}, {0xe60, 0x00000008}, |
| 402 | {0xe68, 0x001b2556}, {0xe6c, 0x00c00096}, |
| 403 | {0xe70, 0x00c00096}, {0xe74, 0x01000056}, |
| 404 | {0xe78, 0x01000014}, {0xe7c, 0x01000056}, |
| 405 | {0xe80, 0x01000014}, {0xe84, 0x00c00096}, |
| 406 | {0xe88, 0x01000056}, {0xe8c, 0x00c00096}, |
| 407 | {0xed0, 0x00c00096}, {0xed4, 0x00c00096}, |
| 408 | {0xed8, 0x00c00096}, {0xedc, 0x000000d6}, |
| 409 | {0xee0, 0x000000d6}, {0xeec, 0x01c00016}, |
| 410 | {0xf14, 0x00000003}, {0xf4c, 0x00000000}, |
| 411 | {0xf00, 0x00000300}, |
| 412 | {0x820, 0x01000100}, {0x800, 0x83040000}, |
| 413 | {0xffff, 0xffffffff}, |
| 414 | }; |
| 415 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 416 | static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = { |
| 417 | {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, |
| 418 | {0x800, 0x80040002}, {0x804, 0x00000003}, |
| 419 | {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, |
| 420 | {0x810, 0x10000330}, {0x814, 0x020c3d10}, |
| 421 | {0x818, 0x02200385}, {0x81c, 0x00000000}, |
| 422 | {0x820, 0x01000100}, {0x824, 0x00390004}, |
| 423 | {0x828, 0x01000100}, {0x82c, 0x00390004}, |
| 424 | {0x830, 0x27272727}, {0x834, 0x27272727}, |
| 425 | {0x838, 0x27272727}, {0x83c, 0x27272727}, |
| 426 | {0x840, 0x00010000}, {0x844, 0x00010000}, |
| 427 | {0x848, 0x27272727}, {0x84c, 0x27272727}, |
| 428 | {0x850, 0x00000000}, {0x854, 0x00000000}, |
| 429 | {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4}, |
| 430 | {0x860, 0x66e60230}, {0x864, 0x061f0130}, |
| 431 | {0x868, 0x27272727}, {0x86c, 0x2b2b2b27}, |
| 432 | {0x870, 0x07000700}, {0x874, 0x22184000}, |
| 433 | {0x878, 0x08080808}, {0x87c, 0x00000000}, |
| 434 | {0x880, 0xc0083070}, {0x884, 0x000004d5}, |
| 435 | {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, |
| 436 | {0x890, 0x00000800}, {0x894, 0xfffffffe}, |
| 437 | {0x898, 0x40302010}, {0x89c, 0x00706050}, |
| 438 | {0x900, 0x00000000}, {0x904, 0x00000023}, |
| 439 | {0x908, 0x00000000}, {0x90c, 0x81121313}, |
| 440 | {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c}, |
| 441 | {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f}, |
| 442 | {0xa10, 0x9500bb78}, {0xa14, 0x11144028}, |
| 443 | {0xa18, 0x00881117}, {0xa1c, 0x89140f00}, |
| 444 | {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317}, |
| 445 | {0xa28, 0x00000204}, {0xa2c, 0x00d30000}, |
| 446 | {0xa70, 0x101fbf00}, {0xa74, 0x00000007}, |
| 447 | {0xc00, 0x48071d40}, {0xc04, 0x03a05633}, |
| 448 | {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c}, |
| 449 | {0xc10, 0x08800000}, {0xc14, 0x40000100}, |
| 450 | {0xc18, 0x08800000}, {0xc1c, 0x40000100}, |
| 451 | {0xc20, 0x00000000}, {0xc24, 0x00000000}, |
| 452 | {0xc28, 0x00000000}, {0xc2c, 0x00000000}, |
| 453 | {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf}, |
| 454 | {0xc38, 0x49795994}, {0xc3c, 0x0a97971c}, |
| 455 | {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7}, |
| 456 | {0xc48, 0xec020107}, {0xc4c, 0x007f037f}, |
| 457 | {0xc50, 0x69543420}, {0xc54, 0x43bc0094}, |
| 458 | {0xc58, 0x69543420}, {0xc5c, 0x433c0094}, |
| 459 | {0xc60, 0x00000000}, {0xc64, 0x5116848b}, |
| 460 | {0xc68, 0x47c00bff}, {0xc6c, 0x00000036}, |
| 461 | {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b}, |
| 462 | {0xc78, 0x0000001f}, {0xc7c, 0x00b99612}, |
| 463 | {0xc80, 0x40000100}, {0xc84, 0x20f60000}, |
| 464 | {0xc88, 0x40000100}, {0xc8c, 0xa0e40000}, |
| 465 | {0xc90, 0x00121820}, {0xc94, 0x00000000}, |
| 466 | {0xc98, 0x00121820}, {0xc9c, 0x00007f7f}, |
| 467 | {0xca0, 0x00000000}, {0xca4, 0x00000080}, |
| 468 | {0xca8, 0x00000000}, {0xcac, 0x00000000}, |
| 469 | {0xcb0, 0x00000000}, {0xcb4, 0x00000000}, |
| 470 | {0xcb8, 0x00000000}, {0xcbc, 0x28000000}, |
| 471 | {0xcc0, 0x00000000}, {0xcc4, 0x00000000}, |
| 472 | {0xcc8, 0x00000000}, {0xccc, 0x00000000}, |
| 473 | {0xcd0, 0x00000000}, {0xcd4, 0x00000000}, |
| 474 | {0xcd8, 0x64b22427}, {0xcdc, 0x00766932}, |
| 475 | {0xce0, 0x00222222}, {0xce4, 0x00000000}, |
| 476 | {0xce8, 0x37644302}, {0xcec, 0x2f97d40c}, |
| 477 | {0xd00, 0x00080740}, {0xd04, 0x00020403}, |
| 478 | {0xd08, 0x0000907f}, {0xd0c, 0x20010201}, |
| 479 | {0xd10, 0xa0633333}, {0xd14, 0x3333bc43}, |
| 480 | {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975}, |
| 481 | {0xd30, 0x00000000}, {0xd34, 0x80608000}, |
| 482 | {0xd38, 0x00000000}, {0xd3c, 0x00027293}, |
| 483 | {0xd40, 0x00000000}, {0xd44, 0x00000000}, |
| 484 | {0xd48, 0x00000000}, {0xd4c, 0x00000000}, |
| 485 | {0xd50, 0x6437140a}, {0xd54, 0x00000000}, |
| 486 | {0xd58, 0x00000000}, {0xd5c, 0x30032064}, |
| 487 | {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, |
| 488 | {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, |
| 489 | {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, |
| 490 | {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a}, |
| 491 | {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a}, |
| 492 | {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a}, |
| 493 | {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a}, |
| 494 | {0xe28, 0x00000000}, {0xe30, 0x1000dc1f}, |
| 495 | {0xe34, 0x10008c1f}, {0xe38, 0x02140102}, |
| 496 | {0xe3c, 0x681604c2}, {0xe40, 0x01007c00}, |
| 497 | {0xe44, 0x01004800}, {0xe48, 0xfb000000}, |
| 498 | {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f}, |
| 499 | {0xe54, 0x10008c1f}, {0xe58, 0x02140102}, |
| 500 | {0xe5c, 0x28160d05}, {0xe60, 0x00000010}, |
| 501 | {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4}, |
| 502 | {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4}, |
| 503 | {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4}, |
| 504 | {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4}, |
| 505 | {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4}, |
| 506 | {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4}, |
| 507 | {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4}, |
| 508 | {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4}, |
| 509 | {0xf14, 0x00000003}, {0xf4c, 0x00000000}, |
| 510 | {0xf00, 0x00000300}, |
| 511 | {0xffff, 0xffffffff}, |
| 512 | }; |
| 513 | |
| 514 | static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = { |
| 515 | {0x024, 0x0011800f}, {0x028, 0x00ffdb83}, |
| 516 | {0x040, 0x000c0004}, {0x800, 0x80040000}, |
| 517 | {0x804, 0x00000001}, {0x808, 0x0000fc00}, |
| 518 | {0x80c, 0x0000000a}, {0x810, 0x10005388}, |
| 519 | {0x814, 0x020c3d10}, {0x818, 0x02200385}, |
| 520 | {0x81c, 0x00000000}, {0x820, 0x01000100}, |
| 521 | {0x824, 0x00390204}, {0x828, 0x00000000}, |
| 522 | {0x82c, 0x00000000}, {0x830, 0x00000000}, |
| 523 | {0x834, 0x00000000}, {0x838, 0x00000000}, |
| 524 | {0x83c, 0x00000000}, {0x840, 0x00010000}, |
| 525 | {0x844, 0x00000000}, {0x848, 0x00000000}, |
| 526 | {0x84c, 0x00000000}, {0x850, 0x00000000}, |
| 527 | {0x854, 0x00000000}, {0x858, 0x569a569a}, |
| 528 | {0x85c, 0x001b25a4}, {0x860, 0x66e60230}, |
| 529 | {0x864, 0x061f0130}, {0x868, 0x00000000}, |
| 530 | {0x86c, 0x20202000}, {0x870, 0x03000300}, |
| 531 | {0x874, 0x22004000}, {0x878, 0x00000808}, |
| 532 | {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070}, |
| 533 | {0x884, 0x000004d5}, {0x888, 0x00000000}, |
| 534 | {0x88c, 0xccc000c0}, {0x890, 0x00000800}, |
| 535 | {0x894, 0xfffffffe}, {0x898, 0x40302010}, |
| 536 | {0x89c, 0x00706050}, {0x900, 0x00000000}, |
| 537 | {0x904, 0x00000023}, {0x908, 0x00000000}, |
| 538 | {0x90c, 0x81121111}, {0xa00, 0x00d047c8}, |
| 539 | {0xa04, 0x80ff000c}, {0xa08, 0x8c838300}, |
| 540 | {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78}, |
| 541 | {0xa14, 0x11144028}, {0xa18, 0x00881117}, |
| 542 | {0xa1c, 0x89140f00}, {0xa20, 0x15160000}, |
| 543 | {0xa24, 0x070b0f12}, {0xa28, 0x00000104}, |
| 544 | {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00}, |
| 545 | {0xa74, 0x00000007}, {0xc00, 0x48071d40}, |
| 546 | {0xc04, 0x03a05611}, {0xc08, 0x000000e4}, |
| 547 | {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, |
| 548 | {0xc14, 0x40000100}, {0xc18, 0x08800000}, |
| 549 | {0xc1c, 0x40000100}, {0xc20, 0x00000000}, |
| 550 | {0xc24, 0x00000000}, {0xc28, 0x00000000}, |
| 551 | {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44}, |
| 552 | {0xc34, 0x469652cf}, {0xc38, 0x49795994}, |
| 553 | {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, |
| 554 | {0xc44, 0x000100b7}, {0xc48, 0xec020107}, |
| 555 | {0xc4c, 0x007f037f}, {0xc50, 0x6954342e}, |
| 556 | {0xc54, 0x43bc0094}, {0xc58, 0x6954342f}, |
| 557 | {0xc5c, 0x433c0094}, {0xc60, 0x00000000}, |
| 558 | {0xc64, 0x5116848b}, {0xc68, 0x47c00bff}, |
| 559 | {0xc6c, 0x00000036}, {0xc70, 0x2c46000d}, |
| 560 | {0xc74, 0x018610db}, {0xc78, 0x0000001f}, |
| 561 | {0xc7c, 0x00b91612}, {0xc80, 0x24000090}, |
| 562 | {0xc84, 0x20f60000}, {0xc88, 0x24000090}, |
| 563 | {0xc8c, 0x20200000}, {0xc90, 0x00121820}, |
| 564 | {0xc94, 0x00000000}, {0xc98, 0x00121820}, |
| 565 | {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, |
| 566 | {0xca4, 0x00000080}, {0xca8, 0x00000000}, |
| 567 | {0xcac, 0x00000000}, {0xcb0, 0x00000000}, |
| 568 | {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, |
| 569 | {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, |
| 570 | {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, |
| 571 | {0xccc, 0x00000000}, {0xcd0, 0x00000000}, |
| 572 | {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, |
| 573 | {0xcdc, 0x00766932}, {0xce0, 0x00222222}, |
| 574 | {0xce4, 0x00000000}, {0xce8, 0x37644302}, |
| 575 | {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, |
| 576 | {0xd04, 0x00020401}, {0xd08, 0x0000907f}, |
| 577 | {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, |
| 578 | {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, |
| 579 | {0xd2c, 0xcc979975}, {0xd30, 0x00000000}, |
| 580 | {0xd34, 0x80608000}, {0xd38, 0x00000000}, |
| 581 | {0xd3c, 0x00027293}, {0xd40, 0x00000000}, |
| 582 | {0xd44, 0x00000000}, {0xd48, 0x00000000}, |
| 583 | {0xd4c, 0x00000000}, {0xd50, 0x6437140a}, |
| 584 | {0xd54, 0x00000000}, {0xd58, 0x00000000}, |
| 585 | {0xd5c, 0x30032064}, {0xd60, 0x4653de68}, |
| 586 | {0xd64, 0x04518a3c}, {0xd68, 0x00002101}, |
| 587 | {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e}, |
| 588 | {0xd74, 0x322c2220}, {0xd78, 0x000e3c24}, |
| 589 | {0xe00, 0x24242424}, {0xe04, 0x24242424}, |
| 590 | {0xe08, 0x03902024}, {0xe10, 0x24242424}, |
| 591 | {0xe14, 0x24242424}, {0xe18, 0x24242424}, |
| 592 | {0xe1c, 0x24242424}, {0xe28, 0x00000000}, |
| 593 | {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, |
| 594 | {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, |
| 595 | {0xe40, 0x01007c00}, {0xe44, 0x01004800}, |
| 596 | {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, |
| 597 | {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, |
| 598 | {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, |
| 599 | {0xe60, 0x00000008}, {0xe68, 0x001b25a4}, |
| 600 | {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0}, |
| 601 | {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0}, |
| 602 | {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0}, |
| 603 | {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0}, |
| 604 | {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0}, |
| 605 | {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0}, |
| 606 | {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0}, |
| 607 | {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448}, |
| 608 | {0xf14, 0x00000003}, {0xf4c, 0x00000000}, |
| 609 | {0xf00, 0x00000300}, |
| 610 | {0xffff, 0xffffffff}, |
| 611 | }; |
| 612 | |
Jes Sorensen | ae14c5d | 2016-04-07 14:19:21 -0400 | [diff] [blame] | 613 | static struct rtl8xxxu_reg32val rtl8192eu_phy_init_table[] = { |
| 614 | {0x800, 0x80040000}, {0x804, 0x00000003}, |
| 615 | {0x808, 0x0000fc00}, {0x80c, 0x0000000a}, |
| 616 | {0x810, 0x10001331}, {0x814, 0x020c3d10}, |
| 617 | {0x818, 0x02220385}, {0x81c, 0x00000000}, |
| 618 | {0x820, 0x01000100}, {0x824, 0x00390204}, |
| 619 | {0x828, 0x01000100}, {0x82c, 0x00390204}, |
| 620 | {0x830, 0x32323232}, {0x834, 0x30303030}, |
| 621 | {0x838, 0x30303030}, {0x83c, 0x30303030}, |
| 622 | {0x840, 0x00010000}, {0x844, 0x00010000}, |
| 623 | {0x848, 0x28282828}, {0x84c, 0x28282828}, |
| 624 | {0x850, 0x00000000}, {0x854, 0x00000000}, |
| 625 | {0x858, 0x009a009a}, {0x85c, 0x01000014}, |
| 626 | {0x860, 0x66f60000}, {0x864, 0x061f0000}, |
| 627 | {0x868, 0x30303030}, {0x86c, 0x30303030}, |
| 628 | {0x870, 0x00000000}, {0x874, 0x55004200}, |
| 629 | {0x878, 0x08080808}, {0x87c, 0x00000000}, |
| 630 | {0x880, 0xb0000c1c}, {0x884, 0x00000001}, |
| 631 | {0x888, 0x00000000}, {0x88c, 0xcc0000c0}, |
| 632 | {0x890, 0x00000800}, {0x894, 0xfffffffe}, |
| 633 | {0x898, 0x40302010}, {0x900, 0x00000000}, |
| 634 | {0x904, 0x00000023}, {0x908, 0x00000000}, |
| 635 | {0x90c, 0x81121313}, {0x910, 0x806c0001}, |
| 636 | {0x914, 0x00000001}, {0x918, 0x00000000}, |
| 637 | {0x91c, 0x00010000}, {0x924, 0x00000001}, |
| 638 | {0x928, 0x00000000}, {0x92c, 0x00000000}, |
| 639 | {0x930, 0x00000000}, {0x934, 0x00000000}, |
| 640 | {0x938, 0x00000000}, {0x93c, 0x00000000}, |
| 641 | {0x940, 0x00000000}, {0x944, 0x00000000}, |
| 642 | {0x94c, 0x00000008}, {0xa00, 0x00d0c7c8}, |
| 643 | {0xa04, 0x81ff000c}, {0xa08, 0x8c838300}, |
| 644 | {0xa0c, 0x2e68120f}, {0xa10, 0x95009b78}, |
| 645 | {0xa14, 0x1114d028}, {0xa18, 0x00881117}, |
| 646 | {0xa1c, 0x89140f00}, {0xa20, 0x1a1b0000}, |
| 647 | {0xa24, 0x090e1317}, {0xa28, 0x00000204}, |
| 648 | {0xa2c, 0x00d30000}, {0xa70, 0x101fff00}, |
| 649 | {0xa74, 0x00000007}, {0xa78, 0x00000900}, |
| 650 | {0xa7c, 0x225b0606}, {0xa80, 0x218075b1}, |
| 651 | {0xb38, 0x00000000}, {0xc00, 0x48071d40}, |
| 652 | {0xc04, 0x03a05633}, {0xc08, 0x000000e4}, |
| 653 | {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000}, |
| 654 | {0xc14, 0x40000100}, {0xc18, 0x08800000}, |
| 655 | {0xc1c, 0x40000100}, {0xc20, 0x00000000}, |
| 656 | {0xc24, 0x00000000}, {0xc28, 0x00000000}, |
| 657 | {0xc2c, 0x00000000}, {0xc30, 0x69e9ac47}, |
| 658 | {0xc34, 0x469652af}, {0xc38, 0x49795994}, |
| 659 | {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f}, |
| 660 | {0xc44, 0x000100b7}, {0xc48, 0xec020107}, |
| 661 | {0xc4c, 0x007f037f}, |
| 662 | #ifdef EXT_PA_8192EU |
| 663 | /* External PA or external LNA */ |
| 664 | {0xc50, 0x00340220}, |
| 665 | #else |
| 666 | {0xc50, 0x00340020}, |
| 667 | #endif |
| 668 | {0xc54, 0x0080801f}, |
| 669 | #ifdef EXT_PA_8192EU |
| 670 | /* External PA or external LNA */ |
| 671 | {0xc58, 0x00000220}, |
| 672 | #else |
| 673 | {0xc58, 0x00000020}, |
| 674 | #endif |
| 675 | {0xc5c, 0x00248492}, {0xc60, 0x00000000}, |
| 676 | {0xc64, 0x7112848b}, {0xc68, 0x47c00bff}, |
| 677 | {0xc6c, 0x00000036}, {0xc70, 0x00000600}, |
| 678 | {0xc74, 0x02013169}, {0xc78, 0x0000001f}, |
| 679 | {0xc7c, 0x00b91612}, |
| 680 | #ifdef EXT_PA_8192EU |
| 681 | /* External PA or external LNA */ |
| 682 | {0xc80, 0x2d4000b5}, |
| 683 | #else |
| 684 | {0xc80, 0x40000100}, |
| 685 | #endif |
| 686 | {0xc84, 0x21f60000}, |
| 687 | #ifdef EXT_PA_8192EU |
| 688 | /* External PA or external LNA */ |
| 689 | {0xc88, 0x2d4000b5}, |
| 690 | #else |
| 691 | {0xc88, 0x40000100}, |
| 692 | #endif |
| 693 | {0xc8c, 0xa0e40000}, {0xc90, 0x00121820}, |
| 694 | {0xc94, 0x00000000}, {0xc98, 0x00121820}, |
| 695 | {0xc9c, 0x00007f7f}, {0xca0, 0x00000000}, |
| 696 | {0xca4, 0x000300a0}, {0xca8, 0x00000000}, |
| 697 | {0xcac, 0x00000000}, {0xcb0, 0x00000000}, |
| 698 | {0xcb4, 0x00000000}, {0xcb8, 0x00000000}, |
| 699 | {0xcbc, 0x28000000}, {0xcc0, 0x00000000}, |
| 700 | {0xcc4, 0x00000000}, {0xcc8, 0x00000000}, |
| 701 | {0xccc, 0x00000000}, {0xcd0, 0x00000000}, |
| 702 | {0xcd4, 0x00000000}, {0xcd8, 0x64b22427}, |
| 703 | {0xcdc, 0x00766932}, {0xce0, 0x00222222}, |
| 704 | {0xce4, 0x00040000}, {0xce8, 0x77644302}, |
| 705 | {0xcec, 0x2f97d40c}, {0xd00, 0x00080740}, |
| 706 | {0xd04, 0x00020403}, {0xd08, 0x0000907f}, |
| 707 | {0xd0c, 0x20010201}, {0xd10, 0xa0633333}, |
| 708 | {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b}, |
| 709 | {0xd1c, 0x0000007f}, {0xd2c, 0xcc979975}, |
| 710 | {0xd30, 0x00000000}, {0xd34, 0x80608000}, |
| 711 | {0xd38, 0x00000000}, {0xd3c, 0x00127353}, |
| 712 | {0xd40, 0x00000000}, {0xd44, 0x00000000}, |
| 713 | {0xd48, 0x00000000}, {0xd4c, 0x00000000}, |
| 714 | {0xd50, 0x6437140a}, {0xd54, 0x00000000}, |
| 715 | {0xd58, 0x00000282}, {0xd5c, 0x30032064}, |
| 716 | {0xd60, 0x4653de68}, {0xd64, 0x04518a3c}, |
| 717 | {0xd68, 0x00002101}, {0xd6c, 0x2a201c16}, |
| 718 | {0xd70, 0x1812362e}, {0xd74, 0x322c2220}, |
| 719 | {0xd78, 0x000e3c24}, {0xd80, 0x01081008}, |
| 720 | {0xd84, 0x00000800}, {0xd88, 0xf0b50000}, |
| 721 | {0xe00, 0x30303030}, {0xe04, 0x30303030}, |
| 722 | {0xe08, 0x03903030}, {0xe10, 0x30303030}, |
| 723 | {0xe14, 0x30303030}, {0xe18, 0x30303030}, |
| 724 | {0xe1c, 0x30303030}, {0xe28, 0x00000000}, |
| 725 | {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f}, |
| 726 | {0xe38, 0x02140102}, {0xe3c, 0x681604c2}, |
| 727 | {0xe40, 0x01007c00}, {0xe44, 0x01004800}, |
| 728 | {0xe48, 0xfb000000}, {0xe4c, 0x000028d1}, |
| 729 | {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f}, |
| 730 | {0xe58, 0x02140102}, {0xe5c, 0x28160d05}, |
| 731 | {0xe60, 0x00000008}, {0xe68, 0x0fc05656}, |
| 732 | {0xe6c, 0x03c09696}, {0xe70, 0x03c09696}, |
| 733 | {0xe74, 0x0c005656}, {0xe78, 0x0c005656}, |
| 734 | {0xe7c, 0x0c005656}, {0xe80, 0x0c005656}, |
| 735 | {0xe84, 0x03c09696}, {0xe88, 0x0c005656}, |
| 736 | {0xe8c, 0x03c09696}, {0xed0, 0x03c09696}, |
| 737 | {0xed4, 0x03c09696}, {0xed8, 0x03c09696}, |
| 738 | {0xedc, 0x0000d6d6}, {0xee0, 0x0000d6d6}, |
| 739 | {0xeec, 0x0fc01616}, {0xee4, 0xb0000c1c}, |
| 740 | {0xee8, 0x00000001}, {0xf14, 0x00000003}, |
| 741 | {0xf4c, 0x00000000}, {0xf00, 0x00000300}, |
| 742 | {0xffff, 0xffffffff}, |
| 743 | }; |
| 744 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 745 | static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = { |
| 746 | {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, |
| 747 | {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, |
| 748 | {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, |
| 749 | {0xc78, 0x7a060001}, {0xc78, 0x79070001}, |
| 750 | {0xc78, 0x78080001}, {0xc78, 0x77090001}, |
| 751 | {0xc78, 0x760a0001}, {0xc78, 0x750b0001}, |
| 752 | {0xc78, 0x740c0001}, {0xc78, 0x730d0001}, |
| 753 | {0xc78, 0x720e0001}, {0xc78, 0x710f0001}, |
| 754 | {0xc78, 0x70100001}, {0xc78, 0x6f110001}, |
| 755 | {0xc78, 0x6e120001}, {0xc78, 0x6d130001}, |
| 756 | {0xc78, 0x6c140001}, {0xc78, 0x6b150001}, |
| 757 | {0xc78, 0x6a160001}, {0xc78, 0x69170001}, |
| 758 | {0xc78, 0x68180001}, {0xc78, 0x67190001}, |
| 759 | {0xc78, 0x661a0001}, {0xc78, 0x651b0001}, |
| 760 | {0xc78, 0x641c0001}, {0xc78, 0x631d0001}, |
| 761 | {0xc78, 0x621e0001}, {0xc78, 0x611f0001}, |
| 762 | {0xc78, 0x60200001}, {0xc78, 0x49210001}, |
| 763 | {0xc78, 0x48220001}, {0xc78, 0x47230001}, |
| 764 | {0xc78, 0x46240001}, {0xc78, 0x45250001}, |
| 765 | {0xc78, 0x44260001}, {0xc78, 0x43270001}, |
| 766 | {0xc78, 0x42280001}, {0xc78, 0x41290001}, |
| 767 | {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, |
| 768 | {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, |
| 769 | {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, |
| 770 | {0xc78, 0x21300001}, {0xc78, 0x20310001}, |
| 771 | {0xc78, 0x06320001}, {0xc78, 0x05330001}, |
| 772 | {0xc78, 0x04340001}, {0xc78, 0x03350001}, |
| 773 | {0xc78, 0x02360001}, {0xc78, 0x01370001}, |
| 774 | {0xc78, 0x00380001}, {0xc78, 0x00390001}, |
| 775 | {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, |
| 776 | {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, |
| 777 | {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, |
| 778 | {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, |
| 779 | {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, |
| 780 | {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, |
| 781 | {0xc78, 0x7a460001}, {0xc78, 0x79470001}, |
| 782 | {0xc78, 0x78480001}, {0xc78, 0x77490001}, |
| 783 | {0xc78, 0x764a0001}, {0xc78, 0x754b0001}, |
| 784 | {0xc78, 0x744c0001}, {0xc78, 0x734d0001}, |
| 785 | {0xc78, 0x724e0001}, {0xc78, 0x714f0001}, |
| 786 | {0xc78, 0x70500001}, {0xc78, 0x6f510001}, |
| 787 | {0xc78, 0x6e520001}, {0xc78, 0x6d530001}, |
| 788 | {0xc78, 0x6c540001}, {0xc78, 0x6b550001}, |
| 789 | {0xc78, 0x6a560001}, {0xc78, 0x69570001}, |
| 790 | {0xc78, 0x68580001}, {0xc78, 0x67590001}, |
| 791 | {0xc78, 0x665a0001}, {0xc78, 0x655b0001}, |
| 792 | {0xc78, 0x645c0001}, {0xc78, 0x635d0001}, |
| 793 | {0xc78, 0x625e0001}, {0xc78, 0x615f0001}, |
| 794 | {0xc78, 0x60600001}, {0xc78, 0x49610001}, |
| 795 | {0xc78, 0x48620001}, {0xc78, 0x47630001}, |
| 796 | {0xc78, 0x46640001}, {0xc78, 0x45650001}, |
| 797 | {0xc78, 0x44660001}, {0xc78, 0x43670001}, |
| 798 | {0xc78, 0x42680001}, {0xc78, 0x41690001}, |
| 799 | {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, |
| 800 | {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, |
| 801 | {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, |
| 802 | {0xc78, 0x21700001}, {0xc78, 0x20710001}, |
| 803 | {0xc78, 0x06720001}, {0xc78, 0x05730001}, |
| 804 | {0xc78, 0x04740001}, {0xc78, 0x03750001}, |
| 805 | {0xc78, 0x02760001}, {0xc78, 0x01770001}, |
| 806 | {0xc78, 0x00780001}, {0xc78, 0x00790001}, |
| 807 | {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, |
| 808 | {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, |
| 809 | {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, |
| 810 | {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, |
| 811 | {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, |
| 812 | {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, |
| 813 | {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, |
| 814 | {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, |
| 815 | {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, |
| 816 | {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, |
| 817 | {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, |
| 818 | {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, |
| 819 | {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, |
| 820 | {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, |
| 821 | {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, |
| 822 | {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, |
| 823 | {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, |
| 824 | {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, |
| 825 | {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, |
| 826 | {0xffff, 0xffffffff} |
| 827 | }; |
| 828 | |
| 829 | static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = { |
| 830 | {0xc78, 0x7b000001}, {0xc78, 0x7b010001}, |
| 831 | {0xc78, 0x7b020001}, {0xc78, 0x7b030001}, |
| 832 | {0xc78, 0x7b040001}, {0xc78, 0x7b050001}, |
| 833 | {0xc78, 0x7b060001}, {0xc78, 0x7b070001}, |
| 834 | {0xc78, 0x7b080001}, {0xc78, 0x7a090001}, |
| 835 | {0xc78, 0x790a0001}, {0xc78, 0x780b0001}, |
| 836 | {0xc78, 0x770c0001}, {0xc78, 0x760d0001}, |
| 837 | {0xc78, 0x750e0001}, {0xc78, 0x740f0001}, |
| 838 | {0xc78, 0x73100001}, {0xc78, 0x72110001}, |
| 839 | {0xc78, 0x71120001}, {0xc78, 0x70130001}, |
| 840 | {0xc78, 0x6f140001}, {0xc78, 0x6e150001}, |
| 841 | {0xc78, 0x6d160001}, {0xc78, 0x6c170001}, |
| 842 | {0xc78, 0x6b180001}, {0xc78, 0x6a190001}, |
| 843 | {0xc78, 0x691a0001}, {0xc78, 0x681b0001}, |
| 844 | {0xc78, 0x671c0001}, {0xc78, 0x661d0001}, |
| 845 | {0xc78, 0x651e0001}, {0xc78, 0x641f0001}, |
| 846 | {0xc78, 0x63200001}, {0xc78, 0x62210001}, |
| 847 | {0xc78, 0x61220001}, {0xc78, 0x60230001}, |
| 848 | {0xc78, 0x46240001}, {0xc78, 0x45250001}, |
| 849 | {0xc78, 0x44260001}, {0xc78, 0x43270001}, |
| 850 | {0xc78, 0x42280001}, {0xc78, 0x41290001}, |
| 851 | {0xc78, 0x402a0001}, {0xc78, 0x262b0001}, |
| 852 | {0xc78, 0x252c0001}, {0xc78, 0x242d0001}, |
| 853 | {0xc78, 0x232e0001}, {0xc78, 0x222f0001}, |
| 854 | {0xc78, 0x21300001}, {0xc78, 0x20310001}, |
| 855 | {0xc78, 0x06320001}, {0xc78, 0x05330001}, |
| 856 | {0xc78, 0x04340001}, {0xc78, 0x03350001}, |
| 857 | {0xc78, 0x02360001}, {0xc78, 0x01370001}, |
| 858 | {0xc78, 0x00380001}, {0xc78, 0x00390001}, |
| 859 | {0xc78, 0x003a0001}, {0xc78, 0x003b0001}, |
| 860 | {0xc78, 0x003c0001}, {0xc78, 0x003d0001}, |
| 861 | {0xc78, 0x003e0001}, {0xc78, 0x003f0001}, |
| 862 | {0xc78, 0x7b400001}, {0xc78, 0x7b410001}, |
| 863 | {0xc78, 0x7b420001}, {0xc78, 0x7b430001}, |
| 864 | {0xc78, 0x7b440001}, {0xc78, 0x7b450001}, |
| 865 | {0xc78, 0x7b460001}, {0xc78, 0x7b470001}, |
| 866 | {0xc78, 0x7b480001}, {0xc78, 0x7a490001}, |
| 867 | {0xc78, 0x794a0001}, {0xc78, 0x784b0001}, |
| 868 | {0xc78, 0x774c0001}, {0xc78, 0x764d0001}, |
| 869 | {0xc78, 0x754e0001}, {0xc78, 0x744f0001}, |
| 870 | {0xc78, 0x73500001}, {0xc78, 0x72510001}, |
| 871 | {0xc78, 0x71520001}, {0xc78, 0x70530001}, |
| 872 | {0xc78, 0x6f540001}, {0xc78, 0x6e550001}, |
| 873 | {0xc78, 0x6d560001}, {0xc78, 0x6c570001}, |
| 874 | {0xc78, 0x6b580001}, {0xc78, 0x6a590001}, |
| 875 | {0xc78, 0x695a0001}, {0xc78, 0x685b0001}, |
| 876 | {0xc78, 0x675c0001}, {0xc78, 0x665d0001}, |
| 877 | {0xc78, 0x655e0001}, {0xc78, 0x645f0001}, |
| 878 | {0xc78, 0x63600001}, {0xc78, 0x62610001}, |
| 879 | {0xc78, 0x61620001}, {0xc78, 0x60630001}, |
| 880 | {0xc78, 0x46640001}, {0xc78, 0x45650001}, |
| 881 | {0xc78, 0x44660001}, {0xc78, 0x43670001}, |
| 882 | {0xc78, 0x42680001}, {0xc78, 0x41690001}, |
| 883 | {0xc78, 0x406a0001}, {0xc78, 0x266b0001}, |
| 884 | {0xc78, 0x256c0001}, {0xc78, 0x246d0001}, |
| 885 | {0xc78, 0x236e0001}, {0xc78, 0x226f0001}, |
| 886 | {0xc78, 0x21700001}, {0xc78, 0x20710001}, |
| 887 | {0xc78, 0x06720001}, {0xc78, 0x05730001}, |
| 888 | {0xc78, 0x04740001}, {0xc78, 0x03750001}, |
| 889 | {0xc78, 0x02760001}, {0xc78, 0x01770001}, |
| 890 | {0xc78, 0x00780001}, {0xc78, 0x00790001}, |
| 891 | {0xc78, 0x007a0001}, {0xc78, 0x007b0001}, |
| 892 | {0xc78, 0x007c0001}, {0xc78, 0x007d0001}, |
| 893 | {0xc78, 0x007e0001}, {0xc78, 0x007f0001}, |
| 894 | {0xc78, 0x3800001e}, {0xc78, 0x3801001e}, |
| 895 | {0xc78, 0x3802001e}, {0xc78, 0x3803001e}, |
| 896 | {0xc78, 0x3804001e}, {0xc78, 0x3805001e}, |
| 897 | {0xc78, 0x3806001e}, {0xc78, 0x3807001e}, |
| 898 | {0xc78, 0x3808001e}, {0xc78, 0x3c09001e}, |
| 899 | {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e}, |
| 900 | {0xc78, 0x440c001e}, {0xc78, 0x480d001e}, |
| 901 | {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e}, |
| 902 | {0xc78, 0x5210001e}, {0xc78, 0x5611001e}, |
| 903 | {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e}, |
| 904 | {0xc78, 0x6014001e}, {0xc78, 0x6015001e}, |
| 905 | {0xc78, 0x6016001e}, {0xc78, 0x6217001e}, |
| 906 | {0xc78, 0x6218001e}, {0xc78, 0x6219001e}, |
| 907 | {0xc78, 0x621a001e}, {0xc78, 0x621b001e}, |
| 908 | {0xc78, 0x621c001e}, {0xc78, 0x621d001e}, |
| 909 | {0xc78, 0x621e001e}, {0xc78, 0x621f001e}, |
| 910 | {0xffff, 0xffffffff} |
| 911 | }; |
| 912 | |
Jes Sorensen | b9f498e | 2016-02-29 17:04:18 -0500 | [diff] [blame] | 913 | static struct rtl8xxxu_reg32val rtl8xxx_agc_8723bu_table[] = { |
| 914 | {0xc78, 0xfd000001}, {0xc78, 0xfc010001}, |
| 915 | {0xc78, 0xfb020001}, {0xc78, 0xfa030001}, |
| 916 | {0xc78, 0xf9040001}, {0xc78, 0xf8050001}, |
| 917 | {0xc78, 0xf7060001}, {0xc78, 0xf6070001}, |
| 918 | {0xc78, 0xf5080001}, {0xc78, 0xf4090001}, |
| 919 | {0xc78, 0xf30a0001}, {0xc78, 0xf20b0001}, |
| 920 | {0xc78, 0xf10c0001}, {0xc78, 0xf00d0001}, |
| 921 | {0xc78, 0xef0e0001}, {0xc78, 0xee0f0001}, |
| 922 | {0xc78, 0xed100001}, {0xc78, 0xec110001}, |
| 923 | {0xc78, 0xeb120001}, {0xc78, 0xea130001}, |
| 924 | {0xc78, 0xe9140001}, {0xc78, 0xe8150001}, |
| 925 | {0xc78, 0xe7160001}, {0xc78, 0xe6170001}, |
| 926 | {0xc78, 0xe5180001}, {0xc78, 0xe4190001}, |
| 927 | {0xc78, 0xe31a0001}, {0xc78, 0xa51b0001}, |
| 928 | {0xc78, 0xa41c0001}, {0xc78, 0xa31d0001}, |
| 929 | {0xc78, 0x671e0001}, {0xc78, 0x661f0001}, |
| 930 | {0xc78, 0x65200001}, {0xc78, 0x64210001}, |
| 931 | {0xc78, 0x63220001}, {0xc78, 0x4a230001}, |
| 932 | {0xc78, 0x49240001}, {0xc78, 0x48250001}, |
| 933 | {0xc78, 0x47260001}, {0xc78, 0x46270001}, |
| 934 | {0xc78, 0x45280001}, {0xc78, 0x44290001}, |
| 935 | {0xc78, 0x432a0001}, {0xc78, 0x422b0001}, |
| 936 | {0xc78, 0x292c0001}, {0xc78, 0x282d0001}, |
| 937 | {0xc78, 0x272e0001}, {0xc78, 0x262f0001}, |
| 938 | {0xc78, 0x0a300001}, {0xc78, 0x09310001}, |
| 939 | {0xc78, 0x08320001}, {0xc78, 0x07330001}, |
| 940 | {0xc78, 0x06340001}, {0xc78, 0x05350001}, |
| 941 | {0xc78, 0x04360001}, {0xc78, 0x03370001}, |
| 942 | {0xc78, 0x02380001}, {0xc78, 0x01390001}, |
| 943 | {0xc78, 0x013a0001}, {0xc78, 0x013b0001}, |
| 944 | {0xc78, 0x013c0001}, {0xc78, 0x013d0001}, |
| 945 | {0xc78, 0x013e0001}, {0xc78, 0x013f0001}, |
| 946 | {0xc78, 0xfc400001}, {0xc78, 0xfb410001}, |
| 947 | {0xc78, 0xfa420001}, {0xc78, 0xf9430001}, |
| 948 | {0xc78, 0xf8440001}, {0xc78, 0xf7450001}, |
| 949 | {0xc78, 0xf6460001}, {0xc78, 0xf5470001}, |
| 950 | {0xc78, 0xf4480001}, {0xc78, 0xf3490001}, |
| 951 | {0xc78, 0xf24a0001}, {0xc78, 0xf14b0001}, |
| 952 | {0xc78, 0xf04c0001}, {0xc78, 0xef4d0001}, |
| 953 | {0xc78, 0xee4e0001}, {0xc78, 0xed4f0001}, |
| 954 | {0xc78, 0xec500001}, {0xc78, 0xeb510001}, |
| 955 | {0xc78, 0xea520001}, {0xc78, 0xe9530001}, |
| 956 | {0xc78, 0xe8540001}, {0xc78, 0xe7550001}, |
| 957 | {0xc78, 0xe6560001}, {0xc78, 0xe5570001}, |
| 958 | {0xc78, 0xe4580001}, {0xc78, 0xe3590001}, |
| 959 | {0xc78, 0xa65a0001}, {0xc78, 0xa55b0001}, |
| 960 | {0xc78, 0xa45c0001}, {0xc78, 0xa35d0001}, |
| 961 | {0xc78, 0x675e0001}, {0xc78, 0x665f0001}, |
| 962 | {0xc78, 0x65600001}, {0xc78, 0x64610001}, |
| 963 | {0xc78, 0x63620001}, {0xc78, 0x62630001}, |
| 964 | {0xc78, 0x61640001}, {0xc78, 0x48650001}, |
| 965 | {0xc78, 0x47660001}, {0xc78, 0x46670001}, |
| 966 | {0xc78, 0x45680001}, {0xc78, 0x44690001}, |
| 967 | {0xc78, 0x436a0001}, {0xc78, 0x426b0001}, |
| 968 | {0xc78, 0x286c0001}, {0xc78, 0x276d0001}, |
| 969 | {0xc78, 0x266e0001}, {0xc78, 0x256f0001}, |
| 970 | {0xc78, 0x24700001}, {0xc78, 0x09710001}, |
| 971 | {0xc78, 0x08720001}, {0xc78, 0x07730001}, |
| 972 | {0xc78, 0x06740001}, {0xc78, 0x05750001}, |
| 973 | {0xc78, 0x04760001}, {0xc78, 0x03770001}, |
| 974 | {0xc78, 0x02780001}, {0xc78, 0x01790001}, |
| 975 | {0xc78, 0x017a0001}, {0xc78, 0x017b0001}, |
| 976 | {0xc78, 0x017c0001}, {0xc78, 0x017d0001}, |
| 977 | {0xc78, 0x017e0001}, {0xc78, 0x017f0001}, |
| 978 | {0xc50, 0x69553422}, |
| 979 | {0xc50, 0x69553420}, |
| 980 | {0x824, 0x00390204}, |
| 981 | {0xffff, 0xffffffff} |
| 982 | }; |
| 983 | |
Jes Sorensen | e293278 | 2016-04-07 14:19:20 -0400 | [diff] [blame] | 984 | static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_std_table[] = { |
| 985 | {0xc78, 0xfb000001}, {0xc78, 0xfb010001}, |
| 986 | {0xc78, 0xfb020001}, {0xc78, 0xfb030001}, |
| 987 | {0xc78, 0xfb040001}, {0xc78, 0xfb050001}, |
| 988 | {0xc78, 0xfa060001}, {0xc78, 0xf9070001}, |
| 989 | {0xc78, 0xf8080001}, {0xc78, 0xf7090001}, |
| 990 | {0xc78, 0xf60a0001}, {0xc78, 0xf50b0001}, |
| 991 | {0xc78, 0xf40c0001}, {0xc78, 0xf30d0001}, |
| 992 | {0xc78, 0xf20e0001}, {0xc78, 0xf10f0001}, |
| 993 | {0xc78, 0xf0100001}, {0xc78, 0xef110001}, |
| 994 | {0xc78, 0xee120001}, {0xc78, 0xed130001}, |
| 995 | {0xc78, 0xec140001}, {0xc78, 0xeb150001}, |
| 996 | {0xc78, 0xea160001}, {0xc78, 0xe9170001}, |
| 997 | {0xc78, 0xe8180001}, {0xc78, 0xe7190001}, |
| 998 | {0xc78, 0xc81a0001}, {0xc78, 0xc71b0001}, |
| 999 | {0xc78, 0xc61c0001}, {0xc78, 0x071d0001}, |
| 1000 | {0xc78, 0x061e0001}, {0xc78, 0x051f0001}, |
| 1001 | {0xc78, 0x04200001}, {0xc78, 0x03210001}, |
| 1002 | {0xc78, 0xaa220001}, {0xc78, 0xa9230001}, |
| 1003 | {0xc78, 0xa8240001}, {0xc78, 0xa7250001}, |
| 1004 | {0xc78, 0xa6260001}, {0xc78, 0x85270001}, |
| 1005 | {0xc78, 0x84280001}, {0xc78, 0x83290001}, |
| 1006 | {0xc78, 0x252a0001}, {0xc78, 0x242b0001}, |
| 1007 | {0xc78, 0x232c0001}, {0xc78, 0x222d0001}, |
| 1008 | {0xc78, 0x672e0001}, {0xc78, 0x662f0001}, |
| 1009 | {0xc78, 0x65300001}, {0xc78, 0x64310001}, |
| 1010 | {0xc78, 0x63320001}, {0xc78, 0x62330001}, |
| 1011 | {0xc78, 0x61340001}, {0xc78, 0x45350001}, |
| 1012 | {0xc78, 0x44360001}, {0xc78, 0x43370001}, |
| 1013 | {0xc78, 0x42380001}, {0xc78, 0x41390001}, |
| 1014 | {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, |
| 1015 | {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, |
| 1016 | {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, |
| 1017 | {0xc78, 0xfb400001}, {0xc78, 0xfb410001}, |
| 1018 | {0xc78, 0xfb420001}, {0xc78, 0xfb430001}, |
| 1019 | {0xc78, 0xfb440001}, {0xc78, 0xfb450001}, |
| 1020 | {0xc78, 0xfa460001}, {0xc78, 0xf9470001}, |
| 1021 | {0xc78, 0xf8480001}, {0xc78, 0xf7490001}, |
| 1022 | {0xc78, 0xf64a0001}, {0xc78, 0xf54b0001}, |
| 1023 | {0xc78, 0xf44c0001}, {0xc78, 0xf34d0001}, |
| 1024 | {0xc78, 0xf24e0001}, {0xc78, 0xf14f0001}, |
| 1025 | {0xc78, 0xf0500001}, {0xc78, 0xef510001}, |
| 1026 | {0xc78, 0xee520001}, {0xc78, 0xed530001}, |
| 1027 | {0xc78, 0xec540001}, {0xc78, 0xeb550001}, |
| 1028 | {0xc78, 0xea560001}, {0xc78, 0xe9570001}, |
| 1029 | {0xc78, 0xe8580001}, {0xc78, 0xe7590001}, |
| 1030 | {0xc78, 0xe65a0001}, {0xc78, 0xe55b0001}, |
| 1031 | {0xc78, 0xe45c0001}, {0xc78, 0xe35d0001}, |
| 1032 | {0xc78, 0xe25e0001}, {0xc78, 0xe15f0001}, |
| 1033 | {0xc78, 0x8a600001}, {0xc78, 0x89610001}, |
| 1034 | {0xc78, 0x88620001}, {0xc78, 0x87630001}, |
| 1035 | {0xc78, 0x86640001}, {0xc78, 0x85650001}, |
| 1036 | {0xc78, 0x84660001}, {0xc78, 0x83670001}, |
| 1037 | {0xc78, 0x82680001}, {0xc78, 0x6b690001}, |
| 1038 | {0xc78, 0x6a6a0001}, {0xc78, 0x696b0001}, |
| 1039 | {0xc78, 0x686c0001}, {0xc78, 0x676d0001}, |
| 1040 | {0xc78, 0x666e0001}, {0xc78, 0x656f0001}, |
| 1041 | {0xc78, 0x64700001}, {0xc78, 0x63710001}, |
| 1042 | {0xc78, 0x62720001}, {0xc78, 0x61730001}, |
| 1043 | {0xc78, 0x49740001}, {0xc78, 0x48750001}, |
| 1044 | {0xc78, 0x47760001}, {0xc78, 0x46770001}, |
| 1045 | {0xc78, 0x45780001}, {0xc78, 0x44790001}, |
| 1046 | {0xc78, 0x437a0001}, {0xc78, 0x427b0001}, |
| 1047 | {0xc78, 0x417c0001}, {0xc78, 0x407d0001}, |
| 1048 | {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, |
| 1049 | {0xc50, 0x00040022}, {0xc50, 0x00040020}, |
| 1050 | {0xffff, 0xffffffff} |
| 1051 | }; |
| 1052 | |
| 1053 | static struct rtl8xxxu_reg32val rtl8xxx_agc_8192eu_highpa_table[] = { |
| 1054 | {0xc78, 0xfa000001}, {0xc78, 0xf9010001}, |
| 1055 | {0xc78, 0xf8020001}, {0xc78, 0xf7030001}, |
| 1056 | {0xc78, 0xf6040001}, {0xc78, 0xf5050001}, |
| 1057 | {0xc78, 0xf4060001}, {0xc78, 0xf3070001}, |
| 1058 | {0xc78, 0xf2080001}, {0xc78, 0xf1090001}, |
| 1059 | {0xc78, 0xf00a0001}, {0xc78, 0xef0b0001}, |
| 1060 | {0xc78, 0xee0c0001}, {0xc78, 0xed0d0001}, |
| 1061 | {0xc78, 0xec0e0001}, {0xc78, 0xeb0f0001}, |
| 1062 | {0xc78, 0xea100001}, {0xc78, 0xe9110001}, |
| 1063 | {0xc78, 0xe8120001}, {0xc78, 0xe7130001}, |
| 1064 | {0xc78, 0xe6140001}, {0xc78, 0xe5150001}, |
| 1065 | {0xc78, 0xe4160001}, {0xc78, 0xe3170001}, |
| 1066 | {0xc78, 0xe2180001}, {0xc78, 0xe1190001}, |
| 1067 | {0xc78, 0x8a1a0001}, {0xc78, 0x891b0001}, |
| 1068 | {0xc78, 0x881c0001}, {0xc78, 0x871d0001}, |
| 1069 | {0xc78, 0x861e0001}, {0xc78, 0x851f0001}, |
| 1070 | {0xc78, 0x84200001}, {0xc78, 0x83210001}, |
| 1071 | {0xc78, 0x82220001}, {0xc78, 0x6a230001}, |
| 1072 | {0xc78, 0x69240001}, {0xc78, 0x68250001}, |
| 1073 | {0xc78, 0x67260001}, {0xc78, 0x66270001}, |
| 1074 | {0xc78, 0x65280001}, {0xc78, 0x64290001}, |
| 1075 | {0xc78, 0x632a0001}, {0xc78, 0x622b0001}, |
| 1076 | {0xc78, 0x612c0001}, {0xc78, 0x602d0001}, |
| 1077 | {0xc78, 0x472e0001}, {0xc78, 0x462f0001}, |
| 1078 | {0xc78, 0x45300001}, {0xc78, 0x44310001}, |
| 1079 | {0xc78, 0x43320001}, {0xc78, 0x42330001}, |
| 1080 | {0xc78, 0x41340001}, {0xc78, 0x40350001}, |
| 1081 | {0xc78, 0x40360001}, {0xc78, 0x40370001}, |
| 1082 | {0xc78, 0x40380001}, {0xc78, 0x40390001}, |
| 1083 | {0xc78, 0x403a0001}, {0xc78, 0x403b0001}, |
| 1084 | {0xc78, 0x403c0001}, {0xc78, 0x403d0001}, |
| 1085 | {0xc78, 0x403e0001}, {0xc78, 0x403f0001}, |
| 1086 | {0xc78, 0xfa400001}, {0xc78, 0xf9410001}, |
| 1087 | {0xc78, 0xf8420001}, {0xc78, 0xf7430001}, |
| 1088 | {0xc78, 0xf6440001}, {0xc78, 0xf5450001}, |
| 1089 | {0xc78, 0xf4460001}, {0xc78, 0xf3470001}, |
| 1090 | {0xc78, 0xf2480001}, {0xc78, 0xf1490001}, |
| 1091 | {0xc78, 0xf04a0001}, {0xc78, 0xef4b0001}, |
| 1092 | {0xc78, 0xee4c0001}, {0xc78, 0xed4d0001}, |
| 1093 | {0xc78, 0xec4e0001}, {0xc78, 0xeb4f0001}, |
| 1094 | {0xc78, 0xea500001}, {0xc78, 0xe9510001}, |
| 1095 | {0xc78, 0xe8520001}, {0xc78, 0xe7530001}, |
| 1096 | {0xc78, 0xe6540001}, {0xc78, 0xe5550001}, |
| 1097 | {0xc78, 0xe4560001}, {0xc78, 0xe3570001}, |
| 1098 | {0xc78, 0xe2580001}, {0xc78, 0xe1590001}, |
| 1099 | {0xc78, 0x8a5a0001}, {0xc78, 0x895b0001}, |
| 1100 | {0xc78, 0x885c0001}, {0xc78, 0x875d0001}, |
| 1101 | {0xc78, 0x865e0001}, {0xc78, 0x855f0001}, |
| 1102 | {0xc78, 0x84600001}, {0xc78, 0x83610001}, |
| 1103 | {0xc78, 0x82620001}, {0xc78, 0x6a630001}, |
| 1104 | {0xc78, 0x69640001}, {0xc78, 0x68650001}, |
| 1105 | {0xc78, 0x67660001}, {0xc78, 0x66670001}, |
| 1106 | {0xc78, 0x65680001}, {0xc78, 0x64690001}, |
| 1107 | {0xc78, 0x636a0001}, {0xc78, 0x626b0001}, |
| 1108 | {0xc78, 0x616c0001}, {0xc78, 0x606d0001}, |
| 1109 | {0xc78, 0x476e0001}, {0xc78, 0x466f0001}, |
| 1110 | {0xc78, 0x45700001}, {0xc78, 0x44710001}, |
| 1111 | {0xc78, 0x43720001}, {0xc78, 0x42730001}, |
| 1112 | {0xc78, 0x41740001}, {0xc78, 0x40750001}, |
| 1113 | {0xc78, 0x40760001}, {0xc78, 0x40770001}, |
| 1114 | {0xc78, 0x40780001}, {0xc78, 0x40790001}, |
| 1115 | {0xc78, 0x407a0001}, {0xc78, 0x407b0001}, |
| 1116 | {0xc78, 0x407c0001}, {0xc78, 0x407d0001}, |
| 1117 | {0xc78, 0x407e0001}, {0xc78, 0x407f0001}, |
| 1118 | {0xc50, 0x00040222}, {0xc50, 0x00040220}, |
| 1119 | {0xffff, 0xffffffff} |
| 1120 | }; |
| 1121 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1122 | static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = { |
| 1123 | {0x00, 0x00030159}, {0x01, 0x00031284}, |
| 1124 | {0x02, 0x00098000}, {0x03, 0x00039c63}, |
| 1125 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, |
| 1126 | {0x0a, 0x0001a3f1}, {0x0b, 0x00014787}, |
| 1127 | {0x0c, 0x000896fe}, {0x0d, 0x0000e02c}, |
| 1128 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, |
| 1129 | {0x19, 0x00000000}, {0x1a, 0x00030355}, |
| 1130 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, |
| 1131 | {0x1d, 0x000a1250}, {0x1e, 0x0000024f}, |
| 1132 | {0x1f, 0x00000000}, {0x20, 0x0000b614}, |
| 1133 | {0x21, 0x0006c000}, {0x22, 0x00000000}, |
| 1134 | {0x23, 0x00001558}, {0x24, 0x00000060}, |
| 1135 | {0x25, 0x00000483}, {0x26, 0x0004f000}, |
| 1136 | {0x27, 0x000ec7d9}, {0x28, 0x00057730}, |
| 1137 | {0x29, 0x00004783}, {0x2a, 0x00000001}, |
| 1138 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, |
| 1139 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, |
| 1140 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, |
| 1141 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, |
| 1142 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, |
| 1143 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, |
| 1144 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, |
| 1145 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, |
| 1146 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, |
| 1147 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, |
| 1148 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, |
| 1149 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, |
| 1150 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, |
| 1151 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, |
| 1152 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, |
| 1153 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, |
| 1154 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, |
| 1155 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, |
| 1156 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, |
| 1157 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, |
| 1158 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, |
| 1159 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, |
| 1160 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, |
| 1161 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, |
| 1162 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, |
| 1163 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, |
| 1164 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, |
| 1165 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, |
| 1166 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, |
| 1167 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, |
| 1168 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, |
| 1169 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, |
| 1170 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, |
| 1171 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, |
| 1172 | {0x10, 0x00000000}, {0x11, 0x00000000}, |
| 1173 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, |
| 1174 | {0x10, 0x0009000f}, {0x11, 0x00023100}, |
| 1175 | {0x12, 0x00032000}, {0x12, 0x00071000}, |
| 1176 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, |
| 1177 | {0x13, 0x000287b3}, {0x13, 0x000244b7}, |
| 1178 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, |
| 1179 | {0x13, 0x00018493}, {0x13, 0x0001429b}, |
| 1180 | {0x13, 0x00010299}, {0x13, 0x0000c29c}, |
| 1181 | {0x13, 0x000081a0}, {0x13, 0x000040ac}, |
| 1182 | {0x13, 0x00000020}, {0x14, 0x0001944c}, |
| 1183 | {0x14, 0x00059444}, {0x14, 0x0009944c}, |
| 1184 | {0x14, 0x000d9444}, {0x15, 0x0000f474}, |
| 1185 | {0x15, 0x0004f477}, {0x15, 0x0008f455}, |
| 1186 | {0x15, 0x000cf455}, {0x16, 0x00000339}, |
| 1187 | {0x16, 0x00040339}, {0x16, 0x00080339}, |
| 1188 | {0x16, 0x000c0366}, {0x00, 0x00010159}, |
| 1189 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, |
| 1190 | {0xfe, 0x00000000}, {0x1f, 0x00000003}, |
| 1191 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 1192 | {0x1e, 0x00000247}, {0x1f, 0x00000000}, |
| 1193 | {0x00, 0x00030159}, |
| 1194 | {0xff, 0xffffffff} |
| 1195 | }; |
| 1196 | |
Jes Sorensen | 22a31d4 | 2016-02-29 17:04:15 -0500 | [diff] [blame] | 1197 | static struct rtl8xxxu_rfregval rtl8723bu_radioa_1t_init_table[] = { |
| 1198 | {0x00, 0x00010000}, {0xb0, 0x000dffe0}, |
| 1199 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 1200 | {0xfe, 0x00000000}, {0xb1, 0x00000018}, |
| 1201 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 1202 | {0xfe, 0x00000000}, {0xb2, 0x00084c00}, |
| 1203 | {0xb5, 0x0000d2cc}, {0xb6, 0x000925aa}, |
| 1204 | {0xb7, 0x00000010}, {0xb8, 0x0000907f}, |
| 1205 | {0x5c, 0x00000002}, {0x7c, 0x00000002}, |
| 1206 | {0x7e, 0x00000005}, {0x8b, 0x0006fc00}, |
| 1207 | {0xb0, 0x000ff9f0}, {0x1c, 0x000739d2}, |
| 1208 | {0x1e, 0x00000000}, {0xdf, 0x00000780}, |
| 1209 | {0x50, 0x00067435}, |
| 1210 | /* |
| 1211 | * The 8723bu vendor driver indicates that bit 8 should be set in |
| 1212 | * 0x51 for package types TFBGA90, TFBGA80, and TFBGA79. However |
| 1213 | * they never actually check the package type - and just default |
| 1214 | * to not setting it. |
| 1215 | */ |
| 1216 | {0x51, 0x0006b04e}, |
| 1217 | {0x52, 0x000007d2}, {0x53, 0x00000000}, |
| 1218 | {0x54, 0x00050400}, {0x55, 0x0004026e}, |
| 1219 | {0xdd, 0x0000004c}, {0x70, 0x00067435}, |
| 1220 | /* |
| 1221 | * 0x71 has same package type condition as for register 0x51 |
| 1222 | */ |
| 1223 | {0x71, 0x0006b04e}, |
| 1224 | {0x72, 0x000007d2}, {0x73, 0x00000000}, |
| 1225 | {0x74, 0x00050400}, {0x75, 0x0004026e}, |
| 1226 | {0xef, 0x00000100}, {0x34, 0x0000add7}, |
| 1227 | {0x35, 0x00005c00}, {0x34, 0x00009dd4}, |
| 1228 | {0x35, 0x00005000}, {0x34, 0x00008dd1}, |
| 1229 | {0x35, 0x00004400}, {0x34, 0x00007dce}, |
| 1230 | {0x35, 0x00003800}, {0x34, 0x00006cd1}, |
| 1231 | {0x35, 0x00004400}, {0x34, 0x00005cce}, |
| 1232 | {0x35, 0x00003800}, {0x34, 0x000048ce}, |
| 1233 | {0x35, 0x00004400}, {0x34, 0x000034ce}, |
| 1234 | {0x35, 0x00003800}, {0x34, 0x00002451}, |
| 1235 | {0x35, 0x00004400}, {0x34, 0x0000144e}, |
| 1236 | {0x35, 0x00003800}, {0x34, 0x00000051}, |
| 1237 | {0x35, 0x00004400}, {0xef, 0x00000000}, |
| 1238 | {0xef, 0x00000100}, {0xed, 0x00000010}, |
| 1239 | {0x44, 0x0000add7}, {0x44, 0x00009dd4}, |
| 1240 | {0x44, 0x00008dd1}, {0x44, 0x00007dce}, |
| 1241 | {0x44, 0x00006cc1}, {0x44, 0x00005cce}, |
| 1242 | {0x44, 0x000044d1}, {0x44, 0x000034ce}, |
| 1243 | {0x44, 0x00002451}, {0x44, 0x0000144e}, |
| 1244 | {0x44, 0x00000051}, {0xef, 0x00000000}, |
| 1245 | {0xed, 0x00000000}, {0x7f, 0x00020080}, |
| 1246 | {0xef, 0x00002000}, {0x3b, 0x000380ef}, |
| 1247 | {0x3b, 0x000302fe}, {0x3b, 0x00028ce6}, |
| 1248 | {0x3b, 0x000200bc}, {0x3b, 0x000188a5}, |
| 1249 | {0x3b, 0x00010fbc}, {0x3b, 0x00008f71}, |
| 1250 | {0x3b, 0x00000900}, {0xef, 0x00000000}, |
| 1251 | {0xed, 0x00000001}, {0x40, 0x000380ef}, |
| 1252 | {0x40, 0x000302fe}, {0x40, 0x00028ce6}, |
| 1253 | {0x40, 0x000200bc}, {0x40, 0x000188a5}, |
| 1254 | {0x40, 0x00010fbc}, {0x40, 0x00008f71}, |
| 1255 | {0x40, 0x00000900}, {0xed, 0x00000000}, |
| 1256 | {0x82, 0x00080000}, {0x83, 0x00008000}, |
| 1257 | {0x84, 0x00048d80}, {0x85, 0x00068000}, |
| 1258 | {0xa2, 0x00080000}, {0xa3, 0x00008000}, |
| 1259 | {0xa4, 0x00048d80}, {0xa5, 0x00068000}, |
| 1260 | {0xed, 0x00000002}, {0xef, 0x00000002}, |
| 1261 | {0x56, 0x00000032}, {0x76, 0x00000032}, |
| 1262 | {0x01, 0x00000780}, |
| 1263 | {0xff, 0xffffffff} |
| 1264 | }; |
| 1265 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1266 | static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = { |
| 1267 | {0x00, 0x00030159}, {0x01, 0x00031284}, |
| 1268 | {0x02, 0x00098000}, {0x03, 0x00018c63}, |
| 1269 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, |
| 1270 | {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, |
| 1271 | {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, |
| 1272 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, |
| 1273 | {0x19, 0x00000000}, {0x1a, 0x00010255}, |
| 1274 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, |
| 1275 | {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, |
| 1276 | {0x1f, 0x00080001}, {0x20, 0x0000b614}, |
| 1277 | {0x21, 0x0006c000}, {0x22, 0x00000000}, |
| 1278 | {0x23, 0x00001558}, {0x24, 0x00000060}, |
| 1279 | {0x25, 0x00000483}, {0x26, 0x0004f000}, |
| 1280 | {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, |
| 1281 | {0x29, 0x00004783}, {0x2a, 0x00000001}, |
| 1282 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, |
| 1283 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, |
| 1284 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, |
| 1285 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, |
| 1286 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, |
| 1287 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, |
| 1288 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, |
| 1289 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, |
| 1290 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, |
| 1291 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, |
| 1292 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, |
| 1293 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, |
| 1294 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, |
| 1295 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, |
| 1296 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, |
| 1297 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, |
| 1298 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, |
| 1299 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, |
| 1300 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, |
| 1301 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, |
| 1302 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, |
| 1303 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, |
| 1304 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, |
| 1305 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, |
| 1306 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, |
| 1307 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, |
| 1308 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, |
| 1309 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, |
| 1310 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, |
| 1311 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, |
| 1312 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, |
| 1313 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, |
| 1314 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, |
| 1315 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, |
| 1316 | {0x10, 0x00000000}, {0x11, 0x00000000}, |
| 1317 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, |
| 1318 | {0x10, 0x0009000f}, {0x11, 0x00023100}, |
| 1319 | {0x12, 0x00032000}, {0x12, 0x00071000}, |
| 1320 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, |
| 1321 | {0x13, 0x000287b3}, {0x13, 0x000244b7}, |
| 1322 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, |
| 1323 | {0x13, 0x00018493}, {0x13, 0x0001429b}, |
| 1324 | {0x13, 0x00010299}, {0x13, 0x0000c29c}, |
| 1325 | {0x13, 0x000081a0}, {0x13, 0x000040ac}, |
| 1326 | {0x13, 0x00000020}, {0x14, 0x0001944c}, |
| 1327 | {0x14, 0x00059444}, {0x14, 0x0009944c}, |
| 1328 | {0x14, 0x000d9444}, {0x15, 0x0000f424}, |
| 1329 | {0x15, 0x0004f424}, {0x15, 0x0008f424}, |
| 1330 | {0x15, 0x000cf424}, {0x16, 0x000e0330}, |
| 1331 | {0x16, 0x000a0330}, {0x16, 0x00060330}, |
| 1332 | {0x16, 0x00020330}, {0x00, 0x00010159}, |
| 1333 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, |
| 1334 | {0xfe, 0x00000000}, {0x1f, 0x00080003}, |
| 1335 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 1336 | {0x1e, 0x00044457}, {0x1f, 0x00080000}, |
| 1337 | {0x00, 0x00030159}, |
| 1338 | {0xff, 0xffffffff} |
| 1339 | }; |
| 1340 | |
| 1341 | static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = { |
| 1342 | {0x00, 0x00030159}, {0x01, 0x00031284}, |
| 1343 | {0x02, 0x00098000}, {0x03, 0x00018c63}, |
| 1344 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, |
| 1345 | {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, |
| 1346 | {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, |
| 1347 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, |
| 1348 | {0x12, 0x00032000}, {0x12, 0x00071000}, |
| 1349 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, |
| 1350 | {0x13, 0x000287af}, {0x13, 0x000244b7}, |
| 1351 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, |
| 1352 | {0x13, 0x00018493}, {0x13, 0x00014297}, |
| 1353 | {0x13, 0x00010295}, {0x13, 0x0000c298}, |
| 1354 | {0x13, 0x0000819c}, {0x13, 0x000040a8}, |
| 1355 | {0x13, 0x0000001c}, {0x14, 0x0001944c}, |
| 1356 | {0x14, 0x00059444}, {0x14, 0x0009944c}, |
| 1357 | {0x14, 0x000d9444}, {0x15, 0x0000f424}, |
| 1358 | {0x15, 0x0004f424}, {0x15, 0x0008f424}, |
| 1359 | {0x15, 0x000cf424}, {0x16, 0x000e0330}, |
| 1360 | {0x16, 0x000a0330}, {0x16, 0x00060330}, |
| 1361 | {0x16, 0x00020330}, |
| 1362 | {0xff, 0xffffffff} |
| 1363 | }; |
| 1364 | |
| 1365 | static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = { |
| 1366 | {0x00, 0x00030159}, {0x01, 0x00031284}, |
| 1367 | {0x02, 0x00098000}, {0x03, 0x00018c63}, |
| 1368 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, |
| 1369 | {0x0a, 0x0001adb1}, {0x0b, 0x00054867}, |
| 1370 | {0x0c, 0x0008992e}, {0x0d, 0x0000e52c}, |
| 1371 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, |
| 1372 | {0x19, 0x00000000}, {0x1a, 0x00010255}, |
| 1373 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, |
| 1374 | {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, |
| 1375 | {0x1f, 0x00080001}, {0x20, 0x0000b614}, |
| 1376 | {0x21, 0x0006c000}, {0x22, 0x00000000}, |
| 1377 | {0x23, 0x00001558}, {0x24, 0x00000060}, |
| 1378 | {0x25, 0x00000483}, {0x26, 0x0004f000}, |
| 1379 | {0x27, 0x000ec7d9}, {0x28, 0x000577c0}, |
| 1380 | {0x29, 0x00004783}, {0x2a, 0x00000001}, |
| 1381 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, |
| 1382 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, |
| 1383 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, |
| 1384 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, |
| 1385 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, |
| 1386 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, |
| 1387 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, |
| 1388 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, |
| 1389 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, |
| 1390 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, |
| 1391 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, |
| 1392 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, |
| 1393 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, |
| 1394 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, |
| 1395 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, |
| 1396 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, |
| 1397 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, |
| 1398 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, |
| 1399 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, |
| 1400 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, |
| 1401 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, |
| 1402 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, |
| 1403 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, |
| 1404 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, |
| 1405 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, |
| 1406 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, |
| 1407 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, |
| 1408 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, |
| 1409 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, |
| 1410 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, |
| 1411 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, |
| 1412 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, |
| 1413 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, |
| 1414 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, |
| 1415 | {0x10, 0x00000000}, {0x11, 0x00000000}, |
| 1416 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, |
| 1417 | {0x10, 0x0009000f}, {0x11, 0x00023100}, |
| 1418 | {0x12, 0x00032000}, {0x12, 0x00071000}, |
| 1419 | {0x12, 0x000b0000}, {0x12, 0x000fc000}, |
| 1420 | {0x13, 0x000287b3}, {0x13, 0x000244b7}, |
| 1421 | {0x13, 0x000204ab}, {0x13, 0x0001c49f}, |
| 1422 | {0x13, 0x00018493}, {0x13, 0x0001429b}, |
| 1423 | {0x13, 0x00010299}, {0x13, 0x0000c29c}, |
| 1424 | {0x13, 0x000081a0}, {0x13, 0x000040ac}, |
| 1425 | {0x13, 0x00000020}, {0x14, 0x0001944c}, |
| 1426 | {0x14, 0x00059444}, {0x14, 0x0009944c}, |
| 1427 | {0x14, 0x000d9444}, {0x15, 0x0000f405}, |
| 1428 | {0x15, 0x0004f405}, {0x15, 0x0008f405}, |
| 1429 | {0x15, 0x000cf405}, {0x16, 0x000e0330}, |
| 1430 | {0x16, 0x000a0330}, {0x16, 0x00060330}, |
| 1431 | {0x16, 0x00020330}, {0x00, 0x00010159}, |
| 1432 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, |
| 1433 | {0xfe, 0x00000000}, {0x1f, 0x00080003}, |
| 1434 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 1435 | {0x1e, 0x00044457}, {0x1f, 0x00080000}, |
| 1436 | {0x00, 0x00030159}, |
| 1437 | {0xff, 0xffffffff} |
| 1438 | }; |
| 1439 | |
| 1440 | static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = { |
| 1441 | {0x00, 0x00030159}, {0x01, 0x00031284}, |
| 1442 | {0x02, 0x00098000}, {0x03, 0x00018c63}, |
| 1443 | {0x04, 0x000210e7}, {0x09, 0x0002044f}, |
| 1444 | {0x0a, 0x0001adb0}, {0x0b, 0x00054867}, |
| 1445 | {0x0c, 0x0008992e}, {0x0d, 0x0000e529}, |
| 1446 | {0x0e, 0x00039ce7}, {0x0f, 0x00000451}, |
| 1447 | {0x19, 0x00000000}, {0x1a, 0x00000255}, |
| 1448 | {0x1b, 0x00060a00}, {0x1c, 0x000fc378}, |
| 1449 | {0x1d, 0x000a1250}, {0x1e, 0x0004445f}, |
| 1450 | {0x1f, 0x00080001}, {0x20, 0x0000b614}, |
| 1451 | {0x21, 0x0006c000}, {0x22, 0x0000083c}, |
| 1452 | {0x23, 0x00001558}, {0x24, 0x00000060}, |
| 1453 | {0x25, 0x00000483}, {0x26, 0x0004f000}, |
| 1454 | {0x27, 0x000ec7d9}, {0x28, 0x000977c0}, |
| 1455 | {0x29, 0x00004783}, {0x2a, 0x00000001}, |
| 1456 | {0x2b, 0x00021334}, {0x2a, 0x00000000}, |
| 1457 | {0x2b, 0x00000054}, {0x2a, 0x00000001}, |
| 1458 | {0x2b, 0x00000808}, {0x2b, 0x00053333}, |
| 1459 | {0x2c, 0x0000000c}, {0x2a, 0x00000002}, |
| 1460 | {0x2b, 0x00000808}, {0x2b, 0x0005b333}, |
| 1461 | {0x2c, 0x0000000d}, {0x2a, 0x00000003}, |
| 1462 | {0x2b, 0x00000808}, {0x2b, 0x00063333}, |
| 1463 | {0x2c, 0x0000000d}, {0x2a, 0x00000004}, |
| 1464 | {0x2b, 0x00000808}, {0x2b, 0x0006b333}, |
| 1465 | {0x2c, 0x0000000d}, {0x2a, 0x00000005}, |
| 1466 | {0x2b, 0x00000808}, {0x2b, 0x00073333}, |
| 1467 | {0x2c, 0x0000000d}, {0x2a, 0x00000006}, |
| 1468 | {0x2b, 0x00000709}, {0x2b, 0x0005b333}, |
| 1469 | {0x2c, 0x0000000d}, {0x2a, 0x00000007}, |
| 1470 | {0x2b, 0x00000709}, {0x2b, 0x00063333}, |
| 1471 | {0x2c, 0x0000000d}, {0x2a, 0x00000008}, |
| 1472 | {0x2b, 0x0000060a}, {0x2b, 0x0004b333}, |
| 1473 | {0x2c, 0x0000000d}, {0x2a, 0x00000009}, |
| 1474 | {0x2b, 0x0000060a}, {0x2b, 0x00053333}, |
| 1475 | {0x2c, 0x0000000d}, {0x2a, 0x0000000a}, |
| 1476 | {0x2b, 0x0000060a}, {0x2b, 0x0005b333}, |
| 1477 | {0x2c, 0x0000000d}, {0x2a, 0x0000000b}, |
| 1478 | {0x2b, 0x0000060a}, {0x2b, 0x00063333}, |
| 1479 | {0x2c, 0x0000000d}, {0x2a, 0x0000000c}, |
| 1480 | {0x2b, 0x0000060a}, {0x2b, 0x0006b333}, |
| 1481 | {0x2c, 0x0000000d}, {0x2a, 0x0000000d}, |
| 1482 | {0x2b, 0x0000060a}, {0x2b, 0x00073333}, |
| 1483 | {0x2c, 0x0000000d}, {0x2a, 0x0000000e}, |
| 1484 | {0x2b, 0x0000050b}, {0x2b, 0x00066666}, |
| 1485 | {0x2c, 0x0000001a}, {0x2a, 0x000e0000}, |
| 1486 | {0x10, 0x0004000f}, {0x11, 0x000e31fc}, |
| 1487 | {0x10, 0x0006000f}, {0x11, 0x000ff9f8}, |
| 1488 | {0x10, 0x0002000f}, {0x11, 0x000203f9}, |
| 1489 | {0x10, 0x0003000f}, {0x11, 0x000ff500}, |
| 1490 | {0x10, 0x00000000}, {0x11, 0x00000000}, |
| 1491 | {0x10, 0x0008000f}, {0x11, 0x0003f100}, |
| 1492 | {0x10, 0x0009000f}, {0x11, 0x00023100}, |
| 1493 | {0x12, 0x000d8000}, {0x12, 0x00090000}, |
| 1494 | {0x12, 0x00051000}, {0x12, 0x00012000}, |
| 1495 | {0x13, 0x00028fb4}, {0x13, 0x00024fa8}, |
| 1496 | {0x13, 0x000207a4}, {0x13, 0x0001c3b0}, |
| 1497 | {0x13, 0x000183a4}, {0x13, 0x00014398}, |
| 1498 | {0x13, 0x000101a4}, {0x13, 0x0000c198}, |
| 1499 | {0x13, 0x000080a4}, {0x13, 0x00004098}, |
| 1500 | {0x13, 0x00000000}, {0x14, 0x0001944c}, |
| 1501 | {0x14, 0x00059444}, {0x14, 0x0009944c}, |
| 1502 | {0x14, 0x000d9444}, {0x15, 0x0000f405}, |
| 1503 | {0x15, 0x0004f405}, {0x15, 0x0008f405}, |
| 1504 | {0x15, 0x000cf405}, {0x16, 0x000e0330}, |
| 1505 | {0x16, 0x000a0330}, {0x16, 0x00060330}, |
| 1506 | {0x16, 0x00020330}, {0x00, 0x00010159}, |
| 1507 | {0x18, 0x0000f401}, {0xfe, 0x00000000}, |
| 1508 | {0xfe, 0x00000000}, {0x1f, 0x00080003}, |
| 1509 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 1510 | {0x1e, 0x00044457}, {0x1f, 0x00080000}, |
| 1511 | {0x00, 0x00030159}, |
| 1512 | {0xff, 0xffffffff} |
| 1513 | }; |
| 1514 | |
Jes Sorensen | 19102f8 | 2016-04-07 14:19:19 -0400 | [diff] [blame] | 1515 | static struct rtl8xxxu_rfregval rtl8192eu_radioa_init_table[] = { |
| 1516 | {0x7f, 0x00000082}, {0x81, 0x0003fc00}, |
| 1517 | {0x00, 0x00030000}, {0x08, 0x00008400}, |
| 1518 | {0x18, 0x00000407}, {0x19, 0x00000012}, |
| 1519 | {0x1b, 0x00000064}, {0x1e, 0x00080009}, |
| 1520 | {0x1f, 0x00000880}, {0x2f, 0x0001a060}, |
| 1521 | {0x3f, 0x00000000}, {0x42, 0x000060c0}, |
| 1522 | {0x57, 0x000d0000}, {0x58, 0x000be180}, |
| 1523 | {0x67, 0x00001552}, {0x83, 0x00000000}, |
| 1524 | {0xb0, 0x000ff9f1}, {0xb1, 0x00055418}, |
| 1525 | {0xb2, 0x0008cc00}, {0xb4, 0x00043083}, |
| 1526 | {0xb5, 0x00008166}, {0xb6, 0x0000803e}, |
| 1527 | {0xb7, 0x0001c69f}, {0xb8, 0x0000407f}, |
| 1528 | {0xb9, 0x00080001}, {0xba, 0x00040001}, |
| 1529 | {0xbb, 0x00000400}, {0xbf, 0x000c0000}, |
| 1530 | {0xc2, 0x00002400}, {0xc3, 0x00000009}, |
| 1531 | {0xc4, 0x00040c91}, {0xc5, 0x00099999}, |
| 1532 | {0xc6, 0x000000a3}, {0xc7, 0x00088820}, |
| 1533 | {0xc8, 0x00076c06}, {0xc9, 0x00000000}, |
| 1534 | {0xca, 0x00080000}, {0xdf, 0x00000180}, |
| 1535 | {0xef, 0x000001a0}, {0x51, 0x00069545}, |
| 1536 | {0x52, 0x0007e45e}, {0x53, 0x00000071}, |
| 1537 | {0x56, 0x00051ff3}, {0x35, 0x000000a8}, |
| 1538 | {0x35, 0x000001e2}, {0x35, 0x000002a8}, |
| 1539 | {0x36, 0x00001c24}, {0x36, 0x00009c24}, |
| 1540 | {0x36, 0x00011c24}, {0x36, 0x00019c24}, |
| 1541 | {0x18, 0x00000c07}, {0x5a, 0x00048000}, |
| 1542 | {0x19, 0x000739d0}, |
| 1543 | #ifdef EXT_PA_8192EU |
| 1544 | /* External PA or external LNA */ |
| 1545 | {0x34, 0x0000a093}, {0x34, 0x0000908f}, |
| 1546 | {0x34, 0x0000808c}, {0x34, 0x0000704d}, |
| 1547 | {0x34, 0x0000604a}, {0x34, 0x00005047}, |
| 1548 | {0x34, 0x0000400a}, {0x34, 0x00003007}, |
| 1549 | {0x34, 0x00002004}, {0x34, 0x00001001}, |
| 1550 | {0x34, 0x00000000}, |
| 1551 | #else |
| 1552 | /* Regular */ |
| 1553 | {0x34, 0x0000add7}, {0x34, 0x00009dd4}, |
| 1554 | {0x34, 0x00008dd1}, {0x34, 0x00007dce}, |
| 1555 | {0x34, 0x00006dcb}, {0x34, 0x00005dc8}, |
| 1556 | {0x34, 0x00004dc5}, {0x34, 0x000034cc}, |
| 1557 | {0x34, 0x0000244f}, {0x34, 0x0000144c}, |
| 1558 | {0x34, 0x00000014}, |
| 1559 | #endif |
| 1560 | {0x00, 0x00030159}, |
| 1561 | {0x84, 0x00068180}, |
| 1562 | {0x86, 0x0000014e}, |
| 1563 | {0x87, 0x00048e00}, |
| 1564 | {0x8e, 0x00065540}, |
| 1565 | {0x8f, 0x00088000}, |
| 1566 | {0xef, 0x000020a0}, |
| 1567 | #ifdef EXT_PA_8192EU |
| 1568 | /* External PA or external LNA */ |
| 1569 | {0x3b, 0x000f07b0}, |
| 1570 | #else |
| 1571 | {0x3b, 0x000f02b0}, |
| 1572 | #endif |
| 1573 | {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, |
| 1574 | {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, |
| 1575 | {0x3b, 0x000a0080}, {0x3b, 0x00090080}, |
| 1576 | {0x3b, 0x0008f780}, |
| 1577 | #ifdef EXT_PA_8192EU |
| 1578 | /* External PA or external LNA */ |
| 1579 | {0x3b, 0x000787b0}, |
| 1580 | #else |
| 1581 | {0x3b, 0x00078730}, |
| 1582 | #endif |
| 1583 | {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0}, |
| 1584 | {0x3b, 0x00040620}, {0x3b, 0x00037090}, |
| 1585 | {0x3b, 0x00020080}, {0x3b, 0x0001f060}, |
| 1586 | {0x3b, 0x0000ffb0}, {0xef, 0x000000a0}, |
| 1587 | {0xfe, 0x00000000}, {0x18, 0x0000fc07}, |
| 1588 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 1589 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 1590 | {0x1e, 0x00000001}, {0x1f, 0x00080000}, |
| 1591 | {0x00, 0x00033e70}, |
| 1592 | {0xff, 0xffffffff} |
| 1593 | }; |
| 1594 | |
| 1595 | static struct rtl8xxxu_rfregval rtl8192eu_radiob_init_table[] = { |
| 1596 | {0x7f, 0x00000082}, {0x81, 0x0003fc00}, |
| 1597 | {0x00, 0x00030000}, {0x08, 0x00008400}, |
| 1598 | {0x18, 0x00000407}, {0x19, 0x00000012}, |
| 1599 | {0x1b, 0x00000064}, {0x1e, 0x00080009}, |
| 1600 | {0x1f, 0x00000880}, {0x2f, 0x0001a060}, |
| 1601 | {0x3f, 0x00000000}, {0x42, 0x000060c0}, |
| 1602 | {0x57, 0x000d0000}, {0x58, 0x000be180}, |
| 1603 | {0x67, 0x00001552}, {0x7f, 0x00000082}, |
| 1604 | {0x81, 0x0003f000}, {0x83, 0x00000000}, |
| 1605 | {0xdf, 0x00000180}, {0xef, 0x000001a0}, |
| 1606 | {0x51, 0x00069545}, {0x52, 0x0007e42e}, |
| 1607 | {0x53, 0x00000071}, {0x56, 0x00051ff3}, |
| 1608 | {0x35, 0x000000a8}, {0x35, 0x000001e0}, |
| 1609 | {0x35, 0x000002a8}, {0x36, 0x00001ca8}, |
| 1610 | {0x36, 0x00009c24}, {0x36, 0x00011c24}, |
| 1611 | {0x36, 0x00019c24}, {0x18, 0x00000c07}, |
| 1612 | {0x5a, 0x00048000}, {0x19, 0x000739d0}, |
| 1613 | #ifdef EXT_PA_8192EU |
| 1614 | /* External PA or external LNA */ |
| 1615 | {0x34, 0x0000a093}, {0x34, 0x0000908f}, |
| 1616 | {0x34, 0x0000808c}, {0x34, 0x0000704d}, |
| 1617 | {0x34, 0x0000604a}, {0x34, 0x00005047}, |
| 1618 | {0x34, 0x0000400a}, {0x34, 0x00003007}, |
| 1619 | {0x34, 0x00002004}, {0x34, 0x00001001}, |
| 1620 | {0x34, 0x00000000}, |
| 1621 | #else |
| 1622 | {0x34, 0x0000add7}, {0x34, 0x00009dd4}, |
| 1623 | {0x34, 0x00008dd1}, {0x34, 0x00007dce}, |
| 1624 | {0x34, 0x00006dcb}, {0x34, 0x00005dc8}, |
| 1625 | {0x34, 0x00004dc5}, {0x34, 0x000034cc}, |
| 1626 | {0x34, 0x0000244f}, {0x34, 0x0000144c}, |
| 1627 | {0x34, 0x00000014}, |
| 1628 | #endif |
| 1629 | {0x00, 0x00030159}, {0x84, 0x00068180}, |
| 1630 | {0x86, 0x000000ce}, {0x87, 0x00048a00}, |
| 1631 | {0x8e, 0x00065540}, {0x8f, 0x00088000}, |
| 1632 | {0xef, 0x000020a0}, |
| 1633 | #ifdef EXT_PA_8192EU |
| 1634 | /* External PA or external LNA */ |
| 1635 | {0x3b, 0x000f07b0}, |
| 1636 | #else |
| 1637 | {0x3b, 0x000f02b0}, |
| 1638 | #endif |
| 1639 | |
| 1640 | {0x3b, 0x000ef7b0}, {0x3b, 0x000d4fb0}, |
| 1641 | {0x3b, 0x000cf060}, {0x3b, 0x000b0090}, |
| 1642 | {0x3b, 0x000a0080}, {0x3b, 0x00090080}, |
| 1643 | {0x3b, 0x0008f780}, |
| 1644 | #ifdef EXT_PA_8192EU |
| 1645 | /* External PA or external LNA */ |
| 1646 | {0x3b, 0x000787b0}, |
| 1647 | #else |
| 1648 | {0x3b, 0x00078730}, |
| 1649 | #endif |
| 1650 | {0x3b, 0x00060fb0}, {0x3b, 0x0005ffa0}, |
| 1651 | {0x3b, 0x00040620}, {0x3b, 0x00037090}, |
| 1652 | {0x3b, 0x00020080}, {0x3b, 0x0001f060}, |
| 1653 | {0x3b, 0x0000ffb0}, {0xef, 0x000000a0}, |
| 1654 | {0x00, 0x00010159}, {0xfe, 0x00000000}, |
| 1655 | {0xfe, 0x00000000}, {0xfe, 0x00000000}, |
| 1656 | {0xfe, 0x00000000}, {0x1e, 0x00000001}, |
| 1657 | {0x1f, 0x00080000}, {0x00, 0x00033e70}, |
| 1658 | {0xff, 0xffffffff} |
| 1659 | }; |
| 1660 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1661 | static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = { |
| 1662 | { /* RF_A */ |
| 1663 | .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1, |
| 1664 | .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2, |
| 1665 | .lssiparm = REG_FPGA0_XA_LSSI_PARM, |
| 1666 | .hspiread = REG_HSPI_XA_READBACK, |
| 1667 | .lssiread = REG_FPGA0_XA_LSSI_READBACK, |
| 1668 | .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL, |
| 1669 | }, |
| 1670 | { /* RF_B */ |
| 1671 | .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1, |
| 1672 | .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2, |
| 1673 | .lssiparm = REG_FPGA0_XB_LSSI_PARM, |
| 1674 | .hspiread = REG_HSPI_XB_READBACK, |
| 1675 | .lssiread = REG_FPGA0_XB_LSSI_READBACK, |
| 1676 | .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL, |
| 1677 | }, |
| 1678 | }; |
| 1679 | |
| 1680 | static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = { |
| 1681 | REG_OFDM0_XA_RX_IQ_IMBALANCE, |
| 1682 | REG_OFDM0_XB_RX_IQ_IMBALANCE, |
| 1683 | REG_OFDM0_ENERGY_CCA_THRES, |
| 1684 | REG_OFDM0_AGCR_SSI_TABLE, |
| 1685 | REG_OFDM0_XA_TX_IQ_IMBALANCE, |
| 1686 | REG_OFDM0_XB_TX_IQ_IMBALANCE, |
| 1687 | REG_OFDM0_XC_TX_AFE, |
| 1688 | REG_OFDM0_XD_TX_AFE, |
| 1689 | REG_OFDM0_RX_IQ_EXT_ANTA |
| 1690 | }; |
| 1691 | |
| 1692 | static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr) |
| 1693 | { |
| 1694 | struct usb_device *udev = priv->udev; |
| 1695 | int len; |
| 1696 | u8 data; |
| 1697 | |
| 1698 | mutex_lock(&priv->usb_buf_mutex); |
| 1699 | len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), |
| 1700 | REALTEK_USB_CMD_REQ, REALTEK_USB_READ, |
| 1701 | addr, 0, &priv->usb_buf.val8, sizeof(u8), |
| 1702 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1703 | data = priv->usb_buf.val8; |
| 1704 | mutex_unlock(&priv->usb_buf_mutex); |
| 1705 | |
| 1706 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) |
| 1707 | dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n", |
| 1708 | __func__, addr, data, len); |
| 1709 | return data; |
| 1710 | } |
| 1711 | |
| 1712 | static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr) |
| 1713 | { |
| 1714 | struct usb_device *udev = priv->udev; |
| 1715 | int len; |
| 1716 | u16 data; |
| 1717 | |
| 1718 | mutex_lock(&priv->usb_buf_mutex); |
| 1719 | len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), |
| 1720 | REALTEK_USB_CMD_REQ, REALTEK_USB_READ, |
| 1721 | addr, 0, &priv->usb_buf.val16, sizeof(u16), |
| 1722 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1723 | data = le16_to_cpu(priv->usb_buf.val16); |
| 1724 | mutex_unlock(&priv->usb_buf_mutex); |
| 1725 | |
| 1726 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) |
| 1727 | dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n", |
| 1728 | __func__, addr, data, len); |
| 1729 | return data; |
| 1730 | } |
| 1731 | |
| 1732 | static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr) |
| 1733 | { |
| 1734 | struct usb_device *udev = priv->udev; |
| 1735 | int len; |
| 1736 | u32 data; |
| 1737 | |
| 1738 | mutex_lock(&priv->usb_buf_mutex); |
| 1739 | len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), |
| 1740 | REALTEK_USB_CMD_REQ, REALTEK_USB_READ, |
| 1741 | addr, 0, &priv->usb_buf.val32, sizeof(u32), |
| 1742 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1743 | data = le32_to_cpu(priv->usb_buf.val32); |
| 1744 | mutex_unlock(&priv->usb_buf_mutex); |
| 1745 | |
| 1746 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ) |
| 1747 | dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n", |
| 1748 | __func__, addr, data, len); |
| 1749 | return data; |
| 1750 | } |
| 1751 | |
| 1752 | static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val) |
| 1753 | { |
| 1754 | struct usb_device *udev = priv->udev; |
| 1755 | int ret; |
| 1756 | |
| 1757 | mutex_lock(&priv->usb_buf_mutex); |
| 1758 | priv->usb_buf.val8 = val; |
| 1759 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), |
| 1760 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, |
| 1761 | addr, 0, &priv->usb_buf.val8, sizeof(u8), |
| 1762 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1763 | |
| 1764 | mutex_unlock(&priv->usb_buf_mutex); |
| 1765 | |
| 1766 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) |
| 1767 | dev_info(&udev->dev, "%s(%04x) = 0x%02x\n", |
| 1768 | __func__, addr, val); |
| 1769 | return ret; |
| 1770 | } |
| 1771 | |
| 1772 | static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val) |
| 1773 | { |
| 1774 | struct usb_device *udev = priv->udev; |
| 1775 | int ret; |
| 1776 | |
| 1777 | mutex_lock(&priv->usb_buf_mutex); |
| 1778 | priv->usb_buf.val16 = cpu_to_le16(val); |
| 1779 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), |
| 1780 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, |
| 1781 | addr, 0, &priv->usb_buf.val16, sizeof(u16), |
| 1782 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1783 | mutex_unlock(&priv->usb_buf_mutex); |
| 1784 | |
| 1785 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) |
| 1786 | dev_info(&udev->dev, "%s(%04x) = 0x%04x\n", |
| 1787 | __func__, addr, val); |
| 1788 | return ret; |
| 1789 | } |
| 1790 | |
| 1791 | static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val) |
| 1792 | { |
| 1793 | struct usb_device *udev = priv->udev; |
| 1794 | int ret; |
| 1795 | |
| 1796 | mutex_lock(&priv->usb_buf_mutex); |
| 1797 | priv->usb_buf.val32 = cpu_to_le32(val); |
| 1798 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), |
| 1799 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, |
| 1800 | addr, 0, &priv->usb_buf.val32, sizeof(u32), |
| 1801 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1802 | mutex_unlock(&priv->usb_buf_mutex); |
| 1803 | |
| 1804 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE) |
| 1805 | dev_info(&udev->dev, "%s(%04x) = 0x%08x\n", |
| 1806 | __func__, addr, val); |
| 1807 | return ret; |
| 1808 | } |
| 1809 | |
| 1810 | static int |
| 1811 | rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len) |
| 1812 | { |
| 1813 | struct usb_device *udev = priv->udev; |
| 1814 | int blocksize = priv->fops->writeN_block_size; |
| 1815 | int ret, i, count, remainder; |
| 1816 | |
| 1817 | count = len / blocksize; |
| 1818 | remainder = len % blocksize; |
| 1819 | |
| 1820 | for (i = 0; i < count; i++) { |
| 1821 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), |
| 1822 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, |
| 1823 | addr, 0, buf, blocksize, |
| 1824 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1825 | if (ret != blocksize) |
| 1826 | goto write_error; |
| 1827 | |
| 1828 | addr += blocksize; |
| 1829 | buf += blocksize; |
| 1830 | } |
| 1831 | |
| 1832 | if (remainder) { |
| 1833 | ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0), |
| 1834 | REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE, |
| 1835 | addr, 0, buf, remainder, |
| 1836 | RTW_USB_CONTROL_MSG_TIMEOUT); |
| 1837 | if (ret != remainder) |
| 1838 | goto write_error; |
| 1839 | } |
| 1840 | |
| 1841 | return len; |
| 1842 | |
| 1843 | write_error: |
| 1844 | dev_info(&udev->dev, |
| 1845 | "%s: Failed to write block at addr: %04x size: %04x\n", |
| 1846 | __func__, addr, blocksize); |
| 1847 | return -EAGAIN; |
| 1848 | } |
| 1849 | |
| 1850 | static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv, |
| 1851 | enum rtl8xxxu_rfpath path, u8 reg) |
| 1852 | { |
| 1853 | u32 hssia, val32, retval; |
| 1854 | |
| 1855 | hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2); |
| 1856 | if (path != RF_A) |
| 1857 | val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2); |
| 1858 | else |
| 1859 | val32 = hssia; |
| 1860 | |
| 1861 | val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK; |
| 1862 | val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT); |
| 1863 | val32 |= FPGA0_HSSI_PARM2_EDGE_READ; |
| 1864 | hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ; |
| 1865 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); |
| 1866 | |
| 1867 | udelay(10); |
| 1868 | |
| 1869 | rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32); |
| 1870 | udelay(100); |
| 1871 | |
| 1872 | hssia |= FPGA0_HSSI_PARM2_EDGE_READ; |
| 1873 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia); |
| 1874 | udelay(10); |
| 1875 | |
| 1876 | val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1); |
| 1877 | if (val32 & FPGA0_HSSI_PARM1_PI) |
| 1878 | retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread); |
| 1879 | else |
| 1880 | retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread); |
| 1881 | |
| 1882 | retval &= 0xfffff; |
| 1883 | |
| 1884 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ) |
| 1885 | dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", |
| 1886 | __func__, reg, retval); |
| 1887 | return retval; |
| 1888 | } |
| 1889 | |
Jes Sorensen | 22a31d4 | 2016-02-29 17:04:15 -0500 | [diff] [blame] | 1890 | /* |
| 1891 | * The RTL8723BU driver indicates that registers 0xb2 and 0xb6 can |
| 1892 | * have write issues in high temperature conditions. We may have to |
| 1893 | * retry writing them. |
| 1894 | */ |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1895 | static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv, |
| 1896 | enum rtl8xxxu_rfpath path, u8 reg, u32 data) |
| 1897 | { |
| 1898 | int ret, retval; |
Jes Sorensen | 2949b9e | 2016-04-07 14:19:25 -0400 | [diff] [blame] | 1899 | u32 dataaddr, val32; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1900 | |
| 1901 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE) |
| 1902 | dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n", |
| 1903 | __func__, reg, data); |
| 1904 | |
| 1905 | data &= FPGA0_LSSI_PARM_DATA_MASK; |
| 1906 | dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data; |
| 1907 | |
Jes Sorensen | 2949b9e | 2016-04-07 14:19:25 -0400 | [diff] [blame] | 1908 | if (priv->rtl_chip == RTL8192E) { |
| 1909 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); |
| 1910 | val32 &= ~0x20000; |
| 1911 | rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); |
| 1912 | } |
| 1913 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1914 | /* Use XB for path B */ |
| 1915 | ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr); |
| 1916 | if (ret != sizeof(dataaddr)) |
| 1917 | retval = -EIO; |
| 1918 | else |
| 1919 | retval = 0; |
| 1920 | |
| 1921 | udelay(1); |
| 1922 | |
Jes Sorensen | 2949b9e | 2016-04-07 14:19:25 -0400 | [diff] [blame] | 1923 | if (priv->rtl_chip == RTL8192E) { |
| 1924 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); |
| 1925 | val32 |= 0x20000; |
| 1926 | rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); |
| 1927 | } |
| 1928 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1929 | return retval; |
| 1930 | } |
| 1931 | |
Jes Sorensen | 8da9157 | 2016-02-29 17:04:29 -0500 | [diff] [blame] | 1932 | static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, |
| 1933 | struct h2c_cmd *h2c, int len) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1934 | { |
| 1935 | struct device *dev = &priv->udev->dev; |
| 1936 | int mbox_nr, retry, retval = 0; |
| 1937 | int mbox_reg, mbox_ext_reg; |
| 1938 | u8 val8; |
| 1939 | |
| 1940 | mutex_lock(&priv->h2c_mutex); |
| 1941 | |
| 1942 | mbox_nr = priv->next_mbox; |
| 1943 | mbox_reg = REG_HMBOX_0 + (mbox_nr * 4); |
Jes Sorensen | ed35d09 | 2016-02-29 17:04:19 -0500 | [diff] [blame] | 1944 | mbox_ext_reg = priv->fops->mbox_ext_reg + |
| 1945 | (mbox_nr * priv->fops->mbox_ext_width); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1946 | |
| 1947 | /* |
| 1948 | * MBOX ready? |
| 1949 | */ |
| 1950 | retry = 100; |
| 1951 | do { |
| 1952 | val8 = rtl8xxxu_read8(priv, REG_HMTFR); |
| 1953 | if (!(val8 & BIT(mbox_nr))) |
| 1954 | break; |
| 1955 | } while (retry--); |
| 1956 | |
| 1957 | if (!retry) { |
Jes Sorensen | c7a5a19 | 2016-02-29 17:04:30 -0500 | [diff] [blame] | 1958 | dev_info(dev, "%s: Mailbox busy\n", __func__); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1959 | retval = -EBUSY; |
| 1960 | goto error; |
| 1961 | } |
| 1962 | |
| 1963 | /* |
| 1964 | * Need to swap as it's being swapped again by rtl8xxxu_write16/32() |
| 1965 | */ |
Jes Sorensen | 8da9157 | 2016-02-29 17:04:29 -0500 | [diff] [blame] | 1966 | if (len > sizeof(u32)) { |
Jes Sorensen | ed35d09 | 2016-02-29 17:04:19 -0500 | [diff] [blame] | 1967 | if (priv->fops->mbox_ext_width == 4) { |
| 1968 | rtl8xxxu_write32(priv, mbox_ext_reg, |
| 1969 | le32_to_cpu(h2c->raw_wide.ext)); |
| 1970 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) |
| 1971 | dev_info(dev, "H2C_EXT %08x\n", |
| 1972 | le32_to_cpu(h2c->raw_wide.ext)); |
| 1973 | } else { |
| 1974 | rtl8xxxu_write16(priv, mbox_ext_reg, |
| 1975 | le16_to_cpu(h2c->raw.ext)); |
| 1976 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) |
| 1977 | dev_info(dev, "H2C_EXT %04x\n", |
| 1978 | le16_to_cpu(h2c->raw.ext)); |
| 1979 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 1980 | } |
| 1981 | rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data)); |
| 1982 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C) |
| 1983 | dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data)); |
| 1984 | |
| 1985 | priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX; |
| 1986 | |
| 1987 | error: |
| 1988 | mutex_unlock(&priv->h2c_mutex); |
| 1989 | return retval; |
| 1990 | } |
| 1991 | |
Jes Sorensen | 394f1bd | 2016-02-29 17:04:49 -0500 | [diff] [blame] | 1992 | static void rtl8723bu_write_btreg(struct rtl8xxxu_priv *priv, u8 reg, u8 data) |
| 1993 | { |
| 1994 | struct h2c_cmd h2c; |
| 1995 | int reqnum = 0; |
| 1996 | |
| 1997 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 1998 | h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; |
| 1999 | h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); |
| 2000 | h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; |
| 2001 | h2c.bt_mp_oper.data = data; |
| 2002 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); |
| 2003 | |
| 2004 | reqnum++; |
| 2005 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 2006 | h2c.bt_mp_oper.cmd = H2C_8723B_BT_MP_OPER; |
| 2007 | h2c.bt_mp_oper.operreq = 0 | (reqnum << 4); |
| 2008 | h2c.bt_mp_oper.opcode = BT_MP_OP_WRITE_REG_VALUE; |
| 2009 | h2c.bt_mp_oper.addr = reg; |
| 2010 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_mp_oper)); |
| 2011 | } |
| 2012 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2013 | static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv) |
| 2014 | { |
| 2015 | u8 val8; |
| 2016 | u32 val32; |
| 2017 | |
| 2018 | val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); |
| 2019 | val8 |= BIT(0) | BIT(3); |
| 2020 | rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8); |
| 2021 | |
| 2022 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); |
| 2023 | val32 &= ~(BIT(4) | BIT(5)); |
| 2024 | val32 |= BIT(3); |
| 2025 | if (priv->rf_paths == 2) { |
| 2026 | val32 &= ~(BIT(20) | BIT(21)); |
| 2027 | val32 |= BIT(19); |
| 2028 | } |
| 2029 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); |
| 2030 | |
| 2031 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); |
| 2032 | val32 &= ~OFDM_RF_PATH_TX_MASK; |
| 2033 | if (priv->tx_paths == 2) |
| 2034 | val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B; |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 2035 | else if (priv->rtl_chip == RTL8192C || priv->rtl_chip == RTL8191C) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2036 | val32 |= OFDM_RF_PATH_TX_B; |
| 2037 | else |
| 2038 | val32 |= OFDM_RF_PATH_TX_A; |
| 2039 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); |
| 2040 | |
| 2041 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 2042 | val32 &= ~FPGA_RF_MODE_JAPAN; |
| 2043 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 2044 | |
| 2045 | if (priv->rf_paths == 2) |
| 2046 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0); |
| 2047 | else |
| 2048 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0); |
| 2049 | |
| 2050 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95); |
| 2051 | if (priv->rf_paths == 2) |
| 2052 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95); |
| 2053 | |
| 2054 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); |
| 2055 | } |
| 2056 | |
| 2057 | static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv) |
| 2058 | { |
| 2059 | u8 sps0; |
| 2060 | u32 val32; |
| 2061 | |
| 2062 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); |
| 2063 | |
| 2064 | sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL); |
| 2065 | |
| 2066 | /* RF RX code for preamble power saving */ |
| 2067 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM); |
| 2068 | val32 &= ~(BIT(3) | BIT(4) | BIT(5)); |
| 2069 | if (priv->rf_paths == 2) |
| 2070 | val32 &= ~(BIT(19) | BIT(20) | BIT(21)); |
| 2071 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32); |
| 2072 | |
| 2073 | /* Disable TX for four paths */ |
| 2074 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); |
| 2075 | val32 &= ~OFDM_RF_PATH_TX_MASK; |
| 2076 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); |
| 2077 | |
| 2078 | /* Enable power saving */ |
| 2079 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 2080 | val32 |= FPGA_RF_MODE_JAPAN; |
| 2081 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 2082 | |
| 2083 | /* AFE control register to power down bits [30:22] */ |
| 2084 | if (priv->rf_paths == 2) |
| 2085 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0); |
| 2086 | else |
| 2087 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0); |
| 2088 | |
| 2089 | /* Power down RF module */ |
| 2090 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0); |
| 2091 | if (priv->rf_paths == 2) |
| 2092 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0); |
| 2093 | |
| 2094 | sps0 &= ~(BIT(0) | BIT(3)); |
| 2095 | rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0); |
| 2096 | } |
| 2097 | |
| 2098 | |
| 2099 | static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv) |
| 2100 | { |
| 2101 | u8 val8; |
| 2102 | |
| 2103 | val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2); |
| 2104 | val8 &= ~BIT(6); |
| 2105 | rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8); |
| 2106 | |
| 2107 | rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64); |
| 2108 | val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2); |
| 2109 | val8 &= ~BIT(0); |
| 2110 | rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8); |
| 2111 | } |
| 2112 | |
| 2113 | |
| 2114 | /* |
| 2115 | * The rtl8723a has 3 channel groups for it's efuse settings. It only |
| 2116 | * supports the 2.4GHz band, so channels 1 - 14: |
| 2117 | * group 0: channels 1 - 3 |
| 2118 | * group 1: channels 4 - 9 |
| 2119 | * group 2: channels 10 - 14 |
| 2120 | * |
| 2121 | * Note: We index from 0 in the code |
| 2122 | */ |
| 2123 | static int rtl8723a_channel_to_group(int channel) |
| 2124 | { |
| 2125 | int group; |
| 2126 | |
| 2127 | if (channel < 4) |
| 2128 | group = 0; |
| 2129 | else if (channel < 10) |
| 2130 | group = 1; |
| 2131 | else |
| 2132 | group = 2; |
| 2133 | |
| 2134 | return group; |
| 2135 | } |
| 2136 | |
Jes Sorensen | 9e24772 | 2016-04-07 14:19:23 -0400 | [diff] [blame] | 2137 | /* |
| 2138 | * Valid for rtl8723bu and rtl8192eu |
| 2139 | */ |
Jes Sorensen | e796dab | 2016-02-29 17:05:19 -0500 | [diff] [blame] | 2140 | static int rtl8723b_channel_to_group(int channel) |
| 2141 | { |
| 2142 | int group; |
| 2143 | |
| 2144 | if (channel < 3) |
| 2145 | group = 0; |
| 2146 | else if (channel < 6) |
| 2147 | group = 1; |
| 2148 | else if (channel < 9) |
| 2149 | group = 2; |
| 2150 | else if (channel < 12) |
| 2151 | group = 3; |
| 2152 | else |
| 2153 | group = 4; |
| 2154 | |
| 2155 | return group; |
| 2156 | } |
| 2157 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2158 | static void rtl8723au_config_channel(struct ieee80211_hw *hw) |
| 2159 | { |
| 2160 | struct rtl8xxxu_priv *priv = hw->priv; |
| 2161 | u32 val32, rsr; |
| 2162 | u8 val8, opmode; |
| 2163 | bool ht = true; |
| 2164 | int sec_ch_above, channel; |
| 2165 | int i; |
| 2166 | |
| 2167 | opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE); |
| 2168 | rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); |
| 2169 | channel = hw->conf.chandef.chan->hw_value; |
| 2170 | |
| 2171 | switch (hw->conf.chandef.width) { |
| 2172 | case NL80211_CHAN_WIDTH_20_NOHT: |
| 2173 | ht = false; |
| 2174 | case NL80211_CHAN_WIDTH_20: |
| 2175 | opmode |= BW_OPMODE_20MHZ; |
| 2176 | rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); |
| 2177 | |
| 2178 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 2179 | val32 &= ~FPGA_RF_MODE; |
| 2180 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 2181 | |
| 2182 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); |
| 2183 | val32 &= ~FPGA_RF_MODE; |
| 2184 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); |
| 2185 | |
| 2186 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); |
| 2187 | val32 |= FPGA0_ANALOG2_20MHZ; |
| 2188 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); |
| 2189 | break; |
| 2190 | case NL80211_CHAN_WIDTH_40: |
| 2191 | if (hw->conf.chandef.center_freq1 > |
| 2192 | hw->conf.chandef.chan->center_freq) { |
| 2193 | sec_ch_above = 1; |
| 2194 | channel += 2; |
| 2195 | } else { |
| 2196 | sec_ch_above = 0; |
| 2197 | channel -= 2; |
| 2198 | } |
| 2199 | |
| 2200 | opmode &= ~BW_OPMODE_20MHZ; |
| 2201 | rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode); |
| 2202 | rsr &= ~RSR_RSC_BANDWIDTH_40M; |
| 2203 | if (sec_ch_above) |
| 2204 | rsr |= RSR_RSC_UPPER_SUB_CHANNEL; |
| 2205 | else |
| 2206 | rsr |= RSR_RSC_LOWER_SUB_CHANNEL; |
| 2207 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr); |
| 2208 | |
| 2209 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 2210 | val32 |= FPGA_RF_MODE; |
| 2211 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 2212 | |
| 2213 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); |
| 2214 | val32 |= FPGA_RF_MODE; |
| 2215 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); |
| 2216 | |
| 2217 | /* |
| 2218 | * Set Control channel to upper or lower. These settings |
| 2219 | * are required only for 40MHz |
| 2220 | */ |
| 2221 | val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); |
| 2222 | val32 &= ~CCK0_SIDEBAND; |
| 2223 | if (!sec_ch_above) |
| 2224 | val32 |= CCK0_SIDEBAND; |
| 2225 | rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); |
| 2226 | |
| 2227 | val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); |
| 2228 | val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ |
| 2229 | if (sec_ch_above) |
| 2230 | val32 |= OFDM_LSTF_PRIME_CH_LOW; |
| 2231 | else |
| 2232 | val32 |= OFDM_LSTF_PRIME_CH_HIGH; |
| 2233 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); |
| 2234 | |
| 2235 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2); |
| 2236 | val32 &= ~FPGA0_ANALOG2_20MHZ; |
| 2237 | rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32); |
| 2238 | |
| 2239 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); |
| 2240 | val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); |
| 2241 | if (sec_ch_above) |
| 2242 | val32 |= FPGA0_PS_UPPER_CHANNEL; |
| 2243 | else |
| 2244 | val32 |= FPGA0_PS_LOWER_CHANNEL; |
| 2245 | rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); |
| 2246 | break; |
| 2247 | |
| 2248 | default: |
| 2249 | break; |
| 2250 | } |
| 2251 | |
| 2252 | for (i = RF_A; i < priv->rf_paths; i++) { |
| 2253 | val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); |
| 2254 | val32 &= ~MODE_AG_CHANNEL_MASK; |
| 2255 | val32 |= channel; |
| 2256 | rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); |
| 2257 | } |
| 2258 | |
| 2259 | if (ht) |
| 2260 | val8 = 0x0e; |
| 2261 | else |
| 2262 | val8 = 0x0a; |
| 2263 | |
| 2264 | rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); |
| 2265 | rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); |
| 2266 | |
| 2267 | rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); |
| 2268 | rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); |
| 2269 | |
| 2270 | for (i = RF_A; i < priv->rf_paths; i++) { |
| 2271 | val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); |
| 2272 | if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40) |
| 2273 | val32 &= ~MODE_AG_CHANNEL_20MHZ; |
| 2274 | else |
| 2275 | val32 |= MODE_AG_CHANNEL_20MHZ; |
| 2276 | rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); |
| 2277 | } |
| 2278 | } |
| 2279 | |
Jes Sorensen | c3f9506 | 2016-02-29 17:04:40 -0500 | [diff] [blame] | 2280 | static void rtl8723bu_config_channel(struct ieee80211_hw *hw) |
| 2281 | { |
| 2282 | struct rtl8xxxu_priv *priv = hw->priv; |
| 2283 | u32 val32, rsr; |
Jes Sorensen | 368633c | 2016-02-29 17:04:42 -0500 | [diff] [blame] | 2284 | u8 val8, subchannel; |
Jes Sorensen | c3f9506 | 2016-02-29 17:04:40 -0500 | [diff] [blame] | 2285 | u16 rf_mode_bw; |
| 2286 | bool ht = true; |
| 2287 | int sec_ch_above, channel; |
| 2288 | int i; |
| 2289 | |
| 2290 | rf_mode_bw = rtl8xxxu_read16(priv, REG_WMAC_TRXPTCL_CTL); |
| 2291 | rf_mode_bw &= ~WMAC_TRXPTCL_CTL_BW_MASK; |
| 2292 | rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); |
| 2293 | channel = hw->conf.chandef.chan->hw_value; |
| 2294 | |
| 2295 | /* Hack */ |
| 2296 | subchannel = 0; |
| 2297 | |
| 2298 | switch (hw->conf.chandef.width) { |
| 2299 | case NL80211_CHAN_WIDTH_20_NOHT: |
| 2300 | ht = false; |
| 2301 | case NL80211_CHAN_WIDTH_20: |
| 2302 | rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_20; |
| 2303 | subchannel = 0; |
| 2304 | |
| 2305 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 2306 | val32 &= ~FPGA_RF_MODE; |
| 2307 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 2308 | |
| 2309 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); |
| 2310 | val32 &= ~FPGA_RF_MODE; |
| 2311 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); |
| 2312 | |
| 2313 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT); |
| 2314 | val32 &= ~(BIT(30) | BIT(31)); |
| 2315 | rtl8xxxu_write32(priv, REG_OFDM0_TX_PSDO_NOISE_WEIGHT, val32); |
| 2316 | |
| 2317 | break; |
| 2318 | case NL80211_CHAN_WIDTH_40: |
| 2319 | rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_40; |
| 2320 | |
| 2321 | if (hw->conf.chandef.center_freq1 > |
| 2322 | hw->conf.chandef.chan->center_freq) { |
| 2323 | sec_ch_above = 1; |
| 2324 | channel += 2; |
| 2325 | } else { |
| 2326 | sec_ch_above = 0; |
| 2327 | channel -= 2; |
| 2328 | } |
| 2329 | |
| 2330 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 2331 | val32 |= FPGA_RF_MODE; |
| 2332 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 2333 | |
| 2334 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE); |
| 2335 | val32 |= FPGA_RF_MODE; |
| 2336 | rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32); |
| 2337 | |
| 2338 | /* |
| 2339 | * Set Control channel to upper or lower. These settings |
| 2340 | * are required only for 40MHz |
| 2341 | */ |
| 2342 | val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM); |
| 2343 | val32 &= ~CCK0_SIDEBAND; |
| 2344 | if (!sec_ch_above) |
| 2345 | val32 |= CCK0_SIDEBAND; |
| 2346 | rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32); |
| 2347 | |
| 2348 | val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); |
| 2349 | val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */ |
| 2350 | if (sec_ch_above) |
| 2351 | val32 |= OFDM_LSTF_PRIME_CH_LOW; |
| 2352 | else |
| 2353 | val32 |= OFDM_LSTF_PRIME_CH_HIGH; |
| 2354 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); |
| 2355 | |
| 2356 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE); |
| 2357 | val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL); |
| 2358 | if (sec_ch_above) |
| 2359 | val32 |= FPGA0_PS_UPPER_CHANNEL; |
| 2360 | else |
| 2361 | val32 |= FPGA0_PS_LOWER_CHANNEL; |
| 2362 | rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32); |
| 2363 | break; |
| 2364 | case NL80211_CHAN_WIDTH_80: |
| 2365 | rf_mode_bw |= WMAC_TRXPTCL_CTL_BW_80; |
| 2366 | break; |
| 2367 | default: |
| 2368 | break; |
| 2369 | } |
| 2370 | |
| 2371 | for (i = RF_A; i < priv->rf_paths; i++) { |
| 2372 | val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); |
| 2373 | val32 &= ~MODE_AG_CHANNEL_MASK; |
| 2374 | val32 |= channel; |
| 2375 | rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); |
| 2376 | } |
| 2377 | |
| 2378 | rtl8xxxu_write16(priv, REG_WMAC_TRXPTCL_CTL, rf_mode_bw); |
| 2379 | rtl8xxxu_write8(priv, REG_DATA_SUBCHANNEL, subchannel); |
| 2380 | |
| 2381 | if (ht) |
| 2382 | val8 = 0x0e; |
| 2383 | else |
| 2384 | val8 = 0x0a; |
| 2385 | |
| 2386 | rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8); |
| 2387 | rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8); |
| 2388 | |
| 2389 | rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808); |
| 2390 | rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a); |
| 2391 | |
| 2392 | for (i = RF_A; i < priv->rf_paths; i++) { |
| 2393 | val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG); |
| 2394 | val32 &= ~MODE_AG_BW_MASK; |
| 2395 | switch(hw->conf.chandef.width) { |
| 2396 | case NL80211_CHAN_WIDTH_80: |
| 2397 | val32 |= MODE_AG_BW_80MHZ_8723B; |
| 2398 | break; |
| 2399 | case NL80211_CHAN_WIDTH_40: |
| 2400 | val32 |= MODE_AG_BW_40MHZ_8723B; |
| 2401 | break; |
| 2402 | default: |
| 2403 | val32 |= MODE_AG_BW_20MHZ_8723B; |
| 2404 | break; |
| 2405 | } |
| 2406 | rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32); |
| 2407 | } |
| 2408 | } |
| 2409 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2410 | static void |
| 2411 | rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) |
| 2412 | { |
| 2413 | u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS]; |
| 2414 | u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS]; |
| 2415 | u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b; |
| 2416 | u8 val8; |
| 2417 | int group, i; |
| 2418 | |
| 2419 | group = rtl8723a_channel_to_group(channel); |
| 2420 | |
| 2421 | cck[0] = priv->cck_tx_power_index_A[group]; |
| 2422 | cck[1] = priv->cck_tx_power_index_B[group]; |
| 2423 | |
| 2424 | ofdm[0] = priv->ht40_1s_tx_power_index_A[group]; |
| 2425 | ofdm[1] = priv->ht40_1s_tx_power_index_B[group]; |
| 2426 | |
| 2427 | ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a; |
| 2428 | ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b; |
| 2429 | |
| 2430 | mcsbase[0] = ofdm[0]; |
| 2431 | mcsbase[1] = ofdm[1]; |
| 2432 | if (!ht40) { |
| 2433 | mcsbase[0] += priv->ht20_tx_power_index_diff[group].a; |
| 2434 | mcsbase[1] += priv->ht20_tx_power_index_diff[group].b; |
| 2435 | } |
| 2436 | |
| 2437 | if (priv->tx_paths > 1) { |
| 2438 | if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a) |
| 2439 | ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a; |
| 2440 | if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b) |
| 2441 | ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b; |
| 2442 | } |
| 2443 | |
| 2444 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) |
| 2445 | dev_info(&priv->udev->dev, |
| 2446 | "%s: Setting TX power CCK A: %02x, " |
| 2447 | "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n", |
| 2448 | __func__, cck[0], cck[1], ofdm[0], ofdm[1]); |
| 2449 | |
| 2450 | for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) { |
| 2451 | if (cck[i] > RF6052_MAX_TX_PWR) |
| 2452 | cck[i] = RF6052_MAX_TX_PWR; |
| 2453 | if (ofdm[i] > RF6052_MAX_TX_PWR) |
| 2454 | ofdm[i] = RF6052_MAX_TX_PWR; |
| 2455 | } |
| 2456 | |
| 2457 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); |
| 2458 | val32 &= 0xffff00ff; |
| 2459 | val32 |= (cck[0] << 8); |
| 2460 | rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); |
| 2461 | |
| 2462 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); |
| 2463 | val32 &= 0xff; |
| 2464 | val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24)); |
| 2465 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); |
| 2466 | |
| 2467 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); |
| 2468 | val32 &= 0xffffff00; |
| 2469 | val32 |= cck[1]; |
| 2470 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); |
| 2471 | |
| 2472 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); |
| 2473 | val32 &= 0xff; |
| 2474 | val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24)); |
| 2475 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); |
| 2476 | |
| 2477 | ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 | |
| 2478 | ofdmbase[0] << 16 | ofdmbase[0] << 24; |
| 2479 | ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 | |
| 2480 | ofdmbase[1] << 16 | ofdmbase[1] << 24; |
| 2481 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a); |
| 2482 | rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b); |
| 2483 | |
| 2484 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a); |
| 2485 | rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b); |
| 2486 | |
| 2487 | mcs_a = mcsbase[0] | mcsbase[0] << 8 | |
| 2488 | mcsbase[0] << 16 | mcsbase[0] << 24; |
| 2489 | mcs_b = mcsbase[1] | mcsbase[1] << 8 | |
| 2490 | mcsbase[1] << 16 | mcsbase[1] << 24; |
| 2491 | |
| 2492 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a); |
| 2493 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b); |
| 2494 | |
| 2495 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a); |
| 2496 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b); |
| 2497 | |
| 2498 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a); |
| 2499 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b); |
| 2500 | |
| 2501 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a); |
| 2502 | for (i = 0; i < 3; i++) { |
| 2503 | if (i != 2) |
| 2504 | val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0; |
| 2505 | else |
| 2506 | val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0; |
| 2507 | rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8); |
| 2508 | } |
| 2509 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b); |
| 2510 | for (i = 0; i < 3; i++) { |
| 2511 | if (i != 2) |
| 2512 | val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0; |
| 2513 | else |
| 2514 | val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0; |
| 2515 | rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8); |
| 2516 | } |
| 2517 | } |
| 2518 | |
Jes Sorensen | e796dab | 2016-02-29 17:05:19 -0500 | [diff] [blame] | 2519 | static void |
| 2520 | rtl8723b_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) |
| 2521 | { |
Jes Sorensen | 1d3cc44 | 2016-02-29 17:05:24 -0500 | [diff] [blame] | 2522 | u32 val32, ofdm, mcs; |
| 2523 | u8 cck, ofdmbase, mcsbase; |
Jes Sorensen | 54bed43 | 2016-02-29 17:05:23 -0500 | [diff] [blame] | 2524 | int group, tx_idx; |
Jes Sorensen | e796dab | 2016-02-29 17:05:19 -0500 | [diff] [blame] | 2525 | |
Jes Sorensen | 54bed43 | 2016-02-29 17:05:23 -0500 | [diff] [blame] | 2526 | tx_idx = 0; |
Jes Sorensen | e796dab | 2016-02-29 17:05:19 -0500 | [diff] [blame] | 2527 | group = rtl8723b_channel_to_group(channel); |
Jes Sorensen | 54bed43 | 2016-02-29 17:05:23 -0500 | [diff] [blame] | 2528 | |
| 2529 | cck = priv->cck_tx_power_index_B[group]; |
| 2530 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); |
| 2531 | val32 &= 0xffff00ff; |
| 2532 | val32 |= (cck << 8); |
| 2533 | rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); |
| 2534 | |
| 2535 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); |
| 2536 | val32 &= 0xff; |
| 2537 | val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); |
| 2538 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); |
| 2539 | |
| 2540 | ofdmbase = priv->ht40_1s_tx_power_index_B[group]; |
| 2541 | ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; |
| 2542 | ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; |
| 2543 | |
| 2544 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); |
| 2545 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); |
Jes Sorensen | 1d3cc44 | 2016-02-29 17:05:24 -0500 | [diff] [blame] | 2546 | |
| 2547 | mcsbase = priv->ht40_1s_tx_power_index_B[group]; |
| 2548 | if (ht40) |
| 2549 | mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; |
| 2550 | else |
| 2551 | mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; |
| 2552 | mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; |
| 2553 | |
| 2554 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); |
| 2555 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); |
Jes Sorensen | e796dab | 2016-02-29 17:05:19 -0500 | [diff] [blame] | 2556 | } |
| 2557 | |
Jes Sorensen | 57e42a2 | 2016-04-14 14:58:49 -0400 | [diff] [blame] | 2558 | static void |
| 2559 | rtl8192e_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40) |
| 2560 | { |
| 2561 | u32 val32, ofdm, mcs; |
| 2562 | u8 cck, ofdmbase, mcsbase; |
| 2563 | int group, tx_idx; |
| 2564 | |
| 2565 | tx_idx = 0; |
| 2566 | group = rtl8723b_channel_to_group(channel); |
| 2567 | |
| 2568 | cck = priv->cck_tx_power_index_A[group]; |
| 2569 | |
| 2570 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32); |
| 2571 | val32 &= 0xffff00ff; |
| 2572 | val32 |= (cck << 8); |
| 2573 | rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32); |
| 2574 | |
| 2575 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); |
| 2576 | val32 &= 0xff; |
| 2577 | val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); |
| 2578 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); |
| 2579 | |
| 2580 | ofdmbase = priv->ht40_1s_tx_power_index_A[group]; |
| 2581 | ofdmbase += priv->ofdm_tx_power_diff[tx_idx].a; |
| 2582 | ofdm = ofdmbase | ofdmbase << 8 | ofdmbase << 16 | ofdmbase << 24; |
| 2583 | |
| 2584 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm); |
| 2585 | rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm); |
| 2586 | |
| 2587 | mcsbase = priv->ht40_1s_tx_power_index_A[group]; |
| 2588 | if (ht40) |
| 2589 | mcsbase += priv->ht40_tx_power_diff[tx_idx++].a; |
| 2590 | else |
| 2591 | mcsbase += priv->ht20_tx_power_diff[tx_idx++].a; |
| 2592 | mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; |
| 2593 | |
| 2594 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs); |
| 2595 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs); |
| 2596 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs); |
| 2597 | rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs); |
| 2598 | |
| 2599 | if (priv->tx_paths > 1) { |
| 2600 | cck = priv->cck_tx_power_index_B[group]; |
| 2601 | |
| 2602 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32); |
| 2603 | val32 &= 0xff; |
| 2604 | val32 |= ((cck << 8) | (cck << 16) | (cck << 24)); |
| 2605 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32); |
| 2606 | |
| 2607 | val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11); |
| 2608 | val32 &= 0xffffff00; |
| 2609 | val32 |= cck; |
| 2610 | rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32); |
| 2611 | |
| 2612 | ofdmbase = priv->ht40_1s_tx_power_index_B[group]; |
| 2613 | ofdmbase += priv->ofdm_tx_power_diff[tx_idx].b; |
| 2614 | ofdm = ofdmbase | ofdmbase << 8 | |
| 2615 | ofdmbase << 16 | ofdmbase << 24; |
| 2616 | |
| 2617 | rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm); |
| 2618 | rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm); |
| 2619 | |
| 2620 | mcsbase = priv->ht40_1s_tx_power_index_B[group]; |
| 2621 | if (ht40) |
| 2622 | mcsbase += priv->ht40_tx_power_diff[tx_idx++].b; |
| 2623 | else |
| 2624 | mcsbase += priv->ht20_tx_power_diff[tx_idx++].b; |
| 2625 | mcs = mcsbase | mcsbase << 8 | mcsbase << 16 | mcsbase << 24; |
| 2626 | |
| 2627 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs); |
| 2628 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs); |
| 2629 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs); |
| 2630 | rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs); |
| 2631 | } |
| 2632 | } |
| 2633 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2634 | static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv, |
| 2635 | enum nl80211_iftype linktype) |
| 2636 | { |
Jes Sorensen | a26703f | 2016-02-03 13:39:56 -0500 | [diff] [blame] | 2637 | u8 val8; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2638 | |
Jes Sorensen | a26703f | 2016-02-03 13:39:56 -0500 | [diff] [blame] | 2639 | val8 = rtl8xxxu_read8(priv, REG_MSR); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2640 | val8 &= ~MSR_LINKTYPE_MASK; |
| 2641 | |
| 2642 | switch (linktype) { |
| 2643 | case NL80211_IFTYPE_UNSPECIFIED: |
| 2644 | val8 |= MSR_LINKTYPE_NONE; |
| 2645 | break; |
| 2646 | case NL80211_IFTYPE_ADHOC: |
| 2647 | val8 |= MSR_LINKTYPE_ADHOC; |
| 2648 | break; |
| 2649 | case NL80211_IFTYPE_STATION: |
| 2650 | val8 |= MSR_LINKTYPE_STATION; |
| 2651 | break; |
| 2652 | case NL80211_IFTYPE_AP: |
| 2653 | val8 |= MSR_LINKTYPE_AP; |
| 2654 | break; |
| 2655 | default: |
| 2656 | goto out; |
| 2657 | } |
| 2658 | |
| 2659 | rtl8xxxu_write8(priv, REG_MSR, val8); |
| 2660 | out: |
| 2661 | return; |
| 2662 | } |
| 2663 | |
| 2664 | static void |
| 2665 | rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry) |
| 2666 | { |
| 2667 | u16 val16; |
| 2668 | |
| 2669 | val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) & |
| 2670 | RETRY_LIMIT_SHORT_MASK) | |
| 2671 | ((long_retry << RETRY_LIMIT_LONG_SHIFT) & |
| 2672 | RETRY_LIMIT_LONG_MASK); |
| 2673 | |
| 2674 | rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); |
| 2675 | } |
| 2676 | |
| 2677 | static void |
| 2678 | rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm) |
| 2679 | { |
| 2680 | u16 val16; |
| 2681 | |
| 2682 | val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) | |
| 2683 | ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK); |
| 2684 | |
| 2685 | rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16); |
| 2686 | } |
| 2687 | |
| 2688 | static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv) |
| 2689 | { |
| 2690 | struct device *dev = &priv->udev->dev; |
| 2691 | char *cut; |
| 2692 | |
| 2693 | switch (priv->chip_cut) { |
| 2694 | case 0: |
| 2695 | cut = "A"; |
| 2696 | break; |
| 2697 | case 1: |
| 2698 | cut = "B"; |
| 2699 | break; |
Jes Sorensen | 0e5d435 | 2016-02-29 17:04:00 -0500 | [diff] [blame] | 2700 | case 2: |
| 2701 | cut = "C"; |
| 2702 | break; |
| 2703 | case 3: |
| 2704 | cut = "D"; |
| 2705 | break; |
| 2706 | case 4: |
| 2707 | cut = "E"; |
| 2708 | break; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2709 | default: |
| 2710 | cut = "unknown"; |
| 2711 | } |
| 2712 | |
| 2713 | dev_info(dev, |
| 2714 | "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n", |
Jes Sorensen | 0e5d435 | 2016-02-29 17:04:00 -0500 | [diff] [blame] | 2715 | priv->chip_name, cut, priv->chip_vendor, priv->tx_paths, |
| 2716 | priv->rx_paths, priv->ep_tx_count, priv->has_wifi, |
| 2717 | priv->has_bluetooth, priv->has_gps, priv->hi_pa); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2718 | |
| 2719 | dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr); |
| 2720 | } |
| 2721 | |
| 2722 | static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv) |
| 2723 | { |
| 2724 | struct device *dev = &priv->udev->dev; |
| 2725 | u32 val32, bonding; |
| 2726 | u16 val16; |
| 2727 | |
| 2728 | val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); |
| 2729 | priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >> |
| 2730 | SYS_CFG_CHIP_VERSION_SHIFT; |
| 2731 | if (val32 & SYS_CFG_TRP_VAUX_EN) { |
| 2732 | dev_info(dev, "Unsupported test chip\n"); |
| 2733 | return -ENOTSUPP; |
| 2734 | } |
| 2735 | |
| 2736 | if (val32 & SYS_CFG_BT_FUNC) { |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 2737 | if (priv->chip_cut >= 3) { |
| 2738 | sprintf(priv->chip_name, "8723BU"); |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 2739 | priv->rtl_chip = RTL8723B; |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 2740 | } else { |
| 2741 | sprintf(priv->chip_name, "8723AU"); |
Jes Sorensen | 0e28b97 | 2016-02-29 17:04:13 -0500 | [diff] [blame] | 2742 | priv->usb_interrupts = 1; |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 2743 | priv->rtl_chip = RTL8723A; |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 2744 | } |
| 2745 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2746 | priv->rf_paths = 1; |
| 2747 | priv->rx_paths = 1; |
| 2748 | priv->tx_paths = 1; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2749 | |
| 2750 | val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL); |
| 2751 | if (val32 & MULTI_WIFI_FUNC_EN) |
| 2752 | priv->has_wifi = 1; |
| 2753 | if (val32 & MULTI_BT_FUNC_EN) |
| 2754 | priv->has_bluetooth = 1; |
| 2755 | if (val32 & MULTI_GPS_FUNC_EN) |
| 2756 | priv->has_gps = 1; |
Jakub Sitnicki | 3845199 | 2016-02-03 13:39:49 -0500 | [diff] [blame] | 2757 | priv->is_multi_func = 1; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2758 | } else if (val32 & SYS_CFG_TYPE_ID) { |
| 2759 | bonding = rtl8xxxu_read32(priv, REG_HPON_FSM); |
| 2760 | bonding &= HPON_FSM_BONDING_MASK; |
Jes Sorensen | 55c0b6a | 2016-04-14 14:58:50 -0400 | [diff] [blame] | 2761 | if (priv->fops->tx_desc_size == |
| 2762 | sizeof(struct rtl8xxxu_txdesc40)) { |
Jes Sorensen | 0e5d435 | 2016-02-29 17:04:00 -0500 | [diff] [blame] | 2763 | if (bonding == HPON_FSM_BONDING_1T2R) { |
| 2764 | sprintf(priv->chip_name, "8191EU"); |
| 2765 | priv->rf_paths = 2; |
| 2766 | priv->rx_paths = 2; |
| 2767 | priv->tx_paths = 1; |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 2768 | priv->rtl_chip = RTL8191E; |
Jes Sorensen | 0e5d435 | 2016-02-29 17:04:00 -0500 | [diff] [blame] | 2769 | } else { |
| 2770 | sprintf(priv->chip_name, "8192EU"); |
| 2771 | priv->rf_paths = 2; |
| 2772 | priv->rx_paths = 2; |
| 2773 | priv->tx_paths = 2; |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 2774 | priv->rtl_chip = RTL8192E; |
Jes Sorensen | 0e5d435 | 2016-02-29 17:04:00 -0500 | [diff] [blame] | 2775 | } |
| 2776 | } else if (bonding == HPON_FSM_BONDING_1T2R) { |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2777 | sprintf(priv->chip_name, "8191CU"); |
| 2778 | priv->rf_paths = 2; |
| 2779 | priv->rx_paths = 2; |
| 2780 | priv->tx_paths = 1; |
Jes Sorensen | 0e28b97 | 2016-02-29 17:04:13 -0500 | [diff] [blame] | 2781 | priv->usb_interrupts = 1; |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 2782 | priv->rtl_chip = RTL8191C; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2783 | } else { |
| 2784 | sprintf(priv->chip_name, "8192CU"); |
| 2785 | priv->rf_paths = 2; |
| 2786 | priv->rx_paths = 2; |
| 2787 | priv->tx_paths = 2; |
Jes Sorensen | 0e28b97 | 2016-02-29 17:04:13 -0500 | [diff] [blame] | 2788 | priv->usb_interrupts = 1; |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 2789 | priv->rtl_chip = RTL8192C; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2790 | } |
| 2791 | priv->has_wifi = 1; |
| 2792 | } else { |
| 2793 | sprintf(priv->chip_name, "8188CU"); |
| 2794 | priv->rf_paths = 1; |
| 2795 | priv->rx_paths = 1; |
| 2796 | priv->tx_paths = 1; |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 2797 | priv->rtl_chip = RTL8188C; |
Jes Sorensen | 0e28b97 | 2016-02-29 17:04:13 -0500 | [diff] [blame] | 2798 | priv->usb_interrupts = 1; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2799 | priv->has_wifi = 1; |
| 2800 | } |
| 2801 | |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 2802 | switch (priv->rtl_chip) { |
| 2803 | case RTL8188E: |
| 2804 | case RTL8192E: |
| 2805 | case RTL8723B: |
Jes Sorensen | 0e5d435 | 2016-02-29 17:04:00 -0500 | [diff] [blame] | 2806 | switch (val32 & SYS_CFG_VENDOR_EXT_MASK) { |
| 2807 | case SYS_CFG_VENDOR_ID_TSMC: |
| 2808 | sprintf(priv->chip_vendor, "TSMC"); |
| 2809 | break; |
| 2810 | case SYS_CFG_VENDOR_ID_SMIC: |
| 2811 | sprintf(priv->chip_vendor, "SMIC"); |
| 2812 | priv->vendor_smic = 1; |
| 2813 | break; |
| 2814 | case SYS_CFG_VENDOR_ID_UMC: |
| 2815 | sprintf(priv->chip_vendor, "UMC"); |
| 2816 | priv->vendor_umc = 1; |
| 2817 | break; |
| 2818 | default: |
| 2819 | sprintf(priv->chip_vendor, "unknown"); |
| 2820 | } |
| 2821 | break; |
| 2822 | default: |
| 2823 | if (val32 & SYS_CFG_VENDOR_ID) { |
| 2824 | sprintf(priv->chip_vendor, "UMC"); |
| 2825 | priv->vendor_umc = 1; |
| 2826 | } else { |
| 2827 | sprintf(priv->chip_vendor, "TSMC"); |
| 2828 | } |
| 2829 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2830 | |
| 2831 | val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS); |
| 2832 | priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28; |
| 2833 | |
| 2834 | val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX); |
| 2835 | if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) { |
| 2836 | priv->ep_tx_high_queue = 1; |
| 2837 | priv->ep_tx_count++; |
| 2838 | } |
| 2839 | |
| 2840 | if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) { |
| 2841 | priv->ep_tx_normal_queue = 1; |
| 2842 | priv->ep_tx_count++; |
| 2843 | } |
| 2844 | |
| 2845 | if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) { |
| 2846 | priv->ep_tx_low_queue = 1; |
| 2847 | priv->ep_tx_count++; |
| 2848 | } |
| 2849 | |
| 2850 | /* |
| 2851 | * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX |
| 2852 | */ |
| 2853 | if (!priv->ep_tx_count) { |
| 2854 | switch (priv->nr_out_eps) { |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 2855 | case 4: |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2856 | case 3: |
| 2857 | priv->ep_tx_low_queue = 1; |
| 2858 | priv->ep_tx_count++; |
| 2859 | case 2: |
| 2860 | priv->ep_tx_normal_queue = 1; |
| 2861 | priv->ep_tx_count++; |
| 2862 | case 1: |
| 2863 | priv->ep_tx_high_queue = 1; |
| 2864 | priv->ep_tx_count++; |
| 2865 | break; |
| 2866 | default: |
| 2867 | dev_info(dev, "Unsupported USB TX end-points\n"); |
| 2868 | return -ENOTSUPP; |
| 2869 | } |
| 2870 | } |
| 2871 | |
| 2872 | return 0; |
| 2873 | } |
| 2874 | |
| 2875 | static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv) |
| 2876 | { |
Jakub Sitnicki | d38f1c3 | 2016-02-29 17:04:25 -0500 | [diff] [blame] | 2877 | struct rtl8723au_efuse *efuse = &priv->efuse_wifi.efuse8723; |
| 2878 | |
| 2879 | if (efuse->rtl_id != cpu_to_le16(0x8129)) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2880 | return -EINVAL; |
| 2881 | |
Jakub Sitnicki | d38f1c3 | 2016-02-29 17:04:25 -0500 | [diff] [blame] | 2882 | ether_addr_copy(priv->mac_addr, efuse->mac_addr); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2883 | |
| 2884 | memcpy(priv->cck_tx_power_index_A, |
Jakub Sitnicki | d38f1c3 | 2016-02-29 17:04:25 -0500 | [diff] [blame] | 2885 | efuse->cck_tx_power_index_A, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 2886 | sizeof(efuse->cck_tx_power_index_A)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2887 | memcpy(priv->cck_tx_power_index_B, |
Jakub Sitnicki | d38f1c3 | 2016-02-29 17:04:25 -0500 | [diff] [blame] | 2888 | efuse->cck_tx_power_index_B, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 2889 | sizeof(efuse->cck_tx_power_index_B)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2890 | |
| 2891 | memcpy(priv->ht40_1s_tx_power_index_A, |
Jakub Sitnicki | d38f1c3 | 2016-02-29 17:04:25 -0500 | [diff] [blame] | 2892 | efuse->ht40_1s_tx_power_index_A, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 2893 | sizeof(efuse->ht40_1s_tx_power_index_A)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2894 | memcpy(priv->ht40_1s_tx_power_index_B, |
Jakub Sitnicki | d38f1c3 | 2016-02-29 17:04:25 -0500 | [diff] [blame] | 2895 | efuse->ht40_1s_tx_power_index_B, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 2896 | sizeof(efuse->ht40_1s_tx_power_index_B)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2897 | |
| 2898 | memcpy(priv->ht20_tx_power_index_diff, |
Jakub Sitnicki | d38f1c3 | 2016-02-29 17:04:25 -0500 | [diff] [blame] | 2899 | efuse->ht20_tx_power_index_diff, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 2900 | sizeof(efuse->ht20_tx_power_index_diff)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2901 | memcpy(priv->ofdm_tx_power_index_diff, |
Jakub Sitnicki | d38f1c3 | 2016-02-29 17:04:25 -0500 | [diff] [blame] | 2902 | efuse->ofdm_tx_power_index_diff, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 2903 | sizeof(efuse->ofdm_tx_power_index_diff)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2904 | |
| 2905 | memcpy(priv->ht40_max_power_offset, |
Jakub Sitnicki | d38f1c3 | 2016-02-29 17:04:25 -0500 | [diff] [blame] | 2906 | efuse->ht40_max_power_offset, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 2907 | sizeof(efuse->ht40_max_power_offset)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2908 | memcpy(priv->ht20_max_power_offset, |
Jakub Sitnicki | d38f1c3 | 2016-02-29 17:04:25 -0500 | [diff] [blame] | 2909 | efuse->ht20_max_power_offset, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 2910 | sizeof(efuse->ht20_max_power_offset)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2911 | |
Jes Sorensen | 4ef22eb | 2016-02-29 17:04:55 -0500 | [diff] [blame] | 2912 | if (priv->efuse_wifi.efuse8723.version >= 0x01) { |
| 2913 | priv->has_xtalk = 1; |
| 2914 | priv->xtalk = priv->efuse_wifi.efuse8723.xtal_k & 0x3f; |
| 2915 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2916 | dev_info(&priv->udev->dev, "Vendor: %.7s\n", |
Jakub Sitnicki | d38f1c3 | 2016-02-29 17:04:25 -0500 | [diff] [blame] | 2917 | efuse->vendor_name); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2918 | dev_info(&priv->udev->dev, "Product: %.41s\n", |
Jakub Sitnicki | d38f1c3 | 2016-02-29 17:04:25 -0500 | [diff] [blame] | 2919 | efuse->device_name); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 2920 | return 0; |
| 2921 | } |
| 2922 | |
Jes Sorensen | 3c836d6 | 2016-02-29 17:04:11 -0500 | [diff] [blame] | 2923 | static int rtl8723bu_parse_efuse(struct rtl8xxxu_priv *priv) |
| 2924 | { |
Jes Sorensen | b8ba860 | 2016-02-29 17:04:28 -0500 | [diff] [blame] | 2925 | struct rtl8723bu_efuse *efuse = &priv->efuse_wifi.efuse8723bu; |
Jes Sorensen | 3be2699 | 2016-02-29 17:05:22 -0500 | [diff] [blame] | 2926 | int i; |
Jes Sorensen | b8ba860 | 2016-02-29 17:04:28 -0500 | [diff] [blame] | 2927 | |
| 2928 | if (efuse->rtl_id != cpu_to_le16(0x8129)) |
Jes Sorensen | 3c836d6 | 2016-02-29 17:04:11 -0500 | [diff] [blame] | 2929 | return -EINVAL; |
| 2930 | |
Jes Sorensen | b8ba860 | 2016-02-29 17:04:28 -0500 | [diff] [blame] | 2931 | ether_addr_copy(priv->mac_addr, efuse->mac_addr); |
Jes Sorensen | 3c836d6 | 2016-02-29 17:04:11 -0500 | [diff] [blame] | 2932 | |
Jes Sorensen | 3be2699 | 2016-02-29 17:05:22 -0500 | [diff] [blame] | 2933 | memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, |
| 2934 | sizeof(efuse->tx_power_index_A.cck_base)); |
| 2935 | memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, |
| 2936 | sizeof(efuse->tx_power_index_B.cck_base)); |
| 2937 | |
| 2938 | memcpy(priv->ht40_1s_tx_power_index_A, |
| 2939 | efuse->tx_power_index_A.ht40_base, |
| 2940 | sizeof(efuse->tx_power_index_A.ht40_base)); |
| 2941 | memcpy(priv->ht40_1s_tx_power_index_B, |
| 2942 | efuse->tx_power_index_B.ht40_base, |
| 2943 | sizeof(efuse->tx_power_index_B.ht40_base)); |
| 2944 | |
| 2945 | priv->ofdm_tx_power_diff[0].a = |
| 2946 | efuse->tx_power_index_A.ht20_ofdm_1s_diff.a; |
| 2947 | priv->ofdm_tx_power_diff[0].b = |
| 2948 | efuse->tx_power_index_B.ht20_ofdm_1s_diff.a; |
| 2949 | |
| 2950 | priv->ht20_tx_power_diff[0].a = |
| 2951 | efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; |
| 2952 | priv->ht20_tx_power_diff[0].b = |
| 2953 | efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; |
| 2954 | |
| 2955 | priv->ht40_tx_power_diff[0].a = 0; |
| 2956 | priv->ht40_tx_power_diff[0].b = 0; |
| 2957 | |
| 2958 | for (i = 1; i < RTL8723B_TX_COUNT; i++) { |
| 2959 | priv->ofdm_tx_power_diff[i].a = |
| 2960 | efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; |
| 2961 | priv->ofdm_tx_power_diff[i].b = |
| 2962 | efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; |
| 2963 | |
| 2964 | priv->ht20_tx_power_diff[i].a = |
| 2965 | efuse->tx_power_index_A.pwr_diff[i - 1].ht20; |
| 2966 | priv->ht20_tx_power_diff[i].b = |
| 2967 | efuse->tx_power_index_B.pwr_diff[i - 1].ht20; |
| 2968 | |
| 2969 | priv->ht40_tx_power_diff[i].a = |
| 2970 | efuse->tx_power_index_A.pwr_diff[i - 1].ht40; |
| 2971 | priv->ht40_tx_power_diff[i].b = |
| 2972 | efuse->tx_power_index_B.pwr_diff[i - 1].ht40; |
| 2973 | } |
| 2974 | |
Jes Sorensen | 4ef22eb | 2016-02-29 17:04:55 -0500 | [diff] [blame] | 2975 | priv->has_xtalk = 1; |
| 2976 | priv->xtalk = priv->efuse_wifi.efuse8723bu.xtal_k & 0x3f; |
| 2977 | |
Jes Sorensen | b8ba860 | 2016-02-29 17:04:28 -0500 | [diff] [blame] | 2978 | dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); |
| 2979 | dev_info(&priv->udev->dev, "Product: %.41s\n", efuse->device_name); |
Jes Sorensen | 3c836d6 | 2016-02-29 17:04:11 -0500 | [diff] [blame] | 2980 | |
| 2981 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) { |
| 2982 | int i; |
| 2983 | unsigned char *raw = priv->efuse_wifi.raw; |
| 2984 | |
| 2985 | dev_info(&priv->udev->dev, |
| 2986 | "%s: dumping efuse (0x%02zx bytes):\n", |
| 2987 | __func__, sizeof(struct rtl8723bu_efuse)); |
| 2988 | for (i = 0; i < sizeof(struct rtl8723bu_efuse); i += 8) { |
| 2989 | dev_info(&priv->udev->dev, "%02x: " |
| 2990 | "%02x %02x %02x %02x %02x %02x %02x %02x\n", i, |
| 2991 | raw[i], raw[i + 1], raw[i + 2], |
| 2992 | raw[i + 3], raw[i + 4], raw[i + 5], |
| 2993 | raw[i + 6], raw[i + 7]); |
| 2994 | } |
| 2995 | } |
| 2996 | |
| 2997 | return 0; |
| 2998 | } |
| 2999 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 3000 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
| 3001 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3002 | static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv) |
| 3003 | { |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3004 | struct rtl8192cu_efuse *efuse = &priv->efuse_wifi.efuse8192; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3005 | int i; |
| 3006 | |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3007 | if (efuse->rtl_id != cpu_to_le16(0x8129)) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3008 | return -EINVAL; |
| 3009 | |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3010 | ether_addr_copy(priv->mac_addr, efuse->mac_addr); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3011 | |
| 3012 | memcpy(priv->cck_tx_power_index_A, |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3013 | efuse->cck_tx_power_index_A, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 3014 | sizeof(efuse->cck_tx_power_index_A)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3015 | memcpy(priv->cck_tx_power_index_B, |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3016 | efuse->cck_tx_power_index_B, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 3017 | sizeof(efuse->cck_tx_power_index_B)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3018 | |
| 3019 | memcpy(priv->ht40_1s_tx_power_index_A, |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3020 | efuse->ht40_1s_tx_power_index_A, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 3021 | sizeof(efuse->ht40_1s_tx_power_index_A)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3022 | memcpy(priv->ht40_1s_tx_power_index_B, |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3023 | efuse->ht40_1s_tx_power_index_B, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 3024 | sizeof(efuse->ht40_1s_tx_power_index_B)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3025 | memcpy(priv->ht40_2s_tx_power_index_diff, |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3026 | efuse->ht40_2s_tx_power_index_diff, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 3027 | sizeof(efuse->ht40_2s_tx_power_index_diff)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3028 | |
| 3029 | memcpy(priv->ht20_tx_power_index_diff, |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3030 | efuse->ht20_tx_power_index_diff, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 3031 | sizeof(efuse->ht20_tx_power_index_diff)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3032 | memcpy(priv->ofdm_tx_power_index_diff, |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3033 | efuse->ofdm_tx_power_index_diff, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 3034 | sizeof(efuse->ofdm_tx_power_index_diff)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3035 | |
| 3036 | memcpy(priv->ht40_max_power_offset, |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3037 | efuse->ht40_max_power_offset, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 3038 | sizeof(efuse->ht40_max_power_offset)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3039 | memcpy(priv->ht20_max_power_offset, |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3040 | efuse->ht20_max_power_offset, |
Jes Sorensen | 3e84f93 | 2016-02-29 17:05:20 -0500 | [diff] [blame] | 3041 | sizeof(efuse->ht20_max_power_offset)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3042 | |
| 3043 | dev_info(&priv->udev->dev, "Vendor: %.7s\n", |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3044 | efuse->vendor_name); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3045 | dev_info(&priv->udev->dev, "Product: %.20s\n", |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3046 | efuse->device_name); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3047 | |
Jakub Sitnicki | 4959444 | 2016-02-29 17:04:26 -0500 | [diff] [blame] | 3048 | if (efuse->rf_regulatory & 0x20) { |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3049 | sprintf(priv->chip_name, "8188RU"); |
| 3050 | priv->hi_pa = 1; |
| 3051 | } |
| 3052 | |
| 3053 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) { |
| 3054 | unsigned char *raw = priv->efuse_wifi.raw; |
| 3055 | |
| 3056 | dev_info(&priv->udev->dev, |
| 3057 | "%s: dumping efuse (0x%02zx bytes):\n", |
| 3058 | __func__, sizeof(struct rtl8192cu_efuse)); |
| 3059 | for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) { |
| 3060 | dev_info(&priv->udev->dev, "%02x: " |
| 3061 | "%02x %02x %02x %02x %02x %02x %02x %02x\n", i, |
| 3062 | raw[i], raw[i + 1], raw[i + 2], |
| 3063 | raw[i + 3], raw[i + 4], raw[i + 5], |
| 3064 | raw[i + 6], raw[i + 7]); |
| 3065 | } |
| 3066 | } |
| 3067 | return 0; |
| 3068 | } |
| 3069 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 3070 | #endif |
| 3071 | |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 3072 | static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv) |
| 3073 | { |
Jes Sorensen | b7dda34d | 2016-02-29 17:04:27 -0500 | [diff] [blame] | 3074 | struct rtl8192eu_efuse *efuse = &priv->efuse_wifi.efuse8192eu; |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 3075 | int i; |
| 3076 | |
Jes Sorensen | b7dda34d | 2016-02-29 17:04:27 -0500 | [diff] [blame] | 3077 | if (efuse->rtl_id != cpu_to_le16(0x8129)) |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 3078 | return -EINVAL; |
| 3079 | |
Jes Sorensen | b7dda34d | 2016-02-29 17:04:27 -0500 | [diff] [blame] | 3080 | ether_addr_copy(priv->mac_addr, efuse->mac_addr); |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 3081 | |
Jes Sorensen | 9e24772 | 2016-04-07 14:19:23 -0400 | [diff] [blame] | 3082 | memcpy(priv->cck_tx_power_index_A, efuse->tx_power_index_A.cck_base, |
| 3083 | sizeof(efuse->tx_power_index_A.cck_base)); |
| 3084 | memcpy(priv->cck_tx_power_index_B, efuse->tx_power_index_B.cck_base, |
| 3085 | sizeof(efuse->tx_power_index_B.cck_base)); |
| 3086 | |
| 3087 | memcpy(priv->ht40_1s_tx_power_index_A, |
| 3088 | efuse->tx_power_index_A.ht40_base, |
| 3089 | sizeof(efuse->tx_power_index_A.ht40_base)); |
| 3090 | memcpy(priv->ht40_1s_tx_power_index_B, |
| 3091 | efuse->tx_power_index_B.ht40_base, |
| 3092 | sizeof(efuse->tx_power_index_B.ht40_base)); |
| 3093 | |
| 3094 | priv->ht20_tx_power_diff[0].a = |
| 3095 | efuse->tx_power_index_A.ht20_ofdm_1s_diff.b; |
| 3096 | priv->ht20_tx_power_diff[0].b = |
| 3097 | efuse->tx_power_index_B.ht20_ofdm_1s_diff.b; |
| 3098 | |
| 3099 | priv->ht40_tx_power_diff[0].a = 0; |
| 3100 | priv->ht40_tx_power_diff[0].b = 0; |
| 3101 | |
| 3102 | for (i = 1; i < RTL8723B_TX_COUNT; i++) { |
| 3103 | priv->ofdm_tx_power_diff[i].a = |
| 3104 | efuse->tx_power_index_A.pwr_diff[i - 1].ofdm; |
| 3105 | priv->ofdm_tx_power_diff[i].b = |
| 3106 | efuse->tx_power_index_B.pwr_diff[i - 1].ofdm; |
| 3107 | |
| 3108 | priv->ht20_tx_power_diff[i].a = |
| 3109 | efuse->tx_power_index_A.pwr_diff[i - 1].ht20; |
| 3110 | priv->ht20_tx_power_diff[i].b = |
| 3111 | efuse->tx_power_index_B.pwr_diff[i - 1].ht20; |
| 3112 | |
| 3113 | priv->ht40_tx_power_diff[i].a = |
| 3114 | efuse->tx_power_index_A.pwr_diff[i - 1].ht40; |
| 3115 | priv->ht40_tx_power_diff[i].b = |
| 3116 | efuse->tx_power_index_B.pwr_diff[i - 1].ht40; |
| 3117 | } |
| 3118 | |
Jes Sorensen | 4ef22eb | 2016-02-29 17:04:55 -0500 | [diff] [blame] | 3119 | priv->has_xtalk = 1; |
| 3120 | priv->xtalk = priv->efuse_wifi.efuse8192eu.xtal_k & 0x3f; |
| 3121 | |
Jes Sorensen | b7dda34d | 2016-02-29 17:04:27 -0500 | [diff] [blame] | 3122 | dev_info(&priv->udev->dev, "Vendor: %.7s\n", efuse->vendor_name); |
| 3123 | dev_info(&priv->udev->dev, "Product: %.11s\n", efuse->device_name); |
| 3124 | dev_info(&priv->udev->dev, "Serial: %.11s\n", efuse->serial); |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 3125 | |
| 3126 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) { |
| 3127 | unsigned char *raw = priv->efuse_wifi.raw; |
| 3128 | |
| 3129 | dev_info(&priv->udev->dev, |
| 3130 | "%s: dumping efuse (0x%02zx bytes):\n", |
| 3131 | __func__, sizeof(struct rtl8192eu_efuse)); |
| 3132 | for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) { |
| 3133 | dev_info(&priv->udev->dev, "%02x: " |
| 3134 | "%02x %02x %02x %02x %02x %02x %02x %02x\n", i, |
| 3135 | raw[i], raw[i + 1], raw[i + 2], |
| 3136 | raw[i + 3], raw[i + 4], raw[i + 5], |
| 3137 | raw[i + 6], raw[i + 7]); |
| 3138 | } |
| 3139 | } |
Jes Sorensen | 0e5d435 | 2016-02-29 17:04:00 -0500 | [diff] [blame] | 3140 | return 0; |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 3141 | } |
| 3142 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3143 | static int |
| 3144 | rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data) |
| 3145 | { |
| 3146 | int i; |
| 3147 | u8 val8; |
| 3148 | u32 val32; |
| 3149 | |
| 3150 | /* Write Address */ |
| 3151 | rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff); |
| 3152 | val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2); |
| 3153 | val8 &= 0xfc; |
| 3154 | val8 |= (offset >> 8) & 0x03; |
| 3155 | rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8); |
| 3156 | |
| 3157 | val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3); |
| 3158 | rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f); |
| 3159 | |
| 3160 | /* Poll for data read */ |
| 3161 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); |
| 3162 | for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) { |
| 3163 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); |
| 3164 | if (val32 & BIT(31)) |
| 3165 | break; |
| 3166 | } |
| 3167 | |
| 3168 | if (i == RTL8XXXU_MAX_REG_POLL) |
| 3169 | return -EIO; |
| 3170 | |
| 3171 | udelay(50); |
| 3172 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); |
| 3173 | |
| 3174 | *data = val32 & 0xff; |
| 3175 | return 0; |
| 3176 | } |
| 3177 | |
| 3178 | static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv) |
| 3179 | { |
| 3180 | struct device *dev = &priv->udev->dev; |
| 3181 | int i, ret = 0; |
| 3182 | u8 val8, word_mask, header, extheader; |
| 3183 | u16 val16, efuse_addr, offset; |
| 3184 | u32 val32; |
| 3185 | |
| 3186 | val16 = rtl8xxxu_read16(priv, REG_9346CR); |
| 3187 | if (val16 & EEPROM_ENABLE) |
| 3188 | priv->has_eeprom = 1; |
| 3189 | if (val16 & EEPROM_BOOT) |
| 3190 | priv->boot_eeprom = 1; |
| 3191 | |
Jakub Sitnicki | 3845199 | 2016-02-03 13:39:49 -0500 | [diff] [blame] | 3192 | if (priv->is_multi_func) { |
| 3193 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST); |
| 3194 | val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT; |
| 3195 | rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32); |
| 3196 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3197 | |
| 3198 | dev_dbg(dev, "Booting from %s\n", |
| 3199 | priv->boot_eeprom ? "EEPROM" : "EFUSE"); |
| 3200 | |
| 3201 | rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE); |
| 3202 | |
| 3203 | /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */ |
| 3204 | val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); |
| 3205 | if (!(val16 & SYS_ISO_PWC_EV12V)) { |
| 3206 | val16 |= SYS_ISO_PWC_EV12V; |
| 3207 | rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); |
| 3208 | } |
| 3209 | /* Reset: 0x0000[28], default valid */ |
| 3210 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 3211 | if (!(val16 & SYS_FUNC_ELDR)) { |
| 3212 | val16 |= SYS_FUNC_ELDR; |
| 3213 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 3214 | } |
| 3215 | |
| 3216 | /* |
| 3217 | * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid |
| 3218 | */ |
| 3219 | val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR); |
| 3220 | if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) { |
| 3221 | val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M); |
| 3222 | rtl8xxxu_write16(priv, REG_SYS_CLKR, val16); |
| 3223 | } |
| 3224 | |
| 3225 | /* Default value is 0xff */ |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 3226 | memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3227 | |
| 3228 | efuse_addr = 0; |
| 3229 | while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) { |
Jakub Sitnicki | f6c4770 | 2016-02-29 17:04:23 -0500 | [diff] [blame] | 3230 | u16 map_addr; |
| 3231 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3232 | ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header); |
| 3233 | if (ret || header == 0xff) |
| 3234 | goto exit; |
| 3235 | |
| 3236 | if ((header & 0x1f) == 0x0f) { /* extended header */ |
| 3237 | offset = (header & 0xe0) >> 5; |
| 3238 | |
| 3239 | ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, |
| 3240 | &extheader); |
| 3241 | if (ret) |
| 3242 | goto exit; |
| 3243 | /* All words disabled */ |
| 3244 | if ((extheader & 0x0f) == 0x0f) |
| 3245 | continue; |
| 3246 | |
| 3247 | offset |= ((extheader & 0xf0) >> 1); |
| 3248 | word_mask = extheader & 0x0f; |
| 3249 | } else { |
| 3250 | offset = (header >> 4) & 0x0f; |
| 3251 | word_mask = header & 0x0f; |
| 3252 | } |
| 3253 | |
Jakub Sitnicki | f6c4770 | 2016-02-29 17:04:23 -0500 | [diff] [blame] | 3254 | /* Get word enable value from PG header */ |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3255 | |
Jakub Sitnicki | f6c4770 | 2016-02-29 17:04:23 -0500 | [diff] [blame] | 3256 | /* We have 8 bits to indicate validity */ |
| 3257 | map_addr = offset * 8; |
| 3258 | if (map_addr >= EFUSE_MAP_LEN) { |
| 3259 | dev_warn(dev, "%s: Illegal map_addr (%04x), " |
| 3260 | "efuse corrupt!\n", |
| 3261 | __func__, map_addr); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3262 | ret = -EINVAL; |
| 3263 | goto exit; |
| 3264 | } |
Jakub Sitnicki | f6c4770 | 2016-02-29 17:04:23 -0500 | [diff] [blame] | 3265 | for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) { |
| 3266 | /* Check word enable condition in the section */ |
Jakub Sitnicki | 32a39dd | 2016-02-29 17:04:24 -0500 | [diff] [blame] | 3267 | if (word_mask & BIT(i)) { |
Jakub Sitnicki | f6c4770 | 2016-02-29 17:04:23 -0500 | [diff] [blame] | 3268 | map_addr += 2; |
Jakub Sitnicki | 32a39dd | 2016-02-29 17:04:24 -0500 | [diff] [blame] | 3269 | continue; |
| 3270 | } |
| 3271 | |
| 3272 | ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); |
| 3273 | if (ret) |
| 3274 | goto exit; |
| 3275 | priv->efuse_wifi.raw[map_addr++] = val8; |
| 3276 | |
| 3277 | ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &val8); |
| 3278 | if (ret) |
| 3279 | goto exit; |
| 3280 | priv->efuse_wifi.raw[map_addr++] = val8; |
Jakub Sitnicki | f6c4770 | 2016-02-29 17:04:23 -0500 | [diff] [blame] | 3281 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3282 | } |
| 3283 | |
| 3284 | exit: |
| 3285 | rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE); |
| 3286 | |
| 3287 | return ret; |
| 3288 | } |
| 3289 | |
Jes Sorensen | d48fe60 | 2016-02-03 13:39:44 -0500 | [diff] [blame] | 3290 | static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv) |
| 3291 | { |
| 3292 | u8 val8; |
| 3293 | u16 sys_func; |
| 3294 | |
| 3295 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
Jes Sorensen | 53b381c | 2016-02-03 13:39:57 -0500 | [diff] [blame] | 3296 | val8 &= ~BIT(0); |
Jes Sorensen | d48fe60 | 2016-02-03 13:39:44 -0500 | [diff] [blame] | 3297 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); |
Jes Sorensen | 7d4ccb8 | 2016-02-29 17:05:50 -0500 | [diff] [blame] | 3298 | |
Jes Sorensen | d48fe60 | 2016-02-03 13:39:44 -0500 | [diff] [blame] | 3299 | sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 3300 | sys_func &= ~SYS_FUNC_CPU_ENABLE; |
| 3301 | rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); |
Jes Sorensen | 7d4ccb8 | 2016-02-29 17:05:50 -0500 | [diff] [blame] | 3302 | |
Jes Sorensen | d48fe60 | 2016-02-03 13:39:44 -0500 | [diff] [blame] | 3303 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
Jes Sorensen | 53b381c | 2016-02-03 13:39:57 -0500 | [diff] [blame] | 3304 | val8 |= BIT(0); |
Jes Sorensen | d48fe60 | 2016-02-03 13:39:44 -0500 | [diff] [blame] | 3305 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); |
Jes Sorensen | 7d4ccb8 | 2016-02-29 17:05:50 -0500 | [diff] [blame] | 3306 | |
| 3307 | sys_func |= SYS_FUNC_CPU_ENABLE; |
| 3308 | rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); |
| 3309 | } |
| 3310 | |
| 3311 | static void rtl8723bu_reset_8051(struct rtl8xxxu_priv *priv) |
| 3312 | { |
| 3313 | u8 val8; |
| 3314 | u16 sys_func; |
| 3315 | |
| 3316 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); |
| 3317 | val8 &= ~BIT(1); |
| 3318 | rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); |
| 3319 | |
| 3320 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
| 3321 | val8 &= ~BIT(0); |
| 3322 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); |
| 3323 | |
| 3324 | sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 3325 | sys_func &= ~SYS_FUNC_CPU_ENABLE; |
| 3326 | rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); |
| 3327 | |
| 3328 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); |
| 3329 | val8 &= ~BIT(1); |
| 3330 | rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); |
| 3331 | |
| 3332 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
| 3333 | val8 |= BIT(0); |
| 3334 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); |
| 3335 | |
Jes Sorensen | d48fe60 | 2016-02-03 13:39:44 -0500 | [diff] [blame] | 3336 | sys_func |= SYS_FUNC_CPU_ENABLE; |
| 3337 | rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func); |
| 3338 | } |
| 3339 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3340 | static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv) |
| 3341 | { |
| 3342 | struct device *dev = &priv->udev->dev; |
| 3343 | int ret = 0, i; |
| 3344 | u32 val32; |
| 3345 | |
| 3346 | /* Poll checksum report */ |
| 3347 | for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { |
| 3348 | val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); |
| 3349 | if (val32 & MCU_FW_DL_CSUM_REPORT) |
| 3350 | break; |
| 3351 | } |
| 3352 | |
| 3353 | if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { |
| 3354 | dev_warn(dev, "Firmware checksum poll timed out\n"); |
| 3355 | ret = -EAGAIN; |
| 3356 | goto exit; |
| 3357 | } |
| 3358 | |
| 3359 | val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); |
| 3360 | val32 |= MCU_FW_DL_READY; |
| 3361 | val32 &= ~MCU_WINT_INIT_READY; |
| 3362 | rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); |
| 3363 | |
Jes Sorensen | d48fe60 | 2016-02-03 13:39:44 -0500 | [diff] [blame] | 3364 | /* |
| 3365 | * Reset the 8051 in order for the firmware to start running, |
| 3366 | * otherwise it won't come up on the 8192eu |
| 3367 | */ |
Jes Sorensen | 7d4ccb8 | 2016-02-29 17:05:50 -0500 | [diff] [blame] | 3368 | priv->fops->reset_8051(priv); |
Jes Sorensen | d48fe60 | 2016-02-03 13:39:44 -0500 | [diff] [blame] | 3369 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3370 | /* Wait for firmware to become ready */ |
| 3371 | for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) { |
| 3372 | val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); |
| 3373 | if (val32 & MCU_WINT_INIT_READY) |
| 3374 | break; |
| 3375 | |
| 3376 | udelay(100); |
| 3377 | } |
| 3378 | |
| 3379 | if (i == RTL8XXXU_FIRMWARE_POLL_MAX) { |
| 3380 | dev_warn(dev, "Firmware failed to start\n"); |
| 3381 | ret = -EAGAIN; |
| 3382 | goto exit; |
| 3383 | } |
| 3384 | |
Jes Sorensen | 3a4be6a | 2016-02-29 17:04:58 -0500 | [diff] [blame] | 3385 | /* |
| 3386 | * Init H2C command |
| 3387 | */ |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 3388 | if (priv->rtl_chip == RTL8723B) |
Jes Sorensen | 3a4be6a | 2016-02-29 17:04:58 -0500 | [diff] [blame] | 3389 | rtl8xxxu_write8(priv, REG_HMTFR, 0x0f); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3390 | exit: |
| 3391 | return ret; |
| 3392 | } |
| 3393 | |
| 3394 | static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv) |
| 3395 | { |
| 3396 | int pages, remainder, i, ret; |
Jes Sorensen | d48fe60 | 2016-02-03 13:39:44 -0500 | [diff] [blame] | 3397 | u8 val8; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3398 | u16 val16; |
| 3399 | u32 val32; |
| 3400 | u8 *fwptr; |
| 3401 | |
| 3402 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1); |
| 3403 | val8 |= 4; |
| 3404 | rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8); |
| 3405 | |
| 3406 | /* 8051 enable */ |
| 3407 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
Jes Sorensen | 43154f6 | 2016-02-03 13:39:35 -0500 | [diff] [blame] | 3408 | val16 |= SYS_FUNC_CPU_ENABLE; |
| 3409 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3410 | |
Jes Sorensen | 216202a | 2016-02-03 13:39:37 -0500 | [diff] [blame] | 3411 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); |
| 3412 | if (val8 & MCU_FW_RAM_SEL) { |
| 3413 | pr_info("do the RAM reset\n"); |
| 3414 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); |
Jes Sorensen | 7d4ccb8 | 2016-02-29 17:05:50 -0500 | [diff] [blame] | 3415 | priv->fops->reset_8051(priv); |
Jes Sorensen | 216202a | 2016-02-03 13:39:37 -0500 | [diff] [blame] | 3416 | } |
| 3417 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3418 | /* MCU firmware download enable */ |
| 3419 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); |
Jes Sorensen | ef1c049 | 2016-02-03 13:39:36 -0500 | [diff] [blame] | 3420 | val8 |= MCU_FW_DL_ENABLE; |
| 3421 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3422 | |
| 3423 | /* 8051 reset */ |
| 3424 | val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL); |
Jes Sorensen | ef1c049 | 2016-02-03 13:39:36 -0500 | [diff] [blame] | 3425 | val32 &= ~BIT(19); |
| 3426 | rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3427 | |
| 3428 | /* Reset firmware download checksum */ |
| 3429 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL); |
Jes Sorensen | ef1c049 | 2016-02-03 13:39:36 -0500 | [diff] [blame] | 3430 | val8 |= MCU_FW_DL_CSUM_REPORT; |
| 3431 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3432 | |
| 3433 | pages = priv->fw_size / RTL_FW_PAGE_SIZE; |
| 3434 | remainder = priv->fw_size % RTL_FW_PAGE_SIZE; |
| 3435 | |
| 3436 | fwptr = priv->fw_data->data; |
| 3437 | |
| 3438 | for (i = 0; i < pages; i++) { |
| 3439 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; |
Jes Sorensen | ef1c049 | 2016-02-03 13:39:36 -0500 | [diff] [blame] | 3440 | val8 |= i; |
| 3441 | rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3442 | |
| 3443 | ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, |
| 3444 | fwptr, RTL_FW_PAGE_SIZE); |
| 3445 | if (ret != RTL_FW_PAGE_SIZE) { |
| 3446 | ret = -EAGAIN; |
| 3447 | goto fw_abort; |
| 3448 | } |
| 3449 | |
| 3450 | fwptr += RTL_FW_PAGE_SIZE; |
| 3451 | } |
| 3452 | |
| 3453 | if (remainder) { |
| 3454 | val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8; |
Jes Sorensen | ef1c049 | 2016-02-03 13:39:36 -0500 | [diff] [blame] | 3455 | val8 |= i; |
| 3456 | rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3457 | ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS, |
| 3458 | fwptr, remainder); |
| 3459 | if (ret != remainder) { |
| 3460 | ret = -EAGAIN; |
| 3461 | goto fw_abort; |
| 3462 | } |
| 3463 | } |
| 3464 | |
| 3465 | ret = 0; |
| 3466 | fw_abort: |
| 3467 | /* MCU firmware download disable */ |
| 3468 | val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL); |
Jes Sorensen | ef1c049 | 2016-02-03 13:39:36 -0500 | [diff] [blame] | 3469 | val16 &= ~MCU_FW_DL_ENABLE; |
| 3470 | rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3471 | |
| 3472 | return ret; |
| 3473 | } |
| 3474 | |
| 3475 | static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name) |
| 3476 | { |
| 3477 | struct device *dev = &priv->udev->dev; |
| 3478 | const struct firmware *fw; |
| 3479 | int ret = 0; |
| 3480 | u16 signature; |
| 3481 | |
| 3482 | dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name); |
| 3483 | if (request_firmware(&fw, fw_name, &priv->udev->dev)) { |
| 3484 | dev_warn(dev, "request_firmware(%s) failed\n", fw_name); |
| 3485 | ret = -EAGAIN; |
| 3486 | goto exit; |
| 3487 | } |
| 3488 | if (!fw) { |
| 3489 | dev_warn(dev, "Firmware data not available\n"); |
| 3490 | ret = -EINVAL; |
| 3491 | goto exit; |
| 3492 | } |
| 3493 | |
| 3494 | priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL); |
Tobias Klauser | 98e27cb | 2016-02-03 13:39:43 -0500 | [diff] [blame] | 3495 | if (!priv->fw_data) { |
| 3496 | ret = -ENOMEM; |
| 3497 | goto exit; |
| 3498 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3499 | priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header); |
| 3500 | |
| 3501 | signature = le16_to_cpu(priv->fw_data->signature); |
| 3502 | switch (signature & 0xfff0) { |
Jes Sorensen | 0e5d435 | 2016-02-29 17:04:00 -0500 | [diff] [blame] | 3503 | case 0x92e0: |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3504 | case 0x92c0: |
| 3505 | case 0x88c0: |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 3506 | case 0x5300: |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3507 | case 0x2300: |
| 3508 | break; |
| 3509 | default: |
| 3510 | ret = -EINVAL; |
| 3511 | dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n", |
| 3512 | __func__, signature); |
| 3513 | } |
| 3514 | |
| 3515 | dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n", |
| 3516 | le16_to_cpu(priv->fw_data->major_version), |
| 3517 | priv->fw_data->minor_version, signature); |
| 3518 | |
| 3519 | exit: |
| 3520 | release_firmware(fw); |
| 3521 | return ret; |
| 3522 | } |
| 3523 | |
| 3524 | static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv) |
| 3525 | { |
| 3526 | char *fw_name; |
| 3527 | int ret; |
| 3528 | |
| 3529 | switch (priv->chip_cut) { |
| 3530 | case 0: |
| 3531 | fw_name = "rtlwifi/rtl8723aufw_A.bin"; |
| 3532 | break; |
| 3533 | case 1: |
| 3534 | if (priv->enable_bluetooth) |
| 3535 | fw_name = "rtlwifi/rtl8723aufw_B.bin"; |
| 3536 | else |
| 3537 | fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin"; |
| 3538 | |
| 3539 | break; |
| 3540 | default: |
| 3541 | return -EINVAL; |
| 3542 | } |
| 3543 | |
| 3544 | ret = rtl8xxxu_load_firmware(priv, fw_name); |
| 3545 | return ret; |
| 3546 | } |
| 3547 | |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 3548 | static int rtl8723bu_load_firmware(struct rtl8xxxu_priv *priv) |
| 3549 | { |
| 3550 | char *fw_name; |
| 3551 | int ret; |
| 3552 | |
| 3553 | if (priv->enable_bluetooth) |
| 3554 | fw_name = "rtlwifi/rtl8723bu_bt.bin"; |
| 3555 | else |
| 3556 | fw_name = "rtlwifi/rtl8723bu_nic.bin"; |
| 3557 | |
| 3558 | ret = rtl8xxxu_load_firmware(priv, fw_name); |
| 3559 | return ret; |
| 3560 | } |
| 3561 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 3562 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
| 3563 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3564 | static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv) |
| 3565 | { |
| 3566 | char *fw_name; |
| 3567 | int ret; |
| 3568 | |
| 3569 | if (!priv->vendor_umc) |
| 3570 | fw_name = "rtlwifi/rtl8192cufw_TMSC.bin"; |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 3571 | else if (priv->chip_cut || priv->rtl_chip == RTL8192C) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3572 | fw_name = "rtlwifi/rtl8192cufw_B.bin"; |
| 3573 | else |
| 3574 | fw_name = "rtlwifi/rtl8192cufw_A.bin"; |
| 3575 | |
| 3576 | ret = rtl8xxxu_load_firmware(priv, fw_name); |
| 3577 | |
| 3578 | return ret; |
| 3579 | } |
| 3580 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 3581 | #endif |
| 3582 | |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 3583 | static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv) |
| 3584 | { |
| 3585 | char *fw_name; |
| 3586 | int ret; |
| 3587 | |
Jes Sorensen | 0e5d435 | 2016-02-29 17:04:00 -0500 | [diff] [blame] | 3588 | fw_name = "rtlwifi/rtl8192eu_nic.bin"; |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 3589 | |
| 3590 | ret = rtl8xxxu_load_firmware(priv, fw_name); |
| 3591 | |
| 3592 | return ret; |
| 3593 | } |
| 3594 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3595 | static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv) |
| 3596 | { |
| 3597 | u16 val16; |
| 3598 | int i = 100; |
| 3599 | |
| 3600 | /* Inform 8051 to perform reset */ |
| 3601 | rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20); |
| 3602 | |
| 3603 | for (i = 100; i > 0; i--) { |
| 3604 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 3605 | |
| 3606 | if (!(val16 & SYS_FUNC_CPU_ENABLE)) { |
| 3607 | dev_dbg(&priv->udev->dev, |
| 3608 | "%s: Firmware self reset success!\n", __func__); |
| 3609 | break; |
| 3610 | } |
| 3611 | udelay(50); |
| 3612 | } |
| 3613 | |
| 3614 | if (!i) { |
| 3615 | /* Force firmware reset */ |
| 3616 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 3617 | val16 &= ~SYS_FUNC_CPU_ENABLE; |
| 3618 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 3619 | } |
| 3620 | } |
| 3621 | |
Jes Sorensen | f0d9f5e | 2016-02-29 17:04:16 -0500 | [diff] [blame] | 3622 | static void rtl8723bu_phy_init_antenna_selection(struct rtl8xxxu_priv *priv) |
| 3623 | { |
| 3624 | u32 val32; |
| 3625 | |
Jes Sorensen | 70bc1e2 | 2016-04-07 14:19:31 -0400 | [diff] [blame] | 3626 | val32 = rtl8xxxu_read32(priv, REG_PAD_CTRL1); |
Jes Sorensen | f0d9f5e | 2016-02-29 17:04:16 -0500 | [diff] [blame] | 3627 | val32 &= ~(BIT(20) | BIT(24)); |
Jes Sorensen | 70bc1e2 | 2016-04-07 14:19:31 -0400 | [diff] [blame] | 3628 | rtl8xxxu_write32(priv, REG_PAD_CTRL1, val32); |
Jes Sorensen | f0d9f5e | 2016-02-29 17:04:16 -0500 | [diff] [blame] | 3629 | |
| 3630 | val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); |
| 3631 | val32 &= ~BIT(4); |
Jes Sorensen | 3a4be6a | 2016-02-29 17:04:58 -0500 | [diff] [blame] | 3632 | rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); |
| 3633 | |
| 3634 | val32 = rtl8xxxu_read32(priv, REG_GPIO_MUXCFG); |
Jes Sorensen | f0d9f5e | 2016-02-29 17:04:16 -0500 | [diff] [blame] | 3635 | val32 |= BIT(3); |
| 3636 | rtl8xxxu_write32(priv, REG_GPIO_MUXCFG, val32); |
| 3637 | |
| 3638 | val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); |
Jes Sorensen | f0d9f5e | 2016-02-29 17:04:16 -0500 | [diff] [blame] | 3639 | val32 |= BIT(24); |
| 3640 | rtl8xxxu_write32(priv, REG_LEDCFG0, val32); |
| 3641 | |
Jes Sorensen | 3a4be6a | 2016-02-29 17:04:58 -0500 | [diff] [blame] | 3642 | val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); |
| 3643 | val32 &= ~BIT(23); |
| 3644 | rtl8xxxu_write32(priv, REG_LEDCFG0, val32); |
| 3645 | |
Jes Sorensen | 120e627 | 2016-02-29 17:05:14 -0500 | [diff] [blame] | 3646 | val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); |
Jes Sorensen | f0d9f5e | 2016-02-29 17:04:16 -0500 | [diff] [blame] | 3647 | val32 |= (BIT(0) | BIT(1)); |
Jes Sorensen | 120e627 | 2016-02-29 17:05:14 -0500 | [diff] [blame] | 3648 | rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); |
Jes Sorensen | f0d9f5e | 2016-02-29 17:04:16 -0500 | [diff] [blame] | 3649 | |
Jes Sorensen | 59b7439 | 2016-02-29 17:05:15 -0500 | [diff] [blame] | 3650 | val32 = rtl8xxxu_read32(priv, REG_RFE_CTRL_ANTA_SRC); |
Jes Sorensen | f0d9f5e | 2016-02-29 17:04:16 -0500 | [diff] [blame] | 3651 | val32 &= 0xffffff00; |
| 3652 | val32 |= 0x77; |
Jes Sorensen | 59b7439 | 2016-02-29 17:05:15 -0500 | [diff] [blame] | 3653 | rtl8xxxu_write32(priv, REG_RFE_CTRL_ANTA_SRC, val32); |
Jes Sorensen | 3a4be6a | 2016-02-29 17:04:58 -0500 | [diff] [blame] | 3654 | |
| 3655 | val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); |
| 3656 | val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; |
| 3657 | rtl8xxxu_write32(priv, REG_PWR_DATA, val32); |
Jes Sorensen | f0d9f5e | 2016-02-29 17:04:16 -0500 | [diff] [blame] | 3658 | } |
| 3659 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3660 | static int |
Jes Sorensen | c606e66 | 2016-04-07 14:19:16 -0400 | [diff] [blame] | 3661 | rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3662 | { |
Jes Sorensen | c606e66 | 2016-04-07 14:19:16 -0400 | [diff] [blame] | 3663 | struct rtl8xxxu_reg8val *array = priv->fops->mactable; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3664 | int i, ret; |
| 3665 | u16 reg; |
| 3666 | u8 val; |
| 3667 | |
| 3668 | for (i = 0; ; i++) { |
| 3669 | reg = array[i].reg; |
| 3670 | val = array[i].val; |
| 3671 | |
| 3672 | if (reg == 0xffff && val == 0xff) |
| 3673 | break; |
| 3674 | |
| 3675 | ret = rtl8xxxu_write8(priv, reg, val); |
| 3676 | if (ret != 1) { |
| 3677 | dev_warn(&priv->udev->dev, |
Jes Sorensen | c606e66 | 2016-04-07 14:19:16 -0400 | [diff] [blame] | 3678 | "Failed to initialize MAC " |
| 3679 | "(reg: %04x, val %02x)\n", reg, val); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3680 | return -EAGAIN; |
| 3681 | } |
| 3682 | } |
| 3683 | |
Jes Sorensen | 8a59485 | 2016-04-07 14:19:26 -0400 | [diff] [blame] | 3684 | if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) |
Jes Sorensen | 8baf670 | 2016-02-29 17:04:54 -0500 | [diff] [blame] | 3685 | rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3686 | |
| 3687 | return 0; |
| 3688 | } |
| 3689 | |
| 3690 | static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv, |
| 3691 | struct rtl8xxxu_reg32val *array) |
| 3692 | { |
| 3693 | int i, ret; |
| 3694 | u16 reg; |
| 3695 | u32 val; |
| 3696 | |
| 3697 | for (i = 0; ; i++) { |
| 3698 | reg = array[i].reg; |
| 3699 | val = array[i].val; |
| 3700 | |
| 3701 | if (reg == 0xffff && val == 0xffffffff) |
| 3702 | break; |
| 3703 | |
| 3704 | ret = rtl8xxxu_write32(priv, reg, val); |
| 3705 | if (ret != sizeof(val)) { |
| 3706 | dev_warn(&priv->udev->dev, |
| 3707 | "Failed to initialize PHY\n"); |
| 3708 | return -EAGAIN; |
| 3709 | } |
| 3710 | udelay(1); |
| 3711 | } |
| 3712 | |
| 3713 | return 0; |
| 3714 | } |
| 3715 | |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 3716 | static void rtl8723au_init_phy_bb(struct rtl8xxxu_priv *priv) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3717 | { |
Jes Sorensen | b84cac1 | 2016-04-14 14:59:00 -0400 | [diff] [blame] | 3718 | u8 val8, ldoa15, ldov12d, lpldo, ldohci12; |
Jes Sorensen | 04313eb | 2016-02-29 17:04:51 -0500 | [diff] [blame] | 3719 | u16 val16; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3720 | u32 val32; |
| 3721 | |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 3722 | val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); |
| 3723 | udelay(2); |
| 3724 | val8 |= AFE_PLL_320_ENABLE; |
| 3725 | rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); |
| 3726 | udelay(2); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3727 | |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 3728 | rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff); |
| 3729 | udelay(2); |
Jes Sorensen | 8baf670 | 2016-02-29 17:04:54 -0500 | [diff] [blame] | 3730 | |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 3731 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 3732 | val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB; |
| 3733 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3734 | |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 3735 | val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL); |
| 3736 | val32 &= ~AFE_XTAL_RF_GATE; |
| 3737 | if (priv->has_bluetooth) |
| 3738 | val32 &= ~AFE_XTAL_BT_GATE; |
| 3739 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3740 | |
| 3741 | /* 6. 0x1f[7:0] = 0x07 */ |
| 3742 | val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; |
| 3743 | rtl8xxxu_write8(priv, REG_RF_CTRL, val8); |
| 3744 | |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 3745 | if (priv->hi_pa) |
Jes Sorensen | abd71bd | 2016-04-07 14:19:22 -0400 | [diff] [blame] | 3746 | rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table); |
| 3747 | else if (priv->tx_paths == 2) |
| 3748 | rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table); |
| 3749 | else |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3750 | rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table); |
| 3751 | |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 3752 | if (priv->rtl_chip == RTL8188C && priv->hi_pa && |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3753 | priv->vendor_umc && priv->chip_cut == 1) |
| 3754 | rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50); |
Jes Sorensen | c82f8d1 | 2016-04-14 14:58:59 -0400 | [diff] [blame] | 3755 | |
| 3756 | if (priv->hi_pa) |
| 3757 | rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table); |
| 3758 | else |
| 3759 | rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table); |
Jes Sorensen | b84cac1 | 2016-04-14 14:59:00 -0400 | [diff] [blame] | 3760 | |
| 3761 | ldoa15 = LDOA15_ENABLE | LDOA15_OBUF; |
| 3762 | ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT); |
| 3763 | ldohci12 = 0x57; |
| 3764 | lpldo = 1; |
| 3765 | val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15; |
| 3766 | rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32); |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 3767 | } |
| 3768 | |
| 3769 | static void rtl8723bu_init_phy_bb(struct rtl8xxxu_priv *priv) |
| 3770 | { |
| 3771 | u8 val8; |
| 3772 | u16 val16; |
| 3773 | |
| 3774 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 3775 | val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; |
| 3776 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 3777 | |
| 3778 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); |
| 3779 | |
| 3780 | /* 6. 0x1f[7:0] = 0x07 */ |
| 3781 | val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; |
| 3782 | rtl8xxxu_write8(priv, REG_RF_CTRL, val8); |
| 3783 | |
| 3784 | /* Why? */ |
| 3785 | rtl8xxxu_write8(priv, REG_SYS_FUNC, 0xe3); |
| 3786 | rtl8xxxu_write8(priv, REG_AFE_XTAL_CTRL + 1, 0x80); |
| 3787 | rtl8xxxu_init_phy_regs(priv, rtl8723b_phy_1t_init_table); |
Jes Sorensen | c82f8d1 | 2016-04-14 14:58:59 -0400 | [diff] [blame] | 3788 | |
| 3789 | rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8723bu_table); |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 3790 | } |
| 3791 | |
| 3792 | static void rtl8192eu_init_phy_bb(struct rtl8xxxu_priv *priv) |
| 3793 | { |
| 3794 | u8 val8; |
| 3795 | u16 val16; |
| 3796 | |
| 3797 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 3798 | val16 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB | SYS_FUNC_DIO_RF; |
| 3799 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 3800 | |
| 3801 | /* 6. 0x1f[7:0] = 0x07 */ |
| 3802 | val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; |
| 3803 | rtl8xxxu_write8(priv, REG_RF_CTRL, val8); |
| 3804 | |
| 3805 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 3806 | val16 |= (SYS_FUNC_USBA | SYS_FUNC_USBD | SYS_FUNC_DIO_RF | |
| 3807 | SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB); |
| 3808 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 3809 | val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB; |
| 3810 | rtl8xxxu_write8(priv, REG_RF_CTRL, val8); |
| 3811 | rtl8xxxu_init_phy_regs(priv, rtl8192eu_phy_init_table); |
Jes Sorensen | c82f8d1 | 2016-04-14 14:58:59 -0400 | [diff] [blame] | 3812 | |
| 3813 | if (priv->hi_pa) |
| 3814 | rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_highpa_table); |
| 3815 | else |
| 3816 | rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_8192eu_std_table); |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 3817 | } |
| 3818 | |
| 3819 | /* |
| 3820 | * Most of this is black magic retrieved from the old rtl8723au driver |
| 3821 | */ |
| 3822 | static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv) |
| 3823 | { |
Jes Sorensen | b84cac1 | 2016-04-14 14:59:00 -0400 | [diff] [blame] | 3824 | u8 val8; |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 3825 | u32 val32; |
| 3826 | |
| 3827 | priv->fops->init_phy_bb(priv); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3828 | |
| 3829 | if (priv->tx_paths == 1 && priv->rx_paths == 2) { |
| 3830 | /* |
| 3831 | * For 1T2R boards, patch the registers. |
| 3832 | * |
| 3833 | * It looks like 8191/2 1T2R boards use path B for TX |
| 3834 | */ |
| 3835 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO); |
| 3836 | val32 &= ~(BIT(0) | BIT(1)); |
| 3837 | val32 |= BIT(1); |
| 3838 | rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32); |
| 3839 | |
| 3840 | val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO); |
| 3841 | val32 &= ~0x300033; |
| 3842 | val32 |= 0x200022; |
| 3843 | rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32); |
| 3844 | |
| 3845 | val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); |
Jes Sorensen | bd8fe40 | 2016-04-14 14:58:56 -0400 | [diff] [blame] | 3846 | val32 &= ~CCK0_AFE_RX_MASK; |
Jes Sorensen | 9068308 | 2016-04-14 14:58:55 -0400 | [diff] [blame] | 3847 | val32 &= 0x00ffffff; |
Jes Sorensen | bd8fe40 | 2016-04-14 14:58:56 -0400 | [diff] [blame] | 3848 | val32 |= 0x40000000; |
| 3849 | val32 |= CCK0_AFE_RX_ANT_B; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3850 | rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); |
| 3851 | |
| 3852 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE); |
| 3853 | val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK); |
| 3854 | val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B | |
| 3855 | OFDM_RF_PATH_TX_B); |
| 3856 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32); |
| 3857 | |
| 3858 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1); |
| 3859 | val32 &= ~(BIT(4) | BIT(5)); |
| 3860 | val32 |= BIT(4); |
| 3861 | rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32); |
| 3862 | |
| 3863 | val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON); |
| 3864 | val32 &= ~(BIT(27) | BIT(26)); |
| 3865 | val32 |= BIT(27); |
| 3866 | rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32); |
| 3867 | |
| 3868 | val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON); |
| 3869 | val32 &= ~(BIT(27) | BIT(26)); |
| 3870 | val32 |= BIT(27); |
| 3871 | rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32); |
| 3872 | |
| 3873 | val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON); |
| 3874 | val32 &= ~(BIT(27) | BIT(26)); |
| 3875 | val32 |= BIT(27); |
| 3876 | rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32); |
| 3877 | |
| 3878 | val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON); |
| 3879 | val32 &= ~(BIT(27) | BIT(26)); |
| 3880 | val32 |= BIT(27); |
| 3881 | rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32); |
| 3882 | |
| 3883 | val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX); |
| 3884 | val32 &= ~(BIT(27) | BIT(26)); |
| 3885 | val32 |= BIT(27); |
| 3886 | rtl8xxxu_write32(priv, REG_TX_TO_TX, val32); |
| 3887 | } |
| 3888 | |
Jes Sorensen | 4ef22eb | 2016-02-29 17:04:55 -0500 | [diff] [blame] | 3889 | if (priv->has_xtalk) { |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3890 | val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL); |
| 3891 | |
Jes Sorensen | 4ef22eb | 2016-02-29 17:04:55 -0500 | [diff] [blame] | 3892 | val8 = priv->xtalk; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3893 | val32 &= 0xff000fff; |
| 3894 | val32 |= ((val8 | (val8 << 6)) << 12); |
| 3895 | |
| 3896 | rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32); |
| 3897 | } |
| 3898 | |
Jes Sorensen | 8a59485 | 2016-04-07 14:19:26 -0400 | [diff] [blame] | 3899 | if (priv->rtl_chip == RTL8192E) |
| 3900 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x000f81fb); |
| 3901 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3902 | return 0; |
| 3903 | } |
| 3904 | |
| 3905 | static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv, |
| 3906 | struct rtl8xxxu_rfregval *array, |
| 3907 | enum rtl8xxxu_rfpath path) |
| 3908 | { |
| 3909 | int i, ret; |
| 3910 | u8 reg; |
| 3911 | u32 val; |
| 3912 | |
| 3913 | for (i = 0; ; i++) { |
| 3914 | reg = array[i].reg; |
| 3915 | val = array[i].val; |
| 3916 | |
| 3917 | if (reg == 0xff && val == 0xffffffff) |
| 3918 | break; |
| 3919 | |
| 3920 | switch (reg) { |
| 3921 | case 0xfe: |
| 3922 | msleep(50); |
| 3923 | continue; |
| 3924 | case 0xfd: |
| 3925 | mdelay(5); |
| 3926 | continue; |
| 3927 | case 0xfc: |
| 3928 | mdelay(1); |
| 3929 | continue; |
| 3930 | case 0xfb: |
| 3931 | udelay(50); |
| 3932 | continue; |
| 3933 | case 0xfa: |
| 3934 | udelay(5); |
| 3935 | continue; |
| 3936 | case 0xf9: |
| 3937 | udelay(1); |
| 3938 | continue; |
| 3939 | } |
| 3940 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 3941 | ret = rtl8xxxu_write_rfreg(priv, path, reg, val); |
| 3942 | if (ret) { |
| 3943 | dev_warn(&priv->udev->dev, |
| 3944 | "Failed to initialize RF\n"); |
| 3945 | return -EAGAIN; |
| 3946 | } |
| 3947 | udelay(1); |
| 3948 | } |
| 3949 | |
| 3950 | return 0; |
| 3951 | } |
| 3952 | |
| 3953 | static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv, |
| 3954 | struct rtl8xxxu_rfregval *table, |
| 3955 | enum rtl8xxxu_rfpath path) |
| 3956 | { |
| 3957 | u32 val32; |
| 3958 | u16 val16, rfsi_rfenv; |
| 3959 | u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2; |
| 3960 | |
| 3961 | switch (path) { |
| 3962 | case RF_A: |
| 3963 | reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL; |
| 3964 | reg_int_oe = REG_FPGA0_XA_RF_INT_OE; |
| 3965 | reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2; |
| 3966 | break; |
| 3967 | case RF_B: |
| 3968 | reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL; |
| 3969 | reg_int_oe = REG_FPGA0_XB_RF_INT_OE; |
| 3970 | reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2; |
| 3971 | break; |
| 3972 | default: |
| 3973 | dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n", |
| 3974 | __func__, path + 'A'); |
| 3975 | return -EINVAL; |
| 3976 | } |
| 3977 | /* For path B, use XB */ |
| 3978 | rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl); |
| 3979 | rfsi_rfenv &= FPGA0_RF_RFENV; |
| 3980 | |
| 3981 | /* |
| 3982 | * These two we might be able to optimize into one |
| 3983 | */ |
| 3984 | val32 = rtl8xxxu_read32(priv, reg_int_oe); |
| 3985 | val32 |= BIT(20); /* 0x10 << 16 */ |
| 3986 | rtl8xxxu_write32(priv, reg_int_oe, val32); |
| 3987 | udelay(1); |
| 3988 | |
| 3989 | val32 = rtl8xxxu_read32(priv, reg_int_oe); |
| 3990 | val32 |= BIT(4); |
| 3991 | rtl8xxxu_write32(priv, reg_int_oe, val32); |
| 3992 | udelay(1); |
| 3993 | |
| 3994 | /* |
| 3995 | * These two we might be able to optimize into one |
| 3996 | */ |
| 3997 | val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); |
| 3998 | val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN; |
| 3999 | rtl8xxxu_write32(priv, reg_hssi_parm2, val32); |
| 4000 | udelay(1); |
| 4001 | |
| 4002 | val32 = rtl8xxxu_read32(priv, reg_hssi_parm2); |
| 4003 | val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN; |
| 4004 | rtl8xxxu_write32(priv, reg_hssi_parm2, val32); |
| 4005 | udelay(1); |
| 4006 | |
| 4007 | rtl8xxxu_init_rf_regs(priv, table, path); |
| 4008 | |
| 4009 | /* For path B, use XB */ |
| 4010 | val16 = rtl8xxxu_read16(priv, reg_sw_ctrl); |
| 4011 | val16 &= ~FPGA0_RF_RFENV; |
| 4012 | val16 |= rfsi_rfenv; |
| 4013 | rtl8xxxu_write16(priv, reg_sw_ctrl, val16); |
| 4014 | |
| 4015 | return 0; |
| 4016 | } |
| 4017 | |
| 4018 | static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data) |
| 4019 | { |
| 4020 | int ret = -EBUSY; |
| 4021 | int count = 0; |
| 4022 | u32 value; |
| 4023 | |
| 4024 | value = LLT_OP_WRITE | address << 8 | data; |
| 4025 | |
| 4026 | rtl8xxxu_write32(priv, REG_LLT_INIT, value); |
| 4027 | |
| 4028 | do { |
| 4029 | value = rtl8xxxu_read32(priv, REG_LLT_INIT); |
| 4030 | if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) { |
| 4031 | ret = 0; |
| 4032 | break; |
| 4033 | } |
| 4034 | } while (count++ < 20); |
| 4035 | |
| 4036 | return ret; |
| 4037 | } |
| 4038 | |
| 4039 | static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page) |
| 4040 | { |
| 4041 | int ret; |
| 4042 | int i; |
| 4043 | |
| 4044 | for (i = 0; i < last_tx_page; i++) { |
| 4045 | ret = rtl8xxxu_llt_write(priv, i, i + 1); |
| 4046 | if (ret) |
| 4047 | goto exit; |
| 4048 | } |
| 4049 | |
| 4050 | ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff); |
| 4051 | if (ret) |
| 4052 | goto exit; |
| 4053 | |
| 4054 | /* Mark remaining pages as a ring buffer */ |
| 4055 | for (i = last_tx_page + 1; i < 0xff; i++) { |
| 4056 | ret = rtl8xxxu_llt_write(priv, i, (i + 1)); |
| 4057 | if (ret) |
| 4058 | goto exit; |
| 4059 | } |
| 4060 | |
| 4061 | /* Let last entry point to the start entry of ring buffer */ |
| 4062 | ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1); |
| 4063 | if (ret) |
| 4064 | goto exit; |
| 4065 | |
| 4066 | exit: |
| 4067 | return ret; |
| 4068 | } |
| 4069 | |
Jes Sorensen | 74b99be | 2016-02-29 17:04:04 -0500 | [diff] [blame] | 4070 | static int rtl8xxxu_auto_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page) |
| 4071 | { |
| 4072 | u32 val32; |
| 4073 | int ret = 0; |
| 4074 | int i; |
| 4075 | |
| 4076 | val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); |
Jes Sorensen | 74b99be | 2016-02-29 17:04:04 -0500 | [diff] [blame] | 4077 | val32 |= AUTO_LLT_INIT_LLT; |
| 4078 | rtl8xxxu_write32(priv, REG_AUTO_LLT, val32); |
| 4079 | |
| 4080 | for (i = 500; i; i--) { |
| 4081 | val32 = rtl8xxxu_read32(priv, REG_AUTO_LLT); |
| 4082 | if (!(val32 & AUTO_LLT_INIT_LLT)) |
| 4083 | break; |
| 4084 | usleep_range(2, 4); |
| 4085 | } |
| 4086 | |
Jes Sorensen | 4de2481 | 2016-02-29 17:04:07 -0500 | [diff] [blame] | 4087 | if (!i) { |
Jes Sorensen | 74b99be | 2016-02-29 17:04:04 -0500 | [diff] [blame] | 4088 | ret = -EBUSY; |
| 4089 | dev_warn(&priv->udev->dev, "LLT table init failed\n"); |
| 4090 | } |
Jes Sorensen | 74b99be | 2016-02-29 17:04:04 -0500 | [diff] [blame] | 4091 | |
| 4092 | return ret; |
| 4093 | } |
| 4094 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 4095 | static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv) |
| 4096 | { |
| 4097 | u16 val16, hi, lo; |
| 4098 | u16 hiq, mgq, bkq, beq, viq, voq; |
| 4099 | int hip, mgp, bkp, bep, vip, vop; |
| 4100 | int ret = 0; |
| 4101 | |
| 4102 | switch (priv->ep_tx_count) { |
| 4103 | case 1: |
| 4104 | if (priv->ep_tx_high_queue) { |
| 4105 | hi = TRXDMA_QUEUE_HIGH; |
| 4106 | } else if (priv->ep_tx_low_queue) { |
| 4107 | hi = TRXDMA_QUEUE_LOW; |
| 4108 | } else if (priv->ep_tx_normal_queue) { |
| 4109 | hi = TRXDMA_QUEUE_NORMAL; |
| 4110 | } else { |
| 4111 | hi = 0; |
| 4112 | ret = -EINVAL; |
| 4113 | } |
| 4114 | |
| 4115 | hiq = hi; |
| 4116 | mgq = hi; |
| 4117 | bkq = hi; |
| 4118 | beq = hi; |
| 4119 | viq = hi; |
| 4120 | voq = hi; |
| 4121 | |
| 4122 | hip = 0; |
| 4123 | mgp = 0; |
| 4124 | bkp = 0; |
| 4125 | bep = 0; |
| 4126 | vip = 0; |
| 4127 | vop = 0; |
| 4128 | break; |
| 4129 | case 2: |
| 4130 | if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) { |
| 4131 | hi = TRXDMA_QUEUE_HIGH; |
| 4132 | lo = TRXDMA_QUEUE_LOW; |
| 4133 | } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) { |
| 4134 | hi = TRXDMA_QUEUE_NORMAL; |
| 4135 | lo = TRXDMA_QUEUE_LOW; |
| 4136 | } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) { |
| 4137 | hi = TRXDMA_QUEUE_HIGH; |
| 4138 | lo = TRXDMA_QUEUE_NORMAL; |
| 4139 | } else { |
| 4140 | ret = -EINVAL; |
| 4141 | hi = 0; |
| 4142 | lo = 0; |
| 4143 | } |
| 4144 | |
| 4145 | hiq = hi; |
| 4146 | mgq = hi; |
| 4147 | bkq = lo; |
| 4148 | beq = lo; |
| 4149 | viq = hi; |
| 4150 | voq = hi; |
| 4151 | |
| 4152 | hip = 0; |
| 4153 | mgp = 0; |
| 4154 | bkp = 1; |
| 4155 | bep = 1; |
| 4156 | vip = 0; |
| 4157 | vop = 0; |
| 4158 | break; |
| 4159 | case 3: |
| 4160 | beq = TRXDMA_QUEUE_LOW; |
| 4161 | bkq = TRXDMA_QUEUE_LOW; |
| 4162 | viq = TRXDMA_QUEUE_NORMAL; |
| 4163 | voq = TRXDMA_QUEUE_HIGH; |
| 4164 | mgq = TRXDMA_QUEUE_HIGH; |
| 4165 | hiq = TRXDMA_QUEUE_HIGH; |
| 4166 | |
| 4167 | hip = hiq ^ 3; |
| 4168 | mgp = mgq ^ 3; |
| 4169 | bkp = bkq ^ 3; |
| 4170 | bep = beq ^ 3; |
| 4171 | vip = viq ^ 3; |
| 4172 | vop = viq ^ 3; |
| 4173 | break; |
| 4174 | default: |
| 4175 | ret = -EINVAL; |
| 4176 | } |
| 4177 | |
| 4178 | /* |
| 4179 | * None of the vendor drivers are configuring the beacon |
| 4180 | * queue here .... why? |
| 4181 | */ |
| 4182 | if (!ret) { |
| 4183 | val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL); |
| 4184 | val16 &= 0x7; |
| 4185 | val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) | |
| 4186 | (viq << TRXDMA_CTRL_VIQ_SHIFT) | |
| 4187 | (beq << TRXDMA_CTRL_BEQ_SHIFT) | |
| 4188 | (bkq << TRXDMA_CTRL_BKQ_SHIFT) | |
| 4189 | (mgq << TRXDMA_CTRL_MGQ_SHIFT) | |
| 4190 | (hiq << TRXDMA_CTRL_HIQ_SHIFT); |
| 4191 | rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16); |
| 4192 | |
| 4193 | priv->pipe_out[TXDESC_QUEUE_VO] = |
| 4194 | usb_sndbulkpipe(priv->udev, priv->out_ep[vop]); |
| 4195 | priv->pipe_out[TXDESC_QUEUE_VI] = |
| 4196 | usb_sndbulkpipe(priv->udev, priv->out_ep[vip]); |
| 4197 | priv->pipe_out[TXDESC_QUEUE_BE] = |
| 4198 | usb_sndbulkpipe(priv->udev, priv->out_ep[bep]); |
| 4199 | priv->pipe_out[TXDESC_QUEUE_BK] = |
| 4200 | usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]); |
| 4201 | priv->pipe_out[TXDESC_QUEUE_BEACON] = |
| 4202 | usb_sndbulkpipe(priv->udev, priv->out_ep[0]); |
| 4203 | priv->pipe_out[TXDESC_QUEUE_MGNT] = |
| 4204 | usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]); |
| 4205 | priv->pipe_out[TXDESC_QUEUE_HIGH] = |
| 4206 | usb_sndbulkpipe(priv->udev, priv->out_ep[hip]); |
| 4207 | priv->pipe_out[TXDESC_QUEUE_CMD] = |
| 4208 | usb_sndbulkpipe(priv->udev, priv->out_ep[0]); |
| 4209 | } |
| 4210 | |
| 4211 | return ret; |
| 4212 | } |
| 4213 | |
| 4214 | static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv, |
| 4215 | bool iqk_ok, int result[][8], |
| 4216 | int candidate, bool tx_only) |
| 4217 | { |
| 4218 | u32 oldval, x, tx0_a, reg; |
| 4219 | int y, tx0_c; |
| 4220 | u32 val32; |
| 4221 | |
| 4222 | if (!iqk_ok) |
| 4223 | return; |
| 4224 | |
| 4225 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); |
| 4226 | oldval = val32 >> 22; |
| 4227 | |
| 4228 | x = result[candidate][0]; |
| 4229 | if ((x & 0x00000200) != 0) |
| 4230 | x = x | 0xfffffc00; |
| 4231 | tx0_a = (x * oldval) >> 8; |
| 4232 | |
| 4233 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); |
| 4234 | val32 &= ~0x3ff; |
| 4235 | val32 |= tx0_a; |
| 4236 | rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); |
| 4237 | |
| 4238 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); |
| 4239 | val32 &= ~BIT(31); |
| 4240 | if ((x * oldval >> 7) & 0x1) |
| 4241 | val32 |= BIT(31); |
| 4242 | rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); |
| 4243 | |
| 4244 | y = result[candidate][1]; |
| 4245 | if ((y & 0x00000200) != 0) |
| 4246 | y = y | 0xfffffc00; |
| 4247 | tx0_c = (y * oldval) >> 8; |
| 4248 | |
| 4249 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE); |
| 4250 | val32 &= ~0xf0000000; |
| 4251 | val32 |= (((tx0_c & 0x3c0) >> 6) << 28); |
| 4252 | rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32); |
| 4253 | |
| 4254 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE); |
| 4255 | val32 &= ~0x003f0000; |
| 4256 | val32 |= ((tx0_c & 0x3f) << 16); |
| 4257 | rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32); |
| 4258 | |
| 4259 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); |
| 4260 | val32 &= ~BIT(29); |
| 4261 | if ((y * oldval >> 7) & 0x1) |
| 4262 | val32 |= BIT(29); |
| 4263 | rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); |
| 4264 | |
| 4265 | if (tx_only) { |
| 4266 | dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); |
| 4267 | return; |
| 4268 | } |
| 4269 | |
| 4270 | reg = result[candidate][2]; |
| 4271 | |
| 4272 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); |
| 4273 | val32 &= ~0x3ff; |
| 4274 | val32 |= (reg & 0x3ff); |
| 4275 | rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); |
| 4276 | |
| 4277 | reg = result[candidate][3] & 0x3F; |
| 4278 | |
| 4279 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE); |
| 4280 | val32 &= ~0xfc00; |
| 4281 | val32 |= ((reg << 10) & 0xfc00); |
| 4282 | rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32); |
| 4283 | |
| 4284 | reg = (result[candidate][3] >> 6) & 0xF; |
| 4285 | |
| 4286 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA); |
| 4287 | val32 &= ~0xf0000000; |
| 4288 | val32 |= (reg << 28); |
| 4289 | rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32); |
| 4290 | } |
| 4291 | |
| 4292 | static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv, |
| 4293 | bool iqk_ok, int result[][8], |
| 4294 | int candidate, bool tx_only) |
| 4295 | { |
| 4296 | u32 oldval, x, tx1_a, reg; |
| 4297 | int y, tx1_c; |
| 4298 | u32 val32; |
| 4299 | |
| 4300 | if (!iqk_ok) |
| 4301 | return; |
| 4302 | |
| 4303 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); |
| 4304 | oldval = val32 >> 22; |
| 4305 | |
| 4306 | x = result[candidate][4]; |
| 4307 | if ((x & 0x00000200) != 0) |
| 4308 | x = x | 0xfffffc00; |
| 4309 | tx1_a = (x * oldval) >> 8; |
| 4310 | |
| 4311 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); |
| 4312 | val32 &= ~0x3ff; |
| 4313 | val32 |= tx1_a; |
| 4314 | rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); |
| 4315 | |
| 4316 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); |
| 4317 | val32 &= ~BIT(27); |
| 4318 | if ((x * oldval >> 7) & 0x1) |
| 4319 | val32 |= BIT(27); |
| 4320 | rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); |
| 4321 | |
| 4322 | y = result[candidate][5]; |
| 4323 | if ((y & 0x00000200) != 0) |
| 4324 | y = y | 0xfffffc00; |
| 4325 | tx1_c = (y * oldval) >> 8; |
| 4326 | |
| 4327 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE); |
| 4328 | val32 &= ~0xf0000000; |
| 4329 | val32 |= (((tx1_c & 0x3c0) >> 6) << 28); |
| 4330 | rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32); |
| 4331 | |
| 4332 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE); |
| 4333 | val32 &= ~0x003f0000; |
| 4334 | val32 |= ((tx1_c & 0x3f) << 16); |
| 4335 | rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32); |
| 4336 | |
| 4337 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES); |
| 4338 | val32 &= ~BIT(25); |
| 4339 | if ((y * oldval >> 7) & 0x1) |
| 4340 | val32 |= BIT(25); |
| 4341 | rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32); |
| 4342 | |
| 4343 | if (tx_only) { |
| 4344 | dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__); |
| 4345 | return; |
| 4346 | } |
| 4347 | |
| 4348 | reg = result[candidate][6]; |
| 4349 | |
| 4350 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); |
| 4351 | val32 &= ~0x3ff; |
| 4352 | val32 |= (reg & 0x3ff); |
| 4353 | rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); |
| 4354 | |
| 4355 | reg = result[candidate][7] & 0x3f; |
| 4356 | |
| 4357 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE); |
| 4358 | val32 &= ~0xfc00; |
| 4359 | val32 |= ((reg << 10) & 0xfc00); |
| 4360 | rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32); |
| 4361 | |
| 4362 | reg = (result[candidate][7] >> 6) & 0xf; |
| 4363 | |
| 4364 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE); |
| 4365 | val32 &= ~0x0000f000; |
| 4366 | val32 |= (reg << 12); |
| 4367 | rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32); |
| 4368 | } |
| 4369 | |
| 4370 | #define MAX_TOLERANCE 5 |
| 4371 | |
| 4372 | static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv, |
| 4373 | int result[][8], int c1, int c2) |
| 4374 | { |
| 4375 | u32 i, j, diff, simubitmap, bound = 0; |
| 4376 | int candidate[2] = {-1, -1}; /* for path A and path B */ |
| 4377 | bool retval = true; |
| 4378 | |
| 4379 | if (priv->tx_paths > 1) |
| 4380 | bound = 8; |
| 4381 | else |
| 4382 | bound = 4; |
| 4383 | |
| 4384 | simubitmap = 0; |
| 4385 | |
| 4386 | for (i = 0; i < bound; i++) { |
| 4387 | diff = (result[c1][i] > result[c2][i]) ? |
| 4388 | (result[c1][i] - result[c2][i]) : |
| 4389 | (result[c2][i] - result[c1][i]); |
| 4390 | if (diff > MAX_TOLERANCE) { |
| 4391 | if ((i == 2 || i == 6) && !simubitmap) { |
| 4392 | if (result[c1][i] + result[c1][i + 1] == 0) |
| 4393 | candidate[(i / 4)] = c2; |
| 4394 | else if (result[c2][i] + result[c2][i + 1] == 0) |
| 4395 | candidate[(i / 4)] = c1; |
| 4396 | else |
| 4397 | simubitmap = simubitmap | (1 << i); |
| 4398 | } else { |
| 4399 | simubitmap = simubitmap | (1 << i); |
| 4400 | } |
| 4401 | } |
| 4402 | } |
| 4403 | |
| 4404 | if (simubitmap == 0) { |
| 4405 | for (i = 0; i < (bound / 4); i++) { |
| 4406 | if (candidate[i] >= 0) { |
| 4407 | for (j = i * 4; j < (i + 1) * 4 - 2; j++) |
| 4408 | result[3][j] = result[candidate[i]][j]; |
| 4409 | retval = false; |
| 4410 | } |
| 4411 | } |
| 4412 | return retval; |
| 4413 | } else if (!(simubitmap & 0x0f)) { |
| 4414 | /* path A OK */ |
| 4415 | for (i = 0; i < 4; i++) |
| 4416 | result[3][i] = result[c1][i]; |
| 4417 | } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) { |
| 4418 | /* path B OK */ |
| 4419 | for (i = 4; i < 8; i++) |
| 4420 | result[3][i] = result[c1][i]; |
| 4421 | } |
| 4422 | |
| 4423 | return false; |
| 4424 | } |
| 4425 | |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 4426 | static bool rtl8723bu_simularity_compare(struct rtl8xxxu_priv *priv, |
| 4427 | int result[][8], int c1, int c2) |
| 4428 | { |
| 4429 | u32 i, j, diff, simubitmap, bound = 0; |
| 4430 | int candidate[2] = {-1, -1}; /* for path A and path B */ |
| 4431 | int tmp1, tmp2; |
| 4432 | bool retval = true; |
| 4433 | |
| 4434 | if (priv->tx_paths > 1) |
| 4435 | bound = 8; |
| 4436 | else |
| 4437 | bound = 4; |
| 4438 | |
| 4439 | simubitmap = 0; |
| 4440 | |
| 4441 | for (i = 0; i < bound; i++) { |
| 4442 | if (i & 1) { |
| 4443 | if ((result[c1][i] & 0x00000200)) |
| 4444 | tmp1 = result[c1][i] | 0xfffffc00; |
| 4445 | else |
| 4446 | tmp1 = result[c1][i]; |
| 4447 | |
| 4448 | if ((result[c2][i]& 0x00000200)) |
| 4449 | tmp2 = result[c2][i] | 0xfffffc00; |
| 4450 | else |
| 4451 | tmp2 = result[c2][i]; |
| 4452 | } else { |
| 4453 | tmp1 = result[c1][i]; |
| 4454 | tmp2 = result[c2][i]; |
| 4455 | } |
| 4456 | |
| 4457 | diff = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1); |
| 4458 | |
| 4459 | if (diff > MAX_TOLERANCE) { |
| 4460 | if ((i == 2 || i == 6) && !simubitmap) { |
| 4461 | if (result[c1][i] + result[c1][i + 1] == 0) |
| 4462 | candidate[(i / 4)] = c2; |
| 4463 | else if (result[c2][i] + result[c2][i + 1] == 0) |
| 4464 | candidate[(i / 4)] = c1; |
| 4465 | else |
| 4466 | simubitmap = simubitmap | (1 << i); |
| 4467 | } else { |
| 4468 | simubitmap = simubitmap | (1 << i); |
| 4469 | } |
| 4470 | } |
| 4471 | } |
| 4472 | |
| 4473 | if (simubitmap == 0) { |
| 4474 | for (i = 0; i < (bound / 4); i++) { |
| 4475 | if (candidate[i] >= 0) { |
| 4476 | for (j = i * 4; j < (i + 1) * 4 - 2; j++) |
| 4477 | result[3][j] = result[candidate[i]][j]; |
| 4478 | retval = false; |
| 4479 | } |
| 4480 | } |
| 4481 | return retval; |
| 4482 | } else { |
| 4483 | if (!(simubitmap & 0x03)) { |
| 4484 | /* path A TX OK */ |
| 4485 | for (i = 0; i < 2; i++) |
| 4486 | result[3][i] = result[c1][i]; |
| 4487 | } |
| 4488 | |
| 4489 | if (!(simubitmap & 0x0c)) { |
| 4490 | /* path A RX OK */ |
| 4491 | for (i = 2; i < 4; i++) |
| 4492 | result[3][i] = result[c1][i]; |
| 4493 | } |
| 4494 | |
| 4495 | if (!(simubitmap & 0x30) && priv->tx_paths > 1) { |
| 4496 | /* path B RX OK */ |
| 4497 | for (i = 4; i < 6; i++) |
| 4498 | result[3][i] = result[c1][i]; |
| 4499 | } |
| 4500 | |
| 4501 | if (!(simubitmap & 0x30) && priv->tx_paths > 1) { |
| 4502 | /* path B RX OK */ |
| 4503 | for (i = 6; i < 8; i++) |
| 4504 | result[3][i] = result[c1][i]; |
| 4505 | } |
| 4506 | } |
| 4507 | |
| 4508 | return false; |
| 4509 | } |
| 4510 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 4511 | static void |
| 4512 | rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup) |
| 4513 | { |
| 4514 | int i; |
| 4515 | |
| 4516 | for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) |
| 4517 | backup[i] = rtl8xxxu_read8(priv, reg[i]); |
| 4518 | |
| 4519 | backup[i] = rtl8xxxu_read32(priv, reg[i]); |
| 4520 | } |
| 4521 | |
| 4522 | static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv, |
| 4523 | const u32 *reg, u32 *backup) |
| 4524 | { |
| 4525 | int i; |
| 4526 | |
| 4527 | for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++) |
| 4528 | rtl8xxxu_write8(priv, reg[i], backup[i]); |
| 4529 | |
| 4530 | rtl8xxxu_write32(priv, reg[i], backup[i]); |
| 4531 | } |
| 4532 | |
| 4533 | static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs, |
| 4534 | u32 *backup, int count) |
| 4535 | { |
| 4536 | int i; |
| 4537 | |
| 4538 | for (i = 0; i < count; i++) |
| 4539 | backup[i] = rtl8xxxu_read32(priv, regs[i]); |
| 4540 | } |
| 4541 | |
| 4542 | static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs, |
| 4543 | u32 *backup, int count) |
| 4544 | { |
| 4545 | int i; |
| 4546 | |
| 4547 | for (i = 0; i < count; i++) |
| 4548 | rtl8xxxu_write32(priv, regs[i], backup[i]); |
| 4549 | } |
| 4550 | |
| 4551 | |
| 4552 | static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs, |
| 4553 | bool path_a_on) |
| 4554 | { |
| 4555 | u32 path_on; |
| 4556 | int i; |
| 4557 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 4558 | if (priv->tx_paths == 1) { |
Jes Sorensen | 8634af5 | 2016-02-29 17:04:33 -0500 | [diff] [blame] | 4559 | path_on = priv->fops->adda_1t_path_on; |
| 4560 | rtl8xxxu_write32(priv, regs[0], priv->fops->adda_1t_init); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 4561 | } else { |
Jes Sorensen | 8634af5 | 2016-02-29 17:04:33 -0500 | [diff] [blame] | 4562 | path_on = path_a_on ? priv->fops->adda_2t_path_on_a : |
| 4563 | priv->fops->adda_2t_path_on_b; |
| 4564 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 4565 | rtl8xxxu_write32(priv, regs[0], path_on); |
| 4566 | } |
| 4567 | |
| 4568 | for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++) |
| 4569 | rtl8xxxu_write32(priv, regs[i], path_on); |
| 4570 | } |
| 4571 | |
| 4572 | static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv, |
| 4573 | const u32 *regs, u32 *backup) |
| 4574 | { |
| 4575 | int i = 0; |
| 4576 | |
| 4577 | rtl8xxxu_write8(priv, regs[i], 0x3f); |
| 4578 | |
| 4579 | for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++) |
| 4580 | rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3))); |
| 4581 | |
| 4582 | rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5))); |
| 4583 | } |
| 4584 | |
| 4585 | static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv) |
| 4586 | { |
| 4587 | u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32; |
| 4588 | int result = 0; |
| 4589 | |
| 4590 | /* path-A IQK setting */ |
| 4591 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f); |
| 4592 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f); |
| 4593 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102); |
| 4594 | |
| 4595 | val32 = (priv->rf_paths > 1) ? 0x28160202 : |
| 4596 | /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */ |
| 4597 | 0x28160502; |
| 4598 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32); |
| 4599 | |
| 4600 | /* path-B IQK setting */ |
| 4601 | if (priv->rf_paths > 1) { |
| 4602 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22); |
| 4603 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22); |
| 4604 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102); |
| 4605 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202); |
| 4606 | } |
| 4607 | |
| 4608 | /* LO calibration setting */ |
| 4609 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1); |
| 4610 | |
| 4611 | /* One shot, path A LOK & IQK */ |
| 4612 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); |
| 4613 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 4614 | |
| 4615 | mdelay(1); |
| 4616 | |
| 4617 | /* Check failed */ |
| 4618 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 4619 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
| 4620 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
| 4621 | reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); |
| 4622 | |
| 4623 | if (!(reg_eac & BIT(28)) && |
| 4624 | ((reg_e94 & 0x03ff0000) != 0x01420000) && |
| 4625 | ((reg_e9c & 0x03ff0000) != 0x00420000)) |
| 4626 | result |= 0x01; |
| 4627 | else /* If TX not OK, ignore RX */ |
| 4628 | goto out; |
| 4629 | |
| 4630 | /* If TX is OK, check whether RX is OK */ |
| 4631 | if (!(reg_eac & BIT(27)) && |
| 4632 | ((reg_ea4 & 0x03ff0000) != 0x01320000) && |
| 4633 | ((reg_eac & 0x03ff0000) != 0x00360000)) |
| 4634 | result |= 0x02; |
| 4635 | else |
| 4636 | dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", |
| 4637 | __func__); |
| 4638 | out: |
| 4639 | return result; |
| 4640 | } |
| 4641 | |
| 4642 | static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv) |
| 4643 | { |
| 4644 | u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc; |
| 4645 | int result = 0; |
| 4646 | |
| 4647 | /* One shot, path B LOK & IQK */ |
| 4648 | rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002); |
| 4649 | rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000); |
| 4650 | |
| 4651 | mdelay(1); |
| 4652 | |
| 4653 | /* Check failed */ |
| 4654 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 4655 | reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
| 4656 | reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
| 4657 | reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); |
| 4658 | reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); |
| 4659 | |
| 4660 | if (!(reg_eac & BIT(31)) && |
| 4661 | ((reg_eb4 & 0x03ff0000) != 0x01420000) && |
| 4662 | ((reg_ebc & 0x03ff0000) != 0x00420000)) |
| 4663 | result |= 0x01; |
| 4664 | else |
| 4665 | goto out; |
| 4666 | |
| 4667 | if (!(reg_eac & BIT(30)) && |
| 4668 | (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) && |
| 4669 | (((reg_ecc & 0x03ff0000) >> 16) != 0x36)) |
| 4670 | result |= 0x02; |
| 4671 | else |
| 4672 | dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", |
| 4673 | __func__); |
| 4674 | out: |
| 4675 | return result; |
| 4676 | } |
| 4677 | |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 4678 | static int rtl8723bu_iqk_path_a(struct rtl8xxxu_priv *priv) |
| 4679 | { |
| 4680 | u32 reg_eac, reg_e94, reg_e9c, path_sel, val32; |
| 4681 | int result = 0; |
| 4682 | |
| 4683 | path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); |
| 4684 | |
| 4685 | /* |
| 4686 | * Leave IQK mode |
| 4687 | */ |
| 4688 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 4689 | val32 &= 0x000000ff; |
| 4690 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 4691 | |
| 4692 | /* |
| 4693 | * Enable path A PA in TX IQK mode |
| 4694 | */ |
| 4695 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); |
| 4696 | val32 |= 0x80000; |
| 4697 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); |
| 4698 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x20000); |
| 4699 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0003f); |
| 4700 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xc7f87); |
| 4701 | |
| 4702 | /* |
| 4703 | * Tx IQK setting |
| 4704 | */ |
| 4705 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); |
| 4706 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 4707 | |
| 4708 | /* path-A IQK setting */ |
| 4709 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); |
| 4710 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); |
| 4711 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); |
| 4712 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); |
| 4713 | |
| 4714 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x821403ea); |
| 4715 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); |
| 4716 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); |
| 4717 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); |
| 4718 | |
| 4719 | /* LO calibration setting */ |
| 4720 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); |
| 4721 | |
| 4722 | /* |
| 4723 | * Enter IQK mode |
| 4724 | */ |
| 4725 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 4726 | val32 &= 0x000000ff; |
| 4727 | val32 |= 0x80800000; |
| 4728 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 4729 | |
| 4730 | /* |
| 4731 | * The vendor driver indicates the USB module is always using |
| 4732 | * S0S1 path 1 for the 8723bu. This may be different for 8192eu |
| 4733 | */ |
| 4734 | if (priv->rf_paths > 1) |
| 4735 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); |
| 4736 | else |
| 4737 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); |
| 4738 | |
| 4739 | /* |
| 4740 | * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. |
| 4741 | * No trace of this in the 8192eu or 8188eu vendor drivers. |
| 4742 | */ |
| 4743 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); |
| 4744 | |
| 4745 | /* One shot, path A LOK & IQK */ |
| 4746 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); |
| 4747 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 4748 | |
| 4749 | mdelay(1); |
| 4750 | |
| 4751 | /* Restore Ant Path */ |
| 4752 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); |
| 4753 | #ifdef RTL8723BU_BT |
| 4754 | /* GNT_BT = 1 */ |
| 4755 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); |
| 4756 | #endif |
| 4757 | |
| 4758 | /* |
| 4759 | * Leave IQK mode |
| 4760 | */ |
| 4761 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 4762 | val32 &= 0x000000ff; |
| 4763 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 4764 | |
| 4765 | /* Check failed */ |
| 4766 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 4767 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
| 4768 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
| 4769 | |
| 4770 | val32 = (reg_e9c >> 16) & 0x3ff; |
| 4771 | if (val32 & 0x200) |
| 4772 | val32 = 0x400 - val32; |
| 4773 | |
| 4774 | if (!(reg_eac & BIT(28)) && |
| 4775 | ((reg_e94 & 0x03ff0000) != 0x01420000) && |
| 4776 | ((reg_e9c & 0x03ff0000) != 0x00420000) && |
| 4777 | ((reg_e94 & 0x03ff0000) < 0x01100000) && |
| 4778 | ((reg_e94 & 0x03ff0000) > 0x00f00000) && |
| 4779 | val32 < 0xf) |
| 4780 | result |= 0x01; |
| 4781 | else /* If TX not OK, ignore RX */ |
| 4782 | goto out; |
| 4783 | |
| 4784 | out: |
| 4785 | return result; |
| 4786 | } |
| 4787 | |
| 4788 | static int rtl8723bu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) |
| 4789 | { |
| 4790 | u32 reg_ea4, reg_eac, reg_e94, reg_e9c, path_sel, val32; |
| 4791 | int result = 0; |
| 4792 | |
| 4793 | path_sel = rtl8xxxu_read32(priv, REG_S0S1_PATH_SWITCH); |
| 4794 | |
| 4795 | /* |
| 4796 | * Leave IQK mode |
| 4797 | */ |
| 4798 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 4799 | val32 &= 0x000000ff; |
| 4800 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 4801 | |
| 4802 | /* |
| 4803 | * Enable path A PA in TX IQK mode |
| 4804 | */ |
| 4805 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); |
| 4806 | val32 |= 0x80000; |
| 4807 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); |
| 4808 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); |
| 4809 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); |
| 4810 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); |
| 4811 | |
| 4812 | /* |
| 4813 | * Tx IQK setting |
| 4814 | */ |
| 4815 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); |
| 4816 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 4817 | |
| 4818 | /* path-A IQK setting */ |
| 4819 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); |
| 4820 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); |
| 4821 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); |
| 4822 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); |
| 4823 | |
| 4824 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160ff0); |
| 4825 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28110000); |
| 4826 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); |
| 4827 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); |
| 4828 | |
| 4829 | /* LO calibration setting */ |
| 4830 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); |
| 4831 | |
| 4832 | /* |
| 4833 | * Enter IQK mode |
| 4834 | */ |
| 4835 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 4836 | val32 &= 0x000000ff; |
| 4837 | val32 |= 0x80800000; |
| 4838 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 4839 | |
| 4840 | /* |
| 4841 | * The vendor driver indicates the USB module is always using |
| 4842 | * S0S1 path 1 for the 8723bu. This may be different for 8192eu |
| 4843 | */ |
| 4844 | if (priv->rf_paths > 1) |
| 4845 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); |
| 4846 | else |
| 4847 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); |
| 4848 | |
| 4849 | /* |
| 4850 | * Bit 12 seems to be BT_GRANT, and is only found in the 8723bu. |
| 4851 | * No trace of this in the 8192eu or 8188eu vendor drivers. |
| 4852 | */ |
| 4853 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); |
| 4854 | |
| 4855 | /* One shot, path A LOK & IQK */ |
| 4856 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); |
| 4857 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 4858 | |
| 4859 | mdelay(1); |
| 4860 | |
| 4861 | /* Restore Ant Path */ |
| 4862 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); |
| 4863 | #ifdef RTL8723BU_BT |
| 4864 | /* GNT_BT = 1 */ |
| 4865 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); |
| 4866 | #endif |
| 4867 | |
| 4868 | /* |
| 4869 | * Leave IQK mode |
| 4870 | */ |
| 4871 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 4872 | val32 &= 0x000000ff; |
| 4873 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 4874 | |
| 4875 | /* Check failed */ |
| 4876 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 4877 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
| 4878 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
| 4879 | |
| 4880 | val32 = (reg_e9c >> 16) & 0x3ff; |
| 4881 | if (val32 & 0x200) |
| 4882 | val32 = 0x400 - val32; |
| 4883 | |
| 4884 | if (!(reg_eac & BIT(28)) && |
| 4885 | ((reg_e94 & 0x03ff0000) != 0x01420000) && |
| 4886 | ((reg_e9c & 0x03ff0000) != 0x00420000) && |
| 4887 | ((reg_e94 & 0x03ff0000) < 0x01100000) && |
| 4888 | ((reg_e94 & 0x03ff0000) > 0x00f00000) && |
| 4889 | val32 < 0xf) |
| 4890 | result |= 0x01; |
| 4891 | else /* If TX not OK, ignore RX */ |
| 4892 | goto out; |
| 4893 | |
| 4894 | val32 = 0x80007c00 | (reg_e94 &0x3ff0000) | |
| 4895 | ((reg_e9c & 0x3ff0000) >> 16); |
| 4896 | rtl8xxxu_write32(priv, REG_TX_IQK, val32); |
| 4897 | |
| 4898 | /* |
| 4899 | * Modify RX IQK mode |
| 4900 | */ |
| 4901 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 4902 | val32 &= 0x000000ff; |
| 4903 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 4904 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); |
| 4905 | val32 |= 0x80000; |
| 4906 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); |
| 4907 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); |
| 4908 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); |
| 4909 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7d77); |
| 4910 | |
| 4911 | /* |
| 4912 | * PA, PAD setting |
| 4913 | */ |
| 4914 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0xf80); |
| 4915 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_55, 0x4021f); |
| 4916 | |
| 4917 | /* |
| 4918 | * RX IQK setting |
| 4919 | */ |
| 4920 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 4921 | |
| 4922 | /* path-A IQK setting */ |
| 4923 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); |
| 4924 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); |
| 4925 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); |
| 4926 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); |
| 4927 | |
| 4928 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82110000); |
| 4929 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x2816001f); |
| 4930 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82110000); |
| 4931 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28110000); |
| 4932 | |
| 4933 | /* LO calibration setting */ |
| 4934 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a8d1); |
| 4935 | |
| 4936 | /* |
| 4937 | * Enter IQK mode |
| 4938 | */ |
| 4939 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 4940 | val32 &= 0x000000ff; |
| 4941 | val32 |= 0x80800000; |
| 4942 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 4943 | |
| 4944 | if (priv->rf_paths > 1) |
| 4945 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000000); |
| 4946 | else |
| 4947 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00000280); |
| 4948 | |
| 4949 | /* |
| 4950 | * Disable BT |
| 4951 | */ |
| 4952 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00000800); |
| 4953 | |
| 4954 | /* One shot, path A LOK & IQK */ |
| 4955 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); |
| 4956 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 4957 | |
| 4958 | mdelay(1); |
| 4959 | |
| 4960 | /* Restore Ant Path */ |
| 4961 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, path_sel); |
| 4962 | #ifdef RTL8723BU_BT |
| 4963 | /* GNT_BT = 1 */ |
| 4964 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, 0x00001800); |
| 4965 | #endif |
| 4966 | |
| 4967 | /* |
| 4968 | * Leave IQK mode |
| 4969 | */ |
| 4970 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 4971 | val32 &= 0x000000ff; |
| 4972 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 4973 | |
| 4974 | /* Check failed */ |
| 4975 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 4976 | reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); |
| 4977 | |
| 4978 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x780); |
| 4979 | |
| 4980 | val32 = (reg_eac >> 16) & 0x3ff; |
| 4981 | if (val32 & 0x200) |
| 4982 | val32 = 0x400 - val32; |
| 4983 | |
| 4984 | if (!(reg_eac & BIT(27)) && |
| 4985 | ((reg_ea4 & 0x03ff0000) != 0x01320000) && |
| 4986 | ((reg_eac & 0x03ff0000) != 0x00360000) && |
| 4987 | ((reg_ea4 & 0x03ff0000) < 0x01100000) && |
| 4988 | ((reg_ea4 & 0x03ff0000) > 0x00f00000) && |
| 4989 | val32 < 0xf) |
| 4990 | result |= 0x02; |
| 4991 | else /* If TX not OK, ignore RX */ |
| 4992 | goto out; |
| 4993 | out: |
| 4994 | return result; |
| 4995 | } |
| 4996 | |
Jes Sorensen | f991f4e | 2016-04-07 14:19:32 -0400 | [diff] [blame] | 4997 | static int rtl8192eu_iqk_path_a(struct rtl8xxxu_priv *priv) |
| 4998 | { |
| 4999 | u32 reg_eac, reg_e94, reg_e9c; |
| 5000 | int result = 0; |
| 5001 | |
| 5002 | /* |
| 5003 | * TX IQK |
| 5004 | * PA/PAD controlled by 0x0 |
| 5005 | */ |
| 5006 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); |
| 5007 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00180); |
| 5008 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 5009 | |
| 5010 | /* Path A IQK setting */ |
| 5011 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); |
| 5012 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); |
| 5013 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); |
| 5014 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); |
| 5015 | |
| 5016 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140303); |
| 5017 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160000); |
| 5018 | |
| 5019 | /* LO calibration setting */ |
| 5020 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00462911); |
| 5021 | |
| 5022 | /* One shot, path A LOK & IQK */ |
| 5023 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000); |
| 5024 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 5025 | |
| 5026 | mdelay(10); |
| 5027 | |
| 5028 | /* Check failed */ |
| 5029 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 5030 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
| 5031 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
| 5032 | |
| 5033 | if (!(reg_eac & BIT(28)) && |
| 5034 | ((reg_e94 & 0x03ff0000) != 0x01420000) && |
| 5035 | ((reg_e9c & 0x03ff0000) != 0x00420000)) |
| 5036 | result |= 0x01; |
| 5037 | |
| 5038 | return result; |
| 5039 | } |
| 5040 | |
| 5041 | static int rtl8192eu_rx_iqk_path_a(struct rtl8xxxu_priv *priv) |
| 5042 | { |
| 5043 | u32 reg_ea4, reg_eac, reg_e94, reg_e9c, val32; |
| 5044 | int result = 0; |
| 5045 | |
| 5046 | /* Leave IQK mode */ |
| 5047 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00); |
| 5048 | |
| 5049 | /* Enable path A PA in TX IQK mode */ |
| 5050 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); |
| 5051 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); |
| 5052 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); |
| 5053 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf117b); |
| 5054 | |
| 5055 | /* PA/PAD control by 0x56, and set = 0x0 */ |
| 5056 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980); |
| 5057 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); |
| 5058 | |
| 5059 | /* Enter IQK mode */ |
| 5060 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 5061 | |
| 5062 | /* TX IQK setting */ |
| 5063 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); |
| 5064 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 5065 | |
| 5066 | /* path-A IQK setting */ |
| 5067 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x18008c1c); |
| 5068 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); |
| 5069 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); |
| 5070 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); |
| 5071 | |
| 5072 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); |
| 5073 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x68160c1f); |
| 5074 | |
| 5075 | /* LO calibration setting */ |
| 5076 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); |
| 5077 | |
| 5078 | /* One shot, path A LOK & IQK */ |
| 5079 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); |
| 5080 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 5081 | |
| 5082 | mdelay(10); |
| 5083 | |
| 5084 | /* Check failed */ |
| 5085 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 5086 | reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A); |
| 5087 | reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A); |
| 5088 | |
| 5089 | if (!(reg_eac & BIT(28)) && |
| 5090 | ((reg_e94 & 0x03ff0000) != 0x01420000) && |
| 5091 | ((reg_e9c & 0x03ff0000) != 0x00420000)) { |
| 5092 | result |= 0x01; |
| 5093 | } else { |
| 5094 | /* PA/PAD controlled by 0x0 */ |
| 5095 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); |
| 5096 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); |
| 5097 | goto out; |
| 5098 | } |
| 5099 | |
| 5100 | val32 = 0x80007c00 | |
| 5101 | (reg_e94 & 0x03ff0000) | ((reg_e9c >> 16) & 0x03ff); |
| 5102 | rtl8xxxu_write32(priv, REG_TX_IQK, val32); |
| 5103 | |
| 5104 | /* Modify RX IQK mode table */ |
| 5105 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); |
| 5106 | |
| 5107 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, 0x800a0); |
| 5108 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); |
| 5109 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0000f); |
| 5110 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7ffa); |
| 5111 | |
| 5112 | /* PA/PAD control by 0x56, and set = 0x0 */ |
| 5113 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x00980); |
| 5114 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_56, 0x51000); |
| 5115 | |
| 5116 | /* Enter IQK mode */ |
| 5117 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 5118 | |
| 5119 | /* IQK setting */ |
| 5120 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 5121 | |
| 5122 | /* Path A IQK setting */ |
| 5123 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); |
| 5124 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x18008c1c); |
| 5125 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); |
| 5126 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); |
| 5127 | |
| 5128 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); |
| 5129 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f); |
| 5130 | |
| 5131 | /* LO calibration setting */ |
| 5132 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); |
| 5133 | |
| 5134 | /* One shot, path A LOK & IQK */ |
| 5135 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); |
| 5136 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 5137 | |
| 5138 | mdelay(10); |
| 5139 | |
| 5140 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 5141 | reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2); |
| 5142 | |
| 5143 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); |
| 5144 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_DF, 0x180); |
| 5145 | |
| 5146 | if (!(reg_eac & BIT(27)) && |
| 5147 | ((reg_ea4 & 0x03ff0000) != 0x01320000) && |
| 5148 | ((reg_eac & 0x03ff0000) != 0x00360000)) |
| 5149 | result |= 0x02; |
| 5150 | else |
| 5151 | dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n", |
| 5152 | __func__); |
| 5153 | |
| 5154 | out: |
| 5155 | return result; |
| 5156 | } |
| 5157 | |
| 5158 | static int rtl8192eu_iqk_path_b(struct rtl8xxxu_priv *priv) |
| 5159 | { |
| 5160 | u32 reg_eac, reg_eb4, reg_ebc; |
| 5161 | int result = 0; |
| 5162 | |
| 5163 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); |
| 5164 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00180); |
| 5165 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 5166 | |
| 5167 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); |
| 5168 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 5169 | |
| 5170 | /* Path B IQK setting */ |
| 5171 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); |
| 5172 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); |
| 5173 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); |
| 5174 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); |
| 5175 | |
| 5176 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x821403e2); |
| 5177 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160000); |
| 5178 | |
| 5179 | /* LO calibration setting */ |
| 5180 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x00492911); |
| 5181 | |
| 5182 | /* One shot, path A LOK & IQK */ |
| 5183 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); |
| 5184 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 5185 | |
| 5186 | mdelay(1); |
| 5187 | |
| 5188 | /* Check failed */ |
| 5189 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 5190 | reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
| 5191 | reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
| 5192 | |
| 5193 | if (!(reg_eac & BIT(31)) && |
| 5194 | ((reg_eb4 & 0x03ff0000) != 0x01420000) && |
| 5195 | ((reg_ebc & 0x03ff0000) != 0x00420000)) |
| 5196 | result |= 0x01; |
| 5197 | else |
| 5198 | dev_warn(&priv->udev->dev, "%s: Path B IQK failed!\n", |
| 5199 | __func__); |
| 5200 | |
| 5201 | return result; |
| 5202 | } |
| 5203 | |
| 5204 | static int rtl8192eu_rx_iqk_path_b(struct rtl8xxxu_priv *priv) |
| 5205 | { |
| 5206 | u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc, val32; |
| 5207 | int result = 0; |
| 5208 | |
| 5209 | /* Leave IQK mode */ |
| 5210 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); |
| 5211 | |
| 5212 | /* Enable path A PA in TX IQK mode */ |
| 5213 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); |
| 5214 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); |
| 5215 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); |
| 5216 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf117b); |
| 5217 | |
| 5218 | /* PA/PAD control by 0x56, and set = 0x0 */ |
| 5219 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980); |
| 5220 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000); |
| 5221 | |
| 5222 | /* Enter IQK mode */ |
| 5223 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 5224 | |
| 5225 | /* TX IQK setting */ |
| 5226 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); |
| 5227 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 5228 | |
| 5229 | /* path-A IQK setting */ |
| 5230 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); |
| 5231 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); |
| 5232 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x18008c1c); |
| 5233 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x38008c1c); |
| 5234 | |
| 5235 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82160c1f); |
| 5236 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x68160c1f); |
| 5237 | |
| 5238 | /* LO calibration setting */ |
| 5239 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a911); |
| 5240 | |
| 5241 | /* One shot, path A LOK & IQK */ |
| 5242 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); |
| 5243 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 5244 | |
| 5245 | mdelay(10); |
| 5246 | |
| 5247 | /* Check failed */ |
| 5248 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 5249 | reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
| 5250 | reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
| 5251 | |
| 5252 | if (!(reg_eac & BIT(31)) && |
| 5253 | ((reg_eb4 & 0x03ff0000) != 0x01420000) && |
| 5254 | ((reg_ebc & 0x03ff0000) != 0x00420000)) { |
| 5255 | result |= 0x01; |
| 5256 | } else { |
| 5257 | /* |
| 5258 | * PA/PAD controlled by 0x0 |
| 5259 | * Vendor driver restores RF_A here which I believe is a bug |
| 5260 | */ |
| 5261 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); |
| 5262 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180); |
| 5263 | goto out; |
| 5264 | } |
| 5265 | |
| 5266 | val32 = 0x80007c00 | |
| 5267 | (reg_eb4 & 0x03ff0000) | ((reg_ebc >> 16) & 0x03ff); |
| 5268 | rtl8xxxu_write32(priv, REG_TX_IQK, val32); |
| 5269 | |
| 5270 | /* Modify RX IQK mode table */ |
| 5271 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); |
| 5272 | |
| 5273 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_WE_LUT, 0x800a0); |
| 5274 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_RCK_OS, 0x30000); |
| 5275 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G1, 0x0000f); |
| 5276 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_TXPA_G2, 0xf7ffa); |
| 5277 | |
| 5278 | /* PA/PAD control by 0x56, and set = 0x0 */ |
| 5279 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x00980); |
| 5280 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_56, 0x51000); |
| 5281 | |
| 5282 | /* Enter IQK mode */ |
| 5283 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 5284 | |
| 5285 | /* IQK setting */ |
| 5286 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 5287 | |
| 5288 | /* Path A IQK setting */ |
| 5289 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x38008c1c); |
| 5290 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x38008c1c); |
| 5291 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x38008c1c); |
| 5292 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x18008c1c); |
| 5293 | |
| 5294 | rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82160c1f); |
| 5295 | rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, 0x28160c1f); |
| 5296 | |
| 5297 | /* LO calibration setting */ |
| 5298 | rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x0046a891); |
| 5299 | |
| 5300 | /* One shot, path A LOK & IQK */ |
| 5301 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xfa000000); |
| 5302 | rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000); |
| 5303 | |
| 5304 | mdelay(10); |
| 5305 | |
| 5306 | reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2); |
| 5307 | reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); |
| 5308 | reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); |
| 5309 | |
| 5310 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); |
| 5311 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_UNKNOWN_DF, 0x180); |
| 5312 | |
| 5313 | if (!(reg_eac & BIT(30)) && |
| 5314 | ((reg_ec4 & 0x03ff0000) != 0x01320000) && |
| 5315 | ((reg_ecc & 0x03ff0000) != 0x00360000)) |
| 5316 | result |= 0x02; |
| 5317 | else |
| 5318 | dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n", |
| 5319 | __func__); |
| 5320 | |
| 5321 | out: |
| 5322 | return result; |
| 5323 | } |
| 5324 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 5325 | static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, |
| 5326 | int result[][8], int t) |
| 5327 | { |
| 5328 | struct device *dev = &priv->udev->dev; |
| 5329 | u32 i, val32; |
| 5330 | int path_a_ok, path_b_ok; |
| 5331 | int retry = 2; |
| 5332 | const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { |
| 5333 | REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, |
| 5334 | REG_RX_WAIT_CCA, REG_TX_CCK_RFON, |
| 5335 | REG_TX_CCK_BBON, REG_TX_OFDM_RFON, |
| 5336 | REG_TX_OFDM_BBON, REG_TX_TO_RX, |
| 5337 | REG_TX_TO_TX, REG_RX_CCK, |
| 5338 | REG_RX_OFDM, REG_RX_WAIT_RIFS, |
| 5339 | REG_RX_TO_RX, REG_STANDBY, |
| 5340 | REG_SLEEP, REG_PMPD_ANAEN |
| 5341 | }; |
| 5342 | const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { |
| 5343 | REG_TXPAUSE, REG_BEACON_CTRL, |
| 5344 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG |
| 5345 | }; |
| 5346 | const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { |
| 5347 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, |
| 5348 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, |
| 5349 | REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, |
| 5350 | REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE |
| 5351 | }; |
| 5352 | |
| 5353 | /* |
| 5354 | * Note: IQ calibration must be performed after loading |
| 5355 | * PHY_REG.txt , and radio_a, radio_b.txt |
| 5356 | */ |
| 5357 | |
| 5358 | if (t == 0) { |
| 5359 | /* Save ADDA parameters, turn Path A ADDA on */ |
| 5360 | rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, |
| 5361 | RTL8XXXU_ADDA_REGS); |
| 5362 | rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); |
| 5363 | rtl8xxxu_save_regs(priv, iqk_bb_regs, |
| 5364 | priv->bb_backup, RTL8XXXU_BB_REGS); |
| 5365 | } |
| 5366 | |
| 5367 | rtl8xxxu_path_adda_on(priv, adda_regs, true); |
| 5368 | |
| 5369 | if (t == 0) { |
| 5370 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1); |
| 5371 | if (val32 & FPGA0_HSSI_PARM1_PI) |
| 5372 | priv->pi_enabled = 1; |
| 5373 | } |
| 5374 | |
| 5375 | if (!priv->pi_enabled) { |
| 5376 | /* Switch BB to PI mode to do IQ Calibration. */ |
| 5377 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100); |
| 5378 | rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100); |
| 5379 | } |
| 5380 | |
| 5381 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 5382 | val32 &= ~FPGA_RF_MODE_CCK; |
| 5383 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 5384 | |
| 5385 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); |
| 5386 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); |
| 5387 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); |
| 5388 | |
| 5389 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); |
| 5390 | val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); |
| 5391 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); |
| 5392 | |
| 5393 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); |
| 5394 | val32 &= ~BIT(10); |
| 5395 | rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); |
| 5396 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); |
| 5397 | val32 &= ~BIT(10); |
| 5398 | rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); |
| 5399 | |
| 5400 | if (priv->tx_paths > 1) { |
| 5401 | rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); |
| 5402 | rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000); |
| 5403 | } |
| 5404 | |
| 5405 | /* MAC settings */ |
| 5406 | rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); |
| 5407 | |
| 5408 | /* Page B init */ |
| 5409 | rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000); |
| 5410 | |
| 5411 | if (priv->tx_paths > 1) |
| 5412 | rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000); |
| 5413 | |
| 5414 | /* IQ calibration setting */ |
| 5415 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 5416 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); |
| 5417 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 5418 | |
| 5419 | for (i = 0; i < retry; i++) { |
| 5420 | path_a_ok = rtl8xxxu_iqk_path_a(priv); |
| 5421 | if (path_a_ok == 0x03) { |
| 5422 | val32 = rtl8xxxu_read32(priv, |
| 5423 | REG_TX_POWER_BEFORE_IQK_A); |
| 5424 | result[t][0] = (val32 >> 16) & 0x3ff; |
| 5425 | val32 = rtl8xxxu_read32(priv, |
| 5426 | REG_TX_POWER_AFTER_IQK_A); |
| 5427 | result[t][1] = (val32 >> 16) & 0x3ff; |
| 5428 | val32 = rtl8xxxu_read32(priv, |
| 5429 | REG_RX_POWER_BEFORE_IQK_A_2); |
| 5430 | result[t][2] = (val32 >> 16) & 0x3ff; |
| 5431 | val32 = rtl8xxxu_read32(priv, |
| 5432 | REG_RX_POWER_AFTER_IQK_A_2); |
| 5433 | result[t][3] = (val32 >> 16) & 0x3ff; |
| 5434 | break; |
| 5435 | } else if (i == (retry - 1) && path_a_ok == 0x01) { |
| 5436 | /* TX IQK OK */ |
| 5437 | dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n", |
| 5438 | __func__); |
| 5439 | |
| 5440 | val32 = rtl8xxxu_read32(priv, |
| 5441 | REG_TX_POWER_BEFORE_IQK_A); |
| 5442 | result[t][0] = (val32 >> 16) & 0x3ff; |
| 5443 | val32 = rtl8xxxu_read32(priv, |
| 5444 | REG_TX_POWER_AFTER_IQK_A); |
| 5445 | result[t][1] = (val32 >> 16) & 0x3ff; |
| 5446 | } |
| 5447 | } |
| 5448 | |
| 5449 | if (!path_a_ok) |
| 5450 | dev_dbg(dev, "%s: Path A IQK failed!\n", __func__); |
| 5451 | |
| 5452 | if (priv->tx_paths > 1) { |
| 5453 | /* |
| 5454 | * Path A into standby |
| 5455 | */ |
| 5456 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0); |
| 5457 | rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000); |
| 5458 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 5459 | |
| 5460 | /* Turn Path B ADDA on */ |
| 5461 | rtl8xxxu_path_adda_on(priv, adda_regs, false); |
| 5462 | |
| 5463 | for (i = 0; i < retry; i++) { |
| 5464 | path_b_ok = rtl8xxxu_iqk_path_b(priv); |
| 5465 | if (path_b_ok == 0x03) { |
| 5466 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
| 5467 | result[t][4] = (val32 >> 16) & 0x3ff; |
| 5468 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
| 5469 | result[t][5] = (val32 >> 16) & 0x3ff; |
| 5470 | val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2); |
| 5471 | result[t][6] = (val32 >> 16) & 0x3ff; |
| 5472 | val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2); |
| 5473 | result[t][7] = (val32 >> 16) & 0x3ff; |
| 5474 | break; |
| 5475 | } else if (i == (retry - 1) && path_b_ok == 0x01) { |
| 5476 | /* TX IQK OK */ |
| 5477 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
| 5478 | result[t][4] = (val32 >> 16) & 0x3ff; |
| 5479 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
| 5480 | result[t][5] = (val32 >> 16) & 0x3ff; |
| 5481 | } |
| 5482 | } |
| 5483 | |
| 5484 | if (!path_b_ok) |
| 5485 | dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); |
| 5486 | } |
| 5487 | |
| 5488 | /* Back to BB mode, load original value */ |
| 5489 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0); |
| 5490 | |
| 5491 | if (t) { |
| 5492 | if (!priv->pi_enabled) { |
| 5493 | /* |
| 5494 | * Switch back BB to SI mode after finishing |
| 5495 | * IQ Calibration |
| 5496 | */ |
| 5497 | val32 = 0x01000000; |
| 5498 | rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32); |
| 5499 | rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32); |
| 5500 | } |
| 5501 | |
| 5502 | /* Reload ADDA power saving parameters */ |
| 5503 | rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, |
| 5504 | RTL8XXXU_ADDA_REGS); |
| 5505 | |
| 5506 | /* Reload MAC parameters */ |
| 5507 | rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); |
| 5508 | |
| 5509 | /* Reload BB parameters */ |
| 5510 | rtl8xxxu_restore_regs(priv, iqk_bb_regs, |
| 5511 | priv->bb_backup, RTL8XXXU_BB_REGS); |
| 5512 | |
| 5513 | /* Restore RX initial gain */ |
| 5514 | rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3); |
| 5515 | |
| 5516 | if (priv->tx_paths > 1) { |
| 5517 | rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, |
| 5518 | 0x00032ed3); |
| 5519 | } |
| 5520 | |
| 5521 | /* Load 0xe30 IQC default value */ |
| 5522 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); |
| 5523 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); |
| 5524 | } |
| 5525 | } |
| 5526 | |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 5527 | static void rtl8723bu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, |
| 5528 | int result[][8], int t) |
| 5529 | { |
| 5530 | struct device *dev = &priv->udev->dev; |
| 5531 | u32 i, val32; |
| 5532 | int path_a_ok /*, path_b_ok */; |
| 5533 | int retry = 2; |
| 5534 | const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { |
| 5535 | REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, |
| 5536 | REG_RX_WAIT_CCA, REG_TX_CCK_RFON, |
| 5537 | REG_TX_CCK_BBON, REG_TX_OFDM_RFON, |
| 5538 | REG_TX_OFDM_BBON, REG_TX_TO_RX, |
| 5539 | REG_TX_TO_TX, REG_RX_CCK, |
| 5540 | REG_RX_OFDM, REG_RX_WAIT_RIFS, |
| 5541 | REG_RX_TO_RX, REG_STANDBY, |
| 5542 | REG_SLEEP, REG_PMPD_ANAEN |
| 5543 | }; |
| 5544 | const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { |
| 5545 | REG_TXPAUSE, REG_BEACON_CTRL, |
| 5546 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG |
| 5547 | }; |
| 5548 | const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { |
| 5549 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, |
| 5550 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, |
| 5551 | REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, |
| 5552 | REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE |
| 5553 | }; |
| 5554 | u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; |
| 5555 | u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; |
| 5556 | |
| 5557 | /* |
| 5558 | * Note: IQ calibration must be performed after loading |
| 5559 | * PHY_REG.txt , and radio_a, radio_b.txt |
| 5560 | */ |
| 5561 | |
| 5562 | if (t == 0) { |
| 5563 | /* Save ADDA parameters, turn Path A ADDA on */ |
| 5564 | rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, |
| 5565 | RTL8XXXU_ADDA_REGS); |
| 5566 | rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); |
| 5567 | rtl8xxxu_save_regs(priv, iqk_bb_regs, |
| 5568 | priv->bb_backup, RTL8XXXU_BB_REGS); |
| 5569 | } |
| 5570 | |
| 5571 | rtl8xxxu_path_adda_on(priv, adda_regs, true); |
| 5572 | |
| 5573 | /* MAC settings */ |
| 5574 | rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); |
| 5575 | |
| 5576 | val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); |
| 5577 | val32 |= 0x0f000000; |
| 5578 | rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); |
| 5579 | |
| 5580 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); |
| 5581 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); |
| 5582 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000); |
| 5583 | |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 5584 | /* |
| 5585 | * RX IQ calibration setting for 8723B D cut large current issue |
| 5586 | * when leaving IPS |
| 5587 | */ |
| 5588 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 5589 | val32 &= 0x000000ff; |
| 5590 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 5591 | |
| 5592 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); |
| 5593 | val32 |= 0x80000; |
| 5594 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); |
| 5595 | |
| 5596 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x30000); |
| 5597 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); |
| 5598 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xf7fb7); |
| 5599 | |
| 5600 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); |
| 5601 | val32 |= 0x20; |
| 5602 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); |
| 5603 | |
| 5604 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_43, 0x60fbd); |
| 5605 | |
| 5606 | for (i = 0; i < retry; i++) { |
| 5607 | path_a_ok = rtl8723bu_iqk_path_a(priv); |
| 5608 | if (path_a_ok == 0x01) { |
| 5609 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 5610 | val32 &= 0x000000ff; |
| 5611 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 5612 | |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 5613 | val32 = rtl8xxxu_read32(priv, |
| 5614 | REG_TX_POWER_BEFORE_IQK_A); |
| 5615 | result[t][0] = (val32 >> 16) & 0x3ff; |
| 5616 | val32 = rtl8xxxu_read32(priv, |
| 5617 | REG_TX_POWER_AFTER_IQK_A); |
| 5618 | result[t][1] = (val32 >> 16) & 0x3ff; |
| 5619 | |
| 5620 | break; |
| 5621 | } |
| 5622 | } |
| 5623 | |
| 5624 | if (!path_a_ok) |
| 5625 | dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); |
| 5626 | |
| 5627 | for (i = 0; i < retry; i++) { |
| 5628 | path_a_ok = rtl8723bu_rx_iqk_path_a(priv); |
| 5629 | if (path_a_ok == 0x03) { |
| 5630 | val32 = rtl8xxxu_read32(priv, |
| 5631 | REG_RX_POWER_BEFORE_IQK_A_2); |
| 5632 | result[t][2] = (val32 >> 16) & 0x3ff; |
| 5633 | val32 = rtl8xxxu_read32(priv, |
| 5634 | REG_RX_POWER_AFTER_IQK_A_2); |
| 5635 | result[t][3] = (val32 >> 16) & 0x3ff; |
| 5636 | |
| 5637 | break; |
| 5638 | } |
| 5639 | } |
| 5640 | |
| 5641 | if (!path_a_ok) |
| 5642 | dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); |
| 5643 | |
| 5644 | if (priv->tx_paths > 1) { |
| 5645 | #if 1 |
| 5646 | dev_warn(dev, "%s: Path B not supported\n", __func__); |
| 5647 | #else |
| 5648 | |
| 5649 | /* |
| 5650 | * Path A into standby |
| 5651 | */ |
| 5652 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 5653 | val32 &= 0x000000ff; |
| 5654 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 5655 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); |
| 5656 | |
| 5657 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 5658 | val32 &= 0x000000ff; |
| 5659 | val32 |= 0x80800000; |
| 5660 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 5661 | |
| 5662 | /* Turn Path B ADDA on */ |
| 5663 | rtl8xxxu_path_adda_on(priv, adda_regs, false); |
| 5664 | |
| 5665 | for (i = 0; i < retry; i++) { |
| 5666 | path_b_ok = rtl8xxxu_iqk_path_b(priv); |
| 5667 | if (path_b_ok == 0x03) { |
| 5668 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
| 5669 | result[t][4] = (val32 >> 16) & 0x3ff; |
| 5670 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
| 5671 | result[t][5] = (val32 >> 16) & 0x3ff; |
| 5672 | break; |
| 5673 | } |
| 5674 | } |
| 5675 | |
| 5676 | if (!path_b_ok) |
| 5677 | dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); |
| 5678 | |
| 5679 | for (i = 0; i < retry; i++) { |
| 5680 | path_b_ok = rtl8723bu_rx_iqk_path_b(priv); |
| 5681 | if (path_a_ok == 0x03) { |
| 5682 | val32 = rtl8xxxu_read32(priv, |
| 5683 | REG_RX_POWER_BEFORE_IQK_B_2); |
| 5684 | result[t][6] = (val32 >> 16) & 0x3ff; |
| 5685 | val32 = rtl8xxxu_read32(priv, |
| 5686 | REG_RX_POWER_AFTER_IQK_B_2); |
| 5687 | result[t][7] = (val32 >> 16) & 0x3ff; |
| 5688 | break; |
| 5689 | } |
| 5690 | } |
| 5691 | |
| 5692 | if (!path_b_ok) |
| 5693 | dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__); |
| 5694 | #endif |
| 5695 | } |
| 5696 | |
| 5697 | /* Back to BB mode, load original value */ |
| 5698 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 5699 | val32 &= 0x000000ff; |
| 5700 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 5701 | |
| 5702 | if (t) { |
| 5703 | /* Reload ADDA power saving parameters */ |
| 5704 | rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, |
| 5705 | RTL8XXXU_ADDA_REGS); |
| 5706 | |
| 5707 | /* Reload MAC parameters */ |
| 5708 | rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); |
| 5709 | |
| 5710 | /* Reload BB parameters */ |
| 5711 | rtl8xxxu_restore_regs(priv, iqk_bb_regs, |
| 5712 | priv->bb_backup, RTL8XXXU_BB_REGS); |
| 5713 | |
| 5714 | /* Restore RX initial gain */ |
| 5715 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); |
| 5716 | val32 &= 0xffffff00; |
| 5717 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); |
| 5718 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); |
| 5719 | |
| 5720 | if (priv->tx_paths > 1) { |
| 5721 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); |
| 5722 | val32 &= 0xffffff00; |
| 5723 | rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, |
| 5724 | val32 | 0x50); |
| 5725 | rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, |
| 5726 | val32 | xb_agc); |
| 5727 | } |
| 5728 | |
| 5729 | /* Load 0xe30 IQC default value */ |
| 5730 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); |
| 5731 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); |
| 5732 | } |
| 5733 | } |
| 5734 | |
Jes Sorensen | f991f4e | 2016-04-07 14:19:32 -0400 | [diff] [blame] | 5735 | static void rtl8192eu_phy_iqcalibrate(struct rtl8xxxu_priv *priv, |
| 5736 | int result[][8], int t) |
| 5737 | { |
| 5738 | struct device *dev = &priv->udev->dev; |
| 5739 | u32 i, val32; |
| 5740 | int path_a_ok, path_b_ok; |
| 5741 | int retry = 2; |
| 5742 | const u32 adda_regs[RTL8XXXU_ADDA_REGS] = { |
| 5743 | REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH, |
| 5744 | REG_RX_WAIT_CCA, REG_TX_CCK_RFON, |
| 5745 | REG_TX_CCK_BBON, REG_TX_OFDM_RFON, |
| 5746 | REG_TX_OFDM_BBON, REG_TX_TO_RX, |
| 5747 | REG_TX_TO_TX, REG_RX_CCK, |
| 5748 | REG_RX_OFDM, REG_RX_WAIT_RIFS, |
| 5749 | REG_RX_TO_RX, REG_STANDBY, |
| 5750 | REG_SLEEP, REG_PMPD_ANAEN |
| 5751 | }; |
| 5752 | const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = { |
| 5753 | REG_TXPAUSE, REG_BEACON_CTRL, |
| 5754 | REG_BEACON_CTRL_1, REG_GPIO_MUXCFG |
| 5755 | }; |
| 5756 | const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = { |
| 5757 | REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR, |
| 5758 | REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B, |
| 5759 | REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE, |
| 5760 | REG_FPGA0_XB_RF_INT_OE, REG_CCK0_AFE_SETTING |
| 5761 | }; |
| 5762 | u8 xa_agc = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1) & 0xff; |
| 5763 | u8 xb_agc = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1) & 0xff; |
| 5764 | |
| 5765 | /* |
| 5766 | * Note: IQ calibration must be performed after loading |
| 5767 | * PHY_REG.txt , and radio_a, radio_b.txt |
| 5768 | */ |
| 5769 | |
| 5770 | if (t == 0) { |
| 5771 | /* Save ADDA parameters, turn Path A ADDA on */ |
| 5772 | rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup, |
| 5773 | RTL8XXXU_ADDA_REGS); |
| 5774 | rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup); |
| 5775 | rtl8xxxu_save_regs(priv, iqk_bb_regs, |
| 5776 | priv->bb_backup, RTL8XXXU_BB_REGS); |
| 5777 | } |
| 5778 | |
| 5779 | rtl8xxxu_path_adda_on(priv, adda_regs, true); |
| 5780 | |
| 5781 | /* MAC settings */ |
| 5782 | rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup); |
| 5783 | |
| 5784 | val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING); |
| 5785 | val32 |= 0x0f000000; |
| 5786 | rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32); |
| 5787 | |
| 5788 | rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600); |
| 5789 | rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4); |
| 5790 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22208200); |
| 5791 | |
| 5792 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL); |
| 5793 | val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT)); |
| 5794 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); |
| 5795 | |
| 5796 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE); |
| 5797 | val32 |= BIT(10); |
| 5798 | rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32); |
| 5799 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE); |
| 5800 | val32 |= BIT(10); |
| 5801 | rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32); |
| 5802 | |
| 5803 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 5804 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); |
| 5805 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 5806 | |
| 5807 | for (i = 0; i < retry; i++) { |
| 5808 | path_a_ok = rtl8192eu_iqk_path_a(priv); |
| 5809 | if (path_a_ok == 0x01) { |
| 5810 | val32 = rtl8xxxu_read32(priv, |
| 5811 | REG_TX_POWER_BEFORE_IQK_A); |
| 5812 | result[t][0] = (val32 >> 16) & 0x3ff; |
| 5813 | val32 = rtl8xxxu_read32(priv, |
| 5814 | REG_TX_POWER_AFTER_IQK_A); |
| 5815 | result[t][1] = (val32 >> 16) & 0x3ff; |
| 5816 | |
| 5817 | break; |
| 5818 | } |
| 5819 | } |
| 5820 | |
| 5821 | if (!path_a_ok) |
| 5822 | dev_dbg(dev, "%s: Path A TX IQK failed!\n", __func__); |
| 5823 | |
| 5824 | for (i = 0; i < retry; i++) { |
| 5825 | path_a_ok = rtl8192eu_rx_iqk_path_a(priv); |
| 5826 | if (path_a_ok == 0x03) { |
| 5827 | val32 = rtl8xxxu_read32(priv, |
| 5828 | REG_RX_POWER_BEFORE_IQK_A_2); |
| 5829 | result[t][2] = (val32 >> 16) & 0x3ff; |
| 5830 | val32 = rtl8xxxu_read32(priv, |
| 5831 | REG_RX_POWER_AFTER_IQK_A_2); |
| 5832 | result[t][3] = (val32 >> 16) & 0x3ff; |
| 5833 | |
| 5834 | break; |
| 5835 | } |
| 5836 | } |
| 5837 | |
| 5838 | if (!path_a_ok) |
| 5839 | dev_dbg(dev, "%s: Path A RX IQK failed!\n", __func__); |
| 5840 | |
| 5841 | if (priv->rf_paths > 1) { |
Jes Sorensen | f991f4e | 2016-04-07 14:19:32 -0400 | [diff] [blame] | 5842 | /* Path A into standby */ |
| 5843 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); |
| 5844 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x10000); |
| 5845 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 5846 | |
| 5847 | /* Turn Path B ADDA on */ |
| 5848 | rtl8xxxu_path_adda_on(priv, adda_regs, false); |
| 5849 | |
| 5850 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000); |
| 5851 | rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00); |
| 5852 | rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800); |
| 5853 | |
| 5854 | for (i = 0; i < retry; i++) { |
| 5855 | path_b_ok = rtl8192eu_iqk_path_b(priv); |
| 5856 | if (path_b_ok == 0x01) { |
| 5857 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B); |
| 5858 | result[t][4] = (val32 >> 16) & 0x3ff; |
| 5859 | val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B); |
| 5860 | result[t][5] = (val32 >> 16) & 0x3ff; |
| 5861 | break; |
| 5862 | } |
| 5863 | } |
| 5864 | |
| 5865 | if (!path_b_ok) |
| 5866 | dev_dbg(dev, "%s: Path B IQK failed!\n", __func__); |
| 5867 | |
| 5868 | for (i = 0; i < retry; i++) { |
| 5869 | path_b_ok = rtl8192eu_rx_iqk_path_b(priv); |
| 5870 | if (path_a_ok == 0x03) { |
| 5871 | val32 = rtl8xxxu_read32(priv, |
| 5872 | REG_RX_POWER_BEFORE_IQK_B_2); |
| 5873 | result[t][6] = (val32 >> 16) & 0x3ff; |
| 5874 | val32 = rtl8xxxu_read32(priv, |
| 5875 | REG_RX_POWER_AFTER_IQK_B_2); |
| 5876 | result[t][7] = (val32 >> 16) & 0x3ff; |
| 5877 | break; |
| 5878 | } |
| 5879 | } |
| 5880 | |
| 5881 | if (!path_b_ok) |
| 5882 | dev_dbg(dev, "%s: Path B RX IQK failed!\n", __func__); |
| 5883 | } |
| 5884 | |
| 5885 | /* Back to BB mode, load original value */ |
| 5886 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x00000000); |
| 5887 | |
| 5888 | if (t) { |
| 5889 | /* Reload ADDA power saving parameters */ |
| 5890 | rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup, |
| 5891 | RTL8XXXU_ADDA_REGS); |
| 5892 | |
| 5893 | /* Reload MAC parameters */ |
| 5894 | rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup); |
| 5895 | |
| 5896 | /* Reload BB parameters */ |
| 5897 | rtl8xxxu_restore_regs(priv, iqk_bb_regs, |
| 5898 | priv->bb_backup, RTL8XXXU_BB_REGS); |
| 5899 | |
| 5900 | /* Restore RX initial gain */ |
| 5901 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1); |
| 5902 | val32 &= 0xffffff00; |
| 5903 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | 0x50); |
| 5904 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, val32 | xa_agc); |
| 5905 | |
| 5906 | if (priv->rf_paths > 1) { |
| 5907 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_AGC_CORE1); |
| 5908 | val32 &= 0xffffff00; |
| 5909 | rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, |
| 5910 | val32 | 0x50); |
| 5911 | rtl8xxxu_write32(priv, REG_OFDM0_XB_AGC_CORE1, |
| 5912 | val32 | xb_agc); |
| 5913 | } |
| 5914 | |
| 5915 | /* Load 0xe30 IQC default value */ |
| 5916 | rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00); |
| 5917 | rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00); |
| 5918 | } |
| 5919 | } |
| 5920 | |
Jes Sorensen | c7a5a19 | 2016-02-29 17:04:30 -0500 | [diff] [blame] | 5921 | static void rtl8xxxu_prepare_calibrate(struct rtl8xxxu_priv *priv, u8 start) |
| 5922 | { |
| 5923 | struct h2c_cmd h2c; |
| 5924 | |
| 5925 | if (priv->fops->mbox_ext_width < 4) |
| 5926 | return; |
| 5927 | |
| 5928 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 5929 | h2c.bt_wlan_calibration.cmd = H2C_8723B_BT_WLAN_CALIBRATION; |
| 5930 | h2c.bt_wlan_calibration.data = start; |
| 5931 | |
| 5932 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_wlan_calibration)); |
| 5933 | } |
| 5934 | |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 5935 | static void rtl8723au_phy_iq_calibrate(struct rtl8xxxu_priv *priv) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 5936 | { |
| 5937 | struct device *dev = &priv->udev->dev; |
| 5938 | int result[4][8]; /* last is final result */ |
| 5939 | int i, candidate; |
| 5940 | bool path_a_ok, path_b_ok; |
| 5941 | u32 reg_e94, reg_e9c, reg_ea4, reg_eac; |
| 5942 | u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; |
| 5943 | s32 reg_tmp = 0; |
| 5944 | bool simu; |
| 5945 | |
Jes Sorensen | c7a5a19 | 2016-02-29 17:04:30 -0500 | [diff] [blame] | 5946 | rtl8xxxu_prepare_calibrate(priv, 1); |
| 5947 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 5948 | memset(result, 0, sizeof(result)); |
| 5949 | candidate = -1; |
| 5950 | |
| 5951 | path_a_ok = false; |
| 5952 | path_b_ok = false; |
| 5953 | |
| 5954 | rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 5955 | |
| 5956 | for (i = 0; i < 3; i++) { |
| 5957 | rtl8xxxu_phy_iqcalibrate(priv, result, i); |
| 5958 | |
| 5959 | if (i == 1) { |
| 5960 | simu = rtl8xxxu_simularity_compare(priv, result, 0, 1); |
| 5961 | if (simu) { |
| 5962 | candidate = 0; |
| 5963 | break; |
| 5964 | } |
| 5965 | } |
| 5966 | |
| 5967 | if (i == 2) { |
| 5968 | simu = rtl8xxxu_simularity_compare(priv, result, 0, 2); |
| 5969 | if (simu) { |
| 5970 | candidate = 0; |
| 5971 | break; |
| 5972 | } |
| 5973 | |
| 5974 | simu = rtl8xxxu_simularity_compare(priv, result, 1, 2); |
| 5975 | if (simu) { |
| 5976 | candidate = 1; |
| 5977 | } else { |
| 5978 | for (i = 0; i < 8; i++) |
| 5979 | reg_tmp += result[3][i]; |
| 5980 | |
| 5981 | if (reg_tmp) |
| 5982 | candidate = 3; |
| 5983 | else |
| 5984 | candidate = -1; |
| 5985 | } |
| 5986 | } |
| 5987 | } |
| 5988 | |
| 5989 | for (i = 0; i < 4; i++) { |
| 5990 | reg_e94 = result[i][0]; |
| 5991 | reg_e9c = result[i][1]; |
| 5992 | reg_ea4 = result[i][2]; |
| 5993 | reg_eac = result[i][3]; |
| 5994 | reg_eb4 = result[i][4]; |
| 5995 | reg_ebc = result[i][5]; |
| 5996 | reg_ec4 = result[i][6]; |
| 5997 | reg_ecc = result[i][7]; |
| 5998 | } |
| 5999 | |
| 6000 | if (candidate >= 0) { |
| 6001 | reg_e94 = result[candidate][0]; |
| 6002 | priv->rege94 = reg_e94; |
| 6003 | reg_e9c = result[candidate][1]; |
| 6004 | priv->rege9c = reg_e9c; |
| 6005 | reg_ea4 = result[candidate][2]; |
| 6006 | reg_eac = result[candidate][3]; |
| 6007 | reg_eb4 = result[candidate][4]; |
| 6008 | priv->regeb4 = reg_eb4; |
| 6009 | reg_ebc = result[candidate][5]; |
| 6010 | priv->regebc = reg_ebc; |
| 6011 | reg_ec4 = result[candidate][6]; |
| 6012 | reg_ecc = result[candidate][7]; |
| 6013 | dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); |
| 6014 | dev_dbg(dev, |
| 6015 | "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x " |
| 6016 | "ecc=%x\n ", __func__, reg_e94, reg_e9c, |
| 6017 | reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); |
| 6018 | path_a_ok = true; |
| 6019 | path_b_ok = true; |
| 6020 | } else { |
| 6021 | reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; |
| 6022 | reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; |
| 6023 | } |
| 6024 | |
| 6025 | if (reg_e94 && candidate >= 0) |
| 6026 | rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, |
| 6027 | candidate, (reg_ea4 == 0)); |
| 6028 | |
| 6029 | if (priv->tx_paths > 1 && reg_eb4) |
| 6030 | rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, |
| 6031 | candidate, (reg_ec4 == 0)); |
| 6032 | |
| 6033 | rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg, |
| 6034 | priv->bb_recovery_backup, RTL8XXXU_BB_REGS); |
Jes Sorensen | c7a5a19 | 2016-02-29 17:04:30 -0500 | [diff] [blame] | 6035 | |
| 6036 | rtl8xxxu_prepare_calibrate(priv, 0); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6037 | } |
| 6038 | |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 6039 | static void rtl8723bu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) |
| 6040 | { |
| 6041 | struct device *dev = &priv->udev->dev; |
| 6042 | int result[4][8]; /* last is final result */ |
| 6043 | int i, candidate; |
| 6044 | bool path_a_ok, path_b_ok; |
| 6045 | u32 reg_e94, reg_e9c, reg_ea4, reg_eac; |
| 6046 | u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; |
| 6047 | u32 val32, bt_control; |
| 6048 | s32 reg_tmp = 0; |
| 6049 | bool simu; |
| 6050 | |
| 6051 | rtl8xxxu_prepare_calibrate(priv, 1); |
| 6052 | |
| 6053 | memset(result, 0, sizeof(result)); |
| 6054 | candidate = -1; |
| 6055 | |
| 6056 | path_a_ok = false; |
| 6057 | path_b_ok = false; |
| 6058 | |
| 6059 | bt_control = rtl8xxxu_read32(priv, REG_BT_CONTROL_8723BU); |
| 6060 | |
| 6061 | for (i = 0; i < 3; i++) { |
| 6062 | rtl8723bu_phy_iqcalibrate(priv, result, i); |
| 6063 | |
| 6064 | if (i == 1) { |
| 6065 | simu = rtl8723bu_simularity_compare(priv, result, 0, 1); |
| 6066 | if (simu) { |
| 6067 | candidate = 0; |
| 6068 | break; |
| 6069 | } |
| 6070 | } |
| 6071 | |
| 6072 | if (i == 2) { |
| 6073 | simu = rtl8723bu_simularity_compare(priv, result, 0, 2); |
| 6074 | if (simu) { |
| 6075 | candidate = 0; |
| 6076 | break; |
| 6077 | } |
| 6078 | |
| 6079 | simu = rtl8723bu_simularity_compare(priv, result, 1, 2); |
| 6080 | if (simu) { |
| 6081 | candidate = 1; |
| 6082 | } else { |
| 6083 | for (i = 0; i < 8; i++) |
| 6084 | reg_tmp += result[3][i]; |
| 6085 | |
| 6086 | if (reg_tmp) |
| 6087 | candidate = 3; |
| 6088 | else |
| 6089 | candidate = -1; |
| 6090 | } |
| 6091 | } |
| 6092 | } |
| 6093 | |
| 6094 | for (i = 0; i < 4; i++) { |
| 6095 | reg_e94 = result[i][0]; |
| 6096 | reg_e9c = result[i][1]; |
| 6097 | reg_ea4 = result[i][2]; |
| 6098 | reg_eac = result[i][3]; |
| 6099 | reg_eb4 = result[i][4]; |
| 6100 | reg_ebc = result[i][5]; |
| 6101 | reg_ec4 = result[i][6]; |
| 6102 | reg_ecc = result[i][7]; |
| 6103 | } |
| 6104 | |
| 6105 | if (candidate >= 0) { |
| 6106 | reg_e94 = result[candidate][0]; |
| 6107 | priv->rege94 = reg_e94; |
| 6108 | reg_e9c = result[candidate][1]; |
| 6109 | priv->rege9c = reg_e9c; |
| 6110 | reg_ea4 = result[candidate][2]; |
| 6111 | reg_eac = result[candidate][3]; |
| 6112 | reg_eb4 = result[candidate][4]; |
| 6113 | priv->regeb4 = reg_eb4; |
| 6114 | reg_ebc = result[candidate][5]; |
| 6115 | priv->regebc = reg_ebc; |
| 6116 | reg_ec4 = result[candidate][6]; |
| 6117 | reg_ecc = result[candidate][7]; |
| 6118 | dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); |
| 6119 | dev_dbg(dev, |
| 6120 | "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x " |
| 6121 | "ecc=%x\n ", __func__, reg_e94, reg_e9c, |
| 6122 | reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); |
| 6123 | path_a_ok = true; |
| 6124 | path_b_ok = true; |
| 6125 | } else { |
| 6126 | reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; |
| 6127 | reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; |
| 6128 | } |
| 6129 | |
| 6130 | if (reg_e94 && candidate >= 0) |
| 6131 | rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, |
| 6132 | candidate, (reg_ea4 == 0)); |
| 6133 | |
| 6134 | if (priv->tx_paths > 1 && reg_eb4) |
| 6135 | rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, |
| 6136 | candidate, (reg_ec4 == 0)); |
| 6137 | |
| 6138 | rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg, |
| 6139 | priv->bb_recovery_backup, RTL8XXXU_BB_REGS); |
| 6140 | |
| 6141 | rtl8xxxu_write32(priv, REG_BT_CONTROL_8723BU, bt_control); |
| 6142 | |
| 6143 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_WE_LUT); |
| 6144 | val32 |= 0x80000; |
| 6145 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_WE_LUT, val32); |
| 6146 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_RCK_OS, 0x18000); |
| 6147 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G1, 0x0001f); |
| 6148 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_TXPA_G2, 0xe6177); |
| 6149 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED); |
| 6150 | val32 |= 0x20; |
| 6151 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_UNKNOWN_ED, val32); |
| 6152 | rtl8xxxu_write_rfreg(priv, RF_A, 0x43, 0x300bd); |
| 6153 | |
Jes Sorensen | 15f9dc9 | 2016-04-14 14:58:54 -0400 | [diff] [blame] | 6154 | if (priv->rf_paths > 1) |
| 6155 | dev_dbg(dev, "%s: 8723BU 2T not supported\n", __func__); |
| 6156 | |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 6157 | rtl8xxxu_prepare_calibrate(priv, 0); |
| 6158 | } |
| 6159 | |
Jes Sorensen | f991f4e | 2016-04-07 14:19:32 -0400 | [diff] [blame] | 6160 | static void rtl8192eu_phy_iq_calibrate(struct rtl8xxxu_priv *priv) |
| 6161 | { |
| 6162 | struct device *dev = &priv->udev->dev; |
| 6163 | int result[4][8]; /* last is final result */ |
| 6164 | int i, candidate; |
| 6165 | bool path_a_ok, path_b_ok; |
| 6166 | u32 reg_e94, reg_e9c, reg_ea4, reg_eac; |
| 6167 | u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc; |
| 6168 | bool simu; |
| 6169 | |
| 6170 | memset(result, 0, sizeof(result)); |
| 6171 | candidate = -1; |
| 6172 | |
| 6173 | path_a_ok = false; |
| 6174 | path_b_ok = false; |
| 6175 | |
| 6176 | for (i = 0; i < 3; i++) { |
| 6177 | rtl8192eu_phy_iqcalibrate(priv, result, i); |
| 6178 | |
| 6179 | if (i == 1) { |
| 6180 | simu = rtl8723bu_simularity_compare(priv, result, 0, 1); |
| 6181 | if (simu) { |
| 6182 | candidate = 0; |
| 6183 | break; |
| 6184 | } |
| 6185 | } |
| 6186 | |
| 6187 | if (i == 2) { |
| 6188 | simu = rtl8723bu_simularity_compare(priv, result, 0, 2); |
| 6189 | if (simu) { |
| 6190 | candidate = 0; |
| 6191 | break; |
| 6192 | } |
| 6193 | |
| 6194 | simu = rtl8723bu_simularity_compare(priv, result, 1, 2); |
| 6195 | if (simu) |
| 6196 | candidate = 1; |
| 6197 | else |
| 6198 | candidate = 3; |
| 6199 | } |
| 6200 | } |
| 6201 | |
| 6202 | for (i = 0; i < 4; i++) { |
| 6203 | reg_e94 = result[i][0]; |
| 6204 | reg_e9c = result[i][1]; |
| 6205 | reg_ea4 = result[i][2]; |
| 6206 | reg_eac = result[i][3]; |
| 6207 | reg_eb4 = result[i][4]; |
| 6208 | reg_ebc = result[i][5]; |
| 6209 | reg_ec4 = result[i][6]; |
| 6210 | reg_ecc = result[i][7]; |
| 6211 | } |
| 6212 | |
| 6213 | if (candidate >= 0) { |
| 6214 | reg_e94 = result[candidate][0]; |
| 6215 | priv->rege94 = reg_e94; |
| 6216 | reg_e9c = result[candidate][1]; |
| 6217 | priv->rege9c = reg_e9c; |
| 6218 | reg_ea4 = result[candidate][2]; |
| 6219 | reg_eac = result[candidate][3]; |
| 6220 | reg_eb4 = result[candidate][4]; |
| 6221 | priv->regeb4 = reg_eb4; |
| 6222 | reg_ebc = result[candidate][5]; |
| 6223 | priv->regebc = reg_ebc; |
| 6224 | reg_ec4 = result[candidate][6]; |
| 6225 | reg_ecc = result[candidate][7]; |
| 6226 | dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate); |
| 6227 | dev_dbg(dev, |
| 6228 | "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x " |
| 6229 | "ecc=%x\n ", __func__, reg_e94, reg_e9c, |
| 6230 | reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc); |
| 6231 | path_a_ok = true; |
| 6232 | path_b_ok = true; |
| 6233 | } else { |
| 6234 | reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100; |
| 6235 | reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0; |
| 6236 | } |
| 6237 | |
| 6238 | if (reg_e94 && candidate >= 0) |
| 6239 | rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result, |
| 6240 | candidate, (reg_ea4 == 0)); |
| 6241 | |
| 6242 | if (priv->rf_paths > 1) |
| 6243 | rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result, |
| 6244 | candidate, (reg_ec4 == 0)); |
| 6245 | |
| 6246 | rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg, |
| 6247 | priv->bb_recovery_backup, RTL8XXXU_BB_REGS); |
| 6248 | } |
| 6249 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6250 | static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv) |
| 6251 | { |
| 6252 | u32 val32; |
| 6253 | u32 rf_amode, rf_bmode = 0, lstf; |
| 6254 | |
| 6255 | /* Check continuous TX and Packet TX */ |
| 6256 | lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF); |
| 6257 | |
| 6258 | if (lstf & OFDM_LSTF_MASK) { |
| 6259 | /* Disable all continuous TX */ |
| 6260 | val32 = lstf & ~OFDM_LSTF_MASK; |
| 6261 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32); |
| 6262 | |
| 6263 | /* Read original RF mode Path A */ |
| 6264 | rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC); |
| 6265 | |
| 6266 | /* Set RF mode to standby Path A */ |
| 6267 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, |
| 6268 | (rf_amode & 0x8ffff) | 0x10000); |
| 6269 | |
| 6270 | /* Path-B */ |
| 6271 | if (priv->tx_paths > 1) { |
| 6272 | rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B, |
| 6273 | RF6052_REG_AC); |
| 6274 | |
| 6275 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, |
| 6276 | (rf_bmode & 0x8ffff) | 0x10000); |
| 6277 | } |
| 6278 | } else { |
| 6279 | /* Deal with Packet TX case */ |
| 6280 | /* block all queues */ |
| 6281 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); |
| 6282 | } |
| 6283 | |
| 6284 | /* Start LC calibration */ |
Jes Sorensen | 0d698de | 2016-02-29 17:04:36 -0500 | [diff] [blame] | 6285 | if (priv->fops->has_s0s1) |
| 6286 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdfbe0); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6287 | val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG); |
| 6288 | val32 |= 0x08000; |
| 6289 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32); |
| 6290 | |
| 6291 | msleep(100); |
| 6292 | |
Jes Sorensen | 0d698de | 2016-02-29 17:04:36 -0500 | [diff] [blame] | 6293 | if (priv->fops->has_s0s1) |
| 6294 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_S0S1, 0xdffe0); |
| 6295 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6296 | /* Restore original parameters */ |
| 6297 | if (lstf & OFDM_LSTF_MASK) { |
| 6298 | /* Path-A */ |
| 6299 | rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf); |
| 6300 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode); |
| 6301 | |
| 6302 | /* Path-B */ |
| 6303 | if (priv->tx_paths > 1) |
| 6304 | rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, |
| 6305 | rf_bmode); |
| 6306 | } else /* Deal with Packet TX case */ |
| 6307 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00); |
| 6308 | } |
| 6309 | |
| 6310 | static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv) |
| 6311 | { |
| 6312 | int i; |
| 6313 | u16 reg; |
| 6314 | |
| 6315 | reg = REG_MACID; |
| 6316 | |
| 6317 | for (i = 0; i < ETH_ALEN; i++) |
| 6318 | rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]); |
| 6319 | |
| 6320 | return 0; |
| 6321 | } |
| 6322 | |
| 6323 | static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid) |
| 6324 | { |
| 6325 | int i; |
| 6326 | u16 reg; |
| 6327 | |
| 6328 | dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid); |
| 6329 | |
| 6330 | reg = REG_BSSID; |
| 6331 | |
| 6332 | for (i = 0; i < ETH_ALEN; i++) |
| 6333 | rtl8xxxu_write8(priv, reg + i, bssid[i]); |
| 6334 | |
| 6335 | return 0; |
| 6336 | } |
| 6337 | |
| 6338 | static void |
| 6339 | rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor) |
| 6340 | { |
| 6341 | u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 }; |
| 6342 | u8 max_agg = 0xf; |
| 6343 | int i; |
| 6344 | |
| 6345 | ampdu_factor = 1 << (ampdu_factor + 2); |
| 6346 | if (ampdu_factor > max_agg) |
| 6347 | ampdu_factor = max_agg; |
| 6348 | |
| 6349 | for (i = 0; i < 4; i++) { |
| 6350 | if ((vals[i] & 0xf0) > (ampdu_factor << 4)) |
| 6351 | vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4); |
| 6352 | |
| 6353 | if ((vals[i] & 0x0f) > ampdu_factor) |
| 6354 | vals[i] = (vals[i] & 0xf0) | ampdu_factor; |
| 6355 | |
| 6356 | rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]); |
| 6357 | } |
| 6358 | } |
| 6359 | |
| 6360 | static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density) |
| 6361 | { |
| 6362 | u8 val8; |
| 6363 | |
| 6364 | val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE); |
| 6365 | val8 &= 0xf8; |
| 6366 | val8 |= density; |
| 6367 | rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8); |
| 6368 | } |
| 6369 | |
| 6370 | static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv) |
| 6371 | { |
| 6372 | u8 val8; |
Colin Ian King | 37ba4b6 | 2016-04-14 16:37:07 -0400 | [diff] [blame^] | 6373 | int count, ret = 0; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6374 | |
| 6375 | /* Start of rtl8723AU_card_enable_flow */ |
| 6376 | /* Act to Cardemu sequence*/ |
| 6377 | /* Turn off RF */ |
| 6378 | rtl8xxxu_write8(priv, REG_RF_CTRL, 0); |
| 6379 | |
| 6380 | /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */ |
| 6381 | val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); |
| 6382 | val8 &= ~LEDCFG2_DPDT_SELECT; |
| 6383 | rtl8xxxu_write8(priv, REG_LEDCFG2, val8); |
| 6384 | |
| 6385 | /* 0x0005[1] = 1 turn off MAC by HW state machine*/ |
| 6386 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6387 | val8 |= BIT(1); |
| 6388 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6389 | |
| 6390 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 6391 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6392 | if ((val8 & BIT(1)) == 0) |
| 6393 | break; |
| 6394 | udelay(10); |
| 6395 | } |
| 6396 | |
| 6397 | if (!count) { |
| 6398 | dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", |
| 6399 | __func__); |
| 6400 | ret = -EBUSY; |
| 6401 | goto exit; |
| 6402 | } |
| 6403 | |
| 6404 | /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ |
| 6405 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); |
| 6406 | val8 |= SYS_ISO_ANALOG_IPS; |
| 6407 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); |
| 6408 | |
| 6409 | /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ |
| 6410 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); |
| 6411 | val8 &= ~LDOA15_ENABLE; |
| 6412 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); |
| 6413 | |
| 6414 | exit: |
| 6415 | return ret; |
| 6416 | } |
| 6417 | |
Jes Sorensen | fe37d5f | 2016-02-29 17:05:47 -0500 | [diff] [blame] | 6418 | static int rtl8723bu_active_to_emu(struct rtl8xxxu_priv *priv) |
| 6419 | { |
| 6420 | u8 val8; |
| 6421 | u16 val16; |
| 6422 | u32 val32; |
Colin Ian King | 37ba4b6 | 2016-04-14 16:37:07 -0400 | [diff] [blame^] | 6423 | int count, ret = 0; |
Jes Sorensen | fe37d5f | 2016-02-29 17:05:47 -0500 | [diff] [blame] | 6424 | |
| 6425 | /* Turn off RF */ |
| 6426 | rtl8xxxu_write8(priv, REG_RF_CTRL, 0); |
| 6427 | |
| 6428 | /* Enable rising edge triggering interrupt */ |
| 6429 | val16 = rtl8xxxu_read16(priv, REG_GPIO_INTM); |
| 6430 | val16 &= ~GPIO_INTM_EDGE_TRIG_IRQ; |
| 6431 | rtl8xxxu_write16(priv, REG_GPIO_INTM, val16); |
| 6432 | |
| 6433 | /* Release WLON reset 0x04[16]= 1*/ |
| 6434 | val32 = rtl8xxxu_read32(priv, REG_GPIO_INTM); |
| 6435 | val32 |= APS_FSMCO_WLON_RESET; |
| 6436 | rtl8xxxu_write32(priv, REG_GPIO_INTM, val32); |
| 6437 | |
| 6438 | /* 0x0005[1] = 1 turn off MAC by HW state machine*/ |
| 6439 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6440 | val8 |= BIT(1); |
| 6441 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6442 | |
| 6443 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 6444 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6445 | if ((val8 & BIT(1)) == 0) |
| 6446 | break; |
| 6447 | udelay(10); |
| 6448 | } |
| 6449 | |
| 6450 | if (!count) { |
| 6451 | dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n", |
| 6452 | __func__); |
| 6453 | ret = -EBUSY; |
| 6454 | goto exit; |
| 6455 | } |
| 6456 | |
| 6457 | /* Enable BT control XTAL setting */ |
| 6458 | val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); |
| 6459 | val8 &= ~AFE_MISC_WL_XTAL_CTRL; |
| 6460 | rtl8xxxu_write8(priv, REG_AFE_MISC, val8); |
| 6461 | |
| 6462 | /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */ |
| 6463 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); |
| 6464 | val8 |= SYS_ISO_ANALOG_IPS; |
| 6465 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); |
| 6466 | |
| 6467 | /* 0x0020[0] = 0 disable LDOA12 MACRO block*/ |
| 6468 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); |
| 6469 | val8 &= ~LDOA15_ENABLE; |
| 6470 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); |
| 6471 | |
| 6472 | exit: |
| 6473 | return ret; |
| 6474 | } |
| 6475 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6476 | static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv) |
| 6477 | { |
| 6478 | u8 val8; |
| 6479 | u8 val32; |
Colin Ian King | 37ba4b6 | 2016-04-14 16:37:07 -0400 | [diff] [blame^] | 6480 | int count, ret = 0; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6481 | |
| 6482 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); |
| 6483 | |
| 6484 | /* |
| 6485 | * Poll - wait for RX packet to complete |
| 6486 | */ |
| 6487 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 6488 | val32 = rtl8xxxu_read32(priv, 0x5f8); |
| 6489 | if (!val32) |
| 6490 | break; |
| 6491 | udelay(10); |
| 6492 | } |
| 6493 | |
| 6494 | if (!count) { |
| 6495 | dev_warn(&priv->udev->dev, |
| 6496 | "%s: RX poll timed out (0x05f8)\n", __func__); |
| 6497 | ret = -EBUSY; |
| 6498 | goto exit; |
| 6499 | } |
| 6500 | |
| 6501 | /* Disable CCK and OFDM, clock gated */ |
| 6502 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); |
| 6503 | val8 &= ~SYS_FUNC_BBRSTB; |
| 6504 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); |
| 6505 | |
| 6506 | udelay(2); |
| 6507 | |
| 6508 | /* Reset baseband */ |
| 6509 | val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC); |
| 6510 | val8 &= ~SYS_FUNC_BB_GLB_RSTN; |
| 6511 | rtl8xxxu_write8(priv, REG_SYS_FUNC, val8); |
| 6512 | |
| 6513 | /* Reset MAC TRX */ |
| 6514 | val8 = rtl8xxxu_read8(priv, REG_CR); |
| 6515 | val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE; |
| 6516 | rtl8xxxu_write8(priv, REG_CR, val8); |
| 6517 | |
| 6518 | /* Reset MAC TRX */ |
| 6519 | val8 = rtl8xxxu_read8(priv, REG_CR + 1); |
| 6520 | val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */ |
| 6521 | rtl8xxxu_write8(priv, REG_CR + 1, val8); |
| 6522 | |
| 6523 | /* Respond TX OK to scheduler */ |
| 6524 | val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST); |
| 6525 | val8 |= DUAL_TSF_TX_OK; |
| 6526 | rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8); |
| 6527 | |
| 6528 | exit: |
| 6529 | return ret; |
| 6530 | } |
| 6531 | |
Jes Sorensen | c05a9db | 2016-02-29 17:04:03 -0500 | [diff] [blame] | 6532 | static void rtl8723a_disabled_to_emu(struct rtl8xxxu_priv *priv) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6533 | { |
| 6534 | u8 val8; |
| 6535 | |
| 6536 | /* Clear suspend enable and power down enable*/ |
| 6537 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6538 | val8 &= ~(BIT(3) | BIT(7)); |
| 6539 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6540 | |
| 6541 | /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/ |
| 6542 | val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); |
| 6543 | val8 &= ~BIT(0); |
| 6544 | rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); |
| 6545 | |
| 6546 | /* 0x04[12:11] = 11 enable WL suspend*/ |
| 6547 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6548 | val8 &= ~(BIT(3) | BIT(4)); |
| 6549 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6550 | } |
| 6551 | |
Jes Sorensen | c05a9db | 2016-02-29 17:04:03 -0500 | [diff] [blame] | 6552 | static void rtl8192e_disabled_to_emu(struct rtl8xxxu_priv *priv) |
| 6553 | { |
| 6554 | u8 val8; |
| 6555 | |
| 6556 | /* Clear suspend enable and power down enable*/ |
| 6557 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6558 | val8 &= ~(BIT(3) | BIT(4)); |
| 6559 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6560 | } |
| 6561 | |
| 6562 | static int rtl8192e_emu_to_active(struct rtl8xxxu_priv *priv) |
| 6563 | { |
| 6564 | u8 val8; |
| 6565 | u32 val32; |
| 6566 | int count, ret = 0; |
| 6567 | |
| 6568 | /* disable HWPDN 0x04[15]=0*/ |
| 6569 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6570 | val8 &= ~BIT(7); |
| 6571 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6572 | |
| 6573 | /* disable SW LPS 0x04[10]= 0 */ |
| 6574 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6575 | val8 &= ~BIT(2); |
| 6576 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6577 | |
| 6578 | /* disable WL suspend*/ |
| 6579 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6580 | val8 &= ~(BIT(3) | BIT(4)); |
| 6581 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6582 | |
| 6583 | /* wait till 0x04[17] = 1 power ready*/ |
| 6584 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 6585 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 6586 | if (val32 & BIT(17)) |
| 6587 | break; |
| 6588 | |
| 6589 | udelay(10); |
| 6590 | } |
| 6591 | |
| 6592 | if (!count) { |
| 6593 | ret = -EBUSY; |
| 6594 | goto exit; |
| 6595 | } |
| 6596 | |
| 6597 | /* We should be able to optimize the following three entries into one */ |
| 6598 | |
| 6599 | /* release WLON reset 0x04[16]= 1*/ |
| 6600 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); |
| 6601 | val8 |= BIT(0); |
| 6602 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); |
| 6603 | |
| 6604 | /* set, then poll until 0 */ |
| 6605 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 6606 | val32 |= APS_FSMCO_MAC_ENABLE; |
| 6607 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 6608 | |
| 6609 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 6610 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 6611 | if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { |
| 6612 | ret = 0; |
| 6613 | break; |
| 6614 | } |
| 6615 | udelay(10); |
| 6616 | } |
| 6617 | |
| 6618 | if (!count) { |
| 6619 | ret = -EBUSY; |
| 6620 | goto exit; |
| 6621 | } |
| 6622 | |
| 6623 | exit: |
| 6624 | return ret; |
| 6625 | } |
| 6626 | |
| 6627 | static int rtl8723a_emu_to_active(struct rtl8xxxu_priv *priv) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6628 | { |
| 6629 | u8 val8; |
| 6630 | u32 val32; |
| 6631 | int count, ret = 0; |
| 6632 | |
| 6633 | /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/ |
| 6634 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); |
| 6635 | val8 |= LDOA15_ENABLE; |
| 6636 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); |
| 6637 | |
| 6638 | /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ |
| 6639 | val8 = rtl8xxxu_read8(priv, 0x0067); |
| 6640 | val8 &= ~BIT(4); |
| 6641 | rtl8xxxu_write8(priv, 0x0067, val8); |
| 6642 | |
| 6643 | mdelay(1); |
| 6644 | |
| 6645 | /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ |
| 6646 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); |
| 6647 | val8 &= ~SYS_ISO_ANALOG_IPS; |
| 6648 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); |
| 6649 | |
| 6650 | /* disable SW LPS 0x04[10]= 0 */ |
| 6651 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6652 | val8 &= ~BIT(2); |
| 6653 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6654 | |
| 6655 | /* wait till 0x04[17] = 1 power ready*/ |
| 6656 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 6657 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 6658 | if (val32 & BIT(17)) |
| 6659 | break; |
| 6660 | |
| 6661 | udelay(10); |
| 6662 | } |
| 6663 | |
| 6664 | if (!count) { |
| 6665 | ret = -EBUSY; |
| 6666 | goto exit; |
| 6667 | } |
| 6668 | |
| 6669 | /* We should be able to optimize the following three entries into one */ |
| 6670 | |
| 6671 | /* release WLON reset 0x04[16]= 1*/ |
| 6672 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); |
| 6673 | val8 |= BIT(0); |
| 6674 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); |
| 6675 | |
| 6676 | /* disable HWPDN 0x04[15]= 0*/ |
| 6677 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6678 | val8 &= ~BIT(7); |
| 6679 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6680 | |
| 6681 | /* disable WL suspend*/ |
| 6682 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6683 | val8 &= ~(BIT(3) | BIT(4)); |
| 6684 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6685 | |
| 6686 | /* set, then poll until 0 */ |
| 6687 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 6688 | val32 |= APS_FSMCO_MAC_ENABLE; |
| 6689 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 6690 | |
| 6691 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 6692 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 6693 | if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { |
| 6694 | ret = 0; |
| 6695 | break; |
| 6696 | } |
| 6697 | udelay(10); |
| 6698 | } |
| 6699 | |
| 6700 | if (!count) { |
| 6701 | ret = -EBUSY; |
| 6702 | goto exit; |
| 6703 | } |
| 6704 | |
| 6705 | /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */ |
| 6706 | /* |
| 6707 | * Note: Vendor driver actually clears this bit, despite the |
| 6708 | * documentation claims it's being set! |
| 6709 | */ |
| 6710 | val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); |
| 6711 | val8 |= LEDCFG2_DPDT_SELECT; |
| 6712 | val8 &= ~LEDCFG2_DPDT_SELECT; |
| 6713 | rtl8xxxu_write8(priv, REG_LEDCFG2, val8); |
| 6714 | |
| 6715 | exit: |
| 6716 | return ret; |
| 6717 | } |
| 6718 | |
Jes Sorensen | 42836db | 2016-02-29 17:04:52 -0500 | [diff] [blame] | 6719 | static int rtl8723b_emu_to_active(struct rtl8xxxu_priv *priv) |
| 6720 | { |
| 6721 | u8 val8; |
| 6722 | u32 val32; |
| 6723 | int count, ret = 0; |
| 6724 | |
| 6725 | /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface */ |
| 6726 | val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL); |
| 6727 | val8 |= LDOA15_ENABLE; |
| 6728 | rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8); |
| 6729 | |
| 6730 | /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/ |
| 6731 | val8 = rtl8xxxu_read8(priv, 0x0067); |
| 6732 | val8 &= ~BIT(4); |
| 6733 | rtl8xxxu_write8(priv, 0x0067, val8); |
| 6734 | |
| 6735 | mdelay(1); |
| 6736 | |
| 6737 | /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */ |
| 6738 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); |
| 6739 | val8 &= ~SYS_ISO_ANALOG_IPS; |
| 6740 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); |
| 6741 | |
| 6742 | /* Disable SW LPS 0x04[10]= 0 */ |
| 6743 | val32 = rtl8xxxu_read8(priv, REG_APS_FSMCO); |
| 6744 | val32 &= ~APS_FSMCO_SW_LPS; |
| 6745 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 6746 | |
| 6747 | /* Wait until 0x04[17] = 1 power ready */ |
| 6748 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 6749 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 6750 | if (val32 & BIT(17)) |
| 6751 | break; |
| 6752 | |
| 6753 | udelay(10); |
| 6754 | } |
| 6755 | |
| 6756 | if (!count) { |
| 6757 | ret = -EBUSY; |
| 6758 | goto exit; |
| 6759 | } |
| 6760 | |
| 6761 | /* We should be able to optimize the following three entries into one */ |
| 6762 | |
| 6763 | /* Release WLON reset 0x04[16]= 1*/ |
| 6764 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 6765 | val32 |= APS_FSMCO_WLON_RESET; |
| 6766 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 6767 | |
| 6768 | /* Disable HWPDN 0x04[15]= 0*/ |
| 6769 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 6770 | val32 &= ~APS_FSMCO_HW_POWERDOWN; |
| 6771 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 6772 | |
| 6773 | /* Disable WL suspend*/ |
| 6774 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 6775 | val32 &= ~(APS_FSMCO_HW_SUSPEND | APS_FSMCO_PCIE); |
| 6776 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 6777 | |
| 6778 | /* Set, then poll until 0 */ |
| 6779 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 6780 | val32 |= APS_FSMCO_MAC_ENABLE; |
| 6781 | rtl8xxxu_write32(priv, REG_APS_FSMCO, val32); |
| 6782 | |
| 6783 | for (count = RTL8XXXU_MAX_REG_POLL; count; count--) { |
| 6784 | val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO); |
| 6785 | if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) { |
| 6786 | ret = 0; |
| 6787 | break; |
| 6788 | } |
| 6789 | udelay(10); |
| 6790 | } |
| 6791 | |
| 6792 | if (!count) { |
| 6793 | ret = -EBUSY; |
| 6794 | goto exit; |
| 6795 | } |
| 6796 | |
| 6797 | /* Enable WL control XTAL setting */ |
| 6798 | val8 = rtl8xxxu_read8(priv, REG_AFE_MISC); |
| 6799 | val8 |= AFE_MISC_WL_XTAL_CTRL; |
| 6800 | rtl8xxxu_write8(priv, REG_AFE_MISC, val8); |
| 6801 | |
| 6802 | /* Enable falling edge triggering interrupt */ |
| 6803 | val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 1); |
| 6804 | val8 |= BIT(1); |
| 6805 | rtl8xxxu_write8(priv, REG_GPIO_INTM + 1, val8); |
| 6806 | |
| 6807 | /* Enable GPIO9 interrupt mode */ |
| 6808 | val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2 + 1); |
| 6809 | val8 |= BIT(1); |
| 6810 | rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2 + 1, val8); |
| 6811 | |
| 6812 | /* Enable GPIO9 input mode */ |
| 6813 | val8 = rtl8xxxu_read8(priv, REG_GPIO_IO_SEL_2); |
| 6814 | val8 &= ~BIT(1); |
| 6815 | rtl8xxxu_write8(priv, REG_GPIO_IO_SEL_2, val8); |
| 6816 | |
| 6817 | /* Enable HSISR GPIO[C:0] interrupt */ |
| 6818 | val8 = rtl8xxxu_read8(priv, REG_HSIMR); |
| 6819 | val8 |= BIT(0); |
| 6820 | rtl8xxxu_write8(priv, REG_HSIMR, val8); |
| 6821 | |
| 6822 | /* Enable HSISR GPIO9 interrupt */ |
| 6823 | val8 = rtl8xxxu_read8(priv, REG_HSIMR + 2); |
| 6824 | val8 |= BIT(1); |
| 6825 | rtl8xxxu_write8(priv, REG_HSIMR + 2, val8); |
| 6826 | |
| 6827 | val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL); |
| 6828 | val8 |= MULTI_WIFI_HW_ROF_EN; |
| 6829 | rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL, val8); |
| 6830 | |
| 6831 | /* For GPIO9 internal pull high setting BIT(14) */ |
| 6832 | val8 = rtl8xxxu_read8(priv, REG_MULTI_FUNC_CTRL + 1); |
| 6833 | val8 |= BIT(6); |
| 6834 | rtl8xxxu_write8(priv, REG_MULTI_FUNC_CTRL + 1, val8); |
| 6835 | |
| 6836 | exit: |
| 6837 | return ret; |
| 6838 | } |
| 6839 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6840 | static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv) |
| 6841 | { |
| 6842 | u8 val8; |
| 6843 | |
| 6844 | /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */ |
| 6845 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20); |
| 6846 | |
| 6847 | /* 0x04[12:11] = 01 enable WL suspend */ |
| 6848 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6849 | val8 &= ~BIT(4); |
| 6850 | val8 |= BIT(3); |
| 6851 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6852 | |
| 6853 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1); |
| 6854 | val8 |= BIT(7); |
| 6855 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8); |
| 6856 | |
| 6857 | /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */ |
| 6858 | val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2); |
| 6859 | val8 |= BIT(0); |
| 6860 | rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8); |
| 6861 | |
| 6862 | return 0; |
| 6863 | } |
| 6864 | |
Jes Sorensen | 430b454 | 2016-02-29 17:05:48 -0500 | [diff] [blame] | 6865 | static int rtl8xxxu_flush_fifo(struct rtl8xxxu_priv *priv) |
| 6866 | { |
Jes Sorensen | 145428e | 2016-02-29 17:05:49 -0500 | [diff] [blame] | 6867 | struct device *dev = &priv->udev->dev; |
Jes Sorensen | 430b454 | 2016-02-29 17:05:48 -0500 | [diff] [blame] | 6868 | u32 val32; |
| 6869 | int retry, retval; |
| 6870 | |
| 6871 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); |
| 6872 | |
| 6873 | val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); |
| 6874 | val32 |= RXPKT_NUM_RW_RELEASE_EN; |
| 6875 | rtl8xxxu_write32(priv, REG_RXPKT_NUM, val32); |
| 6876 | |
| 6877 | retry = 100; |
| 6878 | retval = -EBUSY; |
| 6879 | |
| 6880 | do { |
| 6881 | val32 = rtl8xxxu_read32(priv, REG_RXPKT_NUM); |
| 6882 | if (val32 & RXPKT_NUM_RXDMA_IDLE) { |
| 6883 | retval = 0; |
| 6884 | break; |
| 6885 | } |
| 6886 | } while (retry--); |
| 6887 | |
| 6888 | rtl8xxxu_write16(priv, REG_RQPN_NPQ, 0); |
| 6889 | rtl8xxxu_write32(priv, REG_RQPN, 0x80000000); |
| 6890 | mdelay(2); |
Jes Sorensen | 145428e | 2016-02-29 17:05:49 -0500 | [diff] [blame] | 6891 | |
| 6892 | if (!retry) |
| 6893 | dev_warn(dev, "Failed to flush FIFO\n"); |
Jes Sorensen | 430b454 | 2016-02-29 17:05:48 -0500 | [diff] [blame] | 6894 | |
| 6895 | return retval; |
| 6896 | } |
| 6897 | |
Jes Sorensen | 747bf23 | 2016-04-14 14:59:04 -0400 | [diff] [blame] | 6898 | static void rtl8xxxu_gen1_usb_quirks(struct rtl8xxxu_priv *priv) |
| 6899 | { |
| 6900 | /* Fix USB interface interference issue */ |
| 6901 | rtl8xxxu_write8(priv, 0xfe40, 0xe0); |
| 6902 | rtl8xxxu_write8(priv, 0xfe41, 0x8d); |
| 6903 | rtl8xxxu_write8(priv, 0xfe42, 0x80); |
| 6904 | /* |
| 6905 | * This sets TXDMA_OFFSET_DROP_DATA_EN (bit 9) as well as bits |
| 6906 | * 8 and 5, for which I have found no documentation. |
| 6907 | */ |
| 6908 | rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320); |
| 6909 | |
| 6910 | /* |
| 6911 | * Solve too many protocol error on USB bus. |
| 6912 | * Can't do this for 8188/8192 UMC A cut parts |
| 6913 | */ |
| 6914 | if (!(!priv->chip_cut && priv->vendor_umc)) { |
| 6915 | rtl8xxxu_write8(priv, 0xfe40, 0xe6); |
| 6916 | rtl8xxxu_write8(priv, 0xfe41, 0x94); |
| 6917 | rtl8xxxu_write8(priv, 0xfe42, 0x80); |
| 6918 | |
| 6919 | rtl8xxxu_write8(priv, 0xfe40, 0xe0); |
| 6920 | rtl8xxxu_write8(priv, 0xfe41, 0x19); |
| 6921 | rtl8xxxu_write8(priv, 0xfe42, 0x80); |
| 6922 | |
| 6923 | rtl8xxxu_write8(priv, 0xfe40, 0xe5); |
| 6924 | rtl8xxxu_write8(priv, 0xfe41, 0x91); |
| 6925 | rtl8xxxu_write8(priv, 0xfe42, 0x80); |
| 6926 | |
| 6927 | rtl8xxxu_write8(priv, 0xfe40, 0xe2); |
| 6928 | rtl8xxxu_write8(priv, 0xfe41, 0x81); |
| 6929 | rtl8xxxu_write8(priv, 0xfe42, 0x80); |
| 6930 | } |
| 6931 | } |
| 6932 | |
| 6933 | static void rtl8xxxu_gen2_usb_quirks(struct rtl8xxxu_priv *priv) |
| 6934 | { |
| 6935 | u32 val32; |
| 6936 | |
| 6937 | val32 = rtl8xxxu_read32(priv, REG_TXDMA_OFFSET_CHK); |
| 6938 | val32 |= TXDMA_OFFSET_DROP_DATA_EN; |
| 6939 | rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, val32); |
| 6940 | } |
| 6941 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6942 | static int rtl8723au_power_on(struct rtl8xxxu_priv *priv) |
| 6943 | { |
| 6944 | u8 val8; |
| 6945 | u16 val16; |
| 6946 | u32 val32; |
| 6947 | int ret; |
| 6948 | |
| 6949 | /* |
| 6950 | * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register |
| 6951 | */ |
| 6952 | rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); |
| 6953 | |
Jes Sorensen | c05a9db | 2016-02-29 17:04:03 -0500 | [diff] [blame] | 6954 | rtl8723a_disabled_to_emu(priv); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6955 | |
Jes Sorensen | c05a9db | 2016-02-29 17:04:03 -0500 | [diff] [blame] | 6956 | ret = rtl8723a_emu_to_active(priv); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 6957 | if (ret) |
| 6958 | goto exit; |
| 6959 | |
| 6960 | /* |
| 6961 | * 0x0004[19] = 1, reset 8051 |
| 6962 | */ |
| 6963 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2); |
| 6964 | val8 |= BIT(3); |
| 6965 | rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8); |
| 6966 | |
| 6967 | /* |
| 6968 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block |
| 6969 | * Set CR bit10 to enable 32k calibration. |
| 6970 | */ |
| 6971 | val16 = rtl8xxxu_read16(priv, REG_CR); |
| 6972 | val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | |
| 6973 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | |
| 6974 | CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | |
| 6975 | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | |
| 6976 | CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); |
| 6977 | rtl8xxxu_write16(priv, REG_CR, val16); |
| 6978 | |
| 6979 | /* For EFuse PG */ |
| 6980 | val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL); |
| 6981 | val32 &= ~(BIT(28) | BIT(29) | BIT(30)); |
| 6982 | val32 |= (0x06 << 28); |
| 6983 | rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32); |
| 6984 | exit: |
| 6985 | return ret; |
| 6986 | } |
| 6987 | |
Jes Sorensen | 42836db | 2016-02-29 17:04:52 -0500 | [diff] [blame] | 6988 | static int rtl8723bu_power_on(struct rtl8xxxu_priv *priv) |
| 6989 | { |
| 6990 | u8 val8; |
| 6991 | u16 val16; |
| 6992 | u32 val32; |
| 6993 | int ret; |
| 6994 | |
| 6995 | rtl8723a_disabled_to_emu(priv); |
| 6996 | |
| 6997 | ret = rtl8723b_emu_to_active(priv); |
| 6998 | if (ret) |
| 6999 | goto exit; |
| 7000 | |
| 7001 | /* |
| 7002 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block |
| 7003 | * Set CR bit10 to enable 32k calibration. |
| 7004 | */ |
| 7005 | val16 = rtl8xxxu_read16(priv, REG_CR); |
| 7006 | val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | |
| 7007 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | |
| 7008 | CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | |
| 7009 | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | |
| 7010 | CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); |
| 7011 | rtl8xxxu_write16(priv, REG_CR, val16); |
| 7012 | |
| 7013 | /* |
| 7014 | * BT coexist power on settings. This is identical for 1 and 2 |
| 7015 | * antenna parts. |
| 7016 | */ |
| 7017 | rtl8xxxu_write8(priv, REG_PAD_CTRL1 + 3, 0x20); |
| 7018 | |
| 7019 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 7020 | val16 |= SYS_FUNC_BBRSTB | SYS_FUNC_BB_GLB_RSTN; |
| 7021 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 7022 | |
| 7023 | rtl8xxxu_write8(priv, REG_BT_CONTROL_8723BU + 1, 0x18); |
| 7024 | rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); |
| 7025 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); |
| 7026 | /* Antenna inverse */ |
| 7027 | rtl8xxxu_write8(priv, 0xfe08, 0x01); |
| 7028 | |
| 7029 | val16 = rtl8xxxu_read16(priv, REG_PWR_DATA); |
| 7030 | val16 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; |
| 7031 | rtl8xxxu_write16(priv, REG_PWR_DATA, val16); |
| 7032 | |
| 7033 | val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); |
| 7034 | val32 |= LEDCFG0_DPDT_SELECT; |
| 7035 | rtl8xxxu_write32(priv, REG_LEDCFG0, val32); |
| 7036 | |
| 7037 | val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); |
| 7038 | val8 &= ~PAD_CTRL1_SW_DPDT_SEL_DATA; |
| 7039 | rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); |
| 7040 | exit: |
| 7041 | return ret; |
| 7042 | } |
| 7043 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 7044 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
| 7045 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7046 | static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv) |
| 7047 | { |
| 7048 | u8 val8; |
| 7049 | u16 val16; |
| 7050 | u32 val32; |
| 7051 | int i; |
| 7052 | |
| 7053 | for (i = 100; i; i--) { |
| 7054 | val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO); |
| 7055 | if (val8 & APS_FSMCO_PFM_ALDN) |
| 7056 | break; |
| 7057 | } |
| 7058 | |
| 7059 | if (!i) { |
| 7060 | pr_info("%s: Poll failed\n", __func__); |
| 7061 | return -ENODEV; |
| 7062 | } |
| 7063 | |
| 7064 | /* |
| 7065 | * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register |
| 7066 | */ |
| 7067 | rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0); |
| 7068 | rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b); |
| 7069 | udelay(100); |
| 7070 | |
| 7071 | val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL); |
| 7072 | if (!(val8 & LDOV12D_ENABLE)) { |
| 7073 | pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8); |
| 7074 | val8 |= LDOV12D_ENABLE; |
| 7075 | rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8); |
| 7076 | |
| 7077 | udelay(100); |
| 7078 | |
| 7079 | val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL); |
| 7080 | val8 &= ~SYS_ISO_MD2PP; |
| 7081 | rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8); |
| 7082 | } |
| 7083 | |
| 7084 | /* |
| 7085 | * Auto enable WLAN |
| 7086 | */ |
| 7087 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); |
| 7088 | val16 |= APS_FSMCO_MAC_ENABLE; |
| 7089 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); |
| 7090 | |
| 7091 | for (i = 1000; i; i--) { |
| 7092 | val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO); |
| 7093 | if (!(val16 & APS_FSMCO_MAC_ENABLE)) |
| 7094 | break; |
| 7095 | } |
| 7096 | if (!i) { |
| 7097 | pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__); |
| 7098 | return -EBUSY; |
| 7099 | } |
| 7100 | |
| 7101 | /* |
| 7102 | * Enable radio, GPIO, LED |
| 7103 | */ |
| 7104 | val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN | |
| 7105 | APS_FSMCO_PFM_ALDN; |
| 7106 | rtl8xxxu_write16(priv, REG_APS_FSMCO, val16); |
| 7107 | |
| 7108 | /* |
| 7109 | * Release RF digital isolation |
| 7110 | */ |
| 7111 | val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL); |
| 7112 | val16 &= ~SYS_ISO_DIOR; |
| 7113 | rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16); |
| 7114 | |
| 7115 | val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); |
| 7116 | val8 &= ~APSD_CTRL_OFF; |
| 7117 | rtl8xxxu_write8(priv, REG_APSD_CTRL, val8); |
| 7118 | for (i = 200; i; i--) { |
| 7119 | val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL); |
| 7120 | if (!(val8 & APSD_CTRL_OFF_STATUS)) |
| 7121 | break; |
| 7122 | } |
| 7123 | |
| 7124 | if (!i) { |
| 7125 | pr_info("%s: APSD_CTRL poll failed\n", __func__); |
| 7126 | return -EBUSY; |
| 7127 | } |
| 7128 | |
| 7129 | /* |
| 7130 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block |
| 7131 | */ |
| 7132 | val16 = rtl8xxxu_read16(priv, REG_CR); |
| 7133 | val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | |
| 7134 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE | |
| 7135 | CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE; |
| 7136 | rtl8xxxu_write16(priv, REG_CR, val16); |
| 7137 | |
| 7138 | /* |
| 7139 | * Workaround for 8188RU LNA power leakage problem. |
| 7140 | */ |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 7141 | if (priv->rtl_chip == RTL8188C && priv->hi_pa) { |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7142 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); |
| 7143 | val32 &= ~BIT(1); |
| 7144 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); |
| 7145 | } |
| 7146 | return 0; |
| 7147 | } |
| 7148 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 7149 | #endif |
| 7150 | |
Jes Sorensen | 28e460b0 | 2016-04-07 14:19:33 -0400 | [diff] [blame] | 7151 | /* |
| 7152 | * This is needed for 8723bu as well, presumable |
| 7153 | */ |
| 7154 | static void rtl8192e_crystal_afe_adjust(struct rtl8xxxu_priv *priv) |
| 7155 | { |
| 7156 | u8 val8; |
| 7157 | u32 val32; |
| 7158 | |
| 7159 | /* |
| 7160 | * 40Mhz crystal source, MAC 0x28[2]=0 |
| 7161 | */ |
| 7162 | val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); |
| 7163 | val8 &= 0xfb; |
| 7164 | rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); |
| 7165 | |
| 7166 | val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); |
| 7167 | val32 &= 0xfffffc7f; |
| 7168 | rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); |
| 7169 | |
| 7170 | /* |
| 7171 | * 92e AFE parameter |
| 7172 | * AFE PLL KVCO selection, MAC 0x28[6]=1 |
| 7173 | */ |
| 7174 | val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL); |
| 7175 | val8 &= 0xbf; |
| 7176 | rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8); |
| 7177 | |
| 7178 | /* |
| 7179 | * AFE PLL KVCO selection, MAC 0x78[21]=0 |
| 7180 | */ |
| 7181 | val32 = rtl8xxxu_read32(priv, REG_AFE_CTRL4); |
| 7182 | val32 &= 0xffdfffff; |
| 7183 | rtl8xxxu_write32(priv, REG_AFE_CTRL4, val32); |
| 7184 | } |
| 7185 | |
Jes Sorensen | c05a9db | 2016-02-29 17:04:03 -0500 | [diff] [blame] | 7186 | static int rtl8192eu_power_on(struct rtl8xxxu_priv *priv) |
| 7187 | { |
| 7188 | u16 val16; |
| 7189 | u32 val32; |
| 7190 | int ret; |
| 7191 | |
| 7192 | ret = 0; |
| 7193 | |
| 7194 | val32 = rtl8xxxu_read32(priv, REG_SYS_CFG); |
| 7195 | if (val32 & SYS_CFG_SPS_LDO_SEL) { |
| 7196 | rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0xc3); |
| 7197 | } else { |
| 7198 | /* |
| 7199 | * Raise 1.2V voltage |
| 7200 | */ |
| 7201 | val32 = rtl8xxxu_read32(priv, REG_8192E_LDOV12_CTRL); |
| 7202 | val32 &= 0xff0fffff; |
| 7203 | val32 |= 0x00500000; |
| 7204 | rtl8xxxu_write32(priv, REG_8192E_LDOV12_CTRL, val32); |
| 7205 | rtl8xxxu_write8(priv, REG_LDO_SW_CTRL, 0x83); |
| 7206 | } |
| 7207 | |
Jes Sorensen | 28e460b0 | 2016-04-07 14:19:33 -0400 | [diff] [blame] | 7208 | /* |
| 7209 | * Adjust AFE before enabling PLL |
| 7210 | */ |
| 7211 | rtl8192e_crystal_afe_adjust(priv); |
Jes Sorensen | c05a9db | 2016-02-29 17:04:03 -0500 | [diff] [blame] | 7212 | rtl8192e_disabled_to_emu(priv); |
| 7213 | |
| 7214 | ret = rtl8192e_emu_to_active(priv); |
| 7215 | if (ret) |
| 7216 | goto exit; |
| 7217 | |
| 7218 | rtl8xxxu_write16(priv, REG_CR, 0x0000); |
| 7219 | |
| 7220 | /* |
| 7221 | * Enable MAC DMA/WMAC/SCHEDULE/SEC block |
| 7222 | * Set CR bit10 to enable 32k calibration. |
| 7223 | */ |
| 7224 | val16 = rtl8xxxu_read16(priv, REG_CR); |
| 7225 | val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE | |
| 7226 | CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | |
| 7227 | CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE | |
| 7228 | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE | |
| 7229 | CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE); |
| 7230 | rtl8xxxu_write16(priv, REG_CR, val16); |
| 7231 | |
| 7232 | exit: |
| 7233 | return ret; |
| 7234 | } |
| 7235 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7236 | static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv) |
| 7237 | { |
| 7238 | u8 val8; |
| 7239 | u16 val16; |
| 7240 | u32 val32; |
| 7241 | |
| 7242 | /* |
| 7243 | * Workaround for 8188RU LNA power leakage problem. |
| 7244 | */ |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 7245 | if (priv->rtl_chip == RTL8188C && priv->hi_pa) { |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7246 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM); |
| 7247 | val32 |= BIT(1); |
| 7248 | rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32); |
| 7249 | } |
| 7250 | |
Jes Sorensen | 430b454 | 2016-02-29 17:05:48 -0500 | [diff] [blame] | 7251 | rtl8xxxu_flush_fifo(priv); |
| 7252 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7253 | rtl8xxxu_active_to_lps(priv); |
| 7254 | |
| 7255 | /* Turn off RF */ |
| 7256 | rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00); |
| 7257 | |
| 7258 | /* Reset Firmware if running in RAM */ |
| 7259 | if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) |
| 7260 | rtl8xxxu_firmware_self_reset(priv); |
| 7261 | |
| 7262 | /* Reset MCU */ |
| 7263 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 7264 | val16 &= ~SYS_FUNC_CPU_ENABLE; |
| 7265 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 7266 | |
| 7267 | /* Reset MCU ready status */ |
| 7268 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); |
| 7269 | |
| 7270 | rtl8xxxu_active_to_emu(priv); |
| 7271 | rtl8xxxu_emu_to_disabled(priv); |
| 7272 | |
| 7273 | /* Reset MCU IO Wrapper */ |
| 7274 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
| 7275 | val8 &= ~BIT(0); |
| 7276 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); |
| 7277 | |
| 7278 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1); |
| 7279 | val8 |= BIT(0); |
| 7280 | rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8); |
| 7281 | |
| 7282 | /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */ |
| 7283 | rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e); |
| 7284 | } |
| 7285 | |
Jes Sorensen | fe37d5f | 2016-02-29 17:05:47 -0500 | [diff] [blame] | 7286 | static void rtl8723bu_power_off(struct rtl8xxxu_priv *priv) |
| 7287 | { |
| 7288 | u8 val8; |
| 7289 | u16 val16; |
| 7290 | |
Jes Sorensen | 430b454 | 2016-02-29 17:05:48 -0500 | [diff] [blame] | 7291 | rtl8xxxu_flush_fifo(priv); |
| 7292 | |
Jes Sorensen | fe37d5f | 2016-02-29 17:05:47 -0500 | [diff] [blame] | 7293 | /* |
| 7294 | * Disable TX report timer |
| 7295 | */ |
| 7296 | val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); |
| 7297 | val8 &= ~TX_REPORT_CTRL_TIMER_ENABLE; |
| 7298 | rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); |
| 7299 | |
| 7300 | rtl8xxxu_write16(priv, REG_CR, 0x0000); |
| 7301 | |
| 7302 | rtl8xxxu_active_to_lps(priv); |
| 7303 | |
| 7304 | /* Reset Firmware if running in RAM */ |
| 7305 | if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL) |
| 7306 | rtl8xxxu_firmware_self_reset(priv); |
| 7307 | |
| 7308 | /* Reset MCU */ |
| 7309 | val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC); |
| 7310 | val16 &= ~SYS_FUNC_CPU_ENABLE; |
| 7311 | rtl8xxxu_write16(priv, REG_SYS_FUNC, val16); |
| 7312 | |
| 7313 | /* Reset MCU ready status */ |
| 7314 | rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00); |
| 7315 | |
| 7316 | rtl8723bu_active_to_emu(priv); |
| 7317 | rtl8xxxu_emu_to_disabled(priv); |
| 7318 | } |
| 7319 | |
Jes Sorensen | a3a5dac | 2016-02-29 17:05:16 -0500 | [diff] [blame] | 7320 | #ifdef NEED_PS_TDMA |
Jes Sorensen | 3ca7b32 | 2016-02-29 17:04:43 -0500 | [diff] [blame] | 7321 | static void rtl8723bu_set_ps_tdma(struct rtl8xxxu_priv *priv, |
| 7322 | u8 arg1, u8 arg2, u8 arg3, u8 arg4, u8 arg5) |
| 7323 | { |
| 7324 | struct h2c_cmd h2c; |
| 7325 | |
| 7326 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 7327 | h2c.b_type_dma.cmd = H2C_8723B_B_TYPE_TDMA; |
| 7328 | h2c.b_type_dma.data1 = arg1; |
| 7329 | h2c.b_type_dma.data2 = arg2; |
| 7330 | h2c.b_type_dma.data3 = arg3; |
| 7331 | h2c.b_type_dma.data4 = arg4; |
| 7332 | h2c.b_type_dma.data5 = arg5; |
| 7333 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_type_dma)); |
| 7334 | } |
Jes Sorensen | a3a5dac | 2016-02-29 17:05:16 -0500 | [diff] [blame] | 7335 | #endif |
Jes Sorensen | 3ca7b32 | 2016-02-29 17:04:43 -0500 | [diff] [blame] | 7336 | |
Jes Sorensen | 0290e7d | 2016-02-29 17:05:44 -0500 | [diff] [blame] | 7337 | static void rtl8723b_enable_rf(struct rtl8xxxu_priv *priv) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7338 | { |
Jes Sorensen | f37e922 | 2016-02-29 17:04:41 -0500 | [diff] [blame] | 7339 | struct h2c_cmd h2c; |
| 7340 | u32 val32; |
| 7341 | u8 val8; |
| 7342 | |
| 7343 | /* |
| 7344 | * No indication anywhere as to what 0x0790 does. The 2 antenna |
| 7345 | * vendor code preserves bits 6-7 here. |
| 7346 | */ |
| 7347 | rtl8xxxu_write8(priv, 0x0790, 0x05); |
| 7348 | /* |
| 7349 | * 0x0778 seems to be related to enabling the number of antennas |
| 7350 | * In the vendor driver halbtc8723b2ant_InitHwConfig() sets it |
| 7351 | * to 0x03, while halbtc8723b1ant_InitHwConfig() sets it to 0x01 |
| 7352 | */ |
| 7353 | rtl8xxxu_write8(priv, 0x0778, 0x01); |
| 7354 | |
| 7355 | val8 = rtl8xxxu_read8(priv, REG_GPIO_MUXCFG); |
| 7356 | val8 |= BIT(5); |
| 7357 | rtl8xxxu_write8(priv, REG_GPIO_MUXCFG, val8); |
| 7358 | |
| 7359 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_IQADJ_G1, 0x780); |
| 7360 | |
Jes Sorensen | 394f1bd | 2016-02-29 17:04:49 -0500 | [diff] [blame] | 7361 | rtl8723bu_write_btreg(priv, 0x3c, 0x15); /* BT TRx Mask on */ |
| 7362 | |
Jes Sorensen | f37e922 | 2016-02-29 17:04:41 -0500 | [diff] [blame] | 7363 | /* |
| 7364 | * Set BT grant to low |
| 7365 | */ |
| 7366 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 7367 | h2c.bt_grant.cmd = H2C_8723B_BT_GRANT; |
| 7368 | h2c.bt_grant.data = 0; |
| 7369 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_grant)); |
| 7370 | |
| 7371 | /* |
| 7372 | * WLAN action by PTA |
| 7373 | */ |
Jes Sorensen | fc1c89b | 2016-02-29 17:05:12 -0500 | [diff] [blame] | 7374 | rtl8xxxu_write8(priv, REG_WLAN_ACT_CONTROL_8723B, 0x04); |
Jes Sorensen | f37e922 | 2016-02-29 17:04:41 -0500 | [diff] [blame] | 7375 | |
| 7376 | /* |
| 7377 | * BT select S0/S1 controlled by WiFi |
| 7378 | */ |
| 7379 | val8 = rtl8xxxu_read8(priv, 0x0067); |
| 7380 | val8 |= BIT(5); |
| 7381 | rtl8xxxu_write8(priv, 0x0067, val8); |
| 7382 | |
| 7383 | val32 = rtl8xxxu_read32(priv, REG_PWR_DATA); |
Jes Sorensen | 37f44dc | 2016-02-29 17:05:45 -0500 | [diff] [blame] | 7384 | val32 |= PWR_DATA_EEPRPAD_RFE_CTRL_EN; |
Jes Sorensen | f37e922 | 2016-02-29 17:04:41 -0500 | [diff] [blame] | 7385 | rtl8xxxu_write32(priv, REG_PWR_DATA, val32); |
| 7386 | |
| 7387 | /* |
| 7388 | * Bits 6/7 are marked in/out ... but for what? |
| 7389 | */ |
| 7390 | rtl8xxxu_write8(priv, 0x0974, 0xff); |
| 7391 | |
Jes Sorensen | 120e627 | 2016-02-29 17:05:14 -0500 | [diff] [blame] | 7392 | val32 = rtl8xxxu_read32(priv, REG_RFE_BUFFER); |
Jes Sorensen | f37e922 | 2016-02-29 17:04:41 -0500 | [diff] [blame] | 7393 | val32 |= (BIT(0) | BIT(1)); |
Jes Sorensen | 120e627 | 2016-02-29 17:05:14 -0500 | [diff] [blame] | 7394 | rtl8xxxu_write32(priv, REG_RFE_BUFFER, val32); |
Jes Sorensen | f37e922 | 2016-02-29 17:04:41 -0500 | [diff] [blame] | 7395 | |
| 7396 | rtl8xxxu_write8(priv, REG_RFE_CTRL_ANTA_SRC, 0x77); |
| 7397 | |
| 7398 | val32 = rtl8xxxu_read32(priv, REG_LEDCFG0); |
| 7399 | val32 &= ~BIT(24); |
| 7400 | val32 |= BIT(23); |
| 7401 | rtl8xxxu_write32(priv, REG_LEDCFG0, val32); |
| 7402 | |
| 7403 | /* |
| 7404 | * Fix external switch Main->S1, Aux->S0 |
| 7405 | */ |
| 7406 | val8 = rtl8xxxu_read8(priv, REG_PAD_CTRL1); |
| 7407 | val8 &= ~BIT(0); |
| 7408 | rtl8xxxu_write8(priv, REG_PAD_CTRL1, val8); |
| 7409 | |
| 7410 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 7411 | h2c.ant_sel_rsv.cmd = H2C_8723B_ANT_SEL_RSV; |
| 7412 | h2c.ant_sel_rsv.ant_inverse = 1; |
| 7413 | h2c.ant_sel_rsv.int_switch_type = 0; |
| 7414 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ant_sel_rsv)); |
| 7415 | |
| 7416 | /* |
| 7417 | * 0x280, 0x00, 0x200, 0x80 - not clear |
| 7418 | */ |
Jes Sorensen | 3ca7b32 | 2016-02-29 17:04:43 -0500 | [diff] [blame] | 7419 | rtl8xxxu_write32(priv, REG_S0S1_PATH_SWITCH, 0x00); |
| 7420 | |
| 7421 | /* |
| 7422 | * Software control, antenna at WiFi side |
| 7423 | */ |
Jes Sorensen | a3a5dac | 2016-02-29 17:05:16 -0500 | [diff] [blame] | 7424 | #ifdef NEED_PS_TDMA |
Jes Sorensen | a228a5d | 2016-02-29 17:04:45 -0500 | [diff] [blame] | 7425 | rtl8723bu_set_ps_tdma(priv, 0x08, 0x00, 0x00, 0x00, 0x00); |
Jes Sorensen | a3a5dac | 2016-02-29 17:05:16 -0500 | [diff] [blame] | 7426 | #endif |
| 7427 | |
| 7428 | rtl8xxxu_write32(priv, REG_BT_COEX_TABLE1, 0x55555555); |
| 7429 | rtl8xxxu_write32(priv, REG_BT_COEX_TABLE2, 0x55555555); |
| 7430 | rtl8xxxu_write32(priv, REG_BT_COEX_TABLE3, 0x00ffffff); |
| 7431 | rtl8xxxu_write8(priv, REG_BT_COEX_TABLE4, 0x03); |
Jes Sorensen | 3ca7b32 | 2016-02-29 17:04:43 -0500 | [diff] [blame] | 7432 | |
Jes Sorensen | 6b9eae0 | 2016-02-29 17:04:50 -0500 | [diff] [blame] | 7433 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 7434 | h2c.bt_info.cmd = H2C_8723B_BT_INFO; |
| 7435 | h2c.bt_info.data = BIT(0); |
| 7436 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.bt_info)); |
| 7437 | |
Jes Sorensen | 6b9eae0 | 2016-02-29 17:04:50 -0500 | [diff] [blame] | 7438 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 7439 | h2c.ignore_wlan.cmd = H2C_8723B_BT_IGNORE_WLANACT; |
| 7440 | h2c.ignore_wlan.data = 0; |
| 7441 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ignore_wlan)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7442 | } |
| 7443 | |
Jes Sorensen | fc89a41 | 2016-02-29 17:05:46 -0500 | [diff] [blame] | 7444 | static void rtl8723b_disable_rf(struct rtl8xxxu_priv *priv) |
| 7445 | { |
| 7446 | u32 val32; |
| 7447 | |
| 7448 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); |
| 7449 | |
| 7450 | val32 = rtl8xxxu_read32(priv, REG_RX_WAIT_CCA); |
| 7451 | val32 &= ~(BIT(22) | BIT(23)); |
| 7452 | rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, val32); |
| 7453 | } |
| 7454 | |
Jes Sorensen | 3e88ca4 | 2016-02-29 17:05:08 -0500 | [diff] [blame] | 7455 | static void rtl8723bu_init_aggregation(struct rtl8xxxu_priv *priv) |
| 7456 | { |
| 7457 | u32 agg_rx; |
| 7458 | u8 agg_ctrl; |
| 7459 | |
| 7460 | /* |
| 7461 | * For now simply disable RX aggregation |
| 7462 | */ |
| 7463 | agg_ctrl = rtl8xxxu_read8(priv, REG_TRXDMA_CTRL); |
| 7464 | agg_ctrl &= ~TRXDMA_CTRL_RXDMA_AGG_EN; |
| 7465 | |
| 7466 | agg_rx = rtl8xxxu_read32(priv, REG_RXDMA_AGG_PG_TH); |
| 7467 | agg_rx &= ~RXDMA_USB_AGG_ENABLE; |
| 7468 | agg_rx &= ~0xff0f; |
| 7469 | |
| 7470 | rtl8xxxu_write8(priv, REG_TRXDMA_CTRL, agg_ctrl); |
| 7471 | rtl8xxxu_write32(priv, REG_RXDMA_AGG_PG_TH, agg_rx); |
| 7472 | } |
| 7473 | |
Jes Sorensen | 9c79bf9 | 2016-02-29 17:05:10 -0500 | [diff] [blame] | 7474 | static void rtl8723bu_init_statistics(struct rtl8xxxu_priv *priv) |
| 7475 | { |
| 7476 | u32 val32; |
| 7477 | |
| 7478 | /* Time duration for NHM unit: 4us, 0x2710=40ms */ |
| 7479 | rtl8xxxu_write16(priv, REG_NHM_TIMER_8723B + 2, 0x2710); |
| 7480 | rtl8xxxu_write16(priv, REG_NHM_TH9_TH10_8723B + 2, 0xffff); |
| 7481 | rtl8xxxu_write32(priv, REG_NHM_TH3_TO_TH0_8723B, 0xffffff52); |
| 7482 | rtl8xxxu_write32(priv, REG_NHM_TH7_TO_TH4_8723B, 0xffffffff); |
| 7483 | /* TH8 */ |
| 7484 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_IQK); |
| 7485 | val32 |= 0xff; |
| 7486 | rtl8xxxu_write32(priv, REG_FPGA0_IQK, val32); |
| 7487 | /* Enable CCK */ |
| 7488 | val32 = rtl8xxxu_read32(priv, REG_NHM_TH9_TH10_8723B); |
| 7489 | val32 |= BIT(8) | BIT(9) | BIT(10); |
| 7490 | rtl8xxxu_write32(priv, REG_NHM_TH9_TH10_8723B, val32); |
| 7491 | /* Max power amongst all RX antennas */ |
| 7492 | val32 = rtl8xxxu_read32(priv, REG_OFDM0_FA_RSTC); |
| 7493 | val32 |= BIT(7); |
| 7494 | rtl8xxxu_write32(priv, REG_OFDM0_FA_RSTC, val32); |
| 7495 | } |
| 7496 | |
Jes Sorensen | 89c2a09 | 2016-04-14 14:58:44 -0400 | [diff] [blame] | 7497 | static void rtl8xxxu_old_init_queue_reserved_page(struct rtl8xxxu_priv *priv) |
| 7498 | { |
| 7499 | u8 val8; |
| 7500 | u32 val32; |
| 7501 | |
| 7502 | if (priv->ep_tx_normal_queue) |
| 7503 | val8 = TX_PAGE_NUM_NORM_PQ; |
| 7504 | else |
| 7505 | val8 = 0; |
| 7506 | |
| 7507 | rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8); |
| 7508 | |
| 7509 | val32 = (TX_PAGE_NUM_PUBQ << RQPN_PUB_PQ_SHIFT) | RQPN_LOAD; |
| 7510 | |
| 7511 | if (priv->ep_tx_high_queue) |
| 7512 | val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT); |
| 7513 | if (priv->ep_tx_low_queue) |
| 7514 | val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT); |
| 7515 | |
| 7516 | rtl8xxxu_write32(priv, REG_RQPN, val32); |
| 7517 | } |
| 7518 | |
| 7519 | static void rtl8xxxu_init_queue_reserved_page(struct rtl8xxxu_priv *priv) |
| 7520 | { |
| 7521 | struct rtl8xxxu_fileops *fops = priv->fops; |
| 7522 | u32 hq, lq, nq, eq, pubq; |
| 7523 | u32 val32; |
| 7524 | |
| 7525 | hq = 0; |
| 7526 | lq = 0; |
| 7527 | nq = 0; |
| 7528 | eq = 0; |
| 7529 | pubq = 0; |
| 7530 | |
| 7531 | if (priv->ep_tx_high_queue) |
| 7532 | hq = fops->page_num_hi; |
| 7533 | if (priv->ep_tx_low_queue) |
| 7534 | lq = fops->page_num_lo; |
| 7535 | if (priv->ep_tx_normal_queue) |
| 7536 | nq = fops->page_num_norm; |
| 7537 | |
| 7538 | val32 = (nq << RQPN_NPQ_SHIFT) | (eq << RQPN_EPQ_SHIFT); |
| 7539 | rtl8xxxu_write32(priv, REG_RQPN_NPQ, val32); |
| 7540 | |
| 7541 | pubq = fops->total_page_num - hq - lq - nq; |
| 7542 | |
| 7543 | val32 = RQPN_LOAD; |
| 7544 | val32 |= (hq << RQPN_HI_PQ_SHIFT); |
| 7545 | val32 |= (lq << RQPN_LO_PQ_SHIFT); |
| 7546 | val32 |= (pubq << RQPN_PUB_PQ_SHIFT); |
| 7547 | |
| 7548 | rtl8xxxu_write32(priv, REG_RQPN, val32); |
| 7549 | } |
| 7550 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7551 | static int rtl8xxxu_init_device(struct ieee80211_hw *hw) |
| 7552 | { |
| 7553 | struct rtl8xxxu_priv *priv = hw->priv; |
| 7554 | struct device *dev = &priv->udev->dev; |
| 7555 | struct rtl8xxxu_rfregval *rftable; |
| 7556 | bool macpower; |
| 7557 | int ret; |
| 7558 | u8 val8; |
| 7559 | u16 val16; |
| 7560 | u32 val32; |
| 7561 | |
| 7562 | /* Check if MAC is already powered on */ |
| 7563 | val8 = rtl8xxxu_read8(priv, REG_CR); |
| 7564 | |
| 7565 | /* |
| 7566 | * Fix 92DU-VC S3 hang with the reason is that secondary mac is not |
| 7567 | * initialized. First MAC returns 0xea, second MAC returns 0x00 |
| 7568 | */ |
| 7569 | if (val8 == 0xea) |
| 7570 | macpower = false; |
| 7571 | else |
| 7572 | macpower = true; |
| 7573 | |
| 7574 | ret = priv->fops->power_on(priv); |
| 7575 | if (ret < 0) { |
| 7576 | dev_warn(dev, "%s: Failed power on\n", __func__); |
| 7577 | goto exit; |
| 7578 | } |
| 7579 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7580 | if (!macpower) { |
Jes Sorensen | 89c2a09 | 2016-04-14 14:58:44 -0400 | [diff] [blame] | 7581 | if (priv->fops->total_page_num) |
| 7582 | rtl8xxxu_init_queue_reserved_page(priv); |
Jes Sorensen | 59b24da | 2016-04-14 14:58:43 -0400 | [diff] [blame] | 7583 | else |
Jes Sorensen | 89c2a09 | 2016-04-14 14:58:44 -0400 | [diff] [blame] | 7584 | rtl8xxxu_old_init_queue_reserved_page(priv); |
Jes Sorensen | 07bb46b | 2016-02-29 17:04:05 -0500 | [diff] [blame] | 7585 | } |
| 7586 | |
Jes Sorensen | 59b24da | 2016-04-14 14:58:43 -0400 | [diff] [blame] | 7587 | ret = rtl8xxxu_init_queue_priority(priv); |
| 7588 | dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret); |
| 7589 | if (ret) |
| 7590 | goto exit; |
| 7591 | |
| 7592 | /* |
| 7593 | * Set RX page boundary |
| 7594 | */ |
Jes Sorensen | 24e8e7e | 2016-04-14 14:59:01 -0400 | [diff] [blame] | 7595 | rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, priv->fops->trxff_boundary); |
Jes Sorensen | 59b24da | 2016-04-14 14:58:43 -0400 | [diff] [blame] | 7596 | |
Jes Sorensen | a47b9d4 | 2016-02-29 17:04:06 -0500 | [diff] [blame] | 7597 | ret = rtl8xxxu_download_firmware(priv); |
| 7598 | dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret); |
| 7599 | if (ret) |
| 7600 | goto exit; |
| 7601 | ret = rtl8xxxu_start_firmware(priv); |
| 7602 | dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret); |
| 7603 | if (ret) |
| 7604 | goto exit; |
| 7605 | |
Jes Sorensen | f0d9f5e | 2016-02-29 17:04:16 -0500 | [diff] [blame] | 7606 | if (priv->fops->phy_init_antenna_selection) |
| 7607 | priv->fops->phy_init_antenna_selection(priv); |
| 7608 | |
Jes Sorensen | c606e66 | 2016-04-07 14:19:16 -0400 | [diff] [blame] | 7609 | ret = rtl8xxxu_init_mac(priv); |
Jes Sorensen | b7dd8ff | 2016-02-29 17:04:17 -0500 | [diff] [blame] | 7610 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7611 | dev_dbg(dev, "%s: init_mac %i\n", __func__, ret); |
| 7612 | if (ret) |
| 7613 | goto exit; |
| 7614 | |
| 7615 | ret = rtl8xxxu_init_phy_bb(priv); |
| 7616 | dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret); |
| 7617 | if (ret) |
| 7618 | goto exit; |
| 7619 | |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 7620 | switch(priv->rtl_chip) { |
| 7621 | case RTL8723A: |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7622 | rftable = rtl8723au_radioa_1t_init_table; |
| 7623 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); |
Jes Sorensen | 747bf23 | 2016-04-14 14:59:04 -0400 | [diff] [blame] | 7624 | |
| 7625 | /* Reduce 80M spur */ |
| 7626 | rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d); |
| 7627 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); |
| 7628 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82); |
| 7629 | rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7630 | break; |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 7631 | case RTL8723B: |
Jes Sorensen | 22a31d4 | 2016-02-29 17:04:15 -0500 | [diff] [blame] | 7632 | rftable = rtl8723bu_radioa_1t_init_table; |
| 7633 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); |
Jes Sorensen | 5ac6178 | 2016-02-29 17:05:05 -0500 | [diff] [blame] | 7634 | /* |
| 7635 | * PHY LCK |
| 7636 | */ |
| 7637 | rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdfbe0); |
| 7638 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, 0x8c01); |
| 7639 | msleep(200); |
| 7640 | rtl8xxxu_write_rfreg(priv, RF_A, 0xb0, 0xdffe0); |
Jes Sorensen | 22a31d4 | 2016-02-29 17:04:15 -0500 | [diff] [blame] | 7641 | break; |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 7642 | case RTL8188C: |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7643 | if (priv->hi_pa) |
| 7644 | rftable = rtl8188ru_radioa_1t_highpa_table; |
| 7645 | else |
| 7646 | rftable = rtl8192cu_radioa_1t_init_table; |
| 7647 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); |
| 7648 | break; |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 7649 | case RTL8191C: |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7650 | rftable = rtl8192cu_radioa_1t_init_table; |
| 7651 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); |
| 7652 | break; |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 7653 | case RTL8192C: |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7654 | rftable = rtl8192cu_radioa_2t_init_table; |
| 7655 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); |
| 7656 | if (ret) |
| 7657 | break; |
| 7658 | rftable = rtl8192cu_radiob_2t_init_table; |
| 7659 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B); |
| 7660 | break; |
Jes Sorensen | 19102f8 | 2016-04-07 14:19:19 -0400 | [diff] [blame] | 7661 | case RTL8192E: |
| 7662 | rftable = rtl8192eu_radioa_init_table; |
| 7663 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A); |
| 7664 | if (ret) |
| 7665 | break; |
| 7666 | rftable = rtl8192eu_radiob_init_table; |
| 7667 | ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B); |
| 7668 | break; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7669 | default: |
| 7670 | ret = -EINVAL; |
| 7671 | } |
| 7672 | |
| 7673 | if (ret) |
| 7674 | goto exit; |
| 7675 | |
Jes Sorensen | c157863 | 2016-04-14 14:58:42 -0400 | [diff] [blame] | 7676 | /* RFSW Control - clear bit 14 ?? */ |
Jes Sorensen | b816901 | 2016-04-14 14:58:47 -0400 | [diff] [blame] | 7677 | if (priv->rtl_chip != RTL8723B && priv->rtl_chip != RTL8192E) |
Jes Sorensen | c157863 | 2016-04-14 14:58:42 -0400 | [diff] [blame] | 7678 | rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003); |
Jes Sorensen | 31133da | 2016-04-14 14:59:05 -0400 | [diff] [blame] | 7679 | |
| 7680 | val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW | |
| 7681 | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE | |
| 7682 | ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) << |
| 7683 | FPGA0_RF_BD_CTRL_SHIFT); |
| 7684 | |
Jes Sorensen | c157863 | 2016-04-14 14:58:42 -0400 | [diff] [blame] | 7685 | rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32); |
| 7686 | /* 0x860[6:5]= 00 - why? - this sets antenna B */ |
| 7687 | if (priv->rtl_chip != RTL8192E) |
| 7688 | rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66f60210); |
| 7689 | |
Jes Sorensen | f2a4163 | 2016-02-29 17:05:09 -0500 | [diff] [blame] | 7690 | if (!macpower) { |
Jes Sorensen | 1f1b20f | 2016-02-29 17:05:00 -0500 | [diff] [blame] | 7691 | /* |
| 7692 | * Set TX buffer boundary |
| 7693 | */ |
Jes Sorensen | 80805aa | 2016-04-07 14:19:18 -0400 | [diff] [blame] | 7694 | if (priv->rtl_chip == RTL8192E) |
| 7695 | val8 = TX_TOTAL_PAGE_NUM_8192E + 1; |
| 7696 | else |
| 7697 | val8 = TX_TOTAL_PAGE_NUM + 1; |
Jes Sorensen | 1f1b20f | 2016-02-29 17:05:00 -0500 | [diff] [blame] | 7698 | |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 7699 | if (priv->rtl_chip == RTL8723B) |
Jes Sorensen | 1f1b20f | 2016-02-29 17:05:00 -0500 | [diff] [blame] | 7700 | val8 -= 1; |
| 7701 | |
| 7702 | rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8); |
| 7703 | rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8); |
| 7704 | rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8); |
| 7705 | rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8); |
| 7706 | rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8); |
| 7707 | } |
| 7708 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7709 | /* |
Jes Sorensen | 9b323ee | 2016-04-14 14:59:03 -0400 | [diff] [blame] | 7710 | * The vendor drivers set PBP for all devices, except 8192e. |
| 7711 | * There is no explanation for this in any of the sources. |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7712 | */ |
Jes Sorensen | 9b323ee | 2016-04-14 14:59:03 -0400 | [diff] [blame] | 7713 | val8 = (priv->fops->pbp_rx << PBP_PAGE_SIZE_RX_SHIFT) | |
| 7714 | (priv->fops->pbp_tx << PBP_PAGE_SIZE_TX_SHIFT); |
Jes Sorensen | 2e7c7b3 | 2016-04-14 14:58:46 -0400 | [diff] [blame] | 7715 | if (priv->rtl_chip != RTL8192E) |
| 7716 | rtl8xxxu_write8(priv, REG_PBP, val8); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7717 | |
Jes Sorensen | 59b24da | 2016-04-14 14:58:43 -0400 | [diff] [blame] | 7718 | dev_dbg(dev, "%s: macpower %i\n", __func__, macpower); |
| 7719 | if (!macpower) { |
| 7720 | ret = priv->fops->llt_init(priv, TX_TOTAL_PAGE_NUM); |
| 7721 | if (ret) { |
| 7722 | dev_warn(dev, "%s: LLT table init failed\n", __func__); |
| 7723 | goto exit; |
| 7724 | } |
| 7725 | |
| 7726 | /* |
Jes Sorensen | 0486e80 | 2016-04-14 14:58:45 -0400 | [diff] [blame] | 7727 | * Chip specific quirks |
| 7728 | */ |
Jes Sorensen | 747bf23 | 2016-04-14 14:59:04 -0400 | [diff] [blame] | 7729 | priv->fops->usb_quirks(priv); |
Jes Sorensen | 0486e80 | 2016-04-14 14:58:45 -0400 | [diff] [blame] | 7730 | |
| 7731 | /* |
Jes Sorensen | 59b24da | 2016-04-14 14:58:43 -0400 | [diff] [blame] | 7732 | * Presumably this is for 8188EU as well |
| 7733 | * Enable TX report and TX report timer |
| 7734 | */ |
| 7735 | if (priv->rtl_chip == RTL8723B) { |
| 7736 | val8 = rtl8xxxu_read8(priv, REG_TX_REPORT_CTRL); |
| 7737 | val8 |= TX_REPORT_CTRL_TIMER_ENABLE; |
| 7738 | rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL, val8); |
| 7739 | /* Set MAX RPT MACID */ |
| 7740 | rtl8xxxu_write8(priv, REG_TX_REPORT_CTRL + 1, 0x02); |
| 7741 | /* TX report Timer. Unit: 32us */ |
| 7742 | rtl8xxxu_write16(priv, REG_TX_REPORT_TIME, 0xcdf0); |
| 7743 | |
| 7744 | /* tmp ps ? */ |
| 7745 | val8 = rtl8xxxu_read8(priv, 0xa3); |
| 7746 | val8 &= 0xf8; |
| 7747 | rtl8xxxu_write8(priv, 0xa3, val8); |
| 7748 | } |
| 7749 | } |
| 7750 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7751 | /* |
| 7752 | * Unit in 8 bytes, not obvious what it is used for |
| 7753 | */ |
| 7754 | rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4); |
| 7755 | |
Jes Sorensen | 57e5e2e | 2016-04-07 14:19:27 -0400 | [diff] [blame] | 7756 | if (priv->rtl_chip == RTL8192E) { |
| 7757 | rtl8xxxu_write32(priv, REG_HIMR0, 0x00); |
| 7758 | rtl8xxxu_write32(priv, REG_HIMR1, 0x00); |
| 7759 | } else { |
| 7760 | /* |
| 7761 | * Enable all interrupts - not obvious USB needs to do this |
| 7762 | */ |
| 7763 | rtl8xxxu_write32(priv, REG_HISR, 0xffffffff); |
| 7764 | rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff); |
| 7765 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7766 | |
| 7767 | rtl8xxxu_set_mac(priv); |
| 7768 | rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION); |
| 7769 | |
| 7770 | /* |
| 7771 | * Configure initial WMAC settings |
| 7772 | */ |
| 7773 | val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7774 | RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL | |
| 7775 | RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC; |
| 7776 | rtl8xxxu_write32(priv, REG_RCR, val32); |
| 7777 | |
| 7778 | /* |
| 7779 | * Accept all multicast |
| 7780 | */ |
| 7781 | rtl8xxxu_write32(priv, REG_MAR, 0xffffffff); |
| 7782 | rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff); |
| 7783 | |
| 7784 | /* |
| 7785 | * Init adaptive controls |
| 7786 | */ |
| 7787 | val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); |
| 7788 | val32 &= ~RESPONSE_RATE_BITMAP_ALL; |
| 7789 | val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M; |
| 7790 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); |
| 7791 | |
| 7792 | /* CCK = 0x0a, OFDM = 0x10 */ |
| 7793 | rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10); |
| 7794 | rtl8xxxu_set_retry(priv, 0x30, 0x30); |
| 7795 | rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10); |
| 7796 | |
| 7797 | /* |
| 7798 | * Init EDCA |
| 7799 | */ |
| 7800 | rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a); |
| 7801 | |
| 7802 | /* Set CCK SIFS */ |
| 7803 | rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a); |
| 7804 | |
| 7805 | /* Set OFDM SIFS */ |
| 7806 | rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a); |
| 7807 | |
| 7808 | /* TXOP */ |
| 7809 | rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b); |
| 7810 | rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f); |
| 7811 | rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324); |
| 7812 | rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226); |
| 7813 | |
| 7814 | /* Set data auto rate fallback retry count */ |
| 7815 | rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000); |
| 7816 | rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404); |
| 7817 | rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201); |
| 7818 | rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605); |
| 7819 | |
| 7820 | val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL); |
| 7821 | val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY; |
| 7822 | rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8); |
| 7823 | |
| 7824 | /* Set ACK timeout */ |
| 7825 | rtl8xxxu_write8(priv, REG_ACKTO, 0x40); |
| 7826 | |
| 7827 | /* |
| 7828 | * Initialize beacon parameters |
| 7829 | */ |
| 7830 | val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8); |
| 7831 | rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16); |
| 7832 | rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404); |
| 7833 | rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME); |
| 7834 | rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME); |
| 7835 | rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F); |
| 7836 | |
| 7837 | /* |
Jes Sorensen | c369060 | 2016-02-29 17:05:03 -0500 | [diff] [blame] | 7838 | * Initialize burst parameters |
| 7839 | */ |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 7840 | if (priv->rtl_chip == RTL8723B) { |
Jes Sorensen | c369060 | 2016-02-29 17:05:03 -0500 | [diff] [blame] | 7841 | /* |
| 7842 | * For USB high speed set 512B packets |
| 7843 | */ |
| 7844 | val8 = rtl8xxxu_read8(priv, REG_RXDMA_PRO_8723B); |
| 7845 | val8 &= ~(BIT(4) | BIT(5)); |
| 7846 | val8 |= BIT(4); |
| 7847 | val8 |= BIT(1) | BIT(2) | BIT(3); |
| 7848 | rtl8xxxu_write8(priv, REG_RXDMA_PRO_8723B, val8); |
| 7849 | |
| 7850 | /* |
| 7851 | * For USB high speed set 512B packets |
| 7852 | */ |
| 7853 | val8 = rtl8xxxu_read8(priv, REG_HT_SINGLE_AMPDU_8723B); |
| 7854 | val8 |= BIT(7); |
| 7855 | rtl8xxxu_write8(priv, REG_HT_SINGLE_AMPDU_8723B, val8); |
| 7856 | |
| 7857 | rtl8xxxu_write16(priv, REG_MAX_AGGR_NUM, 0x0c14); |
| 7858 | rtl8xxxu_write8(priv, REG_AMPDU_MAX_TIME_8723B, 0x5e); |
| 7859 | rtl8xxxu_write32(priv, REG_AGGLEN_LMT, 0xffffffff); |
| 7860 | rtl8xxxu_write8(priv, REG_RX_PKT_LIMIT, 0x18); |
| 7861 | rtl8xxxu_write8(priv, REG_PIFS, 0x00); |
| 7862 | rtl8xxxu_write8(priv, REG_USTIME_TSF_8723B, 0x50); |
| 7863 | rtl8xxxu_write8(priv, REG_USTIME_EDCA, 0x50); |
| 7864 | |
| 7865 | val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL); |
| 7866 | val8 |= BIT(5) | BIT(6); |
| 7867 | rtl8xxxu_write8(priv, REG_RSV_CTRL, val8); |
| 7868 | } |
| 7869 | |
Jes Sorensen | 3e88ca4 | 2016-02-29 17:05:08 -0500 | [diff] [blame] | 7870 | if (priv->fops->init_aggregation) |
| 7871 | priv->fops->init_aggregation(priv); |
| 7872 | |
Jes Sorensen | c369060 | 2016-02-29 17:05:03 -0500 | [diff] [blame] | 7873 | /* |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7874 | * Enable CCK and OFDM block |
| 7875 | */ |
| 7876 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 7877 | val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM); |
| 7878 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 7879 | |
| 7880 | /* |
| 7881 | * Invalidate all CAM entries - bit 30 is undocumented |
| 7882 | */ |
| 7883 | rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30)); |
| 7884 | |
| 7885 | /* |
| 7886 | * Start out with default power levels for channel 6, 20MHz |
| 7887 | */ |
Jes Sorensen | e796dab | 2016-02-29 17:05:19 -0500 | [diff] [blame] | 7888 | priv->fops->set_tx_power(priv, 1, false); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7889 | |
| 7890 | /* Let the 8051 take control of antenna setting */ |
Jes Sorensen | 5bdb6b0 | 2016-04-14 14:58:48 -0400 | [diff] [blame] | 7891 | if (priv->rtl_chip != RTL8192E) { |
| 7892 | val8 = rtl8xxxu_read8(priv, REG_LEDCFG2); |
| 7893 | val8 |= LEDCFG2_DPDT_SELECT; |
| 7894 | rtl8xxxu_write8(priv, REG_LEDCFG2, val8); |
| 7895 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7896 | |
| 7897 | rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff); |
| 7898 | |
| 7899 | /* Disable BAR - not sure if this has any effect on USB */ |
| 7900 | rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff); |
| 7901 | |
| 7902 | rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0); |
| 7903 | |
Jes Sorensen | 9c79bf9 | 2016-02-29 17:05:10 -0500 | [diff] [blame] | 7904 | if (priv->fops->init_statistics) |
| 7905 | priv->fops->init_statistics(priv); |
| 7906 | |
Jes Sorensen | b052b7f | 2016-04-07 14:19:30 -0400 | [diff] [blame] | 7907 | if (priv->rtl_chip == RTL8192E) { |
| 7908 | /* |
| 7909 | * 0x4c6[3] 1: RTS BW = Data BW |
| 7910 | * 0: RTS BW depends on CCA / secondary CCA result. |
| 7911 | */ |
| 7912 | val8 = rtl8xxxu_read8(priv, REG_QUEUE_CTRL); |
| 7913 | val8 &= ~BIT(3); |
| 7914 | rtl8xxxu_write8(priv, REG_QUEUE_CTRL, val8); |
| 7915 | /* |
| 7916 | * Reset USB mode switch setting |
| 7917 | */ |
| 7918 | rtl8xxxu_write8(priv, REG_ACLK_MON, 0x00); |
| 7919 | } |
| 7920 | |
Jes Sorensen | fa0f2d4 | 2016-02-29 17:04:37 -0500 | [diff] [blame] | 7921 | rtl8723a_phy_lc_calibrate(priv); |
| 7922 | |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 7923 | priv->fops->phy_iq_calibrate(priv); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7924 | |
| 7925 | /* |
| 7926 | * This should enable thermal meter |
| 7927 | */ |
Jes Sorensen | 55c0b6a | 2016-04-14 14:58:50 -0400 | [diff] [blame] | 7928 | if (priv->fops->tx_desc_size == sizeof(struct rtl8xxxu_txdesc40)) |
Jes Sorensen | 72143b9 | 2016-02-29 17:05:25 -0500 | [diff] [blame] | 7929 | rtl8xxxu_write_rfreg(priv, |
| 7930 | RF_A, RF6052_REG_T_METER_8723B, 0x37cf8); |
| 7931 | else |
| 7932 | rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7933 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7934 | /* Set NAV_UPPER to 30000us */ |
| 7935 | val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT); |
| 7936 | rtl8xxxu_write8(priv, REG_NAV_UPPER, val8); |
| 7937 | |
Jes Sorensen | ba17d82 | 2016-03-31 17:08:39 -0400 | [diff] [blame] | 7938 | if (priv->rtl_chip == RTL8723A) { |
Jes Sorensen | 4042e61 | 2016-02-03 13:40:01 -0500 | [diff] [blame] | 7939 | /* |
| 7940 | * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test, |
| 7941 | * but we need to find root cause. |
| 7942 | * This is 8723au only. |
| 7943 | */ |
| 7944 | val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE); |
| 7945 | if ((val32 & 0xff000000) != 0x83000000) { |
| 7946 | val32 |= FPGA_RF_MODE_CCK; |
| 7947 | rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32); |
| 7948 | } |
Jes Sorensen | 3021e51 | 2016-04-07 14:19:28 -0400 | [diff] [blame] | 7949 | } else if (priv->rtl_chip == RTL8192E) { |
| 7950 | rtl8xxxu_write8(priv, REG_USB_HRPWM, 0x00); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7951 | } |
| 7952 | |
| 7953 | val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL); |
| 7954 | val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK; |
| 7955 | /* ack for xmit mgmt frames. */ |
| 7956 | rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32); |
| 7957 | |
Jes Sorensen | e1394fe | 2016-04-07 14:19:29 -0400 | [diff] [blame] | 7958 | if (priv->rtl_chip == RTL8192E) { |
| 7959 | /* |
| 7960 | * Fix LDPC rx hang issue. |
| 7961 | */ |
| 7962 | val32 = rtl8xxxu_read32(priv, REG_AFE_MISC); |
| 7963 | rtl8xxxu_write8(priv, REG_8192E_LDOV12_CTRL, 0x75); |
| 7964 | val32 &= 0xfff00fff; |
| 7965 | val32 |= 0x0007e000; |
Jes Sorensen | 46b3783 | 2016-04-14 14:59:06 -0400 | [diff] [blame] | 7966 | rtl8xxxu_write32(priv, REG_AFE_MISC, val32); |
Jes Sorensen | e1394fe | 2016-04-07 14:19:29 -0400 | [diff] [blame] | 7967 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7968 | exit: |
| 7969 | return ret; |
| 7970 | } |
| 7971 | |
| 7972 | static void rtl8xxxu_disable_device(struct ieee80211_hw *hw) |
| 7973 | { |
| 7974 | struct rtl8xxxu_priv *priv = hw->priv; |
| 7975 | |
Jes Sorensen | fe37d5f | 2016-02-29 17:05:47 -0500 | [diff] [blame] | 7976 | priv->fops->power_off(priv); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 7977 | } |
| 7978 | |
| 7979 | static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv, |
| 7980 | struct ieee80211_key_conf *key, const u8 *mac) |
| 7981 | { |
| 7982 | u32 cmd, val32, addr, ctrl; |
| 7983 | int j, i, tmp_debug; |
| 7984 | |
| 7985 | tmp_debug = rtl8xxxu_debug; |
| 7986 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY) |
| 7987 | rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE; |
| 7988 | |
| 7989 | /* |
| 7990 | * This is a bit of a hack - the lower bits of the cipher |
| 7991 | * suite selector happens to match the cipher index in the CAM |
| 7992 | */ |
| 7993 | addr = key->keyidx << CAM_CMD_KEY_SHIFT; |
| 7994 | ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID; |
| 7995 | |
| 7996 | for (j = 5; j >= 0; j--) { |
| 7997 | switch (j) { |
| 7998 | case 0: |
| 7999 | val32 = ctrl | (mac[0] << 16) | (mac[1] << 24); |
| 8000 | break; |
| 8001 | case 1: |
| 8002 | val32 = mac[2] | (mac[3] << 8) | |
| 8003 | (mac[4] << 16) | (mac[5] << 24); |
| 8004 | break; |
| 8005 | default: |
| 8006 | i = (j - 2) << 2; |
| 8007 | val32 = key->key[i] | (key->key[i + 1] << 8) | |
| 8008 | key->key[i + 2] << 16 | key->key[i + 3] << 24; |
| 8009 | break; |
| 8010 | } |
| 8011 | |
| 8012 | rtl8xxxu_write32(priv, REG_CAM_WRITE, val32); |
| 8013 | cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j); |
| 8014 | rtl8xxxu_write32(priv, REG_CAM_CMD, cmd); |
| 8015 | udelay(100); |
| 8016 | } |
| 8017 | |
| 8018 | rtl8xxxu_debug = tmp_debug; |
| 8019 | } |
| 8020 | |
| 8021 | static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw, |
Jes Sorensen | 56e4374 | 2016-02-03 13:39:50 -0500 | [diff] [blame] | 8022 | struct ieee80211_vif *vif, const u8 *mac) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8023 | { |
| 8024 | struct rtl8xxxu_priv *priv = hw->priv; |
| 8025 | u8 val8; |
| 8026 | |
| 8027 | val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); |
| 8028 | val8 |= BEACON_DISABLE_TSF_UPDATE; |
| 8029 | rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); |
| 8030 | } |
| 8031 | |
| 8032 | static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw, |
| 8033 | struct ieee80211_vif *vif) |
| 8034 | { |
| 8035 | struct rtl8xxxu_priv *priv = hw->priv; |
| 8036 | u8 val8; |
| 8037 | |
| 8038 | val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); |
| 8039 | val8 &= ~BEACON_DISABLE_TSF_UPDATE; |
| 8040 | rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); |
| 8041 | } |
| 8042 | |
Jes Sorensen | f653e69 | 2016-02-29 17:05:38 -0500 | [diff] [blame] | 8043 | static void rtl8723au_update_rate_mask(struct rtl8xxxu_priv *priv, |
| 8044 | u32 ramask, int sgi) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8045 | { |
| 8046 | struct h2c_cmd h2c; |
| 8047 | |
Jes Sorensen | f653e69 | 2016-02-29 17:05:38 -0500 | [diff] [blame] | 8048 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 8049 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8050 | h2c.ramask.cmd = H2C_SET_RATE_MASK; |
| 8051 | h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff); |
| 8052 | h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16); |
| 8053 | |
| 8054 | h2c.ramask.arg = 0x80; |
| 8055 | if (sgi) |
| 8056 | h2c.ramask.arg |= 0x20; |
| 8057 | |
Jes Sorensen | 7ff8c1a | 2016-02-29 17:04:32 -0500 | [diff] [blame] | 8058 | dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", |
Jes Sorensen | 8da9157 | 2016-02-29 17:04:29 -0500 | [diff] [blame] | 8059 | __func__, ramask, h2c.ramask.arg, sizeof(h2c.ramask)); |
| 8060 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.ramask)); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8061 | } |
| 8062 | |
Jes Sorensen | f653e69 | 2016-02-29 17:05:38 -0500 | [diff] [blame] | 8063 | static void rtl8723bu_update_rate_mask(struct rtl8xxxu_priv *priv, |
| 8064 | u32 ramask, int sgi) |
| 8065 | { |
| 8066 | struct h2c_cmd h2c; |
| 8067 | u8 bw = 0; |
| 8068 | |
| 8069 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 8070 | |
| 8071 | h2c.b_macid_cfg.cmd = H2C_8723B_MACID_CFG_RAID; |
| 8072 | h2c.b_macid_cfg.ramask0 = ramask & 0xff; |
| 8073 | h2c.b_macid_cfg.ramask1 = (ramask >> 8) & 0xff; |
| 8074 | h2c.b_macid_cfg.ramask2 = (ramask >> 16) & 0xff; |
| 8075 | h2c.b_macid_cfg.ramask3 = (ramask >> 24) & 0xff; |
| 8076 | |
| 8077 | h2c.ramask.arg = 0x80; |
| 8078 | h2c.b_macid_cfg.data1 = 0; |
| 8079 | if (sgi) |
| 8080 | h2c.b_macid_cfg.data1 |= BIT(7); |
| 8081 | |
| 8082 | h2c.b_macid_cfg.data2 = bw; |
| 8083 | |
| 8084 | dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x, size %zi\n", |
| 8085 | __func__, ramask, h2c.ramask.arg, sizeof(h2c.b_macid_cfg)); |
| 8086 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.b_macid_cfg)); |
| 8087 | } |
| 8088 | |
Jes Sorensen | 7d794ea | 2016-02-29 17:05:39 -0500 | [diff] [blame] | 8089 | static void rtl8723au_report_connect(struct rtl8xxxu_priv *priv, |
| 8090 | u8 macid, bool connect) |
| 8091 | { |
| 8092 | struct h2c_cmd h2c; |
| 8093 | |
| 8094 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 8095 | |
| 8096 | h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT; |
| 8097 | |
| 8098 | if (connect) |
| 8099 | h2c.joinbss.data = H2C_JOIN_BSS_CONNECT; |
| 8100 | else |
| 8101 | h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT; |
| 8102 | |
| 8103 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.joinbss)); |
| 8104 | } |
| 8105 | |
| 8106 | static void rtl8723bu_report_connect(struct rtl8xxxu_priv *priv, |
| 8107 | u8 macid, bool connect) |
| 8108 | { |
| 8109 | struct h2c_cmd h2c; |
| 8110 | |
| 8111 | memset(&h2c, 0, sizeof(struct h2c_cmd)); |
| 8112 | |
| 8113 | h2c.media_status_rpt.cmd = H2C_8723B_MEDIA_STATUS_RPT; |
| 8114 | if (connect) |
| 8115 | h2c.media_status_rpt.parm |= BIT(0); |
| 8116 | else |
| 8117 | h2c.media_status_rpt.parm &= ~BIT(0); |
| 8118 | |
| 8119 | rtl8723a_h2c_cmd(priv, &h2c, sizeof(h2c.media_status_rpt)); |
| 8120 | } |
| 8121 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8122 | static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg) |
| 8123 | { |
| 8124 | u32 val32; |
| 8125 | u8 rate_idx = 0; |
| 8126 | |
| 8127 | rate_cfg &= RESPONSE_RATE_BITMAP_ALL; |
| 8128 | |
| 8129 | val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); |
| 8130 | val32 &= ~RESPONSE_RATE_BITMAP_ALL; |
| 8131 | val32 |= rate_cfg; |
| 8132 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); |
| 8133 | |
| 8134 | dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg); |
| 8135 | |
| 8136 | while (rate_cfg) { |
| 8137 | rate_cfg = (rate_cfg >> 1); |
| 8138 | rate_idx++; |
| 8139 | } |
| 8140 | rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx); |
| 8141 | } |
| 8142 | |
| 8143 | static void |
| 8144 | rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
| 8145 | struct ieee80211_bss_conf *bss_conf, u32 changed) |
| 8146 | { |
| 8147 | struct rtl8xxxu_priv *priv = hw->priv; |
| 8148 | struct device *dev = &priv->udev->dev; |
| 8149 | struct ieee80211_sta *sta; |
| 8150 | u32 val32; |
| 8151 | u8 val8; |
| 8152 | |
| 8153 | if (changed & BSS_CHANGED_ASSOC) { |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8154 | dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc); |
| 8155 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8156 | rtl8xxxu_set_linktype(priv, vif->type); |
| 8157 | |
| 8158 | if (bss_conf->assoc) { |
| 8159 | u32 ramask; |
| 8160 | int sgi = 0; |
| 8161 | |
| 8162 | rcu_read_lock(); |
| 8163 | sta = ieee80211_find_sta(vif, bss_conf->bssid); |
| 8164 | if (!sta) { |
| 8165 | dev_info(dev, "%s: ASSOC no sta found\n", |
| 8166 | __func__); |
| 8167 | rcu_read_unlock(); |
| 8168 | goto error; |
| 8169 | } |
| 8170 | |
| 8171 | if (sta->ht_cap.ht_supported) |
| 8172 | dev_info(dev, "%s: HT supported\n", __func__); |
| 8173 | if (sta->vht_cap.vht_supported) |
| 8174 | dev_info(dev, "%s: VHT supported\n", __func__); |
| 8175 | |
| 8176 | /* TODO: Set bits 28-31 for rate adaptive id */ |
| 8177 | ramask = (sta->supp_rates[0] & 0xfff) | |
| 8178 | sta->ht_cap.mcs.rx_mask[0] << 12 | |
| 8179 | sta->ht_cap.mcs.rx_mask[1] << 20; |
| 8180 | if (sta->ht_cap.cap & |
| 8181 | (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20)) |
| 8182 | sgi = 1; |
| 8183 | rcu_read_unlock(); |
| 8184 | |
Jes Sorensen | f653e69 | 2016-02-29 17:05:38 -0500 | [diff] [blame] | 8185 | priv->fops->update_rate_mask(priv, ramask, sgi); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8186 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8187 | rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff); |
| 8188 | |
| 8189 | rtl8723a_stop_tx_beacon(priv); |
| 8190 | |
| 8191 | /* joinbss sequence */ |
| 8192 | rtl8xxxu_write16(priv, REG_BCN_PSR_RPT, |
| 8193 | 0xc000 | bss_conf->aid); |
| 8194 | |
Jes Sorensen | 7d794ea | 2016-02-29 17:05:39 -0500 | [diff] [blame] | 8195 | priv->fops->report_connect(priv, 0, true); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8196 | } else { |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8197 | val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); |
| 8198 | val8 |= BEACON_DISABLE_TSF_UPDATE; |
| 8199 | rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); |
| 8200 | |
Jes Sorensen | 7d794ea | 2016-02-29 17:05:39 -0500 | [diff] [blame] | 8201 | priv->fops->report_connect(priv, 0, false); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8202 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8203 | } |
| 8204 | |
| 8205 | if (changed & BSS_CHANGED_ERP_PREAMBLE) { |
| 8206 | dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n", |
| 8207 | bss_conf->use_short_preamble); |
| 8208 | val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET); |
| 8209 | if (bss_conf->use_short_preamble) |
| 8210 | val32 |= RSR_ACK_SHORT_PREAMBLE; |
| 8211 | else |
| 8212 | val32 &= ~RSR_ACK_SHORT_PREAMBLE; |
| 8213 | rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32); |
| 8214 | } |
| 8215 | |
| 8216 | if (changed & BSS_CHANGED_ERP_SLOT) { |
| 8217 | dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n", |
| 8218 | bss_conf->use_short_slot); |
| 8219 | |
| 8220 | if (bss_conf->use_short_slot) |
| 8221 | val8 = 9; |
| 8222 | else |
| 8223 | val8 = 20; |
| 8224 | rtl8xxxu_write8(priv, REG_SLOT, val8); |
| 8225 | } |
| 8226 | |
| 8227 | if (changed & BSS_CHANGED_BSSID) { |
| 8228 | dev_dbg(dev, "Changed BSSID!\n"); |
| 8229 | rtl8xxxu_set_bssid(priv, bss_conf->bssid); |
| 8230 | } |
| 8231 | |
| 8232 | if (changed & BSS_CHANGED_BASIC_RATES) { |
| 8233 | dev_dbg(dev, "Changed BASIC_RATES!\n"); |
| 8234 | rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates); |
| 8235 | } |
| 8236 | error: |
| 8237 | return; |
| 8238 | } |
| 8239 | |
| 8240 | static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue) |
| 8241 | { |
| 8242 | u32 rtlqueue; |
| 8243 | |
| 8244 | switch (queue) { |
| 8245 | case IEEE80211_AC_VO: |
| 8246 | rtlqueue = TXDESC_QUEUE_VO; |
| 8247 | break; |
| 8248 | case IEEE80211_AC_VI: |
| 8249 | rtlqueue = TXDESC_QUEUE_VI; |
| 8250 | break; |
| 8251 | case IEEE80211_AC_BE: |
| 8252 | rtlqueue = TXDESC_QUEUE_BE; |
| 8253 | break; |
| 8254 | case IEEE80211_AC_BK: |
| 8255 | rtlqueue = TXDESC_QUEUE_BK; |
| 8256 | break; |
| 8257 | default: |
| 8258 | rtlqueue = TXDESC_QUEUE_BE; |
| 8259 | } |
| 8260 | |
| 8261 | return rtlqueue; |
| 8262 | } |
| 8263 | |
| 8264 | static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb) |
| 8265 | { |
| 8266 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
| 8267 | u32 queue; |
| 8268 | |
| 8269 | if (ieee80211_is_mgmt(hdr->frame_control)) |
| 8270 | queue = TXDESC_QUEUE_MGNT; |
| 8271 | else |
| 8272 | queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb)); |
| 8273 | |
| 8274 | return queue; |
| 8275 | } |
| 8276 | |
Jes Sorensen | 179e174 | 2016-02-29 17:05:27 -0500 | [diff] [blame] | 8277 | /* |
| 8278 | * Despite newer chips 8723b/8812/8821 having a larger TX descriptor |
| 8279 | * format. The descriptor checksum is still only calculated over the |
| 8280 | * initial 32 bytes of the descriptor! |
| 8281 | */ |
Jes Sorensen | dbb2896 | 2016-03-31 17:08:33 -0400 | [diff] [blame] | 8282 | static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_txdesc32 *tx_desc) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8283 | { |
| 8284 | __le16 *ptr = (__le16 *)tx_desc; |
| 8285 | u16 csum = 0; |
| 8286 | int i; |
| 8287 | |
| 8288 | /* |
| 8289 | * Clear csum field before calculation, as the csum field is |
| 8290 | * in the middle of the struct. |
| 8291 | */ |
| 8292 | tx_desc->csum = cpu_to_le16(0); |
| 8293 | |
Jes Sorensen | dbb2896 | 2016-03-31 17:08:33 -0400 | [diff] [blame] | 8294 | for (i = 0; i < (sizeof(struct rtl8xxxu_txdesc32) / sizeof(u16)); i++) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8295 | csum = csum ^ le16_to_cpu(ptr[i]); |
| 8296 | |
| 8297 | tx_desc->csum |= cpu_to_le16(csum); |
| 8298 | } |
| 8299 | |
| 8300 | static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv) |
| 8301 | { |
| 8302 | struct rtl8xxxu_tx_urb *tx_urb, *tmp; |
| 8303 | unsigned long flags; |
| 8304 | |
| 8305 | spin_lock_irqsave(&priv->tx_urb_lock, flags); |
| 8306 | list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) { |
| 8307 | list_del(&tx_urb->list); |
| 8308 | priv->tx_urb_free_count--; |
| 8309 | usb_free_urb(&tx_urb->urb); |
| 8310 | } |
| 8311 | spin_unlock_irqrestore(&priv->tx_urb_lock, flags); |
| 8312 | } |
| 8313 | |
| 8314 | static struct rtl8xxxu_tx_urb * |
| 8315 | rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv) |
| 8316 | { |
| 8317 | struct rtl8xxxu_tx_urb *tx_urb; |
| 8318 | unsigned long flags; |
| 8319 | |
| 8320 | spin_lock_irqsave(&priv->tx_urb_lock, flags); |
| 8321 | tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list, |
| 8322 | struct rtl8xxxu_tx_urb, list); |
| 8323 | if (tx_urb) { |
| 8324 | list_del(&tx_urb->list); |
| 8325 | priv->tx_urb_free_count--; |
| 8326 | if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER && |
| 8327 | !priv->tx_stopped) { |
| 8328 | priv->tx_stopped = true; |
| 8329 | ieee80211_stop_queues(priv->hw); |
| 8330 | } |
| 8331 | } |
| 8332 | |
| 8333 | spin_unlock_irqrestore(&priv->tx_urb_lock, flags); |
| 8334 | |
| 8335 | return tx_urb; |
| 8336 | } |
| 8337 | |
| 8338 | static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv, |
| 8339 | struct rtl8xxxu_tx_urb *tx_urb) |
| 8340 | { |
| 8341 | unsigned long flags; |
| 8342 | |
| 8343 | INIT_LIST_HEAD(&tx_urb->list); |
| 8344 | |
| 8345 | spin_lock_irqsave(&priv->tx_urb_lock, flags); |
| 8346 | |
| 8347 | list_add(&tx_urb->list, &priv->tx_urb_free_list); |
| 8348 | priv->tx_urb_free_count++; |
| 8349 | if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER && |
| 8350 | priv->tx_stopped) { |
| 8351 | priv->tx_stopped = false; |
| 8352 | ieee80211_wake_queues(priv->hw); |
| 8353 | } |
| 8354 | |
| 8355 | spin_unlock_irqrestore(&priv->tx_urb_lock, flags); |
| 8356 | } |
| 8357 | |
| 8358 | static void rtl8xxxu_tx_complete(struct urb *urb) |
| 8359 | { |
| 8360 | struct sk_buff *skb = (struct sk_buff *)urb->context; |
| 8361 | struct ieee80211_tx_info *tx_info; |
| 8362 | struct ieee80211_hw *hw; |
Jes Sorensen | 179e174 | 2016-02-29 17:05:27 -0500 | [diff] [blame] | 8363 | struct rtl8xxxu_priv *priv; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8364 | struct rtl8xxxu_tx_urb *tx_urb = |
| 8365 | container_of(urb, struct rtl8xxxu_tx_urb, urb); |
| 8366 | |
| 8367 | tx_info = IEEE80211_SKB_CB(skb); |
| 8368 | hw = tx_info->rate_driver_data[0]; |
Jes Sorensen | 179e174 | 2016-02-29 17:05:27 -0500 | [diff] [blame] | 8369 | priv = hw->priv; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8370 | |
Jes Sorensen | 179e174 | 2016-02-29 17:05:27 -0500 | [diff] [blame] | 8371 | skb_pull(skb, priv->fops->tx_desc_size); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8372 | |
| 8373 | ieee80211_tx_info_clear_status(tx_info); |
| 8374 | tx_info->status.rates[0].idx = -1; |
| 8375 | tx_info->status.rates[0].count = 0; |
| 8376 | |
| 8377 | if (!urb->status) |
| 8378 | tx_info->flags |= IEEE80211_TX_STAT_ACK; |
| 8379 | |
| 8380 | ieee80211_tx_status_irqsafe(hw, skb); |
| 8381 | |
Jes Sorensen | 179e174 | 2016-02-29 17:05:27 -0500 | [diff] [blame] | 8382 | rtl8xxxu_free_tx_urb(priv, tx_urb); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8383 | } |
| 8384 | |
| 8385 | static void rtl8xxxu_dump_action(struct device *dev, |
| 8386 | struct ieee80211_hdr *hdr) |
| 8387 | { |
| 8388 | struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr; |
| 8389 | u16 cap, timeout; |
| 8390 | |
| 8391 | if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION)) |
| 8392 | return; |
| 8393 | |
| 8394 | switch (mgmt->u.action.u.addba_resp.action_code) { |
| 8395 | case WLAN_ACTION_ADDBA_RESP: |
| 8396 | cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab); |
| 8397 | timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout); |
| 8398 | dev_info(dev, "WLAN_ACTION_ADDBA_RESP: " |
| 8399 | "timeout %i, tid %02x, buf_size %02x, policy %02x, " |
| 8400 | "status %02x\n", |
| 8401 | timeout, |
| 8402 | (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, |
| 8403 | (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, |
| 8404 | (cap >> 1) & 0x1, |
| 8405 | le16_to_cpu(mgmt->u.action.u.addba_resp.status)); |
| 8406 | break; |
| 8407 | case WLAN_ACTION_ADDBA_REQ: |
| 8408 | cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab); |
| 8409 | timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout); |
| 8410 | dev_info(dev, "WLAN_ACTION_ADDBA_REQ: " |
| 8411 | "timeout %i, tid %02x, buf_size %02x, policy %02x\n", |
| 8412 | timeout, |
| 8413 | (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2, |
| 8414 | (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6, |
| 8415 | (cap >> 1) & 0x1); |
| 8416 | break; |
| 8417 | default: |
| 8418 | dev_info(dev, "action frame %02x\n", |
| 8419 | mgmt->u.action.u.addba_resp.action_code); |
| 8420 | break; |
| 8421 | } |
| 8422 | } |
| 8423 | |
| 8424 | static void rtl8xxxu_tx(struct ieee80211_hw *hw, |
| 8425 | struct ieee80211_tx_control *control, |
| 8426 | struct sk_buff *skb) |
| 8427 | { |
| 8428 | struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; |
| 8429 | struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb); |
| 8430 | struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info); |
| 8431 | struct rtl8xxxu_priv *priv = hw->priv; |
Jes Sorensen | dbb2896 | 2016-03-31 17:08:33 -0400 | [diff] [blame] | 8432 | struct rtl8xxxu_txdesc32 *tx_desc; |
| 8433 | struct rtl8xxxu_txdesc40 *tx_desc40; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8434 | struct rtl8xxxu_tx_urb *tx_urb; |
| 8435 | struct ieee80211_sta *sta = NULL; |
| 8436 | struct ieee80211_vif *vif = tx_info->control.vif; |
| 8437 | struct device *dev = &priv->udev->dev; |
| 8438 | u32 queue, rate; |
| 8439 | u16 pktlen = skb->len; |
| 8440 | u16 seq_number; |
| 8441 | u16 rate_flag = tx_info->control.rates[0].flags; |
Jes Sorensen | 179e174 | 2016-02-29 17:05:27 -0500 | [diff] [blame] | 8442 | int tx_desc_size = priv->fops->tx_desc_size; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8443 | int ret; |
Jes Sorensen | cc2646d | 2016-02-29 17:05:32 -0500 | [diff] [blame] | 8444 | bool usedesc40, ampdu_enable; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8445 | |
Jes Sorensen | 179e174 | 2016-02-29 17:05:27 -0500 | [diff] [blame] | 8446 | if (skb_headroom(skb) < tx_desc_size) { |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8447 | dev_warn(dev, |
| 8448 | "%s: Not enough headroom (%i) for tx descriptor\n", |
| 8449 | __func__, skb_headroom(skb)); |
| 8450 | goto error; |
| 8451 | } |
| 8452 | |
Jes Sorensen | 179e174 | 2016-02-29 17:05:27 -0500 | [diff] [blame] | 8453 | if (unlikely(skb->len > (65535 - tx_desc_size))) { |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8454 | dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n", |
| 8455 | __func__, skb->len); |
| 8456 | goto error; |
| 8457 | } |
| 8458 | |
| 8459 | tx_urb = rtl8xxxu_alloc_tx_urb(priv); |
| 8460 | if (!tx_urb) { |
| 8461 | dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__); |
| 8462 | goto error; |
| 8463 | } |
| 8464 | |
| 8465 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX) |
| 8466 | dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n", |
| 8467 | __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen); |
| 8468 | |
| 8469 | if (ieee80211_is_action(hdr->frame_control)) |
| 8470 | rtl8xxxu_dump_action(dev, hdr); |
| 8471 | |
Jes Sorensen | cc2646d | 2016-02-29 17:05:32 -0500 | [diff] [blame] | 8472 | usedesc40 = (tx_desc_size == 40); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8473 | tx_info->rate_driver_data[0] = hw; |
| 8474 | |
| 8475 | if (control && control->sta) |
| 8476 | sta = control->sta; |
| 8477 | |
Jes Sorensen | dbb2896 | 2016-03-31 17:08:33 -0400 | [diff] [blame] | 8478 | tx_desc = (struct rtl8xxxu_txdesc32 *)skb_push(skb, tx_desc_size); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8479 | |
Jes Sorensen | 179e174 | 2016-02-29 17:05:27 -0500 | [diff] [blame] | 8480 | memset(tx_desc, 0, tx_desc_size); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8481 | tx_desc->pkt_size = cpu_to_le16(pktlen); |
Jes Sorensen | 179e174 | 2016-02-29 17:05:27 -0500 | [diff] [blame] | 8482 | tx_desc->pkt_offset = tx_desc_size; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8483 | |
| 8484 | tx_desc->txdw0 = |
| 8485 | TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT; |
| 8486 | if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) || |
| 8487 | is_broadcast_ether_addr(ieee80211_get_DA(hdr))) |
| 8488 | tx_desc->txdw0 |= TXDESC_BROADMULTICAST; |
| 8489 | |
| 8490 | queue = rtl8xxxu_queue_select(hw, skb); |
| 8491 | tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT); |
| 8492 | |
| 8493 | if (tx_info->control.hw_key) { |
| 8494 | switch (tx_info->control.hw_key->cipher) { |
| 8495 | case WLAN_CIPHER_SUITE_WEP40: |
| 8496 | case WLAN_CIPHER_SUITE_WEP104: |
| 8497 | case WLAN_CIPHER_SUITE_TKIP: |
| 8498 | tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4); |
| 8499 | break; |
| 8500 | case WLAN_CIPHER_SUITE_CCMP: |
| 8501 | tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES); |
| 8502 | break; |
| 8503 | default: |
| 8504 | break; |
| 8505 | } |
| 8506 | } |
| 8507 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8508 | /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */ |
Jes Sorensen | a40ace4 | 2016-02-29 17:05:31 -0500 | [diff] [blame] | 8509 | ampdu_enable = false; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8510 | if (ieee80211_is_data_qos(hdr->frame_control) && sta) { |
| 8511 | if (sta->ht_cap.ht_supported) { |
| 8512 | u32 ampdu, val32; |
| 8513 | |
| 8514 | ampdu = (u32)sta->ht_cap.ampdu_density; |
| 8515 | val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT; |
| 8516 | tx_desc->txdw2 |= cpu_to_le32(val32); |
Jes Sorensen | ce2d1db | 2016-02-29 17:05:30 -0500 | [diff] [blame] | 8517 | |
Jes Sorensen | a40ace4 | 2016-02-29 17:05:31 -0500 | [diff] [blame] | 8518 | ampdu_enable = true; |
| 8519 | } |
| 8520 | } |
| 8521 | |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8522 | if (rate_flag & IEEE80211_TX_RC_MCS) |
| 8523 | rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0; |
| 8524 | else |
| 8525 | rate = tx_rate->hw_value; |
| 8526 | |
Jes Sorensen | cc2646d | 2016-02-29 17:05:32 -0500 | [diff] [blame] | 8527 | seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl)); |
| 8528 | if (!usedesc40) { |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8529 | tx_desc->txdw5 = cpu_to_le32(rate); |
| 8530 | |
| 8531 | if (ieee80211_is_data(hdr->frame_control)) |
| 8532 | tx_desc->txdw5 |= cpu_to_le32(0x0001ff00); |
| 8533 | |
Jes Sorensen | cc2646d | 2016-02-29 17:05:32 -0500 | [diff] [blame] | 8534 | tx_desc->txdw3 = |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8535 | cpu_to_le32((u32)seq_number << TXDESC32_SEQ_SHIFT); |
Jes Sorensen | cc2646d | 2016-02-29 17:05:32 -0500 | [diff] [blame] | 8536 | |
Jes Sorensen | a40ace4 | 2016-02-29 17:05:31 -0500 | [diff] [blame] | 8537 | if (ampdu_enable) |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8538 | tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_ENABLE); |
Jes Sorensen | a40ace4 | 2016-02-29 17:05:31 -0500 | [diff] [blame] | 8539 | else |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8540 | tx_desc->txdw1 |= cpu_to_le32(TXDESC32_AGG_BREAK); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8541 | |
| 8542 | if (ieee80211_is_mgmt(hdr->frame_control)) { |
| 8543 | tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value); |
| 8544 | tx_desc->txdw4 |= |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8545 | cpu_to_le32(TXDESC32_USE_DRIVER_RATE); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8546 | tx_desc->txdw5 |= |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8547 | cpu_to_le32(6 << TXDESC32_RETRY_LIMIT_SHIFT); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8548 | tx_desc->txdw5 |= |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8549 | cpu_to_le32(TXDESC32_RETRY_LIMIT_ENABLE); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8550 | } |
| 8551 | |
| 8552 | if (ieee80211_is_data_qos(hdr->frame_control)) |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8553 | tx_desc->txdw4 |= cpu_to_le32(TXDESC32_QOS); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8554 | |
| 8555 | if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE || |
| 8556 | (sta && vif && vif->bss_conf.use_short_preamble)) |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8557 | tx_desc->txdw4 |= cpu_to_le32(TXDESC32_SHORT_PREAMBLE); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8558 | |
| 8559 | if (rate_flag & IEEE80211_TX_RC_SHORT_GI || |
| 8560 | (ieee80211_is_data_qos(hdr->frame_control) && |
| 8561 | sta && sta->ht_cap.cap & |
| 8562 | (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) { |
Jes Sorensen | 1df1de3 | 2016-03-31 17:08:36 -0400 | [diff] [blame] | 8563 | tx_desc->txdw5 |= cpu_to_le32(TXDESC32_SHORT_GI); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8564 | } |
| 8565 | |
| 8566 | if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) { |
| 8567 | /* |
| 8568 | * Use RTS rate 24M - does the mac80211 tell |
| 8569 | * us which to use? |
| 8570 | */ |
| 8571 | tx_desc->txdw4 |= |
| 8572 | cpu_to_le32(DESC_RATE_24M << |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8573 | TXDESC32_RTS_RATE_SHIFT); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8574 | tx_desc->txdw4 |= |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8575 | cpu_to_le32(TXDESC32_RTS_CTS_ENABLE); |
| 8576 | tx_desc->txdw4 |= cpu_to_le32(TXDESC32_HW_RTS_ENABLE); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8577 | } |
Jes Sorensen | a40ace4 | 2016-02-29 17:05:31 -0500 | [diff] [blame] | 8578 | } else { |
Jes Sorensen | dbb2896 | 2016-03-31 17:08:33 -0400 | [diff] [blame] | 8579 | tx_desc40 = (struct rtl8xxxu_txdesc40 *)tx_desc; |
Jes Sorensen | cc2646d | 2016-02-29 17:05:32 -0500 | [diff] [blame] | 8580 | |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8581 | tx_desc40->txdw4 = cpu_to_le32(rate); |
| 8582 | if (ieee80211_is_data(hdr->frame_control)) { |
| 8583 | tx_desc->txdw4 |= |
| 8584 | cpu_to_le32(0x1f << |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8585 | TXDESC40_DATA_RATE_FB_SHIFT); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8586 | } |
| 8587 | |
Jes Sorensen | cc2646d | 2016-02-29 17:05:32 -0500 | [diff] [blame] | 8588 | tx_desc40->txdw9 = |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8589 | cpu_to_le32((u32)seq_number << TXDESC40_SEQ_SHIFT); |
Jes Sorensen | cc2646d | 2016-02-29 17:05:32 -0500 | [diff] [blame] | 8590 | |
Jes Sorensen | a40ace4 | 2016-02-29 17:05:31 -0500 | [diff] [blame] | 8591 | if (ampdu_enable) |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8592 | tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_ENABLE); |
Jes Sorensen | a40ace4 | 2016-02-29 17:05:31 -0500 | [diff] [blame] | 8593 | else |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8594 | tx_desc40->txdw2 |= cpu_to_le32(TXDESC40_AGG_BREAK); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8595 | |
| 8596 | if (ieee80211_is_mgmt(hdr->frame_control)) { |
| 8597 | tx_desc40->txdw4 = cpu_to_le32(tx_rate->hw_value); |
| 8598 | tx_desc40->txdw3 |= |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8599 | cpu_to_le32(TXDESC40_USE_DRIVER_RATE); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8600 | tx_desc40->txdw4 |= |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8601 | cpu_to_le32(6 << TXDESC40_RETRY_LIMIT_SHIFT); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8602 | tx_desc40->txdw4 |= |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8603 | cpu_to_le32(TXDESC40_RETRY_LIMIT_ENABLE); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8604 | } |
| 8605 | |
| 8606 | if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE || |
| 8607 | (sta && vif && vif->bss_conf.use_short_preamble)) |
| 8608 | tx_desc40->txdw5 |= |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8609 | cpu_to_le32(TXDESC40_SHORT_PREAMBLE); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8610 | |
| 8611 | if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) { |
| 8612 | /* |
| 8613 | * Use RTS rate 24M - does the mac80211 tell |
| 8614 | * us which to use? |
| 8615 | */ |
| 8616 | tx_desc->txdw4 |= |
| 8617 | cpu_to_le32(DESC_RATE_24M << |
Jes Sorensen | 33f3724 | 2016-03-31 17:08:34 -0400 | [diff] [blame] | 8618 | TXDESC40_RTS_RATE_SHIFT); |
| 8619 | tx_desc->txdw3 |= cpu_to_le32(TXDESC40_RTS_CTS_ENABLE); |
| 8620 | tx_desc->txdw3 |= cpu_to_le32(TXDESC40_HW_RTS_ENABLE); |
Jes Sorensen | 4c68360 | 2016-02-29 17:05:35 -0500 | [diff] [blame] | 8621 | } |
Jes Sorensen | 6979494 | 2016-02-29 17:05:43 -0500 | [diff] [blame] | 8622 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8623 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8624 | rtl8xxxu_calc_tx_desc_csum(tx_desc); |
| 8625 | |
| 8626 | usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue], |
| 8627 | skb->data, skb->len, rtl8xxxu_tx_complete, skb); |
| 8628 | |
| 8629 | usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor); |
| 8630 | ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC); |
| 8631 | if (ret) { |
| 8632 | usb_unanchor_urb(&tx_urb->urb); |
| 8633 | rtl8xxxu_free_tx_urb(priv, tx_urb); |
| 8634 | goto error; |
| 8635 | } |
| 8636 | return; |
| 8637 | error: |
| 8638 | dev_kfree_skb(skb); |
| 8639 | } |
| 8640 | |
| 8641 | static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv, |
| 8642 | struct ieee80211_rx_status *rx_status, |
Jes Sorensen | 8795708 | 2016-02-29 17:05:42 -0500 | [diff] [blame] | 8643 | struct rtl8723au_phy_stats *phy_stats, |
| 8644 | u32 rxmcs) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8645 | { |
| 8646 | if (phy_stats->sgi_en) |
| 8647 | rx_status->flag |= RX_FLAG_SHORT_GI; |
| 8648 | |
Jes Sorensen | 8795708 | 2016-02-29 17:05:42 -0500 | [diff] [blame] | 8649 | if (rxmcs < DESC_RATE_6M) { |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8650 | /* |
| 8651 | * Handle PHY stats for CCK rates |
| 8652 | */ |
| 8653 | u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a; |
| 8654 | |
| 8655 | switch (cck_agc_rpt & 0xc0) { |
| 8656 | case 0xc0: |
| 8657 | rx_status->signal = -46 - (cck_agc_rpt & 0x3e); |
| 8658 | break; |
| 8659 | case 0x80: |
| 8660 | rx_status->signal = -26 - (cck_agc_rpt & 0x3e); |
| 8661 | break; |
| 8662 | case 0x40: |
| 8663 | rx_status->signal = -12 - (cck_agc_rpt & 0x3e); |
| 8664 | break; |
| 8665 | case 0x00: |
| 8666 | rx_status->signal = 16 - (cck_agc_rpt & 0x3e); |
| 8667 | break; |
| 8668 | } |
| 8669 | } else { |
| 8670 | rx_status->signal = |
| 8671 | (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110; |
| 8672 | } |
| 8673 | } |
| 8674 | |
| 8675 | static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv) |
| 8676 | { |
| 8677 | struct rtl8xxxu_rx_urb *rx_urb, *tmp; |
| 8678 | unsigned long flags; |
| 8679 | |
| 8680 | spin_lock_irqsave(&priv->rx_urb_lock, flags); |
| 8681 | |
| 8682 | list_for_each_entry_safe(rx_urb, tmp, |
| 8683 | &priv->rx_urb_pending_list, list) { |
| 8684 | list_del(&rx_urb->list); |
| 8685 | priv->rx_urb_pending_count--; |
| 8686 | usb_free_urb(&rx_urb->urb); |
| 8687 | } |
| 8688 | |
| 8689 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); |
| 8690 | } |
| 8691 | |
| 8692 | static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv, |
| 8693 | struct rtl8xxxu_rx_urb *rx_urb) |
| 8694 | { |
| 8695 | struct sk_buff *skb; |
| 8696 | unsigned long flags; |
| 8697 | int pending = 0; |
| 8698 | |
| 8699 | spin_lock_irqsave(&priv->rx_urb_lock, flags); |
| 8700 | |
| 8701 | if (!priv->shutdown) { |
| 8702 | list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list); |
| 8703 | priv->rx_urb_pending_count++; |
| 8704 | pending = priv->rx_urb_pending_count; |
| 8705 | } else { |
| 8706 | skb = (struct sk_buff *)rx_urb->urb.context; |
| 8707 | dev_kfree_skb(skb); |
| 8708 | usb_free_urb(&rx_urb->urb); |
| 8709 | } |
| 8710 | |
| 8711 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); |
| 8712 | |
| 8713 | if (pending > RTL8XXXU_RX_URB_PENDING_WATER) |
| 8714 | schedule_work(&priv->rx_urb_wq); |
| 8715 | } |
| 8716 | |
| 8717 | static void rtl8xxxu_rx_urb_work(struct work_struct *work) |
| 8718 | { |
| 8719 | struct rtl8xxxu_priv *priv; |
| 8720 | struct rtl8xxxu_rx_urb *rx_urb, *tmp; |
| 8721 | struct list_head local; |
| 8722 | struct sk_buff *skb; |
| 8723 | unsigned long flags; |
| 8724 | int ret; |
| 8725 | |
| 8726 | priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq); |
| 8727 | INIT_LIST_HEAD(&local); |
| 8728 | |
| 8729 | spin_lock_irqsave(&priv->rx_urb_lock, flags); |
| 8730 | |
| 8731 | list_splice_init(&priv->rx_urb_pending_list, &local); |
| 8732 | priv->rx_urb_pending_count = 0; |
| 8733 | |
| 8734 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); |
| 8735 | |
| 8736 | list_for_each_entry_safe(rx_urb, tmp, &local, list) { |
| 8737 | list_del_init(&rx_urb->list); |
| 8738 | ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); |
| 8739 | /* |
| 8740 | * If out of memory or temporary error, put it back on the |
| 8741 | * queue and try again. Otherwise the device is dead/gone |
| 8742 | * and we should drop it. |
| 8743 | */ |
| 8744 | switch (ret) { |
| 8745 | case 0: |
| 8746 | break; |
| 8747 | case -ENOMEM: |
| 8748 | case -EAGAIN: |
| 8749 | rtl8xxxu_queue_rx_urb(priv, rx_urb); |
| 8750 | break; |
| 8751 | default: |
| 8752 | pr_info("failed to requeue urb %i\n", ret); |
| 8753 | skb = (struct sk_buff *)rx_urb->urb.context; |
| 8754 | dev_kfree_skb(skb); |
| 8755 | usb_free_urb(&rx_urb->urb); |
| 8756 | } |
| 8757 | } |
| 8758 | } |
| 8759 | |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 8760 | static int rtl8xxxu_parse_rxdesc16(struct rtl8xxxu_priv *priv, |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8761 | struct sk_buff *skb, |
| 8762 | struct ieee80211_rx_status *rx_status) |
| 8763 | { |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 8764 | struct rtl8xxxu_rxdesc16 *rx_desc = |
| 8765 | (struct rtl8xxxu_rxdesc16 *)skb->data; |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8766 | struct rtl8723au_phy_stats *phy_stats; |
Jes Sorensen | 2cb79eb | 2016-04-14 14:58:51 -0400 | [diff] [blame] | 8767 | __le32 *_rx_desc_le = (__le32 *)skb->data; |
| 8768 | u32 *_rx_desc = (u32 *)skb->data; |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8769 | int drvinfo_sz, desc_shift; |
Jes Sorensen | 2cb79eb | 2016-04-14 14:58:51 -0400 | [diff] [blame] | 8770 | int i; |
| 8771 | |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 8772 | for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc16) / sizeof(u32)); i++) |
Jes Sorensen | 2cb79eb | 2016-04-14 14:58:51 -0400 | [diff] [blame] | 8773 | _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8774 | |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 8775 | skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc16)); |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8776 | |
| 8777 | phy_stats = (struct rtl8723au_phy_stats *)skb->data; |
| 8778 | |
| 8779 | drvinfo_sz = rx_desc->drvinfo_sz * 8; |
| 8780 | desc_shift = rx_desc->shift; |
| 8781 | skb_pull(skb, drvinfo_sz + desc_shift); |
| 8782 | |
| 8783 | if (rx_desc->phy_stats) |
Jes Sorensen | 8795708 | 2016-02-29 17:05:42 -0500 | [diff] [blame] | 8784 | rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats, |
| 8785 | rx_desc->rxmcs); |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8786 | |
| 8787 | rx_status->mactime = le32_to_cpu(rx_desc->tsfl); |
| 8788 | rx_status->flag |= RX_FLAG_MACTIME_START; |
| 8789 | |
| 8790 | if (!rx_desc->swdec) |
| 8791 | rx_status->flag |= RX_FLAG_DECRYPTED; |
| 8792 | if (rx_desc->crc32) |
| 8793 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; |
| 8794 | if (rx_desc->bw) |
| 8795 | rx_status->flag |= RX_FLAG_40MHZ; |
| 8796 | |
| 8797 | if (rx_desc->rxht) { |
| 8798 | rx_status->flag |= RX_FLAG_HT; |
| 8799 | rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; |
| 8800 | } else { |
| 8801 | rx_status->rate_idx = rx_desc->rxmcs; |
| 8802 | } |
| 8803 | |
| 8804 | return RX_TYPE_DATA_PKT; |
| 8805 | } |
| 8806 | |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 8807 | static int rtl8xxxu_parse_rxdesc24(struct rtl8xxxu_priv *priv, |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8808 | struct sk_buff *skb, |
| 8809 | struct ieee80211_rx_status *rx_status) |
| 8810 | { |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 8811 | struct rtl8xxxu_rxdesc24 *rx_desc = |
| 8812 | (struct rtl8xxxu_rxdesc24 *)skb->data; |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8813 | struct rtl8723au_phy_stats *phy_stats; |
Jes Sorensen | 2cb79eb | 2016-04-14 14:58:51 -0400 | [diff] [blame] | 8814 | __le32 *_rx_desc_le = (__le32 *)skb->data; |
| 8815 | u32 *_rx_desc = (u32 *)skb->data; |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8816 | int drvinfo_sz, desc_shift; |
Jes Sorensen | 2cb79eb | 2016-04-14 14:58:51 -0400 | [diff] [blame] | 8817 | int i; |
| 8818 | |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 8819 | for (i = 0; i < (sizeof(struct rtl8xxxu_rxdesc24) / sizeof(u32)); i++) |
Jes Sorensen | 2cb79eb | 2016-04-14 14:58:51 -0400 | [diff] [blame] | 8820 | _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]); |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8821 | |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 8822 | skb_pull(skb, sizeof(struct rtl8xxxu_rxdesc24)); |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8823 | |
| 8824 | phy_stats = (struct rtl8723au_phy_stats *)skb->data; |
| 8825 | |
| 8826 | drvinfo_sz = rx_desc->drvinfo_sz * 8; |
| 8827 | desc_shift = rx_desc->shift; |
| 8828 | skb_pull(skb, drvinfo_sz + desc_shift); |
| 8829 | |
Jes Sorensen | e975b87 | 2016-02-29 17:05:36 -0500 | [diff] [blame] | 8830 | if (rx_desc->rpt_sel) { |
| 8831 | struct device *dev = &priv->udev->dev; |
| 8832 | dev_dbg(dev, "%s: C2H packet\n", __func__); |
| 8833 | return RX_TYPE_C2H; |
| 8834 | } |
| 8835 | |
Jes Sorensen | 8795708 | 2016-02-29 17:05:42 -0500 | [diff] [blame] | 8836 | if (rx_desc->phy_stats) |
| 8837 | rtl8xxxu_rx_parse_phystats(priv, rx_status, phy_stats, |
| 8838 | rx_desc->rxmcs); |
| 8839 | |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8840 | rx_status->mactime = le32_to_cpu(rx_desc->tsfl); |
| 8841 | rx_status->flag |= RX_FLAG_MACTIME_START; |
| 8842 | |
| 8843 | if (!rx_desc->swdec) |
| 8844 | rx_status->flag |= RX_FLAG_DECRYPTED; |
| 8845 | if (rx_desc->crc32) |
| 8846 | rx_status->flag |= RX_FLAG_FAILED_FCS_CRC; |
| 8847 | if (rx_desc->bw) |
| 8848 | rx_status->flag |= RX_FLAG_40MHZ; |
| 8849 | |
| 8850 | if (rx_desc->rxmcs >= DESC_RATE_MCS0) { |
| 8851 | rx_status->flag |= RX_FLAG_HT; |
| 8852 | rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0; |
| 8853 | } else { |
| 8854 | rx_status->rate_idx = rx_desc->rxmcs; |
| 8855 | } |
| 8856 | |
Jes Sorensen | e975b87 | 2016-02-29 17:05:36 -0500 | [diff] [blame] | 8857 | return RX_TYPE_DATA_PKT; |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8858 | } |
| 8859 | |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 8860 | static void rtl8723bu_handle_c2h(struct rtl8xxxu_priv *priv, |
| 8861 | struct sk_buff *skb) |
| 8862 | { |
| 8863 | struct rtl8723bu_c2h *c2h = (struct rtl8723bu_c2h *)skb->data; |
| 8864 | struct device *dev = &priv->udev->dev; |
| 8865 | int len; |
| 8866 | |
| 8867 | len = skb->len - 2; |
| 8868 | |
Jes Sorensen | 5e00d50 | 2016-02-29 17:05:28 -0500 | [diff] [blame] | 8869 | dev_dbg(dev, "C2H ID %02x seq %02x, len %02x source %02x\n", |
| 8870 | c2h->id, c2h->seq, len, c2h->bt_info.response_source); |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 8871 | |
| 8872 | switch(c2h->id) { |
| 8873 | case C2H_8723B_BT_INFO: |
| 8874 | if (c2h->bt_info.response_source > |
| 8875 | BT_INFO_SRC_8723B_BT_ACTIVE_SEND) |
Jes Sorensen | 5e00d50 | 2016-02-29 17:05:28 -0500 | [diff] [blame] | 8876 | dev_dbg(dev, "C2H_BT_INFO WiFi only firmware\n"); |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 8877 | else |
Jes Sorensen | 5e00d50 | 2016-02-29 17:05:28 -0500 | [diff] [blame] | 8878 | dev_dbg(dev, "C2H_BT_INFO BT/WiFi coexist firmware\n"); |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 8879 | |
| 8880 | if (c2h->bt_info.bt_has_reset) |
Jes Sorensen | 5e00d50 | 2016-02-29 17:05:28 -0500 | [diff] [blame] | 8881 | dev_dbg(dev, "BT has been reset\n"); |
Jes Sorensen | 394f1bd | 2016-02-29 17:04:49 -0500 | [diff] [blame] | 8882 | if (c2h->bt_info.tx_rx_mask) |
Jes Sorensen | 5e00d50 | 2016-02-29 17:05:28 -0500 | [diff] [blame] | 8883 | dev_dbg(dev, "BT TRx mask\n"); |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 8884 | |
| 8885 | break; |
Jes Sorensen | 394f1bd | 2016-02-29 17:04:49 -0500 | [diff] [blame] | 8886 | case C2H_8723B_BT_MP_INFO: |
Jes Sorensen | 5e00d50 | 2016-02-29 17:05:28 -0500 | [diff] [blame] | 8887 | dev_dbg(dev, "C2H_MP_INFO ext ID %02x, status %02x\n", |
| 8888 | c2h->bt_mp_info.ext_id, c2h->bt_mp_info.status); |
Jes Sorensen | 394f1bd | 2016-02-29 17:04:49 -0500 | [diff] [blame] | 8889 | break; |
Jes Sorensen | 55a18dd | 2016-02-29 17:05:41 -0500 | [diff] [blame] | 8890 | case C2H_8723B_RA_REPORT: |
| 8891 | dev_dbg(dev, |
| 8892 | "C2H RA RPT: rate %02x, unk %i, macid %02x, noise %i\n", |
| 8893 | c2h->ra_report.rate, c2h->ra_report.dummy0_0, |
| 8894 | c2h->ra_report.macid, c2h->ra_report.noisy_state); |
| 8895 | break; |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 8896 | default: |
Jes Sorensen | 739dc9f | 2016-02-29 17:05:40 -0500 | [diff] [blame] | 8897 | dev_info(dev, "Unhandled C2H event %02x seq %02x\n", |
| 8898 | c2h->id, c2h->seq); |
| 8899 | print_hex_dump(KERN_INFO, "C2H content: ", DUMP_PREFIX_NONE, |
| 8900 | 16, 1, c2h->raw.payload, len, false); |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 8901 | break; |
| 8902 | } |
| 8903 | } |
| 8904 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8905 | static void rtl8xxxu_rx_complete(struct urb *urb) |
| 8906 | { |
| 8907 | struct rtl8xxxu_rx_urb *rx_urb = |
| 8908 | container_of(urb, struct rtl8xxxu_rx_urb, urb); |
| 8909 | struct ieee80211_hw *hw = rx_urb->hw; |
| 8910 | struct rtl8xxxu_priv *priv = hw->priv; |
| 8911 | struct sk_buff *skb = (struct sk_buff *)urb->context; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8912 | struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8913 | struct device *dev = &priv->udev->dev; |
Jes Sorensen | 2cb79eb | 2016-04-14 14:58:51 -0400 | [diff] [blame] | 8914 | int rx_type; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8915 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8916 | skb_put(skb, urb->actual_length); |
| 8917 | |
| 8918 | if (urb->status == 0) { |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8919 | memset(rx_status, 0, sizeof(struct ieee80211_rx_status)); |
| 8920 | |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8921 | rx_type = priv->fops->parse_rx_desc(priv, skb, rx_status); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8922 | |
| 8923 | rx_status->freq = hw->conf.chandef.chan->center_freq; |
| 8924 | rx_status->band = hw->conf.chandef.chan->band; |
| 8925 | |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8926 | if (rx_type == RX_TYPE_DATA_PKT) |
| 8927 | ieee80211_rx_irqsafe(hw, skb); |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 8928 | else { |
| 8929 | rtl8723bu_handle_c2h(priv, skb); |
Jes Sorensen | b18cdfd | 2016-02-29 17:04:47 -0500 | [diff] [blame] | 8930 | dev_kfree_skb(skb); |
Jes Sorensen | b2b43b7 | 2016-02-29 17:04:48 -0500 | [diff] [blame] | 8931 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8932 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8933 | skb = NULL; |
| 8934 | rx_urb->urb.context = NULL; |
| 8935 | rtl8xxxu_queue_rx_urb(priv, rx_urb); |
| 8936 | } else { |
| 8937 | dev_dbg(dev, "%s: status %i\n", __func__, urb->status); |
| 8938 | goto cleanup; |
| 8939 | } |
| 8940 | return; |
| 8941 | |
| 8942 | cleanup: |
| 8943 | usb_free_urb(urb); |
| 8944 | dev_kfree_skb(skb); |
| 8945 | return; |
| 8946 | } |
| 8947 | |
| 8948 | static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv, |
| 8949 | struct rtl8xxxu_rx_urb *rx_urb) |
| 8950 | { |
| 8951 | struct sk_buff *skb; |
| 8952 | int skb_size; |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 8953 | int ret, rx_desc_sz; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8954 | |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 8955 | rx_desc_sz = priv->fops->rx_desc_size; |
| 8956 | skb_size = rx_desc_sz + RTL_RX_BUFFER_SIZE; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8957 | skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL); |
| 8958 | if (!skb) |
| 8959 | return -ENOMEM; |
| 8960 | |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 8961 | memset(skb->data, 0, rx_desc_sz); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 8962 | usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data, |
| 8963 | skb_size, rtl8xxxu_rx_complete, skb); |
| 8964 | usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor); |
| 8965 | ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC); |
| 8966 | if (ret) |
| 8967 | usb_unanchor_urb(&rx_urb->urb); |
| 8968 | return ret; |
| 8969 | } |
| 8970 | |
| 8971 | static void rtl8xxxu_int_complete(struct urb *urb) |
| 8972 | { |
| 8973 | struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context; |
| 8974 | struct device *dev = &priv->udev->dev; |
| 8975 | int ret; |
| 8976 | |
| 8977 | dev_dbg(dev, "%s: status %i\n", __func__, urb->status); |
| 8978 | if (urb->status == 0) { |
| 8979 | usb_anchor_urb(urb, &priv->int_anchor); |
| 8980 | ret = usb_submit_urb(urb, GFP_ATOMIC); |
| 8981 | if (ret) |
| 8982 | usb_unanchor_urb(urb); |
| 8983 | } else { |
| 8984 | dev_info(dev, "%s: Error %i\n", __func__, urb->status); |
| 8985 | } |
| 8986 | } |
| 8987 | |
| 8988 | |
| 8989 | static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw) |
| 8990 | { |
| 8991 | struct rtl8xxxu_priv *priv = hw->priv; |
| 8992 | struct urb *urb; |
| 8993 | u32 val32; |
| 8994 | int ret; |
| 8995 | |
| 8996 | urb = usb_alloc_urb(0, GFP_KERNEL); |
| 8997 | if (!urb) |
| 8998 | return -ENOMEM; |
| 8999 | |
| 9000 | usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt, |
| 9001 | priv->int_buf, USB_INTR_CONTENT_LENGTH, |
| 9002 | rtl8xxxu_int_complete, priv, 1); |
| 9003 | usb_anchor_urb(urb, &priv->int_anchor); |
| 9004 | ret = usb_submit_urb(urb, GFP_KERNEL); |
| 9005 | if (ret) { |
| 9006 | usb_unanchor_urb(urb); |
| 9007 | goto error; |
| 9008 | } |
| 9009 | |
| 9010 | val32 = rtl8xxxu_read32(priv, REG_USB_HIMR); |
| 9011 | val32 |= USB_HIMR_CPWM; |
| 9012 | rtl8xxxu_write32(priv, REG_USB_HIMR, val32); |
| 9013 | |
| 9014 | error: |
| 9015 | return ret; |
| 9016 | } |
| 9017 | |
| 9018 | static int rtl8xxxu_add_interface(struct ieee80211_hw *hw, |
| 9019 | struct ieee80211_vif *vif) |
| 9020 | { |
| 9021 | struct rtl8xxxu_priv *priv = hw->priv; |
| 9022 | int ret; |
| 9023 | u8 val8; |
| 9024 | |
| 9025 | switch (vif->type) { |
| 9026 | case NL80211_IFTYPE_STATION: |
| 9027 | rtl8723a_stop_tx_beacon(priv); |
| 9028 | |
| 9029 | val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL); |
| 9030 | val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE | |
| 9031 | BEACON_DISABLE_TSF_UPDATE; |
| 9032 | rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8); |
| 9033 | ret = 0; |
| 9034 | break; |
| 9035 | default: |
| 9036 | ret = -EOPNOTSUPP; |
| 9037 | } |
| 9038 | |
| 9039 | rtl8xxxu_set_linktype(priv, vif->type); |
| 9040 | |
| 9041 | return ret; |
| 9042 | } |
| 9043 | |
| 9044 | static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw, |
| 9045 | struct ieee80211_vif *vif) |
| 9046 | { |
| 9047 | struct rtl8xxxu_priv *priv = hw->priv; |
| 9048 | |
| 9049 | dev_dbg(&priv->udev->dev, "%s\n", __func__); |
| 9050 | } |
| 9051 | |
| 9052 | static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed) |
| 9053 | { |
| 9054 | struct rtl8xxxu_priv *priv = hw->priv; |
| 9055 | struct device *dev = &priv->udev->dev; |
| 9056 | u16 val16; |
| 9057 | int ret = 0, channel; |
| 9058 | bool ht40; |
| 9059 | |
| 9060 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL) |
| 9061 | dev_info(dev, |
| 9062 | "%s: channel: %i (changed %08x chandef.width %02x)\n", |
| 9063 | __func__, hw->conf.chandef.chan->hw_value, |
| 9064 | changed, hw->conf.chandef.width); |
| 9065 | |
| 9066 | if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) { |
| 9067 | val16 = ((hw->conf.long_frame_max_tx_count << |
| 9068 | RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) | |
| 9069 | ((hw->conf.short_frame_max_tx_count << |
| 9070 | RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK); |
| 9071 | rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16); |
| 9072 | } |
| 9073 | |
| 9074 | if (changed & IEEE80211_CONF_CHANGE_CHANNEL) { |
| 9075 | switch (hw->conf.chandef.width) { |
| 9076 | case NL80211_CHAN_WIDTH_20_NOHT: |
| 9077 | case NL80211_CHAN_WIDTH_20: |
| 9078 | ht40 = false; |
| 9079 | break; |
| 9080 | case NL80211_CHAN_WIDTH_40: |
| 9081 | ht40 = true; |
| 9082 | break; |
| 9083 | default: |
| 9084 | ret = -ENOTSUPP; |
| 9085 | goto exit; |
| 9086 | } |
| 9087 | |
| 9088 | channel = hw->conf.chandef.chan->hw_value; |
| 9089 | |
Jes Sorensen | e796dab | 2016-02-29 17:05:19 -0500 | [diff] [blame] | 9090 | priv->fops->set_tx_power(priv, channel, ht40); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9091 | |
Jes Sorensen | 1ea8e84 | 2016-02-29 17:05:04 -0500 | [diff] [blame] | 9092 | priv->fops->config_channel(hw); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9093 | } |
| 9094 | |
| 9095 | exit: |
| 9096 | return ret; |
| 9097 | } |
| 9098 | |
| 9099 | static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw, |
| 9100 | struct ieee80211_vif *vif, u16 queue, |
| 9101 | const struct ieee80211_tx_queue_params *param) |
| 9102 | { |
| 9103 | struct rtl8xxxu_priv *priv = hw->priv; |
| 9104 | struct device *dev = &priv->udev->dev; |
| 9105 | u32 val32; |
| 9106 | u8 aifs, acm_ctrl, acm_bit; |
| 9107 | |
| 9108 | aifs = param->aifs; |
| 9109 | |
| 9110 | val32 = aifs | |
| 9111 | fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT | |
| 9112 | fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT | |
| 9113 | (u32)param->txop << EDCA_PARAM_TXOP_SHIFT; |
| 9114 | |
| 9115 | acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL); |
| 9116 | dev_dbg(dev, |
| 9117 | "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n", |
| 9118 | __func__, queue, val32, param->acm, acm_ctrl); |
| 9119 | |
| 9120 | switch (queue) { |
| 9121 | case IEEE80211_AC_VO: |
| 9122 | acm_bit = ACM_HW_CTRL_VO; |
| 9123 | rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32); |
| 9124 | break; |
| 9125 | case IEEE80211_AC_VI: |
| 9126 | acm_bit = ACM_HW_CTRL_VI; |
| 9127 | rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32); |
| 9128 | break; |
| 9129 | case IEEE80211_AC_BE: |
| 9130 | acm_bit = ACM_HW_CTRL_BE; |
| 9131 | rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32); |
| 9132 | break; |
| 9133 | case IEEE80211_AC_BK: |
| 9134 | acm_bit = ACM_HW_CTRL_BK; |
| 9135 | rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32); |
| 9136 | break; |
| 9137 | default: |
| 9138 | acm_bit = 0; |
| 9139 | break; |
| 9140 | } |
| 9141 | |
| 9142 | if (param->acm) |
| 9143 | acm_ctrl |= acm_bit; |
| 9144 | else |
| 9145 | acm_ctrl &= ~acm_bit; |
| 9146 | rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl); |
| 9147 | |
| 9148 | return 0; |
| 9149 | } |
| 9150 | |
| 9151 | static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw, |
| 9152 | unsigned int changed_flags, |
| 9153 | unsigned int *total_flags, u64 multicast) |
| 9154 | { |
| 9155 | struct rtl8xxxu_priv *priv = hw->priv; |
Bruno Randolf | 3bed4bf | 2016-02-03 13:39:51 -0500 | [diff] [blame] | 9156 | u32 rcr = rtl8xxxu_read32(priv, REG_RCR); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9157 | |
| 9158 | dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n", |
| 9159 | __func__, changed_flags, *total_flags); |
| 9160 | |
Bruno Randolf | 3bed4bf | 2016-02-03 13:39:51 -0500 | [diff] [blame] | 9161 | /* |
| 9162 | * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR) |
| 9163 | */ |
| 9164 | |
| 9165 | if (*total_flags & FIF_FCSFAIL) |
| 9166 | rcr |= RCR_ACCEPT_CRC32; |
| 9167 | else |
| 9168 | rcr &= ~RCR_ACCEPT_CRC32; |
| 9169 | |
| 9170 | /* |
| 9171 | * FIF_PLCPFAIL not supported? |
| 9172 | */ |
| 9173 | |
| 9174 | if (*total_flags & FIF_BCN_PRBRESP_PROMISC) |
| 9175 | rcr &= ~RCR_CHECK_BSSID_BEACON; |
| 9176 | else |
| 9177 | rcr |= RCR_CHECK_BSSID_BEACON; |
| 9178 | |
| 9179 | if (*total_flags & FIF_CONTROL) |
| 9180 | rcr |= RCR_ACCEPT_CTRL_FRAME; |
| 9181 | else |
| 9182 | rcr &= ~RCR_ACCEPT_CTRL_FRAME; |
| 9183 | |
| 9184 | if (*total_flags & FIF_OTHER_BSS) { |
| 9185 | rcr |= RCR_ACCEPT_AP; |
| 9186 | rcr &= ~RCR_CHECK_BSSID_MATCH; |
| 9187 | } else { |
| 9188 | rcr &= ~RCR_ACCEPT_AP; |
| 9189 | rcr |= RCR_CHECK_BSSID_MATCH; |
| 9190 | } |
| 9191 | |
| 9192 | if (*total_flags & FIF_PSPOLL) |
| 9193 | rcr |= RCR_ACCEPT_PM; |
| 9194 | else |
| 9195 | rcr &= ~RCR_ACCEPT_PM; |
| 9196 | |
| 9197 | /* |
| 9198 | * FIF_PROBE_REQ ignored as probe requests always seem to be accepted |
| 9199 | */ |
| 9200 | |
| 9201 | rtl8xxxu_write32(priv, REG_RCR, rcr); |
| 9202 | |
Jes Sorensen | 755bda1 | 2016-02-03 13:39:54 -0500 | [diff] [blame] | 9203 | *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC | |
| 9204 | FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL | |
| 9205 | FIF_PROBE_REQ); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9206 | } |
| 9207 | |
| 9208 | static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts) |
| 9209 | { |
| 9210 | if (rts > 2347) |
| 9211 | return -EINVAL; |
| 9212 | |
| 9213 | return 0; |
| 9214 | } |
| 9215 | |
| 9216 | static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, |
| 9217 | struct ieee80211_vif *vif, |
| 9218 | struct ieee80211_sta *sta, |
| 9219 | struct ieee80211_key_conf *key) |
| 9220 | { |
| 9221 | struct rtl8xxxu_priv *priv = hw->priv; |
| 9222 | struct device *dev = &priv->udev->dev; |
| 9223 | u8 mac_addr[ETH_ALEN]; |
| 9224 | u8 val8; |
| 9225 | u16 val16; |
| 9226 | u32 val32; |
| 9227 | int retval = -EOPNOTSUPP; |
| 9228 | |
| 9229 | dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n", |
| 9230 | __func__, cmd, key->cipher, key->keyidx); |
| 9231 | |
| 9232 | if (vif->type != NL80211_IFTYPE_STATION) |
| 9233 | return -EOPNOTSUPP; |
| 9234 | |
| 9235 | if (key->keyidx > 3) |
| 9236 | return -EOPNOTSUPP; |
| 9237 | |
| 9238 | switch (key->cipher) { |
| 9239 | case WLAN_CIPHER_SUITE_WEP40: |
| 9240 | case WLAN_CIPHER_SUITE_WEP104: |
| 9241 | |
| 9242 | break; |
| 9243 | case WLAN_CIPHER_SUITE_CCMP: |
| 9244 | key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX; |
| 9245 | break; |
| 9246 | case WLAN_CIPHER_SUITE_TKIP: |
| 9247 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; |
| 9248 | default: |
| 9249 | return -EOPNOTSUPP; |
| 9250 | } |
| 9251 | |
| 9252 | if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) { |
| 9253 | dev_dbg(dev, "%s: pairwise key\n", __func__); |
| 9254 | ether_addr_copy(mac_addr, sta->addr); |
| 9255 | } else { |
| 9256 | dev_dbg(dev, "%s: group key\n", __func__); |
| 9257 | eth_broadcast_addr(mac_addr); |
| 9258 | } |
| 9259 | |
| 9260 | val16 = rtl8xxxu_read16(priv, REG_CR); |
| 9261 | val16 |= CR_SECURITY_ENABLE; |
| 9262 | rtl8xxxu_write16(priv, REG_CR, val16); |
| 9263 | |
| 9264 | val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY | |
| 9265 | SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY; |
| 9266 | val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY; |
| 9267 | rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8); |
| 9268 | |
| 9269 | switch (cmd) { |
| 9270 | case SET_KEY: |
| 9271 | key->hw_key_idx = key->keyidx; |
| 9272 | key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; |
| 9273 | rtl8xxxu_cam_write(priv, key, mac_addr); |
| 9274 | retval = 0; |
| 9275 | break; |
| 9276 | case DISABLE_KEY: |
| 9277 | rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000); |
| 9278 | val32 = CAM_CMD_POLLING | CAM_CMD_WRITE | |
| 9279 | key->keyidx << CAM_CMD_KEY_SHIFT; |
| 9280 | rtl8xxxu_write32(priv, REG_CAM_CMD, val32); |
| 9281 | retval = 0; |
| 9282 | break; |
| 9283 | default: |
| 9284 | dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd); |
| 9285 | } |
| 9286 | |
| 9287 | return retval; |
| 9288 | } |
| 9289 | |
| 9290 | static int |
| 9291 | rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, |
Sara Sharon | 50ea05e | 2015-12-30 16:06:04 +0200 | [diff] [blame] | 9292 | struct ieee80211_ampdu_params *params) |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9293 | { |
| 9294 | struct rtl8xxxu_priv *priv = hw->priv; |
| 9295 | struct device *dev = &priv->udev->dev; |
| 9296 | u8 ampdu_factor, ampdu_density; |
Sara Sharon | 50ea05e | 2015-12-30 16:06:04 +0200 | [diff] [blame] | 9297 | struct ieee80211_sta *sta = params->sta; |
| 9298 | enum ieee80211_ampdu_mlme_action action = params->action; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9299 | |
| 9300 | switch (action) { |
| 9301 | case IEEE80211_AMPDU_TX_START: |
| 9302 | dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__); |
| 9303 | ampdu_factor = sta->ht_cap.ampdu_factor; |
| 9304 | ampdu_density = sta->ht_cap.ampdu_density; |
| 9305 | rtl8xxxu_set_ampdu_factor(priv, ampdu_factor); |
| 9306 | rtl8xxxu_set_ampdu_min_space(priv, ampdu_density); |
| 9307 | dev_dbg(dev, |
| 9308 | "Changed HT: ampdu_factor %02x, ampdu_density %02x\n", |
| 9309 | ampdu_factor, ampdu_density); |
| 9310 | break; |
| 9311 | case IEEE80211_AMPDU_TX_STOP_FLUSH: |
| 9312 | dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__); |
| 9313 | rtl8xxxu_set_ampdu_factor(priv, 0); |
| 9314 | rtl8xxxu_set_ampdu_min_space(priv, 0); |
| 9315 | break; |
| 9316 | case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: |
| 9317 | dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n", |
| 9318 | __func__); |
| 9319 | rtl8xxxu_set_ampdu_factor(priv, 0); |
| 9320 | rtl8xxxu_set_ampdu_min_space(priv, 0); |
| 9321 | break; |
| 9322 | case IEEE80211_AMPDU_RX_START: |
| 9323 | dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__); |
| 9324 | break; |
| 9325 | case IEEE80211_AMPDU_RX_STOP: |
| 9326 | dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__); |
| 9327 | break; |
| 9328 | default: |
| 9329 | break; |
| 9330 | } |
| 9331 | return 0; |
| 9332 | } |
| 9333 | |
| 9334 | static int rtl8xxxu_start(struct ieee80211_hw *hw) |
| 9335 | { |
| 9336 | struct rtl8xxxu_priv *priv = hw->priv; |
| 9337 | struct rtl8xxxu_rx_urb *rx_urb; |
| 9338 | struct rtl8xxxu_tx_urb *tx_urb; |
| 9339 | unsigned long flags; |
| 9340 | int ret, i; |
| 9341 | |
| 9342 | ret = 0; |
| 9343 | |
| 9344 | init_usb_anchor(&priv->rx_anchor); |
| 9345 | init_usb_anchor(&priv->tx_anchor); |
| 9346 | init_usb_anchor(&priv->int_anchor); |
| 9347 | |
Jes Sorensen | db08de9 | 2016-02-29 17:05:17 -0500 | [diff] [blame] | 9348 | priv->fops->enable_rf(priv); |
Jes Sorensen | 0e28b97 | 2016-02-29 17:04:13 -0500 | [diff] [blame] | 9349 | if (priv->usb_interrupts) { |
| 9350 | ret = rtl8xxxu_submit_int_urb(hw); |
| 9351 | if (ret) |
| 9352 | goto exit; |
| 9353 | } |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9354 | |
| 9355 | for (i = 0; i < RTL8XXXU_TX_URBS; i++) { |
| 9356 | tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL); |
| 9357 | if (!tx_urb) { |
| 9358 | if (!i) |
| 9359 | ret = -ENOMEM; |
| 9360 | |
| 9361 | goto error_out; |
| 9362 | } |
| 9363 | usb_init_urb(&tx_urb->urb); |
| 9364 | INIT_LIST_HEAD(&tx_urb->list); |
| 9365 | tx_urb->hw = hw; |
| 9366 | list_add(&tx_urb->list, &priv->tx_urb_free_list); |
| 9367 | priv->tx_urb_free_count++; |
| 9368 | } |
| 9369 | |
| 9370 | priv->tx_stopped = false; |
| 9371 | |
| 9372 | spin_lock_irqsave(&priv->rx_urb_lock, flags); |
| 9373 | priv->shutdown = false; |
| 9374 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); |
| 9375 | |
| 9376 | for (i = 0; i < RTL8XXXU_RX_URBS; i++) { |
| 9377 | rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL); |
| 9378 | if (!rx_urb) { |
| 9379 | if (!i) |
| 9380 | ret = -ENOMEM; |
| 9381 | |
| 9382 | goto error_out; |
| 9383 | } |
| 9384 | usb_init_urb(&rx_urb->urb); |
| 9385 | INIT_LIST_HEAD(&rx_urb->list); |
| 9386 | rx_urb->hw = hw; |
| 9387 | |
| 9388 | ret = rtl8xxxu_submit_rx_urb(priv, rx_urb); |
| 9389 | } |
| 9390 | exit: |
| 9391 | /* |
Bruno Randolf | c85ea11 | 2016-02-03 13:39:55 -0500 | [diff] [blame] | 9392 | * Accept all data and mgmt frames |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9393 | */ |
Bruno Randolf | c85ea11 | 2016-02-03 13:39:55 -0500 | [diff] [blame] | 9394 | rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9395 | rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff); |
| 9396 | |
| 9397 | rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e); |
| 9398 | |
| 9399 | return ret; |
| 9400 | |
| 9401 | error_out: |
| 9402 | rtl8xxxu_free_tx_resources(priv); |
| 9403 | /* |
| 9404 | * Disable all data and mgmt frames |
| 9405 | */ |
| 9406 | rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); |
| 9407 | rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); |
| 9408 | |
| 9409 | return ret; |
| 9410 | } |
| 9411 | |
| 9412 | static void rtl8xxxu_stop(struct ieee80211_hw *hw) |
| 9413 | { |
| 9414 | struct rtl8xxxu_priv *priv = hw->priv; |
| 9415 | unsigned long flags; |
| 9416 | |
| 9417 | rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff); |
| 9418 | |
| 9419 | rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000); |
| 9420 | rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000); |
| 9421 | |
| 9422 | spin_lock_irqsave(&priv->rx_urb_lock, flags); |
| 9423 | priv->shutdown = true; |
| 9424 | spin_unlock_irqrestore(&priv->rx_urb_lock, flags); |
| 9425 | |
| 9426 | usb_kill_anchored_urbs(&priv->rx_anchor); |
| 9427 | usb_kill_anchored_urbs(&priv->tx_anchor); |
Jes Sorensen | 0e28b97 | 2016-02-29 17:04:13 -0500 | [diff] [blame] | 9428 | if (priv->usb_interrupts) |
| 9429 | usb_kill_anchored_urbs(&priv->int_anchor); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9430 | |
Jes Sorensen | fc89a41 | 2016-02-29 17:05:46 -0500 | [diff] [blame] | 9431 | priv->fops->disable_rf(priv); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9432 | |
| 9433 | /* |
| 9434 | * Disable interrupts |
| 9435 | */ |
Jes Sorensen | 0e28b97 | 2016-02-29 17:04:13 -0500 | [diff] [blame] | 9436 | if (priv->usb_interrupts) |
| 9437 | rtl8xxxu_write32(priv, REG_USB_HIMR, 0); |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9438 | |
| 9439 | rtl8xxxu_free_rx_resources(priv); |
| 9440 | rtl8xxxu_free_tx_resources(priv); |
| 9441 | } |
| 9442 | |
| 9443 | static const struct ieee80211_ops rtl8xxxu_ops = { |
| 9444 | .tx = rtl8xxxu_tx, |
| 9445 | .add_interface = rtl8xxxu_add_interface, |
| 9446 | .remove_interface = rtl8xxxu_remove_interface, |
| 9447 | .config = rtl8xxxu_config, |
| 9448 | .conf_tx = rtl8xxxu_conf_tx, |
| 9449 | .bss_info_changed = rtl8xxxu_bss_info_changed, |
| 9450 | .configure_filter = rtl8xxxu_configure_filter, |
| 9451 | .set_rts_threshold = rtl8xxxu_set_rts_threshold, |
| 9452 | .start = rtl8xxxu_start, |
| 9453 | .stop = rtl8xxxu_stop, |
| 9454 | .sw_scan_start = rtl8xxxu_sw_scan_start, |
| 9455 | .sw_scan_complete = rtl8xxxu_sw_scan_complete, |
| 9456 | .set_key = rtl8xxxu_set_key, |
| 9457 | .ampdu_action = rtl8xxxu_ampdu_action, |
| 9458 | }; |
| 9459 | |
| 9460 | static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv, |
| 9461 | struct usb_interface *interface) |
| 9462 | { |
| 9463 | struct usb_interface_descriptor *interface_desc; |
| 9464 | struct usb_host_interface *host_interface; |
| 9465 | struct usb_endpoint_descriptor *endpoint; |
| 9466 | struct device *dev = &priv->udev->dev; |
| 9467 | int i, j = 0, endpoints; |
| 9468 | u8 dir, xtype, num; |
| 9469 | int ret = 0; |
| 9470 | |
| 9471 | host_interface = &interface->altsetting[0]; |
| 9472 | interface_desc = &host_interface->desc; |
| 9473 | endpoints = interface_desc->bNumEndpoints; |
| 9474 | |
| 9475 | for (i = 0; i < endpoints; i++) { |
| 9476 | endpoint = &host_interface->endpoint[i].desc; |
| 9477 | |
| 9478 | dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK; |
| 9479 | num = usb_endpoint_num(endpoint); |
| 9480 | xtype = usb_endpoint_type(endpoint); |
| 9481 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) |
| 9482 | dev_dbg(dev, |
| 9483 | "%s: endpoint: dir %02x, # %02x, type %02x\n", |
| 9484 | __func__, dir, num, xtype); |
| 9485 | if (usb_endpoint_dir_in(endpoint) && |
| 9486 | usb_endpoint_xfer_bulk(endpoint)) { |
| 9487 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) |
| 9488 | dev_dbg(dev, "%s: in endpoint num %i\n", |
| 9489 | __func__, num); |
| 9490 | |
| 9491 | if (priv->pipe_in) { |
| 9492 | dev_warn(dev, |
| 9493 | "%s: Too many IN pipes\n", __func__); |
| 9494 | ret = -EINVAL; |
| 9495 | goto exit; |
| 9496 | } |
| 9497 | |
| 9498 | priv->pipe_in = usb_rcvbulkpipe(priv->udev, num); |
| 9499 | } |
| 9500 | |
| 9501 | if (usb_endpoint_dir_in(endpoint) && |
| 9502 | usb_endpoint_xfer_int(endpoint)) { |
| 9503 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) |
| 9504 | dev_dbg(dev, "%s: interrupt endpoint num %i\n", |
| 9505 | __func__, num); |
| 9506 | |
| 9507 | if (priv->pipe_interrupt) { |
| 9508 | dev_warn(dev, "%s: Too many INTERRUPT pipes\n", |
| 9509 | __func__); |
| 9510 | ret = -EINVAL; |
| 9511 | goto exit; |
| 9512 | } |
| 9513 | |
| 9514 | priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num); |
| 9515 | } |
| 9516 | |
| 9517 | if (usb_endpoint_dir_out(endpoint) && |
| 9518 | usb_endpoint_xfer_bulk(endpoint)) { |
| 9519 | if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB) |
| 9520 | dev_dbg(dev, "%s: out endpoint num %i\n", |
| 9521 | __func__, num); |
| 9522 | if (j >= RTL8XXXU_OUT_ENDPOINTS) { |
| 9523 | dev_warn(dev, |
| 9524 | "%s: Too many OUT pipes\n", __func__); |
| 9525 | ret = -EINVAL; |
| 9526 | goto exit; |
| 9527 | } |
| 9528 | priv->out_ep[j++] = num; |
| 9529 | } |
| 9530 | } |
| 9531 | exit: |
| 9532 | priv->nr_out_eps = j; |
| 9533 | return ret; |
| 9534 | } |
| 9535 | |
| 9536 | static int rtl8xxxu_probe(struct usb_interface *interface, |
| 9537 | const struct usb_device_id *id) |
| 9538 | { |
| 9539 | struct rtl8xxxu_priv *priv; |
| 9540 | struct ieee80211_hw *hw; |
| 9541 | struct usb_device *udev; |
| 9542 | struct ieee80211_supported_band *sband; |
| 9543 | int ret = 0; |
| 9544 | int untested = 1; |
| 9545 | |
| 9546 | udev = usb_get_dev(interface_to_usbdev(interface)); |
| 9547 | |
| 9548 | switch (id->idVendor) { |
| 9549 | case USB_VENDOR_ID_REALTEK: |
| 9550 | switch(id->idProduct) { |
| 9551 | case 0x1724: |
| 9552 | case 0x8176: |
| 9553 | case 0x8178: |
| 9554 | case 0x817f: |
| 9555 | untested = 0; |
| 9556 | break; |
| 9557 | } |
| 9558 | break; |
| 9559 | case 0x7392: |
| 9560 | if (id->idProduct == 0x7811) |
| 9561 | untested = 0; |
| 9562 | break; |
Jes Sorensen | e1d70c9 | 2016-04-14 16:37:06 -0400 | [diff] [blame] | 9563 | case 0x050d: |
| 9564 | if (id->idProduct == 0x1004) |
| 9565 | untested = 0; |
| 9566 | break; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9567 | default: |
| 9568 | break; |
| 9569 | } |
| 9570 | |
| 9571 | if (untested) { |
Jes Sorensen | eaa4d14 | 2016-02-29 17:04:31 -0500 | [diff] [blame] | 9572 | rtl8xxxu_debug |= RTL8XXXU_DEBUG_EFUSE; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9573 | dev_info(&udev->dev, |
| 9574 | "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n", |
| 9575 | id->idVendor, id->idProduct); |
| 9576 | dev_info(&udev->dev, |
| 9577 | "Please report results to Jes.Sorensen@gmail.com\n"); |
| 9578 | } |
| 9579 | |
| 9580 | hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops); |
| 9581 | if (!hw) { |
| 9582 | ret = -ENOMEM; |
| 9583 | goto exit; |
| 9584 | } |
| 9585 | |
| 9586 | priv = hw->priv; |
| 9587 | priv->hw = hw; |
| 9588 | priv->udev = udev; |
| 9589 | priv->fops = (struct rtl8xxxu_fileops *)id->driver_info; |
| 9590 | mutex_init(&priv->usb_buf_mutex); |
| 9591 | mutex_init(&priv->h2c_mutex); |
| 9592 | INIT_LIST_HEAD(&priv->tx_urb_free_list); |
| 9593 | spin_lock_init(&priv->tx_urb_lock); |
| 9594 | INIT_LIST_HEAD(&priv->rx_urb_pending_list); |
| 9595 | spin_lock_init(&priv->rx_urb_lock); |
| 9596 | INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work); |
| 9597 | |
| 9598 | usb_set_intfdata(interface, hw); |
| 9599 | |
| 9600 | ret = rtl8xxxu_parse_usb(priv, interface); |
| 9601 | if (ret) |
| 9602 | goto exit; |
| 9603 | |
| 9604 | ret = rtl8xxxu_identify_chip(priv); |
| 9605 | if (ret) { |
| 9606 | dev_err(&udev->dev, "Fatal - failed to identify chip\n"); |
| 9607 | goto exit; |
| 9608 | } |
| 9609 | |
| 9610 | ret = rtl8xxxu_read_efuse(priv); |
| 9611 | if (ret) { |
| 9612 | dev_err(&udev->dev, "Fatal - failed to read EFuse\n"); |
| 9613 | goto exit; |
| 9614 | } |
| 9615 | |
| 9616 | ret = priv->fops->parse_efuse(priv); |
| 9617 | if (ret) { |
| 9618 | dev_err(&udev->dev, "Fatal - failed to parse EFuse\n"); |
| 9619 | goto exit; |
| 9620 | } |
| 9621 | |
| 9622 | rtl8xxxu_print_chipinfo(priv); |
| 9623 | |
| 9624 | ret = priv->fops->load_firmware(priv); |
| 9625 | if (ret) { |
| 9626 | dev_err(&udev->dev, "Fatal - failed to load firmware\n"); |
| 9627 | goto exit; |
| 9628 | } |
| 9629 | |
| 9630 | ret = rtl8xxxu_init_device(hw); |
| 9631 | |
| 9632 | hw->wiphy->max_scan_ssids = 1; |
| 9633 | hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN; |
| 9634 | hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION); |
| 9635 | hw->queues = 4; |
| 9636 | |
| 9637 | sband = &rtl8xxxu_supported_band; |
| 9638 | sband->ht_cap.ht_supported = true; |
| 9639 | sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K; |
| 9640 | sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16; |
| 9641 | sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40; |
| 9642 | memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs)); |
| 9643 | sband->ht_cap.mcs.rx_mask[0] = 0xff; |
| 9644 | sband->ht_cap.mcs.rx_mask[4] = 0x01; |
| 9645 | if (priv->rf_paths > 1) { |
| 9646 | sband->ht_cap.mcs.rx_mask[1] = 0xff; |
| 9647 | sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40; |
| 9648 | } |
| 9649 | sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED; |
| 9650 | /* |
| 9651 | * Some APs will negotiate HT20_40 in a noisy environment leading |
| 9652 | * to miserable performance. Rather than defaulting to this, only |
| 9653 | * enable it if explicitly requested at module load time. |
| 9654 | */ |
| 9655 | if (rtl8xxxu_ht40_2g) { |
| 9656 | dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n"); |
| 9657 | sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40; |
| 9658 | } |
Johannes Berg | 57fbcce | 2016-04-12 15:56:15 +0200 | [diff] [blame] | 9659 | hw->wiphy->bands[NL80211_BAND_2GHZ] = sband; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9660 | |
| 9661 | hw->wiphy->rts_threshold = 2347; |
| 9662 | |
| 9663 | SET_IEEE80211_DEV(priv->hw, &interface->dev); |
| 9664 | SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr); |
| 9665 | |
Jes Sorensen | 179e174 | 2016-02-29 17:05:27 -0500 | [diff] [blame] | 9666 | hw->extra_tx_headroom = priv->fops->tx_desc_size; |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9667 | ieee80211_hw_set(hw, SIGNAL_DBM); |
| 9668 | /* |
| 9669 | * The firmware handles rate control |
| 9670 | */ |
| 9671 | ieee80211_hw_set(hw, HAS_RATE_CONTROL); |
| 9672 | ieee80211_hw_set(hw, AMPDU_AGGREGATION); |
| 9673 | |
| 9674 | ret = ieee80211_register_hw(priv->hw); |
| 9675 | if (ret) { |
| 9676 | dev_err(&udev->dev, "%s: Failed to register: %i\n", |
| 9677 | __func__, ret); |
| 9678 | goto exit; |
| 9679 | } |
| 9680 | |
| 9681 | exit: |
| 9682 | if (ret < 0) |
| 9683 | usb_put_dev(udev); |
| 9684 | return ret; |
| 9685 | } |
| 9686 | |
| 9687 | static void rtl8xxxu_disconnect(struct usb_interface *interface) |
| 9688 | { |
| 9689 | struct rtl8xxxu_priv *priv; |
| 9690 | struct ieee80211_hw *hw; |
| 9691 | |
| 9692 | hw = usb_get_intfdata(interface); |
| 9693 | priv = hw->priv; |
| 9694 | |
| 9695 | rtl8xxxu_disable_device(hw); |
| 9696 | usb_set_intfdata(interface, NULL); |
| 9697 | |
| 9698 | dev_info(&priv->udev->dev, "disconnecting\n"); |
| 9699 | |
| 9700 | ieee80211_unregister_hw(hw); |
| 9701 | |
| 9702 | kfree(priv->fw_data); |
| 9703 | mutex_destroy(&priv->usb_buf_mutex); |
| 9704 | mutex_destroy(&priv->h2c_mutex); |
| 9705 | |
| 9706 | usb_put_dev(priv->udev); |
| 9707 | ieee80211_free_hw(hw); |
| 9708 | } |
| 9709 | |
| 9710 | static struct rtl8xxxu_fileops rtl8723au_fops = { |
| 9711 | .parse_efuse = rtl8723au_parse_efuse, |
| 9712 | .load_firmware = rtl8723au_load_firmware, |
| 9713 | .power_on = rtl8723au_power_on, |
Jes Sorensen | fe37d5f | 2016-02-29 17:05:47 -0500 | [diff] [blame] | 9714 | .power_off = rtl8xxxu_power_off, |
Jes Sorensen | 7d4ccb8 | 2016-02-29 17:05:50 -0500 | [diff] [blame] | 9715 | .reset_8051 = rtl8xxxu_reset_8051, |
Jes Sorensen | 74b99be | 2016-02-29 17:04:04 -0500 | [diff] [blame] | 9716 | .llt_init = rtl8xxxu_init_llt_table, |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 9717 | .init_phy_bb = rtl8723au_init_phy_bb, |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 9718 | .phy_iq_calibrate = rtl8723au_phy_iq_calibrate, |
Jes Sorensen | c3f9506 | 2016-02-29 17:04:40 -0500 | [diff] [blame] | 9719 | .config_channel = rtl8723au_config_channel, |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 9720 | .parse_rx_desc = rtl8xxxu_parse_rxdesc16, |
Jes Sorensen | db08de9 | 2016-02-29 17:05:17 -0500 | [diff] [blame] | 9721 | .enable_rf = rtl8723a_enable_rf, |
Jes Sorensen | fc89a41 | 2016-02-29 17:05:46 -0500 | [diff] [blame] | 9722 | .disable_rf = rtl8723a_disable_rf, |
Jes Sorensen | 747bf23 | 2016-04-14 14:59:04 -0400 | [diff] [blame] | 9723 | .usb_quirks = rtl8xxxu_gen1_usb_quirks, |
Jes Sorensen | e796dab | 2016-02-29 17:05:19 -0500 | [diff] [blame] | 9724 | .set_tx_power = rtl8723a_set_tx_power, |
Jes Sorensen | f653e69 | 2016-02-29 17:05:38 -0500 | [diff] [blame] | 9725 | .update_rate_mask = rtl8723au_update_rate_mask, |
Jes Sorensen | 7d794ea | 2016-02-29 17:05:39 -0500 | [diff] [blame] | 9726 | .report_connect = rtl8723au_report_connect, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9727 | .writeN_block_size = 1024, |
Jes Sorensen | ed35d09 | 2016-02-29 17:04:19 -0500 | [diff] [blame] | 9728 | .mbox_ext_reg = REG_HMBOX_EXT_0, |
| 9729 | .mbox_ext_width = 2, |
Jes Sorensen | dbb2896 | 2016-03-31 17:08:33 -0400 | [diff] [blame] | 9730 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 9731 | .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), |
Jes Sorensen | 8634af5 | 2016-02-29 17:04:33 -0500 | [diff] [blame] | 9732 | .adda_1t_init = 0x0b1b25a0, |
| 9733 | .adda_1t_path_on = 0x0bdb25a0, |
| 9734 | .adda_2t_path_on_a = 0x04db25a4, |
| 9735 | .adda_2t_path_on_b = 0x0b1b25a4, |
Jes Sorensen | 24e8e7e | 2016-04-14 14:59:01 -0400 | [diff] [blame] | 9736 | .trxff_boundary = 0x27ff, |
Jes Sorensen | 9b323ee | 2016-04-14 14:59:03 -0400 | [diff] [blame] | 9737 | .pbp_rx = PBP_PAGE_SIZE_128, |
| 9738 | .pbp_tx = PBP_PAGE_SIZE_128, |
Jes Sorensen | c606e66 | 2016-04-07 14:19:16 -0400 | [diff] [blame] | 9739 | .mactable = rtl8723a_mac_init_table, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9740 | }; |
| 9741 | |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 9742 | static struct rtl8xxxu_fileops rtl8723bu_fops = { |
Jes Sorensen | 3c836d6 | 2016-02-29 17:04:11 -0500 | [diff] [blame] | 9743 | .parse_efuse = rtl8723bu_parse_efuse, |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 9744 | .load_firmware = rtl8723bu_load_firmware, |
Jes Sorensen | 42836db | 2016-02-29 17:04:52 -0500 | [diff] [blame] | 9745 | .power_on = rtl8723bu_power_on, |
Jes Sorensen | fe37d5f | 2016-02-29 17:05:47 -0500 | [diff] [blame] | 9746 | .power_off = rtl8723bu_power_off, |
Jes Sorensen | 7d4ccb8 | 2016-02-29 17:05:50 -0500 | [diff] [blame] | 9747 | .reset_8051 = rtl8723bu_reset_8051, |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 9748 | .llt_init = rtl8xxxu_auto_llt_table, |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 9749 | .init_phy_bb = rtl8723bu_init_phy_bb, |
Jes Sorensen | f0d9f5e | 2016-02-29 17:04:16 -0500 | [diff] [blame] | 9750 | .phy_init_antenna_selection = rtl8723bu_phy_init_antenna_selection, |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 9751 | .phy_iq_calibrate = rtl8723bu_phy_iq_calibrate, |
Jes Sorensen | c3f9506 | 2016-02-29 17:04:40 -0500 | [diff] [blame] | 9752 | .config_channel = rtl8723bu_config_channel, |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 9753 | .parse_rx_desc = rtl8xxxu_parse_rxdesc24, |
Jes Sorensen | 3e88ca4 | 2016-02-29 17:05:08 -0500 | [diff] [blame] | 9754 | .init_aggregation = rtl8723bu_init_aggregation, |
Jes Sorensen | 9c79bf9 | 2016-02-29 17:05:10 -0500 | [diff] [blame] | 9755 | .init_statistics = rtl8723bu_init_statistics, |
Jes Sorensen | db08de9 | 2016-02-29 17:05:17 -0500 | [diff] [blame] | 9756 | .enable_rf = rtl8723b_enable_rf, |
Jes Sorensen | fc89a41 | 2016-02-29 17:05:46 -0500 | [diff] [blame] | 9757 | .disable_rf = rtl8723b_disable_rf, |
Jes Sorensen | 747bf23 | 2016-04-14 14:59:04 -0400 | [diff] [blame] | 9758 | .usb_quirks = rtl8xxxu_gen2_usb_quirks, |
Jes Sorensen | e796dab | 2016-02-29 17:05:19 -0500 | [diff] [blame] | 9759 | .set_tx_power = rtl8723b_set_tx_power, |
Jes Sorensen | f653e69 | 2016-02-29 17:05:38 -0500 | [diff] [blame] | 9760 | .update_rate_mask = rtl8723bu_update_rate_mask, |
Jes Sorensen | 7d794ea | 2016-02-29 17:05:39 -0500 | [diff] [blame] | 9761 | .report_connect = rtl8723bu_report_connect, |
Jes Sorensen | adfc012 | 2016-02-29 17:04:12 -0500 | [diff] [blame] | 9762 | .writeN_block_size = 1024, |
Jes Sorensen | ed35d09 | 2016-02-29 17:04:19 -0500 | [diff] [blame] | 9763 | .mbox_ext_reg = REG_HMBOX_EXT0_8723B, |
| 9764 | .mbox_ext_width = 4, |
Jes Sorensen | dbb2896 | 2016-03-31 17:08:33 -0400 | [diff] [blame] | 9765 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 9766 | .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), |
Jes Sorensen | 0d698de | 2016-02-29 17:04:36 -0500 | [diff] [blame] | 9767 | .has_s0s1 = 1, |
Jes Sorensen | 8634af5 | 2016-02-29 17:04:33 -0500 | [diff] [blame] | 9768 | .adda_1t_init = 0x01c00014, |
| 9769 | .adda_1t_path_on = 0x01c00014, |
| 9770 | .adda_2t_path_on_a = 0x01c00014, |
| 9771 | .adda_2t_path_on_b = 0x01c00014, |
Jes Sorensen | 24e8e7e | 2016-04-14 14:59:01 -0400 | [diff] [blame] | 9772 | .trxff_boundary = 0x3f7f, |
Jes Sorensen | 9b323ee | 2016-04-14 14:59:03 -0400 | [diff] [blame] | 9773 | .pbp_rx = PBP_PAGE_SIZE_256, |
| 9774 | .pbp_tx = PBP_PAGE_SIZE_256, |
Jes Sorensen | c606e66 | 2016-04-07 14:19:16 -0400 | [diff] [blame] | 9775 | .mactable = rtl8723b_mac_init_table, |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 9776 | }; |
| 9777 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 9778 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
| 9779 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9780 | static struct rtl8xxxu_fileops rtl8192cu_fops = { |
| 9781 | .parse_efuse = rtl8192cu_parse_efuse, |
| 9782 | .load_firmware = rtl8192cu_load_firmware, |
| 9783 | .power_on = rtl8192cu_power_on, |
Jes Sorensen | fe37d5f | 2016-02-29 17:05:47 -0500 | [diff] [blame] | 9784 | .power_off = rtl8xxxu_power_off, |
Jes Sorensen | 7d4ccb8 | 2016-02-29 17:05:50 -0500 | [diff] [blame] | 9785 | .reset_8051 = rtl8xxxu_reset_8051, |
Jes Sorensen | 74b99be | 2016-02-29 17:04:04 -0500 | [diff] [blame] | 9786 | .llt_init = rtl8xxxu_init_llt_table, |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 9787 | .init_phy_bb = rtl8723au_init_phy_bb, |
Jes Sorensen | e1547c5 | 2016-02-29 17:04:35 -0500 | [diff] [blame] | 9788 | .phy_iq_calibrate = rtl8723au_phy_iq_calibrate, |
Jes Sorensen | c3f9506 | 2016-02-29 17:04:40 -0500 | [diff] [blame] | 9789 | .config_channel = rtl8723au_config_channel, |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 9790 | .parse_rx_desc = rtl8xxxu_parse_rxdesc16, |
Jes Sorensen | db08de9 | 2016-02-29 17:05:17 -0500 | [diff] [blame] | 9791 | .enable_rf = rtl8723a_enable_rf, |
Jes Sorensen | fc89a41 | 2016-02-29 17:05:46 -0500 | [diff] [blame] | 9792 | .disable_rf = rtl8723a_disable_rf, |
Jes Sorensen | 747bf23 | 2016-04-14 14:59:04 -0400 | [diff] [blame] | 9793 | .usb_quirks = rtl8xxxu_gen1_usb_quirks, |
Jes Sorensen | e796dab | 2016-02-29 17:05:19 -0500 | [diff] [blame] | 9794 | .set_tx_power = rtl8723a_set_tx_power, |
Jes Sorensen | f653e69 | 2016-02-29 17:05:38 -0500 | [diff] [blame] | 9795 | .update_rate_mask = rtl8723au_update_rate_mask, |
Jes Sorensen | 7d794ea | 2016-02-29 17:05:39 -0500 | [diff] [blame] | 9796 | .report_connect = rtl8723au_report_connect, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9797 | .writeN_block_size = 128, |
Jes Sorensen | ed35d09 | 2016-02-29 17:04:19 -0500 | [diff] [blame] | 9798 | .mbox_ext_reg = REG_HMBOX_EXT_0, |
| 9799 | .mbox_ext_width = 2, |
Jes Sorensen | dbb2896 | 2016-03-31 17:08:33 -0400 | [diff] [blame] | 9800 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc32), |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 9801 | .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc16), |
Jes Sorensen | 8634af5 | 2016-02-29 17:04:33 -0500 | [diff] [blame] | 9802 | .adda_1t_init = 0x0b1b25a0, |
| 9803 | .adda_1t_path_on = 0x0bdb25a0, |
| 9804 | .adda_2t_path_on_a = 0x04db25a4, |
| 9805 | .adda_2t_path_on_b = 0x0b1b25a4, |
Jes Sorensen | 24e8e7e | 2016-04-14 14:59:01 -0400 | [diff] [blame] | 9806 | .trxff_boundary = 0x27ff, |
Jes Sorensen | 9b323ee | 2016-04-14 14:59:03 -0400 | [diff] [blame] | 9807 | .pbp_rx = PBP_PAGE_SIZE_128, |
| 9808 | .pbp_tx = PBP_PAGE_SIZE_128, |
Jes Sorensen | c606e66 | 2016-04-07 14:19:16 -0400 | [diff] [blame] | 9809 | .mactable = rtl8723a_mac_init_table, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9810 | }; |
| 9811 | |
Kalle Valo | c096377 | 2015-10-25 18:24:38 +0200 | [diff] [blame] | 9812 | #endif |
| 9813 | |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 9814 | static struct rtl8xxxu_fileops rtl8192eu_fops = { |
| 9815 | .parse_efuse = rtl8192eu_parse_efuse, |
| 9816 | .load_firmware = rtl8192eu_load_firmware, |
Jes Sorensen | c05a9db | 2016-02-29 17:04:03 -0500 | [diff] [blame] | 9817 | .power_on = rtl8192eu_power_on, |
Jes Sorensen | fe37d5f | 2016-02-29 17:05:47 -0500 | [diff] [blame] | 9818 | .power_off = rtl8xxxu_power_off, |
Jes Sorensen | 7d4ccb8 | 2016-02-29 17:05:50 -0500 | [diff] [blame] | 9819 | .reset_8051 = rtl8xxxu_reset_8051, |
Jes Sorensen | 74b99be | 2016-02-29 17:04:04 -0500 | [diff] [blame] | 9820 | .llt_init = rtl8xxxu_auto_llt_table, |
Jes Sorensen | cb87725 | 2016-04-14 14:58:57 -0400 | [diff] [blame] | 9821 | .init_phy_bb = rtl8192eu_init_phy_bb, |
Jes Sorensen | f991f4e | 2016-04-07 14:19:32 -0400 | [diff] [blame] | 9822 | .phy_iq_calibrate = rtl8192eu_phy_iq_calibrate, |
Jes Sorensen | c3f9506 | 2016-02-29 17:04:40 -0500 | [diff] [blame] | 9823 | .config_channel = rtl8723bu_config_channel, |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 9824 | .parse_rx_desc = rtl8xxxu_parse_rxdesc24, |
Jes Sorensen | db08de9 | 2016-02-29 17:05:17 -0500 | [diff] [blame] | 9825 | .enable_rf = rtl8723b_enable_rf, |
Jes Sorensen | fc89a41 | 2016-02-29 17:05:46 -0500 | [diff] [blame] | 9826 | .disable_rf = rtl8723b_disable_rf, |
Jes Sorensen | 747bf23 | 2016-04-14 14:59:04 -0400 | [diff] [blame] | 9827 | .usb_quirks = rtl8xxxu_gen2_usb_quirks, |
Jes Sorensen | 57e42a2 | 2016-04-14 14:58:49 -0400 | [diff] [blame] | 9828 | .set_tx_power = rtl8192e_set_tx_power, |
Jes Sorensen | 91cbe4e | 2016-03-31 17:08:41 -0400 | [diff] [blame] | 9829 | .update_rate_mask = rtl8723bu_update_rate_mask, |
| 9830 | .report_connect = rtl8723bu_report_connect, |
Jes Sorensen | c05a9db | 2016-02-29 17:04:03 -0500 | [diff] [blame] | 9831 | .writeN_block_size = 128, |
Jes Sorensen | ed35d09 | 2016-02-29 17:04:19 -0500 | [diff] [blame] | 9832 | .mbox_ext_reg = REG_HMBOX_EXT0_8723B, |
| 9833 | .mbox_ext_width = 4, |
Jes Sorensen | f3fc251 | 2016-03-31 17:08:37 -0400 | [diff] [blame] | 9834 | .tx_desc_size = sizeof(struct rtl8xxxu_txdesc40), |
Jes Sorensen | a49c7ce | 2016-04-14 14:58:52 -0400 | [diff] [blame] | 9835 | .rx_desc_size = sizeof(struct rtl8xxxu_rxdesc24), |
Jes Sorensen | 55c0b6a | 2016-04-14 14:58:50 -0400 | [diff] [blame] | 9836 | .has_s0s1 = 0, |
Jes Sorensen | 8634af5 | 2016-02-29 17:04:33 -0500 | [diff] [blame] | 9837 | .adda_1t_init = 0x0fc01616, |
| 9838 | .adda_1t_path_on = 0x0fc01616, |
| 9839 | .adda_2t_path_on_a = 0x0fc01616, |
| 9840 | .adda_2t_path_on_b = 0x0fc01616, |
Jes Sorensen | 24e8e7e | 2016-04-14 14:59:01 -0400 | [diff] [blame] | 9841 | .trxff_boundary = 0x3cff, |
Jes Sorensen | c606e66 | 2016-04-07 14:19:16 -0400 | [diff] [blame] | 9842 | .mactable = rtl8192e_mac_init_table, |
Jes Sorensen | 89c2a09 | 2016-04-14 14:58:44 -0400 | [diff] [blame] | 9843 | .total_page_num = TX_TOTAL_PAGE_NUM_8192E, |
| 9844 | .page_num_hi = TX_PAGE_NUM_HI_PQ_8192E, |
| 9845 | .page_num_lo = TX_PAGE_NUM_LO_PQ_8192E, |
| 9846 | .page_num_norm = TX_PAGE_NUM_NORM_PQ_8192E, |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 9847 | }; |
| 9848 | |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9849 | static struct usb_device_id dev_table[] = { |
| 9850 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff), |
| 9851 | .driver_info = (unsigned long)&rtl8723au_fops}, |
| 9852 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff), |
| 9853 | .driver_info = (unsigned long)&rtl8723au_fops}, |
| 9854 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff), |
| 9855 | .driver_info = (unsigned long)&rtl8723au_fops}, |
Jes Sorensen | 3307d84 | 2016-02-29 17:03:59 -0500 | [diff] [blame] | 9856 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff), |
| 9857 | .driver_info = (unsigned long)&rtl8192eu_fops}, |
Jes Sorensen | 35a741f | 2016-02-29 17:04:10 -0500 | [diff] [blame] | 9858 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0xb720, 0xff, 0xff, 0xff), |
| 9859 | .driver_info = (unsigned long)&rtl8723bu_fops}, |
Kalle Valo | 033695b | 2015-10-23 20:27:58 +0300 | [diff] [blame] | 9860 | #ifdef CONFIG_RTL8XXXU_UNTESTED |
| 9861 | /* Still supported by rtlwifi */ |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9862 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff), |
| 9863 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9864 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff), |
| 9865 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9866 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff), |
| 9867 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9868 | /* Tested by Larry Finger */ |
| 9869 | {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff), |
| 9870 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
Jes Sorensen | e1d70c9 | 2016-04-14 16:37:06 -0400 | [diff] [blame] | 9871 | /* Tested by Andrea Merello */ |
| 9872 | {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff), |
| 9873 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9874 | /* Currently untested 8188 series devices */ |
| 9875 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff), |
| 9876 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9877 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff), |
| 9878 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9879 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff), |
| 9880 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9881 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff), |
| 9882 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9883 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff), |
| 9884 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9885 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff), |
| 9886 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9887 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff), |
| 9888 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9889 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff), |
| 9890 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9891 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff), |
| 9892 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9893 | {USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff), |
| 9894 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9895 | {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff), |
| 9896 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9897 | {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff), |
| 9898 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9899 | {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff), |
| 9900 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9901 | {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff), |
| 9902 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9903 | {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff), |
| 9904 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9905 | {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff), |
| 9906 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9907 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff), |
| 9908 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9909 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff), |
| 9910 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9911 | {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff), |
| 9912 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9913 | {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff), |
| 9914 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9915 | {USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff), |
| 9916 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9917 | {USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff), |
| 9918 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9919 | {USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff), |
| 9920 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9921 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff), |
| 9922 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9923 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff), |
| 9924 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9925 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff), |
| 9926 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9927 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff), |
| 9928 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9929 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff), |
| 9930 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9931 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff), |
| 9932 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9933 | {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff), |
| 9934 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9935 | {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff), |
| 9936 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9937 | {USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff), |
| 9938 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9939 | {USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff), |
| 9940 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9941 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff), |
| 9942 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9943 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff), |
| 9944 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9945 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff), |
| 9946 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9947 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff), |
| 9948 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9949 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff), |
| 9950 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9951 | {USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff), |
| 9952 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9953 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff), |
| 9954 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9955 | /* Currently untested 8192 series devices */ |
| 9956 | {USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff), |
| 9957 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
Jes Sorensen | 26f1fad | 2015-10-14 20:44:51 -0400 | [diff] [blame] | 9958 | {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff), |
| 9959 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9960 | {USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff), |
| 9961 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9962 | {USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff), |
| 9963 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9964 | {USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff), |
| 9965 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9966 | {USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff), |
| 9967 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9968 | {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff), |
| 9969 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9970 | {USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff), |
| 9971 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9972 | {USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff), |
| 9973 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9974 | {USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff), |
| 9975 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9976 | {USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff), |
| 9977 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9978 | {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff), |
| 9979 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9980 | {USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff), |
| 9981 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9982 | {USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff), |
| 9983 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9984 | {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff), |
| 9985 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9986 | {USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff), |
| 9987 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9988 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff), |
| 9989 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9990 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff), |
| 9991 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9992 | {USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff), |
| 9993 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9994 | {USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff), |
| 9995 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9996 | {USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff), |
| 9997 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 9998 | {USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff), |
| 9999 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 10000 | {USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff), |
| 10001 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 10002 | {USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff), |
| 10003 | .driver_info = (unsigned long)&rtl8192cu_fops}, |
| 10004 | #endif |
| 10005 | { } |
| 10006 | }; |
| 10007 | |
| 10008 | static struct usb_driver rtl8xxxu_driver = { |
| 10009 | .name = DRIVER_NAME, |
| 10010 | .probe = rtl8xxxu_probe, |
| 10011 | .disconnect = rtl8xxxu_disconnect, |
| 10012 | .id_table = dev_table, |
| 10013 | .disable_hub_initiated_lpm = 1, |
| 10014 | }; |
| 10015 | |
| 10016 | static int __init rtl8xxxu_module_init(void) |
| 10017 | { |
| 10018 | int res; |
| 10019 | |
| 10020 | res = usb_register(&rtl8xxxu_driver); |
| 10021 | if (res < 0) |
| 10022 | pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res); |
| 10023 | |
| 10024 | return res; |
| 10025 | } |
| 10026 | |
| 10027 | static void __exit rtl8xxxu_module_exit(void) |
| 10028 | { |
| 10029 | usb_deregister(&rtl8xxxu_driver); |
| 10030 | } |
| 10031 | |
| 10032 | |
| 10033 | MODULE_DEVICE_TABLE(usb, dev_table); |
| 10034 | |
| 10035 | module_init(rtl8xxxu_module_init); |
| 10036 | module_exit(rtl8xxxu_module_exit); |