blob: 48deca6aecc56fd5a83a08070050e4f528b46afc [file] [log] [blame]
Sandeep Panda91de3d82018-01-02 17:53:40 +05301/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
Raviteja Tamatame97849a2017-09-12 20:25:50 +05302 *
3 * This program is free software; you can redistribute it and/or modify
4 * it under the terms of the GNU General Public License version 2 and
5 * only version 2 as published by the Free Software Foundation.
6 *
7 * This program is distributed in the hope that it will be useful,
8 * but WITHOUT ANY WARRANTY; without even the implied warranty of
9 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
10 * GNU General Public License for more details.
11 */
12
13#include "dsi-panel-sim-video.dtsi"
14#include "dsi-panel-sim-cmd.dtsi"
15#include "dsi-panel-sim-dsc375-cmd.dtsi"
16#include "dsi-panel-sim-dualmipi-video.dtsi"
17#include "dsi-panel-sim-dualmipi-cmd.dtsi"
18#include "dsi-panel-sim-dualmipi-dsc375-cmd.dtsi"
19#include "dsi-panel-nt35597-truly-dualmipi-wqxga-video.dtsi"
20#include "dsi-panel-nt35597-truly-dualmipi-wqxga-cmd.dtsi"
21#include "dsi-panel-nt35597-truly-dsc-wqxga-cmd.dtsi"
22#include "dsi-panel-nt35597-truly-dsc-wqxga-video.dtsi"
Rashi Bindra5f52b4e2017-09-26 18:17:06 +053023#include "dsi-panel-nt35597-dualmipi-wqxga-video.dtsi"
24#include "dsi-panel-nt35597-dualmipi-wqxga-cmd.dtsi"
25#include "dsi-panel-nt35695b-truly-fhd-video.dtsi"
26#include "dsi-panel-nt35695b-truly-fhd-cmd.dtsi"
27#include "dsi-panel-rm67195-amoled-fhd-cmd.dtsi"
Yuan Zhao3e1868e2017-09-25 16:47:29 +080028#include "dsi-panel-nt36850-truly-dualmipi-wqhd-cmd.dtsi"
Yuan Zhaoccd2d3d2017-11-23 13:09:10 +080029#include "dsi-panel-hx8399-truly-singlemipi-fhd-video.dtsi"
Raviteja Tamatame97849a2017-09-12 20:25:50 +053030#include <dt-bindings/clock/mdss-10nm-pll-clk.h>
31
32&soc {
33 dsi_panel_pwr_supply: dsi_panel_pwr_supply {
34 #address-cells = <1>;
35 #size-cells = <0>;
36
37 qcom,panel-supply-entry@0 {
38 reg = <0>;
39 qcom,supply-name = "vddio";
40 qcom,supply-min-voltage = <1800000>;
41 qcom,supply-max-voltage = <1800000>;
42 qcom,supply-enable-load = <62000>;
43 qcom,supply-disable-load = <80>;
44 qcom,supply-post-on-sleep = <20>;
45 };
46
47 qcom,panel-supply-entry@1 {
48 reg = <1>;
49 qcom,supply-name = "lab";
50 qcom,supply-min-voltage = <4600000>;
51 qcom,supply-max-voltage = <6000000>;
52 qcom,supply-enable-load = <100000>;
53 qcom,supply-disable-load = <100>;
54 };
55
56 qcom,panel-supply-entry@2 {
57 reg = <2>;
58 qcom,supply-name = "ibb";
59 qcom,supply-min-voltage = <4600000>;
60 qcom,supply-max-voltage = <6000000>;
61 qcom,supply-enable-load = <100000>;
62 qcom,supply-disable-load = <100>;
63 qcom,supply-post-on-sleep = <20>;
64 };
65 };
66
67 dsi_panel_pwr_supply_no_labibb: dsi_panel_pwr_supply_no_labibb {
68 #address-cells = <1>;
69 #size-cells = <0>;
70
71 qcom,panel-supply-entry@0 {
72 reg = <0>;
73 qcom,supply-name = "vddio";
74 qcom,supply-min-voltage = <1800000>;
75 qcom,supply-max-voltage = <1800000>;
76 qcom,supply-enable-load = <62000>;
77 qcom,supply-disable-load = <80>;
78 qcom,supply-post-on-sleep = <20>;
79 };
80 };
81
82 dsi_panel_pwr_supply_vdd_no_labibb: dsi_panel_pwr_supply_vdd_no_labibb {
83 #address-cells = <1>;
84 #size-cells = <0>;
85
86 qcom,panel-supply-entry@0 {
87 reg = <0>;
88 qcom,supply-name = "vddio";
89 qcom,supply-min-voltage = <1800000>;
90 qcom,supply-max-voltage = <1800000>;
91 qcom,supply-enable-load = <62000>;
92 qcom,supply-disable-load = <80>;
93 qcom,supply-post-on-sleep = <20>;
94 };
95
96 qcom,panel-supply-entry@1 {
97 reg = <1>;
98 qcom,supply-name = "vdd";
99 qcom,supply-min-voltage = <3000000>;
100 qcom,supply-max-voltage = <3000000>;
101 qcom,supply-enable-load = <857000>;
102 qcom,supply-disable-load = <0>;
103 qcom,supply-post-on-sleep = <0>;
104 };
105 };
106
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530107 dsi_panel_pwr_supply_labibb_amoled: dsi_panel_pwr_supply_labibb_amoled {
108 #address-cells = <1>;
109 #size-cells = <0>;
110
111 qcom,panel-supply-entry@0 {
112 reg = <0>;
Vishnuvardhan Prodduturid5fb0802017-11-08 14:49:31 +0530113 qcom,supply-name = "vddio";
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530114 qcom,supply-min-voltage = <1800000>;
Vishnuvardhan Prodduturid5fb0802017-11-08 14:49:31 +0530115 qcom,supply-max-voltage = <1800000>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530116 qcom,supply-enable-load = <32000>;
117 qcom,supply-disable-load = <80>;
118 };
119
120 qcom,panel-supply-entry@1 {
121 reg = <1>;
122 qcom,supply-name = "vdda-3p3";
123 qcom,supply-min-voltage = <3300000>;
124 qcom,supply-max-voltage = <3300000>;
125 qcom,supply-enable-load = <13200>;
126 qcom,supply-disable-load = <80>;
127 };
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530128 };
129
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530130 dsi_dual_nt35597_truly_video_display: qcom,dsi-display@0 {
131 compatible = "qcom,dsi-display";
132 label = "dsi_dual_nt35597_truly_video_display";
133 qcom,display-type = "primary";
134
135 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
136 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
137 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
138 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
139 clock-names = "src_byte_clk", "src_pixel_clk";
140
141 pinctrl-names = "panel_active", "panel_suspend";
142 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
143 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
144 qcom,platform-reset-gpio = <&tlmm 75 0>;
145 qcom,panel-mode-gpio = <&tlmm 76 0>;
146
147 qcom,dsi-panel = <&dsi_dual_nt35597_truly_video>;
148 vddio-supply = <&pm660_l11>;
149 lab-supply = <&lcdb_ldo_vreg>;
150 ibb-supply = <&lcdb_ncp_vreg>;
151 };
152
153 dsi_dual_nt35597_truly_cmd_display: qcom,dsi-display@1 {
154 compatible = "qcom,dsi-display";
155 label = "dsi_dual_nt35597_truly_cmd_display";
156 qcom,display-type = "primary";
157
158 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
159 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
160 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
161 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
162 clock-names = "src_byte_clk", "src_pixel_clk";
163
164 pinctrl-names = "panel_active", "panel_suspend";
165 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
166 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
167 qcom,platform-te-gpio = <&tlmm 10 0>;
168 qcom,platform-reset-gpio = <&tlmm 75 0>;
169 qcom,panel-mode-gpio = <&tlmm 76 0>;
170
171 qcom,dsi-panel = <&dsi_dual_nt35597_truly_cmd>;
172 vddio-supply = <&pm660_l11>;
173 lab-supply = <&lcdb_ldo_vreg>;
174 ibb-supply = <&lcdb_ncp_vreg>;
175 };
176
177 dsi_nt35597_truly_dsc_cmd_display: qcom,dsi-display@2 {
178 compatible = "qcom,dsi-display";
179 label = "dsi_nt35597_truly_dsc_cmd_display";
180 qcom,display-type = "primary";
181
182 qcom,dsi-ctrl = <&mdss_dsi1>;
183 qcom,dsi-phy = <&mdss_dsi_phy1>;
184 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
185 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
186 clock-names = "src_byte_clk", "src_pixel_clk";
187
188 pinctrl-names = "panel_active", "panel_suspend";
189 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
190 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
191 qcom,platform-te-gpio = <&tlmm 10 0>;
192 qcom,platform-reset-gpio = <&tlmm 75 0>;
193 qcom,panel-mode-gpio = <&tlmm 76 0>;
194
195 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_cmd>;
196 vddio-supply = <&pm660_l11>;
197 lab-supply = <&lcdb_ldo_vreg>;
198 ibb-supply = <&lcdb_ncp_vreg>;
199 };
200
201 dsi_nt35597_truly_dsc_video_display: qcom,dsi-display@3 {
202 compatible = "qcom,dsi-display";
203 label = "dsi_nt35597_truly_dsc_video_display";
204 qcom,display-type = "primary";
205
206 qcom,dsi-ctrl = <&mdss_dsi1>;
207 qcom,dsi-phy = <&mdss_dsi_phy1>;
208 clocks = <&mdss_dsi1_pll BYTECLK_MUX_1_CLK>,
209 <&mdss_dsi1_pll PCLK_MUX_1_CLK>;
210 clock-names = "src_byte_clk", "src_pixel_clk";
211
212 pinctrl-names = "panel_active", "panel_suspend";
213 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
214 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
215 qcom,platform-te-gpio = <&tlmm 10 0>;
216 qcom,platform-reset-gpio = <&tlmm 75 0>;
217 qcom,panel-mode-gpio = <&tlmm 76 0>;
218
219 qcom,dsi-panel = <&dsi_nt35597_truly_dsc_video>;
220 vddio-supply = <&pm660_l11>;
221 lab-supply = <&lcdb_ldo_vreg>;
222 ibb-supply = <&lcdb_ncp_vreg>;
223 };
224
225 dsi_sim_vid_display: qcom,dsi-display@4 {
226 compatible = "qcom,dsi-display";
227 label = "dsi_sim_vid_display";
228 qcom,display-type = "primary";
229
230 qcom,dsi-ctrl = <&mdss_dsi0>;
231 qcom,dsi-phy = <&mdss_dsi_phy0>;
232 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
233 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
234 clock-names = "src_byte_clk", "src_pixel_clk";
235
236 pinctrl-names = "panel_active", "panel_suspend";
237 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
238 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
239
240 qcom,dsi-panel = <&dsi_sim_vid>;
241 };
242
243 dsi_dual_sim_vid_display: qcom,dsi-display@5 {
244 compatible = "qcom,dsi-display";
245 label = "dsi_dual_sim_vid_display";
246 qcom,display-type = "primary";
247
248 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
249 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
250 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
251 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
252 clock-names = "src_byte_clk", "src_pixel_clk";
253
254 pinctrl-names = "panel_active", "panel_suspend";
255 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
256 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
257
258 qcom,dsi-panel = <&dsi_dual_sim_vid>;
259 };
260
261 dsi_sim_cmd_display: qcom,dsi-display@6 {
262 compatible = "qcom,dsi-display";
263 label = "dsi_sim_cmd_display";
264 qcom,display-type = "primary";
265
266 qcom,dsi-ctrl = <&mdss_dsi0>;
267 qcom,dsi-phy = <&mdss_dsi_phy0>;
268 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
269 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
270 clock-names = "src_byte_clk", "src_pixel_clk";
271
272 pinctrl-names = "panel_active", "panel_suspend";
273 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
274 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
275
276 qcom,dsi-panel = <&dsi_sim_cmd>;
277 };
278
279 dsi_dual_sim_cmd_display: qcom,dsi-display@7 {
280 compatible = "qcom,dsi-display";
281 label = "dsi_dual_sim_cmd_display";
282 qcom,display-type = "primary";
283
284 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
285 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
286 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
287 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
288 clock-names = "src_byte_clk", "src_pixel_clk";
289
290 pinctrl-names = "panel_active", "panel_suspend";
291 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
292 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
293
294 qcom,dsi-panel = <&dsi_dual_sim_cmd>;
295 };
296
297 dsi_sim_dsc_375_cmd_display: qcom,dsi-display@8 {
298 compatible = "qcom,dsi-display";
299 label = "dsi_sim_dsc_375_cmd_display";
300 qcom,display-type = "primary";
301
302 qcom,dsi-ctrl = <&mdss_dsi0>;
303 qcom,dsi-phy = <&mdss_dsi_phy0>;
304 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
305 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
306 clock-names = "src_byte_clk", "src_pixel_clk";
307
308 pinctrl-names = "panel_active", "panel_suspend";
309 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
310 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
311
312 qcom,dsi-panel = <&dsi_sim_dsc_375_cmd>;
313 };
314
315 dsi_dual_sim_dsc_375_cmd_display: qcom,dsi-display@9 {
316 compatible = "qcom,dsi-display";
317 label = "dsi_dual_sim_dsc_375_cmd_display";
318 qcom,display-type = "primary";
319
320 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
321 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
322 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
323 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
324 clock-names = "src_byte_clk", "src_pixel_clk";
325
326 pinctrl-names = "panel_active", "panel_suspend";
327 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
328 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
329
330 qcom,dsi-panel = <&dsi_dual_sim_dsc_375_cmd>;
331 };
332
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530333 dsi_dual_nt35597_video_display: qcom,dsi-display@10 {
334 compatible = "qcom,dsi-display";
335 label = "dsi_dual_nt35597_video_display";
336 qcom,display-type = "primary";
337
338 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
339 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
340 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
341 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
342 clock-names = "src_byte_clk", "src_pixel_clk";
343
344 pinctrl-names = "panel_active", "panel_suspend";
345 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
346 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
347 qcom,platform-reset-gpio = <&tlmm 75 0>;
348 qcom,panel-mode-gpio = <&tlmm 76 0>;
349
350 qcom,dsi-panel = <&dsi_dual_nt35597_video>;
351 vddio-supply = <&pm660_l11>;
352 lab-supply = <&lcdb_ldo_vreg>;
353 ibb-supply = <&lcdb_ncp_vreg>;
354 };
355
356 dsi_dual_nt35597_cmd_display: qcom,dsi-display@11 {
357 compatible = "qcom,dsi-display";
358 label = "dsi_dual_nt35597_cmd_display";
359 qcom,display-type = "primary";
360
361 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
362 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
363 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
364 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
365 clock-names = "src_byte_clk", "src_pixel_clk";
366
367 pinctrl-names = "panel_active", "panel_suspend";
368 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
369 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
370 qcom,platform-reset-gpio = <&tlmm 75 0>;
371 qcom,panel-mode-gpio = <&tlmm 76 0>;
372
373 qcom,dsi-panel = <&dsi_dual_nt35597_cmd>;
374 vddio-supply = <&pm660_l11>;
375 lab-supply = <&lcdb_ldo_vreg>;
376 ibb-supply = <&lcdb_ncp_vreg>;
377 };
378
379 dsi_rm67195_amoled_fhd_cmd_display: qcom,dsi-display@12 {
380 compatible = "qcom,dsi-display";
381 label = "dsi_rm67195_amoled_fhd_cmd_display";
382 qcom,display-type = "primary";
383
384 qcom,dsi-ctrl = <&mdss_dsi0>;
385 qcom,dsi-phy = <&mdss_dsi_phy0>;
386 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
387 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
388 clock-names = "src_byte_clk", "src_pixel_clk";
389
390 pinctrl-names = "panel_active", "panel_suspend";
391 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
392 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
393 qcom,platform-te-gpio = <&tlmm 10 0>;
394 qcom,platform-reset-gpio = <&tlmm 75 0>;
395
396 qcom,dsi-panel = <&dsi_rm67195_amoled_fhd_cmd>;
397 vddio-supply = <&pm660_l11>;
Vishnuvardhan Prodduturid5fb0802017-11-08 14:49:31 +0530398 vdda-3p3-supply = <&pm660l_l6>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530399 };
400
401 dsi_nt35695b_truly_fhd_video_display: qcom,dsi-display@13 {
402 compatible = "qcom,dsi-display";
403 label = "dsi_nt35695b_truly_fhd_video_display";
404 qcom,display-type = "primary";
405
406 qcom,dsi-ctrl = <&mdss_dsi0>;
407 qcom,dsi-phy = <&mdss_dsi_phy0>;
408 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
409 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
410 clock-names = "src_byte_clk", "src_pixel_clk";
411
412 pinctrl-names = "panel_active", "panel_suspend";
413 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
414 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
415 qcom,platform-reset-gpio = <&tlmm 75 0>;
416
417 qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_video>;
418 vddio-supply = <&pm660_l11>;
419 lab-supply = <&lcdb_ldo_vreg>;
420 ibb-supply = <&lcdb_ncp_vreg>;
421 };
422
423 dsi_nt35695b_truly_fhd_cmd_display: qcom,dsi-display@14 {
424 compatible = "qcom,dsi-display";
425 label = "dsi_nt35695b_truly_fhd_cmd_display";
426 qcom,display-type = "primary";
427
428 qcom,dsi-ctrl = <&mdss_dsi0>;
429 qcom,dsi-phy = <&mdss_dsi_phy0>;
430 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
431 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
432 clock-names = "src_byte_clk", "src_pixel_clk";
433
434 pinctrl-names = "panel_active", "panel_suspend";
435 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
436 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
437 qcom,platform-te-gpio = <&tlmm 10 0>;
438 qcom,platform-reset-gpio = <&tlmm 75 0>;
439
440 qcom,dsi-panel = <&dsi_nt35695b_truly_fhd_cmd>;
441 vddio-supply = <&pm660_l11>;
442 lab-supply = <&lcdb_ldo_vreg>;
443 ibb-supply = <&lcdb_ncp_vreg>;
444 };
445
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800446 dsi_dual_nt36850_truly_cmd_display: qcom,dsi-display@15 {
447 compatible = "qcom,dsi-display";
448 label = "dsi_dual_nt36850_truly_cmd_display";
449 qcom,display-type = "primary";
450
451 qcom,dsi-ctrl = <&mdss_dsi0 &mdss_dsi1>;
452 qcom,dsi-phy = <&mdss_dsi_phy0 &mdss_dsi_phy1>;
453 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
454 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
455 clock-names = "src_byte_clk", "src_pixel_clk";
456
457 pinctrl-names = "panel_active", "panel_suspend";
458 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
459 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
460 qcom,platform-te-gpio = <&tlmm 10 0>;
461 qcom,platform-reset-gpio = <&tlmm 75 0>;
462
463 qcom,dsi-panel = <&dsi_dual_nt36850_truly_cmd>;
464 vddio-supply = <&pm660_l11>;
465 lab-supply = <&lcdb_ldo_vreg>;
466 ibb-supply = <&lcdb_ncp_vreg>;
467 };
468
Yuan Zhaoccd2d3d2017-11-23 13:09:10 +0800469 dsi_hx8399_truly_cmd_display: qcom,dsi-display@16 {
470 compatible = "qcom,dsi-display";
471 label = "dsi_hx8399_truly_cmd_display";
472 qcom,display-type = "primary";
473
474 qcom,dsi-ctrl = <&mdss_dsi0>;
475 qcom,dsi-phy = <&mdss_dsi_phy0>;
476 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
477 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
478 clock-names = "src_byte_clk", "src_pixel_clk";
479
480 pinctrl-names = "panel_active", "panel_suspend";
481 pinctrl-0 = <&sde_dsi_active &sde_te_active>;
482 pinctrl-1 = <&sde_dsi_suspend &sde_te_suspend>;
483 qcom,platform-te-gpio = <&tlmm 10 0>;
484 qcom,platform-reset-gpio = <&tlmm 75 0>;
485
486 qcom,dsi-panel = <&dsi_hx8399_truly_cmd>;
487 vddio-supply = <&pm660_l11>;
488 lab-supply = <&lcdb_ldo_vreg>;
489 ibb-supply = <&lcdb_ncp_vreg>;
490 };
491
Ray Zhang8f165582018-01-22 11:10:10 +0800492 ext_dsi_bridge_display: qcom,dsi-display@17 {
493 compatible = "qcom,dsi-display";
494 label = "ext_dsi_bridge_display";
495 qcom,display-type = "primary";
496
497 qcom,dsi-ctrl = <&mdss_dsi0>;
498 qcom,dsi-phy = <&mdss_dsi_phy0>;
499 clocks = <&mdss_dsi0_pll BYTECLK_MUX_0_CLK>,
500 <&mdss_dsi0_pll PCLK_MUX_0_CLK>;
501 clock-names = "src_byte_clk", "src_pixel_clk";
502
503 ports {
504 #address-cells = <1>;
505 #size-cells = <0>;
506
507 port@0 {
508 reg = <0>;
509 ext_dsi_out: endpoint {
510 };
511 };
512 };
513 };
514
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530515 sde_wb: qcom,wb-display@0 {
516 compatible = "qcom,wb-display";
517 cell-index = <0>;
518 label = "wb_display";
519 };
520
521 ext_disp: qcom,msm-ext-disp {
522 compatible = "qcom,msm-ext-disp";
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530523
524 ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
525 compatible = "qcom,msm-ext-disp-audio-codec-rx";
526 };
527 };
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530528};
529
530&sde_dp {
Padmanabhan Komanduruf3838e42017-10-20 12:50:47 +0530531 qcom,dp-usbpd-detection = <&pm660_pdphy>;
532 qcom,ext-disp = <&ext_disp>;
533
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530534 pinctrl-names = "mdss_dp_active", "mdss_dp_sleep";
535 pinctrl-0 = <&sde_dp_aux_active &sde_dp_usbplug_cc_active>;
536 pinctrl-1 = <&sde_dp_aux_suspend &sde_dp_usbplug_cc_suspend>;
537 qcom,aux-en-gpio = <&tlmm 50 0>;
538 qcom,aux-sel-gpio = <&tlmm 40 0>;
539 qcom,usbplug-cc-gpio = <&tlmm 38 0>;
540};
541
542&mdss_mdp {
Padmanabhan Komandurud03f38f2017-10-10 15:34:41 +0530543 connectors = <&sde_rscc &sde_wb &sde_dp>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530544};
545
546&dsi_dual_nt35597_truly_video {
547 qcom,mdss-dsi-t-clk-post = <0x0D>;
548 qcom,mdss-dsi-t-clk-pre = <0x2D>;
Raviteja Tamatam52a580f2017-10-31 11:29:06 +0530549 qcom,mdss-dsi-min-refresh-rate = <53>;
550 qcom,mdss-dsi-max-refresh-rate = <60>;
551 qcom,mdss-dsi-pan-enable-dynamic-fps;
552 qcom,mdss-dsi-pan-fps-update =
553 "dfps_immediate_porch_mode_vfp";
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530554 qcom,esd-check-enabled;
555 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
556 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
557 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
558 qcom,mdss-dsi-panel-status-value = <0x9c>;
559 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
560 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530561 qcom,mdss-dsi-display-timings {
562 timing@0{
563 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
564 07 05 03 04 00];
565 qcom,display-topology = <2 0 2>,
566 <1 0 2>;
567 qcom,default-topology-index = <0>;
568 };
569 };
570};
571
572&dsi_dual_nt35597_truly_cmd {
573 qcom,mdss-dsi-t-clk-post = <0x0D>;
574 qcom,mdss-dsi-t-clk-pre = <0x2D>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530575 qcom,ulps-enabled;
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530576 qcom,esd-check-enabled;
577 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
578 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
579 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
580 qcom,mdss-dsi-panel-status-value = <0x9c>;
581 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
582 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530583 qcom,mdss-dsi-display-timings {
584 timing@0{
585 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
586 07 05 03 04 00];
587 qcom,display-topology = <2 0 2>,
588 <1 0 2>;
589 qcom,default-topology-index = <0>;
Sandeep Pandae34dcd72017-11-23 18:33:00 +0530590 qcom,partial-update-enabled = "single_roi";
591 qcom,panel-roi-alignment = <720 128 720 128 1440 128>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530592 };
593 };
594};
595
596&dsi_nt35597_truly_dsc_cmd {
597 qcom,mdss-dsi-t-clk-post = <0x0b>;
598 qcom,mdss-dsi-t-clk-pre = <0x23>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530599 qcom,ulps-enabled;
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530600 qcom,esd-check-enabled;
601 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
602 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
603 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
604 qcom,mdss-dsi-panel-status-value = <0x9c>;
605 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
606 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530607 qcom,mdss-dsi-display-timings {
608 timing@0{
609 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
610 05 03 03 04 00];
611 qcom,display-topology = <1 1 1>,
612 <2 2 1>, /* dsc merge */
613 <2 1 1>; /* 3d mux */
614 qcom,default-topology-index = <1>;
615 };
616 };
617};
618
619&dsi_nt35597_truly_dsc_video {
620 qcom,mdss-dsi-t-clk-post = <0x0b>;
621 qcom,mdss-dsi-t-clk-pre = <0x23>;
Raviteja Tamatam52a580f2017-10-31 11:29:06 +0530622 qcom,mdss-dsi-min-refresh-rate = <53>;
623 qcom,mdss-dsi-max-refresh-rate = <60>;
624 qcom,mdss-dsi-pan-enable-dynamic-fps;
625 qcom,mdss-dsi-pan-fps-update =
626 "dfps_immediate_porch_mode_vfp";
Sandeep Panda8d29a7a2017-11-13 10:30:54 +0530627 qcom,esd-check-enabled;
628 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
629 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
630 qcom,mdss-dsi-panel-status-command-state = "dsi_hs_mode";
631 qcom,mdss-dsi-panel-status-value = <0x9c>;
632 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
633 qcom,mdss-dsi-panel-status-read-length = <1>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530634 qcom,mdss-dsi-display-timings {
635 timing@0{
636 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
637 04 03 03 04 00];
638 qcom,display-topology = <1 1 1>,
639 <2 2 1>, /* dsc merge */
640 <2 1 1>; /* 3d mux */
641 qcom,default-topology-index = <1>;
642 };
643 };
644};
645
646&dsi_sim_vid {
647 qcom,mdss-dsi-t-clk-post = <0x0d>;
648 qcom,mdss-dsi-t-clk-pre = <0x2d>;
649 qcom,mdss-dsi-display-timings {
650 timing@0{
651 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
652 07 05 03 04 00];
653 qcom,display-topology = <1 0 1>,
654 <2 0 1>;
655 qcom,default-topology-index = <0>;
656 };
657 };
658};
659
660&dsi_dual_sim_vid {
661 qcom,mdss-dsi-t-clk-post = <0x0d>;
662 qcom,mdss-dsi-t-clk-pre = <0x2d>;
663 qcom,mdss-dsi-display-timings {
664 timing@0{
665 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
666 07 05 03 04 00];
667 qcom,display-topology = <2 0 2>,
668 <1 0 2>;
669 qcom,default-topology-index = <0>;
670 };
671 };
672};
673
674&dsi_sim_cmd {
Sandeep Panda665a5352017-12-22 16:08:48 +0530675 qcom,mdss-dsi-t-clk-post = <0x0c>;
676 qcom,mdss-dsi-t-clk-pre = <0x29>;
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530677 qcom,mdss-dsi-display-timings {
678 timing@0{
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530679 qcom,display-topology = <1 0 1>,
Sandeep Panda665a5352017-12-22 16:08:48 +0530680 <2 2 1>;
681 qcom,default-topology-index = <1>;
682 qcom,panel-roi-alignment = <720 40 720 40 720 40>;
683 qcom,partial-update-enabled = "single_roi";
684 qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
685 07 04 03 04 00];
686 };
687 timing@1{
688 qcom,display-topology = <1 0 1>,
689 <2 2 1>;
690 qcom,default-topology-index = <1>;
691 qcom,panel-roi-alignment = <540 40 540 40 540 40>;
692 qcom,partial-update-enabled = "single_roi";
693 qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
694 07 04 03 04 00];
695 };
696 timing@2{
697 qcom,display-topology = <1 0 1>,
698 <2 2 1>;
699 qcom,default-topology-index = <1>;
700 qcom,panel-roi-alignment = <360 40 360 40 360 40>;
701 qcom,partial-update-enabled = "single_roi";
702 qcom,mdss-dsi-panel-phy-timings = [00 1a 06 06 22 20 07
703 07 04 03 04 00];
Raviteja Tamatame97849a2017-09-12 20:25:50 +0530704 };
705 };
706};
707
708&dsi_dual_sim_cmd {
709 qcom,mdss-dsi-t-clk-post = <0x0d>;
710 qcom,mdss-dsi-t-clk-pre = <0x2d>;
711 qcom,mdss-dsi-display-timings {
712 timing@0{
713 qcom,mdss-dsi-panel-phy-timings = [00 24 09 09 26 24 09
714 09 06 03 04 00];
715 qcom,display-topology = <2 0 2>;
716 qcom,default-topology-index = <0>;
717 };
718 timing@1{
719 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
720 07 05 03 04 00];
721 qcom,display-topology = <2 0 2>,
722 <1 0 2>;
723 qcom,default-topology-index = <0>;
724 };
725 timing@2{
726 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
727 06 04 03 04 00];
728 qcom,display-topology = <2 0 2>;
729 qcom,default-topology-index = <0>;
730 };
731 };
732};
733
734&dsi_sim_dsc_375_cmd {
735 qcom,mdss-dsi-t-clk-post = <0x0d>;
736 qcom,mdss-dsi-t-clk-pre = <0x2d>;
737 qcom,mdss-dsi-display-timings {
738 timing@0 { /* 1080p */
739 qcom,mdss-dsi-panel-phy-timings = [00 1A 06 06 22 20 07
740 07 04 03 04 00];
741 qcom,display-topology = <1 1 1>;
742 qcom,default-topology-index = <0>;
743 };
744 timing@1 { /* qhd */
745 qcom,mdss-dsi-panel-phy-timings = [00 15 05 05 20 1f 05
746 05 03 03 04 00];
747 qcom,display-topology = <1 1 1>,
748 <2 2 1>, /* dsc merge */
749 <2 1 1>; /* 3d mux */
750 qcom,default-topology-index = <0>;
751 };
752 };
753};
754
755&dsi_dual_sim_dsc_375_cmd {
756 qcom,mdss-dsi-t-clk-post = <0x0d>;
757 qcom,mdss-dsi-t-clk-pre = <0x2d>;
758 qcom,mdss-dsi-display-timings {
759 timing@0 { /* qhd */
760 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
761 07 05 03 04 00];
762 qcom,display-topology = <2 2 2>;
763 qcom,default-topology-index = <0>;
764 };
765 timing@1 { /* 4k */
766 qcom,mdss-dsi-panel-phy-timings = [00 18 06 06 21 20 06
767 06 04 03 04 00];
768 qcom,display-topology = <2 2 2>;
769 qcom,default-topology-index = <0>;
770 };
771 };
772};
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530773
774&dsi_dual_nt35597_video {
775 qcom,mdss-dsi-t-clk-post = <0x0d>;
776 qcom,mdss-dsi-t-clk-pre = <0x2d>;
777 qcom,mdss-dsi-display-timings {
778 timing@0 {
Sandeep Panda4443ddb2017-12-15 15:56:17 +0530779 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
780 07 05 03 04 00];
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530781 qcom,display-topology = <2 0 2>,
782 <1 0 2>;
783 qcom,default-topology-index = <0>;
784 };
785 };
786};
787
788&dsi_dual_nt35597_cmd {
789 qcom,mdss-dsi-t-clk-post = <0x0d>;
790 qcom,mdss-dsi-t-clk-pre = <0x2d>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530791 qcom,ulps-enabled;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530792 qcom,mdss-dsi-display-timings {
793 timing@0 {
Sandeep Panda4443ddb2017-12-15 15:56:17 +0530794 qcom,mdss-dsi-panel-phy-timings = [00 1c 07 07 23 21 07
795 07 05 03 04 00];
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530796 qcom,display-topology = <2 0 2>,
797 <1 0 2>;
798 qcom,default-topology-index = <0>;
Sandeep Pandae34dcd72017-11-23 18:33:00 +0530799 qcom,partial-update-enabled = "single_roi";
800 qcom,panel-roi-alignment = <720 128 720 128 1440 128>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530801 };
802 };
803};
804
805&dsi_rm67195_amoled_fhd_cmd {
806 qcom,mdss-dsi-t-clk-post = <0x07>;
807 qcom,mdss-dsi-t-clk-pre = <0x1c>;
808 qcom,mdss-dsi-display-timings {
809 timing@0 {
810 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
811 05 07 05 03 04 00];
812 qcom,display-topology = <1 0 1>;
813 qcom,default-topology-index = <0>;
814 };
815 };
816};
817
818&dsi_nt35695b_truly_fhd_video {
819 qcom,mdss-dsi-t-clk-post = <0x07>;
820 qcom,mdss-dsi-t-clk-pre = <0x1c>;
Raviteja Tamatamd5ca1b82017-11-30 13:23:54 +0530821 qcom,mdss-dsi-min-refresh-rate = <48>;
822 qcom,mdss-dsi-max-refresh-rate = <60>;
823 qcom,mdss-dsi-pan-enable-dynamic-fps;
824 qcom,mdss-dsi-pan-fps-update =
825 "dfps_immediate_porch_mode_vfp";
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530826 qcom,mdss-dsi-display-timings {
827 timing@0 {
828 qcom,mdss-dsi-panel-phy-timings = [00 1c 05 06 0b 0c
829 05 07 05 03 04 00];
830 qcom,display-topology = <1 0 1>;
831 qcom,default-topology-index = <0>;
832 };
833 };
834};
835
836&dsi_nt35695b_truly_fhd_cmd {
Sandeep Panda91de3d82018-01-02 17:53:40 +0530837 qcom,mdss-dsi-t-clk-post = <0x0d>;
838 qcom,mdss-dsi-t-clk-pre = <0x2d>;
Sandeep Panda5d8d7242017-11-01 12:15:33 +0530839 qcom,ulps-enabled;
Jayant Shekhar4812b012018-01-03 18:47:24 +0530840 qcom,mdss-mdp-transfer-time-us = <14500>;
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530841 qcom,mdss-dsi-display-timings {
842 timing@0 {
Sandeep Panda91de3d82018-01-02 17:53:40 +0530843 qcom,mdss-dsi-panel-phy-timings = [00 1c 08 07 23 22
844 07 07 05 03 04 00];
Rashi Bindra5f52b4e2017-09-26 18:17:06 +0530845 qcom,display-topology = <1 0 1>;
846 qcom,default-topology-index = <0>;
847 };
848 };
849};
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800850
851&dsi_dual_nt36850_truly_cmd {
Yuan Zhao33c507a2018-01-04 19:39:07 +0800852 qcom,mdss-dsi-t-clk-post = <0x28>;
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800853 qcom,mdss-dsi-t-clk-pre = <0x30>;
Yuan Zhao33c507a2018-01-04 19:39:07 +0800854 qcom,esd-check-enabled;
855 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
856 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
Yuan Zhao77bf6f72018-02-08 14:32:50 +0800857 qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
Yuan Zhao33c507a2018-01-04 19:39:07 +0800858 qcom,mdss-dsi-panel-status-value = <0x9c>;
859 qcom,mdss-dsi-panel-on-check-value = <0x9c>;
860 qcom,mdss-dsi-panel-status-read-length = <1>;
Yuan Zhao3e1868e2017-09-25 16:47:29 +0800861 qcom,mdss-dsi-display-timings {
862 timing@0{
863 qcom,mdss-dsi-panel-phy-timings = [00 1f 08 08 24 23 08
864 08 05 03 04 00];
865 qcom,display-topology = <2 0 2>,
866 <1 0 2>;
867 qcom,default-topology-index = <0>;
868 };
869 };
870};
Yuan Zhaoccd2d3d2017-11-23 13:09:10 +0800871
872&dsi_hx8399_truly_cmd {
873 qcom,mdss-dsi-t-clk-post = <0x0E>;
874 qcom,mdss-dsi-t-clk-pre = <0x30>;
Yuan Zhao77bf6f72018-02-08 14:32:50 +0800875 qcom,mdss-dsi-min-refresh-rate = <55>;
876 qcom,mdss-dsi-max-refresh-rate = <60>;
877 qcom,mdss-dsi-pan-enable-dynamic-fps;
878 qcom,mdss-dsi-pan-fps-update =
879 "dfps_immediate_porch_mode_vfp";
880 qcom,esd-check-enabled;
881 qcom,mdss-dsi-panel-status-check-mode = "reg_read";
882 qcom,mdss-dsi-panel-status-command = [06 01 00 01 00 00 01 0a];
883 qcom,mdss-dsi-panel-status-command-state = "dsi_lp_mode";
884 qcom,mdss-dsi-panel-status-value = <0x9d 0x9d 0x9d 0x9d>;
885 qcom,mdss-dsi-panel-on-check-value = <0x9d 0x9d 0x9d 0x9d>;
886 qcom,mdss-dsi-panel-status-read-length = <4>;
Yuan Zhaoccd2d3d2017-11-23 13:09:10 +0800887 qcom,mdss-dsi-display-timings {
888 timing@0 {
889 qcom,mdss-dsi-panel-phy-timings = [00 1f 08 08 24 22 08
890 08 05 03 04 00];
891 qcom,display-topology = <1 0 1>;
892 qcom,default-topology-index = <0>;
893 };
894 };
895};