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Linus Torvalds1da177e2005-04-16 15:20:36 -07001/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 * PCI Bus Services, see include/linux/pci.h for further explanation.
3 *
4 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
5 * David Mosberger-Tang
6 *
7 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
8 */
9
Tomasz Nowicki2ab51dd2016-06-10 15:36:26 -050010#include <linux/acpi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070011#include <linux/kernel.h>
12#include <linux/delay.h>
Mika Westerberg9d26d3a2016-06-02 11:17:12 +030013#include <linux/dmi.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070014#include <linux/init.h>
Lorenzo Pieralisi7c674702014-12-27 18:19:12 -070015#include <linux/of.h>
16#include <linux/of_pci.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070017#include <linux/pci.h>
David Brownell075c1772007-04-26 00:12:06 -070018#include <linux/pm.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090019#include <linux/slab.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070020#include <linux/module.h>
21#include <linux/spinlock.h>
Tim Schmielau4e57b682005-10-30 15:03:48 -080022#include <linux/string.h>
vignesh babu229f5af2007-08-13 18:23:14 +053023#include <linux/log2.h>
Shaohua Li7d715a62008-02-25 09:46:41 +080024#include <linux/pci-aspm.h>
Stephen Rothwellc300bd2fb2008-07-10 02:16:44 +020025#include <linux/pm_wakeup.h>
Sheng Yang8dd7f802008-10-21 17:38:25 +080026#include <linux/interrupt.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090027#include <linux/device.h>
Rafael J. Wysockib67ea762010-02-17 23:44:09 +010028#include <linux/pm_runtime.h>
Alex Williamson608c3882013-08-08 14:09:43 -060029#include <linux/pci_hotplug.h>
Sinan Kaya4d3f1382016-06-10 21:55:11 +020030#include <linux/vmalloc.h>
Yuji Shimada32a9a6822009-03-16 17:13:39 +090031#include <asm/setup.h>
Ben Dooks2a2aca32016-06-17 16:05:13 +010032#include <asm/dma.h>
Taku Izumib07461a2015-09-17 10:09:37 -050033#include <linux/aer.h>
Greg KHbc56b9e2005-04-08 14:53:31 +090034#include "pci.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070035
Alan Stern00240c32009-04-27 13:33:16 -040036const char *pci_power_names[] = {
37 "error", "D0", "D1", "D2", "D3hot", "D3cold", "unknown",
38};
39EXPORT_SYMBOL_GPL(pci_power_names);
40
Rafael J. Wysocki93177a72010-01-02 22:57:24 +010041int isa_dma_bridge_buggy;
42EXPORT_SYMBOL(isa_dma_bridge_buggy);
43
44int pci_pci_problems;
45EXPORT_SYMBOL(pci_pci_problems);
46
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +010047unsigned int pci_pm_d3_delay;
48
Matthew Garrettdf17e622010-10-04 14:22:29 -040049static void pci_pme_list_scan(struct work_struct *work);
50
51static LIST_HEAD(pci_pme_list);
52static DEFINE_MUTEX(pci_pme_list_mutex);
53static DECLARE_DELAYED_WORK(pci_pme_work, pci_pme_list_scan);
54
55struct pci_pme_device {
56 struct list_head list;
57 struct pci_dev *dev;
58};
59
60#define PME_TIMEOUT 1000 /* How long between PME checks */
61
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +010062static void pci_dev_d3_sleep(struct pci_dev *dev)
63{
64 unsigned int delay = dev->d3_delay;
65
66 if (delay < pci_pm_d3_delay)
67 delay = pci_pm_d3_delay;
68
69 msleep(delay);
70}
Linus Torvalds1da177e2005-04-16 15:20:36 -070071
Jeff Garzik32a2eea2007-10-11 16:57:27 -040072#ifdef CONFIG_PCI_DOMAINS
73int pci_domains_supported = 1;
74#endif
75
Atsushi Nemoto4516a612007-02-05 16:36:06 -080076#define DEFAULT_CARDBUS_IO_SIZE (256)
77#define DEFAULT_CARDBUS_MEM_SIZE (64*1024*1024)
78/* pci=cbmemsize=nnM,cbiosize=nn can override this */
79unsigned long pci_cardbus_io_size = DEFAULT_CARDBUS_IO_SIZE;
80unsigned long pci_cardbus_mem_size = DEFAULT_CARDBUS_MEM_SIZE;
81
Eric W. Biederman28760482009-09-09 14:09:24 -070082#define DEFAULT_HOTPLUG_IO_SIZE (256)
83#define DEFAULT_HOTPLUG_MEM_SIZE (2*1024*1024)
84/* pci=hpmemsize=nnM,hpiosize=nn can override this */
85unsigned long pci_hotplug_io_size = DEFAULT_HOTPLUG_IO_SIZE;
86unsigned long pci_hotplug_mem_size = DEFAULT_HOTPLUG_MEM_SIZE;
87
Keith Busche16b4662016-07-21 21:40:28 -060088#define DEFAULT_HOTPLUG_BUS_SIZE 1
89unsigned long pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
90
Keith Busch27d868b2015-08-24 08:48:16 -050091enum pcie_bus_config_types pcie_bus_config = PCIE_BUS_DEFAULT;
Jon Masonb03e7492011-07-20 15:20:54 -050092
Jesse Barnesac1aa472009-10-26 13:20:44 -070093/*
94 * The default CLS is used if arch didn't set CLS explicitly and not
95 * all pci devices agree on the same value. Arch can override either
96 * the dfl or actual value as it sees fit. Don't forget this is
97 * measured in 32-bit words, not bytes.
98 */
Bill Pemberton15856ad2012-11-21 15:35:00 -050099u8 pci_dfl_cache_line_size = L1_CACHE_BYTES >> 2;
Jesse Barnesac1aa472009-10-26 13:20:44 -0700100u8 pci_cache_line_size;
101
Myron Stowe96c55902011-10-28 15:48:38 -0600102/*
103 * If we set up a device for bus mastering, we need to check the latency
104 * timer as certain BIOSes forget to set it properly.
105 */
106unsigned int pcibios_max_latency = 255;
107
Rafael J. Wysocki6748dcc2012-03-01 00:06:33 +0100108/* If set, the PCIe ARI capability will not be used. */
109static bool pcie_ari_disabled;
110
Mika Westerberg9d26d3a2016-06-02 11:17:12 +0300111/* Disable bridge_d3 for all PCIe ports */
112static bool pci_bridge_d3_disable;
113/* Force bridge_d3 for all PCIe ports */
114static bool pci_bridge_d3_force;
115
116static int __init pcie_port_pm_setup(char *str)
117{
118 if (!strcmp(str, "off"))
119 pci_bridge_d3_disable = true;
120 else if (!strcmp(str, "force"))
121 pci_bridge_d3_force = true;
122 return 1;
123}
124__setup("pcie_port_pm=", pcie_port_pm_setup);
125
Linus Torvalds1da177e2005-04-16 15:20:36 -0700126/**
127 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
128 * @bus: pointer to PCI bus structure to search
129 *
130 * Given a PCI bus, returns the highest PCI bus number present in the set
131 * including the given PCI bus and its list of child PCI buses.
132 */
Ryan Desfosses07656d83082014-04-11 01:01:53 -0400133unsigned char pci_bus_max_busnr(struct pci_bus *bus)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700134{
Yijing Wang94e6a9b2014-02-13 21:14:03 +0800135 struct pci_bus *tmp;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700136 unsigned char max, n;
137
Yinghai Lub918c622012-05-17 18:51:11 -0700138 max = bus->busn_res.end;
Yijing Wang94e6a9b2014-02-13 21:14:03 +0800139 list_for_each_entry(tmp, &bus->children, node) {
140 n = pci_bus_max_busnr(tmp);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400141 if (n > max)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700142 max = n;
143 }
144 return max;
145}
Kristen Accardib82db5c2006-01-17 16:56:56 -0800146EXPORT_SYMBOL_GPL(pci_bus_max_busnr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700147
Andrew Morton1684f5d2008-12-01 14:30:30 -0800148#ifdef CONFIG_HAS_IOMEM
149void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar)
150{
Bjorn Helgaas1f7bf3b2015-03-12 12:30:11 -0500151 struct resource *res = &pdev->resource[bar];
152
Andrew Morton1684f5d2008-12-01 14:30:30 -0800153 /*
154 * Make sure the BAR is actually a memory resource, not an IO resource
155 */
Bjorn Helgaas646c0282015-03-12 12:30:15 -0500156 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) {
Bjorn Helgaas1f7bf3b2015-03-12 12:30:11 -0500157 dev_warn(&pdev->dev, "can't ioremap BAR %d: %pR\n", bar, res);
Andrew Morton1684f5d2008-12-01 14:30:30 -0800158 return NULL;
159 }
Bjorn Helgaas1f7bf3b2015-03-12 12:30:11 -0500160 return ioremap_nocache(res->start, resource_size(res));
Andrew Morton1684f5d2008-12-01 14:30:30 -0800161}
162EXPORT_SYMBOL_GPL(pci_ioremap_bar);
Luis R. Rodriguezc43996f2015-08-24 12:13:23 -0700163
164void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar)
165{
166 /*
167 * Make sure the BAR is actually a memory resource, not an IO resource
168 */
169 if (!(pci_resource_flags(pdev, bar) & IORESOURCE_MEM)) {
170 WARN_ON(1);
171 return NULL;
172 }
173 return ioremap_wc(pci_resource_start(pdev, bar),
174 pci_resource_len(pdev, bar));
175}
176EXPORT_SYMBOL_GPL(pci_ioremap_wc_bar);
Andrew Morton1684f5d2008-12-01 14:30:30 -0800177#endif
178
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100179
180static int __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn,
181 u8 pos, int cap, int *ttl)
Roland Dreier24a4e372005-10-28 17:35:34 -0700182{
183 u8 id;
Sean O. Stalley55db3202015-04-02 14:10:19 -0700184 u16 ent;
185
186 pci_bus_read_config_byte(bus, devfn, pos, &pos);
Roland Dreier24a4e372005-10-28 17:35:34 -0700187
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100188 while ((*ttl)--) {
Roland Dreier24a4e372005-10-28 17:35:34 -0700189 if (pos < 0x40)
190 break;
191 pos &= ~3;
Sean O. Stalley55db3202015-04-02 14:10:19 -0700192 pci_bus_read_config_word(bus, devfn, pos, &ent);
193
194 id = ent & 0xff;
Roland Dreier24a4e372005-10-28 17:35:34 -0700195 if (id == 0xff)
196 break;
197 if (id == cap)
198 return pos;
Sean O. Stalley55db3202015-04-02 14:10:19 -0700199 pos = (ent >> 8);
Roland Dreier24a4e372005-10-28 17:35:34 -0700200 }
201 return 0;
202}
203
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100204static int __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn,
205 u8 pos, int cap)
206{
207 int ttl = PCI_FIND_CAP_TTL;
208
209 return __pci_find_next_cap_ttl(bus, devfn, pos, cap, &ttl);
210}
211
Roland Dreier24a4e372005-10-28 17:35:34 -0700212int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap)
213{
214 return __pci_find_next_cap(dev->bus, dev->devfn,
215 pos + PCI_CAP_LIST_NEXT, cap);
216}
217EXPORT_SYMBOL_GPL(pci_find_next_capability);
218
Michael Ellermand3bac112006-11-22 18:26:16 +1100219static int __pci_bus_find_cap_start(struct pci_bus *bus,
220 unsigned int devfn, u8 hdr_type)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700221{
222 u16 status;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700223
224 pci_bus_read_config_word(bus, devfn, PCI_STATUS, &status);
225 if (!(status & PCI_STATUS_CAP_LIST))
226 return 0;
227
228 switch (hdr_type) {
229 case PCI_HEADER_TYPE_NORMAL:
230 case PCI_HEADER_TYPE_BRIDGE:
Michael Ellermand3bac112006-11-22 18:26:16 +1100231 return PCI_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700232 case PCI_HEADER_TYPE_CARDBUS:
Michael Ellermand3bac112006-11-22 18:26:16 +1100233 return PCI_CB_CAPABILITY_LIST;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700234 }
Michael Ellermand3bac112006-11-22 18:26:16 +1100235
236 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700237}
238
239/**
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700240 * pci_find_capability - query for devices' capabilities
Linus Torvalds1da177e2005-04-16 15:20:36 -0700241 * @dev: PCI device to query
242 * @cap: capability code
243 *
244 * Tell if a device supports a given PCI capability.
245 * Returns the address of the requested capability structure within the
246 * device's PCI configuration space or 0 in case the device does not
247 * support it. Possible values for @cap:
248 *
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700249 * %PCI_CAP_ID_PM Power Management
250 * %PCI_CAP_ID_AGP Accelerated Graphics Port
251 * %PCI_CAP_ID_VPD Vital Product Data
252 * %PCI_CAP_ID_SLOTID Slot Identification
Linus Torvalds1da177e2005-04-16 15:20:36 -0700253 * %PCI_CAP_ID_MSI Message Signalled Interrupts
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700254 * %PCI_CAP_ID_CHSWP CompactPCI HotSwap
Linus Torvalds1da177e2005-04-16 15:20:36 -0700255 * %PCI_CAP_ID_PCIX PCI-X
256 * %PCI_CAP_ID_EXP PCI Express
257 */
258int pci_find_capability(struct pci_dev *dev, int cap)
259{
Michael Ellermand3bac112006-11-22 18:26:16 +1100260 int pos;
261
262 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
263 if (pos)
264 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap);
265
266 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700267}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -0600268EXPORT_SYMBOL(pci_find_capability);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700269
270/**
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700271 * pci_bus_find_capability - query for devices' capabilities
Linus Torvalds1da177e2005-04-16 15:20:36 -0700272 * @bus: the PCI bus to query
273 * @devfn: PCI device to query
274 * @cap: capability code
275 *
276 * Like pci_find_capability() but works for pci devices that do not have a
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700277 * pci_dev structure set up yet.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700278 *
279 * Returns the address of the requested capability structure within the
280 * device's PCI configuration space or 0 in case the device does not
281 * support it.
282 */
283int pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap)
284{
Michael Ellermand3bac112006-11-22 18:26:16 +1100285 int pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700286 u8 hdr_type;
287
288 pci_bus_read_config_byte(bus, devfn, PCI_HEADER_TYPE, &hdr_type);
289
Michael Ellermand3bac112006-11-22 18:26:16 +1100290 pos = __pci_bus_find_cap_start(bus, devfn, hdr_type & 0x7f);
291 if (pos)
292 pos = __pci_find_next_cap(bus, devfn, pos, cap);
293
294 return pos;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700295}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -0600296EXPORT_SYMBOL(pci_bus_find_capability);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700297
298/**
Bjorn Helgaas44a9a362012-07-13 14:24:59 -0600299 * pci_find_next_ext_capability - Find an extended capability
300 * @dev: PCI device to query
301 * @start: address at which to start looking (0 to start at beginning of list)
302 * @cap: capability code
303 *
304 * Returns the address of the next matching extended capability structure
305 * within the device's PCI configuration space or 0 if the device does
306 * not support it. Some capabilities can occur several times, e.g., the
307 * vendor-specific capability, and this provides a way to find them all.
308 */
309int pci_find_next_ext_capability(struct pci_dev *dev, int start, int cap)
310{
311 u32 header;
312 int ttl;
313 int pos = PCI_CFG_SPACE_SIZE;
314
315 /* minimum 8 bytes per capability */
316 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
317
318 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE)
319 return 0;
320
321 if (start)
322 pos = start;
323
324 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
325 return 0;
326
327 /*
328 * If we have no capabilities, this is indicated by cap ID,
329 * cap version and next pointer all being 0.
330 */
331 if (header == 0)
332 return 0;
333
334 while (ttl-- > 0) {
335 if (PCI_EXT_CAP_ID(header) == cap && pos != start)
336 return pos;
337
338 pos = PCI_EXT_CAP_NEXT(header);
339 if (pos < PCI_CFG_SPACE_SIZE)
340 break;
341
342 if (pci_read_config_dword(dev, pos, &header) != PCIBIOS_SUCCESSFUL)
343 break;
344 }
345
346 return 0;
347}
348EXPORT_SYMBOL_GPL(pci_find_next_ext_capability);
349
350/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700351 * pci_find_ext_capability - Find an extended capability
352 * @dev: PCI device to query
353 * @cap: capability code
354 *
355 * Returns the address of the requested extended capability structure
356 * within the device's PCI configuration space or 0 if the device does
357 * not support it. Possible values for @cap:
358 *
359 * %PCI_EXT_CAP_ID_ERR Advanced Error Reporting
360 * %PCI_EXT_CAP_ID_VC Virtual Channel
361 * %PCI_EXT_CAP_ID_DSN Device Serial Number
362 * %PCI_EXT_CAP_ID_PWR Power Budgeting
363 */
364int pci_find_ext_capability(struct pci_dev *dev, int cap)
365{
Bjorn Helgaas44a9a362012-07-13 14:24:59 -0600366 return pci_find_next_ext_capability(dev, 0, cap);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700367}
Brice Goglin3a720d72006-05-23 06:10:01 -0400368EXPORT_SYMBOL_GPL(pci_find_ext_capability);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700369
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100370static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
371{
372 int rc, ttl = PCI_FIND_CAP_TTL;
373 u8 cap, mask;
374
375 if (ht_cap == HT_CAPTYPE_SLAVE || ht_cap == HT_CAPTYPE_HOST)
376 mask = HT_3BIT_CAP_MASK;
377 else
378 mask = HT_5BIT_CAP_MASK;
379
380 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos,
381 PCI_CAP_ID_HT, &ttl);
382 while (pos) {
383 rc = pci_read_config_byte(dev, pos + 3, &cap);
384 if (rc != PCIBIOS_SUCCESSFUL)
385 return 0;
386
387 if ((cap & mask) == ht_cap)
388 return pos;
389
Brice Goglin47a4d5b2007-01-10 23:15:29 -0800390 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn,
391 pos + PCI_CAP_LIST_NEXT,
Michael Ellerman687d5fe2006-11-22 18:26:18 +1100392 PCI_CAP_ID_HT, &ttl);
393 }
394
395 return 0;
396}
397/**
398 * pci_find_next_ht_capability - query a device's Hypertransport capabilities
399 * @dev: PCI device to query
400 * @pos: Position from which to continue searching
401 * @ht_cap: Hypertransport capability code
402 *
403 * To be used in conjunction with pci_find_ht_capability() to search for
404 * all capabilities matching @ht_cap. @pos should always be a value returned
405 * from pci_find_ht_capability().
406 *
407 * NB. To be 100% safe against broken PCI devices, the caller should take
408 * steps to avoid an infinite loop.
409 */
410int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap)
411{
412 return __pci_find_next_ht_cap(dev, pos + PCI_CAP_LIST_NEXT, ht_cap);
413}
414EXPORT_SYMBOL_GPL(pci_find_next_ht_capability);
415
416/**
417 * pci_find_ht_capability - query a device's Hypertransport capabilities
418 * @dev: PCI device to query
419 * @ht_cap: Hypertransport capability code
420 *
421 * Tell if a device supports a given Hypertransport capability.
422 * Returns an address within the device's PCI configuration space
423 * or 0 in case the device does not support the request capability.
424 * The address points to the PCI capability, of type PCI_CAP_ID_HT,
425 * which has a Hypertransport capability matching @ht_cap.
426 */
427int pci_find_ht_capability(struct pci_dev *dev, int ht_cap)
428{
429 int pos;
430
431 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type);
432 if (pos)
433 pos = __pci_find_next_ht_cap(dev, pos, ht_cap);
434
435 return pos;
436}
437EXPORT_SYMBOL_GPL(pci_find_ht_capability);
438
Linus Torvalds1da177e2005-04-16 15:20:36 -0700439/**
440 * pci_find_parent_resource - return resource region of parent bus of given region
441 * @dev: PCI device structure contains resources to be searched
442 * @res: child resource record for which parent is sought
443 *
444 * For given resource region of given device, return the resource
Bjorn Helgaasf44116a2014-02-26 11:25:58 -0700445 * region of parent bus the given region is contained in.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700446 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400447struct resource *pci_find_parent_resource(const struct pci_dev *dev,
448 struct resource *res)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700449{
450 const struct pci_bus *bus = dev->bus;
Bjorn Helgaasf44116a2014-02-26 11:25:58 -0700451 struct resource *r;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700452 int i;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700453
Bjorn Helgaas89a74ec2010-02-23 10:24:31 -0700454 pci_bus_for_each_resource(bus, r, i) {
Linus Torvalds1da177e2005-04-16 15:20:36 -0700455 if (!r)
456 continue;
Bjorn Helgaasf44116a2014-02-26 11:25:58 -0700457 if (res->start && resource_contains(r, res)) {
458
459 /*
460 * If the window is prefetchable but the BAR is
461 * not, the allocator made a mistake.
462 */
463 if (r->flags & IORESOURCE_PREFETCH &&
464 !(res->flags & IORESOURCE_PREFETCH))
465 return NULL;
466
467 /*
468 * If we're below a transparent bridge, there may
469 * be both a positively-decoded aperture and a
470 * subtractively-decoded region that contain the BAR.
471 * We want the positively-decoded one, so this depends
472 * on pci_bus_for_each_resource() giving us those
473 * first.
474 */
475 return r;
476 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700477 }
Bjorn Helgaasf44116a2014-02-26 11:25:58 -0700478 return NULL;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700479}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -0600480EXPORT_SYMBOL(pci_find_parent_resource);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700481
482/**
Mika Westerbergafd29f92016-09-15 11:07:03 +0300483 * pci_find_resource - Return matching PCI device resource
484 * @dev: PCI device to query
485 * @res: Resource to look for
486 *
487 * Goes over standard PCI resources (BARs) and checks if the given resource
488 * is partially or fully contained in any of them. In that case the
489 * matching resource is returned, %NULL otherwise.
490 */
491struct resource *pci_find_resource(struct pci_dev *dev, struct resource *res)
492{
493 int i;
494
495 for (i = 0; i < PCI_ROM_RESOURCE; i++) {
496 struct resource *r = &dev->resource[i];
497
498 if (r->start && resource_contains(r, res))
499 return r;
500 }
501
502 return NULL;
503}
504EXPORT_SYMBOL(pci_find_resource);
505
506/**
Hariprasad Shenaic56d4452015-10-18 19:55:04 +0530507 * pci_find_pcie_root_port - return PCIe Root Port
508 * @dev: PCI device to query
509 *
510 * Traverse up the parent chain and return the PCIe Root Port PCI Device
511 * for a given PCI Device.
512 */
513struct pci_dev *pci_find_pcie_root_port(struct pci_dev *dev)
514{
515 struct pci_dev *bridge, *highest_pcie_bridge = NULL;
516
517 bridge = pci_upstream_bridge(dev);
518 while (bridge && pci_is_pcie(bridge)) {
519 highest_pcie_bridge = bridge;
520 bridge = pci_upstream_bridge(bridge);
521 }
522
523 if (pci_pcie_type(highest_pcie_bridge) != PCI_EXP_TYPE_ROOT_PORT)
524 return NULL;
525
526 return highest_pcie_bridge;
527}
528EXPORT_SYMBOL(pci_find_pcie_root_port);
529
530/**
Alex Williamson157e8762013-12-17 16:43:39 -0700531 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
532 * @dev: the PCI device to operate on
533 * @pos: config space offset of status word
534 * @mask: mask of bit(s) to care about in status word
535 *
536 * Return 1 when mask bit(s) in status word clear, 0 otherwise.
537 */
538int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask)
539{
540 int i;
541
542 /* Wait for Transaction Pending bit clean */
543 for (i = 0; i < 4; i++) {
544 u16 status;
545 if (i)
546 msleep((1 << (i - 1)) * 100);
547
548 pci_read_config_word(dev, pos, &status);
549 if (!(status & mask))
550 return 1;
551 }
552
553 return 0;
554}
555
556/**
Wei Yang70675e02015-07-29 16:52:58 +0800557 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
John W. Linville064b53db2005-07-27 10:19:44 -0400558 * @dev: PCI device to have its BARs restored
559 *
560 * Restore the BAR values for a given device, so as to make it
561 * accessible by its driver.
562 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400563static void pci_restore_bars(struct pci_dev *dev)
John W. Linville064b53db2005-07-27 10:19:44 -0400564{
Yu Zhaobc5f5a82008-11-22 02:40:00 +0800565 int i;
John W. Linville064b53db2005-07-27 10:19:44 -0400566
Yu Zhaobc5f5a82008-11-22 02:40:00 +0800567 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++)
Yu Zhao14add802008-11-22 02:38:52 +0800568 pci_update_resource(dev, i);
John W. Linville064b53db2005-07-27 10:19:44 -0400569}
570
Julia Lawall299f2ff2015-12-06 17:33:45 +0100571static const struct pci_platform_pm_ops *pci_platform_pm;
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200572
Julia Lawall299f2ff2015-12-06 17:33:45 +0100573int pci_set_platform_pm(const struct pci_platform_pm_ops *ops)
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200574{
Lukas Wunnercc7cc022016-09-18 05:39:20 +0200575 if (!ops->is_manageable || !ops->set_state || !ops->get_state ||
576 !ops->choose_state || !ops->sleep_wake || !ops->run_wake ||
577 !ops->need_resume)
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200578 return -EINVAL;
579 pci_platform_pm = ops;
580 return 0;
581}
582
583static inline bool platform_pci_power_manageable(struct pci_dev *dev)
584{
585 return pci_platform_pm ? pci_platform_pm->is_manageable(dev) : false;
586}
587
588static inline int platform_pci_set_power_state(struct pci_dev *dev,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -0400589 pci_power_t t)
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200590{
591 return pci_platform_pm ? pci_platform_pm->set_state(dev, t) : -ENOSYS;
592}
593
Lukas Wunnercc7cc022016-09-18 05:39:20 +0200594static inline pci_power_t platform_pci_get_power_state(struct pci_dev *dev)
595{
596 return pci_platform_pm ? pci_platform_pm->get_state(dev) : PCI_UNKNOWN;
597}
598
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200599static inline pci_power_t platform_pci_choose_state(struct pci_dev *dev)
600{
601 return pci_platform_pm ?
602 pci_platform_pm->choose_state(dev) : PCI_POWER_ERROR;
603}
Randy Dunlap8f7020d2005-10-23 11:57:38 -0700604
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +0200605static inline int platform_pci_sleep_wake(struct pci_dev *dev, bool enable)
606{
607 return pci_platform_pm ?
608 pci_platform_pm->sleep_wake(dev, enable) : -ENODEV;
609}
610
Rafael J. Wysockib67ea762010-02-17 23:44:09 +0100611static inline int platform_pci_run_wake(struct pci_dev *dev, bool enable)
612{
613 return pci_platform_pm ?
614 pci_platform_pm->run_wake(dev, enable) : -ENODEV;
615}
616
Rafael J. Wysockibac2a902015-01-21 02:17:42 +0100617static inline bool platform_pci_need_resume(struct pci_dev *dev)
618{
619 return pci_platform_pm ? pci_platform_pm->need_resume(dev) : false;
620}
621
John W. Linville064b53db2005-07-27 10:19:44 -0400622/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200623 * pci_raw_set_power_state - Use PCI PM registers to set the power state of
624 * given PCI device
625 * @dev: PCI device to handle.
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200626 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700627 *
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200628 * RETURN VALUE:
629 * -EINVAL if the requested state is invalid.
630 * -EIO if device does not support PCI PM or its PM capabilities register has a
631 * wrong version, or device doesn't support the requested state.
632 * 0 if device already is in the requested state.
633 * 0 if device's power state has been successfully changed.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700634 */
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100635static int pci_raw_set_power_state(struct pci_dev *dev, pci_power_t state)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700636{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200637 u16 pmcsr;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200638 bool need_restore = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700639
Rafael J. Wysocki4a865902009-03-16 22:40:36 +0100640 /* Check if we're already there */
641 if (dev->current_state == state)
642 return 0;
643
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200644 if (!dev->pm_cap)
Andrew Lunncca03de2007-07-09 11:55:58 -0700645 return -EIO;
646
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200647 if (state < PCI_D0 || state > PCI_D3hot)
648 return -EINVAL;
649
Linus Torvalds1da177e2005-04-16 15:20:36 -0700650 /* Validate current state:
Bjorn Helgaasf7625982013-11-14 11:28:18 -0700651 * Can enter D0 from any state, but if we can only go deeper
Linus Torvalds1da177e2005-04-16 15:20:36 -0700652 * to sleep if we're already in a low power state
653 */
Rafael J. Wysocki4a865902009-03-16 22:40:36 +0100654 if (state != PCI_D0 && dev->current_state <= PCI_D3cold
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200655 && dev->current_state > state) {
Ryan Desfosses227f0642014-04-18 20:13:50 -0400656 dev_err(&dev->dev, "invalid power transition (from state %d to %d)\n",
657 dev->current_state, state);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700658 return -EINVAL;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200659 }
Linus Torvalds1da177e2005-04-16 15:20:36 -0700660
Linus Torvalds1da177e2005-04-16 15:20:36 -0700661 /* check if this device supports the desired state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200662 if ((state == PCI_D1 && !dev->d1_support)
663 || (state == PCI_D2 && !dev->d2_support))
Daniel Ritz3fe9d192005-08-17 15:32:19 -0700664 return -EIO;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700665
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200666 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
John W. Linville064b53db2005-07-27 10:19:44 -0400667
John W. Linville32a36582005-09-14 09:52:42 -0400668 /* If we're (effectively) in D3, force entire word to 0.
Linus Torvalds1da177e2005-04-16 15:20:36 -0700669 * This doesn't affect PME_Status, disables PME_En, and
670 * sets PowerState to 0.
671 */
John W. Linville32a36582005-09-14 09:52:42 -0400672 switch (dev->current_state) {
John W. Linvilled3535fb2005-09-28 17:50:51 -0400673 case PCI_D0:
674 case PCI_D1:
675 case PCI_D2:
676 pmcsr &= ~PCI_PM_CTRL_STATE_MASK;
677 pmcsr |= state;
678 break;
Rafael J. Wysockif62795f2009-05-18 22:51:12 +0200679 case PCI_D3hot:
680 case PCI_D3cold:
John W. Linville32a36582005-09-14 09:52:42 -0400681 case PCI_UNKNOWN: /* Boot-up */
682 if ((pmcsr & PCI_PM_CTRL_STATE_MASK) == PCI_D3hot
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100683 && !(pmcsr & PCI_PM_CTRL_NO_SOFT_RESET))
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200684 need_restore = true;
John W. Linville32a36582005-09-14 09:52:42 -0400685 /* Fall-through: force to D0 */
John W. Linville32a36582005-09-14 09:52:42 -0400686 default:
John W. Linvilled3535fb2005-09-28 17:50:51 -0400687 pmcsr = 0;
John W. Linville32a36582005-09-14 09:52:42 -0400688 break;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700689 }
690
691 /* enter specified state */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200692 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700693
694 /* Mandatory power management transition delays */
695 /* see PCI PM 1.1 5.6.1 table 18 */
696 if (state == PCI_D3hot || dev->current_state == PCI_D3hot)
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +0100697 pci_dev_d3_sleep(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700698 else if (state == PCI_D2 || dev->current_state == PCI_D2)
Rafael J. Wysockiaa8c6c92009-01-16 21:54:43 +0100699 udelay(PCI_PM_D2_DELAY);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700700
Rafael J. Wysockie13cdbd2009-10-05 00:48:40 +0200701 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
702 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
703 if (dev->current_state != state && printk_ratelimit())
Ryan Desfosses227f0642014-04-18 20:13:50 -0400704 dev_info(&dev->dev, "Refused to change power state, currently in D%d\n",
705 dev->current_state);
John W. Linville064b53db2005-07-27 10:19:44 -0400706
Huang Ying448bd852012-06-23 10:23:51 +0800707 /*
708 * According to section 5.4.1 of the "PCI BUS POWER MANAGEMENT
John W. Linville064b53db2005-07-27 10:19:44 -0400709 * INTERFACE SPECIFICATION, REV. 1.2", a device transitioning
710 * from D3hot to D0 _may_ perform an internal reset, thereby
711 * going to "D0 Uninitialized" rather than "D0 Initialized".
712 * For example, at least some versions of the 3c905B and the
713 * 3c556B exhibit this behaviour.
714 *
715 * At least some laptop BIOSen (e.g. the Thinkpad T21) leave
716 * devices in a D3hot state at boot. Consequently, we need to
717 * restore at least the BARs so that the device will be
718 * accessible to its driver.
719 */
720 if (need_restore)
721 pci_restore_bars(dev);
722
Rafael J. Wysockif00a20e2009-03-16 22:40:08 +0100723 if (dev->bus->self)
Shaohua Li7d715a62008-02-25 09:46:41 +0800724 pcie_aspm_pm_state_change(dev->bus->self);
725
Linus Torvalds1da177e2005-04-16 15:20:36 -0700726 return 0;
727}
728
729/**
Lukas Wunnera6a64022016-09-18 05:39:20 +0200730 * pci_update_current_state - Read power state of given device and cache it
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200731 * @dev: PCI device to handle.
Rafael J. Wysockif06fc0b2008-12-27 16:30:52 +0100732 * @state: State to cache in case the device doesn't have the PM capability
Lukas Wunnera6a64022016-09-18 05:39:20 +0200733 *
734 * The power state is read from the PMCSR register, which however is
735 * inaccessible in D3cold. The platform firmware is therefore queried first
736 * to detect accessibility of the register. In case the platform firmware
737 * reports an incorrect state or the device isn't power manageable by the
738 * platform at all, we try to detect D3cold by testing accessibility of the
739 * vendor ID in config space.
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200740 */
Rafael J. Wysocki734104292009-01-07 13:07:15 +0100741void pci_update_current_state(struct pci_dev *dev, pci_power_t state)
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200742{
Lukas Wunnera6a64022016-09-18 05:39:20 +0200743 if (platform_pci_get_power_state(dev) == PCI_D3cold ||
744 !pci_device_is_present(dev)) {
745 dev->current_state = PCI_D3cold;
746 } else if (dev->pm_cap) {
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200747 u16 pmcsr;
748
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200749 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200750 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
Rafael J. Wysockif06fc0b2008-12-27 16:30:52 +0100751 } else {
752 dev->current_state = state;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200753 }
754}
755
756/**
Rafael J. Wysockidb288c92012-07-05 15:20:00 -0600757 * pci_power_up - Put the given device into D0 forcibly
758 * @dev: PCI device to power up
759 */
760void pci_power_up(struct pci_dev *dev)
761{
762 if (platform_pci_power_manageable(dev))
763 platform_pci_set_power_state(dev, PCI_D0);
764
765 pci_raw_set_power_state(dev, PCI_D0);
766 pci_update_current_state(dev, PCI_D0);
767}
768
769/**
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100770 * pci_platform_power_transition - Use platform to change device power state
771 * @dev: PCI device to handle.
772 * @state: State to put the device into.
773 */
774static int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state)
775{
776 int error;
777
778 if (platform_pci_power_manageable(dev)) {
779 error = platform_pci_set_power_state(dev, state);
780 if (!error)
781 pci_update_current_state(dev, state);
Rafael J. Wysocki769ba722013-04-12 13:58:17 +0000782 } else
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100783 error = -ENODEV;
Rafael J. Wysocki769ba722013-04-12 13:58:17 +0000784
785 if (error && !dev->pm_cap) /* Fall back to PCI_D0 */
786 dev->current_state = PCI_D0;
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100787
788 return error;
789}
790
791/**
Stephen Hemminger0b950f02014-01-10 17:14:48 -0700792 * pci_wakeup - Wake up a PCI device
793 * @pci_dev: Device to handle.
794 * @ign: ignored parameter
795 */
796static int pci_wakeup(struct pci_dev *pci_dev, void *ign)
797{
798 pci_wakeup_event(pci_dev);
799 pm_request_resume(&pci_dev->dev);
800 return 0;
801}
802
803/**
804 * pci_wakeup_bus - Walk given bus and wake up devices on it
805 * @bus: Top bus of the subtree to walk.
806 */
807static void pci_wakeup_bus(struct pci_bus *bus)
808{
809 if (bus)
810 pci_walk_bus(bus, pci_wakeup, NULL);
811}
812
813/**
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100814 * __pci_start_power_transition - Start power transition of a PCI device
815 * @dev: PCI device to handle.
816 * @state: State to put the device into.
817 */
818static void __pci_start_power_transition(struct pci_dev *dev, pci_power_t state)
819{
Huang Ying448bd852012-06-23 10:23:51 +0800820 if (state == PCI_D0) {
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100821 pci_platform_power_transition(dev, PCI_D0);
Huang Ying448bd852012-06-23 10:23:51 +0800822 /*
823 * Mandatory power management transition delays, see
824 * PCI Express Base Specification Revision 2.0 Section
825 * 6.6.1: Conventional Reset. Do not delay for
826 * devices powered on/off by corresponding bridge,
827 * because have already delayed for the bridge.
828 */
829 if (dev->runtime_d3cold) {
830 msleep(dev->d3cold_delay);
831 /*
832 * When powering on a bridge from D3cold, the
833 * whole hierarchy may be powered on into
834 * D0uninitialized state, resume them to give
835 * them a chance to suspend again
836 */
837 pci_wakeup_bus(dev->subordinate);
838 }
839 }
840}
841
842/**
843 * __pci_dev_set_current_state - Set current state of a PCI device
844 * @dev: Device to handle
845 * @data: pointer to state to be set
846 */
847static int __pci_dev_set_current_state(struct pci_dev *dev, void *data)
848{
849 pci_power_t state = *(pci_power_t *)data;
850
851 dev->current_state = state;
852 return 0;
853}
854
855/**
856 * __pci_bus_set_current_state - Walk given bus and set current state of devices
857 * @bus: Top bus of the subtree to walk.
858 * @state: state to be set
859 */
860static void __pci_bus_set_current_state(struct pci_bus *bus, pci_power_t state)
861{
862 if (bus)
863 pci_walk_bus(bus, __pci_dev_set_current_state, &state);
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100864}
865
866/**
867 * __pci_complete_power_transition - Complete power transition of a PCI device
868 * @dev: PCI device to handle.
869 * @state: State to put the device into.
870 *
871 * This function should not be called directly by device drivers.
872 */
873int __pci_complete_power_transition(struct pci_dev *dev, pci_power_t state)
874{
Huang Ying448bd852012-06-23 10:23:51 +0800875 int ret;
876
Rafael J. Wysockidb288c92012-07-05 15:20:00 -0600877 if (state <= PCI_D0)
Huang Ying448bd852012-06-23 10:23:51 +0800878 return -EINVAL;
879 ret = pci_platform_power_transition(dev, state);
880 /* Power off the bridge may power off the whole hierarchy */
881 if (!ret && state == PCI_D3cold)
882 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold);
883 return ret;
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100884}
885EXPORT_SYMBOL_GPL(__pci_complete_power_transition);
886
887/**
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200888 * pci_set_power_state - Set the power state of a PCI device
889 * @dev: PCI device to handle.
890 * @state: PCI power state (D0, D1, D2, D3hot) to put the device into.
891 *
Nick Andrew877d0312009-01-26 11:06:57 +0100892 * Transition a device to a new power state, using the platform firmware and/or
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200893 * the device's PCI PM registers.
894 *
895 * RETURN VALUE:
896 * -EINVAL if the requested state is invalid.
897 * -EIO if device does not support PCI PM or its PM capabilities register has a
898 * wrong version, or device doesn't support the requested state.
899 * 0 if device already is in the requested state.
900 * 0 if device's power state has been successfully changed.
901 */
902int pci_set_power_state(struct pci_dev *dev, pci_power_t state)
903{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +0200904 int error;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200905
906 /* bound the state we're entering */
Huang Ying448bd852012-06-23 10:23:51 +0800907 if (state > PCI_D3cold)
908 state = PCI_D3cold;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200909 else if (state < PCI_D0)
910 state = PCI_D0;
911 else if ((state == PCI_D1 || state == PCI_D2) && pci_no_d1d2(dev))
912 /*
913 * If the device or the parent bridge do not support PCI PM,
914 * ignore the request if we're doing anything other than putting
915 * it into D0 (which would only happen on boot).
916 */
917 return 0;
918
Rafael J. Wysockidb288c92012-07-05 15:20:00 -0600919 /* Check if we're already there */
920 if (dev->current_state == state)
921 return 0;
922
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100923 __pci_start_power_transition(dev, state);
924
Alan Cox979b1792008-07-24 17:18:38 +0100925 /* This device is quirked not to be put into D3, so
926 don't put it in D3 */
Huang Ying448bd852012-06-23 10:23:51 +0800927 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3))
Alan Cox979b1792008-07-24 17:18:38 +0100928 return 0;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200929
Huang Ying448bd852012-06-23 10:23:51 +0800930 /*
931 * To put device in D3cold, we put device into D3hot in native
932 * way, then put device into D3cold with platform ops
933 */
934 error = pci_raw_set_power_state(dev, state > PCI_D3hot ?
935 PCI_D3hot : state);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200936
Rafael J. Wysocki0e5dd462009-03-26 22:51:40 +0100937 if (!__pci_complete_power_transition(dev, state))
938 error = 0;
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200939
940 return error;
941}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -0600942EXPORT_SYMBOL(pci_set_power_state);
Rafael J. Wysocki44e4e662008-07-07 03:32:52 +0200943
944/**
Linus Torvalds1da177e2005-04-16 15:20:36 -0700945 * pci_choose_state - Choose the power state of a PCI device
946 * @dev: PCI device to be suspended
947 * @state: target sleep state for the whole system. This is the value
948 * that is passed to suspend() function.
949 *
950 * Returns PCI power state suitable for given device and given system
951 * message.
952 */
953
954pci_power_t pci_choose_state(struct pci_dev *dev, pm_message_t state)
955{
Shaohua Liab826ca2007-07-20 10:03:22 +0800956 pci_power_t ret;
David Shaohua Li0f644742005-03-19 00:15:48 -0500957
Yijing Wang728cdb72013-06-18 16:22:14 +0800958 if (!dev->pm_cap)
Linus Torvalds1da177e2005-04-16 15:20:36 -0700959 return PCI_D0;
960
Rafael J. Wysocki961d9122008-07-07 03:32:02 +0200961 ret = platform_pci_choose_state(dev);
962 if (ret != PCI_POWER_ERROR)
963 return ret;
Pavel Machekca078ba2005-09-03 15:56:57 -0700964
965 switch (state.event) {
966 case PM_EVENT_ON:
967 return PCI_D0;
968 case PM_EVENT_FREEZE:
David Brownellb887d2e2006-08-14 23:11:05 -0700969 case PM_EVENT_PRETHAW:
970 /* REVISIT both freeze and pre-thaw "should" use D0 */
Pavel Machekca078ba2005-09-03 15:56:57 -0700971 case PM_EVENT_SUSPEND:
Rafael J. Wysocki3a2d5b72008-02-23 19:13:25 +0100972 case PM_EVENT_HIBERNATE:
Pavel Machekca078ba2005-09-03 15:56:57 -0700973 return PCI_D3hot;
Linus Torvalds1da177e2005-04-16 15:20:36 -0700974 default:
Bjorn Helgaas80ccba12008-06-13 10:52:11 -0600975 dev_info(&dev->dev, "unrecognized suspend event %d\n",
976 state.event);
Linus Torvalds1da177e2005-04-16 15:20:36 -0700977 BUG();
978 }
979 return PCI_D0;
980}
Linus Torvalds1da177e2005-04-16 15:20:36 -0700981EXPORT_SYMBOL(pci_choose_state);
982
Yu Zhao89858512009-02-16 02:55:47 +0800983#define PCI_EXP_SAVE_REGS 7
984
Alex Williamsonfd0f7f72013-12-17 16:43:45 -0700985static struct pci_cap_saved_state *_pci_find_saved_cap(struct pci_dev *pci_dev,
986 u16 cap, bool extended)
Yinghai Lu34a48762012-02-11 00:18:41 -0800987{
988 struct pci_cap_saved_state *tmp;
Yinghai Lu34a48762012-02-11 00:18:41 -0800989
Sasha Levinb67bfe02013-02-27 17:06:00 -0800990 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) {
Alex Williamsonfd0f7f72013-12-17 16:43:45 -0700991 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap)
Yinghai Lu34a48762012-02-11 00:18:41 -0800992 return tmp;
993 }
994 return NULL;
995}
996
Alex Williamsonfd0f7f72013-12-17 16:43:45 -0700997struct pci_cap_saved_state *pci_find_saved_cap(struct pci_dev *dev, char cap)
998{
999 return _pci_find_saved_cap(dev, cap, false);
1000}
1001
1002struct pci_cap_saved_state *pci_find_saved_ext_cap(struct pci_dev *dev, u16 cap)
1003{
1004 return _pci_find_saved_cap(dev, cap, true);
1005}
1006
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001007static int pci_save_pcie_state(struct pci_dev *dev)
1008{
Jiang Liu59875ae2012-07-24 17:20:06 +08001009 int i = 0;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001010 struct pci_cap_saved_state *save_state;
1011 u16 *cap;
1012
Jiang Liu59875ae2012-07-24 17:20:06 +08001013 if (!pci_is_pcie(dev))
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001014 return 0;
1015
Eric W. Biederman9f355752007-03-08 13:06:13 -07001016 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001017 if (!save_state) {
Harvey Harrisone496b612009-01-07 16:22:37 -08001018 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001019 return -ENOMEM;
1020 }
Jiang Liu59875ae2012-07-24 17:20:06 +08001021
Alex Williamson24a4742f2011-05-10 10:02:11 -06001022 cap = (u16 *)&save_state->cap.data[0];
Jiang Liu59875ae2012-07-24 17:20:06 +08001023 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &cap[i++]);
1024 pcie_capability_read_word(dev, PCI_EXP_LNKCTL, &cap[i++]);
1025 pcie_capability_read_word(dev, PCI_EXP_SLTCTL, &cap[i++]);
1026 pcie_capability_read_word(dev, PCI_EXP_RTCTL, &cap[i++]);
1027 pcie_capability_read_word(dev, PCI_EXP_DEVCTL2, &cap[i++]);
1028 pcie_capability_read_word(dev, PCI_EXP_LNKCTL2, &cap[i++]);
1029 pcie_capability_read_word(dev, PCI_EXP_SLTCTL2, &cap[i++]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001030
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001031 return 0;
1032}
1033
1034static void pci_restore_pcie_state(struct pci_dev *dev)
1035{
Jiang Liu59875ae2012-07-24 17:20:06 +08001036 int i = 0;
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001037 struct pci_cap_saved_state *save_state;
1038 u16 *cap;
1039
1040 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_EXP);
Jiang Liu59875ae2012-07-24 17:20:06 +08001041 if (!save_state)
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001042 return;
Jiang Liu59875ae2012-07-24 17:20:06 +08001043
Alex Williamson24a4742f2011-05-10 10:02:11 -06001044 cap = (u16 *)&save_state->cap.data[0];
Jiang Liu59875ae2012-07-24 17:20:06 +08001045 pcie_capability_write_word(dev, PCI_EXP_DEVCTL, cap[i++]);
1046 pcie_capability_write_word(dev, PCI_EXP_LNKCTL, cap[i++]);
1047 pcie_capability_write_word(dev, PCI_EXP_SLTCTL, cap[i++]);
1048 pcie_capability_write_word(dev, PCI_EXP_RTCTL, cap[i++]);
1049 pcie_capability_write_word(dev, PCI_EXP_DEVCTL2, cap[i++]);
1050 pcie_capability_write_word(dev, PCI_EXP_LNKCTL2, cap[i++]);
1051 pcie_capability_write_word(dev, PCI_EXP_SLTCTL2, cap[i++]);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001052}
1053
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001054
1055static int pci_save_pcix_state(struct pci_dev *dev)
1056{
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001057 int pos;
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001058 struct pci_cap_saved_state *save_state;
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001059
1060 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
Wei Yang0a1a9b42015-06-30 09:16:44 +08001061 if (!pos)
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001062 return 0;
1063
Shaohua Lif34303d2007-12-18 09:56:47 +08001064 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001065 if (!save_state) {
Harvey Harrisone496b612009-01-07 16:22:37 -08001066 dev_err(&dev->dev, "buffer not found in %s\n", __func__);
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001067 return -ENOMEM;
1068 }
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001069
Alex Williamson24a4742f2011-05-10 10:02:11 -06001070 pci_read_config_word(dev, pos + PCI_X_CMD,
1071 (u16 *)save_state->cap.data);
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01001072
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001073 return 0;
1074}
1075
1076static void pci_restore_pcix_state(struct pci_dev *dev)
1077{
1078 int i = 0, pos;
1079 struct pci_cap_saved_state *save_state;
1080 u16 *cap;
1081
1082 save_state = pci_find_saved_cap(dev, PCI_CAP_ID_PCIX);
1083 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
Wei Yang0a1a9b42015-06-30 09:16:44 +08001084 if (!save_state || !pos)
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001085 return;
Alex Williamson24a4742f2011-05-10 10:02:11 -06001086 cap = (u16 *)&save_state->cap.data[0];
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001087
1088 pci_write_config_word(dev, pos + PCI_X_CMD, cap[i++]);
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001089}
1090
1091
Linus Torvalds1da177e2005-04-16 15:20:36 -07001092/**
1093 * pci_save_state - save the PCI configuration space of a device before suspending
1094 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -07001095 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001096int pci_save_state(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001097{
1098 int i;
1099 /* XXX: 100% dword access ok here? */
1100 for (i = 0; i < 16; i++)
Kleber Sacilotto de Souza9e0b5b22009-11-25 00:55:51 -02001101 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]);
Rafael J. Wysockiaa8c6c92009-01-16 21:54:43 +01001102 dev->state_saved = true;
Quentin Lambert79e50e72014-09-07 20:03:32 +02001103
1104 i = pci_save_pcie_state(dev);
1105 if (i != 0)
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001106 return i;
Quentin Lambert79e50e72014-09-07 20:03:32 +02001107
1108 i = pci_save_pcix_state(dev);
1109 if (i != 0)
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001110 return i;
Quentin Lambert79e50e72014-09-07 20:03:32 +02001111
Quentin Lambert754834b2014-11-06 17:45:55 +01001112 return pci_save_vc_state(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001113}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001114EXPORT_SYMBOL(pci_save_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001115
Rafael J. Wysockiebfc5b82012-04-15 21:40:40 +02001116static void pci_restore_config_dword(struct pci_dev *pdev, int offset,
1117 u32 saved_val, int retry)
1118{
1119 u32 val;
1120
1121 pci_read_config_dword(pdev, offset, &val);
1122 if (val == saved_val)
1123 return;
1124
1125 for (;;) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04001126 dev_dbg(&pdev->dev, "restoring config space at offset %#x (was %#x, writing %#x)\n",
1127 offset, val, saved_val);
Rafael J. Wysockiebfc5b82012-04-15 21:40:40 +02001128 pci_write_config_dword(pdev, offset, saved_val);
1129 if (retry-- <= 0)
1130 return;
1131
1132 pci_read_config_dword(pdev, offset, &val);
1133 if (val == saved_val)
1134 return;
1135
1136 mdelay(1);
1137 }
1138}
1139
Rafael J. Wysockia6cb9ee2012-04-16 23:07:50 +02001140static void pci_restore_config_space_range(struct pci_dev *pdev,
1141 int start, int end, int retry)
Rafael J. Wysockiebfc5b82012-04-15 21:40:40 +02001142{
1143 int index;
1144
1145 for (index = end; index >= start; index--)
1146 pci_restore_config_dword(pdev, 4 * index,
1147 pdev->saved_config_space[index],
1148 retry);
1149}
1150
Rafael J. Wysockia6cb9ee2012-04-16 23:07:50 +02001151static void pci_restore_config_space(struct pci_dev *pdev)
1152{
1153 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) {
1154 pci_restore_config_space_range(pdev, 10, 15, 0);
1155 /* Restore BARs before the command register. */
1156 pci_restore_config_space_range(pdev, 4, 9, 10);
1157 pci_restore_config_space_range(pdev, 0, 3, 0);
1158 } else {
1159 pci_restore_config_space_range(pdev, 0, 15, 0);
1160 }
1161}
1162
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001163/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001164 * pci_restore_state - Restore the saved state of a PCI device
1165 * @dev: - PCI device that we're dealing with
Linus Torvalds1da177e2005-04-16 15:20:36 -07001166 */
Jon Mason1d3c16a2010-11-30 17:43:26 -06001167void pci_restore_state(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001168{
Alek Duc82f63e2009-08-08 08:46:19 +08001169 if (!dev->state_saved)
Jon Mason1d3c16a2010-11-30 17:43:26 -06001170 return;
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02001171
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001172 /* PCI Express register must be restored first */
1173 pci_restore_pcie_state(dev);
Hao, Xudong1900ca12011-12-17 21:24:40 +08001174 pci_restore_ats_state(dev);
Alex Williamson425c1b22013-12-17 16:43:51 -07001175 pci_restore_vc_state(dev);
Michael S. Tsirkinb56a5a22006-08-21 16:22:22 +03001176
Taku Izumib07461a2015-09-17 10:09:37 -05001177 pci_cleanup_aer_error_status_regs(dev);
1178
Rafael J. Wysockia6cb9ee2012-04-16 23:07:50 +02001179 pci_restore_config_space(dev);
Rafael J. Wysockiebfc5b82012-04-15 21:40:40 +02001180
Stephen Hemmingercc692a52006-11-08 16:17:15 -08001181 pci_restore_pcix_state(dev);
Shaohua Li41017f02006-02-08 17:11:38 +08001182 pci_restore_msi_state(dev);
Alexander Duyckccbc1752015-07-07 12:24:35 -07001183
1184 /* Restore ACS and IOV configuration state */
1185 pci_enable_acs(dev);
Yu Zhao8c5cdb62009-03-20 11:25:12 +08001186 pci_restore_iov_state(dev);
Michael Ellerman8fed4b62007-01-25 19:34:08 +11001187
Rafael J. Wysocki4b77b0a2009-09-09 23:49:59 +02001188 dev->state_saved = false;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001189}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001190EXPORT_SYMBOL(pci_restore_state);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001191
Alex Williamsonffbdd3f2011-05-10 10:02:27 -06001192struct pci_saved_state {
1193 u32 config_space[16];
1194 struct pci_cap_saved_data cap[0];
1195};
1196
1197/**
1198 * pci_store_saved_state - Allocate and return an opaque struct containing
1199 * the device saved state.
1200 * @dev: PCI device that we're dealing with
1201 *
Bjorn Helgaasf7625982013-11-14 11:28:18 -07001202 * Return NULL if no state or error.
Alex Williamsonffbdd3f2011-05-10 10:02:27 -06001203 */
1204struct pci_saved_state *pci_store_saved_state(struct pci_dev *dev)
1205{
1206 struct pci_saved_state *state;
1207 struct pci_cap_saved_state *tmp;
1208 struct pci_cap_saved_data *cap;
Alex Williamsonffbdd3f2011-05-10 10:02:27 -06001209 size_t size;
1210
1211 if (!dev->state_saved)
1212 return NULL;
1213
1214 size = sizeof(*state) + sizeof(struct pci_cap_saved_data);
1215
Sasha Levinb67bfe02013-02-27 17:06:00 -08001216 hlist_for_each_entry(tmp, &dev->saved_cap_space, next)
Alex Williamsonffbdd3f2011-05-10 10:02:27 -06001217 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1218
1219 state = kzalloc(size, GFP_KERNEL);
1220 if (!state)
1221 return NULL;
1222
1223 memcpy(state->config_space, dev->saved_config_space,
1224 sizeof(state->config_space));
1225
1226 cap = state->cap;
Sasha Levinb67bfe02013-02-27 17:06:00 -08001227 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) {
Alex Williamsonffbdd3f2011-05-10 10:02:27 -06001228 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size;
1229 memcpy(cap, &tmp->cap, len);
1230 cap = (struct pci_cap_saved_data *)((u8 *)cap + len);
1231 }
1232 /* Empty cap_save terminates list */
1233
1234 return state;
1235}
1236EXPORT_SYMBOL_GPL(pci_store_saved_state);
1237
1238/**
1239 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1240 * @dev: PCI device that we're dealing with
1241 * @state: Saved state returned from pci_store_saved_state()
1242 */
Konrad Rzeszutek Wilk98d9b272014-12-03 16:40:31 -05001243int pci_load_saved_state(struct pci_dev *dev,
1244 struct pci_saved_state *state)
Alex Williamsonffbdd3f2011-05-10 10:02:27 -06001245{
1246 struct pci_cap_saved_data *cap;
1247
1248 dev->state_saved = false;
1249
1250 if (!state)
1251 return 0;
1252
1253 memcpy(dev->saved_config_space, state->config_space,
1254 sizeof(state->config_space));
1255
1256 cap = state->cap;
1257 while (cap->size) {
1258 struct pci_cap_saved_state *tmp;
1259
Alex Williamsonfd0f7f72013-12-17 16:43:45 -07001260 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended);
Alex Williamsonffbdd3f2011-05-10 10:02:27 -06001261 if (!tmp || tmp->cap.size != cap->size)
1262 return -EINVAL;
1263
1264 memcpy(tmp->cap.data, cap->data, tmp->cap.size);
1265 cap = (struct pci_cap_saved_data *)((u8 *)cap +
1266 sizeof(struct pci_cap_saved_data) + cap->size);
1267 }
1268
1269 dev->state_saved = true;
1270 return 0;
1271}
Konrad Rzeszutek Wilk98d9b272014-12-03 16:40:31 -05001272EXPORT_SYMBOL_GPL(pci_load_saved_state);
Alex Williamsonffbdd3f2011-05-10 10:02:27 -06001273
1274/**
1275 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
1276 * and free the memory allocated for it.
1277 * @dev: PCI device that we're dealing with
1278 * @state: Pointer to saved state returned from pci_store_saved_state()
1279 */
1280int pci_load_and_free_saved_state(struct pci_dev *dev,
1281 struct pci_saved_state **state)
1282{
1283 int ret = pci_load_saved_state(dev, *state);
1284 kfree(*state);
1285 *state = NULL;
1286 return ret;
1287}
1288EXPORT_SYMBOL_GPL(pci_load_and_free_saved_state);
1289
Bjorn Helgaas8a9d5602014-02-26 11:26:00 -07001290int __weak pcibios_enable_device(struct pci_dev *dev, int bars)
1291{
1292 return pci_enable_resources(dev, bars);
1293}
1294
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001295static int do_pci_enable_device(struct pci_dev *dev, int bars)
1296{
1297 int err;
Vidya Sagar1f6ae472014-07-16 15:33:42 +05301298 struct pci_dev *bridge;
Bjorn Helgaas1e2571a2014-01-29 16:13:51 -07001299 u16 cmd;
1300 u8 pin;
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001301
1302 err = pci_set_power_state(dev, PCI_D0);
1303 if (err < 0 && err != -EIO)
1304 return err;
Vidya Sagar1f6ae472014-07-16 15:33:42 +05301305
1306 bridge = pci_upstream_bridge(dev);
1307 if (bridge)
1308 pcie_aspm_powersave_config_link(bridge);
1309
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001310 err = pcibios_enable_device(dev, bars);
1311 if (err < 0)
1312 return err;
1313 pci_fixup_device(pci_fixup_enable, dev);
1314
Bjorn Helgaas866d5412014-03-07 16:06:05 -07001315 if (dev->msi_enabled || dev->msix_enabled)
1316 return 0;
1317
Bjorn Helgaas1e2571a2014-01-29 16:13:51 -07001318 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
1319 if (pin) {
1320 pci_read_config_word(dev, PCI_COMMAND, &cmd);
1321 if (cmd & PCI_COMMAND_INTX_DISABLE)
1322 pci_write_config_word(dev, PCI_COMMAND,
1323 cmd & ~PCI_COMMAND_INTX_DISABLE);
1324 }
1325
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001326 return 0;
1327}
1328
1329/**
Tejun Heo0b62e132007-07-27 14:43:35 +09001330 * pci_reenable_device - Resume abandoned device
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001331 * @dev: PCI device to be resumed
1332 *
1333 * Note this function is a backend of pci_default_resume and is not supposed
1334 * to be called by normal code, write proper resume handler and use it instead.
1335 */
Tejun Heo0b62e132007-07-27 14:43:35 +09001336int pci_reenable_device(struct pci_dev *dev)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001337{
Yuji Shimada296ccb02009-04-03 16:41:46 +09001338 if (pci_is_enabled(dev))
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001339 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1);
1340 return 0;
1341}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001342EXPORT_SYMBOL(pci_reenable_device);
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001343
Yinghai Lu928bea92013-07-22 14:37:17 -07001344static void pci_enable_bridge(struct pci_dev *dev)
1345{
Bjorn Helgaas79272132013-11-06 10:00:51 -07001346 struct pci_dev *bridge;
Yinghai Lu928bea92013-07-22 14:37:17 -07001347 int retval;
1348
Bjorn Helgaas79272132013-11-06 10:00:51 -07001349 bridge = pci_upstream_bridge(dev);
1350 if (bridge)
1351 pci_enable_bridge(bridge);
Yinghai Lu928bea92013-07-22 14:37:17 -07001352
Yinghai Lucf3e1fe2013-11-05 13:34:38 -07001353 if (pci_is_enabled(dev)) {
Bjorn Helgaasfbeeb822013-11-05 13:34:51 -07001354 if (!dev->is_busmaster)
Yinghai Lucf3e1fe2013-11-05 13:34:38 -07001355 pci_set_master(dev);
Yinghai Lu928bea92013-07-22 14:37:17 -07001356 return;
Yinghai Lucf3e1fe2013-11-05 13:34:38 -07001357 }
1358
Yinghai Lu928bea92013-07-22 14:37:17 -07001359 retval = pci_enable_device(dev);
1360 if (retval)
1361 dev_err(&dev->dev, "Error enabling bridge (%d), continuing\n",
1362 retval);
1363 pci_set_master(dev);
1364}
1365
Bjorn Helgaasb4b4fbb2013-01-04 12:12:55 -07001366static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001367{
Bjorn Helgaas79272132013-11-06 10:00:51 -07001368 struct pci_dev *bridge;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001369 int err;
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001370 int i, bars = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001371
Jesse Barnes97c145f2010-11-05 15:16:36 -04001372 /*
1373 * Power state could be unknown at this point, either due to a fresh
1374 * boot or a device removal call. So get the current power state
1375 * so that things like MSI message writing will behave as expected
1376 * (e.g. if the device really is in D0 at enable time).
1377 */
1378 if (dev->pm_cap) {
1379 u16 pmcsr;
1380 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
1381 dev->current_state = (pmcsr & PCI_PM_CTRL_STATE_MASK);
1382 }
1383
Bjorn Helgaascc7ba392013-02-11 16:47:01 -07001384 if (atomic_inc_return(&dev->enable_cnt) > 1)
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +09001385 return 0; /* already enabled */
1386
Bjorn Helgaas79272132013-11-06 10:00:51 -07001387 bridge = pci_upstream_bridge(dev);
1388 if (bridge)
1389 pci_enable_bridge(bridge);
Yinghai Lu928bea92013-07-22 14:37:17 -07001390
Yinghai Lu497f16f2011-12-17 18:33:37 -08001391 /* only skip sriov related */
1392 for (i = 0; i <= PCI_ROM_RESOURCE; i++)
1393 if (dev->resource[i].flags & flags)
1394 bars |= (1 << i);
1395 for (i = PCI_BRIDGE_RESOURCES; i < DEVICE_COUNT_RESOURCE; i++)
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001396 if (dev->resource[i].flags & flags)
1397 bars |= (1 << i);
1398
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001399 err = do_pci_enable_device(dev, bars);
Greg Kroah-Hartman95a62962005-07-28 11:37:33 -07001400 if (err < 0)
Hidetoshi Seto38cc1302006-12-18 10:30:00 +09001401 atomic_dec(&dev->enable_cnt);
Hidetoshi Seto9fb625c2006-12-18 10:28:43 +09001402 return err;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001403}
1404
1405/**
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001406 * pci_enable_device_io - Initialize a device for use with IO space
1407 * @dev: PCI device to be initialized
1408 *
1409 * Initialize device before it's used by a driver. Ask low-level code
1410 * to enable I/O resources. Wake up the device if it was suspended.
1411 * Beware, this function can fail.
1412 */
1413int pci_enable_device_io(struct pci_dev *dev)
1414{
Bjorn Helgaasb4b4fbb2013-01-04 12:12:55 -07001415 return pci_enable_device_flags(dev, IORESOURCE_IO);
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001416}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001417EXPORT_SYMBOL(pci_enable_device_io);
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001418
1419/**
1420 * pci_enable_device_mem - Initialize a device for use with Memory space
1421 * @dev: PCI device to be initialized
1422 *
1423 * Initialize device before it's used by a driver. Ask low-level code
1424 * to enable Memory resources. Wake up the device if it was suspended.
1425 * Beware, this function can fail.
1426 */
1427int pci_enable_device_mem(struct pci_dev *dev)
1428{
Bjorn Helgaasb4b4fbb2013-01-04 12:12:55 -07001429 return pci_enable_device_flags(dev, IORESOURCE_MEM);
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001430}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001431EXPORT_SYMBOL(pci_enable_device_mem);
Benjamin Herrenschmidtb7189892007-12-20 15:28:08 +11001432
Linus Torvalds1da177e2005-04-16 15:20:36 -07001433/**
1434 * pci_enable_device - Initialize device before it's used by a driver.
1435 * @dev: PCI device to be initialized
1436 *
1437 * Initialize device before it's used by a driver. Ask low-level code
1438 * to enable I/O and memory. Wake up the device if it was suspended.
1439 * Beware, this function can fail.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001440 *
1441 * Note we don't actually enable the device many times if we call
1442 * this function repeatedly (we just increment the count).
Linus Torvalds1da177e2005-04-16 15:20:36 -07001443 */
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001444int pci_enable_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001445{
Bjorn Helgaasb4b4fbb2013-01-04 12:12:55 -07001446 return pci_enable_device_flags(dev, IORESOURCE_MEM | IORESOURCE_IO);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001447}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001448EXPORT_SYMBOL(pci_enable_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001449
Tejun Heo9ac78492007-01-20 16:00:26 +09001450/*
1451 * Managed PCI resources. This manages device on/off, intx/msi/msix
1452 * on/off and BAR regions. pci_dev itself records msi/msix status, so
1453 * there's no need to track it separately. pci_devres is initialized
1454 * when a device is enabled using managed PCI device enable interface.
1455 */
1456struct pci_devres {
Tejun Heo7f375f32007-02-25 04:36:01 -08001457 unsigned int enabled:1;
1458 unsigned int pinned:1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001459 unsigned int orig_intx:1;
1460 unsigned int restore_intx:1;
1461 u32 region_mask;
1462};
1463
1464static void pcim_release(struct device *gendev, void *res)
1465{
Geliang Tangf3d2f1652016-01-08 12:05:39 -06001466 struct pci_dev *dev = to_pci_dev(gendev);
Tejun Heo9ac78492007-01-20 16:00:26 +09001467 struct pci_devres *this = res;
1468 int i;
1469
1470 if (dev->msi_enabled)
1471 pci_disable_msi(dev);
1472 if (dev->msix_enabled)
1473 pci_disable_msix(dev);
1474
1475 for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
1476 if (this->region_mask & (1 << i))
1477 pci_release_region(dev, i);
1478
1479 if (this->restore_intx)
1480 pci_intx(dev, this->orig_intx);
1481
Tejun Heo7f375f32007-02-25 04:36:01 -08001482 if (this->enabled && !this->pinned)
Tejun Heo9ac78492007-01-20 16:00:26 +09001483 pci_disable_device(dev);
1484}
1485
Ryan Desfosses07656d83082014-04-11 01:01:53 -04001486static struct pci_devres *get_pci_dr(struct pci_dev *pdev)
Tejun Heo9ac78492007-01-20 16:00:26 +09001487{
1488 struct pci_devres *dr, *new_dr;
1489
1490 dr = devres_find(&pdev->dev, pcim_release, NULL, NULL);
1491 if (dr)
1492 return dr;
1493
1494 new_dr = devres_alloc(pcim_release, sizeof(*new_dr), GFP_KERNEL);
1495 if (!new_dr)
1496 return NULL;
1497 return devres_get(&pdev->dev, new_dr, NULL, NULL);
1498}
1499
Ryan Desfosses07656d83082014-04-11 01:01:53 -04001500static struct pci_devres *find_pci_dr(struct pci_dev *pdev)
Tejun Heo9ac78492007-01-20 16:00:26 +09001501{
1502 if (pci_is_managed(pdev))
1503 return devres_find(&pdev->dev, pcim_release, NULL, NULL);
1504 return NULL;
1505}
1506
1507/**
1508 * pcim_enable_device - Managed pci_enable_device()
1509 * @pdev: PCI device to be initialized
1510 *
1511 * Managed pci_enable_device().
1512 */
1513int pcim_enable_device(struct pci_dev *pdev)
1514{
1515 struct pci_devres *dr;
1516 int rc;
1517
1518 dr = get_pci_dr(pdev);
1519 if (unlikely(!dr))
1520 return -ENOMEM;
Tejun Heob95d58e2008-01-30 18:20:04 +09001521 if (dr->enabled)
1522 return 0;
Tejun Heo9ac78492007-01-20 16:00:26 +09001523
1524 rc = pci_enable_device(pdev);
1525 if (!rc) {
1526 pdev->is_managed = 1;
Tejun Heo7f375f32007-02-25 04:36:01 -08001527 dr->enabled = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001528 }
1529 return rc;
1530}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001531EXPORT_SYMBOL(pcim_enable_device);
Tejun Heo9ac78492007-01-20 16:00:26 +09001532
1533/**
1534 * pcim_pin_device - Pin managed PCI device
1535 * @pdev: PCI device to pin
1536 *
1537 * Pin managed PCI device @pdev. Pinned device won't be disabled on
1538 * driver detach. @pdev must have been enabled with
1539 * pcim_enable_device().
1540 */
1541void pcim_pin_device(struct pci_dev *pdev)
1542{
1543 struct pci_devres *dr;
1544
1545 dr = find_pci_dr(pdev);
Tejun Heo7f375f32007-02-25 04:36:01 -08001546 WARN_ON(!dr || !dr->enabled);
Tejun Heo9ac78492007-01-20 16:00:26 +09001547 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -08001548 dr->pinned = 1;
Tejun Heo9ac78492007-01-20 16:00:26 +09001549}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001550EXPORT_SYMBOL(pcim_pin_device);
Tejun Heo9ac78492007-01-20 16:00:26 +09001551
Matthew Garretteca0d462012-12-05 14:33:27 -07001552/*
1553 * pcibios_add_device - provide arch specific hooks when adding device dev
1554 * @dev: the PCI device being added
1555 *
1556 * Permits the platform to provide architecture specific functionality when
1557 * devices are added. This is the default implementation. Architecture
1558 * implementations can override this.
1559 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001560int __weak pcibios_add_device(struct pci_dev *dev)
Matthew Garretteca0d462012-12-05 14:33:27 -07001561{
1562 return 0;
1563}
1564
Linus Torvalds1da177e2005-04-16 15:20:36 -07001565/**
Sebastian Ott6ae32c52013-06-04 19:18:14 +02001566 * pcibios_release_device - provide arch specific hooks when releasing device dev
1567 * @dev: the PCI device being released
1568 *
1569 * Permits the platform to provide architecture specific functionality when
1570 * devices are released. This is the default implementation. Architecture
1571 * implementations can override this.
1572 */
1573void __weak pcibios_release_device(struct pci_dev *dev) {}
1574
1575/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07001576 * pcibios_disable_device - disable arch specific PCI resources for device dev
1577 * @dev: the PCI device to disable
1578 *
1579 * Disables architecture specific PCI resources for the device. This
1580 * is the default implementation. Architecture implementations can
1581 * override this.
1582 */
Bogicevic Sasaff3ce482015-12-27 13:21:11 -08001583void __weak pcibios_disable_device(struct pci_dev *dev) {}
Linus Torvalds1da177e2005-04-16 15:20:36 -07001584
Hanjun Guoa43ae582014-05-06 11:29:52 +08001585/**
1586 * pcibios_penalize_isa_irq - penalize an ISA IRQ
1587 * @irq: ISA IRQ to penalize
1588 * @active: IRQ active or not
1589 *
1590 * Permits the platform to provide architecture-specific functionality when
1591 * penalizing ISA IRQs. This is the default implementation. Architecture
1592 * implementations can override this.
1593 */
1594void __weak pcibios_penalize_isa_irq(int irq, int active) {}
1595
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001596static void do_pci_disable_device(struct pci_dev *dev)
1597{
1598 u16 pci_command;
1599
1600 pci_read_config_word(dev, PCI_COMMAND, &pci_command);
1601 if (pci_command & PCI_COMMAND_MASTER) {
1602 pci_command &= ~PCI_COMMAND_MASTER;
1603 pci_write_config_word(dev, PCI_COMMAND, pci_command);
1604 }
1605
1606 pcibios_disable_device(dev);
1607}
1608
1609/**
1610 * pci_disable_enabled_device - Disable device without updating enable_cnt
1611 * @dev: PCI device to disable
1612 *
1613 * NOTE: This function is a backend of PCI power management routines and is
1614 * not supposed to be called drivers.
1615 */
1616void pci_disable_enabled_device(struct pci_dev *dev)
1617{
Yuji Shimada296ccb02009-04-03 16:41:46 +09001618 if (pci_is_enabled(dev))
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001619 do_pci_disable_device(dev);
1620}
1621
Linus Torvalds1da177e2005-04-16 15:20:36 -07001622/**
1623 * pci_disable_device - Disable PCI device after use
1624 * @dev: PCI device to be disabled
1625 *
1626 * Signal to the system that the PCI device is not in use by the system
1627 * anymore. This only involves disabling PCI bus-mastering, if active.
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001628 *
1629 * Note we don't actually disable the device until all callers of
Roman Fietzeee6583f2010-05-18 14:45:47 +02001630 * pci_enable_device() have called pci_disable_device().
Linus Torvalds1da177e2005-04-16 15:20:36 -07001631 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04001632void pci_disable_device(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001633{
Tejun Heo9ac78492007-01-20 16:00:26 +09001634 struct pci_devres *dr;
Shaohua Li99dc8042006-05-26 10:58:27 +08001635
Tejun Heo9ac78492007-01-20 16:00:26 +09001636 dr = find_pci_dr(dev);
1637 if (dr)
Tejun Heo7f375f32007-02-25 04:36:01 -08001638 dr->enabled = 0;
Tejun Heo9ac78492007-01-20 16:00:26 +09001639
Konstantin Khlebnikovfd6dcea2013-02-04 15:56:01 +04001640 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0,
1641 "disabling already-disabled device");
1642
Bjorn Helgaascc7ba392013-02-11 16:47:01 -07001643 if (atomic_dec_return(&dev->enable_cnt) != 0)
Inaky Perez-Gonzalezbae94d02006-11-22 12:40:31 -08001644 return;
1645
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001646 do_pci_disable_device(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001647
Rafael J. Wysockifa58d302009-01-07 13:03:42 +01001648 dev->is_busmaster = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001649}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001650EXPORT_SYMBOL(pci_disable_device);
Linus Torvalds1da177e2005-04-16 15:20:36 -07001651
1652/**
Brian Kingf7bdd122007-04-06 16:39:36 -05001653 * pcibios_set_pcie_reset_state - set reset state for device dev
Stefan Assmann45e829e2009-12-03 06:49:24 -05001654 * @dev: the PCIe device reset
Brian Kingf7bdd122007-04-06 16:39:36 -05001655 * @state: Reset state to enter into
1656 *
1657 *
Stefan Assmann45e829e2009-12-03 06:49:24 -05001658 * Sets the PCIe reset state for the device. This is the default
Brian Kingf7bdd122007-04-06 16:39:36 -05001659 * implementation. Architecture implementations can override this.
1660 */
Bjorn Helgaasd6d88c82012-06-19 06:54:49 -06001661int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev,
1662 enum pcie_reset_state state)
Brian Kingf7bdd122007-04-06 16:39:36 -05001663{
1664 return -EINVAL;
1665}
1666
1667/**
1668 * pci_set_pcie_reset_state - set reset state for device dev
Stefan Assmann45e829e2009-12-03 06:49:24 -05001669 * @dev: the PCIe device reset
Brian Kingf7bdd122007-04-06 16:39:36 -05001670 * @state: Reset state to enter into
1671 *
1672 *
1673 * Sets the PCI reset state for the device.
1674 */
1675int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state)
1676{
1677 return pcibios_set_pcie_reset_state(dev, state);
1678}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001679EXPORT_SYMBOL_GPL(pci_set_pcie_reset_state);
Brian Kingf7bdd122007-04-06 16:39:36 -05001680
1681/**
Rafael J. Wysocki58ff4632010-02-17 23:36:58 +01001682 * pci_check_pme_status - Check if given device has generated PME.
1683 * @dev: Device to check.
1684 *
1685 * Check the PME status of the device and if set, clear it and clear PME enable
1686 * (if set). Return 'true' if PME status and PME enable were both set or
1687 * 'false' otherwise.
1688 */
1689bool pci_check_pme_status(struct pci_dev *dev)
1690{
1691 int pmcsr_pos;
1692 u16 pmcsr;
1693 bool ret = false;
1694
1695 if (!dev->pm_cap)
1696 return false;
1697
1698 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL;
1699 pci_read_config_word(dev, pmcsr_pos, &pmcsr);
1700 if (!(pmcsr & PCI_PM_CTRL_PME_STATUS))
1701 return false;
1702
1703 /* Clear PME status. */
1704 pmcsr |= PCI_PM_CTRL_PME_STATUS;
1705 if (pmcsr & PCI_PM_CTRL_PME_ENABLE) {
1706 /* Disable PME to avoid interrupt flood. */
1707 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1708 ret = true;
1709 }
1710
1711 pci_write_config_word(dev, pmcsr_pos, pmcsr);
1712
1713 return ret;
1714}
1715
1716/**
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001717 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
1718 * @dev: Device to handle.
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001719 * @pme_poll_reset: Whether or not to reset the device's pme_poll flag.
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001720 *
1721 * Check if @dev has generated PME and queue a resume request for it in that
1722 * case.
1723 */
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001724static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset)
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001725{
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001726 if (pme_poll_reset && dev->pme_poll)
1727 dev->pme_poll = false;
1728
Rafael J. Wysockic125e962010-07-05 22:43:53 +02001729 if (pci_check_pme_status(dev)) {
Rafael J. Wysockic125e962010-07-05 22:43:53 +02001730 pci_wakeup_event(dev);
Rafael J. Wysocki0f953bf2010-12-29 13:22:08 +01001731 pm_request_resume(&dev->dev);
Rafael J. Wysockic125e962010-07-05 22:43:53 +02001732 }
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001733 return 0;
1734}
1735
1736/**
1737 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
1738 * @bus: Top bus of the subtree to walk.
1739 */
1740void pci_pme_wakeup_bus(struct pci_bus *bus)
1741{
1742 if (bus)
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001743 pci_walk_bus(bus, pci_pme_wakeup, (void *)true);
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01001744}
1745
Huang Ying448bd852012-06-23 10:23:51 +08001746
1747/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001748 * pci_pme_capable - check the capability of PCI device to generate PME#
1749 * @dev: PCI device to handle.
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001750 * @state: PCI state from which device will issue PME#.
1751 */
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02001752bool pci_pme_capable(struct pci_dev *dev, pci_power_t state)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001753{
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001754 if (!dev->pm_cap)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001755 return false;
1756
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001757 return !!(dev->pme_support & (1 << state));
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001758}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001759EXPORT_SYMBOL(pci_pme_capable);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001760
Matthew Garrettdf17e622010-10-04 14:22:29 -04001761static void pci_pme_list_scan(struct work_struct *work)
1762{
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001763 struct pci_pme_device *pme_dev, *n;
Matthew Garrettdf17e622010-10-04 14:22:29 -04001764
1765 mutex_lock(&pci_pme_list_mutex);
Bjorn Helgaasce300002014-01-24 09:51:06 -07001766 list_for_each_entry_safe(pme_dev, n, &pci_pme_list, list) {
1767 if (pme_dev->dev->pme_poll) {
1768 struct pci_dev *bridge;
Zheng Yan71a83bd2012-06-23 10:23:49 +08001769
Bjorn Helgaasce300002014-01-24 09:51:06 -07001770 bridge = pme_dev->dev->bus->self;
1771 /*
1772 * If bridge is in low power state, the
1773 * configuration space of subordinate devices
1774 * may be not accessible
1775 */
1776 if (bridge && bridge->current_state != PCI_D0)
1777 continue;
1778 pci_pme_wakeup(pme_dev->dev, NULL);
1779 } else {
1780 list_del(&pme_dev->list);
1781 kfree(pme_dev);
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001782 }
Matthew Garrettdf17e622010-10-04 14:22:29 -04001783 }
Bjorn Helgaasce300002014-01-24 09:51:06 -07001784 if (!list_empty(&pci_pme_list))
Lukas Wunnerdb663642017-04-18 20:44:30 +02001785 queue_delayed_work(system_freezable_wq, &pci_pme_work,
1786 msecs_to_jiffies(PME_TIMEOUT));
Matthew Garrettdf17e622010-10-04 14:22:29 -04001787 mutex_unlock(&pci_pme_list_mutex);
1788}
1789
Rafael J. Wysocki2cef5482015-09-30 01:10:24 +02001790static void __pci_pme_active(struct pci_dev *dev, bool enable)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001791{
1792 u16 pmcsr;
1793
Rafael J. Wysockiffaddbe2013-04-10 10:32:51 +00001794 if (!dev->pme_support)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001795 return;
1796
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001797 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001798 /* Clear PME_Status by writing 1 to it and enable PME# */
1799 pmcsr |= PCI_PM_CTRL_PME_STATUS | PCI_PM_CTRL_PME_ENABLE;
1800 if (!enable)
1801 pmcsr &= ~PCI_PM_CTRL_PME_ENABLE;
1802
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02001803 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr);
Rafael J. Wysocki2cef5482015-09-30 01:10:24 +02001804}
1805
1806/**
1807 * pci_pme_active - enable or disable PCI device's PME# function
1808 * @dev: PCI device to handle.
1809 * @enable: 'true' to enable PME# generation; 'false' to disable it.
1810 *
1811 * The caller must verify that the device is capable of generating PME# before
1812 * calling this function with @enable equal to 'true'.
1813 */
1814void pci_pme_active(struct pci_dev *dev, bool enable)
1815{
1816 __pci_pme_active(dev, enable);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001817
Huang Ying6e965e02012-10-26 13:07:51 +08001818 /*
1819 * PCI (as opposed to PCIe) PME requires that the device have
1820 * its PME# line hooked up correctly. Not all hardware vendors
1821 * do this, so the PME never gets delivered and the device
1822 * remains asleep. The easiest way around this is to
1823 * periodically walk the list of suspended devices and check
1824 * whether any have their PME flag set. The assumption is that
1825 * we'll wake up often enough anyway that this won't be a huge
1826 * hit, and the power savings from the devices will still be a
1827 * win.
1828 *
1829 * Although PCIe uses in-band PME message instead of PME# line
1830 * to report PME, PME does not work for some PCIe devices in
1831 * reality. For example, there are devices that set their PME
1832 * status bits, but don't really bother to send a PME message;
1833 * there are PCI Express Root Ports that don't bother to
1834 * trigger interrupts when they receive PME messages from the
1835 * devices below. So PME poll is used for PCIe devices too.
1836 */
Matthew Garrettdf17e622010-10-04 14:22:29 -04001837
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02001838 if (dev->pme_poll) {
Matthew Garrettdf17e622010-10-04 14:22:29 -04001839 struct pci_pme_device *pme_dev;
1840 if (enable) {
1841 pme_dev = kmalloc(sizeof(struct pci_pme_device),
1842 GFP_KERNEL);
Bjorn Helgaas0394cb12013-10-16 12:32:53 -06001843 if (!pme_dev) {
1844 dev_warn(&dev->dev, "can't enable PME#\n");
1845 return;
1846 }
Matthew Garrettdf17e622010-10-04 14:22:29 -04001847 pme_dev->dev = dev;
1848 mutex_lock(&pci_pme_list_mutex);
1849 list_add(&pme_dev->list, &pci_pme_list);
1850 if (list_is_singular(&pci_pme_list))
Lukas Wunnerdb663642017-04-18 20:44:30 +02001851 queue_delayed_work(system_freezable_wq,
1852 &pci_pme_work,
1853 msecs_to_jiffies(PME_TIMEOUT));
Matthew Garrettdf17e622010-10-04 14:22:29 -04001854 mutex_unlock(&pci_pme_list_mutex);
1855 } else {
1856 mutex_lock(&pci_pme_list_mutex);
1857 list_for_each_entry(pme_dev, &pci_pme_list, list) {
1858 if (pme_dev->dev == dev) {
1859 list_del(&pme_dev->list);
1860 kfree(pme_dev);
1861 break;
1862 }
1863 }
1864 mutex_unlock(&pci_pme_list_mutex);
1865 }
1866 }
1867
Vincent Palatin85b85822011-12-05 11:51:18 -08001868 dev_dbg(&dev->dev, "PME# %s\n", enable ? "enabled" : "disabled");
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001869}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001870EXPORT_SYMBOL(pci_pme_active);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001871
1872/**
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001873 * __pci_enable_wake - enable PCI device as wakeup event source
David Brownell075c1772007-04-26 00:12:06 -07001874 * @dev: PCI device affected
1875 * @state: PCI state from which device will issue wakeup events
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001876 * @runtime: True if the events are to be generated at run time
David Brownell075c1772007-04-26 00:12:06 -07001877 * @enable: True to enable event generation; false to disable
Linus Torvalds1da177e2005-04-16 15:20:36 -07001878 *
David Brownell075c1772007-04-26 00:12:06 -07001879 * This enables the device as a wakeup event source, or disables it.
1880 * When such events involves platform-specific hooks, those hooks are
1881 * called automatically by this routine.
1882 *
1883 * Devices with legacy power management (no standard PCI PM capabilities)
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001884 * always require such platform hooks.
David Brownell075c1772007-04-26 00:12:06 -07001885 *
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001886 * RETURN VALUE:
1887 * 0 is returned on success
1888 * -EINVAL is returned if device is not supposed to wake up the system
1889 * Error code depending on the platform is returned if both the platform and
1890 * the native mechanism fail to enable the generation of wake-up events
Linus Torvalds1da177e2005-04-16 15:20:36 -07001891 */
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001892int __pci_enable_wake(struct pci_dev *dev, pci_power_t state,
1893 bool runtime, bool enable)
Linus Torvalds1da177e2005-04-16 15:20:36 -07001894{
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001895 int ret = 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07001896
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001897 if (enable && !runtime && !device_may_wakeup(&dev->dev))
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001898 return -EINVAL;
1899
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001900 /* Don't do the same thing twice in a row for one device. */
1901 if (!!enable == !!dev->wakeup_prepared)
1902 return 0;
1903
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001904 /*
1905 * According to "PCI System Architecture" 4th ed. by Tom Shanley & Don
1906 * Anderson we should be doing PME# wake enable followed by ACPI wake
1907 * enable. To disable wake-up we call the platform first, for symmetry.
David Brownell075c1772007-04-26 00:12:06 -07001908 */
1909
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001910 if (enable) {
1911 int error;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001912
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001913 if (pci_pme_capable(dev, state))
1914 pci_pme_active(dev, true);
1915 else
1916 ret = 1;
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001917 error = runtime ? platform_pci_run_wake(dev, true) :
1918 platform_pci_sleep_wake(dev, true);
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001919 if (ret)
1920 ret = error;
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001921 if (!ret)
1922 dev->wakeup_prepared = true;
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001923 } else {
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001924 if (runtime)
1925 platform_pci_run_wake(dev, false);
1926 else
1927 platform_pci_sleep_wake(dev, false);
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001928 pci_pme_active(dev, false);
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02001929 dev->wakeup_prepared = false;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001930 }
1931
Rafael J. Wysocki5bcc2fb2009-09-08 23:12:59 +02001932 return ret;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001933}
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01001934EXPORT_SYMBOL(__pci_enable_wake);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02001935
1936/**
Rafael J. Wysocki0235c4f2008-08-18 21:38:00 +02001937 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
1938 * @dev: PCI device to prepare
1939 * @enable: True to enable wake-up event generation; false to disable
1940 *
1941 * Many drivers want the device to wake up the system from D3_hot or D3_cold
1942 * and this function allows them to set that up cleanly - pci_enable_wake()
1943 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
1944 * ordering constraints.
1945 *
1946 * This function only returns error code if the device is not capable of
1947 * generating PME# from both D3_hot and D3_cold, and the platform is unable to
1948 * enable wake-up power for it.
1949 */
1950int pci_wake_from_d3(struct pci_dev *dev, bool enable)
1951{
1952 return pci_pme_capable(dev, PCI_D3cold) ?
1953 pci_enable_wake(dev, PCI_D3cold, enable) :
1954 pci_enable_wake(dev, PCI_D3hot, enable);
1955}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06001956EXPORT_SYMBOL(pci_wake_from_d3);
Rafael J. Wysocki0235c4f2008-08-18 21:38:00 +02001957
1958/**
Jesse Barnes37139072008-07-28 11:49:26 -07001959 * pci_target_state - find an appropriate low power state for a given PCI dev
1960 * @dev: PCI device
1961 *
1962 * Use underlying platform code to find a supported low power state for @dev.
1963 * If the platform can't manage @dev, return the deepest state from which it
1964 * can generate wake events, based on any available PME info.
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001965 */
Stephen Hemminger0b950f02014-01-10 17:14:48 -07001966static pci_power_t pci_target_state(struct pci_dev *dev)
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001967{
1968 pci_power_t target_state = PCI_D3hot;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001969
1970 if (platform_pci_power_manageable(dev)) {
1971 /*
1972 * Call the platform to choose the target state of the device
1973 * and enable wake-up from this state if supported.
1974 */
1975 pci_power_t state = platform_pci_choose_state(dev);
1976
1977 switch (state) {
1978 case PCI_POWER_ERROR:
1979 case PCI_UNKNOWN:
1980 break;
1981 case PCI_D1:
1982 case PCI_D2:
1983 if (pci_no_d1d2(dev))
1984 break;
1985 default:
1986 target_state = state;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02001987 }
Lukas Wunner4132a572016-09-18 05:39:20 +02001988
1989 return target_state;
1990 }
1991
1992 if (!dev->pm_cap)
Rafael J. Wysockid2abdf62009-06-14 21:25:02 +02001993 target_state = PCI_D0;
Lukas Wunner4132a572016-09-18 05:39:20 +02001994
1995 /*
1996 * If the device is in D3cold even though it's not power-manageable by
1997 * the platform, it may have been powered down by non-standard means.
1998 * Best to let it slumber.
1999 */
2000 if (dev->current_state == PCI_D3cold)
2001 target_state = PCI_D3cold;
2002
2003 if (device_may_wakeup(&dev->dev)) {
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02002004 /*
2005 * Find the deepest state from which the device can generate
2006 * wake-up events, make it the target state and enable device
2007 * to generate PME#.
2008 */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02002009 if (dev->pme_support) {
2010 while (target_state
2011 && !(dev->pme_support & (1 << target_state)))
2012 target_state--;
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02002013 }
2014 }
2015
Rafael J. Wysockie5899e12008-07-19 14:39:24 +02002016 return target_state;
2017}
2018
2019/**
2020 * pci_prepare_to_sleep - prepare PCI device for system-wide transition into a sleep state
2021 * @dev: Device to handle.
2022 *
2023 * Choose the power state appropriate for the device depending on whether
2024 * it can wake up the system and/or is power manageable by the platform
2025 * (PCI_D3hot is the default) and put the device into that state.
2026 */
2027int pci_prepare_to_sleep(struct pci_dev *dev)
2028{
2029 pci_power_t target_state = pci_target_state(dev);
2030 int error;
2031
2032 if (target_state == PCI_POWER_ERROR)
2033 return -EIO;
2034
Rafael J. Wysocki8efb8c72009-03-30 21:46:27 +02002035 pci_enable_wake(dev, target_state, device_may_wakeup(&dev->dev));
Rafael J. Wysockic157dfa2008-07-13 22:45:06 +02002036
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02002037 error = pci_set_power_state(dev, target_state);
2038
2039 if (error)
2040 pci_enable_wake(dev, target_state, false);
2041
2042 return error;
2043}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06002044EXPORT_SYMBOL(pci_prepare_to_sleep);
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02002045
2046/**
Randy Dunlap443bd1c2008-07-21 09:27:18 -07002047 * pci_back_from_sleep - turn PCI device on during system-wide transition into working state
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02002048 * @dev: Device to handle.
2049 *
Thomas Weber88393162010-03-16 11:47:56 +01002050 * Disable device's system wake-up capability and put it into D0.
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02002051 */
2052int pci_back_from_sleep(struct pci_dev *dev)
2053{
2054 pci_enable_wake(dev, PCI_D0, false);
2055 return pci_set_power_state(dev, PCI_D0);
2056}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06002057EXPORT_SYMBOL(pci_back_from_sleep);
Rafael J. Wysocki404cc2d2008-07-07 03:35:26 +02002058
2059/**
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01002060 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2061 * @dev: PCI device being suspended.
2062 *
2063 * Prepare @dev to generate wake-up events at run time and put it into a low
2064 * power state.
2065 */
2066int pci_finish_runtime_suspend(struct pci_dev *dev)
2067{
2068 pci_power_t target_state = pci_target_state(dev);
2069 int error;
2070
2071 if (target_state == PCI_POWER_ERROR)
2072 return -EIO;
2073
Huang Ying448bd852012-06-23 10:23:51 +08002074 dev->runtime_d3cold = target_state == PCI_D3cold;
2075
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01002076 __pci_enable_wake(dev, target_state, true, pci_dev_run_wake(dev));
2077
2078 error = pci_set_power_state(dev, target_state);
2079
Huang Ying448bd852012-06-23 10:23:51 +08002080 if (error) {
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01002081 __pci_enable_wake(dev, target_state, true, false);
Huang Ying448bd852012-06-23 10:23:51 +08002082 dev->runtime_d3cold = false;
2083 }
Rafael J. Wysocki6cbf8212010-02-17 23:44:58 +01002084
2085 return error;
2086}
2087
2088/**
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01002089 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2090 * @dev: Device to check.
2091 *
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002092 * Return true if the device itself is capable of generating wake-up events
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01002093 * (through the platform or using the native PCIe PME) or if the device supports
2094 * PME and one of its upstream bridges can generate wake-up events.
2095 */
2096bool pci_dev_run_wake(struct pci_dev *dev)
2097{
2098 struct pci_bus *bus = dev->bus;
2099
2100 if (device_run_wake(&dev->dev))
2101 return true;
2102
2103 if (!dev->pme_support)
2104 return false;
2105
Alan Sternd8c34b02016-10-21 16:45:38 -04002106 /* PME-capable in principle, but not from the intended sleep state */
2107 if (!pci_pme_capable(dev, pci_target_state(dev)))
2108 return false;
2109
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01002110 while (bus->parent) {
2111 struct pci_dev *bridge = bus->self;
2112
2113 if (device_run_wake(&bridge->dev))
2114 return true;
2115
2116 bus = bus->parent;
2117 }
2118
2119 /* We have reached the root bus. */
2120 if (bus->bridge)
2121 return device_run_wake(bus->bridge);
2122
2123 return false;
2124}
2125EXPORT_SYMBOL_GPL(pci_dev_run_wake);
2126
Rafael J. Wysockibac2a902015-01-21 02:17:42 +01002127/**
2128 * pci_dev_keep_suspended - Check if the device can stay in the suspended state.
2129 * @pci_dev: Device to check.
2130 *
2131 * Return 'true' if the device is runtime-suspended, it doesn't have to be
2132 * reconfigured due to wakeup settings difference between system and runtime
2133 * suspend and the current power state of it is suitable for the upcoming
2134 * (system) transition.
Rafael J. Wysocki2cef5482015-09-30 01:10:24 +02002135 *
2136 * If the device is not configured for system wakeup, disable PME for it before
2137 * returning 'true' to prevent it from waking up the system unnecessarily.
Rafael J. Wysockibac2a902015-01-21 02:17:42 +01002138 */
2139bool pci_dev_keep_suspended(struct pci_dev *pci_dev)
2140{
2141 struct device *dev = &pci_dev->dev;
2142
2143 if (!pm_runtime_suspended(dev)
Rafael J. Wysocki2cef5482015-09-30 01:10:24 +02002144 || pci_target_state(pci_dev) != pci_dev->current_state
Imre Deakb372d352017-05-23 14:18:17 -05002145 || platform_pci_need_resume(pci_dev)
2146 || (pci_dev->dev_flags & PCI_DEV_FLAGS_NEEDS_RESUME))
Rafael J. Wysockibac2a902015-01-21 02:17:42 +01002147 return false;
2148
Rafael J. Wysocki2cef5482015-09-30 01:10:24 +02002149 /*
2150 * At this point the device is good to go unless it's been configured
2151 * to generate PME at the runtime suspend time, but it is not supposed
2152 * to wake up the system. In that case, simply disable PME for it
2153 * (it will have to be re-enabled on exit from system resume).
2154 *
2155 * If the device's power state is D3cold and the platform check above
2156 * hasn't triggered, the device's configuration is suitable and we don't
2157 * need to manipulate it at all.
2158 */
2159 spin_lock_irq(&dev->power.lock);
2160
2161 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold &&
2162 !device_may_wakeup(dev))
2163 __pci_pme_active(pci_dev, false);
2164
2165 spin_unlock_irq(&dev->power.lock);
2166 return true;
2167}
2168
2169/**
2170 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2171 * @pci_dev: Device to handle.
2172 *
2173 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2174 * it might have been disabled during the prepare phase of system suspend if
2175 * the device was not configured for system wakeup.
2176 */
2177void pci_dev_complete_resume(struct pci_dev *pci_dev)
2178{
2179 struct device *dev = &pci_dev->dev;
2180
2181 if (!pci_dev_run_wake(pci_dev))
2182 return;
2183
2184 spin_lock_irq(&dev->power.lock);
2185
2186 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold)
2187 __pci_pme_active(pci_dev, true);
2188
2189 spin_unlock_irq(&dev->power.lock);
Rafael J. Wysockibac2a902015-01-21 02:17:42 +01002190}
2191
Huang Yingb3c32c42012-10-25 09:36:03 +08002192void pci_config_pm_runtime_get(struct pci_dev *pdev)
2193{
2194 struct device *dev = &pdev->dev;
2195 struct device *parent = dev->parent;
2196
2197 if (parent)
2198 pm_runtime_get_sync(parent);
2199 pm_runtime_get_noresume(dev);
2200 /*
2201 * pdev->current_state is set to PCI_D3cold during suspending,
2202 * so wait until suspending completes
2203 */
2204 pm_runtime_barrier(dev);
2205 /*
2206 * Only need to resume devices in D3cold, because config
2207 * registers are still accessible for devices suspended but
2208 * not in D3cold.
2209 */
2210 if (pdev->current_state == PCI_D3cold)
2211 pm_runtime_resume(dev);
2212}
2213
2214void pci_config_pm_runtime_put(struct pci_dev *pdev)
2215{
2216 struct device *dev = &pdev->dev;
2217 struct device *parent = dev->parent;
2218
2219 pm_runtime_put(dev);
2220 if (parent)
2221 pm_runtime_put_sync(parent);
2222}
2223
Rafael J. Wysockib67ea762010-02-17 23:44:09 +01002224/**
Mika Westerberg9d26d3a2016-06-02 11:17:12 +03002225 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
2226 * @bridge: Bridge to check
2227 *
2228 * This function checks if it is possible to move the bridge to D3.
2229 * Currently we only allow D3 for recent enough PCIe ports.
2230 */
2231static bool pci_bridge_d3_possible(struct pci_dev *bridge)
2232{
2233 unsigned int year;
2234
2235 if (!pci_is_pcie(bridge))
2236 return false;
2237
2238 switch (pci_pcie_type(bridge)) {
2239 case PCI_EXP_TYPE_ROOT_PORT:
2240 case PCI_EXP_TYPE_UPSTREAM:
2241 case PCI_EXP_TYPE_DOWNSTREAM:
2242 if (pci_bridge_d3_disable)
2243 return false;
2244 if (pci_bridge_d3_force)
2245 return true;
2246
2247 /*
2248 * It should be safe to put PCIe ports from 2015 or newer
2249 * to D3.
2250 */
2251 if (dmi_get_date(DMI_BIOS_DATE, &year, NULL, NULL) &&
2252 year >= 2015) {
2253 return true;
2254 }
2255 break;
2256 }
2257
2258 return false;
2259}
2260
2261static int pci_dev_check_d3cold(struct pci_dev *dev, void *data)
2262{
2263 bool *d3cold_ok = data;
2264 bool no_d3cold;
2265
2266 /*
2267 * The device needs to be allowed to go D3cold and if it is wake
2268 * capable to do so from D3cold.
2269 */
2270 no_d3cold = dev->no_d3cold || !dev->d3cold_allowed ||
2271 (device_may_wakeup(&dev->dev) && !pci_pme_capable(dev, PCI_D3cold)) ||
2272 !pci_power_manageable(dev);
2273
2274 *d3cold_ok = !no_d3cold;
2275
2276 return no_d3cold;
2277}
2278
2279/*
2280 * pci_bridge_d3_update - Update bridge D3 capabilities
2281 * @dev: PCI device which is changed
2282 * @remove: Is the device being removed
2283 *
2284 * Update upstream bridge PM capabilities accordingly depending on if the
2285 * device PM configuration was changed or the device is being removed. The
2286 * change is also propagated upstream.
2287 */
2288static void pci_bridge_d3_update(struct pci_dev *dev, bool remove)
2289{
2290 struct pci_dev *bridge;
2291 bool d3cold_ok = true;
2292
2293 bridge = pci_upstream_bridge(dev);
2294 if (!bridge || !pci_bridge_d3_possible(bridge))
2295 return;
2296
2297 pci_dev_get(bridge);
2298 /*
2299 * If the device is removed we do not care about its D3cold
2300 * capabilities.
2301 */
2302 if (!remove)
2303 pci_dev_check_d3cold(dev, &d3cold_ok);
2304
2305 if (d3cold_ok) {
2306 /*
2307 * We need to go through all children to find out if all of
2308 * them can still go to D3cold.
2309 */
2310 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold,
2311 &d3cold_ok);
2312 }
2313
2314 if (bridge->bridge_d3 != d3cold_ok) {
2315 bridge->bridge_d3 = d3cold_ok;
2316 /* Propagate change to upstream bridges */
2317 pci_bridge_d3_update(bridge, false);
2318 }
2319
2320 pci_dev_put(bridge);
2321}
2322
2323/**
2324 * pci_bridge_d3_device_changed - Update bridge D3 capabilities on change
2325 * @dev: PCI device that was changed
2326 *
2327 * If a device is added or its PM configuration, such as is it allowed to
2328 * enter D3cold, is changed this function updates upstream bridge PM
2329 * capabilities accordingly.
2330 */
2331void pci_bridge_d3_device_changed(struct pci_dev *dev)
2332{
2333 pci_bridge_d3_update(dev, false);
2334}
2335
2336/**
2337 * pci_bridge_d3_device_removed - Update bridge D3 capabilities on remove
2338 * @dev: PCI device being removed
2339 *
2340 * Function updates upstream bridge PM capabilities based on other devices
2341 * still left on the bus.
2342 */
2343void pci_bridge_d3_device_removed(struct pci_dev *dev)
2344{
2345 pci_bridge_d3_update(dev, true);
2346}
2347
2348/**
2349 * pci_d3cold_enable - Enable D3cold for device
2350 * @dev: PCI device to handle
2351 *
2352 * This function can be used in drivers to enable D3cold from the device
2353 * they handle. It also updates upstream PCI bridge PM capabilities
2354 * accordingly.
2355 */
2356void pci_d3cold_enable(struct pci_dev *dev)
2357{
2358 if (dev->no_d3cold) {
2359 dev->no_d3cold = false;
2360 pci_bridge_d3_device_changed(dev);
2361 }
2362}
2363EXPORT_SYMBOL_GPL(pci_d3cold_enable);
2364
2365/**
2366 * pci_d3cold_disable - Disable D3cold for device
2367 * @dev: PCI device to handle
2368 *
2369 * This function can be used in drivers to disable D3cold from the device
2370 * they handle. It also updates upstream PCI bridge PM capabilities
2371 * accordingly.
2372 */
2373void pci_d3cold_disable(struct pci_dev *dev)
2374{
2375 if (!dev->no_d3cold) {
2376 dev->no_d3cold = true;
2377 pci_bridge_d3_device_changed(dev);
2378 }
2379}
2380EXPORT_SYMBOL_GPL(pci_d3cold_disable);
2381
2382/**
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02002383 * pci_pm_init - Initialize PM functions of given PCI device
2384 * @dev: PCI device to handle.
2385 */
2386void pci_pm_init(struct pci_dev *dev)
2387{
2388 int pm;
2389 u16 pmc;
David Brownell075c1772007-04-26 00:12:06 -07002390
Rafael J. Wysockibb910a72010-02-27 21:37:37 +01002391 pm_runtime_forbid(&dev->dev);
Huang Ying967577b2012-11-20 16:08:22 +08002392 pm_runtime_set_active(&dev->dev);
2393 pm_runtime_enable(&dev->dev);
Rafael J. Wysockia1e4d722010-02-08 19:16:33 +01002394 device_enable_async_suspend(&dev->dev);
Rafael J. Wysockie80bb092009-09-08 23:14:49 +02002395 dev->wakeup_prepared = false;
Rafael J. Wysockibb910a72010-02-27 21:37:37 +01002396
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02002397 dev->pm_cap = 0;
Rafael J. Wysockiffaddbe2013-04-10 10:32:51 +00002398 dev->pme_support = 0;
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02002399
Linus Torvalds1da177e2005-04-16 15:20:36 -07002400 /* find PCI PM capability in list */
2401 pm = pci_find_capability(dev, PCI_CAP_ID_PM);
David Brownell075c1772007-04-26 00:12:06 -07002402 if (!pm)
Linus Torvalds50246dd2009-01-16 08:14:51 -08002403 return;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002404 /* Check device's ability to generate PME# */
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02002405 pci_read_config_word(dev, pm + PCI_PM_PMC, &pmc);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002406
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02002407 if ((pmc & PCI_PM_CAP_VER_MASK) > 3) {
2408 dev_err(&dev->dev, "unsupported PM cap regs version (%u)\n",
2409 pmc & PCI_PM_CAP_VER_MASK);
Linus Torvalds50246dd2009-01-16 08:14:51 -08002410 return;
David Brownell075c1772007-04-26 00:12:06 -07002411 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002412
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02002413 dev->pm_cap = pm;
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +01002414 dev->d3_delay = PCI_PM_D3_WAIT;
Huang Ying448bd852012-06-23 10:23:51 +08002415 dev->d3cold_delay = PCI_PM_D3COLD_WAIT;
Mika Westerberg9d26d3a2016-06-02 11:17:12 +03002416 dev->bridge_d3 = pci_bridge_d3_possible(dev);
Huang Ying4f9c1392012-08-08 09:07:38 +08002417 dev->d3cold_allowed = true;
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02002418
2419 dev->d1_support = false;
2420 dev->d2_support = false;
2421 if (!pci_no_d1d2(dev)) {
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06002422 if (pmc & PCI_PM_CAP_D1)
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02002423 dev->d1_support = true;
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06002424 if (pmc & PCI_PM_CAP_D2)
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02002425 dev->d2_support = true;
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06002426
2427 if (dev->d1_support || dev->d2_support)
2428 dev_printk(KERN_DEBUG, &dev->dev, "supports%s%s\n",
Jesse Barnesec84f122008-09-23 11:43:34 -07002429 dev->d1_support ? " D1" : "",
2430 dev->d2_support ? " D2" : "");
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02002431 }
2432
2433 pmc &= PCI_PM_CAP_PME_MASK;
2434 if (pmc) {
Bjorn Helgaas10c3d712009-11-04 10:32:42 -07002435 dev_printk(KERN_DEBUG, &dev->dev,
2436 "PME# supported from%s%s%s%s%s\n",
Bjorn Helgaasc9ed77e2008-08-22 09:37:02 -06002437 (pmc & PCI_PM_CAP_PME_D0) ? " D0" : "",
2438 (pmc & PCI_PM_CAP_PME_D1) ? " D1" : "",
2439 (pmc & PCI_PM_CAP_PME_D2) ? " D2" : "",
2440 (pmc & PCI_PM_CAP_PME_D3) ? " D3hot" : "",
2441 (pmc & PCI_PM_CAP_PME_D3cold) ? " D3cold" : "");
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02002442 dev->pme_support = pmc >> PCI_PM_CAP_PME_SHIFT;
Rafael J. Wysocki379021d2011-10-03 23:16:33 +02002443 dev->pme_poll = true;
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02002444 /*
2445 * Make device's PM flags reflect the wake-up capability, but
2446 * let the user space enable it to wake up the system as needed.
2447 */
2448 device_set_wakeup_capable(&dev->dev, true);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02002449 /* Disable the PME# generation functionality */
Rafael J. Wysocki337001b2008-07-07 03:36:24 +02002450 pci_pme_active(dev, false);
Rafael J. Wysockieb9d0fe2008-07-07 03:34:48 +02002451 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07002452}
2453
Sean O. Stalley938174e2015-10-29 17:35:39 -05002454static unsigned long pci_ea_flags(struct pci_dev *dev, u8 prop)
2455{
Alex Williamson92efb1b2016-05-16 15:12:02 -05002456 unsigned long flags = IORESOURCE_PCI_FIXED | IORESOURCE_PCI_EA_BEI;
Sean O. Stalley938174e2015-10-29 17:35:39 -05002457
2458 switch (prop) {
2459 case PCI_EA_P_MEM:
2460 case PCI_EA_P_VF_MEM:
2461 flags |= IORESOURCE_MEM;
2462 break;
2463 case PCI_EA_P_MEM_PREFETCH:
2464 case PCI_EA_P_VF_MEM_PREFETCH:
2465 flags |= IORESOURCE_MEM | IORESOURCE_PREFETCH;
2466 break;
2467 case PCI_EA_P_IO:
2468 flags |= IORESOURCE_IO;
2469 break;
2470 default:
2471 return 0;
2472 }
2473
2474 return flags;
2475}
2476
2477static struct resource *pci_ea_get_resource(struct pci_dev *dev, u8 bei,
2478 u8 prop)
2479{
2480 if (bei <= PCI_EA_BEI_BAR5 && prop <= PCI_EA_P_IO)
2481 return &dev->resource[bei];
David Daney11183992015-10-29 17:35:40 -05002482#ifdef CONFIG_PCI_IOV
2483 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5 &&
2484 (prop == PCI_EA_P_VF_MEM || prop == PCI_EA_P_VF_MEM_PREFETCH))
2485 return &dev->resource[PCI_IOV_RESOURCES +
2486 bei - PCI_EA_BEI_VF_BAR0];
2487#endif
Sean O. Stalley938174e2015-10-29 17:35:39 -05002488 else if (bei == PCI_EA_BEI_ROM)
2489 return &dev->resource[PCI_ROM_RESOURCE];
2490 else
2491 return NULL;
2492}
2493
2494/* Read an Enhanced Allocation (EA) entry */
2495static int pci_ea_read(struct pci_dev *dev, int offset)
2496{
2497 struct resource *res;
2498 int ent_size, ent_offset = offset;
2499 resource_size_t start, end;
2500 unsigned long flags;
Bjorn Helgaas26635112015-10-29 17:35:40 -05002501 u32 dw0, bei, base, max_offset;
Sean O. Stalley938174e2015-10-29 17:35:39 -05002502 u8 prop;
2503 bool support_64 = (sizeof(resource_size_t) >= 8);
2504
2505 pci_read_config_dword(dev, ent_offset, &dw0);
2506 ent_offset += 4;
2507
2508 /* Entry size field indicates DWORDs after 1st */
2509 ent_size = ((dw0 & PCI_EA_ES) + 1) << 2;
2510
2511 if (!(dw0 & PCI_EA_ENABLE)) /* Entry not enabled */
2512 goto out;
2513
Bjorn Helgaas26635112015-10-29 17:35:40 -05002514 bei = (dw0 & PCI_EA_BEI) >> 4;
2515 prop = (dw0 & PCI_EA_PP) >> 8;
2516
Sean O. Stalley938174e2015-10-29 17:35:39 -05002517 /*
2518 * If the Property is in the reserved range, try the Secondary
2519 * Property instead.
2520 */
2521 if (prop > PCI_EA_P_BRIDGE_IO && prop < PCI_EA_P_MEM_RESERVED)
Bjorn Helgaas26635112015-10-29 17:35:40 -05002522 prop = (dw0 & PCI_EA_SP) >> 16;
Sean O. Stalley938174e2015-10-29 17:35:39 -05002523 if (prop > PCI_EA_P_BRIDGE_IO)
2524 goto out;
2525
Bjorn Helgaas26635112015-10-29 17:35:40 -05002526 res = pci_ea_get_resource(dev, bei, prop);
Sean O. Stalley938174e2015-10-29 17:35:39 -05002527 if (!res) {
Bjorn Helgaas26635112015-10-29 17:35:40 -05002528 dev_err(&dev->dev, "Unsupported EA entry BEI: %u\n", bei);
Sean O. Stalley938174e2015-10-29 17:35:39 -05002529 goto out;
2530 }
2531
2532 flags = pci_ea_flags(dev, prop);
2533 if (!flags) {
2534 dev_err(&dev->dev, "Unsupported EA properties: %#x\n", prop);
2535 goto out;
2536 }
2537
2538 /* Read Base */
2539 pci_read_config_dword(dev, ent_offset, &base);
2540 start = (base & PCI_EA_FIELD_MASK);
2541 ent_offset += 4;
2542
2543 /* Read MaxOffset */
2544 pci_read_config_dword(dev, ent_offset, &max_offset);
2545 ent_offset += 4;
2546
2547 /* Read Base MSBs (if 64-bit entry) */
2548 if (base & PCI_EA_IS_64) {
2549 u32 base_upper;
2550
2551 pci_read_config_dword(dev, ent_offset, &base_upper);
2552 ent_offset += 4;
2553
2554 flags |= IORESOURCE_MEM_64;
2555
2556 /* entry starts above 32-bit boundary, can't use */
2557 if (!support_64 && base_upper)
2558 goto out;
2559
2560 if (support_64)
2561 start |= ((u64)base_upper << 32);
2562 }
2563
2564 end = start + (max_offset | 0x03);
2565
2566 /* Read MaxOffset MSBs (if 64-bit entry) */
2567 if (max_offset & PCI_EA_IS_64) {
2568 u32 max_offset_upper;
2569
2570 pci_read_config_dword(dev, ent_offset, &max_offset_upper);
2571 ent_offset += 4;
2572
2573 flags |= IORESOURCE_MEM_64;
2574
2575 /* entry too big, can't use */
2576 if (!support_64 && max_offset_upper)
2577 goto out;
2578
2579 if (support_64)
2580 end += ((u64)max_offset_upper << 32);
2581 }
2582
2583 if (end < start) {
2584 dev_err(&dev->dev, "EA Entry crosses address boundary\n");
2585 goto out;
2586 }
2587
2588 if (ent_size != ent_offset - offset) {
2589 dev_err(&dev->dev,
2590 "EA Entry Size (%d) does not match length read (%d)\n",
2591 ent_size, ent_offset - offset);
2592 goto out;
2593 }
2594
2595 res->name = pci_name(dev);
2596 res->start = start;
2597 res->end = end;
2598 res->flags = flags;
Bjorn Helgaas597becb2015-10-29 17:35:40 -05002599
2600 if (bei <= PCI_EA_BEI_BAR5)
2601 dev_printk(KERN_DEBUG, &dev->dev, "BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2602 bei, res, prop);
2603 else if (bei == PCI_EA_BEI_ROM)
2604 dev_printk(KERN_DEBUG, &dev->dev, "ROM: %pR (from Enhanced Allocation, properties %#02x)\n",
2605 res, prop);
2606 else if (bei >= PCI_EA_BEI_VF_BAR0 && bei <= PCI_EA_BEI_VF_BAR5)
2607 dev_printk(KERN_DEBUG, &dev->dev, "VF BAR %d: %pR (from Enhanced Allocation, properties %#02x)\n",
2608 bei - PCI_EA_BEI_VF_BAR0, res, prop);
2609 else
2610 dev_printk(KERN_DEBUG, &dev->dev, "BEI %d res: %pR (from Enhanced Allocation, properties %#02x)\n",
2611 bei, res, prop);
2612
Sean O. Stalley938174e2015-10-29 17:35:39 -05002613out:
2614 return offset + ent_size;
2615}
2616
Colin Ian Kingdcbb4082016-04-05 12:12:45 -05002617/* Enhanced Allocation Initialization */
Sean O. Stalley938174e2015-10-29 17:35:39 -05002618void pci_ea_init(struct pci_dev *dev)
2619{
2620 int ea;
2621 u8 num_ent;
2622 int offset;
2623 int i;
2624
2625 /* find PCI EA capability in list */
2626 ea = pci_find_capability(dev, PCI_CAP_ID_EA);
2627 if (!ea)
2628 return;
2629
2630 /* determine the number of entries */
2631 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT,
2632 &num_ent);
2633 num_ent &= PCI_EA_NUM_ENT_MASK;
2634
2635 offset = ea + PCI_EA_FIRST_ENT;
2636
2637 /* Skip DWORD 2 for type 1 functions */
2638 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE)
2639 offset += 4;
2640
2641 /* parse each EA entry */
2642 for (i = 0; i < num_ent; ++i)
2643 offset = pci_ea_read(dev, offset);
2644}
2645
Yinghai Lu34a48762012-02-11 00:18:41 -08002646static void pci_add_saved_cap(struct pci_dev *pci_dev,
2647 struct pci_cap_saved_state *new_cap)
2648{
2649 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space);
2650}
2651
Jesse Barneseb9c39d2008-12-17 12:10:05 -08002652/**
Alex Williamsonfd0f7f72013-12-17 16:43:45 -07002653 * _pci_add_cap_save_buffer - allocate buffer for saving given
2654 * capability registers
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002655 * @dev: the PCI device
2656 * @cap: the capability to allocate the buffer for
Alex Williamsonfd0f7f72013-12-17 16:43:45 -07002657 * @extended: Standard or Extended capability ID
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002658 * @size: requested size of the buffer
2659 */
Alex Williamsonfd0f7f72013-12-17 16:43:45 -07002660static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap,
2661 bool extended, unsigned int size)
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002662{
2663 int pos;
2664 struct pci_cap_saved_state *save_state;
2665
Alex Williamsonfd0f7f72013-12-17 16:43:45 -07002666 if (extended)
2667 pos = pci_find_ext_capability(dev, cap);
2668 else
2669 pos = pci_find_capability(dev, cap);
2670
Wei Yang0a1a9b42015-06-30 09:16:44 +08002671 if (!pos)
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002672 return 0;
2673
2674 save_state = kzalloc(sizeof(*save_state) + size, GFP_KERNEL);
2675 if (!save_state)
2676 return -ENOMEM;
2677
Alex Williamson24a4742f2011-05-10 10:02:11 -06002678 save_state->cap.cap_nr = cap;
Alex Williamsonfd0f7f72013-12-17 16:43:45 -07002679 save_state->cap.cap_extended = extended;
Alex Williamson24a4742f2011-05-10 10:02:11 -06002680 save_state->cap.size = size;
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002681 pci_add_saved_cap(dev, save_state);
2682
2683 return 0;
2684}
2685
Alex Williamsonfd0f7f72013-12-17 16:43:45 -07002686int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size)
2687{
2688 return _pci_add_cap_save_buffer(dev, cap, false, size);
2689}
2690
2691int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size)
2692{
2693 return _pci_add_cap_save_buffer(dev, cap, true, size);
2694}
2695
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002696/**
2697 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
2698 * @dev: the PCI device
2699 */
2700void pci_allocate_cap_save_buffers(struct pci_dev *dev)
2701{
2702 int error;
2703
Yu Zhao89858512009-02-16 02:55:47 +08002704 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_EXP,
2705 PCI_EXP_SAVE_REGS * sizeof(u16));
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002706 if (error)
2707 dev_err(&dev->dev,
2708 "unable to preallocate PCI Express save buffer\n");
2709
2710 error = pci_add_cap_save_buffer(dev, PCI_CAP_ID_PCIX, sizeof(u16));
2711 if (error)
2712 dev_err(&dev->dev,
2713 "unable to preallocate PCI-X save buffer\n");
Alex Williamson425c1b22013-12-17 16:43:51 -07002714
2715 pci_allocate_vc_save_buffers(dev);
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002716}
2717
Yinghai Luf7968412012-02-11 00:18:30 -08002718void pci_free_cap_save_buffers(struct pci_dev *dev)
2719{
2720 struct pci_cap_saved_state *tmp;
Sasha Levinb67bfe02013-02-27 17:06:00 -08002721 struct hlist_node *n;
Yinghai Luf7968412012-02-11 00:18:30 -08002722
Sasha Levinb67bfe02013-02-27 17:06:00 -08002723 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next)
Yinghai Luf7968412012-02-11 00:18:30 -08002724 kfree(tmp);
2725}
2726
Rafael J. Wysocki63f48982008-12-07 22:02:58 +01002727/**
Yijing Wang31ab2472013-01-15 11:12:17 +08002728 * pci_configure_ari - enable or disable ARI forwarding
Yu Zhao58c3a722008-10-14 14:02:53 +08002729 * @dev: the PCI device
Yijing Wangb0cc6022013-01-15 11:12:16 +08002730 *
2731 * If @dev and its upstream bridge both support ARI, enable ARI in the
2732 * bridge. Otherwise, disable ARI in the bridge.
Yu Zhao58c3a722008-10-14 14:02:53 +08002733 */
Yijing Wang31ab2472013-01-15 11:12:17 +08002734void pci_configure_ari(struct pci_dev *dev)
Yu Zhao58c3a722008-10-14 14:02:53 +08002735{
Yu Zhao58c3a722008-10-14 14:02:53 +08002736 u32 cap;
Zhao, Yu81135872008-10-23 13:15:39 +08002737 struct pci_dev *bridge;
Yu Zhao58c3a722008-10-14 14:02:53 +08002738
Rafael J. Wysocki6748dcc2012-03-01 00:06:33 +01002739 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn)
Yu Zhao58c3a722008-10-14 14:02:53 +08002740 return;
2741
Zhao, Yu81135872008-10-23 13:15:39 +08002742 bridge = dev->bus->self;
Myron Stowecb97ae32012-06-01 15:16:31 -06002743 if (!bridge)
Zhao, Yu81135872008-10-23 13:15:39 +08002744 return;
2745
Jiang Liu59875ae2012-07-24 17:20:06 +08002746 pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
Yu Zhao58c3a722008-10-14 14:02:53 +08002747 if (!(cap & PCI_EXP_DEVCAP2_ARI))
2748 return;
2749
Yijing Wangb0cc6022013-01-15 11:12:16 +08002750 if (pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI)) {
2751 pcie_capability_set_word(bridge, PCI_EXP_DEVCTL2,
2752 PCI_EXP_DEVCTL2_ARI);
2753 bridge->ari_enabled = 1;
2754 } else {
2755 pcie_capability_clear_word(bridge, PCI_EXP_DEVCTL2,
2756 PCI_EXP_DEVCTL2_ARI);
2757 bridge->ari_enabled = 0;
2758 }
Yu Zhao58c3a722008-10-14 14:02:53 +08002759}
2760
Chris Wright5d990b62009-12-04 12:15:21 -08002761static int pci_acs_enable;
2762
2763/**
2764 * pci_request_acs - ask for ACS to be enabled if supported
2765 */
2766void pci_request_acs(void)
2767{
2768 pci_acs_enable = 1;
2769}
2770
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002771/**
Alex Williamson2c744242014-02-03 14:27:33 -07002772 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilites
Allen Kayae21ee62009-10-07 10:27:17 -07002773 * @dev: the PCI device
2774 */
Alex Williamsonc1d61c92016-03-31 16:34:32 -06002775static void pci_std_enable_acs(struct pci_dev *dev)
Allen Kayae21ee62009-10-07 10:27:17 -07002776{
2777 int pos;
2778 u16 cap;
2779 u16 ctrl;
2780
Allen Kayae21ee62009-10-07 10:27:17 -07002781 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS);
2782 if (!pos)
Alex Williamsonc1d61c92016-03-31 16:34:32 -06002783 return;
Allen Kayae21ee62009-10-07 10:27:17 -07002784
2785 pci_read_config_word(dev, pos + PCI_ACS_CAP, &cap);
2786 pci_read_config_word(dev, pos + PCI_ACS_CTRL, &ctrl);
2787
2788 /* Source Validation */
2789 ctrl |= (cap & PCI_ACS_SV);
2790
2791 /* P2P Request Redirect */
2792 ctrl |= (cap & PCI_ACS_RR);
2793
2794 /* P2P Completion Redirect */
2795 ctrl |= (cap & PCI_ACS_CR);
2796
2797 /* Upstream Forwarding */
2798 ctrl |= (cap & PCI_ACS_UF);
2799
2800 pci_write_config_word(dev, pos + PCI_ACS_CTRL, ctrl);
Alex Williamson2c744242014-02-03 14:27:33 -07002801}
2802
2803/**
2804 * pci_enable_acs - enable ACS if hardware support it
2805 * @dev: the PCI device
2806 */
2807void pci_enable_acs(struct pci_dev *dev)
2808{
2809 if (!pci_acs_enable)
2810 return;
2811
Alex Williamsonc1d61c92016-03-31 16:34:32 -06002812 if (!pci_dev_specific_enable_acs(dev))
Alex Williamson2c744242014-02-03 14:27:33 -07002813 return;
2814
Alex Williamsonc1d61c92016-03-31 16:34:32 -06002815 pci_std_enable_acs(dev);
Allen Kayae21ee62009-10-07 10:27:17 -07002816}
2817
Alex Williamson0a671192013-06-27 16:39:48 -06002818static bool pci_acs_flags_enabled(struct pci_dev *pdev, u16 acs_flags)
2819{
2820 int pos;
Alex Williamson83db7e02013-06-27 16:39:54 -06002821 u16 cap, ctrl;
Alex Williamson0a671192013-06-27 16:39:48 -06002822
2823 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ACS);
2824 if (!pos)
2825 return false;
2826
Alex Williamson83db7e02013-06-27 16:39:54 -06002827 /*
2828 * Except for egress control, capabilities are either required
2829 * or only required if controllable. Features missing from the
2830 * capability field can therefore be assumed as hard-wired enabled.
2831 */
2832 pci_read_config_word(pdev, pos + PCI_ACS_CAP, &cap);
2833 acs_flags &= (cap | PCI_ACS_EC);
2834
Alex Williamson0a671192013-06-27 16:39:48 -06002835 pci_read_config_word(pdev, pos + PCI_ACS_CTRL, &ctrl);
2836 return (ctrl & acs_flags) == acs_flags;
2837}
2838
Allen Kayae21ee62009-10-07 10:27:17 -07002839/**
Alex Williamsonad805752012-06-11 05:27:07 +00002840 * pci_acs_enabled - test ACS against required flags for a given device
2841 * @pdev: device to test
2842 * @acs_flags: required PCI ACS flags
2843 *
2844 * Return true if the device supports the provided flags. Automatically
2845 * filters out flags that are not implemented on multifunction devices.
Alex Williamson0a671192013-06-27 16:39:48 -06002846 *
2847 * Note that this interface checks the effective ACS capabilities of the
2848 * device rather than the actual capabilities. For instance, most single
2849 * function endpoints are not required to support ACS because they have no
2850 * opportunity for peer-to-peer access. We therefore return 'true'
2851 * regardless of whether the device exposes an ACS capability. This makes
2852 * it much easier for callers of this function to ignore the actual type
2853 * or topology of the device when testing ACS support.
Alex Williamsonad805752012-06-11 05:27:07 +00002854 */
2855bool pci_acs_enabled(struct pci_dev *pdev, u16 acs_flags)
2856{
Alex Williamson0a671192013-06-27 16:39:48 -06002857 int ret;
Alex Williamsonad805752012-06-11 05:27:07 +00002858
2859 ret = pci_dev_specific_acs_enabled(pdev, acs_flags);
2860 if (ret >= 0)
2861 return ret > 0;
2862
Alex Williamson0a671192013-06-27 16:39:48 -06002863 /*
2864 * Conventional PCI and PCI-X devices never support ACS, either
2865 * effectively or actually. The shared bus topology implies that
2866 * any device on the bus can receive or snoop DMA.
2867 */
Alex Williamsonad805752012-06-11 05:27:07 +00002868 if (!pci_is_pcie(pdev))
2869 return false;
2870
Alex Williamson0a671192013-06-27 16:39:48 -06002871 switch (pci_pcie_type(pdev)) {
2872 /*
2873 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec,
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002874 * but since their primary interface is PCI/X, we conservatively
Alex Williamson0a671192013-06-27 16:39:48 -06002875 * handle them as we would a non-PCIe device.
2876 */
2877 case PCI_EXP_TYPE_PCIE_BRIDGE:
2878 /*
2879 * PCIe 3.0, 6.12.1 excludes ACS on these devices. "ACS is never
2880 * applicable... must never implement an ACS Extended Capability...".
2881 * This seems arbitrary, but we take a conservative interpretation
2882 * of this statement.
2883 */
2884 case PCI_EXP_TYPE_PCI_BRIDGE:
2885 case PCI_EXP_TYPE_RC_EC:
2886 return false;
2887 /*
2888 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should
2889 * implement ACS in order to indicate their peer-to-peer capabilities,
2890 * regardless of whether they are single- or multi-function devices.
2891 */
2892 case PCI_EXP_TYPE_DOWNSTREAM:
2893 case PCI_EXP_TYPE_ROOT_PORT:
2894 return pci_acs_flags_enabled(pdev, acs_flags);
2895 /*
2896 * PCIe 3.0, 6.12.1.2 specifies ACS capabilities that should be
2897 * implemented by the remaining PCIe types to indicate peer-to-peer
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002898 * capabilities, but only when they are part of a multifunction
Alex Williamson0a671192013-06-27 16:39:48 -06002899 * device. The footnote for section 6.12 indicates the specific
2900 * PCIe types included here.
2901 */
2902 case PCI_EXP_TYPE_ENDPOINT:
2903 case PCI_EXP_TYPE_UPSTREAM:
2904 case PCI_EXP_TYPE_LEG_END:
2905 case PCI_EXP_TYPE_RC_END:
2906 if (!pdev->multifunction)
2907 break;
2908
Alex Williamson0a671192013-06-27 16:39:48 -06002909 return pci_acs_flags_enabled(pdev, acs_flags);
Alex Williamsonad805752012-06-11 05:27:07 +00002910 }
2911
Alex Williamson0a671192013-06-27 16:39:48 -06002912 /*
Bjorn Helgaasf7625982013-11-14 11:28:18 -07002913 * PCIe 3.0, 6.12.1.3 specifies no ACS capabilities are applicable
Alex Williamson0a671192013-06-27 16:39:48 -06002914 * to single function devices with the exception of downstream ports.
2915 */
Alex Williamsonad805752012-06-11 05:27:07 +00002916 return true;
2917}
2918
2919/**
2920 * pci_acs_path_enable - test ACS flags from start to end in a hierarchy
2921 * @start: starting downstream device
2922 * @end: ending upstream device or NULL to search to the root bus
2923 * @acs_flags: required flags
2924 *
2925 * Walk up a device tree from start to end testing PCI ACS support. If
2926 * any step along the way does not support the required flags, return false.
2927 */
2928bool pci_acs_path_enabled(struct pci_dev *start,
2929 struct pci_dev *end, u16 acs_flags)
2930{
2931 struct pci_dev *pdev, *parent = start;
2932
2933 do {
2934 pdev = parent;
2935
2936 if (!pci_acs_enabled(pdev, acs_flags))
2937 return false;
2938
2939 if (pci_is_root_bus(pdev->bus))
2940 return (end == NULL);
2941
2942 parent = pdev->bus->self;
2943 } while (pdev != end);
2944
2945 return true;
2946}
2947
2948/**
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002949 * pci_swizzle_interrupt_pin - swizzle INTx for device behind bridge
2950 * @dev: the PCI device
Wang Sheng-Huibb5c2de2013-05-28 11:17:41 +08002951 * @pin: the INTx pin (1=INTA, 2=INTB, 3=INTC, 4=INTD)
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002952 *
2953 * Perform INTx swizzling for a device behind one level of bridge. This is
2954 * required by section 9.1 of the PCI-to-PCI bridge specification for devices
Matthew Wilcox46b952a2009-07-01 14:24:30 -07002955 * behind bridges on add-in cards. For devices with ARI enabled, the slot
2956 * number is always 0 (see the Implementation Note in section 2.2.8.1 of
2957 * the PCI Express Base Specification, Revision 2.1)
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002958 */
John Crispin3df425f2012-04-12 17:33:07 +02002959u8 pci_swizzle_interrupt_pin(const struct pci_dev *dev, u8 pin)
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002960{
Matthew Wilcox46b952a2009-07-01 14:24:30 -07002961 int slot;
2962
2963 if (pci_ari_enabled(dev->bus))
2964 slot = 0;
2965 else
2966 slot = PCI_SLOT(dev->devfn);
2967
2968 return (((pin - 1) + slot) % 4) + 1;
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002969}
2970
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04002971int pci_get_interrupt_pin(struct pci_dev *dev, struct pci_dev **bridge)
Linus Torvalds1da177e2005-04-16 15:20:36 -07002972{
2973 u8 pin;
2974
Kristen Accardi514d2072005-11-02 16:24:39 -08002975 pin = dev->pin;
Linus Torvalds1da177e2005-04-16 15:20:36 -07002976 if (!pin)
2977 return -1;
Bjorn Helgaas878f2e52008-12-09 16:11:46 -07002978
Kenji Kaneshige8784fd42009-05-26 16:07:33 +09002979 while (!pci_is_root_bus(dev->bus)) {
Bjorn Helgaas57c2cf72008-12-11 11:24:23 -07002980 pin = pci_swizzle_interrupt_pin(dev, pin);
Linus Torvalds1da177e2005-04-16 15:20:36 -07002981 dev = dev->bus->self;
2982 }
2983 *bridge = dev;
2984 return pin;
2985}
2986
2987/**
Bjorn Helgaas68feac82008-12-16 21:36:55 -07002988 * pci_common_swizzle - swizzle INTx all the way to root bridge
2989 * @dev: the PCI device
2990 * @pinp: pointer to the INTx pin value (1=INTA, 2=INTB, 3=INTD, 4=INTD)
2991 *
2992 * Perform INTx swizzling for a device. This traverses through all PCI-to-PCI
2993 * bridges all the way up to a PCI root bus.
2994 */
2995u8 pci_common_swizzle(struct pci_dev *dev, u8 *pinp)
2996{
2997 u8 pin = *pinp;
2998
Kenji Kaneshige1eb39482009-05-26 16:08:36 +09002999 while (!pci_is_root_bus(dev->bus)) {
Bjorn Helgaas68feac82008-12-16 21:36:55 -07003000 pin = pci_swizzle_interrupt_pin(dev, pin);
3001 dev = dev->bus->self;
3002 }
3003 *pinp = pin;
3004 return PCI_SLOT(dev->devfn);
3005}
Ray Juie6b29de2015-04-08 11:21:33 -07003006EXPORT_SYMBOL_GPL(pci_common_swizzle);
Bjorn Helgaas68feac82008-12-16 21:36:55 -07003007
3008/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07003009 * pci_release_region - Release a PCI bar
3010 * @pdev: PCI device whose resources were previously reserved by pci_request_region
3011 * @bar: BAR to release
3012 *
3013 * Releases the PCI I/O and memory resources previously reserved by a
3014 * successful call to pci_request_region. Call this function only
3015 * after all use of the PCI regions has ceased.
3016 */
3017void pci_release_region(struct pci_dev *pdev, int bar)
3018{
Tejun Heo9ac78492007-01-20 16:00:26 +09003019 struct pci_devres *dr;
3020
Linus Torvalds1da177e2005-04-16 15:20:36 -07003021 if (pci_resource_len(pdev, bar) == 0)
3022 return;
3023 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO)
3024 release_region(pci_resource_start(pdev, bar),
3025 pci_resource_len(pdev, bar));
3026 else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM)
3027 release_mem_region(pci_resource_start(pdev, bar),
3028 pci_resource_len(pdev, bar));
Tejun Heo9ac78492007-01-20 16:00:26 +09003029
3030 dr = find_pci_dr(pdev);
3031 if (dr)
3032 dr->region_mask &= ~(1 << bar);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003033}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003034EXPORT_SYMBOL(pci_release_region);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003035
3036/**
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08003037 * __pci_request_region - Reserved PCI I/O and memory resource
Linus Torvalds1da177e2005-04-16 15:20:36 -07003038 * @pdev: PCI device whose resources are to be reserved
3039 * @bar: BAR to be reserved
3040 * @res_name: Name to be associated with resource.
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08003041 * @exclusive: whether the region access is exclusive or not
Linus Torvalds1da177e2005-04-16 15:20:36 -07003042 *
3043 * Mark the PCI region associated with PCI device @pdev BR @bar as
3044 * being reserved by owner @res_name. Do not access any
3045 * address inside the PCI regions unless this call returns
3046 * successfully.
3047 *
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08003048 * If @exclusive is set, then the region is marked so that userspace
3049 * is explicitly not allowed to map the resource via /dev/mem or
Bjorn Helgaasf7625982013-11-14 11:28:18 -07003050 * sysfs MMIO access.
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08003051 *
Linus Torvalds1da177e2005-04-16 15:20:36 -07003052 * Returns 0 on success, or %EBUSY on error. A warning
3053 * message is also printed on failure.
3054 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003055static int __pci_request_region(struct pci_dev *pdev, int bar,
3056 const char *res_name, int exclusive)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003057{
Tejun Heo9ac78492007-01-20 16:00:26 +09003058 struct pci_devres *dr;
3059
Linus Torvalds1da177e2005-04-16 15:20:36 -07003060 if (pci_resource_len(pdev, bar) == 0)
3061 return 0;
Bjorn Helgaasf7625982013-11-14 11:28:18 -07003062
Linus Torvalds1da177e2005-04-16 15:20:36 -07003063 if (pci_resource_flags(pdev, bar) & IORESOURCE_IO) {
3064 if (!request_region(pci_resource_start(pdev, bar),
3065 pci_resource_len(pdev, bar), res_name))
3066 goto err_out;
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003067 } else if (pci_resource_flags(pdev, bar) & IORESOURCE_MEM) {
Arjan van de Vene8de1482008-10-22 19:55:31 -07003068 if (!__request_mem_region(pci_resource_start(pdev, bar),
3069 pci_resource_len(pdev, bar), res_name,
3070 exclusive))
Linus Torvalds1da177e2005-04-16 15:20:36 -07003071 goto err_out;
3072 }
Tejun Heo9ac78492007-01-20 16:00:26 +09003073
3074 dr = find_pci_dr(pdev);
3075 if (dr)
3076 dr->region_mask |= 1 << bar;
3077
Linus Torvalds1da177e2005-04-16 15:20:36 -07003078 return 0;
3079
3080err_out:
Bjorn Helgaasc7dabef2009-10-27 13:26:47 -06003081 dev_warn(&pdev->dev, "BAR %d: can't reserve %pR\n", bar,
Benjamin Herrenschmidt096e6f62008-10-20 15:07:37 +11003082 &pdev->resource[bar]);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003083 return -EBUSY;
3084}
3085
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09003086/**
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08003087 * pci_request_region - Reserve PCI I/O and memory resource
Arjan van de Vene8de1482008-10-22 19:55:31 -07003088 * @pdev: PCI device whose resources are to be reserved
3089 * @bar: BAR to be reserved
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08003090 * @res_name: Name to be associated with resource
Arjan van de Vene8de1482008-10-22 19:55:31 -07003091 *
Randy Dunlapf5ddcac2009-01-09 17:03:20 -08003092 * Mark the PCI region associated with PCI device @pdev BAR @bar as
Arjan van de Vene8de1482008-10-22 19:55:31 -07003093 * being reserved by owner @res_name. Do not access any
3094 * address inside the PCI regions unless this call returns
3095 * successfully.
3096 *
3097 * Returns 0 on success, or %EBUSY on error. A warning
3098 * message is also printed on failure.
3099 */
3100int pci_request_region(struct pci_dev *pdev, int bar, const char *res_name)
3101{
3102 return __pci_request_region(pdev, bar, res_name, 0);
3103}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003104EXPORT_SYMBOL(pci_request_region);
Arjan van de Vene8de1482008-10-22 19:55:31 -07003105
3106/**
3107 * pci_request_region_exclusive - Reserved PCI I/O and memory resource
3108 * @pdev: PCI device whose resources are to be reserved
3109 * @bar: BAR to be reserved
3110 * @res_name: Name to be associated with resource.
3111 *
3112 * Mark the PCI region associated with PCI device @pdev BR @bar as
3113 * being reserved by owner @res_name. Do not access any
3114 * address inside the PCI regions unless this call returns
3115 * successfully.
3116 *
3117 * Returns 0 on success, or %EBUSY on error. A warning
3118 * message is also printed on failure.
3119 *
3120 * The key difference that _exclusive makes it that userspace is
3121 * explicitly not allowed to map the resource via /dev/mem or
Bjorn Helgaasf7625982013-11-14 11:28:18 -07003122 * sysfs.
Arjan van de Vene8de1482008-10-22 19:55:31 -07003123 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003124int pci_request_region_exclusive(struct pci_dev *pdev, int bar,
3125 const char *res_name)
Arjan van de Vene8de1482008-10-22 19:55:31 -07003126{
3127 return __pci_request_region(pdev, bar, res_name, IORESOURCE_EXCLUSIVE);
3128}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003129EXPORT_SYMBOL(pci_request_region_exclusive);
3130
Arjan van de Vene8de1482008-10-22 19:55:31 -07003131/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09003132 * pci_release_selected_regions - Release selected PCI I/O and memory resources
3133 * @pdev: PCI device whose resources were previously reserved
3134 * @bars: Bitmask of BARs to be released
3135 *
3136 * Release selected PCI I/O and memory resources previously reserved.
3137 * Call this function only after all use of the PCI regions has ceased.
3138 */
3139void pci_release_selected_regions(struct pci_dev *pdev, int bars)
3140{
3141 int i;
3142
3143 for (i = 0; i < 6; i++)
3144 if (bars & (1 << i))
3145 pci_release_region(pdev, i);
3146}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003147EXPORT_SYMBOL(pci_release_selected_regions);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09003148
Bjorn Helgaas9738abe2013-04-12 11:20:03 -06003149static int __pci_request_selected_regions(struct pci_dev *pdev, int bars,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003150 const char *res_name, int excl)
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09003151{
3152 int i;
3153
3154 for (i = 0; i < 6; i++)
3155 if (bars & (1 << i))
Arjan van de Vene8de1482008-10-22 19:55:31 -07003156 if (__pci_request_region(pdev, i, res_name, excl))
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09003157 goto err_out;
3158 return 0;
3159
3160err_out:
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003161 while (--i >= 0)
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09003162 if (bars & (1 << i))
3163 pci_release_region(pdev, i);
3164
3165 return -EBUSY;
3166}
Linus Torvalds1da177e2005-04-16 15:20:36 -07003167
Arjan van de Vene8de1482008-10-22 19:55:31 -07003168
3169/**
3170 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
3171 * @pdev: PCI device whose resources are to be reserved
3172 * @bars: Bitmask of BARs to be requested
3173 * @res_name: Name to be associated with resource
3174 */
3175int pci_request_selected_regions(struct pci_dev *pdev, int bars,
3176 const char *res_name)
3177{
3178 return __pci_request_selected_regions(pdev, bars, res_name, 0);
3179}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003180EXPORT_SYMBOL(pci_request_selected_regions);
Arjan van de Vene8de1482008-10-22 19:55:31 -07003181
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003182int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars,
3183 const char *res_name)
Arjan van de Vene8de1482008-10-22 19:55:31 -07003184{
3185 return __pci_request_selected_regions(pdev, bars, res_name,
3186 IORESOURCE_EXCLUSIVE);
3187}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003188EXPORT_SYMBOL(pci_request_selected_regions_exclusive);
Arjan van de Vene8de1482008-10-22 19:55:31 -07003189
Linus Torvalds1da177e2005-04-16 15:20:36 -07003190/**
3191 * pci_release_regions - Release reserved PCI I/O and memory resources
3192 * @pdev: PCI device whose resources were previously reserved by pci_request_regions
3193 *
3194 * Releases all PCI I/O and memory resources previously reserved by a
3195 * successful call to pci_request_regions. Call this function only
3196 * after all use of the PCI regions has ceased.
3197 */
3198
3199void pci_release_regions(struct pci_dev *pdev)
3200{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09003201 pci_release_selected_regions(pdev, (1 << 6) - 1);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003202}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003203EXPORT_SYMBOL(pci_release_regions);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003204
3205/**
3206 * pci_request_regions - Reserved PCI I/O and memory resources
3207 * @pdev: PCI device whose resources are to be reserved
3208 * @res_name: Name to be associated with resource.
3209 *
3210 * Mark all PCI regions associated with PCI device @pdev as
3211 * being reserved by owner @res_name. Do not access any
3212 * address inside the PCI regions unless this call returns
3213 * successfully.
3214 *
3215 * Returns 0 on success, or %EBUSY on error. A warning
3216 * message is also printed on failure.
3217 */
Jeff Garzik3c990e92006-03-04 21:52:42 -05003218int pci_request_regions(struct pci_dev *pdev, const char *res_name)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003219{
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09003220 return pci_request_selected_regions(pdev, ((1 << 6) - 1), res_name);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003221}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003222EXPORT_SYMBOL(pci_request_regions);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003223
3224/**
Arjan van de Vene8de1482008-10-22 19:55:31 -07003225 * pci_request_regions_exclusive - Reserved PCI I/O and memory resources
3226 * @pdev: PCI device whose resources are to be reserved
3227 * @res_name: Name to be associated with resource.
3228 *
3229 * Mark all PCI regions associated with PCI device @pdev as
3230 * being reserved by owner @res_name. Do not access any
3231 * address inside the PCI regions unless this call returns
3232 * successfully.
3233 *
3234 * pci_request_regions_exclusive() will mark the region so that
Bjorn Helgaasf7625982013-11-14 11:28:18 -07003235 * /dev/mem and the sysfs MMIO access will not be allowed.
Arjan van de Vene8de1482008-10-22 19:55:31 -07003236 *
3237 * Returns 0 on success, or %EBUSY on error. A warning
3238 * message is also printed on failure.
3239 */
3240int pci_request_regions_exclusive(struct pci_dev *pdev, const char *res_name)
3241{
3242 return pci_request_selected_regions_exclusive(pdev,
3243 ((1 << 6) - 1), res_name);
3244}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003245EXPORT_SYMBOL(pci_request_regions_exclusive);
Arjan van de Vene8de1482008-10-22 19:55:31 -07003246
Tomasz Nowickic5076cf2016-05-11 17:34:51 -05003247#ifdef PCI_IOBASE
3248struct io_range {
3249 struct list_head list;
3250 phys_addr_t start;
3251 resource_size_t size;
3252};
3253
3254static LIST_HEAD(io_range_list);
3255static DEFINE_SPINLOCK(io_range_lock);
3256#endif
3257
3258/*
3259 * Record the PCI IO range (expressed as CPU physical address + size).
3260 * Return a negative value if an error has occured, zero otherwise
3261 */
3262int __weak pci_register_io_range(phys_addr_t addr, resource_size_t size)
3263{
3264 int err = 0;
3265
3266#ifdef PCI_IOBASE
3267 struct io_range *range;
3268 resource_size_t allocated_size = 0;
3269
3270 /* check if the range hasn't been previously recorded */
3271 spin_lock(&io_range_lock);
3272 list_for_each_entry(range, &io_range_list, list) {
3273 if (addr >= range->start && addr + size <= range->start + size) {
3274 /* range already registered, bail out */
3275 goto end_register;
3276 }
3277 allocated_size += range->size;
3278 }
3279
3280 /* range not registed yet, check for available space */
3281 if (allocated_size + size - 1 > IO_SPACE_LIMIT) {
3282 /* if it's too big check if 64K space can be reserved */
3283 if (allocated_size + SZ_64K - 1 > IO_SPACE_LIMIT) {
3284 err = -E2BIG;
3285 goto end_register;
3286 }
3287
3288 size = SZ_64K;
3289 pr_warn("Requested IO range too big, new size set to 64K\n");
3290 }
3291
3292 /* add the range to the list */
3293 range = kzalloc(sizeof(*range), GFP_ATOMIC);
3294 if (!range) {
3295 err = -ENOMEM;
3296 goto end_register;
3297 }
3298
3299 range->start = addr;
3300 range->size = size;
3301
3302 list_add_tail(&range->list, &io_range_list);
3303
3304end_register:
3305 spin_unlock(&io_range_lock);
3306#endif
3307
3308 return err;
3309}
3310
3311phys_addr_t pci_pio_to_address(unsigned long pio)
3312{
3313 phys_addr_t address = (phys_addr_t)OF_BAD_ADDR;
3314
3315#ifdef PCI_IOBASE
3316 struct io_range *range;
3317 resource_size_t allocated_size = 0;
3318
3319 if (pio > IO_SPACE_LIMIT)
3320 return address;
3321
3322 spin_lock(&io_range_lock);
3323 list_for_each_entry(range, &io_range_list, list) {
3324 if (pio >= allocated_size && pio < allocated_size + range->size) {
3325 address = range->start + pio - allocated_size;
3326 break;
3327 }
3328 allocated_size += range->size;
3329 }
3330 spin_unlock(&io_range_lock);
3331#endif
3332
3333 return address;
3334}
3335
3336unsigned long __weak pci_address_to_pio(phys_addr_t address)
3337{
3338#ifdef PCI_IOBASE
3339 struct io_range *res;
3340 resource_size_t offset = 0;
3341 unsigned long addr = -1;
3342
3343 spin_lock(&io_range_lock);
3344 list_for_each_entry(res, &io_range_list, list) {
3345 if (address >= res->start && address < res->start + res->size) {
3346 addr = address - res->start + offset;
3347 break;
3348 }
3349 offset += res->size;
3350 }
3351 spin_unlock(&io_range_lock);
3352
3353 return addr;
3354#else
3355 if (address > IO_SPACE_LIMIT)
3356 return (unsigned long)-1;
3357
3358 return (unsigned long) address;
3359#endif
3360}
3361
Liviu Dudau8b921ac2014-09-29 15:29:30 +01003362/**
3363 * pci_remap_iospace - Remap the memory mapped I/O space
3364 * @res: Resource describing the I/O space
3365 * @phys_addr: physical address of range to be mapped
3366 *
3367 * Remap the memory mapped I/O space described by the @res
3368 * and the CPU physical address @phys_addr into virtual address space.
3369 * Only architectures that have memory mapped IO functions defined
3370 * (and the PCI_IOBASE value defined) should call this function.
3371 */
3372int __weak pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr)
3373{
3374#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3375 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3376
3377 if (!(res->flags & IORESOURCE_IO))
3378 return -EINVAL;
3379
3380 if (res->end > IO_SPACE_LIMIT)
3381 return -EINVAL;
3382
3383 return ioremap_page_range(vaddr, vaddr + resource_size(res), phys_addr,
3384 pgprot_device(PAGE_KERNEL));
3385#else
3386 /* this architecture does not have memory mapped I/O space,
3387 so this function should never be called */
3388 WARN_ONCE(1, "This architecture does not support memory mapped I/O\n");
3389 return -ENODEV;
3390#endif
3391}
3392
Sinan Kaya4d3f1382016-06-10 21:55:11 +02003393/**
3394 * pci_unmap_iospace - Unmap the memory mapped I/O space
3395 * @res: resource to be unmapped
3396 *
3397 * Unmap the CPU virtual address @res from virtual address space.
3398 * Only architectures that have memory mapped IO functions defined
3399 * (and the PCI_IOBASE value defined) should call this function.
3400 */
3401void pci_unmap_iospace(struct resource *res)
3402{
3403#if defined(PCI_IOBASE) && defined(CONFIG_MMU)
3404 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start;
3405
3406 unmap_kernel_range(vaddr, resource_size(res));
3407#endif
3408}
3409
Ben Hutchings6a479072008-12-23 03:08:29 +00003410static void __pci_set_master(struct pci_dev *dev, bool enable)
3411{
3412 u16 old_cmd, cmd;
3413
3414 pci_read_config_word(dev, PCI_COMMAND, &old_cmd);
3415 if (enable)
3416 cmd = old_cmd | PCI_COMMAND_MASTER;
3417 else
3418 cmd = old_cmd & ~PCI_COMMAND_MASTER;
3419 if (cmd != old_cmd) {
3420 dev_dbg(&dev->dev, "%s bus mastering\n",
3421 enable ? "enabling" : "disabling");
3422 pci_write_config_word(dev, PCI_COMMAND, cmd);
3423 }
3424 dev->is_busmaster = enable;
3425}
Arjan van de Vene8de1482008-10-22 19:55:31 -07003426
3427/**
Myron Stowe2b6f2c32012-06-25 21:30:57 -06003428 * pcibios_setup - process "pci=" kernel boot arguments
3429 * @str: string used to pass in "pci=" kernel boot arguments
3430 *
3431 * Process kernel boot arguments. This is the default implementation.
3432 * Architecture specific implementations can override this as necessary.
3433 */
3434char * __weak __init pcibios_setup(char *str)
3435{
3436 return str;
3437}
3438
3439/**
Myron Stowe96c55902011-10-28 15:48:38 -06003440 * pcibios_set_master - enable PCI bus-mastering for device dev
3441 * @dev: the PCI device to enable
3442 *
3443 * Enables PCI bus-mastering for the device. This is the default
3444 * implementation. Architecture specific implementations can override
3445 * this if necessary.
3446 */
3447void __weak pcibios_set_master(struct pci_dev *dev)
3448{
3449 u8 lat;
3450
Myron Stowef6766782011-10-28 15:49:20 -06003451 /* The latency timer doesn't apply to PCIe (either Type 0 or Type 1) */
3452 if (pci_is_pcie(dev))
3453 return;
3454
Myron Stowe96c55902011-10-28 15:48:38 -06003455 pci_read_config_byte(dev, PCI_LATENCY_TIMER, &lat);
3456 if (lat < 16)
3457 lat = (64 <= pcibios_max_latency) ? 64 : pcibios_max_latency;
3458 else if (lat > pcibios_max_latency)
3459 lat = pcibios_max_latency;
3460 else
3461 return;
Bjorn Helgaasa0064822013-09-23 15:25:26 -06003462
Myron Stowe96c55902011-10-28 15:48:38 -06003463 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat);
3464}
3465
3466/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07003467 * pci_set_master - enables bus-mastering for device dev
3468 * @dev: the PCI device to enable
3469 *
3470 * Enables bus-mastering on the device and calls pcibios_set_master()
3471 * to do the needed arch specific settings.
3472 */
Ben Hutchings6a479072008-12-23 03:08:29 +00003473void pci_set_master(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003474{
Ben Hutchings6a479072008-12-23 03:08:29 +00003475 __pci_set_master(dev, true);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003476 pcibios_set_master(dev);
3477}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003478EXPORT_SYMBOL(pci_set_master);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003479
Ben Hutchings6a479072008-12-23 03:08:29 +00003480/**
3481 * pci_clear_master - disables bus-mastering for device dev
3482 * @dev: the PCI device to disable
3483 */
3484void pci_clear_master(struct pci_dev *dev)
3485{
3486 __pci_set_master(dev, false);
3487}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003488EXPORT_SYMBOL(pci_clear_master);
Ben Hutchings6a479072008-12-23 03:08:29 +00003489
Linus Torvalds1da177e2005-04-16 15:20:36 -07003490/**
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06003491 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
3492 * @dev: the PCI device for which MWI is to be enabled
Linus Torvalds1da177e2005-04-16 15:20:36 -07003493 *
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06003494 * Helper function for pci_set_mwi.
3495 * Originally copied from drivers/net/acenic.c.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003496 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
3497 *
3498 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3499 */
Tejun Heo15ea76d2009-09-22 17:34:48 +09003500int pci_set_cacheline_size(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003501{
3502 u8 cacheline_size;
3503
3504 if (!pci_cache_line_size)
Tejun Heo15ea76d2009-09-22 17:34:48 +09003505 return -EINVAL;
Linus Torvalds1da177e2005-04-16 15:20:36 -07003506
3507 /* Validate current setting: the PCI_CACHE_LINE_SIZE must be
3508 equal to or multiple of the right value. */
3509 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3510 if (cacheline_size >= pci_cache_line_size &&
3511 (cacheline_size % pci_cache_line_size) == 0)
3512 return 0;
3513
3514 /* Write the correct value. */
3515 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, pci_cache_line_size);
3516 /* Read it back. */
3517 pci_read_config_byte(dev, PCI_CACHE_LINE_SIZE, &cacheline_size);
3518 if (cacheline_size == pci_cache_line_size)
3519 return 0;
3520
Ryan Desfosses227f0642014-04-18 20:13:50 -04003521 dev_printk(KERN_DEBUG, &dev->dev, "cache line size of %d is not supported\n",
3522 pci_cache_line_size << 2);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003523
3524 return -EINVAL;
3525}
Tejun Heo15ea76d2009-09-22 17:34:48 +09003526EXPORT_SYMBOL_GPL(pci_set_cacheline_size);
3527
Linus Torvalds1da177e2005-04-16 15:20:36 -07003528/**
3529 * pci_set_mwi - enables memory-write-invalidate PCI transaction
3530 * @dev: the PCI device for which MWI is enabled
3531 *
Randy Dunlap694625c2007-07-09 11:55:54 -07003532 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
Linus Torvalds1da177e2005-04-16 15:20:36 -07003533 *
3534 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3535 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003536int pci_set_mwi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003537{
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003538#ifdef PCI_DISABLE_MWI
3539 return 0;
3540#else
Linus Torvalds1da177e2005-04-16 15:20:36 -07003541 int rc;
3542 u16 cmd;
3543
Matthew Wilcoxedb2d972006-10-10 08:01:21 -06003544 rc = pci_set_cacheline_size(dev);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003545 if (rc)
3546 return rc;
3547
3548 pci_read_config_word(dev, PCI_COMMAND, &cmd);
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003549 if (!(cmd & PCI_COMMAND_INVALIDATE)) {
Bjorn Helgaas80ccba12008-06-13 10:52:11 -06003550 dev_dbg(&dev->dev, "enabling Mem-Wr-Inval\n");
Linus Torvalds1da177e2005-04-16 15:20:36 -07003551 cmd |= PCI_COMMAND_INVALIDATE;
3552 pci_write_config_word(dev, PCI_COMMAND, cmd);
3553 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07003554 return 0;
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003555#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003556}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003557EXPORT_SYMBOL(pci_set_mwi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003558
3559/**
Randy Dunlap694625c2007-07-09 11:55:54 -07003560 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
3561 * @dev: the PCI device for which MWI is enabled
3562 *
3563 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
3564 * Callers are not required to check the return value.
3565 *
3566 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
3567 */
3568int pci_try_set_mwi(struct pci_dev *dev)
3569{
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003570#ifdef PCI_DISABLE_MWI
3571 return 0;
3572#else
3573 return pci_set_mwi(dev);
3574#endif
Randy Dunlap694625c2007-07-09 11:55:54 -07003575}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003576EXPORT_SYMBOL(pci_try_set_mwi);
Randy Dunlap694625c2007-07-09 11:55:54 -07003577
3578/**
Linus Torvalds1da177e2005-04-16 15:20:36 -07003579 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
3580 * @dev: the PCI device to disable
3581 *
3582 * Disables PCI Memory-Write-Invalidate transaction on the device
3583 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003584void pci_clear_mwi(struct pci_dev *dev)
Linus Torvalds1da177e2005-04-16 15:20:36 -07003585{
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003586#ifndef PCI_DISABLE_MWI
Linus Torvalds1da177e2005-04-16 15:20:36 -07003587 u16 cmd;
3588
3589 pci_read_config_word(dev, PCI_COMMAND, &cmd);
3590 if (cmd & PCI_COMMAND_INVALIDATE) {
3591 cmd &= ~PCI_COMMAND_INVALIDATE;
3592 pci_write_config_word(dev, PCI_COMMAND, cmd);
3593 }
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003594#endif
Linus Torvalds1da177e2005-04-16 15:20:36 -07003595}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003596EXPORT_SYMBOL(pci_clear_mwi);
Linus Torvalds1da177e2005-04-16 15:20:36 -07003597
Brett M Russa04ce0f2005-08-15 15:23:41 -04003598/**
3599 * pci_intx - enables/disables PCI INTx for device dev
Randy Dunlap8f7020d2005-10-23 11:57:38 -07003600 * @pdev: the PCI device to operate on
3601 * @enable: boolean: whether to enable or disable PCI INTx
Brett M Russa04ce0f2005-08-15 15:23:41 -04003602 *
3603 * Enables/disables PCI INTx for device dev
3604 */
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003605void pci_intx(struct pci_dev *pdev, int enable)
Brett M Russa04ce0f2005-08-15 15:23:41 -04003606{
3607 u16 pci_command, new;
3608
3609 pci_read_config_word(pdev, PCI_COMMAND, &pci_command);
3610
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003611 if (enable)
Brett M Russa04ce0f2005-08-15 15:23:41 -04003612 new = pci_command & ~PCI_COMMAND_INTX_DISABLE;
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04003613 else
Brett M Russa04ce0f2005-08-15 15:23:41 -04003614 new = pci_command | PCI_COMMAND_INTX_DISABLE;
Brett M Russa04ce0f2005-08-15 15:23:41 -04003615
3616 if (new != pci_command) {
Tejun Heo9ac78492007-01-20 16:00:26 +09003617 struct pci_devres *dr;
3618
Brett M Russ2fd9d742005-09-09 10:02:22 -07003619 pci_write_config_word(pdev, PCI_COMMAND, new);
Tejun Heo9ac78492007-01-20 16:00:26 +09003620
3621 dr = find_pci_dr(pdev);
3622 if (dr && !dr->restore_intx) {
3623 dr->restore_intx = 1;
3624 dr->orig_intx = !enable;
3625 }
Brett M Russa04ce0f2005-08-15 15:23:41 -04003626 }
3627}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06003628EXPORT_SYMBOL_GPL(pci_intx);
Brett M Russa04ce0f2005-08-15 15:23:41 -04003629
Eric W. Biedermanf5f2b132007-03-05 00:30:07 -08003630/**
Jan Kiszkaa2e27782011-11-04 09:46:00 +01003631 * pci_intx_mask_supported - probe for INTx masking support
Randy Dunlap6e9292c2012-01-21 11:02:35 -08003632 * @dev: the PCI device to operate on
Jan Kiszkaa2e27782011-11-04 09:46:00 +01003633 *
3634 * Check if the device dev support INTx masking via the config space
3635 * command word.
3636 */
3637bool pci_intx_mask_supported(struct pci_dev *dev)
3638{
3639 bool mask_supported = false;
3640 u16 orig, new;
3641
Bjorn Helgaasfbebb9f2012-06-16 14:40:22 -06003642 if (dev->broken_intx_masking)
3643 return false;
3644
Jan Kiszkaa2e27782011-11-04 09:46:00 +01003645 pci_cfg_access_lock(dev);
3646
3647 pci_read_config_word(dev, PCI_COMMAND, &orig);
3648 pci_write_config_word(dev, PCI_COMMAND,
3649 orig ^ PCI_COMMAND_INTX_DISABLE);
3650 pci_read_config_word(dev, PCI_COMMAND, &new);
3651
3652 /*
3653 * There's no way to protect against hardware bugs or detect them
3654 * reliably, but as long as we know what the value should be, let's
3655 * go ahead and check it.
3656 */
3657 if ((new ^ orig) & ~PCI_COMMAND_INTX_DISABLE) {
Ryan Desfosses227f0642014-04-18 20:13:50 -04003658 dev_err(&dev->dev, "Command register changed from 0x%x to 0x%x: driver or hardware bug?\n",
3659 orig, new);
Jan Kiszkaa2e27782011-11-04 09:46:00 +01003660 } else if ((new ^ orig) & PCI_COMMAND_INTX_DISABLE) {
3661 mask_supported = true;
3662 pci_write_config_word(dev, PCI_COMMAND, orig);
3663 }
3664
3665 pci_cfg_access_unlock(dev);
3666 return mask_supported;
3667}
3668EXPORT_SYMBOL_GPL(pci_intx_mask_supported);
3669
3670static bool pci_check_and_set_intx_mask(struct pci_dev *dev, bool mask)
3671{
3672 struct pci_bus *bus = dev->bus;
3673 bool mask_updated = true;
3674 u32 cmd_status_dword;
3675 u16 origcmd, newcmd;
3676 unsigned long flags;
3677 bool irq_pending;
3678
3679 /*
3680 * We do a single dword read to retrieve both command and status.
3681 * Document assumptions that make this possible.
3682 */
3683 BUILD_BUG_ON(PCI_COMMAND % 4);
3684 BUILD_BUG_ON(PCI_COMMAND + 2 != PCI_STATUS);
3685
3686 raw_spin_lock_irqsave(&pci_lock, flags);
3687
3688 bus->ops->read(bus, dev->devfn, PCI_COMMAND, 4, &cmd_status_dword);
3689
3690 irq_pending = (cmd_status_dword >> 16) & PCI_STATUS_INTERRUPT;
3691
3692 /*
3693 * Check interrupt status register to see whether our device
3694 * triggered the interrupt (when masking) or the next IRQ is
3695 * already pending (when unmasking).
3696 */
3697 if (mask != irq_pending) {
3698 mask_updated = false;
3699 goto done;
3700 }
3701
3702 origcmd = cmd_status_dword;
3703 newcmd = origcmd & ~PCI_COMMAND_INTX_DISABLE;
3704 if (mask)
3705 newcmd |= PCI_COMMAND_INTX_DISABLE;
3706 if (newcmd != origcmd)
3707 bus->ops->write(bus, dev->devfn, PCI_COMMAND, 2, newcmd);
3708
3709done:
3710 raw_spin_unlock_irqrestore(&pci_lock, flags);
3711
3712 return mask_updated;
3713}
3714
3715/**
3716 * pci_check_and_mask_intx - mask INTx on pending interrupt
Randy Dunlap6e9292c2012-01-21 11:02:35 -08003717 * @dev: the PCI device to operate on
Jan Kiszkaa2e27782011-11-04 09:46:00 +01003718 *
3719 * Check if the device dev has its INTx line asserted, mask it and
3720 * return true in that case. False is returned if not interrupt was
3721 * pending.
3722 */
3723bool pci_check_and_mask_intx(struct pci_dev *dev)
3724{
3725 return pci_check_and_set_intx_mask(dev, true);
3726}
3727EXPORT_SYMBOL_GPL(pci_check_and_mask_intx);
3728
3729/**
Bjorn Helgaasebd50b92014-01-14 17:10:39 -07003730 * pci_check_and_unmask_intx - unmask INTx if no interrupt is pending
Randy Dunlap6e9292c2012-01-21 11:02:35 -08003731 * @dev: the PCI device to operate on
Jan Kiszkaa2e27782011-11-04 09:46:00 +01003732 *
3733 * Check if the device dev has its INTx line asserted, unmask it if not
3734 * and return true. False is returned and the mask remains active if
3735 * there was still an interrupt pending.
3736 */
3737bool pci_check_and_unmask_intx(struct pci_dev *dev)
3738{
3739 return pci_check_and_set_intx_mask(dev, false);
3740}
3741EXPORT_SYMBOL_GPL(pci_check_and_unmask_intx);
3742
Casey Leedom3775a202013-08-06 15:48:36 +05303743/**
3744 * pci_wait_for_pending_transaction - waits for pending transaction
3745 * @dev: the PCI device to operate on
3746 *
3747 * Return 0 if transaction is pending 1 otherwise.
3748 */
3749int pci_wait_for_pending_transaction(struct pci_dev *dev)
Sheng Yang8dd7f802008-10-21 17:38:25 +08003750{
Alex Williamson157e8762013-12-17 16:43:39 -07003751 if (!pci_is_pcie(dev))
3752 return 1;
Sheng Yang8dd7f802008-10-21 17:38:25 +08003753
Gavin Shand0b4cc42014-05-19 13:06:46 +10003754 return pci_wait_for_pending(dev, pci_pcie_cap(dev) + PCI_EXP_DEVSTA,
3755 PCI_EXP_DEVSTA_TRPND);
Casey Leedom3775a202013-08-06 15:48:36 +05303756}
3757EXPORT_SYMBOL(pci_wait_for_pending_transaction);
Sheng Yang5fe5db02009-02-09 14:53:47 +08003758
Alex Williamson5adecf82016-02-22 13:05:48 -07003759/*
3760 * We should only need to wait 100ms after FLR, but some devices take longer.
3761 * Wait for up to 1000ms for config space to return something other than -1.
3762 * Intel IGD requires this when an LCD panel is attached. We read the 2nd
3763 * dword because VFs don't implement the 1st dword.
3764 */
3765static void pci_flr_wait(struct pci_dev *dev)
3766{
3767 int i = 0;
3768 u32 id;
3769
3770 do {
3771 msleep(100);
3772 pci_read_config_dword(dev, PCI_COMMAND, &id);
3773 } while (i++ < 10 && id == ~0);
3774
3775 if (id == ~0)
3776 dev_warn(&dev->dev, "Failed to return from FLR\n");
3777 else if (i > 1)
3778 dev_info(&dev->dev, "Required additional %dms to return from FLR\n",
3779 (i - 1) * 100);
3780}
3781
Casey Leedom3775a202013-08-06 15:48:36 +05303782static int pcie_flr(struct pci_dev *dev, int probe)
3783{
3784 u32 cap;
3785
3786 pcie_capability_read_dword(dev, PCI_EXP_DEVCAP, &cap);
3787 if (!(cap & PCI_EXP_DEVCAP_FLR))
3788 return -ENOTTY;
3789
3790 if (probe)
3791 return 0;
3792
3793 if (!pci_wait_for_pending_transaction(dev))
Gavin Shanbb383e22014-11-12 13:41:51 +11003794 dev_err(&dev->dev, "timed out waiting for pending transaction; performing function level reset anyway\n");
Casey Leedom3775a202013-08-06 15:48:36 +05303795
Jiang Liu59875ae2012-07-24 17:20:06 +08003796 pcie_capability_set_word(dev, PCI_EXP_DEVCTL, PCI_EXP_DEVCTL_BCR_FLR);
Alex Williamson5adecf82016-02-22 13:05:48 -07003797 pci_flr_wait(dev);
Sheng Yang8dd7f802008-10-21 17:38:25 +08003798 return 0;
3799}
Sheng Yangd91cdc72008-11-11 17:17:47 +08003800
Yu Zhao8c1c6992009-06-13 15:52:13 +08003801static int pci_af_flr(struct pci_dev *dev, int probe)
Sheng Yang1ca88792008-11-11 17:17:48 +08003802{
Yu Zhao8c1c6992009-06-13 15:52:13 +08003803 int pos;
Sheng Yang1ca88792008-11-11 17:17:48 +08003804 u8 cap;
3805
Yu Zhao8c1c6992009-06-13 15:52:13 +08003806 pos = pci_find_capability(dev, PCI_CAP_ID_AF);
3807 if (!pos)
Sheng Yang1ca88792008-11-11 17:17:48 +08003808 return -ENOTTY;
Yu Zhao8c1c6992009-06-13 15:52:13 +08003809
3810 pci_read_config_byte(dev, pos + PCI_AF_CAP, &cap);
Sheng Yang1ca88792008-11-11 17:17:48 +08003811 if (!(cap & PCI_AF_CAP_TP) || !(cap & PCI_AF_CAP_FLR))
3812 return -ENOTTY;
3813
3814 if (probe)
3815 return 0;
3816
Alex Williamsond066c942014-06-17 15:40:13 -06003817 /*
3818 * Wait for Transaction Pending bit to clear. A word-aligned test
3819 * is used, so we use the conrol offset rather than status and shift
3820 * the test bit to match.
3821 */
Gavin Shanbb383e22014-11-12 13:41:51 +11003822 if (!pci_wait_for_pending(dev, pos + PCI_AF_CTRL,
Alex Williamsond066c942014-06-17 15:40:13 -06003823 PCI_AF_STATUS_TP << 8))
Gavin Shanbb383e22014-11-12 13:41:51 +11003824 dev_err(&dev->dev, "timed out waiting for pending transaction; performing AF function level reset anyway\n");
Yu Zhao8c1c6992009-06-13 15:52:13 +08003825
Yu Zhao8c1c6992009-06-13 15:52:13 +08003826 pci_write_config_byte(dev, pos + PCI_AF_CTRL, PCI_AF_CTRL_FLR);
Alex Williamson5adecf82016-02-22 13:05:48 -07003827 pci_flr_wait(dev);
Sheng Yang1ca88792008-11-11 17:17:48 +08003828 return 0;
3829}
3830
Rafael J. Wysocki83d74e02011-03-05 21:48:44 +01003831/**
3832 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
3833 * @dev: Device to reset.
3834 * @probe: If set, only check if the device can be reset this way.
3835 *
3836 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
3837 * unset, it will be reinitialized internally when going from PCI_D3hot to
3838 * PCI_D0. If that's the case and the device is not in a low-power state
3839 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
3840 *
3841 * NOTE: This causes the caller to sleep for twice the device power transition
3842 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
Bjorn Helgaasf7625982013-11-14 11:28:18 -07003843 * by default (i.e. unless the @dev's d3_delay field has a different value).
Rafael J. Wysocki83d74e02011-03-05 21:48:44 +01003844 * Moreover, only devices in D0 can be reset by this function.
3845 */
Yu Zhaof85876b2009-06-13 15:52:14 +08003846static int pci_pm_reset(struct pci_dev *dev, int probe)
Sheng Yangd91cdc72008-11-11 17:17:47 +08003847{
Yu Zhaof85876b2009-06-13 15:52:14 +08003848 u16 csr;
Sheng Yangd91cdc72008-11-11 17:17:47 +08003849
Alex Williamson51e53732014-11-21 11:24:08 -07003850 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET)
Yu Zhaof85876b2009-06-13 15:52:14 +08003851 return -ENOTTY;
Sheng Yangd91cdc72008-11-11 17:17:47 +08003852
Yu Zhaof85876b2009-06-13 15:52:14 +08003853 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr);
3854 if (csr & PCI_PM_CTRL_NO_SOFT_RESET)
3855 return -ENOTTY;
Sheng Yang1ca88792008-11-11 17:17:48 +08003856
Yu Zhaof85876b2009-06-13 15:52:14 +08003857 if (probe)
3858 return 0;
3859
3860 if (dev->current_state != PCI_D0)
3861 return -EINVAL;
3862
3863 csr &= ~PCI_PM_CTRL_STATE_MASK;
3864 csr |= PCI_D3hot;
3865 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +01003866 pci_dev_d3_sleep(dev);
Yu Zhaof85876b2009-06-13 15:52:14 +08003867
3868 csr &= ~PCI_PM_CTRL_STATE_MASK;
3869 csr |= PCI_D0;
3870 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr);
Rafael J. Wysocki1ae861e2009-12-31 12:15:54 +01003871 pci_dev_d3_sleep(dev);
Yu Zhaof85876b2009-06-13 15:52:14 +08003872
3873 return 0;
3874}
3875
Gavin Shan9e330022014-06-19 17:22:44 +10003876void pci_reset_secondary_bus(struct pci_dev *dev)
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08003877{
3878 u16 ctrl;
Alex Williamson64e86742013-08-08 14:09:24 -06003879
3880 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &ctrl);
3881 ctrl |= PCI_BRIDGE_CTL_BUS_RESET;
3882 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
Alex Williamsonde0c5482013-08-08 14:10:13 -06003883 /*
3884 * PCI spec v3.0 7.6.4.2 requires minimum Trst of 1ms. Double
Bjorn Helgaasf7625982013-11-14 11:28:18 -07003885 * this to 2ms to ensure that we meet the minimum requirement.
Alex Williamsonde0c5482013-08-08 14:10:13 -06003886 */
3887 msleep(2);
Alex Williamson64e86742013-08-08 14:09:24 -06003888
3889 ctrl &= ~PCI_BRIDGE_CTL_BUS_RESET;
3890 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, ctrl);
Alex Williamsonde0c5482013-08-08 14:10:13 -06003891
3892 /*
3893 * Trhfa for conventional PCI is 2^25 clock cycles.
3894 * Assuming a minimum 33MHz clock this results in a 1s
3895 * delay before we can consider subordinate devices to
3896 * be re-initialized. PCIe has some ways to shorten this,
3897 * but we don't make use of them yet.
3898 */
3899 ssleep(1);
Alex Williamson64e86742013-08-08 14:09:24 -06003900}
Gavin Shand92a2082014-04-24 18:00:24 +10003901
Gavin Shan9e330022014-06-19 17:22:44 +10003902void __weak pcibios_reset_secondary_bus(struct pci_dev *dev)
3903{
3904 pci_reset_secondary_bus(dev);
3905}
3906
Gavin Shand92a2082014-04-24 18:00:24 +10003907/**
3908 * pci_reset_bridge_secondary_bus - Reset the secondary bus on a PCI bridge.
3909 * @dev: Bridge device
3910 *
3911 * Use the bridge control register to assert reset on the secondary bus.
3912 * Devices on the secondary bus are left in power-on state.
3913 */
3914void pci_reset_bridge_secondary_bus(struct pci_dev *dev)
3915{
3916 pcibios_reset_secondary_bus(dev);
3917}
Alex Williamson64e86742013-08-08 14:09:24 -06003918EXPORT_SYMBOL_GPL(pci_reset_bridge_secondary_bus);
3919
3920static int pci_parent_bus_reset(struct pci_dev *dev, int probe)
3921{
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08003922 struct pci_dev *pdev;
3923
Alex Williamsonf331a852015-01-15 18:16:04 -06003924 if (pci_is_root_bus(dev->bus) || dev->subordinate ||
3925 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08003926 return -ENOTTY;
3927
3928 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3929 if (pdev != dev)
3930 return -ENOTTY;
3931
3932 if (probe)
3933 return 0;
3934
Alex Williamson64e86742013-08-08 14:09:24 -06003935 pci_reset_bridge_secondary_bus(dev->bus->self);
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08003936
3937 return 0;
3938}
3939
Alex Williamson608c3882013-08-08 14:09:43 -06003940static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, int probe)
3941{
3942 int rc = -ENOTTY;
3943
3944 if (!hotplug || !try_module_get(hotplug->ops->owner))
3945 return rc;
3946
3947 if (hotplug->ops->reset_slot)
3948 rc = hotplug->ops->reset_slot(hotplug, probe);
3949
3950 module_put(hotplug->ops->owner);
3951
3952 return rc;
3953}
3954
3955static int pci_dev_reset_slot_function(struct pci_dev *dev, int probe)
3956{
3957 struct pci_dev *pdev;
3958
Alex Williamsonf331a852015-01-15 18:16:04 -06003959 if (dev->subordinate || !dev->slot ||
3960 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)
Alex Williamson608c3882013-08-08 14:09:43 -06003961 return -ENOTTY;
3962
3963 list_for_each_entry(pdev, &dev->bus->devices, bus_list)
3964 if (pdev != dev && pdev->slot == dev->slot)
3965 return -ENOTTY;
3966
3967 return pci_reset_hotplug_slot(dev->slot->hotplug, probe);
3968}
3969
Konrad Rzeszutek Wilk977f8572012-04-24 13:15:18 -06003970static int __pci_dev_reset(struct pci_dev *dev, int probe)
Sheng Yang8dd7f802008-10-21 17:38:25 +08003971{
Yu Zhao8c1c6992009-06-13 15:52:13 +08003972 int rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08003973
Yu Zhao8c1c6992009-06-13 15:52:13 +08003974 might_sleep();
Sheng Yang8dd7f802008-10-21 17:38:25 +08003975
Dexuan Cuib9c3b262009-12-07 13:03:21 +08003976 rc = pci_dev_specific_reset(dev, probe);
3977 if (rc != -ENOTTY)
3978 goto done;
3979
Yu Zhao8c1c6992009-06-13 15:52:13 +08003980 rc = pcie_flr(dev, probe);
3981 if (rc != -ENOTTY)
3982 goto done;
3983
3984 rc = pci_af_flr(dev, probe);
Yu Zhaof85876b2009-06-13 15:52:14 +08003985 if (rc != -ENOTTY)
3986 goto done;
3987
3988 rc = pci_pm_reset(dev, probe);
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08003989 if (rc != -ENOTTY)
3990 goto done;
3991
Alex Williamson608c3882013-08-08 14:09:43 -06003992 rc = pci_dev_reset_slot_function(dev, probe);
3993 if (rc != -ENOTTY)
3994 goto done;
3995
Yu Zhaoc12ff1d2009-06-13 15:52:15 +08003996 rc = pci_parent_bus_reset(dev, probe);
Yu Zhao8c1c6992009-06-13 15:52:13 +08003997done:
Konrad Rzeszutek Wilk977f8572012-04-24 13:15:18 -06003998 return rc;
3999}
4000
Alex Williamson77cb9852013-08-08 14:09:49 -06004001static void pci_dev_lock(struct pci_dev *dev)
4002{
4003 pci_cfg_access_lock(dev);
4004 /* block PM suspend, driver probe, etc. */
4005 device_lock(&dev->dev);
4006}
4007
Alex Williamson61cf16d2013-12-16 15:14:31 -07004008/* Return 1 on successful lock, 0 on contention */
4009static int pci_dev_trylock(struct pci_dev *dev)
4010{
4011 if (pci_cfg_access_trylock(dev)) {
4012 if (device_trylock(&dev->dev))
4013 return 1;
4014 pci_cfg_access_unlock(dev);
4015 }
4016
4017 return 0;
4018}
4019
Alex Williamson77cb9852013-08-08 14:09:49 -06004020static void pci_dev_unlock(struct pci_dev *dev)
4021{
4022 device_unlock(&dev->dev);
4023 pci_cfg_access_unlock(dev);
4024}
4025
Keith Busch3ebe7f92014-05-02 10:40:42 -06004026/**
4027 * pci_reset_notify - notify device driver of reset
4028 * @dev: device to be notified of reset
4029 * @prepare: 'true' if device is about to be reset; 'false' if reset attempt
4030 * completed
4031 *
4032 * Must be called prior to device access being disabled and after device
4033 * access is restored.
4034 */
4035static void pci_reset_notify(struct pci_dev *dev, bool prepare)
4036{
4037 const struct pci_error_handlers *err_handler =
4038 dev->driver ? dev->driver->err_handler : NULL;
4039 if (err_handler && err_handler->reset_notify)
4040 err_handler->reset_notify(dev, prepare);
4041}
4042
Alex Williamson77cb9852013-08-08 14:09:49 -06004043static void pci_dev_save_and_disable(struct pci_dev *dev)
4044{
Keith Busch3ebe7f92014-05-02 10:40:42 -06004045 pci_reset_notify(dev, true);
4046
Alex Williamsona6cbaad2013-08-08 14:10:02 -06004047 /*
4048 * Wake-up device prior to save. PM registers default to D0 after
4049 * reset and a simple register restore doesn't reliably return
4050 * to a non-D0 state anyway.
4051 */
4052 pci_set_power_state(dev, PCI_D0);
4053
Alex Williamson77cb9852013-08-08 14:09:49 -06004054 pci_save_state(dev);
4055 /*
4056 * Disable the device by clearing the Command register, except for
4057 * INTx-disable which is set. This not only disables MMIO and I/O port
4058 * BARs, but also prevents the device from being Bus Master, preventing
4059 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3
4060 * compliant devices, INTx-disable prevents legacy interrupts.
4061 */
4062 pci_write_config_word(dev, PCI_COMMAND, PCI_COMMAND_INTX_DISABLE);
4063}
4064
4065static void pci_dev_restore(struct pci_dev *dev)
4066{
4067 pci_restore_state(dev);
Keith Busch3ebe7f92014-05-02 10:40:42 -06004068 pci_reset_notify(dev, false);
Alex Williamson77cb9852013-08-08 14:09:49 -06004069}
4070
Konrad Rzeszutek Wilk977f8572012-04-24 13:15:18 -06004071static int pci_dev_reset(struct pci_dev *dev, int probe)
4072{
4073 int rc;
4074
Alex Williamson77cb9852013-08-08 14:09:49 -06004075 if (!probe)
4076 pci_dev_lock(dev);
Konrad Rzeszutek Wilk977f8572012-04-24 13:15:18 -06004077
4078 rc = __pci_dev_reset(dev, probe);
4079
Alex Williamson77cb9852013-08-08 14:09:49 -06004080 if (!probe)
4081 pci_dev_unlock(dev);
4082
Yu Zhao8c1c6992009-06-13 15:52:13 +08004083 return rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08004084}
Keith Busch3ebe7f92014-05-02 10:40:42 -06004085
Sheng Yang8dd7f802008-10-21 17:38:25 +08004086/**
Yu Zhao8c1c6992009-06-13 15:52:13 +08004087 * __pci_reset_function - reset a PCI device function
4088 * @dev: PCI device to reset
Sheng Yang8dd7f802008-10-21 17:38:25 +08004089 *
4090 * Some devices allow an individual function to be reset without affecting
4091 * other functions in the same device. The PCI device must be responsive
4092 * to PCI config space in order to use this function.
4093 *
4094 * The device function is presumed to be unused when this function is called.
4095 * Resetting the device will make the contents of PCI configuration space
4096 * random, so any caller of this must be prepared to reinitialise the
4097 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4098 * etc.
4099 *
Yu Zhao8c1c6992009-06-13 15:52:13 +08004100 * Returns 0 if the device function was successfully reset or negative if the
Sheng Yang8dd7f802008-10-21 17:38:25 +08004101 * device doesn't support resetting a single function.
4102 */
Yu Zhao8c1c6992009-06-13 15:52:13 +08004103int __pci_reset_function(struct pci_dev *dev)
Sheng Yang8dd7f802008-10-21 17:38:25 +08004104{
Yu Zhao8c1c6992009-06-13 15:52:13 +08004105 return pci_dev_reset(dev, 0);
Sheng Yang8dd7f802008-10-21 17:38:25 +08004106}
Yu Zhao8c1c6992009-06-13 15:52:13 +08004107EXPORT_SYMBOL_GPL(__pci_reset_function);
Sheng Yang8dd7f802008-10-21 17:38:25 +08004108
4109/**
Konrad Rzeszutek Wilk6fbf9e72012-01-12 12:06:46 -05004110 * __pci_reset_function_locked - reset a PCI device function while holding
4111 * the @dev mutex lock.
4112 * @dev: PCI device to reset
4113 *
4114 * Some devices allow an individual function to be reset without affecting
4115 * other functions in the same device. The PCI device must be responsive
4116 * to PCI config space in order to use this function.
4117 *
4118 * The device function is presumed to be unused and the caller is holding
4119 * the device mutex lock when this function is called.
4120 * Resetting the device will make the contents of PCI configuration space
4121 * random, so any caller of this must be prepared to reinitialise the
4122 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
4123 * etc.
4124 *
4125 * Returns 0 if the device function was successfully reset or negative if the
4126 * device doesn't support resetting a single function.
4127 */
4128int __pci_reset_function_locked(struct pci_dev *dev)
4129{
Konrad Rzeszutek Wilk977f8572012-04-24 13:15:18 -06004130 return __pci_dev_reset(dev, 0);
Konrad Rzeszutek Wilk6fbf9e72012-01-12 12:06:46 -05004131}
4132EXPORT_SYMBOL_GPL(__pci_reset_function_locked);
4133
4134/**
Michael S. Tsirkin711d5772009-07-27 23:37:48 +03004135 * pci_probe_reset_function - check whether the device can be safely reset
4136 * @dev: PCI device to reset
4137 *
4138 * Some devices allow an individual function to be reset without affecting
4139 * other functions in the same device. The PCI device must be responsive
4140 * to PCI config space in order to use this function.
4141 *
4142 * Returns 0 if the device function can be reset or negative if the
4143 * device doesn't support resetting a single function.
4144 */
4145int pci_probe_reset_function(struct pci_dev *dev)
4146{
4147 return pci_dev_reset(dev, 1);
4148}
4149
4150/**
Yu Zhao8c1c6992009-06-13 15:52:13 +08004151 * pci_reset_function - quiesce and reset a PCI device function
4152 * @dev: PCI device to reset
Sheng Yang8dd7f802008-10-21 17:38:25 +08004153 *
4154 * Some devices allow an individual function to be reset without affecting
4155 * other functions in the same device. The PCI device must be responsive
4156 * to PCI config space in order to use this function.
4157 *
4158 * This function does not just reset the PCI portion of a device, but
4159 * clears all the state associated with the device. This function differs
Yu Zhao8c1c6992009-06-13 15:52:13 +08004160 * from __pci_reset_function in that it saves and restores device state
Sheng Yang8dd7f802008-10-21 17:38:25 +08004161 * over the reset.
4162 *
Yu Zhao8c1c6992009-06-13 15:52:13 +08004163 * Returns 0 if the device function was successfully reset or negative if the
Sheng Yang8dd7f802008-10-21 17:38:25 +08004164 * device doesn't support resetting a single function.
4165 */
4166int pci_reset_function(struct pci_dev *dev)
4167{
Yu Zhao8c1c6992009-06-13 15:52:13 +08004168 int rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08004169
Yu Zhao8c1c6992009-06-13 15:52:13 +08004170 rc = pci_dev_reset(dev, 1);
4171 if (rc)
4172 return rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08004173
Alex Williamson77cb9852013-08-08 14:09:49 -06004174 pci_dev_save_and_disable(dev);
Sheng Yang8dd7f802008-10-21 17:38:25 +08004175
Yu Zhao8c1c6992009-06-13 15:52:13 +08004176 rc = pci_dev_reset(dev, 0);
Sheng Yang8dd7f802008-10-21 17:38:25 +08004177
Alex Williamson77cb9852013-08-08 14:09:49 -06004178 pci_dev_restore(dev);
Sheng Yang8dd7f802008-10-21 17:38:25 +08004179
Yu Zhao8c1c6992009-06-13 15:52:13 +08004180 return rc;
Sheng Yang8dd7f802008-10-21 17:38:25 +08004181}
4182EXPORT_SYMBOL_GPL(pci_reset_function);
4183
Alex Williamson61cf16d2013-12-16 15:14:31 -07004184/**
4185 * pci_try_reset_function - quiesce and reset a PCI device function
4186 * @dev: PCI device to reset
4187 *
4188 * Same as above, except return -EAGAIN if unable to lock device.
4189 */
4190int pci_try_reset_function(struct pci_dev *dev)
4191{
4192 int rc;
4193
4194 rc = pci_dev_reset(dev, 1);
4195 if (rc)
4196 return rc;
4197
4198 pci_dev_save_and_disable(dev);
4199
4200 if (pci_dev_trylock(dev)) {
4201 rc = __pci_dev_reset(dev, 0);
4202 pci_dev_unlock(dev);
4203 } else
4204 rc = -EAGAIN;
4205
4206 pci_dev_restore(dev);
4207
4208 return rc;
4209}
4210EXPORT_SYMBOL_GPL(pci_try_reset_function);
4211
Alex Williamsonf331a852015-01-15 18:16:04 -06004212/* Do any devices on or below this bus prevent a bus reset? */
4213static bool pci_bus_resetable(struct pci_bus *bus)
4214{
4215 struct pci_dev *dev;
4216
4217 list_for_each_entry(dev, &bus->devices, bus_list) {
4218 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4219 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4220 return false;
4221 }
4222
4223 return true;
4224}
4225
Alex Williamson090a3c52013-08-08 14:09:55 -06004226/* Lock devices from the top of the tree down */
4227static void pci_bus_lock(struct pci_bus *bus)
4228{
4229 struct pci_dev *dev;
4230
4231 list_for_each_entry(dev, &bus->devices, bus_list) {
4232 pci_dev_lock(dev);
4233 if (dev->subordinate)
4234 pci_bus_lock(dev->subordinate);
4235 }
4236}
4237
4238/* Unlock devices from the bottom of the tree up */
4239static void pci_bus_unlock(struct pci_bus *bus)
4240{
4241 struct pci_dev *dev;
4242
4243 list_for_each_entry(dev, &bus->devices, bus_list) {
4244 if (dev->subordinate)
4245 pci_bus_unlock(dev->subordinate);
4246 pci_dev_unlock(dev);
4247 }
4248}
4249
Alex Williamson61cf16d2013-12-16 15:14:31 -07004250/* Return 1 on successful lock, 0 on contention */
4251static int pci_bus_trylock(struct pci_bus *bus)
4252{
4253 struct pci_dev *dev;
4254
4255 list_for_each_entry(dev, &bus->devices, bus_list) {
4256 if (!pci_dev_trylock(dev))
4257 goto unlock;
4258 if (dev->subordinate) {
4259 if (!pci_bus_trylock(dev->subordinate)) {
4260 pci_dev_unlock(dev);
4261 goto unlock;
4262 }
4263 }
4264 }
4265 return 1;
4266
4267unlock:
4268 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) {
4269 if (dev->subordinate)
4270 pci_bus_unlock(dev->subordinate);
4271 pci_dev_unlock(dev);
4272 }
4273 return 0;
4274}
4275
Alex Williamsonf331a852015-01-15 18:16:04 -06004276/* Do any devices on or below this slot prevent a bus reset? */
4277static bool pci_slot_resetable(struct pci_slot *slot)
4278{
4279 struct pci_dev *dev;
4280
4281 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4282 if (!dev->slot || dev->slot != slot)
4283 continue;
4284 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET ||
4285 (dev->subordinate && !pci_bus_resetable(dev->subordinate)))
4286 return false;
4287 }
4288
4289 return true;
4290}
4291
Alex Williamson090a3c52013-08-08 14:09:55 -06004292/* Lock devices from the top of the tree down */
4293static void pci_slot_lock(struct pci_slot *slot)
4294{
4295 struct pci_dev *dev;
4296
4297 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4298 if (!dev->slot || dev->slot != slot)
4299 continue;
4300 pci_dev_lock(dev);
4301 if (dev->subordinate)
4302 pci_bus_lock(dev->subordinate);
4303 }
4304}
4305
4306/* Unlock devices from the bottom of the tree up */
4307static void pci_slot_unlock(struct pci_slot *slot)
4308{
4309 struct pci_dev *dev;
4310
4311 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4312 if (!dev->slot || dev->slot != slot)
4313 continue;
4314 if (dev->subordinate)
4315 pci_bus_unlock(dev->subordinate);
4316 pci_dev_unlock(dev);
4317 }
4318}
4319
Alex Williamson61cf16d2013-12-16 15:14:31 -07004320/* Return 1 on successful lock, 0 on contention */
4321static int pci_slot_trylock(struct pci_slot *slot)
4322{
4323 struct pci_dev *dev;
4324
4325 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4326 if (!dev->slot || dev->slot != slot)
4327 continue;
4328 if (!pci_dev_trylock(dev))
4329 goto unlock;
4330 if (dev->subordinate) {
4331 if (!pci_bus_trylock(dev->subordinate)) {
4332 pci_dev_unlock(dev);
4333 goto unlock;
4334 }
4335 }
4336 }
4337 return 1;
4338
4339unlock:
4340 list_for_each_entry_continue_reverse(dev,
4341 &slot->bus->devices, bus_list) {
4342 if (!dev->slot || dev->slot != slot)
4343 continue;
4344 if (dev->subordinate)
4345 pci_bus_unlock(dev->subordinate);
4346 pci_dev_unlock(dev);
4347 }
4348 return 0;
4349}
4350
Alex Williamson090a3c52013-08-08 14:09:55 -06004351/* Save and disable devices from the top of the tree down */
4352static void pci_bus_save_and_disable(struct pci_bus *bus)
4353{
4354 struct pci_dev *dev;
4355
4356 list_for_each_entry(dev, &bus->devices, bus_list) {
4357 pci_dev_save_and_disable(dev);
4358 if (dev->subordinate)
4359 pci_bus_save_and_disable(dev->subordinate);
4360 }
4361}
4362
4363/*
4364 * Restore devices from top of the tree down - parent bridges need to be
4365 * restored before we can get to subordinate devices.
4366 */
4367static void pci_bus_restore(struct pci_bus *bus)
4368{
4369 struct pci_dev *dev;
4370
4371 list_for_each_entry(dev, &bus->devices, bus_list) {
4372 pci_dev_restore(dev);
4373 if (dev->subordinate)
4374 pci_bus_restore(dev->subordinate);
4375 }
4376}
4377
4378/* Save and disable devices from the top of the tree down */
4379static void pci_slot_save_and_disable(struct pci_slot *slot)
4380{
4381 struct pci_dev *dev;
4382
4383 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4384 if (!dev->slot || dev->slot != slot)
4385 continue;
4386 pci_dev_save_and_disable(dev);
4387 if (dev->subordinate)
4388 pci_bus_save_and_disable(dev->subordinate);
4389 }
4390}
4391
4392/*
4393 * Restore devices from top of the tree down - parent bridges need to be
4394 * restored before we can get to subordinate devices.
4395 */
4396static void pci_slot_restore(struct pci_slot *slot)
4397{
4398 struct pci_dev *dev;
4399
4400 list_for_each_entry(dev, &slot->bus->devices, bus_list) {
4401 if (!dev->slot || dev->slot != slot)
4402 continue;
4403 pci_dev_restore(dev);
4404 if (dev->subordinate)
4405 pci_bus_restore(dev->subordinate);
4406 }
4407}
4408
4409static int pci_slot_reset(struct pci_slot *slot, int probe)
4410{
4411 int rc;
4412
Alex Williamsonf331a852015-01-15 18:16:04 -06004413 if (!slot || !pci_slot_resetable(slot))
Alex Williamson090a3c52013-08-08 14:09:55 -06004414 return -ENOTTY;
4415
4416 if (!probe)
4417 pci_slot_lock(slot);
4418
4419 might_sleep();
4420
4421 rc = pci_reset_hotplug_slot(slot->hotplug, probe);
4422
4423 if (!probe)
4424 pci_slot_unlock(slot);
4425
4426 return rc;
4427}
4428
4429/**
Alex Williamson9a3d2b92013-08-14 14:06:05 -06004430 * pci_probe_reset_slot - probe whether a PCI slot can be reset
4431 * @slot: PCI slot to probe
4432 *
4433 * Return 0 if slot can be reset, negative if a slot reset is not supported.
4434 */
4435int pci_probe_reset_slot(struct pci_slot *slot)
4436{
4437 return pci_slot_reset(slot, 1);
4438}
4439EXPORT_SYMBOL_GPL(pci_probe_reset_slot);
4440
4441/**
Alex Williamson090a3c52013-08-08 14:09:55 -06004442 * pci_reset_slot - reset a PCI slot
4443 * @slot: PCI slot to reset
4444 *
4445 * A PCI bus may host multiple slots, each slot may support a reset mechanism
4446 * independent of other slots. For instance, some slots may support slot power
4447 * control. In the case of a 1:1 bus to slot architecture, this function may
4448 * wrap the bus reset to avoid spurious slot related events such as hotplug.
4449 * Generally a slot reset should be attempted before a bus reset. All of the
4450 * function of the slot and any subordinate buses behind the slot are reset
4451 * through this function. PCI config space of all devices in the slot and
4452 * behind the slot is saved before and restored after reset.
4453 *
4454 * Return 0 on success, non-zero on error.
4455 */
4456int pci_reset_slot(struct pci_slot *slot)
4457{
4458 int rc;
4459
4460 rc = pci_slot_reset(slot, 1);
4461 if (rc)
4462 return rc;
4463
4464 pci_slot_save_and_disable(slot);
4465
4466 rc = pci_slot_reset(slot, 0);
4467
4468 pci_slot_restore(slot);
4469
4470 return rc;
4471}
4472EXPORT_SYMBOL_GPL(pci_reset_slot);
4473
Alex Williamson61cf16d2013-12-16 15:14:31 -07004474/**
4475 * pci_try_reset_slot - Try to reset a PCI slot
4476 * @slot: PCI slot to reset
4477 *
4478 * Same as above except return -EAGAIN if the slot cannot be locked
4479 */
4480int pci_try_reset_slot(struct pci_slot *slot)
4481{
4482 int rc;
4483
4484 rc = pci_slot_reset(slot, 1);
4485 if (rc)
4486 return rc;
4487
4488 pci_slot_save_and_disable(slot);
4489
4490 if (pci_slot_trylock(slot)) {
4491 might_sleep();
4492 rc = pci_reset_hotplug_slot(slot->hotplug, 0);
4493 pci_slot_unlock(slot);
4494 } else
4495 rc = -EAGAIN;
4496
4497 pci_slot_restore(slot);
4498
4499 return rc;
4500}
4501EXPORT_SYMBOL_GPL(pci_try_reset_slot);
4502
Alex Williamson090a3c52013-08-08 14:09:55 -06004503static int pci_bus_reset(struct pci_bus *bus, int probe)
4504{
Alex Williamsonf331a852015-01-15 18:16:04 -06004505 if (!bus->self || !pci_bus_resetable(bus))
Alex Williamson090a3c52013-08-08 14:09:55 -06004506 return -ENOTTY;
4507
4508 if (probe)
4509 return 0;
4510
4511 pci_bus_lock(bus);
4512
4513 might_sleep();
4514
4515 pci_reset_bridge_secondary_bus(bus->self);
4516
4517 pci_bus_unlock(bus);
4518
4519 return 0;
4520}
4521
4522/**
Alex Williamson9a3d2b92013-08-14 14:06:05 -06004523 * pci_probe_reset_bus - probe whether a PCI bus can be reset
4524 * @bus: PCI bus to probe
4525 *
4526 * Return 0 if bus can be reset, negative if a bus reset is not supported.
4527 */
4528int pci_probe_reset_bus(struct pci_bus *bus)
4529{
4530 return pci_bus_reset(bus, 1);
4531}
4532EXPORT_SYMBOL_GPL(pci_probe_reset_bus);
4533
4534/**
Alex Williamson090a3c52013-08-08 14:09:55 -06004535 * pci_reset_bus - reset a PCI bus
4536 * @bus: top level PCI bus to reset
4537 *
4538 * Do a bus reset on the given bus and any subordinate buses, saving
4539 * and restoring state of all devices.
4540 *
4541 * Return 0 on success, non-zero on error.
4542 */
4543int pci_reset_bus(struct pci_bus *bus)
4544{
4545 int rc;
4546
4547 rc = pci_bus_reset(bus, 1);
4548 if (rc)
4549 return rc;
4550
4551 pci_bus_save_and_disable(bus);
4552
4553 rc = pci_bus_reset(bus, 0);
4554
4555 pci_bus_restore(bus);
4556
4557 return rc;
4558}
4559EXPORT_SYMBOL_GPL(pci_reset_bus);
4560
Sheng Yang8dd7f802008-10-21 17:38:25 +08004561/**
Alex Williamson61cf16d2013-12-16 15:14:31 -07004562 * pci_try_reset_bus - Try to reset a PCI bus
4563 * @bus: top level PCI bus to reset
4564 *
4565 * Same as above except return -EAGAIN if the bus cannot be locked
4566 */
4567int pci_try_reset_bus(struct pci_bus *bus)
4568{
4569 int rc;
4570
4571 rc = pci_bus_reset(bus, 1);
4572 if (rc)
4573 return rc;
4574
4575 pci_bus_save_and_disable(bus);
4576
4577 if (pci_bus_trylock(bus)) {
4578 might_sleep();
4579 pci_reset_bridge_secondary_bus(bus->self);
4580 pci_bus_unlock(bus);
4581 } else
4582 rc = -EAGAIN;
4583
4584 pci_bus_restore(bus);
4585
4586 return rc;
4587}
4588EXPORT_SYMBOL_GPL(pci_try_reset_bus);
4589
4590/**
Peter Orubad556ad42007-05-15 13:59:13 +02004591 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
4592 * @dev: PCI device to query
4593 *
4594 * Returns mmrbc: maximum designed memory read count in bytes
4595 * or appropriate error value.
4596 */
4597int pcix_get_max_mmrbc(struct pci_dev *dev)
4598{
Dean Nelson7c9e2b12010-03-09 22:26:55 -05004599 int cap;
Peter Orubad556ad42007-05-15 13:59:13 +02004600 u32 stat;
4601
4602 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4603 if (!cap)
4604 return -EINVAL;
4605
Dean Nelson7c9e2b12010-03-09 22:26:55 -05004606 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
Peter Orubad556ad42007-05-15 13:59:13 +02004607 return -EINVAL;
4608
Dean Nelson25daeb52010-03-09 22:26:40 -05004609 return 512 << ((stat & PCI_X_STATUS_MAX_READ) >> 21);
Peter Orubad556ad42007-05-15 13:59:13 +02004610}
4611EXPORT_SYMBOL(pcix_get_max_mmrbc);
4612
4613/**
4614 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
4615 * @dev: PCI device to query
4616 *
4617 * Returns mmrbc: maximum memory read count in bytes
4618 * or appropriate error value.
4619 */
4620int pcix_get_mmrbc(struct pci_dev *dev)
4621{
Dean Nelson7c9e2b12010-03-09 22:26:55 -05004622 int cap;
Dean Nelsonbdc2bda2010-03-09 22:26:48 -05004623 u16 cmd;
Peter Orubad556ad42007-05-15 13:59:13 +02004624
4625 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4626 if (!cap)
4627 return -EINVAL;
4628
Dean Nelson7c9e2b12010-03-09 22:26:55 -05004629 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4630 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02004631
Dean Nelson7c9e2b12010-03-09 22:26:55 -05004632 return 512 << ((cmd & PCI_X_CMD_MAX_READ) >> 2);
Peter Orubad556ad42007-05-15 13:59:13 +02004633}
4634EXPORT_SYMBOL(pcix_get_mmrbc);
4635
4636/**
4637 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
4638 * @dev: PCI device to query
4639 * @mmrbc: maximum memory read count in bytes
4640 * valid values are 512, 1024, 2048, 4096
4641 *
4642 * If possible sets maximum memory read byte count, some bridges have erratas
4643 * that prevent this.
4644 */
4645int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc)
4646{
Dean Nelson7c9e2b12010-03-09 22:26:55 -05004647 int cap;
Dean Nelsonbdc2bda2010-03-09 22:26:48 -05004648 u32 stat, v, o;
4649 u16 cmd;
Peter Orubad556ad42007-05-15 13:59:13 +02004650
vignesh babu229f5af2007-08-13 18:23:14 +05304651 if (mmrbc < 512 || mmrbc > 4096 || !is_power_of_2(mmrbc))
Dean Nelson7c9e2b12010-03-09 22:26:55 -05004652 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02004653
4654 v = ffs(mmrbc) - 10;
4655
4656 cap = pci_find_capability(dev, PCI_CAP_ID_PCIX);
4657 if (!cap)
Dean Nelson7c9e2b12010-03-09 22:26:55 -05004658 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02004659
Dean Nelson7c9e2b12010-03-09 22:26:55 -05004660 if (pci_read_config_dword(dev, cap + PCI_X_STATUS, &stat))
4661 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02004662
4663 if (v > (stat & PCI_X_STATUS_MAX_READ) >> 21)
4664 return -E2BIG;
4665
Dean Nelson7c9e2b12010-03-09 22:26:55 -05004666 if (pci_read_config_word(dev, cap + PCI_X_CMD, &cmd))
4667 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02004668
4669 o = (cmd & PCI_X_CMD_MAX_READ) >> 2;
4670 if (o != v) {
Bjorn Helgaas809a3bf2012-06-20 16:41:16 -06004671 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC))
Peter Orubad556ad42007-05-15 13:59:13 +02004672 return -EIO;
4673
4674 cmd &= ~PCI_X_CMD_MAX_READ;
4675 cmd |= v << 2;
Dean Nelson7c9e2b12010-03-09 22:26:55 -05004676 if (pci_write_config_word(dev, cap + PCI_X_CMD, cmd))
4677 return -EIO;
Peter Orubad556ad42007-05-15 13:59:13 +02004678 }
Dean Nelson7c9e2b12010-03-09 22:26:55 -05004679 return 0;
Peter Orubad556ad42007-05-15 13:59:13 +02004680}
4681EXPORT_SYMBOL(pcix_set_mmrbc);
4682
4683/**
4684 * pcie_get_readrq - get PCI Express read request size
4685 * @dev: PCI device to query
4686 *
4687 * Returns maximum memory read request in bytes
4688 * or appropriate error value.
4689 */
4690int pcie_get_readrq(struct pci_dev *dev)
4691{
Peter Orubad556ad42007-05-15 13:59:13 +02004692 u16 ctl;
4693
Jiang Liu59875ae2012-07-24 17:20:06 +08004694 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
Peter Orubad556ad42007-05-15 13:59:13 +02004695
Jiang Liu59875ae2012-07-24 17:20:06 +08004696 return 128 << ((ctl & PCI_EXP_DEVCTL_READRQ) >> 12);
Peter Orubad556ad42007-05-15 13:59:13 +02004697}
4698EXPORT_SYMBOL(pcie_get_readrq);
4699
4700/**
4701 * pcie_set_readrq - set PCI Express maximum memory read request
4702 * @dev: PCI device to query
Randy Dunlap42e61f42007-07-23 21:42:11 -07004703 * @rq: maximum memory read count in bytes
Peter Orubad556ad42007-05-15 13:59:13 +02004704 * valid values are 128, 256, 512, 1024, 2048, 4096
4705 *
Jon Masonc9b378c2011-06-28 18:26:25 -05004706 * If possible sets maximum memory read request in bytes
Peter Orubad556ad42007-05-15 13:59:13 +02004707 */
4708int pcie_set_readrq(struct pci_dev *dev, int rq)
4709{
Jiang Liu59875ae2012-07-24 17:20:06 +08004710 u16 v;
Peter Orubad556ad42007-05-15 13:59:13 +02004711
vignesh babu229f5af2007-08-13 18:23:14 +05304712 if (rq < 128 || rq > 4096 || !is_power_of_2(rq))
Jiang Liu59875ae2012-07-24 17:20:06 +08004713 return -EINVAL;
Peter Orubad556ad42007-05-15 13:59:13 +02004714
Benjamin Herrenschmidta1c473a2011-10-14 14:56:15 -05004715 /*
4716 * If using the "performance" PCIe config, we clamp the
4717 * read rq size to the max packet size to prevent the
4718 * host bridge generating requests larger than we can
4719 * cope with
4720 */
4721 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
4722 int mps = pcie_get_mps(dev);
4723
Benjamin Herrenschmidta1c473a2011-10-14 14:56:15 -05004724 if (mps < rq)
4725 rq = mps;
4726 }
4727
4728 v = (ffs(rq) - 8) << 12;
Peter Orubad556ad42007-05-15 13:59:13 +02004729
Jiang Liu59875ae2012-07-24 17:20:06 +08004730 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4731 PCI_EXP_DEVCTL_READRQ, v);
Peter Orubad556ad42007-05-15 13:59:13 +02004732}
4733EXPORT_SYMBOL(pcie_set_readrq);
4734
4735/**
Jon Masonb03e7492011-07-20 15:20:54 -05004736 * pcie_get_mps - get PCI Express maximum payload size
4737 * @dev: PCI device to query
4738 *
4739 * Returns maximum payload size in bytes
Jon Masonb03e7492011-07-20 15:20:54 -05004740 */
4741int pcie_get_mps(struct pci_dev *dev)
4742{
Jon Masonb03e7492011-07-20 15:20:54 -05004743 u16 ctl;
4744
Jiang Liu59875ae2012-07-24 17:20:06 +08004745 pcie_capability_read_word(dev, PCI_EXP_DEVCTL, &ctl);
Jon Masonb03e7492011-07-20 15:20:54 -05004746
Jiang Liu59875ae2012-07-24 17:20:06 +08004747 return 128 << ((ctl & PCI_EXP_DEVCTL_PAYLOAD) >> 5);
Jon Masonb03e7492011-07-20 15:20:54 -05004748}
Yijing Wangf1c66c42013-09-24 12:08:06 -06004749EXPORT_SYMBOL(pcie_get_mps);
Jon Masonb03e7492011-07-20 15:20:54 -05004750
4751/**
4752 * pcie_set_mps - set PCI Express maximum payload size
4753 * @dev: PCI device to query
Randy Dunlap47c08f32011-08-20 11:49:43 -07004754 * @mps: maximum payload size in bytes
Jon Masonb03e7492011-07-20 15:20:54 -05004755 * valid values are 128, 256, 512, 1024, 2048, 4096
4756 *
4757 * If possible sets maximum payload size
4758 */
4759int pcie_set_mps(struct pci_dev *dev, int mps)
4760{
Jiang Liu59875ae2012-07-24 17:20:06 +08004761 u16 v;
Jon Masonb03e7492011-07-20 15:20:54 -05004762
4763 if (mps < 128 || mps > 4096 || !is_power_of_2(mps))
Jiang Liu59875ae2012-07-24 17:20:06 +08004764 return -EINVAL;
Jon Masonb03e7492011-07-20 15:20:54 -05004765
4766 v = ffs(mps) - 8;
Bjorn Helgaasf7625982013-11-14 11:28:18 -07004767 if (v > dev->pcie_mpss)
Jiang Liu59875ae2012-07-24 17:20:06 +08004768 return -EINVAL;
Jon Masonb03e7492011-07-20 15:20:54 -05004769 v <<= 5;
4770
Jiang Liu59875ae2012-07-24 17:20:06 +08004771 return pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
4772 PCI_EXP_DEVCTL_PAYLOAD, v);
Jon Masonb03e7492011-07-20 15:20:54 -05004773}
Yijing Wangf1c66c42013-09-24 12:08:06 -06004774EXPORT_SYMBOL(pcie_set_mps);
Jon Masonb03e7492011-07-20 15:20:54 -05004775
4776/**
Jacob Keller81377c82013-07-31 06:53:26 +00004777 * pcie_get_minimum_link - determine minimum link settings of a PCI device
4778 * @dev: PCI device to query
4779 * @speed: storage for minimum speed
4780 * @width: storage for minimum width
4781 *
4782 * This function will walk up the PCI device chain and determine the minimum
4783 * link width and speed of the device.
4784 */
4785int pcie_get_minimum_link(struct pci_dev *dev, enum pci_bus_speed *speed,
4786 enum pcie_link_width *width)
4787{
4788 int ret;
4789
4790 *speed = PCI_SPEED_UNKNOWN;
4791 *width = PCIE_LNK_WIDTH_UNKNOWN;
4792
4793 while (dev) {
4794 u16 lnksta;
4795 enum pci_bus_speed next_speed;
4796 enum pcie_link_width next_width;
4797
4798 ret = pcie_capability_read_word(dev, PCI_EXP_LNKSTA, &lnksta);
4799 if (ret)
4800 return ret;
4801
4802 next_speed = pcie_link_speed[lnksta & PCI_EXP_LNKSTA_CLS];
4803 next_width = (lnksta & PCI_EXP_LNKSTA_NLW) >>
4804 PCI_EXP_LNKSTA_NLW_SHIFT;
4805
4806 if (next_speed < *speed)
4807 *speed = next_speed;
4808
4809 if (next_width < *width)
4810 *width = next_width;
4811
4812 dev = dev->bus->self;
4813 }
4814
4815 return 0;
4816}
4817EXPORT_SYMBOL(pcie_get_minimum_link);
4818
4819/**
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09004820 * pci_select_bars - Make BAR mask from the type of resource
Randy Dunlapf95d8822007-02-10 14:41:56 -08004821 * @dev: the PCI device for which BAR mask is made
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09004822 * @flags: resource type mask to be selected
4823 *
4824 * This helper routine makes bar mask from the type of resource.
4825 */
4826int pci_select_bars(struct pci_dev *dev, unsigned long flags)
4827{
4828 int i, bars = 0;
4829 for (i = 0; i < PCI_NUM_RESOURCES; i++)
4830 if (pci_resource_flags(dev, i) & flags)
4831 bars |= (1 << i);
4832 return bars;
4833}
Ryan Desfossesb7fe9432014-04-25 14:32:25 -06004834EXPORT_SYMBOL(pci_select_bars);
Hidetoshi Setoc87deff2006-12-18 10:31:06 +09004835
Mike Travis95a8b6e2010-02-02 14:38:13 -08004836/* Some architectures require additional programming to enable VGA */
4837static arch_set_vga_state_t arch_set_vga_state;
4838
4839void __init pci_register_set_vga_state(arch_set_vga_state_t func)
4840{
4841 arch_set_vga_state = func; /* NULL disables */
4842}
4843
4844static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode,
Ryan Desfosses3c78bc62014-04-18 20:13:49 -04004845 unsigned int command_bits, u32 flags)
Mike Travis95a8b6e2010-02-02 14:38:13 -08004846{
4847 if (arch_set_vga_state)
4848 return arch_set_vga_state(dev, decode, command_bits,
Dave Airlie7ad35cf2011-05-25 14:00:49 +10004849 flags);
Mike Travis95a8b6e2010-02-02 14:38:13 -08004850 return 0;
4851}
4852
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004853/**
4854 * pci_set_vga_state - set VGA decode state on device and parents if requested
Randy Dunlap19eea632009-09-17 15:28:22 -07004855 * @dev: the PCI device
4856 * @decode: true = enable decoding, false = disable decoding
4857 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
Randy Dunlap3f37d622011-05-25 19:21:25 -07004858 * @flags: traverse ancestors and change bridges
Dave Airlie3448a192010-06-01 15:32:24 +10004859 * CHANGE_BRIDGE_ONLY / CHANGE_BRIDGE
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004860 */
4861int pci_set_vga_state(struct pci_dev *dev, bool decode,
Dave Airlie3448a192010-06-01 15:32:24 +10004862 unsigned int command_bits, u32 flags)
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004863{
4864 struct pci_bus *bus;
4865 struct pci_dev *bridge;
4866 u16 cmd;
Mike Travis95a8b6e2010-02-02 14:38:13 -08004867 int rc;
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004868
Bjorn Helgaas67ebd812014-04-05 15:14:22 -06004869 WARN_ON((flags & PCI_VGA_STATE_CHANGE_DECODES) && (command_bits & ~(PCI_COMMAND_IO|PCI_COMMAND_MEMORY)));
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004870
Mike Travis95a8b6e2010-02-02 14:38:13 -08004871 /* ARCH specific VGA enables */
Dave Airlie3448a192010-06-01 15:32:24 +10004872 rc = pci_set_vga_state_arch(dev, decode, command_bits, flags);
Mike Travis95a8b6e2010-02-02 14:38:13 -08004873 if (rc)
4874 return rc;
4875
Dave Airlie3448a192010-06-01 15:32:24 +10004876 if (flags & PCI_VGA_STATE_CHANGE_DECODES) {
4877 pci_read_config_word(dev, PCI_COMMAND, &cmd);
4878 if (decode == true)
4879 cmd |= command_bits;
4880 else
4881 cmd &= ~command_bits;
4882 pci_write_config_word(dev, PCI_COMMAND, cmd);
4883 }
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004884
Dave Airlie3448a192010-06-01 15:32:24 +10004885 if (!(flags & PCI_VGA_STATE_CHANGE_BRIDGE))
Benjamin Herrenschmidtdeb2d2e2009-08-11 15:52:06 +10004886 return 0;
4887
4888 bus = dev->bus;
4889 while (bus) {
4890 bridge = bus->self;
4891 if (bridge) {
4892 pci_read_config_word(bridge, PCI_BRIDGE_CONTROL,
4893 &cmd);
4894 if (decode == true)
4895 cmd |= PCI_BRIDGE_CTL_VGA;
4896 else
4897 cmd &= ~PCI_BRIDGE_CTL_VGA;
4898 pci_write_config_word(bridge, PCI_BRIDGE_CONTROL,
4899 cmd);
4900 }
4901 bus = bus->parent;
4902 }
4903 return 0;
4904}
4905
Bjorn Helgaasf0af9592016-02-24 13:43:45 -06004906/**
4907 * pci_add_dma_alias - Add a DMA devfn alias for a device
4908 * @dev: the PCI device for which alias is added
4909 * @devfn: alias slot and function
4910 *
4911 * This helper encodes 8-bit devfn as bit number in dma_alias_mask.
4912 * It should be called early, preferably as PCI fixup header quirk.
4913 */
4914void pci_add_dma_alias(struct pci_dev *dev, u8 devfn)
4915{
Jacek Lawrynowicz338c3142016-03-03 15:38:02 +01004916 if (!dev->dma_alias_mask)
4917 dev->dma_alias_mask = kcalloc(BITS_TO_LONGS(U8_MAX),
4918 sizeof(long), GFP_KERNEL);
4919 if (!dev->dma_alias_mask) {
4920 dev_warn(&dev->dev, "Unable to allocate DMA alias mask\n");
4921 return;
4922 }
4923
4924 set_bit(devfn, dev->dma_alias_mask);
Bjorn Helgaas48c83082016-02-24 13:43:54 -06004925 dev_info(&dev->dev, "Enabling fixed DMA alias to %02x.%d\n",
4926 PCI_SLOT(devfn), PCI_FUNC(devfn));
Bjorn Helgaasf0af9592016-02-24 13:43:45 -06004927}
4928
Jacek Lawrynowicz338c3142016-03-03 15:38:02 +01004929bool pci_devs_are_dma_aliases(struct pci_dev *dev1, struct pci_dev *dev2)
4930{
4931 return (dev1->dma_alias_mask &&
4932 test_bit(dev2->devfn, dev1->dma_alias_mask)) ||
4933 (dev2->dma_alias_mask &&
4934 test_bit(dev1->devfn, dev2->dma_alias_mask));
4935}
4936
Rafael J. Wysocki8496e852013-12-01 02:34:37 +01004937bool pci_device_is_present(struct pci_dev *pdev)
4938{
4939 u32 v;
4940
4941 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0);
4942}
4943EXPORT_SYMBOL_GPL(pci_device_is_present);
4944
Rafael J. Wysocki08249652015-04-13 16:23:36 +02004945void pci_ignore_hotplug(struct pci_dev *dev)
4946{
4947 struct pci_dev *bridge = dev->bus->self;
4948
4949 dev->ignore_hotplug = 1;
4950 /* Propagate the "ignore hotplug" setting to the parent bridge. */
4951 if (bridge)
4952 bridge->ignore_hotplug = 1;
4953}
4954EXPORT_SYMBOL_GPL(pci_ignore_hotplug);
4955
Yuji Shimada32a9a6822009-03-16 17:13:39 +09004956#define RESOURCE_ALIGNMENT_PARAM_SIZE COMMAND_LINE_SIZE
4957static char resource_alignment_param[RESOURCE_ALIGNMENT_PARAM_SIZE] = {0};
Thomas Gleixnere9d1e492009-11-06 22:41:23 +00004958static DEFINE_SPINLOCK(resource_alignment_lock);
Yuji Shimada32a9a6822009-03-16 17:13:39 +09004959
4960/**
4961 * pci_specified_resource_alignment - get resource alignment specified by user.
4962 * @dev: the PCI device to get
4963 *
4964 * RETURNS: Resource alignment if it is specified.
4965 * Zero if it is not specified.
4966 */
Bjorn Helgaas9738abe2013-04-12 11:20:03 -06004967static resource_size_t pci_specified_resource_alignment(struct pci_dev *dev)
Yuji Shimada32a9a6822009-03-16 17:13:39 +09004968{
4969 int seg, bus, slot, func, align_order, count;
Koehrer Mathias (ETAS/ESW5)644a5442016-06-07 14:24:17 +00004970 unsigned short vendor, device, subsystem_vendor, subsystem_device;
Yuji Shimada32a9a6822009-03-16 17:13:39 +09004971 resource_size_t align = 0;
4972 char *p;
4973
4974 spin_lock(&resource_alignment_lock);
4975 p = resource_alignment_param;
Yongji Xief0b99f72016-09-13 17:00:31 +08004976 if (!*p)
4977 goto out;
4978 if (pci_has_flag(PCI_PROBE_ONLY)) {
4979 pr_info_once("PCI: Ignoring requested alignments (PCI_PROBE_ONLY)\n");
4980 goto out;
4981 }
4982
Yuji Shimada32a9a6822009-03-16 17:13:39 +09004983 while (*p) {
4984 count = 0;
4985 if (sscanf(p, "%d%n", &align_order, &count) == 1 &&
4986 p[count] == '@') {
4987 p += count + 1;
4988 } else {
4989 align_order = -1;
4990 }
Koehrer Mathias (ETAS/ESW5)644a5442016-06-07 14:24:17 +00004991 if (strncmp(p, "pci:", 4) == 0) {
4992 /* PCI vendor/device (subvendor/subdevice) ids are specified */
4993 p += 4;
4994 if (sscanf(p, "%hx:%hx:%hx:%hx%n",
4995 &vendor, &device, &subsystem_vendor, &subsystem_device, &count) != 4) {
4996 if (sscanf(p, "%hx:%hx%n", &vendor, &device, &count) != 2) {
4997 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: pci:%s\n",
4998 p);
4999 break;
5000 }
5001 subsystem_vendor = subsystem_device = 0;
5002 }
5003 p += count;
5004 if ((!vendor || (vendor == dev->vendor)) &&
5005 (!device || (device == dev->device)) &&
5006 (!subsystem_vendor || (subsystem_vendor == dev->subsystem_vendor)) &&
5007 (!subsystem_device || (subsystem_device == dev->subsystem_device))) {
5008 if (align_order == -1)
5009 align = PAGE_SIZE;
5010 else
5011 align = 1 << align_order;
5012 /* Found */
Yuji Shimada32a9a6822009-03-16 17:13:39 +09005013 break;
5014 }
5015 }
Koehrer Mathias (ETAS/ESW5)644a5442016-06-07 14:24:17 +00005016 else {
5017 if (sscanf(p, "%x:%x:%x.%x%n",
5018 &seg, &bus, &slot, &func, &count) != 4) {
5019 seg = 0;
5020 if (sscanf(p, "%x:%x.%x%n",
5021 &bus, &slot, &func, &count) != 3) {
5022 /* Invalid format */
5023 printk(KERN_ERR "PCI: Can't parse resource_alignment parameter: %s\n",
5024 p);
5025 break;
5026 }
5027 }
5028 p += count;
5029 if (seg == pci_domain_nr(dev->bus) &&
5030 bus == dev->bus->number &&
5031 slot == PCI_SLOT(dev->devfn) &&
5032 func == PCI_FUNC(dev->devfn)) {
5033 if (align_order == -1)
5034 align = PAGE_SIZE;
5035 else
5036 align = 1 << align_order;
5037 /* Found */
5038 break;
5039 }
Yuji Shimada32a9a6822009-03-16 17:13:39 +09005040 }
5041 if (*p != ';' && *p != ',') {
5042 /* End of param or invalid format */
5043 break;
5044 }
5045 p++;
5046 }
Yongji Xief0b99f72016-09-13 17:00:31 +08005047out:
Yuji Shimada32a9a6822009-03-16 17:13:39 +09005048 spin_unlock(&resource_alignment_lock);
5049 return align;
5050}
5051
Yinghai Lu2069ecf2012-02-15 21:40:31 -08005052/*
5053 * This function disables memory decoding and releases memory resources
5054 * of the device specified by kernel's boot parameter 'pci=resource_alignment='.
5055 * It also rounds up size to specified alignment.
5056 * Later on, the kernel will assign page-aligned memory resource back
5057 * to the device.
5058 */
5059void pci_reassigndev_resource_alignment(struct pci_dev *dev)
5060{
5061 int i;
5062 struct resource *r;
5063 resource_size_t align, size;
5064 u16 command;
5065
Yongji Xie62d9a782016-09-13 17:00:32 +08005066 /*
5067 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec
5068 * 3.4.1.11. Their resources are allocated from the space
5069 * described by the VF BARx register in the PF's SR-IOV capability.
5070 * We can't influence their alignment here.
5071 */
5072 if (dev->is_virtfn)
5073 return;
5074
Yinghai Lu10c463a2012-03-18 22:46:26 -07005075 /* check if specified PCI is target device to reassign */
5076 align = pci_specified_resource_alignment(dev);
5077 if (!align)
Yinghai Lu2069ecf2012-02-15 21:40:31 -08005078 return;
5079
5080 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL &&
5081 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) {
5082 dev_warn(&dev->dev,
5083 "Can't reassign resources to host bridge.\n");
5084 return;
5085 }
5086
5087 dev_info(&dev->dev,
5088 "Disabling memory decoding and releasing memory resources.\n");
5089 pci_read_config_word(dev, PCI_COMMAND, &command);
5090 command &= ~PCI_COMMAND_MEMORY;
5091 pci_write_config_word(dev, PCI_COMMAND, command);
5092
Yinghai Lu2069ecf2012-02-15 21:40:31 -08005093 for (i = 0; i < PCI_BRIDGE_RESOURCES; i++) {
5094 r = &dev->resource[i];
5095 if (!(r->flags & IORESOURCE_MEM))
5096 continue;
Yongji Xief0b99f72016-09-13 17:00:31 +08005097 if (r->flags & IORESOURCE_PCI_FIXED) {
5098 dev_info(&dev->dev, "Ignoring requested alignment for BAR%d: %pR\n",
5099 i, r);
5100 continue;
5101 }
5102
Yinghai Lu2069ecf2012-02-15 21:40:31 -08005103 size = resource_size(r);
5104 if (size < align) {
5105 size = align;
5106 dev_info(&dev->dev,
5107 "Rounding up size of resource #%d to %#llx.\n",
5108 i, (unsigned long long)size);
5109 }
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07005110 r->flags |= IORESOURCE_UNSET;
Yinghai Lu2069ecf2012-02-15 21:40:31 -08005111 r->end = size - 1;
5112 r->start = 0;
5113 }
5114 /* Need to disable bridge's resource window,
5115 * to enable the kernel to reassign new resource
5116 * window later on.
5117 */
5118 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE &&
5119 (dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
5120 for (i = PCI_BRIDGE_RESOURCES; i < PCI_NUM_RESOURCES; i++) {
5121 r = &dev->resource[i];
5122 if (!(r->flags & IORESOURCE_MEM))
5123 continue;
Bjorn Helgaasbd064f02014-02-26 11:25:58 -07005124 r->flags |= IORESOURCE_UNSET;
Yinghai Lu2069ecf2012-02-15 21:40:31 -08005125 r->end = resource_size(r) - 1;
5126 r->start = 0;
5127 }
5128 pci_disable_bridge_window(dev);
5129 }
5130}
5131
Bjorn Helgaas9738abe2013-04-12 11:20:03 -06005132static ssize_t pci_set_resource_alignment_param(const char *buf, size_t count)
Yuji Shimada32a9a6822009-03-16 17:13:39 +09005133{
5134 if (count > RESOURCE_ALIGNMENT_PARAM_SIZE - 1)
5135 count = RESOURCE_ALIGNMENT_PARAM_SIZE - 1;
5136 spin_lock(&resource_alignment_lock);
5137 strncpy(resource_alignment_param, buf, count);
5138 resource_alignment_param[count] = '\0';
5139 spin_unlock(&resource_alignment_lock);
5140 return count;
5141}
5142
Bjorn Helgaas9738abe2013-04-12 11:20:03 -06005143static ssize_t pci_get_resource_alignment_param(char *buf, size_t size)
Yuji Shimada32a9a6822009-03-16 17:13:39 +09005144{
5145 size_t count;
5146 spin_lock(&resource_alignment_lock);
5147 count = snprintf(buf, size, "%s", resource_alignment_param);
5148 spin_unlock(&resource_alignment_lock);
5149 return count;
5150}
5151
5152static ssize_t pci_resource_alignment_show(struct bus_type *bus, char *buf)
5153{
5154 return pci_get_resource_alignment_param(buf, PAGE_SIZE);
5155}
5156
5157static ssize_t pci_resource_alignment_store(struct bus_type *bus,
5158 const char *buf, size_t count)
5159{
5160 return pci_set_resource_alignment_param(buf, count);
5161}
5162
Ben Dooks21751a92016-06-09 11:42:13 +01005163static BUS_ATTR(resource_alignment, 0644, pci_resource_alignment_show,
Yuji Shimada32a9a6822009-03-16 17:13:39 +09005164 pci_resource_alignment_store);
5165
5166static int __init pci_resource_alignment_sysfs_init(void)
5167{
5168 return bus_create_file(&pci_bus_type,
5169 &bus_attr_resource_alignment);
5170}
Yuji Shimada32a9a6822009-03-16 17:13:39 +09005171late_initcall(pci_resource_alignment_sysfs_init);
5172
Bill Pemberton15856ad2012-11-21 15:35:00 -05005173static void pci_no_domains(void)
Jeff Garzik32a2eea2007-10-11 16:57:27 -04005174{
5175#ifdef CONFIG_PCI_DOMAINS
5176 pci_domains_supported = 0;
5177#endif
5178}
5179
Liviu Dudau41e5c0f2014-09-29 15:29:27 +01005180#ifdef CONFIG_PCI_DOMAINS
5181static atomic_t __domain_nr = ATOMIC_INIT(-1);
5182
5183int pci_get_new_domain_nr(void)
5184{
5185 return atomic_inc_return(&__domain_nr);
5186}
Lorenzo Pieralisi7c674702014-12-27 18:19:12 -07005187
5188#ifdef CONFIG_PCI_DOMAINS_GENERIC
Tomasz Nowicki1a4f93f2016-06-10 21:55:15 +02005189static int of_pci_bus_find_domain_nr(struct device *parent)
Lorenzo Pieralisi7c674702014-12-27 18:19:12 -07005190{
5191 static int use_dt_domains = -1;
Krzysztof =?utf-8?Q?Ha=C5=82asa?=54c6e2d2016-03-01 07:07:18 +01005192 int domain = -1;
Lorenzo Pieralisi7c674702014-12-27 18:19:12 -07005193
Krzysztof =?utf-8?Q?Ha=C5=82asa?=54c6e2d2016-03-01 07:07:18 +01005194 if (parent)
5195 domain = of_get_pci_domain_nr(parent->of_node);
Lorenzo Pieralisi7c674702014-12-27 18:19:12 -07005196 /*
5197 * Check DT domain and use_dt_domains values.
5198 *
5199 * If DT domain property is valid (domain >= 0) and
5200 * use_dt_domains != 0, the DT assignment is valid since this means
5201 * we have not previously allocated a domain number by using
5202 * pci_get_new_domain_nr(); we should also update use_dt_domains to
5203 * 1, to indicate that we have just assigned a domain number from
5204 * DT.
5205 *
5206 * If DT domain property value is not valid (ie domain < 0), and we
5207 * have not previously assigned a domain number from DT
5208 * (use_dt_domains != 1) we should assign a domain number by
5209 * using the:
5210 *
5211 * pci_get_new_domain_nr()
5212 *
5213 * API and update the use_dt_domains value to keep track of method we
5214 * are using to assign domain numbers (use_dt_domains = 0).
5215 *
5216 * All other combinations imply we have a platform that is trying
5217 * to mix domain numbers obtained from DT and pci_get_new_domain_nr(),
5218 * which is a recipe for domain mishandling and it is prevented by
5219 * invalidating the domain value (domain = -1) and printing a
5220 * corresponding error.
5221 */
5222 if (domain >= 0 && use_dt_domains) {
5223 use_dt_domains = 1;
5224 } else if (domain < 0 && use_dt_domains != 1) {
5225 use_dt_domains = 0;
5226 domain = pci_get_new_domain_nr();
5227 } else {
5228 dev_err(parent, "Node %s has inconsistent \"linux,pci-domain\" property in DT\n",
5229 parent->of_node->full_name);
5230 domain = -1;
5231 }
5232
Tomasz Nowicki9c7cb892016-06-10 21:55:14 +02005233 return domain;
Lorenzo Pieralisi7c674702014-12-27 18:19:12 -07005234}
Tomasz Nowicki1a4f93f2016-06-10 21:55:15 +02005235
5236int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent)
5237{
Tomasz Nowicki2ab51dd2016-06-10 15:36:26 -05005238 return acpi_disabled ? of_pci_bus_find_domain_nr(parent) :
5239 acpi_pci_bus_find_domain_nr(bus);
Lorenzo Pieralisi7c674702014-12-27 18:19:12 -07005240}
5241#endif
Liviu Dudau41e5c0f2014-09-29 15:29:27 +01005242#endif
5243
Andrew Patterson0ef5f8f2008-11-10 15:30:50 -07005244/**
Taku Izumi642c92d2012-10-30 15:26:18 +09005245 * pci_ext_cfg_avail - can we access extended PCI config space?
Andrew Patterson0ef5f8f2008-11-10 15:30:50 -07005246 *
5247 * Returns 1 if we can access PCI extended config space (offsets
5248 * greater than 0xff). This is the default implementation. Architecture
5249 * implementations can override this.
5250 */
Taku Izumi642c92d2012-10-30 15:26:18 +09005251int __weak pci_ext_cfg_avail(void)
Andrew Patterson0ef5f8f2008-11-10 15:30:50 -07005252{
5253 return 1;
5254}
5255
Benjamin Herrenschmidt2d1c8612009-12-09 17:52:13 +11005256void __weak pci_fixup_cardbus(struct pci_bus *bus)
5257{
5258}
5259EXPORT_SYMBOL(pci_fixup_cardbus);
5260
Al Viroad04d312008-11-22 17:37:14 +00005261static int __init pci_setup(char *str)
Linus Torvalds1da177e2005-04-16 15:20:36 -07005262{
5263 while (str) {
5264 char *k = strchr(str, ',');
5265 if (k)
5266 *k++ = 0;
5267 if (*str && (str = pcibios_setup(str)) && *str) {
Matthew Wilcox309e57d2006-03-05 22:33:34 -07005268 if (!strcmp(str, "nomsi")) {
5269 pci_no_msi();
Randy Dunlap7f785762007-10-05 13:17:58 -07005270 } else if (!strcmp(str, "noaer")) {
5271 pci_no_aer();
Yinghai Lub55438f2012-02-23 19:23:30 -08005272 } else if (!strncmp(str, "realloc=", 8)) {
5273 pci_realloc_get_opt(str + 8);
Ram Paif483d392011-07-07 11:19:10 -07005274 } else if (!strncmp(str, "realloc", 7)) {
Yinghai Lub55438f2012-02-23 19:23:30 -08005275 pci_realloc_get_opt("on");
Jeff Garzik32a2eea2007-10-11 16:57:27 -04005276 } else if (!strcmp(str, "nodomains")) {
5277 pci_no_domains();
Rafael J. Wysocki6748dcc2012-03-01 00:06:33 +01005278 } else if (!strncmp(str, "noari", 5)) {
5279 pcie_ari_disabled = true;
Atsushi Nemoto4516a612007-02-05 16:36:06 -08005280 } else if (!strncmp(str, "cbiosize=", 9)) {
5281 pci_cardbus_io_size = memparse(str + 9, &str);
5282 } else if (!strncmp(str, "cbmemsize=", 10)) {
5283 pci_cardbus_mem_size = memparse(str + 10, &str);
Yuji Shimada32a9a6822009-03-16 17:13:39 +09005284 } else if (!strncmp(str, "resource_alignment=", 19)) {
5285 pci_set_resource_alignment_param(str + 19,
5286 strlen(str + 19));
Andrew Patterson43c16402009-04-22 16:52:09 -06005287 } else if (!strncmp(str, "ecrc=", 5)) {
5288 pcie_ecrc_get_policy(str + 5);
Eric W. Biederman28760482009-09-09 14:09:24 -07005289 } else if (!strncmp(str, "hpiosize=", 9)) {
5290 pci_hotplug_io_size = memparse(str + 9, &str);
5291 } else if (!strncmp(str, "hpmemsize=", 10)) {
5292 pci_hotplug_mem_size = memparse(str + 10, &str);
Keith Busche16b4662016-07-21 21:40:28 -06005293 } else if (!strncmp(str, "hpbussize=", 10)) {
5294 pci_hotplug_bus_size =
5295 simple_strtoul(str + 10, &str, 0);
5296 if (pci_hotplug_bus_size > 0xff)
5297 pci_hotplug_bus_size = DEFAULT_HOTPLUG_BUS_SIZE;
Jon Mason5f39e672011-10-03 09:50:20 -05005298 } else if (!strncmp(str, "pcie_bus_tune_off", 17)) {
5299 pcie_bus_config = PCIE_BUS_TUNE_OFF;
Jon Masonb03e7492011-07-20 15:20:54 -05005300 } else if (!strncmp(str, "pcie_bus_safe", 13)) {
5301 pcie_bus_config = PCIE_BUS_SAFE;
5302 } else if (!strncmp(str, "pcie_bus_perf", 13)) {
5303 pcie_bus_config = PCIE_BUS_PERFORMANCE;
Jon Mason5f39e672011-10-03 09:50:20 -05005304 } else if (!strncmp(str, "pcie_bus_peer2peer", 18)) {
5305 pcie_bus_config = PCIE_BUS_PEER2PEER;
Bjorn Helgaas284f5f92012-04-30 15:21:02 -06005306 } else if (!strncmp(str, "pcie_scan_all", 13)) {
5307 pci_add_flags(PCI_SCAN_ALL_PCIE_DEVS);
Matthew Wilcox309e57d2006-03-05 22:33:34 -07005308 } else {
5309 printk(KERN_ERR "PCI: Unknown option `%s'\n",
5310 str);
5311 }
Linus Torvalds1da177e2005-04-16 15:20:36 -07005312 }
5313 str = k;
5314 }
Andi Kleen0637a702006-09-26 10:52:41 +02005315 return 0;
Linus Torvalds1da177e2005-04-16 15:20:36 -07005316}
Andi Kleen0637a702006-09-26 10:52:41 +02005317early_param("pci", pci_setup);