Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 1 | /* |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 2 | * Copyright 2012 Red Hat Inc. |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice shall be included in |
| 12 | * all copies or substantial portions of the Software. |
| 13 | * |
| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
| 21 | * |
| 22 | * Authors: Ben Skeggs |
| 23 | */ |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 24 | #include <engine/fifo.h> |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 25 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 26 | #include <core/client.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 27 | #include <core/engctx.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 28 | #include <core/enum.h> |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 29 | #include <core/handle.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 30 | #include <subdev/bar.h> |
Ben Skeggs | 5222555 | 2013-12-23 01:51:16 +1000 | [diff] [blame] | 31 | #include <subdev/fb.h> |
Ben Skeggs | 5ce3bf3 | 2015-01-14 09:57:36 +1000 | [diff] [blame] | 32 | #include <subdev/mmu.h> |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 33 | #include <subdev/timer.h> |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 34 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 35 | #include <nvif/class.h> |
Ben Skeggs | f58ddf9 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 36 | #include <nvif/ioctl.h> |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 37 | #include <nvif/unpack.h> |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 38 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 39 | struct gf100_fifo { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 40 | struct nvkm_fifo base; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 41 | |
| 42 | struct work_struct fault; |
| 43 | u64 mask; |
| 44 | |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 45 | struct { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 46 | struct nvkm_gpuobj *mem[2]; |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 47 | int active; |
| 48 | wait_queue_head_t wait; |
| 49 | } runlist; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 50 | |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 51 | struct { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 52 | struct nvkm_gpuobj *mem; |
| 53 | struct nvkm_vma bar; |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 54 | } user; |
Ben Skeggs | ec9c088 | 2010-12-31 12:10:49 +1000 | [diff] [blame] | 55 | int spoon_nr; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 56 | }; |
| 57 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 58 | struct gf100_fifo_base { |
| 59 | struct nvkm_fifo_base base; |
| 60 | struct nvkm_gpuobj *pgd; |
| 61 | struct nvkm_vm *vm; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 62 | }; |
| 63 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 64 | struct gf100_fifo_chan { |
| 65 | struct nvkm_fifo_chan base; |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 66 | enum { |
| 67 | STOPPED, |
| 68 | RUNNING, |
| 69 | KILLED |
| 70 | } state; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 71 | }; |
| 72 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 73 | /******************************************************************************* |
| 74 | * FIFO channel objects |
| 75 | ******************************************************************************/ |
| 76 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 77 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 78 | gf100_fifo_runlist_update(struct gf100_fifo *fifo) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 79 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 80 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 81 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 82 | struct nvkm_bar *bar = device->bar; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 83 | struct nvkm_gpuobj *cur; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 84 | int i, p; |
| 85 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 86 | mutex_lock(&nv_subdev(fifo)->mutex); |
| 87 | cur = fifo->runlist.mem[fifo->runlist.active]; |
| 88 | fifo->runlist.active = !fifo->runlist.active; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 89 | |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 90 | nvkm_kmap(cur); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 91 | for (i = 0, p = 0; i < 128; i++) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 92 | struct gf100_fifo_chan *chan = (void *)fifo->base.channel[i]; |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 93 | if (chan && chan->state == RUNNING) { |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 94 | nvkm_wo32(cur, p + 0, i); |
| 95 | nvkm_wo32(cur, p + 4, 0x00000004); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 96 | p += 8; |
| 97 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 98 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 99 | bar->flush(bar); |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 100 | nvkm_done(cur); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 101 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 102 | nvkm_wr32(device, 0x002270, cur->addr >> 12); |
| 103 | nvkm_wr32(device, 0x002274, 0x01f00000 | (p >> 3)); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 104 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 105 | if (wait_event_timeout(fifo->runlist.wait, |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 106 | !(nvkm_rd32(device, 0x00227c) & 0x00100000), |
Ben Skeggs | 3cf6290 | 2014-02-22 01:05:01 +1000 | [diff] [blame] | 107 | msecs_to_jiffies(2000)) == 0) |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 108 | nvkm_error(subdev, "runlist update timeout\n"); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 109 | mutex_unlock(&nv_subdev(fifo)->mutex); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 110 | } |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 111 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 112 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 113 | gf100_fifo_context_attach(struct nvkm_object *parent, |
| 114 | struct nvkm_object *object) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 115 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 116 | struct nvkm_bar *bar = nvkm_bar(parent); |
| 117 | struct gf100_fifo_base *base = (void *)parent->parent; |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 118 | struct nvkm_gpuobj *engn = &base->base.gpuobj; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 119 | struct nvkm_engctx *ectx = (void *)object; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 120 | u32 addr; |
| 121 | int ret; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 122 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 123 | switch (nv_engidx(object->engine)) { |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 124 | case NVDEV_ENGINE_SW : return 0; |
| 125 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
| 126 | case NVDEV_ENGINE_CE0 : addr = 0x0230; break; |
| 127 | case NVDEV_ENGINE_CE1 : addr = 0x0240; break; |
| 128 | case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; |
| 129 | case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; |
| 130 | case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 131 | default: |
| 132 | return -EINVAL; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 133 | } |
| 134 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 135 | if (!ectx->vma.node) { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 136 | ret = nvkm_gpuobj_map_vm(nv_gpuobj(ectx), base->vm, |
| 137 | NV_MEM_ACCESS_RW, &ectx->vma); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 138 | if (ret) |
| 139 | return ret; |
Ben Skeggs | 4c2d422 | 2012-08-10 15:10:34 +1000 | [diff] [blame] | 140 | |
| 141 | nv_engctx(ectx)->addr = nv_gpuobj(base)->addr >> 12; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 142 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 143 | |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 144 | nvkm_kmap(engn); |
| 145 | nvkm_wo32(engn, addr + 0x00, lower_32_bits(ectx->vma.offset) | 4); |
| 146 | nvkm_wo32(engn, addr + 0x04, upper_32_bits(ectx->vma.offset)); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 147 | bar->flush(bar); |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 148 | nvkm_done(engn); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 149 | return 0; |
| 150 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 151 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 152 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 153 | gf100_fifo_context_detach(struct nvkm_object *parent, bool suspend, |
| 154 | struct nvkm_object *object) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 155 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 156 | struct gf100_fifo *fifo = (void *)parent->engine; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 157 | struct gf100_fifo_base *base = (void *)parent->parent; |
| 158 | struct gf100_fifo_chan *chan = (void *)parent; |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 159 | struct nvkm_gpuobj *engn = &base->base.gpuobj; |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 160 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 161 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 162 | struct nvkm_bar *bar = device->bar; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 163 | u32 addr; |
| 164 | |
| 165 | switch (nv_engidx(object->engine)) { |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 166 | case NVDEV_ENGINE_SW : return 0; |
| 167 | case NVDEV_ENGINE_GR : addr = 0x0210; break; |
| 168 | case NVDEV_ENGINE_CE0 : addr = 0x0230; break; |
| 169 | case NVDEV_ENGINE_CE1 : addr = 0x0240; break; |
| 170 | case NVDEV_ENGINE_MSVLD : addr = 0x0270; break; |
| 171 | case NVDEV_ENGINE_MSPDEC: addr = 0x0250; break; |
| 172 | case NVDEV_ENGINE_MSPPP : addr = 0x0260; break; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 173 | default: |
| 174 | return -EINVAL; |
| 175 | } |
| 176 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 177 | nvkm_wr32(device, 0x002634, chan->base.chid); |
Ben Skeggs | af3082b | 2015-08-20 14:54:11 +1000 | [diff] [blame] | 178 | if (nvkm_msec(device, 2000, |
| 179 | if (nvkm_rd32(device, 0x002634) == chan->base.chid) |
| 180 | break; |
| 181 | ) < 0) { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 182 | nvkm_error(subdev, "channel %d [%s] kick timeout\n", |
| 183 | chan->base.chid, nvkm_client_name(chan)); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 184 | if (suspend) |
| 185 | return -EBUSY; |
| 186 | } |
| 187 | |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 188 | nvkm_kmap(engn); |
| 189 | nvkm_wo32(engn, addr + 0x00, 0x00000000); |
| 190 | nvkm_wo32(engn, addr + 0x04, 0x00000000); |
Ben Skeggs | edc260d | 2012-11-27 11:05:36 +1000 | [diff] [blame] | 191 | bar->flush(bar); |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 192 | nvkm_done(engn); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 193 | return 0; |
| 194 | } |
| 195 | |
| 196 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 197 | gf100_fifo_chan_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
| 198 | struct nvkm_oclass *oclass, void *data, u32 size, |
| 199 | struct nvkm_object **pobject) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 200 | { |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 201 | union { |
Ben Skeggs | 159045c | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 202 | struct fermi_channel_gpfifo_v0 v0; |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 203 | } *args = data; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 204 | struct nvkm_bar *bar = nvkm_bar(parent); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 205 | struct gf100_fifo *fifo = (void *)engine; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 206 | struct gf100_fifo_base *base = (void *)parent; |
| 207 | struct gf100_fifo_chan *chan; |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 208 | struct nvkm_gpuobj *ramfc = &base->base.gpuobj; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 209 | u64 usermem, ioffset, ilength; |
| 210 | int ret, i; |
| 211 | |
Ben Skeggs | 5300394 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 212 | nvif_ioctl(parent, "create channel gpfifo size %d\n", size); |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 213 | if (nvif_unpack(args->v0, 0, 0, false)) { |
Ben Skeggs | 159045c | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 214 | nvif_ioctl(parent, "create channel gpfifo vers %d " |
Ben Skeggs | 5300394 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 215 | "ioffset %016llx ilength %08x\n", |
Ben Skeggs | 159045c | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 216 | args->v0.version, args->v0.ioffset, |
Ben Skeggs | 5300394 | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 217 | args->v0.ilength); |
Ben Skeggs | 159045c | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 218 | if (args->v0.vm) |
| 219 | return -ENOENT; |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 220 | } else |
| 221 | return ret; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 222 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 223 | ret = nvkm_fifo_channel_create(parent, engine, oclass, 1, |
Ben Skeggs | 159045c | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 224 | fifo->user.bar.offset, 0x1000, 0, |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 225 | (1ULL << NVDEV_ENGINE_SW) | |
| 226 | (1ULL << NVDEV_ENGINE_GR) | |
| 227 | (1ULL << NVDEV_ENGINE_CE0) | |
| 228 | (1ULL << NVDEV_ENGINE_CE1) | |
| 229 | (1ULL << NVDEV_ENGINE_MSVLD) | |
| 230 | (1ULL << NVDEV_ENGINE_MSPDEC) | |
| 231 | (1ULL << NVDEV_ENGINE_MSPPP), &chan); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 232 | *pobject = nv_object(chan); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 233 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 234 | return ret; |
| 235 | |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 236 | args->v0.chid = chan->base.chid; |
| 237 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 238 | nv_parent(chan)->context_attach = gf100_fifo_context_attach; |
| 239 | nv_parent(chan)->context_detach = gf100_fifo_context_detach; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 240 | |
| 241 | usermem = chan->base.chid * 0x1000; |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 242 | ioffset = args->v0.ioffset; |
| 243 | ilength = order_base_2(args->v0.ilength / 8); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 244 | |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 245 | nvkm_kmap(fifo->user.mem); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 246 | for (i = 0; i < 0x1000; i += 4) |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 247 | nvkm_wo32(fifo->user.mem, usermem + i, 0x00000000); |
| 248 | nvkm_done(fifo->user.mem); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 249 | |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 250 | nvkm_kmap(ramfc); |
| 251 | nvkm_wo32(ramfc, 0x08, lower_32_bits(fifo->user.mem->addr + usermem)); |
| 252 | nvkm_wo32(ramfc, 0x0c, upper_32_bits(fifo->user.mem->addr + usermem)); |
| 253 | nvkm_wo32(ramfc, 0x10, 0x0000face); |
| 254 | nvkm_wo32(ramfc, 0x30, 0xfffff902); |
| 255 | nvkm_wo32(ramfc, 0x48, lower_32_bits(ioffset)); |
| 256 | nvkm_wo32(ramfc, 0x4c, upper_32_bits(ioffset) | (ilength << 16)); |
| 257 | nvkm_wo32(ramfc, 0x54, 0x00000002); |
| 258 | nvkm_wo32(ramfc, 0x84, 0x20400000); |
| 259 | nvkm_wo32(ramfc, 0x94, 0x30000001); |
| 260 | nvkm_wo32(ramfc, 0x9c, 0x00000100); |
| 261 | nvkm_wo32(ramfc, 0xa4, 0x1f1f1f1f); |
| 262 | nvkm_wo32(ramfc, 0xa8, 0x1f1f1f1f); |
| 263 | nvkm_wo32(ramfc, 0xac, 0x0000001f); |
| 264 | nvkm_wo32(ramfc, 0xb8, 0xf8000000); |
| 265 | nvkm_wo32(ramfc, 0xf8, 0x10003080); /* 0x002310 */ |
| 266 | nvkm_wo32(ramfc, 0xfc, 0x10000010); /* 0x002350 */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 267 | bar->flush(bar); |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 268 | nvkm_done(ramfc); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 269 | return 0; |
| 270 | } |
| 271 | |
| 272 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 273 | gf100_fifo_chan_init(struct nvkm_object *object) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 274 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 275 | struct nvkm_gpuobj *base = nv_gpuobj(object->parent); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 276 | struct gf100_fifo *fifo = (void *)object->engine; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 277 | struct gf100_fifo_chan *chan = (void *)object; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 278 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 279 | u32 chid = chan->base.chid; |
| 280 | int ret; |
| 281 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 282 | ret = nvkm_fifo_channel_init(&chan->base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 283 | if (ret) |
| 284 | return ret; |
| 285 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 286 | nvkm_wr32(device, 0x003000 + (chid * 8), 0xc0000000 | base->addr >> 12); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 287 | |
| 288 | if (chan->state == STOPPED && (chan->state = RUNNING) == RUNNING) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 289 | nvkm_wr32(device, 0x003004 + (chid * 8), 0x001f0001); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 290 | gf100_fifo_runlist_update(fifo); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 291 | } |
| 292 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 293 | return 0; |
| 294 | } |
| 295 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 296 | static void gf100_fifo_intr_engine(struct gf100_fifo *fifo); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 297 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 298 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 299 | gf100_fifo_chan_fini(struct nvkm_object *object, bool suspend) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 300 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 301 | struct gf100_fifo *fifo = (void *)object->engine; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 302 | struct gf100_fifo_chan *chan = (void *)object; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 303 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 304 | u32 chid = chan->base.chid; |
| 305 | |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 306 | if (chan->state == RUNNING && (chan->state = STOPPED) == STOPPED) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 307 | nvkm_mask(device, 0x003004 + (chid * 8), 0x00000001, 0x00000000); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 308 | gf100_fifo_runlist_update(fifo); |
Ben Skeggs | e2822b7 | 2014-02-22 00:52:45 +1000 | [diff] [blame] | 309 | } |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 310 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 311 | gf100_fifo_intr_engine(fifo); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 312 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 313 | nvkm_wr32(device, 0x003000 + (chid * 8), 0x00000000); |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 314 | return nvkm_fifo_channel_fini(&chan->base, suspend); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 315 | } |
| 316 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 317 | static struct nvkm_ofuncs |
| 318 | gf100_fifo_ofuncs = { |
| 319 | .ctor = gf100_fifo_chan_ctor, |
| 320 | .dtor = _nvkm_fifo_channel_dtor, |
| 321 | .init = gf100_fifo_chan_init, |
| 322 | .fini = gf100_fifo_chan_fini, |
| 323 | .map = _nvkm_fifo_channel_map, |
| 324 | .rd32 = _nvkm_fifo_channel_rd32, |
| 325 | .wr32 = _nvkm_fifo_channel_wr32, |
| 326 | .ntfy = _nvkm_fifo_channel_ntfy |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 327 | }; |
| 328 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 329 | static struct nvkm_oclass |
| 330 | gf100_fifo_sclass[] = { |
| 331 | { FERMI_CHANNEL_GPFIFO, &gf100_fifo_ofuncs }, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 332 | {} |
| 333 | }; |
| 334 | |
| 335 | /******************************************************************************* |
| 336 | * FIFO context - instmem heap and vm setup |
| 337 | ******************************************************************************/ |
| 338 | |
| 339 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 340 | gf100_fifo_context_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
| 341 | struct nvkm_oclass *oclass, void *data, u32 size, |
| 342 | struct nvkm_object **pobject) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 343 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 344 | struct gf100_fifo_base *base; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 345 | int ret; |
| 346 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 347 | ret = nvkm_fifo_context_create(parent, engine, oclass, NULL, 0x1000, |
| 348 | 0x1000, NVOBJ_FLAG_ZERO_ALLOC | |
| 349 | NVOBJ_FLAG_HEAP, &base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 350 | *pobject = nv_object(base); |
| 351 | if (ret) |
| 352 | return ret; |
| 353 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 354 | ret = nvkm_gpuobj_new(nv_object(base), NULL, 0x10000, 0x1000, 0, |
| 355 | &base->pgd); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 356 | if (ret) |
| 357 | return ret; |
| 358 | |
Ben Skeggs | 5444e77 | 2015-08-20 14:54:14 +1000 | [diff] [blame] | 359 | nvkm_kmap(&base->base.gpuobj); |
| 360 | nvkm_wo32(&base->base.gpuobj, 0x0200, lower_32_bits(base->pgd->addr)); |
| 361 | nvkm_wo32(&base->base.gpuobj, 0x0204, upper_32_bits(base->pgd->addr)); |
| 362 | nvkm_wo32(&base->base.gpuobj, 0x0208, 0xffffffff); |
| 363 | nvkm_wo32(&base->base.gpuobj, 0x020c, 0x000000ff); |
| 364 | nvkm_done(&base->base.gpuobj); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 365 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 366 | ret = nvkm_vm_ref(nvkm_client(parent)->vm, &base->vm, base->pgd); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 367 | if (ret) |
| 368 | return ret; |
| 369 | |
| 370 | return 0; |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 371 | } |
| 372 | |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 373 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 374 | gf100_fifo_context_dtor(struct nvkm_object *object) |
Ben Skeggs | 4b223ee | 2010-08-03 10:00:56 +1000 | [diff] [blame] | 375 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 376 | struct gf100_fifo_base *base = (void *)object; |
| 377 | nvkm_vm_ref(NULL, &base->vm, base->pgd); |
| 378 | nvkm_gpuobj_ref(NULL, &base->pgd); |
| 379 | nvkm_fifo_context_destroy(&base->base); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 380 | } |
| 381 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 382 | static struct nvkm_oclass |
| 383 | gf100_fifo_cclass = { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 384 | .handle = NV_ENGCTX(FIFO, 0xc0), |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 385 | .ofuncs = &(struct nvkm_ofuncs) { |
| 386 | .ctor = gf100_fifo_context_ctor, |
| 387 | .dtor = gf100_fifo_context_dtor, |
| 388 | .init = _nvkm_fifo_context_init, |
| 389 | .fini = _nvkm_fifo_context_fini, |
| 390 | .rd32 = _nvkm_fifo_context_rd32, |
| 391 | .wr32 = _nvkm_fifo_context_wr32, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 392 | }, |
| 393 | }; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 394 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 395 | /******************************************************************************* |
| 396 | * PFIFO engine |
| 397 | ******************************************************************************/ |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 398 | |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 399 | static inline int |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 400 | gf100_fifo_engidx(struct gf100_fifo *fifo, u32 engn) |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 401 | { |
| 402 | switch (engn) { |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 403 | case NVDEV_ENGINE_GR : engn = 0; break; |
| 404 | case NVDEV_ENGINE_MSVLD : engn = 1; break; |
| 405 | case NVDEV_ENGINE_MSPPP : engn = 2; break; |
| 406 | case NVDEV_ENGINE_MSPDEC: engn = 3; break; |
| 407 | case NVDEV_ENGINE_CE0 : engn = 4; break; |
| 408 | case NVDEV_ENGINE_CE1 : engn = 5; break; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 409 | default: |
| 410 | return -1; |
| 411 | } |
| 412 | |
| 413 | return engn; |
| 414 | } |
| 415 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 416 | static inline struct nvkm_engine * |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 417 | gf100_fifo_engine(struct gf100_fifo *fifo, u32 engn) |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 418 | { |
| 419 | switch (engn) { |
| 420 | case 0: engn = NVDEV_ENGINE_GR; break; |
Ben Skeggs | eccf7e8a | 2015-01-14 10:09:24 +1000 | [diff] [blame] | 421 | case 1: engn = NVDEV_ENGINE_MSVLD; break; |
Ben Skeggs | fd8666f | 2015-01-14 12:26:28 +1000 | [diff] [blame] | 422 | case 2: engn = NVDEV_ENGINE_MSPPP; break; |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 423 | case 3: engn = NVDEV_ENGINE_MSPDEC; break; |
Ben Skeggs | aedf24f | 2015-01-14 11:50:20 +1000 | [diff] [blame] | 424 | case 4: engn = NVDEV_ENGINE_CE0; break; |
| 425 | case 5: engn = NVDEV_ENGINE_CE1; break; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 426 | default: |
| 427 | return NULL; |
| 428 | } |
| 429 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 430 | return nvkm_engine(fifo, engn); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 431 | } |
| 432 | |
| 433 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 434 | gf100_fifo_recover_work(struct work_struct *work) |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 435 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 436 | struct gf100_fifo *fifo = container_of(work, typeof(*fifo), fault); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 437 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 438 | struct nvkm_object *engine; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 439 | unsigned long flags; |
| 440 | u32 engn, engm = 0; |
| 441 | u64 mask, todo; |
| 442 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 443 | spin_lock_irqsave(&fifo->base.lock, flags); |
| 444 | mask = fifo->mask; |
| 445 | fifo->mask = 0ULL; |
| 446 | spin_unlock_irqrestore(&fifo->base.lock, flags); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 447 | |
| 448 | for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 449 | engm |= 1 << gf100_fifo_engidx(fifo, engn); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 450 | nvkm_mask(device, 0x002630, engm, engm); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 451 | |
| 452 | for (todo = mask; engn = __ffs64(todo), todo; todo &= ~(1 << engn)) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 453 | if ((engine = (void *)nvkm_engine(fifo, engn))) { |
Ben Skeggs | cbea21e | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 454 | nvkm_object_fini(engine, false); |
| 455 | WARN_ON(nvkm_object_init(engine)); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 456 | } |
| 457 | } |
| 458 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 459 | gf100_fifo_runlist_update(fifo); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 460 | nvkm_wr32(device, 0x00262c, engm); |
| 461 | nvkm_mask(device, 0x002630, engm, 0x00000000); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 462 | } |
| 463 | |
| 464 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 465 | gf100_fifo_recover(struct gf100_fifo *fifo, struct nvkm_engine *engine, |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 466 | struct gf100_fifo_chan *chan) |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 467 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 468 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 469 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 470 | u32 chid = chan->base.chid; |
| 471 | unsigned long flags; |
| 472 | |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 473 | nvkm_error(subdev, "%s engine fault on channel %d, recovering...\n", |
Ben Skeggs | f029021 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 474 | nvkm_subdev_name[engine->subdev.index], chid); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 475 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 476 | nvkm_mask(device, 0x003004 + (chid * 0x08), 0x00000001, 0x00000000); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 477 | chan->state = KILLED; |
| 478 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 479 | spin_lock_irqsave(&fifo->base.lock, flags); |
| 480 | fifo->mask |= 1ULL << nv_engidx(engine); |
| 481 | spin_unlock_irqrestore(&fifo->base.lock, flags); |
| 482 | schedule_work(&fifo->fault); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 483 | } |
| 484 | |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 485 | static int |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 486 | gf100_fifo_swmthd(struct gf100_fifo *fifo, u32 chid, u32 mthd, u32 data) |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 487 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 488 | struct gf100_fifo_chan *chan = NULL; |
| 489 | struct nvkm_handle *bind; |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 490 | unsigned long flags; |
| 491 | int ret = -EINVAL; |
| 492 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 493 | spin_lock_irqsave(&fifo->base.lock, flags); |
| 494 | if (likely(chid >= fifo->base.min && chid <= fifo->base.max)) |
| 495 | chan = (void *)fifo->base.channel[chid]; |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 496 | if (unlikely(!chan)) |
| 497 | goto out; |
| 498 | |
Ben Skeggs | f58ddf9 | 2015-08-20 14:54:16 +1000 | [diff] [blame] | 499 | bind = nvkm_namedb_get_class(nv_namedb(chan), NVIF_IOCTL_NEW_V0_SW_GF100); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 500 | if (likely(bind)) { |
| 501 | if (!mthd || !nv_call(bind->object, mthd, data)) |
| 502 | ret = 0; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 503 | nvkm_namedb_put(bind); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 504 | } |
| 505 | |
| 506 | out: |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 507 | spin_unlock_irqrestore(&fifo->base.lock, flags); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 508 | return ret; |
| 509 | } |
| 510 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 511 | static const struct nvkm_enum |
| 512 | gf100_fifo_sched_reason[] = { |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 513 | { 0x0a, "CTXSW_TIMEOUT" }, |
| 514 | {} |
| 515 | }; |
| 516 | |
| 517 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 518 | gf100_fifo_intr_sched_ctxsw(struct gf100_fifo *fifo) |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 519 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 520 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 521 | struct nvkm_engine *engine; |
| 522 | struct gf100_fifo_chan *chan; |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 523 | u32 engn; |
| 524 | |
| 525 | for (engn = 0; engn < 6; engn++) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 526 | u32 stat = nvkm_rd32(device, 0x002640 + (engn * 0x04)); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 527 | u32 busy = (stat & 0x80000000); |
| 528 | u32 save = (stat & 0x00100000); /* maybe? */ |
| 529 | u32 unk0 = (stat & 0x00040000); |
| 530 | u32 unk1 = (stat & 0x00001000); |
| 531 | u32 chid = (stat & 0x0000007f); |
| 532 | (void)save; |
| 533 | |
| 534 | if (busy && unk0 && unk1) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 535 | if (!(chan = (void *)fifo->base.channel[chid])) |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 536 | continue; |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 537 | if (!(engine = gf100_fifo_engine(fifo, engn))) |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 538 | continue; |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 539 | gf100_fifo_recover(fifo, engine, chan); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 540 | } |
| 541 | } |
| 542 | } |
| 543 | |
| 544 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 545 | gf100_fifo_intr_sched(struct gf100_fifo *fifo) |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 546 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 547 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 548 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 549 | u32 intr = nvkm_rd32(device, 0x00254c); |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 550 | u32 code = intr & 0x000000ff; |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 551 | const struct nvkm_enum *en; |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 552 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 553 | en = nvkm_enum_find(gf100_fifo_sched_reason, code); |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 554 | |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 555 | nvkm_error(subdev, "SCHED_ERROR %02x [%s]\n", code, en ? en->name : ""); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 556 | |
| 557 | switch (code) { |
| 558 | case 0x0a: |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 559 | gf100_fifo_intr_sched_ctxsw(fifo); |
Ben Skeggs | 61fdf62 | 2014-02-22 12:44:23 +1000 | [diff] [blame] | 560 | break; |
| 561 | default: |
| 562 | break; |
| 563 | } |
Ben Skeggs | 4047653 | 2014-02-22 01:18:46 +1000 | [diff] [blame] | 564 | } |
| 565 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 566 | static const struct nvkm_enum |
| 567 | gf100_fifo_fault_engine[] = { |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 568 | { 0x00, "PGRAPH", NULL, NVDEV_ENGINE_GR }, |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 569 | { 0x03, "PEEPHOLE", NULL, NVDEV_ENGINE_IFB }, |
| 570 | { 0x04, "BAR1", NULL, NVDEV_SUBDEV_BAR }, |
| 571 | { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM }, |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 572 | { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO }, |
Ben Skeggs | eccf7e8a | 2015-01-14 10:09:24 +1000 | [diff] [blame] | 573 | { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD }, |
Ben Skeggs | fd8666f | 2015-01-14 12:26:28 +1000 | [diff] [blame] | 574 | { 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 575 | { 0x13, "PCOUNTER" }, |
Ben Skeggs | 37a5d02 | 2015-01-14 12:50:04 +1000 | [diff] [blame] | 576 | { 0x14, "PMSPDEC", NULL, NVDEV_ENGINE_MSPDEC }, |
Ben Skeggs | aedf24f | 2015-01-14 11:50:20 +1000 | [diff] [blame] | 577 | { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 }, |
| 578 | { 0x16, "PCE1", NULL, NVDEV_ENGINE_CE1 }, |
Ben Skeggs | 7a31347 | 2011-03-29 00:52:59 +1000 | [diff] [blame] | 579 | { 0x17, "PDAEMON" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 580 | {} |
| 581 | }; |
| 582 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 583 | static const struct nvkm_enum |
| 584 | gf100_fifo_fault_reason[] = { |
Ben Skeggs | e296663 | 2011-03-29 08:57:34 +1000 | [diff] [blame] | 585 | { 0x00, "PT_NOT_PRESENT" }, |
| 586 | { 0x01, "PT_TOO_SHORT" }, |
| 587 | { 0x02, "PAGE_NOT_PRESENT" }, |
| 588 | { 0x03, "VM_LIMIT_EXCEEDED" }, |
| 589 | { 0x04, "NO_CHANNEL" }, |
| 590 | { 0x05, "PAGE_SYSTEM_ONLY" }, |
| 591 | { 0x06, "PAGE_READ_ONLY" }, |
| 592 | { 0x0a, "COMPRESSED_SYSRAM" }, |
| 593 | { 0x0c, "INVALID_STORAGE_TYPE" }, |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 594 | {} |
| 595 | }; |
| 596 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 597 | static const struct nvkm_enum |
| 598 | gf100_fifo_fault_hubclient[] = { |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 599 | { 0x01, "PCOPY0" }, |
| 600 | { 0x02, "PCOPY1" }, |
| 601 | { 0x04, "DISPATCH" }, |
| 602 | { 0x05, "CTXCTL" }, |
| 603 | { 0x06, "PFIFO" }, |
| 604 | { 0x07, "BAR_READ" }, |
| 605 | { 0x08, "BAR_WRITE" }, |
| 606 | { 0x0b, "PVP" }, |
Ben Skeggs | fd8666f | 2015-01-14 12:26:28 +1000 | [diff] [blame] | 607 | { 0x0c, "PMSPPP" }, |
Ben Skeggs | eccf7e8a | 2015-01-14 10:09:24 +1000 | [diff] [blame] | 608 | { 0x0d, "PMSVLD" }, |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 609 | { 0x11, "PCOUNTER" }, |
| 610 | { 0x12, "PDAEMON" }, |
| 611 | { 0x14, "CCACHE" }, |
| 612 | { 0x15, "CCACHE_POST" }, |
| 613 | {} |
| 614 | }; |
| 615 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 616 | static const struct nvkm_enum |
| 617 | gf100_fifo_fault_gpcclient[] = { |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 618 | { 0x01, "TEX" }, |
| 619 | { 0x0c, "ESETUP" }, |
| 620 | { 0x0e, "CTXCTL" }, |
| 621 | { 0x0f, "PROP" }, |
| 622 | {} |
| 623 | }; |
| 624 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 625 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 626 | gf100_fifo_intr_fault(struct gf100_fifo *fifo, int unit) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 627 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 628 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 629 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 630 | u32 inst = nvkm_rd32(device, 0x002800 + (unit * 0x10)); |
| 631 | u32 valo = nvkm_rd32(device, 0x002804 + (unit * 0x10)); |
| 632 | u32 vahi = nvkm_rd32(device, 0x002808 + (unit * 0x10)); |
| 633 | u32 stat = nvkm_rd32(device, 0x00280c + (unit * 0x10)); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 634 | u32 gpc = (stat & 0x1f000000) >> 24; |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 635 | u32 client = (stat & 0x00001f00) >> 8; |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 636 | u32 write = (stat & 0x00000080); |
| 637 | u32 hub = (stat & 0x00000040); |
| 638 | u32 reason = (stat & 0x0000000f); |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 639 | struct nvkm_object *engctx = NULL, *object; |
| 640 | struct nvkm_engine *engine = NULL; |
| 641 | const struct nvkm_enum *er, *eu, *ec; |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 642 | char gpcid[8] = ""; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 643 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 644 | er = nvkm_enum_find(gf100_fifo_fault_reason, reason); |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 645 | eu = nvkm_enum_find(gf100_fifo_fault_engine, unit); |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 646 | if (hub) { |
| 647 | ec = nvkm_enum_find(gf100_fifo_fault_hubclient, client); |
| 648 | } else { |
| 649 | ec = nvkm_enum_find(gf100_fifo_fault_gpcclient, client); |
| 650 | snprintf(gpcid, sizeof(gpcid), "GPC%d/", gpc); |
| 651 | } |
| 652 | |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 653 | if (eu) { |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 654 | switch (eu->data2) { |
| 655 | case NVDEV_SUBDEV_BAR: |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 656 | nvkm_mask(device, 0x001704, 0x00000000, 0x00000000); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 657 | break; |
| 658 | case NVDEV_SUBDEV_INSTMEM: |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 659 | nvkm_mask(device, 0x001714, 0x00000000, 0x00000000); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 660 | break; |
| 661 | case NVDEV_ENGINE_IFB: |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 662 | nvkm_mask(device, 0x001718, 0x00000000, 0x00000000); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 663 | break; |
| 664 | default: |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 665 | engine = nvkm_engine(fifo, eu->data2); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 666 | if (engine) |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 667 | engctx = nvkm_engctx_get(engine, inst); |
Ben Skeggs | 33f8c6d | 2014-02-22 01:29:26 +1000 | [diff] [blame] | 668 | break; |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 669 | } |
Ben Skeggs | 7795bee | 2011-03-29 09:28:24 +1000 | [diff] [blame] | 670 | } |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 671 | |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 672 | nvkm_error(subdev, |
| 673 | "%s fault at %010llx engine %02x [%s] client %02x [%s%s] " |
| 674 | "reason %02x [%s] on channel %d [%010llx %s]\n", |
| 675 | write ? "write" : "read", (u64)vahi << 32 | valo, |
| 676 | unit, eu ? eu->name : "", client, gpcid, ec ? ec->name : "", |
| 677 | reason, er ? er->name : "", -1, (u64)inst << 12, |
| 678 | nvkm_client_name(engctx)); |
Marcin Slusarz | 93260d3 | 2012-12-09 23:00:34 +0100 | [diff] [blame] | 679 | |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 680 | object = engctx; |
| 681 | while (object) { |
| 682 | switch (nv_mclass(object)) { |
Ben Skeggs | bbf8906 | 2014-08-10 04:10:25 +1000 | [diff] [blame] | 683 | case FERMI_CHANNEL_GPFIFO: |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 684 | gf100_fifo_recover(fifo, engine, (void *)object); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 685 | break; |
| 686 | } |
| 687 | object = object->parent; |
| 688 | } |
| 689 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 690 | nvkm_engctx_put(engctx); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 691 | } |
| 692 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 693 | static const struct nvkm_bitfield |
| 694 | gf100_fifo_pbdma_intr[] = { |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 695 | /* { 0x00008000, "" } seen with null ib push */ |
| 696 | { 0x00200000, "ILLEGAL_MTHD" }, |
| 697 | { 0x00800000, "EMPTY_SUBC" }, |
| 698 | {} |
| 699 | }; |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 700 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 701 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 702 | gf100_fifo_intr_pbdma(struct gf100_fifo *fifo, int unit) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 703 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 704 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 705 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 706 | u32 stat = nvkm_rd32(device, 0x040108 + (unit * 0x2000)); |
| 707 | u32 addr = nvkm_rd32(device, 0x0400c0 + (unit * 0x2000)); |
| 708 | u32 data = nvkm_rd32(device, 0x0400c4 + (unit * 0x2000)); |
| 709 | u32 chid = nvkm_rd32(device, 0x040120 + (unit * 0x2000)) & 0x7f; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 710 | u32 subc = (addr & 0x00070000) >> 16; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 711 | u32 mthd = (addr & 0x00003ffc); |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 712 | u32 show= stat; |
| 713 | char msg[128]; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 714 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 715 | if (stat & 0x00800000) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 716 | if (!gf100_fifo_swmthd(fifo, chid, mthd, data)) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 717 | show &= ~0x00800000; |
Ben Skeggs | d5316e2 | 2012-03-21 13:53:49 +1000 | [diff] [blame] | 718 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 719 | |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 720 | if (show) { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 721 | nvkm_snprintbf(msg, sizeof(msg), gf100_fifo_pbdma_intr, show); |
| 722 | nvkm_error(subdev, "PBDMA%d: %08x [%s] ch %d [%s] subc %d " |
| 723 | "mthd %04x data %08x\n", |
| 724 | unit, show, msg, chid, |
| 725 | nvkm_client_name_for_fifo_chid(&fifo->base, chid), |
| 726 | subc, mthd, data); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 727 | } |
| 728 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 729 | nvkm_wr32(device, 0x0400c0 + (unit * 0x2000), 0x80600008); |
| 730 | nvkm_wr32(device, 0x040108 + (unit * 0x2000), stat); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 731 | } |
| 732 | |
| 733 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 734 | gf100_fifo_intr_runlist(struct gf100_fifo *fifo) |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 735 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 736 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 737 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 738 | u32 intr = nvkm_rd32(device, 0x002a00); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 739 | |
| 740 | if (intr & 0x10000000) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 741 | wake_up(&fifo->runlist.wait); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 742 | nvkm_wr32(device, 0x002a00, 0x10000000); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 743 | intr &= ~0x10000000; |
| 744 | } |
| 745 | |
| 746 | if (intr) { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 747 | nvkm_error(subdev, "RUNLIST %08x\n", intr); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 748 | nvkm_wr32(device, 0x002a00, intr); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 749 | } |
| 750 | } |
| 751 | |
| 752 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 753 | gf100_fifo_intr_engine_unit(struct gf100_fifo *fifo, int engn) |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 754 | { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 755 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 756 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 757 | u32 intr = nvkm_rd32(device, 0x0025a8 + (engn * 0x04)); |
| 758 | u32 inte = nvkm_rd32(device, 0x002628); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 759 | u32 unkn; |
| 760 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 761 | nvkm_wr32(device, 0x0025a8 + (engn * 0x04), intr); |
Ben Skeggs | 19a1082 | 2014-12-01 11:44:27 +1000 | [diff] [blame] | 762 | |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 763 | for (unkn = 0; unkn < 8; unkn++) { |
| 764 | u32 ints = (intr >> (unkn * 0x04)) & inte; |
| 765 | if (ints & 0x1) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 766 | nvkm_fifo_uevent(&fifo->base); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 767 | ints &= ~1; |
| 768 | } |
| 769 | if (ints) { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 770 | nvkm_error(subdev, "ENGINE %d %d %01x", |
| 771 | engn, unkn, ints); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 772 | nvkm_mask(device, 0x002628, ints, 0); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 773 | } |
| 774 | } |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 775 | } |
| 776 | |
| 777 | static void |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 778 | gf100_fifo_intr_engine(struct gf100_fifo *fifo) |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 779 | { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 780 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 781 | u32 mask = nvkm_rd32(device, 0x0025a4); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 782 | while (mask) { |
| 783 | u32 unit = __ffs(mask); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 784 | gf100_fifo_intr_engine_unit(fifo, unit); |
Ben Skeggs | e99bf01 | 2014-02-22 00:18:17 +1000 | [diff] [blame] | 785 | mask &= ~(1 << unit); |
| 786 | } |
| 787 | } |
| 788 | |
| 789 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 790 | gf100_fifo_intr(struct nvkm_subdev *subdev) |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 791 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 792 | struct gf100_fifo *fifo = (void *)subdev; |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 793 | struct nvkm_device *device = fifo->base.engine.subdev.device; |
| 794 | u32 mask = nvkm_rd32(device, 0x002140); |
| 795 | u32 stat = nvkm_rd32(device, 0x002100) & mask; |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 796 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 797 | if (stat & 0x00000001) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 798 | u32 intr = nvkm_rd32(device, 0x00252c); |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 799 | nvkm_warn(subdev, "INTR 00000001: %08x\n", intr); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 800 | nvkm_wr32(device, 0x002100, 0x00000001); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 801 | stat &= ~0x00000001; |
| 802 | } |
| 803 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 804 | if (stat & 0x00000100) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 805 | gf100_fifo_intr_sched(fifo); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 806 | nvkm_wr32(device, 0x002100, 0x00000100); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 807 | stat &= ~0x00000100; |
| 808 | } |
| 809 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 810 | if (stat & 0x00010000) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 811 | u32 intr = nvkm_rd32(device, 0x00256c); |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 812 | nvkm_warn(subdev, "INTR 00010000: %08x\n", intr); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 813 | nvkm_wr32(device, 0x002100, 0x00010000); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 814 | stat &= ~0x00010000; |
| 815 | } |
| 816 | |
| 817 | if (stat & 0x01000000) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 818 | u32 intr = nvkm_rd32(device, 0x00258c); |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 819 | nvkm_warn(subdev, "INTR 01000000: %08x\n", intr); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 820 | nvkm_wr32(device, 0x002100, 0x01000000); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 821 | stat &= ~0x01000000; |
| 822 | } |
| 823 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 824 | if (stat & 0x10000000) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 825 | u32 mask = nvkm_rd32(device, 0x00259c); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 826 | while (mask) { |
| 827 | u32 unit = __ffs(mask); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 828 | gf100_fifo_intr_fault(fifo, unit); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 829 | nvkm_wr32(device, 0x00259c, (1 << unit)); |
Ben Skeggs | d439a5a | 2014-02-22 00:39:36 +1000 | [diff] [blame] | 830 | mask &= ~(1 << unit); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 831 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 832 | stat &= ~0x10000000; |
| 833 | } |
| 834 | |
| 835 | if (stat & 0x20000000) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 836 | u32 mask = nvkm_rd32(device, 0x0025a0); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 837 | while (mask) { |
| 838 | u32 unit = __ffs(mask); |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 839 | gf100_fifo_intr_pbdma(fifo, unit); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 840 | nvkm_wr32(device, 0x0025a0, (1 << unit)); |
Ben Skeggs | 083c214 | 2014-02-22 00:31:29 +1000 | [diff] [blame] | 841 | mask &= ~(1 << unit); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 842 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 843 | stat &= ~0x20000000; |
| 844 | } |
| 845 | |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 846 | if (stat & 0x40000000) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 847 | gf100_fifo_intr_runlist(fifo); |
Ben Skeggs | cc8cd64 | 2011-01-28 13:42:16 +1000 | [diff] [blame] | 848 | stat &= ~0x40000000; |
| 849 | } |
| 850 | |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 851 | if (stat & 0x80000000) { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 852 | gf100_fifo_intr_engine(fifo); |
Ben Skeggs | 32256c8 | 2013-01-31 19:49:33 -0500 | [diff] [blame] | 853 | stat &= ~0x80000000; |
| 854 | } |
| 855 | |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 856 | if (stat) { |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 857 | nvkm_error(subdev, "INTR %08x\n", stat); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 858 | nvkm_mask(device, 0x002140, stat, 0x00000000); |
| 859 | nvkm_wr32(device, 0x002100, stat); |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 860 | } |
Ben Skeggs | b2b0993 | 2010-11-24 10:47:15 +1000 | [diff] [blame] | 861 | } |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 862 | |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 863 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 864 | gf100_fifo_uevent_init(struct nvkm_event *event, int type, int index) |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 865 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 866 | struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 867 | struct nvkm_device *device = fifo->engine.subdev.device; |
| 868 | nvkm_mask(device, 0x002140, 0x80000000, 0x80000000); |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 869 | } |
| 870 | |
| 871 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 872 | gf100_fifo_uevent_fini(struct nvkm_event *event, int type, int index) |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 873 | { |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 874 | struct nvkm_fifo *fifo = container_of(event, typeof(*fifo), uevent); |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 875 | struct nvkm_device *device = fifo->engine.subdev.device; |
| 876 | nvkm_mask(device, 0x002140, 0x80000000, 0x00000000); |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 877 | } |
| 878 | |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 879 | static const struct nvkm_event_func |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 880 | gf100_fifo_uevent_func = { |
| 881 | .ctor = nvkm_fifo_uevent_ctor, |
| 882 | .init = gf100_fifo_uevent_init, |
| 883 | .fini = gf100_fifo_uevent_fini, |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 884 | }; |
| 885 | |
| 886 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 887 | gf100_fifo_ctor(struct nvkm_object *parent, struct nvkm_object *engine, |
| 888 | struct nvkm_oclass *oclass, void *data, u32 size, |
| 889 | struct nvkm_object **pobject) |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 890 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 891 | struct gf100_fifo *fifo; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 892 | int ret; |
| 893 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 894 | ret = nvkm_fifo_create(parent, engine, oclass, 0, 127, &fifo); |
| 895 | *pobject = nv_object(fifo); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 896 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 897 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 898 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 899 | INIT_WORK(&fifo->fault, gf100_fifo_recover_work); |
Ben Skeggs | 24e8341 | 2014-02-05 11:18:38 +1000 | [diff] [blame] | 900 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 901 | ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0, |
| 902 | &fifo->runlist.mem[0]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 903 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 904 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 905 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 906 | ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 0x1000, 0x1000, 0, |
| 907 | &fifo->runlist.mem[1]); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 908 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 909 | return ret; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 910 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 911 | init_waitqueue_head(&fifo->runlist.wait); |
Ben Skeggs | a07d0e7 | 2014-02-22 00:28:47 +1000 | [diff] [blame] | 912 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 913 | ret = nvkm_gpuobj_new(nv_object(fifo), NULL, 128 * 0x1000, 0x1000, 0, |
| 914 | &fifo->user.mem); |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 915 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 916 | return ret; |
Ben Skeggs | 9da226f | 2012-07-13 16:54:45 +1000 | [diff] [blame] | 917 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 918 | ret = nvkm_gpuobj_map(fifo->user.mem, NV_MEM_ACCESS_RW, |
| 919 | &fifo->user.bar); |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 920 | if (ret) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 921 | return ret; |
| 922 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 923 | ret = nvkm_event_init(&gf100_fifo_uevent_func, 1, 1, &fifo->base.uevent); |
Ben Skeggs | 79ca277 | 2014-08-10 04:10:20 +1000 | [diff] [blame] | 924 | if (ret) |
| 925 | return ret; |
Ben Skeggs | 9bd2ddb | 2013-01-31 13:51:20 +1000 | [diff] [blame] | 926 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 927 | nv_subdev(fifo)->unit = 0x00000100; |
| 928 | nv_subdev(fifo)->intr = gf100_fifo_intr; |
| 929 | nv_engine(fifo)->cclass = &gf100_fifo_cclass; |
| 930 | nv_engine(fifo)->sclass = gf100_fifo_sclass; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 931 | return 0; |
Ben Skeggs | c420b2d | 2012-05-01 20:48:08 +1000 | [diff] [blame] | 932 | } |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 933 | |
| 934 | static void |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 935 | gf100_fifo_dtor(struct nvkm_object *object) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 936 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 937 | struct gf100_fifo *fifo = (void *)object; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 938 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 939 | nvkm_gpuobj_unmap(&fifo->user.bar); |
| 940 | nvkm_gpuobj_ref(NULL, &fifo->user.mem); |
| 941 | nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[0]); |
| 942 | nvkm_gpuobj_ref(NULL, &fifo->runlist.mem[1]); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 943 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 944 | nvkm_fifo_destroy(&fifo->base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 945 | } |
| 946 | |
| 947 | static int |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 948 | gf100_fifo_init(struct nvkm_object *object) |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 949 | { |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 950 | struct gf100_fifo *fifo = (void *)object; |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 951 | struct nvkm_subdev *subdev = &fifo->base.engine.subdev; |
| 952 | struct nvkm_device *device = subdev->device; |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 953 | int ret, i; |
| 954 | |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 955 | ret = nvkm_fifo_init(&fifo->base); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 956 | if (ret) |
| 957 | return ret; |
| 958 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 959 | nvkm_wr32(device, 0x000204, 0xffffffff); |
| 960 | nvkm_wr32(device, 0x002204, 0xffffffff); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 961 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 962 | fifo->spoon_nr = hweight32(nvkm_rd32(device, 0x002204)); |
Ben Skeggs | e5c5e4f | 2015-08-20 14:54:13 +1000 | [diff] [blame] | 963 | nvkm_debug(subdev, "%d PBDMA unit(s)\n", fifo->spoon_nr); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 964 | |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 965 | /* assign engines to PBDMAs */ |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 966 | if (fifo->spoon_nr >= 3) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 967 | nvkm_wr32(device, 0x002208, ~(1 << 0)); /* PGRAPH */ |
| 968 | nvkm_wr32(device, 0x00220c, ~(1 << 1)); /* PVP */ |
| 969 | nvkm_wr32(device, 0x002210, ~(1 << 1)); /* PMSPP */ |
| 970 | nvkm_wr32(device, 0x002214, ~(1 << 1)); /* PMSVLD */ |
| 971 | nvkm_wr32(device, 0x002218, ~(1 << 2)); /* PCE0 */ |
| 972 | nvkm_wr32(device, 0x00221c, ~(1 << 1)); /* PCE1 */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 973 | } |
| 974 | |
Ben Skeggs | 0357466 | 2014-01-28 11:47:46 +1000 | [diff] [blame] | 975 | /* PBDMA[n] */ |
Ben Skeggs | 6189f1b | 2015-08-20 14:54:07 +1000 | [diff] [blame] | 976 | for (i = 0; i < fifo->spoon_nr; i++) { |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 977 | nvkm_mask(device, 0x04013c + (i * 0x2000), 0x10000100, 0x00000000); |
| 978 | nvkm_wr32(device, 0x040108 + (i * 0x2000), 0xffffffff); /* INTR */ |
| 979 | nvkm_wr32(device, 0x04010c + (i * 0x2000), 0xfffffeff); /* INTREN */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 980 | } |
| 981 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 982 | nvkm_mask(device, 0x002200, 0x00000001, 0x00000001); |
| 983 | nvkm_wr32(device, 0x002254, 0x10000000 | fifo->user.bar.offset >> 12); |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 984 | |
Ben Skeggs | 8774440 | 2015-08-20 14:54:10 +1000 | [diff] [blame] | 985 | nvkm_wr32(device, 0x002100, 0xffffffff); |
| 986 | nvkm_wr32(device, 0x002140, 0x7fffffff); |
| 987 | nvkm_wr32(device, 0x002628, 0x00000001); /* ENGINE_INTR_EN */ |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 988 | return 0; |
| 989 | } |
| 990 | |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 991 | struct nvkm_oclass * |
| 992 | gf100_fifo_oclass = &(struct nvkm_oclass) { |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 993 | .handle = NV_ENGINE(FIFO, 0xc0), |
Ben Skeggs | 05c7145 | 2015-01-14 15:28:47 +1000 | [diff] [blame] | 994 | .ofuncs = &(struct nvkm_ofuncs) { |
| 995 | .ctor = gf100_fifo_ctor, |
| 996 | .dtor = gf100_fifo_dtor, |
| 997 | .init = gf100_fifo_init, |
| 998 | .fini = _nvkm_fifo_fini, |
Ben Skeggs | ebb945a | 2012-07-20 08:17:34 +1000 | [diff] [blame] | 999 | }, |
| 1000 | }; |